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Diffstat (limited to 'arch/powerpc/boot/dts/mpc8568mds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts489
1 files changed, 214 insertions, 275 deletions
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index a123ec9456b..bead2b655b9 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -1,7 +1,7 @@
/*
* MPC8568E MDS Device Tree Source
*
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2007, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -9,367 +9,306 @@
* option) any later version.
*/
-
-/*
-/memreserve/ 00000000 1000000;
-*/
+/include/ "fsl/mpc8568si-pre.dtsi"
/ {
model = "MPC8568EMDS";
compatible = "MPC8568EMDS", "MPC85xxMDS";
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,8568@0 {
- device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <20>; // 32 bytes
- i-cache-line-size = <20>; // 32 bytes
- d-cache-size = <8000>; // L1, 32K
- i-cache-size = <8000>; // L1, 32K
- timebase-frequency = <0>;
- bus-frequency = <0>;
- clock-frequency = <0>;
- 32-bit;
- };
+
+ aliases {
+ pci0 = &pci0;
+ pci1 = &pci1;
+ rapidio0 = &rio;
};
memory {
device_type = "memory";
- reg = <00000000 10000000>;
+ reg = <0x0 0x0 0x0 0x0>;
};
- bcsr@f8000000 {
- device_type = "board-control";
- reg = <f8000000 8000>;
- };
+ lbc: localbus@e0005000 {
+ reg = <0x0 0xe0005000 0x0 0x1000>;
+ ranges = <0x0 0x0 0xfe000000 0x02000000
+ 0x1 0x0 0xf8000000 0x00008000
+ 0x2 0x0 0xf0000000 0x04000000
+ 0x4 0x0 0xf8008000 0x00008000
+ 0x5 0x0 0xf8010000 0x00008000>;
- soc8568@e0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- #interrupt-cells = <2>;
- device_type = "soc";
- ranges = <0 e0000000 00100000>;
- reg = <e0000000 00100000>;
- bus-frequency = <0>;
-
- memory-controller@2000 {
- compatible = "fsl,8568-memory-controller";
- reg = <2000 1000>;
- interrupt-parent = <&mpic>;
- interrupts = <2 2>;
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x02000000>;
+ bank-width = <2>;
+ device-width = <2>;
};
- l2-cache-controller@20000 {
- compatible = "fsl,8568-l2-cache-controller";
- reg = <20000 1000>;
- cache-line-size = <20>; // 32 bytes
- cache-size = <80000>; // L2, 512K
- interrupt-parent = <&mpic>;
- interrupts = <0 2>;
+ bcsr@1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8568mds-bcsr";
+ reg = <1 0 0x8000>;
+ ranges = <0 1 0 0x8000>;
+
+ bcsr5: gpio-controller@11 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8568mds-bcsr-gpio";
+ reg = <0x5 0x1>;
+ gpio-controller;
+ };
};
- i2c@3000 {
- device_type = "i2c";
- compatible = "fsl-i2c";
- reg = <3000 100>;
- interrupts = <1b 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
+ pib@4,0 {
+ compatible = "fsl,mpc8568mds-pib";
+ reg = <4 0 0x8000>;
};
- i2c@3100 {
- device_type = "i2c";
- compatible = "fsl-i2c";
- reg = <3100 100>;
- interrupts = <1b 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
+ pib@5,0 {
+ compatible = "fsl,mpc8568mds-pib";
+ reg = <5 0 0x8000>;
+ };
+ };
+
+ soc: soc8568@e0000000 {
+ ranges = <0x0 0x0 0xe0000000 0x100000>;
+
+ i2c-sleep-nexus {
+ i2c@3000 {
+ rtc@68 {
+ compatible = "dallas,ds1374";
+ reg = <0x68>;
+ interrupts = <3 1 0 0>;
+ };
+ };
+ };
+
+ enet0: ethernet@24000 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy2>;
};
mdio@24520 {
- #address-cells = <1>;
- #size-cells = <0>;
- device_type = "mdio";
- compatible = "gianfar";
- reg = <24520 20>;
- phy0: ethernet-phy@0 {
- interrupt-parent = <&mpic>;
- interrupts = <31 1>;
- reg = <0>;
- device_type = "ethernet-phy";
+ phy0: ethernet-phy@7 {
+ interrupts = <1 1 0 0>;
+ reg = <0x7>;
};
phy1: ethernet-phy@1 {
- interrupt-parent = <&mpic>;
- interrupts = <32 1>;
- reg = <1>;
- device_type = "ethernet-phy";
+ interrupts = <2 1 0 0>;
+ reg = <0x1>;
};
phy2: ethernet-phy@2 {
- interrupt-parent = <&mpic>;
- interrupts = <31 1>;
- reg = <2>;
- device_type = "ethernet-phy";
+ interrupts = <1 1 0 0>;
+ reg = <0x2>;
};
phy3: ethernet-phy@3 {
- interrupt-parent = <&mpic>;
- interrupts = <32 1>;
- reg = <3>;
- device_type = "ethernet-phy";
+ interrupts = <2 1 0 0>;
+ reg = <0x3>;
+ };
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
};
};
- ethernet@24000 {
- #address-cells = <1>;
- #size-cells = <0>;
- device_type = "network";
- model = "eTSEC";
- compatible = "gianfar";
- reg = <24000 1000>;
- mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <d 2 e 2 12 2>;
- interrupt-parent = <&mpic>;
- phy-handle = <&phy2>;
- };
-
- ethernet@25000 {
- #address-cells = <1>;
- #size-cells = <0>;
- device_type = "network";
- model = "eTSEC";
- compatible = "gianfar";
- reg = <25000 1000>;
- mac-address = [ 00 00 00 00 00 00];
- interrupts = <13 2 14 2 18 2>;
- interrupt-parent = <&mpic>;
+ enet1: ethernet@25000 {
+ tbi-handle = <&tbi1>;
phy-handle = <&phy3>;
+ sleep = <&pmc 0x00000040>;
};
- serial@4500 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <4500 100>;
- clock-frequency = <0>;
- interrupts = <1a 2>;
- interrupt-parent = <&mpic>;
- };
-
- serial@4600 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <4600 100>;
- clock-frequency = <0>;
- interrupts = <1a 2>;
- interrupt-parent = <&mpic>;
- };
-
- crypto@30000 {
- device_type = "crypto";
- model = "SEC2";
- compatible = "talitos";
- reg = <30000 f000>;
- interrupts = <1d 2>;
- interrupt-parent = <&mpic>;
- num-channels = <4>;
- channel-fifo-len = <18>;
- exec-units-mask = <000000fe>;
- descriptor-types-mask = <012b0ebf>;
+ mdio@25520 {
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
};
- mpic: pic@40000 {
- clock-frequency = <0>;
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <40000 40000>;
- built-in;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- big-endian;
- };
par_io@e0100 {
- reg = <e0100 100>;
- device_type = "par_io";
num-ports = <7>;
pio1: ucc_pin@01 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
- 4 0a 1 0 2 0 /* TxD0 */
- 4 09 1 0 2 0 /* TxD1 */
- 4 08 1 0 2 0 /* TxD2 */
- 4 07 1 0 2 0 /* TxD3 */
- 4 17 1 0 2 0 /* TxD4 */
- 4 16 1 0 2 0 /* TxD5 */
- 4 15 1 0 2 0 /* TxD6 */
- 4 14 1 0 2 0 /* TxD7 */
- 4 0f 2 0 2 0 /* RxD0 */
- 4 0e 2 0 2 0 /* RxD1 */
- 4 0d 2 0 2 0 /* RxD2 */
- 4 0c 2 0 2 0 /* RxD3 */
- 4 1d 2 0 2 0 /* RxD4 */
- 4 1c 2 0 2 0 /* RxD5 */
- 4 1b 2 0 2 0 /* RxD6 */
- 4 1a 2 0 2 0 /* RxD7 */
- 4 0b 1 0 2 0 /* TX_EN */
- 4 18 1 0 2 0 /* TX_ER */
- 4 0f 2 0 2 0 /* RX_DV */
- 4 1e 2 0 2 0 /* RX_ER */
- 4 11 2 0 2 0 /* RX_CLK */
- 4 13 1 0 2 0 /* GTX_CLK */
- 1 1f 2 0 3 0>; /* GTX125 */
+ 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
+ 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
+ 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
+ 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
+ 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
+ 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
+ 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
+ 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
+ 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
+ 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
+ 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
+ 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
+ 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
+ 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
+ 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
+ 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
+ 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
+ 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
+ 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
+ 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
+ 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
+ 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
+ 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
};
+
pio2: ucc_pin@02 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
- 5 0a 1 0 2 0 /* TxD0 */
- 5 09 1 0 2 0 /* TxD1 */
- 5 08 1 0 2 0 /* TxD2 */
- 5 07 1 0 2 0 /* TxD3 */
- 5 17 1 0 2 0 /* TxD4 */
- 5 16 1 0 2 0 /* TxD5 */
- 5 15 1 0 2 0 /* TxD6 */
- 5 14 1 0 2 0 /* TxD7 */
- 5 0f 2 0 2 0 /* RxD0 */
- 5 0e 2 0 2 0 /* RxD1 */
- 5 0d 2 0 2 0 /* RxD2 */
- 5 0c 2 0 2 0 /* RxD3 */
- 5 1d 2 0 2 0 /* RxD4 */
- 5 1c 2 0 2 0 /* RxD5 */
- 5 1b 2 0 2 0 /* RxD6 */
- 5 1a 2 0 2 0 /* RxD7 */
- 5 0b 1 0 2 0 /* TX_EN */
- 5 18 1 0 2 0 /* TX_ER */
- 5 10 2 0 2 0 /* RX_DV */
- 5 1e 2 0 2 0 /* RX_ER */
- 5 11 2 0 2 0 /* RX_CLK */
- 5 13 1 0 2 0 /* GTX_CLK */
- 1 1f 2 0 3 0 /* GTX125 */
- 4 06 3 0 2 0 /* MDIO */
- 4 05 1 0 2 0>; /* MDC */
+ 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
+ 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
+ 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
+ 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
+ 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
+ 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
+ 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
+ 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
+ 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
+ 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
+ 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
+ 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
+ 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
+ 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
+ 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
+ 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
+ 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
+ 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
+ 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
+ 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
+ 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
+ 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
+ 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
+ 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
+ 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
};
};
};
- qe@e0080000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "qe";
- model = "QE";
- ranges = <0 e0080000 00040000>;
- reg = <e0080000 480>;
- brg-frequency = <0>;
- bus-frequency = <179A7B00>;
-
- muram@10000 {
- device_type = "muram";
- ranges = <0 00010000 0000c000>;
-
- data-only@0{
- reg = <0 c000>;
- };
- };
+ qe: qe@e0080000 {
+ ranges = <0x0 0x0 0xe0080000 0x40000>;
+ reg = <0x0 0xe0080000 0x0 0x480>;
spi@4c0 {
- device_type = "spi";
- compatible = "fsl_spi";
- reg = <4c0 40>;
- interrupts = <2>;
- interrupt-parent = <&qeic>;
mode = "cpu";
};
spi@500 {
- device_type = "spi";
- compatible = "fsl_spi";
- reg = <500 40>;
- interrupts = <1>;
- interrupt-parent = <&qeic>;
mode = "cpu";
};
- ucc@2000 {
+ enet2: ucc@2000 {
device_type = "network";
compatible = "ucc_geth";
- model = "UCC";
- device-id = <1>;
- reg = <2000 200>;
- interrupts = <20>;
- interrupt-parent = <&qeic>;
- mac-address = [ 00 04 9f 00 23 23 ];
- rx-clock = <0>;
- tx-clock = <19>;
- phy-handle = <&qe_phy0>;
- phy-connection-type = "gmii";
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk16";
pio-handle = <&pio1>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "rgmii-id";
};
- ucc@3000 {
+ enet3: ucc@3000 {
device_type = "network";
compatible = "ucc_geth";
- model = "UCC";
- device-id = <2>;
- reg = <3000 200>;
- interrupts = <21>;
- interrupt-parent = <&qeic>;
- mac-address = [ 00 11 22 33 44 55 ];
- rx-clock = <0>;
- tx-clock = <14>;
- phy-handle = <&qe_phy1>;
- phy-connection-type = "gmii";
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk16";
pio-handle = <&pio2>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
};
mdio@2120 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <2120 18>;
- device_type = "mdio";
- compatible = "ucc_geth_phy";
+ reg = <0x2120 0x18>;
+ compatible = "fsl,ucc-mdio";
/* These are the same PHYs as on
* gianfar's MDIO bus */
- qe_phy0: ethernet-phy@00 {
+ qe_phy0: ethernet-phy@07 {
interrupt-parent = <&mpic>;
- interrupts = <31 1>;
- reg = <0>;
- device_type = "ethernet-phy";
+ interrupts = <1 1 0 0>;
+ reg = <0x7>;
};
qe_phy1: ethernet-phy@01 {
interrupt-parent = <&mpic>;
- interrupts = <32 1>;
- reg = <1>;
- device_type = "ethernet-phy";
+ interrupts = <2 1 0 0>;
+ reg = <0x1>;
};
qe_phy2: ethernet-phy@02 {
interrupt-parent = <&mpic>;
- interrupts = <31 1>;
- reg = <2>;
- device_type = "ethernet-phy";
+ interrupts = <1 1 0 0>;
+ reg = <0x2>;
};
qe_phy3: ethernet-phy@03 {
interrupt-parent = <&mpic>;
- interrupts = <32 1>;
- reg = <3>;
- device_type = "ethernet-phy";
+ interrupts = <2 1 0 0>;
+ reg = <0x3>;
};
};
+ };
+
+ pci0: pci@e0008000 {
+ reg = <0x0 0xe0008000 0x0 0x1000>;
+ ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0x0 0xe2000000 0x0 0x800000>;
+ clock-frequency = <66666666>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x12 AD18 */
+ 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 0 0
+ 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 0 0
+ 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 0 0
+ 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 0 0
- qeic: qeic@80 {
- interrupt-controller;
- device_type = "qeic";
- #address-cells = <0>;
- #interrupt-cells = <1>;
- reg = <80 80>;
- built-in;
- big-endian;
- interrupts = <1e 2 1e 2>; //high:30 low:30
- interrupt-parent = <&mpic>;
+ /* IDSEL 0x13 AD19 */
+ 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 0 0
+ 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 0 0
+ 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
+ 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1 0 0>;
+ };
+
+ /* PCI Express */
+ pci1: pcie@e000a000 {
+ ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0x0 0xe2800000 0x0 0x800000>;
+ reg = <0x0 0xe000a000 0x0 0x1000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x10000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x800000>;
+ };
+ };
+
+ rio: rapidio@e00c00000 {
+ reg = <0x0 0xe00c0000 0x0 0x20000>;
+ port1 {
+ ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ green {
+ gpios = <&bcsr5 1 0>;
};
+ amber {
+ gpios = <&bcsr5 2 0>;
+ };
+
+ red {
+ gpios = <&bcsr5 3 0>;
+ };
};
};
+
+/include/ "fsl/mpc8568si-post.dtsi"
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2026-01-05 20:15:53 +0000