diff options
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8544ds.dts')
| -rw-r--r-- | arch/powerpc/boot/dts/mpc8544ds.dts | 197 |
1 files changed, 76 insertions, 121 deletions
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts index 3033599e74e..ed38874c3a3 100644 --- a/arch/powerpc/boot/dts/mpc8544ds.dts +++ b/arch/powerpc/boot/dts/mpc8544ds.dts @@ -1,7 +1,7 @@ /* * MPC8544 DS Device Tree Source * - * Copyright 2007 Freescale Semiconductor Inc. + * Copyright 2007, 2008 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -9,144 +9,99 @@ * option) any later version. */ +/include/ "fsl/mpc8544si-pre.dtsi" + / { model = "MPC8544DS"; compatible = "MPC8544DS", "MPC85xxDS"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #cpus = <1>; - #address-cells = <1>; - #size-cells = <0>; - - PowerPC,8544@0 { - device_type = "cpu"; - reg = <0>; - d-cache-line-size = <20>; // 32 bytes - i-cache-line-size = <20>; // 32 bytes - d-cache-size = <8000>; // L1, 32K - i-cache-size = <8000>; // L1, 32K - timebase-frequency = <0>; - bus-frequency = <0>; - clock-frequency = <0>; - 32-bit; - }; - }; memory { device_type = "memory"; - reg = <00000000 00000000>; // Filled by U-Boot + reg = <0 0 0 0>; // Filled by U-Boot }; - soc8544@e0000000 { - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <2>; - device_type = "soc"; - ranges = <0 e0000000 00100000>; - reg = <e0000000 00100000>; // CCSRBAR 1M - bus-frequency = <0>; // Filled out by uboot. - - memory-controller@2000 { - compatible = "fsl,8544-memory-controller"; - reg = <2000 1000>; - interrupt-parent = <&mpic>; - interrupts = <2 2>; - }; + board_lbc: lbc: localbus@e0005000 { + reg = <0 0xe0005000 0 0x1000>; - l2-cache-controller@20000 { - compatible = "fsl,8544-l2-cache-controller"; - reg = <20000 1000>; - cache-line-size = <20>; // 32 bytes - cache-size = <40000>; // L2, 256K - interrupt-parent = <&mpic>; - interrupts = <0 2>; - }; + ranges = <0x0 0x0 0x0 0xff800000 0x800000>; + }; - i2c@3000 { - device_type = "i2c"; - compatible = "fsl-i2c"; - reg = <3000 100>; - interrupts = <1b 2>; - interrupt-parent = <&mpic>; - dfsrr; - }; + board_soc: soc: soc8544@e0000000 { + ranges = <0x0 0x0 0xe0000000 0x100000>; + }; - mdio@24520 { - #address-cells = <1>; - #size-cells = <0>; - device_type = "mdio"; - compatible = "gianfar"; - reg = <24520 20>; - phy0: ethernet-phy@0 { - interrupt-parent = <&mpic>; - interrupts = <3a 1>; - reg = <0>; - device_type = "ethernet-phy"; - }; - phy1: ethernet-phy@1 { - interrupt-parent = <&mpic>; - interrupts = <3a 1>; - reg = <1>; - device_type = "ethernet-phy"; - }; - }; + pci0: pci@e0008000 { + reg = <0 0xe0008000 0 0x1000>; + ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>; + clock-frequency = <66666666>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < - ethernet@24000 { - #address-cells = <1>; - #size-cells = <0>; - device_type = "network"; - model = "TSEC"; - compatible = "gianfar"; - reg = <24000 1000>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <d 2 e 2 12 2>; - interrupt-parent = <&mpic>; - phy-handle = <&phy0>; - }; + /* IDSEL 0x11 J17 Slot 1 */ + 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 + 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 + 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0 + 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 - ethernet@26000 { - #address-cells = <1>; - #size-cells = <0>; - device_type = "network"; - model = "TSEC"; - compatible = "gianfar"; - reg = <26000 1000>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <f 2 10 2 11 2>; - interrupt-parent = <&mpic>; - phy-handle = <&phy1>; - }; + /* IDSEL 0x12 J16 Slot 2 */ - serial@4500 { - device_type = "serial"; - compatible = "ns16550"; - reg = <4500 100>; - clock-frequency = <0>; - interrupts = <1a 2>; - interrupt-parent = <&mpic>; + 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 + 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0 + 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 + 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0>; + }; + + pci1: pcie@e0009000 { + reg = <0x0 0xe0009000 0x0 0x1000>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xe1010000 0x0 0x10000>; + pcie@0 { + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x10000>; }; + }; + + pci2: pcie@e000a000 { + reg = <0x0 0xe000a000 0x0 0x1000>; + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000 + 0x1000000 0x0 0x00000000 0 0xe1020000 0x0 0x10000>; + pcie@0 { + ranges = <0x2000000 0x0 0xa0000000 + 0x2000000 0x0 0xa0000000 + 0x0 0x10000000 - serial@4600 { - device_type = "serial"; - compatible = "ns16550"; - reg = <4600 100>; - clock-frequency = <0>; - interrupts = <1a 2>; - interrupt-parent = <&mpic>; + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x10000>; }; + }; - mpic: pic@40000 { - clock-frequency = <0>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <40000 40000>; - built-in; - compatible = "chrp,open-pic"; - device_type = "open-pic"; - big-endian; + board_pci3: pci3: pcie@e000b000 { + reg = <0x0 0xe000b000 0x0 0x1000>; + ranges = <0x2000000 0x0 0xb0000000 0 0xb0000000 0x0 0x100000 + 0x1000000 0x0 0x00000000 0 0xb0100000 0x0 0x100000>; + pcie@0 { + ranges = <0x2000000 0x0 0xb0000000 + 0x2000000 0x0 0xb0000000 + 0x0 0x100000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; }; }; }; + +/* + * mpc8544ds.dtsi must be last to ensure board_pci3 overrides pci3 settings + * for interrupt-map & interrupt-map-mask + */ + +/include/ "fsl/mpc8544si-post.dtsi" +/include/ "mpc8544ds.dtsi" |