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-rw-r--r--arch/mips/tx4927/common/tx4927_dbgio.c1
-rw-r--r--arch/mips/tx4927/common/tx4927_prom.c12
-rw-r--r--arch/mips/tx4927/common/tx4927_setup.c11
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c21
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c32
5 files changed, 36 insertions, 41 deletions
diff --git a/arch/mips/tx4927/common/tx4927_dbgio.c b/arch/mips/tx4927/common/tx4927_dbgio.c
index 09bdf2baa83..d8423e001b2 100644
--- a/arch/mips/tx4927/common/tx4927_dbgio.c
+++ b/arch/mips/tx4927/common/tx4927_dbgio.c
@@ -31,7 +31,6 @@
#include <asm/mipsregs.h>
#include <asm/system.h>
-#include <asm/tx4927/tx4927_mips.h>
u8 getDebugChar(void)
{
diff --git a/arch/mips/tx4927/common/tx4927_prom.c b/arch/mips/tx4927/common/tx4927_prom.c
index 7d4cbf512d8..6eed53d8f38 100644
--- a/arch/mips/tx4927/common/tx4927_prom.c
+++ b/arch/mips/tx4927/common/tx4927_prom.c
@@ -38,7 +38,7 @@
#include <asm/bootinfo.h>
#include <asm/tx4927/tx4927.h>
-static unsigned int __init tx4927_process_sdccr(u64 * addr)
+static unsigned int __init tx4927_process_sdccr(unsigned long addr)
{
u64 val;
unsigned int sdccr_ce;
@@ -52,7 +52,7 @@ static unsigned int __init tx4927_process_sdccr(u64 * addr)
unsigned int mw = 0;
unsigned int msize = 0;
- val = (*((vu64 *) (addr)));
+ val = __raw_readq((void __iomem *)addr);
/* MVMCP -- need #defs for these bits masks */
sdccr_ce = ((val & (1 << 10)) >> 10);
@@ -136,10 +136,10 @@ unsigned int __init tx4927_get_mem_size(void)
unsigned int total;
/* MVMCP -- need #defs for these registers */
- c0 = tx4927_process_sdccr((u64 *) 0xff1f8000);
- c1 = tx4927_process_sdccr((u64 *) 0xff1f8008);
- c2 = tx4927_process_sdccr((u64 *) 0xff1f8010);
- c3 = tx4927_process_sdccr((u64 *) 0xff1f8018);
+ c0 = tx4927_process_sdccr(0xff1f8000);
+ c1 = tx4927_process_sdccr(0xff1f8008);
+ c2 = tx4927_process_sdccr(0xff1f8010);
+ c3 = tx4927_process_sdccr(0xff1f8018);
total = c0 + c1 + c2 + c3;
return (total);
diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c
index c8e49feb345..b18ed58f88a 100644
--- a/arch/mips/tx4927/common/tx4927_setup.c
+++ b/arch/mips/tx4927/common/tx4927_setup.c
@@ -124,10 +124,10 @@ dump_cp0(char *key)
return;
}
-void print_pic(char *key, u32 reg, char *name)
+void print_pic(char *key, unsigned long reg, char *name)
{
- printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name,
- TX4927_RD(reg));
+ printk(KERN_INFO "%s pic:0x%08lx:%s=0x%08x\n", key, reg, name,
+ __raw_readl((void __iomem *)reg));
return;
}
@@ -166,9 +166,10 @@ void dump_pic(char *key)
}
-void print_addr(char *hdr, char *key, u32 addr)
+void print_addr(char *hdr, char *key, unsigned long addr)
{
- printk("%s %s:0x%08x=0x%08x\n", hdr, key, addr, TX4927_RD(addr));
+ printk(KERN_INFO "%s %s:0x%08lx=0x%08x\n", hdr, key, addr,
+ __raw_readl((void __iomem *)addr));
return;
}
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index 55123564881..305eb12f84c 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -204,8 +204,8 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
.mask_ack = toshiba_rbtx4927_irq_ioc_disable,
.unmask = toshiba_rbtx4927_irq_ioc_enable,
};
-#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
-#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
+#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL
+#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL
u32 bit2num(u32 num)
@@ -224,7 +224,7 @@ int toshiba_rbtx4927_irq_nested(int sw_irq)
{
u32 level3;
- level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
+ level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
if (level3) {
sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3);
if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) {
@@ -288,9 +288,9 @@ static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
panic("\n");
}
- v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
+ v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
- TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
+ writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB);
}
@@ -308,9 +308,10 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
panic("\n");
}
- v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
+ v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
- TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
+ writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB);
+ mmiowb();
}
@@ -387,12 +388,12 @@ void toshiba_rbtx4927_irq_dump_pics(char *s)
level1_m = level0_m;
level1_s = level0_s & 0x87;
- level2 = TX4927_RD(0xff1ff6a0);
+ level2 = __raw_readl((void __iomem *)0xff1ff6a0UL);
level2_p = (((level2 & 0x10000)) ? 0 : 1);
level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f));
- level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f;
- level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
+ level3_m = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f;
+ level3_s = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
level4_m = inb(0x21);
outb(0x0A, 0x20);
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
index 3e84237abe6..4f302062b2d 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
@@ -679,25 +679,30 @@ void __init tx4927_pci_setup(void)
#endif /* CONFIG_PCI */
+static void __noreturn wait_forever(void)
+{
+ while (1)
+ if (cpu_wait)
+ (*cpu_wait)();
+}
+
void toshiba_rbtx4927_restart(char *command)
{
printk(KERN_NOTICE "System Rebooting...\n");
/* enable the s/w reset register */
- reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET);
+ writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);
/* wait for enable to be seen */
- while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) &
+ while ((readb(RBTX4927_SW_RESET_ENABLE) &
RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
/* do a s/w reset */
- reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET);
+ writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);
/* do something passive while waiting for reset */
local_irq_disable();
- while (1)
- asm_wait();
-
+ wait_forever();
/* no return */
}
@@ -706,9 +711,7 @@ void toshiba_rbtx4927_halt(void)
{
printk(KERN_NOTICE "System Halted\n");
local_irq_disable();
- while (1) {
- asm_wait();
- }
+ wait_forever();
/* no return */
}
@@ -720,7 +723,7 @@ void toshiba_rbtx4927_power_off(void)
void __init toshiba_rbtx4927_setup(void)
{
- vu32 cp0_config;
+ u32 cp0_config;
char *argptr;
printk("CPU is %s\n", toshiba_name);
@@ -747,15 +750,6 @@ void __init toshiba_rbtx4927_setup(void)
}
#endif
- /* setup serial stuff */
- TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
- ":Setting up tx4927 sio.\n");
- TX4927_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
- TX4927_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
-
- TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
- "+\n");
-
set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
":mips_io_port_base=0x%08lx\n",
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-12-02 20:49:06 +0000