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Diffstat (limited to 'arch/mips/sibyte/sb1250/irq.c')
-rw-r--r--arch/mips/sibyte/sb1250/irq.c96
1 files changed, 37 insertions, 59 deletions
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 808ac2959b8..6d8dba5cf34 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -22,12 +22,10 @@
#include <linux/spinlock.h>
#include <linux/smp.h>
#include <linux/mm.h>
-#include <linux/slab.h>
#include <linux/kernel_stat.h>
#include <asm/errno.h>
#include <asm/signal.h>
-#include <asm/system.h>
#include <asm/time.h>
#include <asm/io.h>
@@ -44,48 +42,27 @@
* for interrupt lines
*/
-
-static void end_sb1250_irq(unsigned int irq);
-static void enable_sb1250_irq(unsigned int irq);
-static void disable_sb1250_irq(unsigned int irq);
-static void ack_sb1250_irq(unsigned int irq);
-#ifdef CONFIG_SMP
-static void sb1250_set_affinity(unsigned int irq, const struct cpumask *mask);
-#endif
-
#ifdef CONFIG_SIBYTE_HAS_LDT
extern unsigned long ldt_eoi_space;
#endif
-static struct irq_chip sb1250_irq_type = {
- .name = "SB1250-IMR",
- .ack = ack_sb1250_irq,
- .mask = disable_sb1250_irq,
- .mask_ack = ack_sb1250_irq,
- .unmask = enable_sb1250_irq,
- .end = end_sb1250_irq,
-#ifdef CONFIG_SMP
- .set_affinity = sb1250_set_affinity
-#endif
-};
-
/* Store the CPU id (not the logical number) */
int sb1250_irq_owner[SB1250_NR_IRQS];
-DEFINE_SPINLOCK(sb1250_imr_lock);
+static DEFINE_RAW_SPINLOCK(sb1250_imr_lock);
void sb1250_mask_irq(int cpu, int irq)
{
unsigned long flags;
u64 cur_ints;
- spin_lock_irqsave(&sb1250_imr_lock, flags);
+ raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
cur_ints |= (((u64) 1) << irq);
____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
- spin_unlock_irqrestore(&sb1250_imr_lock, flags);
+ raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
}
void sb1250_unmask_irq(int cpu, int irq)
@@ -93,36 +70,31 @@ void sb1250_unmask_irq(int cpu, int irq)
unsigned long flags;
u64 cur_ints;
- spin_lock_irqsave(&sb1250_imr_lock, flags);
+ raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
cur_ints &= ~(((u64) 1) << irq);
____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
- spin_unlock_irqrestore(&sb1250_imr_lock, flags);
+ raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
}
#ifdef CONFIG_SMP
-static void sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
+static int sb1250_set_affinity(struct irq_data *d, const struct cpumask *mask,
+ bool force)
{
int i = 0, old_cpu, cpu, int_on;
+ unsigned int irq = d->irq;
u64 cur_ints;
- struct irq_desc *desc = irq_desc + irq;
unsigned long flags;
- i = cpumask_first(mask);
-
- if (cpumask_weight(mask) > 1) {
- printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
- return;
- }
+ i = cpumask_first_and(mask, cpu_online_mask);
/* Convert logical CPU to physical CPU */
cpu = cpu_logical_map(i);
/* Protect against other affinity changers and IMR manipulation */
- spin_lock_irqsave(&desc->lock, flags);
- spin_lock(&sb1250_imr_lock);
+ raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
/* Swizzle each CPU's IMR (but leave the IP selection alone) */
old_cpu = sb1250_irq_owner[irq];
@@ -144,26 +116,30 @@ static void sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
R_IMR_INTERRUPT_MASK));
}
- spin_unlock(&sb1250_imr_lock);
- spin_unlock_irqrestore(&desc->lock, flags);
+ raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
+
+ return 0;
}
#endif
-/*****************************************************************************/
-
-static void disable_sb1250_irq(unsigned int irq)
+static void disable_sb1250_irq(struct irq_data *d)
{
+ unsigned int irq = d->irq;
+
sb1250_mask_irq(sb1250_irq_owner[irq], irq);
}
-static void enable_sb1250_irq(unsigned int irq)
+static void enable_sb1250_irq(struct irq_data *d)
{
+ unsigned int irq = d->irq;
+
sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
}
-static void ack_sb1250_irq(unsigned int irq)
+static void ack_sb1250_irq(struct irq_data *d)
{
+ unsigned int irq = d->irq;
#ifdef CONFIG_SIBYTE_HAS_LDT
u64 pending;
@@ -206,21 +182,23 @@ static void ack_sb1250_irq(unsigned int irq)
sb1250_mask_irq(sb1250_irq_owner[irq], irq);
}
-
-static void end_sb1250_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
- sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
- }
-}
-
+static struct irq_chip sb1250_irq_type = {
+ .name = "SB1250-IMR",
+ .irq_mask_ack = ack_sb1250_irq,
+ .irq_unmask = enable_sb1250_irq,
+ .irq_mask = disable_sb1250_irq,
+#ifdef CONFIG_SMP
+ .irq_set_affinity = sb1250_set_affinity
+#endif
+};
void __init init_sb1250_irqs(void)
{
int i;
for (i = 0; i < SB1250_NR_IRQS; i++) {
- set_irq_chip(i, &sb1250_irq_type);
+ irq_set_chip_and_handler(i, &sb1250_irq_type,
+ handle_level_irq);
sb1250_irq_owner[i] = 0;
}
}
@@ -243,7 +221,7 @@ void __init init_sb1250_irqs(void)
* On the second cpu, everything is set to IP5, which is
* ignored, EXCEPT the mailbox interrupt. That one is
* set to IP[2] so it is handled. This is needed so we
- * can do cross-cpu function calls, as requred by SMP
+ * can do cross-cpu function calls, as required by SMP
*/
#define IMR_IP2_VAL K_INT_MAP_I0
@@ -286,7 +264,7 @@ void __init arch_init_irq(void)
IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3)));
- /* Clear the mailboxes. The firmware may leave them dirty */
+ /* Clear the mailboxes. The firmware may leave them dirty */
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
__raw_writeq(0xffffffffffffffffULL,
@@ -299,7 +277,7 @@ void __init arch_init_irq(void)
/*
* Note that the timer interrupts are also mapped, but this is
- * done in sb1250_time_init(). Also, the profiling driver
+ * done in sb1250_time_init(). Also, the profiling driver
* does its own management of IP7.
*/
@@ -316,7 +294,7 @@ static inline void dispatch_ip2(void)
/*
* Default...we've hit an IP[2] interrupt, which means we've got to
- * check the 1250 interrupt registers to figure out what to do. Need
+ * check the 1250 interrupt registers to figure out what to do. Need
* to detect which CPU we're on, now that smp_affinity is supported.
*/
mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
@@ -345,7 +323,7 @@ asmlinkage void plat_irq_dispatch(void)
if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
do_IRQ(MIPS_CPU_IRQ_BASE + 7);
else if (pending & CAUSEF_IP4)
- do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */
+ do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */
#ifdef CONFIG_SMP
else if (pending & CAUSEF_IP3)
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-12-10 20:39:19 +0000