diff options
Diffstat (limited to 'arch/mips/sgi-ip22/ip22-nvram.c')
| -rw-r--r-- | arch/mips/sgi-ip22/ip22-nvram.c | 54 |
1 files changed, 28 insertions, 26 deletions
diff --git a/arch/mips/sgi-ip22/ip22-nvram.c b/arch/mips/sgi-ip22/ip22-nvram.c index e19d60d5fcc..e077036a676 100644 --- a/arch/mips/sgi-ip22/ip22-nvram.c +++ b/arch/mips/sgi-ip22/ip22-nvram.c @@ -14,11 +14,11 @@ #define EEPROM_WRITE 0xa000 /* serial memory write */ #define EEPROM_WRALL 0x8800 /* write all registers */ #define EEPROM_WDS 0x8000 /* disable all programming */ -#define EEPROM_PRREAD 0xc000 /* read protect register */ -#define EEPROM_PREN 0x9800 /* enable protect register mode */ -#define EEPROM_PRCLEAR 0xffff /* clear protect register */ -#define EEPROM_PRWRITE 0xa000 /* write protect register */ -#define EEPROM_PRDS 0x8000 /* disable protect register, forever */ +#define EEPROM_PRREAD 0xc000 /* read protect register */ +#define EEPROM_PREN 0x9800 /* enable protect register mode */ +#define EEPROM_PRCLEAR 0xffff /* clear protect register */ +#define EEPROM_PRWRITE 0xa000 /* write protect register */ +#define EEPROM_PRDS 0x8000 /* disable protect register, forever */ #define EEPROM_EPROT 0x01 /* Protect register enable */ #define EEPROM_CSEL 0x02 /* Chip select */ @@ -27,26 +27,26 @@ #define EEPROM_DATI 0x10 /* Data in */ /* We need to use these functions early... */ -#define delay() ({ \ +#define delay() ({ \ int x; \ for (x=0; x<100000; x++) __asm__ __volatile__(""); }) #define eeprom_cs_on(ptr) ({ \ - *ptr &= ~EEPROM_DATO; \ - *ptr &= ~EEPROM_ECLK; \ - *ptr &= ~EEPROM_EPROT; \ - delay(); \ - *ptr |= EEPROM_CSEL; \ - *ptr |= EEPROM_ECLK; }) + __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \ + __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \ + __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \ + delay(); \ + __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \ + __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); }) #define eeprom_cs_off(ptr) ({ \ - *ptr &= ~EEPROM_ECLK; \ - *ptr &= ~EEPROM_CSEL; \ - *ptr |= EEPROM_EPROT; \ - *ptr |= EEPROM_ECLK; }) + __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \ + __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \ + __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \ + __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); }) -#define BITS_IN_COMMAND 11 +#define BITS_IN_COMMAND 11 /* * clock in the nvram command and the register number. For the * national semiconductor nv ram chip the op code is 3 bits and @@ -60,15 +60,17 @@ static inline void eeprom_cmd(unsigned int *ctrl, unsigned cmd, unsigned reg) ser_cmd = cmd | (reg << (16 - BITS_IN_COMMAND)); for (i = 0; i < BITS_IN_COMMAND; i++) { if (ser_cmd & (1<<15)) /* if high order bit set */ - writel(readl(ctrl) | EEPROM_DATO, ctrl); + __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); else - writel(readl(ctrl) & ~EEPROM_DATO, ctrl); - writel(readl(ctrl) & ~EEPROM_ECLK, ctrl); - writel(readl(ctrl) | EEPROM_ECLK, ctrl); + __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl); + __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl); + delay(); + __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl); + delay(); ser_cmd <<= 1; } /* see data sheet timing diagram */ - writel(readl(ctrl) & ~EEPROM_DATO, ctrl); + __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl); } unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg) @@ -76,18 +78,18 @@ unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg) unsigned short res = 0; int i; - writel(readl(ctrl) & ~EEPROM_EPROT, ctrl); + __raw_writel(__raw_readl(ctrl) & ~EEPROM_EPROT, ctrl); eeprom_cs_on(ctrl); eeprom_cmd(ctrl, EEPROM_READ, reg); /* clock the data ouf of serial mem */ for (i = 0; i < 16; i++) { - writel(readl(ctrl) & ~EEPROM_ECLK, ctrl); + __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl); delay(); - writel(readl(ctrl) | EEPROM_ECLK, ctrl); + __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl); delay(); res <<= 1; - if (readl(ctrl) & EEPROM_DATI) + if (__raw_readl(ctrl) & EEPROM_DATI) res |= 1; } |
