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-rw-r--r--arch/mips/rb532/Makefile2
-rw-r--r--arch/mips/rb532/Platform7
-rw-r--r--arch/mips/rb532/devices.c135
-rw-r--r--arch/mips/rb532/gpio.c230
-rw-r--r--arch/mips/rb532/irq.c62
-rw-r--r--arch/mips/rb532/prom.c19
-rw-r--r--arch/mips/rb532/serial.c9
-rw-r--r--arch/mips/rb532/setup.c5
-rw-r--r--arch/mips/rb532/time.c1
9 files changed, 245 insertions, 225 deletions
diff --git a/arch/mips/rb532/Makefile b/arch/mips/rb532/Makefile
index 8f0b6b6a162..efdecdb6e3e 100644
--- a/arch/mips/rb532/Makefile
+++ b/arch/mips/rb532/Makefile
@@ -3,5 +3,3 @@
#
obj-y += irq.o time.o setup.o serial.o prom.o gpio.o devices.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/rb532/Platform b/arch/mips/rb532/Platform
new file mode 100644
index 00000000000..aeec45a7cbb
--- /dev/null
+++ b/arch/mips/rb532/Platform
@@ -0,0 +1,7 @@
+#
+# Routerboard 532
+#
+platform-$(CONFIG_MIKROTIK_RB532) += rb532/
+cflags-$(CONFIG_MIKROTIK_RB532) += \
+ -I$(srctree)/arch/mips/include/asm/mach-rc32434
+load-$(CONFIG_MIKROTIK_RB532) += 0xffffffff80101000
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
index 82ab395efa3..3af00b2a26e 100644
--- a/arch/mips/rb532/devices.c
+++ b/arch/mips/rb532/devices.c
@@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
+#include <linux/export.h>
#include <linux/init.h>
#include <linux/ctype.h>
#include <linux/string.h>
@@ -24,6 +25,7 @@
#include <linux/mtd/partitions.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
+#include <linux/serial_8250.h>
#include <asm/bootinfo.h>
@@ -34,20 +36,33 @@
#include <asm/mach-rc32434/rb.h>
#include <asm/mach-rc32434/integ.h>
#include <asm/mach-rc32434/gpio.h>
-
-#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0)
-#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1)
-#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9)
-#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10)
+#include <asm/mach-rc32434/irq.h>
#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
-/* NAND definitions */
-#define GPIO_RDY (1 << 0x08)
-#define GPIO_WPX (1 << 0x09)
-#define GPIO_ALE (1 << 0x0a)
-#define GPIO_CLE (1 << 0x0b)
+extern unsigned int idt_cpu_freq;
+
+static struct mpmc_device dev3;
+
+void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev3.lock, flags);
+
+ dev3.state = (dev3.state | or_mask) & ~nand_mask;
+ writeb(dev3.state, dev3.base);
+
+ spin_unlock_irqrestore(&dev3.lock, flags);
+}
+EXPORT_SYMBOL(set_latch_u5);
+
+unsigned char get_latch_u5(void)
+{
+ return dev3.state;
+}
+EXPORT_SYMBOL(get_latch_u5);
static struct resource korina_dev0_res[] = {
{
@@ -94,15 +109,12 @@ static struct korina_device korina_dev0_data = {
};
static struct platform_device korina_dev0 = {
- .id = 0,
+ .id = -1,
.name = "korina",
- .dev.platform_data = &korina_dev0_data,
.resource = korina_dev0_res,
.num_resources = ARRAY_SIZE(korina_dev0_res),
};
-#define CF_GPIO_NUM 13
-
static struct resource cf_slot0_res[] = {
{
.name = "cf_membase",
@@ -116,11 +128,11 @@ static struct resource cf_slot0_res[] = {
};
static struct cf_device cf_slot0_data = {
- .gpio_pin = 13
+ .gpio_pin = CF_GPIO_NUM
};
static struct platform_device cf_slot0 = {
- .id = 0,
+ .id = -1,
.name = "pata-rb532-cf",
.dev.platform_data = &cf_slot0_data,
.resource = cf_slot0_res,
@@ -130,7 +142,7 @@ static struct platform_device cf_slot0 = {
/* Resources and device for NAND */
static int rb532_dev_ready(struct mtd_info *mtd)
{
- return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
+ return gpio_get_value(GPIO_RDY);
}
static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
@@ -185,29 +197,12 @@ static struct mtd_partition rb532_partition_info[] = {
static struct platform_device rb532_led = {
.name = "rb532-led",
- .id = 0,
-};
-
-static struct gpio_keys_button rb532_gpio_btn[] = {
- {
- .gpio = 1,
- .code = BTN_0,
- .desc = "S1",
- .active_low = 1,
- }
-};
-
-static struct gpio_keys_platform_data rb532_gpio_btn_data = {
- .buttons = rb532_gpio_btn,
- .nbuttons = ARRAY_SIZE(rb532_gpio_btn),
+ .id = -1,
};
static struct platform_device rb532_button = {
- .name = "gpio-keys",
+ .name = "rb532-button",
.id = -1,
- .dev = {
- .platform_data = &rb532_gpio_btn_data,
- }
};
static struct resource rb532_wdt_res[] = {
@@ -220,51 +215,65 @@ static struct resource rb532_wdt_res[] = {
};
static struct platform_device rb532_wdt = {
- .name = "rc32434_wdt",
- .id = -1,
- .resource = rb532_wdt_res,
+ .name = "rc32434_wdt",
+ .id = -1,
+ .resource = rb532_wdt_res,
.num_resources = ARRAY_SIZE(rb532_wdt_res),
};
+static struct plat_serial8250_port rb532_uart_res[] = {
+ {
+ .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
+ .irq = UART0_IRQ,
+ .regshift = 2,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF,
+ },
+ {
+ .flags = 0,
+ }
+};
+
+static struct platform_device rb532_uart = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev.platform_data = &rb532_uart_res,
+};
+
static struct platform_device *rb532_devs[] = {
&korina_dev0,
&nand_slot0,
&cf_slot0,
&rb532_led,
&rb532_button,
+ &rb532_uart,
&rb532_wdt
};
static void __init parse_mac_addr(char *macstr)
{
- int i, j;
- unsigned char result, value;
+ int i, h, l;
for (i = 0; i < 6; i++) {
- result = 0;
-
if (i != 5 && *(macstr + 2) != ':')
return;
- for (j = 0; j < 2; j++) {
- if (isxdigit(*macstr)
- && (value =
- isdigit(*macstr) ? *macstr -
- '0' : toupper(*macstr) - 'A' + 10) < 16) {
- result = result * 16 + value;
- macstr++;
- } else
- return;
- }
+ h = hex_to_bin(*macstr++);
+ if (h == -1)
+ return;
+
+ l = hex_to_bin(*macstr++);
+ if (l == -1)
+ return;
macstr++;
- korina_dev0_data.mac[i] = result;
+ korina_dev0_data.mac[i] = (h << 4) + l;
}
}
/* NAND definitions */
-#define NAND_CHIP_DELAY 25
+#define NAND_CHIP_DELAY 25
static void __init rb532_nand_setup(void)
{
@@ -284,7 +293,6 @@ static void __init rb532_nand_setup(void)
rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
rb532_nand_data.chip.partitions = rb532_partition_info;
rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
- rb532_nand_data.chip.options = NAND_NO_AUTOINCR;
}
@@ -292,7 +300,7 @@ static int __init plat_setup_devices(void)
{
/* Look for the CF card reader */
if (!readl(IDT434_REG_BASE + DEV1MASK))
- rb532_devs[1] = NULL;
+ rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */
else {
cf_slot0_res[0].start =
readl(IDT434_REG_BASE + DEV1BASE);
@@ -303,9 +311,22 @@ static int __init plat_setup_devices(void)
nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
+ /* Read and map device controller 3 */
+ dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1);
+
+ if (!dev3.base) {
+ printk(KERN_ERR "rb532: cannot remap device controller 3\n");
+ return -ENXIO;
+ }
+
/* Initialise the NAND device */
rb532_nand_setup();
+ /* set the uart clock to the current cpu frequency */
+ rb532_uart_res[0].uartclk = idt_cpu_freq;
+
+ dev_set_drvdata(&korina_dev0.dev, &korina_dev0_data);
+
return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
}
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
index 00a1c7877bf..a18007613c3 100644
--- a/arch/mips/rb532/gpio.c
+++ b/arch/mips/rb532/gpio.c
@@ -27,194 +27,174 @@
*/
#include <linux/kernel.h>
-#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/types.h>
-#include <linux/pci.h>
+#include <linux/export.h>
#include <linux/spinlock.h>
-#include <linux/io.h>
#include <linux/platform_device.h>
-
-#include <asm/addrspace.h>
+#include <linux/gpio.h>
#include <asm/mach-rc32434/rb.h>
+#include <asm/mach-rc32434/gpio.h>
-struct rb532_gpio_reg __iomem *rb532_gpio_reg0;
-EXPORT_SYMBOL(rb532_gpio_reg0);
-
-struct mpmc_device dev3;
-
-static struct resource rb532_gpio_reg0_res[] = {
- {
- .name = "gpio_reg0",
- .start = (u32)(IDT434_REG_BASE + GPIOBASE),
- .end = (u32)(IDT434_REG_BASE + GPIOBASE + sizeof(struct rb532_gpio_reg)),
- .flags = IORESOURCE_MEM,
- }
+struct rb532_gpio_chip {
+ struct gpio_chip chip;
+ void __iomem *regbase;
};
-static struct resource rb532_dev3_ctl_res[] = {
+static struct resource rb532_gpio_reg0_res[] = {
{
- .name = "dev3_ctl",
- .start = (u32)(IDT434_REG_BASE + DEV3BASE),
- .end = (u32)(IDT434_REG_BASE + DEV3BASE + sizeof(struct dev_reg)),
+ .name = "gpio_reg0",
+ .start = REGBASE + GPIOBASE,
+ .end = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
.flags = IORESOURCE_MEM,
}
};
-void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
+/* rb532_set_bit - sanely set a bit
+ *
+ * bitval: new value for the bit
+ * offset: bit index in the 4 byte address range
+ * ioaddr: 4 byte aligned address being altered
+ */
+static inline void rb532_set_bit(unsigned bitval,
+ unsigned offset, void __iomem *ioaddr)
{
unsigned long flags;
- unsigned data;
- unsigned i = 0;
+ u32 val;
- spin_lock_irqsave(&dev3.lock, flags);
+ local_irq_save(flags);
- data = *(volatile unsigned *) (IDT434_REG_BASE + reg_offs);
- for (i = 0; i != len; ++i) {
- if (val & (1 << i))
- data |= (1 << (i + bit));
- else
- data &= ~(1 << (i + bit));
- }
- writel(data, (IDT434_REG_BASE + reg_offs));
+ val = readl(ioaddr);
+ val &= ~(!bitval << offset); /* unset bit if bitval == 0 */
+ val |= (!!bitval << offset); /* set bit if bitval == 1 */
+ writel(val, ioaddr);
- spin_unlock_irqrestore(&dev3.lock, flags);
+ local_irq_restore(flags);
}
-EXPORT_SYMBOL(set_434_reg);
-unsigned get_434_reg(unsigned reg_offs)
+/* rb532_get_bit - read a bit
+ *
+ * returns the boolean state of the bit, which may be > 1
+ */
+static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr)
{
- return readl(IDT434_REG_BASE + reg_offs);
+ return (readl(ioaddr) & (1 << offset));
}
-EXPORT_SYMBOL(get_434_reg);
-void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
+/*
+ * Return GPIO level */
+static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
{
- unsigned long flags;
-
- spin_lock_irqsave(&dev3.lock, flags);
+ struct rb532_gpio_chip *gpch;
- dev3.state = (dev3.state | or_mask) & ~nand_mask;
- writel(dev3.state, &dev3.base);
-
- spin_unlock_irqrestore(&dev3.lock, flags);
+ gpch = container_of(chip, struct rb532_gpio_chip, chip);
+ return rb532_get_bit(offset, gpch->regbase + GPIOD);
}
-EXPORT_SYMBOL(set_latch_u5);
-unsigned char get_latch_u5(void)
+/*
+ * Set output GPIO level
+ */
+static void rb532_gpio_set(struct gpio_chip *chip,
+ unsigned offset, int value)
{
- return dev3.state;
-}
-EXPORT_SYMBOL(get_latch_u5);
+ struct rb532_gpio_chip *gpch;
-int rb532_gpio_get_value(unsigned gpio)
-{
- return readl(&rb532_gpio_reg0->gpiod) & (1 << gpio);
+ gpch = container_of(chip, struct rb532_gpio_chip, chip);
+ rb532_set_bit(value, offset, gpch->regbase + GPIOD);
}
-EXPORT_SYMBOL(rb532_gpio_get_value);
-void rb532_gpio_set_value(unsigned gpio, int value)
+/*
+ * Set GPIO direction to input
+ */
+static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
- unsigned tmp;
-
- tmp = readl(&rb532_gpio_reg0->gpiod) & ~(1 << gpio);
- if (value)
- tmp |= 1 << gpio;
+ struct rb532_gpio_chip *gpch;
- writel(tmp, (void *)&rb532_gpio_reg0->gpiod);
-}
-EXPORT_SYMBOL(rb532_gpio_set_value);
+ gpch = container_of(chip, struct rb532_gpio_chip, chip);
-int rb532_gpio_direction_input(unsigned gpio)
-{
- writel(readl(&rb532_gpio_reg0->gpiocfg) & ~(1 << gpio),
- (void *)&rb532_gpio_reg0->gpiocfg);
+ /* disable alternate function in case it's set */
+ rb532_set_bit(0, offset, gpch->regbase + GPIOFUNC);
+ rb532_set_bit(0, offset, gpch->regbase + GPIOCFG);
return 0;
}
-EXPORT_SYMBOL(rb532_gpio_direction_input);
-int rb532_gpio_direction_output(unsigned gpio, int value)
+/*
+ * Set GPIO direction to output
+ */
+static int rb532_gpio_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
{
- gpio_set_value(gpio, value);
- writel(readl(&rb532_gpio_reg0->gpiocfg) | (1 << gpio),
- (void *)&rb532_gpio_reg0->gpiocfg);
+ struct rb532_gpio_chip *gpch;
- return 0;
-}
-EXPORT_SYMBOL(rb532_gpio_direction_output);
+ gpch = container_of(chip, struct rb532_gpio_chip, chip);
-void rb532_gpio_set_int_level(unsigned gpio, int value)
-{
- unsigned tmp;
+ /* disable alternate function in case it's set */
+ rb532_set_bit(0, offset, gpch->regbase + GPIOFUNC);
- tmp = readl(&rb532_gpio_reg0->gpioilevel) & ~(1 << gpio);
- if (value)
- tmp |= 1 << gpio;
- writel(tmp, (void *)&rb532_gpio_reg0->gpioilevel);
-}
-EXPORT_SYMBOL(rb532_gpio_set_int_level);
+ /* set the initial output value */
+ rb532_set_bit(value, offset, gpch->regbase + GPIOD);
-int rb532_gpio_get_int_level(unsigned gpio)
-{
- return readl(&rb532_gpio_reg0->gpioilevel) & (1 << gpio);
+ rb532_set_bit(1, offset, gpch->regbase + GPIOCFG);
+ return 0;
}
-EXPORT_SYMBOL(rb532_gpio_get_int_level);
-
-void rb532_gpio_set_int_status(unsigned gpio, int value)
-{
- unsigned tmp;
- tmp = readl(&rb532_gpio_reg0->gpioistat);
- if (value)
- tmp |= 1 << gpio;
- writel(tmp, (void *)&rb532_gpio_reg0->gpioistat);
-}
-EXPORT_SYMBOL(rb532_gpio_set_int_status);
+static struct rb532_gpio_chip rb532_gpio_chip[] = {
+ [0] = {
+ .chip = {
+ .label = "gpio0",
+ .direction_input = rb532_gpio_direction_input,
+ .direction_output = rb532_gpio_direction_output,
+ .get = rb532_gpio_get,
+ .set = rb532_gpio_set,
+ .base = 0,
+ .ngpio = 32,
+ },
+ },
+};
-int rb532_gpio_get_int_status(unsigned gpio)
+/*
+ * Set GPIO interrupt level
+ */
+void rb532_gpio_set_ilevel(int bit, unsigned gpio)
{
- return readl(&rb532_gpio_reg0->gpioistat) & (1 << gpio);
+ rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL);
}
-EXPORT_SYMBOL(rb532_gpio_get_int_status);
+EXPORT_SYMBOL(rb532_gpio_set_ilevel);
-void rb532_gpio_set_func(unsigned gpio, int value)
+/*
+ * Set GPIO interrupt status
+ */
+void rb532_gpio_set_istat(int bit, unsigned gpio)
{
- unsigned tmp;
-
- tmp = readl(&rb532_gpio_reg0->gpiofunc);
- if (value)
- tmp |= 1 << gpio;
- writel(tmp, (void *)&rb532_gpio_reg0->gpiofunc);
+ rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT);
}
-EXPORT_SYMBOL(rb532_gpio_set_func);
+EXPORT_SYMBOL(rb532_gpio_set_istat);
-int rb532_gpio_get_func(unsigned gpio)
+/*
+ * Configure GPIO alternate function
+ */
+void rb532_gpio_set_func(unsigned gpio)
{
- return readl(&rb532_gpio_reg0->gpiofunc) & (1 << gpio);
+ rb532_set_bit(1, gpio, rb532_gpio_chip->regbase + GPIOFUNC);
}
-EXPORT_SYMBOL(rb532_gpio_get_func);
+EXPORT_SYMBOL(rb532_gpio_set_func);
int __init rb532_gpio_init(void)
{
- rb532_gpio_reg0 = ioremap_nocache(rb532_gpio_reg0_res[0].start,
- rb532_gpio_reg0_res[0].end -
- rb532_gpio_reg0_res[0].start);
+ struct resource *r;
+
+ r = rb532_gpio_reg0_res;
+ rb532_gpio_chip->regbase = ioremap_nocache(r->start, resource_size(r));
- if (!rb532_gpio_reg0) {
+ if (!rb532_gpio_chip->regbase) {
printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
return -ENXIO;
}
- dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start,
- rb532_dev3_ctl_res[0].end -
- rb532_dev3_ctl_res[0].start);
-
- if (!dev3.base) {
- printk(KERN_ERR "rb532: cannot remap device controller 3\n");
- return -ENXIO;
- }
+ /* Register our GPIO chip */
+ gpiochip_add(&rb532_gpio_chip->chip);
return 0;
}
diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
index c0d0f950caf..3a431e802bb 100644
--- a/arch/mips/rb532/irq.c
+++ b/arch/mips/rb532/irq.c
@@ -21,7 +21,7 @@
*
* Copyright 2002 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
- * stevel@mvista.com or source@mvista.com
+ * stevel@mvista.com or source@mvista.com
*/
#include <linux/bitops.h>
@@ -36,23 +36,22 @@
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
-#include <linux/slab.h>
#include <linux/random.h>
#include <linux/delay.h>
#include <asm/bootinfo.h>
#include <asm/time.h>
#include <asm/mipsregs.h>
-#include <asm/system.h>
-#include <asm/mach-rc32434/rc32434.h>
+#include <asm/mach-rc32434/irq.h>
+#include <asm/mach-rc32434/gpio.h>
struct intr_group {
u32 mask; /* mask of valid bits in pending/mask registers */
volatile u32 *base_addr;
};
-#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
+#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
#if (NR_IRQS < RC32434_NR_IRQS)
#error Too little irqs defined. Did you override <asm/irq.h> ?
@@ -111,10 +110,10 @@ static inline void ack_local_irq(unsigned int ip)
clear_c0_cause(ipnum);
}
-static void rb532_enable_irq(unsigned int irq_nr)
+static void rb532_enable_irq(struct irq_data *d)
{
+ unsigned int group, intr_bit, irq_nr = d->irq;
int ip = irq_nr - GROUP0_IRQ_BASE;
- unsigned int group, intr_bit;
volatile unsigned int *addr;
if (ip < 0)
@@ -132,10 +131,10 @@ static void rb532_enable_irq(unsigned int irq_nr)
}
}
-static void rb532_disable_irq(unsigned int irq_nr)
+static void rb532_disable_irq(struct irq_data *d)
{
+ unsigned int group, intr_bit, mask, irq_nr = d->irq;
int ip = irq_nr - GROUP0_IRQ_BASE;
- unsigned int group, intr_bit, mask;
volatile unsigned int *addr;
if (ip < 0) {
@@ -150,6 +149,10 @@ static void rb532_disable_irq(unsigned int irq_nr)
mask |= intr_bit;
WRITE_MASK(addr, mask);
+ /* There is a maximum of 14 GPIO interrupts */
+ if (group == GPIO_MAPPED_IRQ_GROUP && irq_nr <= (GROUP4_IRQ_BASE + 13))
+ rb532_gpio_set_istat(0, irq_nr - GPIO_MAPPED_IRQ_BASE);
+
/*
* if there are no more interrupts enabled in this
* group, disable corresponding IP
@@ -159,18 +162,41 @@ static void rb532_disable_irq(unsigned int irq_nr)
}
}
-static void rb532_mask_and_ack_irq(unsigned int irq_nr)
+static void rb532_mask_and_ack_irq(struct irq_data *d)
+{
+ rb532_disable_irq(d);
+ ack_local_irq(group_to_ip(irq_to_group(d->irq)));
+}
+
+static int rb532_set_type(struct irq_data *d, unsigned type)
{
- rb532_disable_irq(irq_nr);
- ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
+ int gpio = d->irq - GPIO_MAPPED_IRQ_BASE;
+ int group = irq_to_group(d->irq);
+
+ if (group != GPIO_MAPPED_IRQ_GROUP || d->irq > (GROUP4_IRQ_BASE + 13))
+ return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;
+
+ switch (type) {
+ case IRQ_TYPE_LEVEL_HIGH:
+ rb532_gpio_set_ilevel(1, gpio);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ rb532_gpio_set_ilevel(0, gpio);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
}
static struct irq_chip rc32434_irq_type = {
.name = "RB532",
- .ack = rb532_disable_irq,
- .mask = rb532_disable_irq,
- .mask_ack = rb532_mask_and_ack_irq,
- .unmask = rb532_enable_irq,
+ .irq_ack = rb532_disable_irq,
+ .irq_mask = rb532_disable_irq,
+ .irq_mask_ack = rb532_mask_and_ack_irq,
+ .irq_unmask = rb532_enable_irq,
+ .irq_set_type = rb532_set_type,
};
void __init arch_init_irq(void)
@@ -180,8 +206,8 @@ void __init arch_init_irq(void)
pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
for (i = 0; i < RC32434_NR_IRQS; i++)
- set_irq_chip_and_handler(i, &rc32434_irq_type,
- handle_level_irq);
+ irq_set_chip_and_handler(i, &rc32434_irq_type,
+ handle_level_irq);
}
/* Main Interrupt dispatcher */
diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c
index 1bc0af8febf..a757ded437c 100644
--- a/arch/mips/rb532/prom.c
+++ b/arch/mips/rb532/prom.c
@@ -37,12 +37,8 @@
#include <asm/mach-rc32434/ddr.h>
#include <asm/mach-rc32434/prom.h>
-extern void __init setup_serial_port(void);
-
unsigned int idt_cpu_freq = 132000000;
EXPORT_SYMBOL(idt_cpu_freq);
-unsigned int gpio_bootup_state;
-EXPORT_SYMBOL(gpio_bootup_state);
static struct resource ddr_reg[] = {
{
@@ -73,15 +69,14 @@ static inline unsigned long tag2ul(char *arg, const char *tag)
void __init prom_setup_cmdline(void)
{
- char cmd_line[CL_SIZE];
+ static char cmd_line[COMMAND_LINE_SIZE] __initdata;
char *cp, *board;
int prom_argc;
- char **prom_argv, **prom_envp;
+ char **prom_argv;
int i;
prom_argc = fw_arg0;
prom_argv = (char **) fw_arg1;
- prom_envp = (char **) fw_arg2;
cp = cmd_line;
/* Note: it is common that parameters start
@@ -108,9 +103,6 @@ void __init prom_setup_cmdline(void)
mips_machtype = MACH_MIKROTIK_RB532;
}
- if (match_tag(prom_argv[i], GPIO_TAG))
- gpio_bootup_state = tag2ul(prom_argv[i], GPIO_TAG);
-
strcpy(cp, prom_argv[i]);
cp += strlen(prom_argv[i]);
}
@@ -122,12 +114,7 @@ void __init prom_setup_cmdline(void)
strcpy(cp, arcs_cmdline);
cp += strlen(arcs_cmdline);
}
- if (gpio_bootup_state & 0x02)
- strcpy(cp, GPIO_INIT_NOBUTTON);
- else
- strcpy(cp, GPIO_INIT_BUTTON);
-
- cmd_line[CL_SIZE-1] = '\0';
+ cmd_line[COMMAND_LINE_SIZE - 1] = '\0';
strcpy(arcs_cmdline, cmd_line);
}
diff --git a/arch/mips/rb532/serial.c b/arch/mips/rb532/serial.c
index 1a05b5ddee0..70482540b3d 100644
--- a/arch/mips/rb532/serial.c
+++ b/arch/mips/rb532/serial.c
@@ -29,18 +29,19 @@
#include <linux/tty.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
+#include <linux/irq.h>
#include <asm/serial.h>
-#include <asm/mach-rc32434/rc32434.h>
+#include <asm/mach-rc32434/rb.h>
extern unsigned int idt_cpu_freq;
static struct uart_port rb532_uart = {
- .type = PORT_16550A,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 0,
- .irq = RC32434_UART0_IRQ,
+ .irq = UART0_IRQ,
.iotype = UPIO_MEM,
- .membase = (char *)KSEG1ADDR(RC32434_UART0_BASE),
+ .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
.regshift = 2
};
diff --git a/arch/mips/rb532/setup.c b/arch/mips/rb532/setup.c
index 7aafa95ac20..d0c64e71d53 100644
--- a/arch/mips/rb532/setup.c
+++ b/arch/mips/rb532/setup.c
@@ -3,13 +3,14 @@
*/
#include <linux/init.h>
+#include <linux/export.h>
#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <linux/ioport.h>
-#include <asm/mach-rc32434/rc32434.h>
+#include <asm/mach-rc32434/rb.h>
#include <asm/mach-rc32434/pci.h>
struct pci_reg __iomem *pci_reg;
@@ -27,7 +28,7 @@ static struct resource pci0_res[] = {
static void rb_machine_restart(char *command)
{
/* just jump to the reset vector */
- writel(0x80000001, (void *)KSEG1ADDR(RC32434_REG_BASE + RC32434_RST));
+ writel(0x80000001, IDT434_REG_BASE + RST);
((void (*)(void)) KSEG1ADDR(0x1FC00000u))();
}
diff --git a/arch/mips/rb532/time.c b/arch/mips/rb532/time.c
index 8e7a46855b5..1377d599f0e 100644
--- a/arch/mips/rb532/time.c
+++ b/arch/mips/rb532/time.c
@@ -28,7 +28,6 @@
#include <linux/timex.h>
#include <asm/mipsregs.h>
-#include <asm/debug.h>
#include <asm/time.h>
#include <asm/mach-rc32434/rc32434.h>
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-12-19 23:34:01 +0000