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Diffstat (limited to 'arch/mips/pci/pci-ip32.c')
-rw-r--r--arch/mips/pci/pci-ip32.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c
index 180af89bcb1..b1e061f7fdc 100644
--- a/arch/mips/pci/pci-ip32.c
+++ b/arch/mips/pci/pci-ip32.c
@@ -6,7 +6,6 @@
* Copyright (C) 2000, 2001 Keith M Wesolowski
* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
*/
-#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
@@ -19,11 +18,11 @@
/*
* Handle errors from the bridge. This includes master and target aborts,
- * various command and address errors, and the interrupt test. This gets
- * registered on the bridge error irq. It's conceivable that some of these
- * conditions warrant a panic. Anybody care to say which ones?
+ * various command and address errors, and the interrupt test. This gets
+ * registered on the bridge error irq. It's conceivable that some of these
+ * conditions warrant a panic. Anybody care to say which ones?
*/
-static irqreturn_t macepci_error(int irq, void *dev, struct pt_regs *regs)
+static irqreturn_t macepci_error(int irq, void *dev)
{
char s;
unsigned int flags = mace->pci.error;
@@ -120,6 +119,7 @@ static struct pci_controller mace_pci_controller = {
.iommu = 0,
.mem_offset = MACE_PCI_MEM_OFFSET,
.io_offset = 0,
+ .io_map_base = CKSEG1ADDR(MACEPCI_LOW_IO),
};
static int __init mace_init(void)
@@ -136,7 +136,8 @@ static int __init mace_init(void)
BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0,
"MACE PCI error", NULL));
- iomem_resource = mace_pci_mem_resource;
+ /* extend memory resources */
+ iomem_resource.end = mace_pci_mem_resource.end;
ioport_resource = mace_pci_io_resource;
register_pci_controller(&mace_pci_controller);