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Diffstat (limited to 'arch/mips/mm/tlb-r4k.c')
-rw-r--r--arch/mips/mm/tlb-r4k.c337
1 files changed, 192 insertions, 145 deletions
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 8297970f0bb..3914e27456f 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -3,40 +3,56 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
*/
-#include <linux/config.h>
+#include <linux/cpu_pm.h>
#include <linux/init.h>
#include <linux/sched.h>
+#include <linux/smp.h>
#include <linux/mm.h>
+#include <linux/hugetlb.h>
+#include <linux/module.h>
#include <asm/cpu.h>
+#include <asm/cpu-type.h>
#include <asm/bootinfo.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
-#include <asm/system.h>
+#include <asm/tlb.h>
+#include <asm/tlbmisc.h>
extern void build_tlb_refill_handler(void);
/*
- * Make sure all entries differ. If they're not different
- * MIPS32 will take revenge ...
+ * LOONGSON2/3 has a 4 entry itlb which is a subset of dtlb,
+ * unfortunately, itlb is not totally transparent to software.
*/
-#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
+static inline void flush_itlb(void)
+{
+ switch (current_cpu_type()) {
+ case CPU_LOONGSON2:
+ case CPU_LOONGSON3:
+ write_c0_diag(4);
+ break;
+ default:
+ break;
+ }
+}
-/* CP0 hazard avoidance. */
-#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
- "nop; nop; nop; nop; nop; nop;\n\t" \
- ".set reorder\n\t")
+static inline void flush_itlb_vm(struct vm_area_struct *vma)
+{
+ if (vma->vm_flags & VM_EXEC)
+ flush_itlb();
+}
void local_flush_tlb_all(void)
{
unsigned long flags;
unsigned long old_ctx;
- int entry;
+ int entry, ftlbhighset;
local_irq_save(flags);
/* Save old context and create impossible VPN2 value */
@@ -47,18 +63,37 @@ void local_flush_tlb_all(void)
entry = read_c0_wired();
/* Blast 'em all away. */
- while (entry < current_cpu_data.tlbsize) {
- /* Make sure all entries differ. */
- write_c0_entryhi(UNIQUE_ENTRYHI(entry));
- write_c0_index(entry);
- mtc0_tlbw_hazard();
- tlb_write_indexed();
- entry++;
+ if (cpu_has_tlbinv) {
+ if (current_cpu_data.tlbsizevtlb) {
+ write_c0_index(0);
+ mtc0_tlbw_hazard();
+ tlbinvf(); /* invalidate VTLB */
+ }
+ ftlbhighset = current_cpu_data.tlbsizevtlb +
+ current_cpu_data.tlbsizeftlbsets;
+ for (entry = current_cpu_data.tlbsizevtlb;
+ entry < ftlbhighset;
+ entry++) {
+ write_c0_index(entry);
+ mtc0_tlbw_hazard();
+ tlbinvf(); /* invalidate one FTLB set */
+ }
+ } else {
+ while (entry < current_cpu_data.tlbsize) {
+ /* Make sure all entries differ. */
+ write_c0_entryhi(UNIQUE_ENTRYHI(entry));
+ write_c0_index(entry);
+ mtc0_tlbw_hazard();
+ tlb_write_indexed();
+ entry++;
+ }
}
tlbw_use_hazard();
write_c0_entryhi(old_ctx);
+ flush_itlb();
local_irq_restore(flags);
}
+EXPORT_SYMBOL(local_flush_tlb_all);
/* All entries common to a mm share an asid. To effectively flush
these entries, we just bump the asid. */
@@ -84,19 +119,18 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
int cpu = smp_processor_id();
if (cpu_context(cpu, mm) != 0) {
- unsigned long flags;
- int size;
+ unsigned long size, flags;
- size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
- size = (size + 1) >> 1;
local_irq_save(flags);
- if (size <= current_cpu_data.tlbsize/2) {
+ start = round_down(start, PAGE_SIZE << 1);
+ end = round_up(end, PAGE_SIZE << 1);
+ size = (end - start) >> (PAGE_SHIFT + 1);
+ if (size <= (current_cpu_data.tlbsizeftlbsets ?
+ current_cpu_data.tlbsize / 8 :
+ current_cpu_data.tlbsize / 2)) {
int oldpid = read_c0_entryhi();
int newpid = cpu_asid(cpu, mm);
- start &= (PAGE_MASK << 1);
- end += ((PAGE_SIZE << 1) - 1);
- end &= (PAGE_MASK << 1);
while (start < end) {
int idx;
@@ -104,7 +138,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
start += (PAGE_SIZE << 1);
mtc0_tlbw_hazard();
tlb_probe();
- BARRIER;
+ tlb_probe_hazard();
idx = read_c0_index();
write_c0_entrylo0(0);
write_c0_entrylo1(0);
@@ -120,19 +154,21 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
} else {
drop_mmu_context(mm, cpu);
}
+ flush_itlb();
local_irq_restore(flags);
}
}
void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
- unsigned long flags;
- int size;
+ unsigned long size, flags;
+ local_irq_save(flags);
size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
size = (size + 1) >> 1;
- local_irq_save(flags);
- if (size <= current_cpu_data.tlbsize / 2) {
+ if (size <= (current_cpu_data.tlbsizeftlbsets ?
+ current_cpu_data.tlbsize / 8 :
+ current_cpu_data.tlbsize / 2)) {
int pid = read_c0_entryhi();
start &= (PAGE_MASK << 1);
@@ -146,7 +182,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
start += (PAGE_SIZE << 1);
mtc0_tlbw_hazard();
tlb_probe();
- BARRIER;
+ tlb_probe_hazard();
idx = read_c0_index();
write_c0_entrylo0(0);
write_c0_entrylo1(0);
@@ -162,6 +198,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
} else {
local_flush_tlb_all();
}
+ flush_itlb();
local_irq_restore(flags);
}
@@ -180,7 +217,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
write_c0_entryhi(page | newpid);
mtc0_tlbw_hazard();
tlb_probe();
- BARRIER;
+ tlb_probe_hazard();
idx = read_c0_index();
write_c0_entrylo0(0);
write_c0_entrylo1(0);
@@ -194,6 +231,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
finish:
write_c0_entryhi(oldpid);
+ flush_itlb_vm(vma);
local_irq_restore(flags);
}
}
@@ -213,7 +251,7 @@ void local_flush_tlb_one(unsigned long page)
write_c0_entryhi(page);
mtc0_tlbw_hazard();
tlb_probe();
- BARRIER;
+ tlb_probe_hazard();
idx = read_c0_index();
write_c0_entrylo0(0);
write_c0_entrylo1(0);
@@ -225,7 +263,7 @@ void local_flush_tlb_one(unsigned long page)
tlbw_use_hazard();
}
write_c0_entryhi(oldpid);
-
+ flush_itlb();
local_irq_restore(flags);
}
@@ -257,65 +295,53 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
pgdp = pgd_offset(vma->vm_mm, address);
mtc0_tlbw_hazard();
tlb_probe();
- BARRIER;
+ tlb_probe_hazard();
pudp = pud_offset(pgdp, address);
pmdp = pmd_offset(pudp, address);
idx = read_c0_index();
- ptep = pte_offset_map(pmdp, address);
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+ /* this could be a huge page */
+ if (pmd_huge(*pmdp)) {
+ unsigned long lo;
+ write_c0_pagemask(PM_HUGE_MASK);
+ ptep = (pte_t *)pmdp;
+ lo = pte_to_entrylo(pte_val(*ptep));
+ write_c0_entrylo0(lo);
+ write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
- write_c0_entrylo0(ptep->pte_high);
- ptep++;
- write_c0_entrylo1(ptep->pte_high);
-#else
- write_c0_entrylo0(pte_val(*ptep++) >> 6);
- write_c0_entrylo1(pte_val(*ptep) >> 6);
+ mtc0_tlbw_hazard();
+ if (idx < 0)
+ tlb_write_random();
+ else
+ tlb_write_indexed();
+ tlbw_use_hazard();
+ write_c0_pagemask(PM_DEFAULT_MASK);
+ } else
#endif
- mtc0_tlbw_hazard();
- if (idx < 0)
- tlb_write_random();
- else
- tlb_write_indexed();
- tlbw_use_hazard();
- local_irq_restore(flags);
-}
+ {
+ ptep = pte_offset_map(pmdp, address);
-#if 0
-static void r4k_update_mmu_cache_hwbug(struct vm_area_struct * vma,
- unsigned long address, pte_t pte)
-{
- unsigned long flags;
- unsigned int asid;
- pgd_t *pgdp;
- pmd_t *pmdp;
- pte_t *ptep;
- int idx;
-
- local_irq_save(flags);
- address &= (PAGE_MASK << 1);
- asid = read_c0_entryhi() & ASID_MASK;
- write_c0_entryhi(address | asid);
- pgdp = pgd_offset(vma->vm_mm, address);
- mtc0_tlbw_hazard();
- tlb_probe();
- BARRIER;
- pmdp = pmd_offset(pgdp, address);
- idx = read_c0_index();
- ptep = pte_offset_map(pmdp, address);
- write_c0_entrylo0(pte_val(*ptep++) >> 6);
- write_c0_entrylo1(pte_val(*ptep) >> 6);
- mtc0_tlbw_hazard();
- if (idx < 0)
- tlb_write_random();
- else
- tlb_write_indexed();
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+ write_c0_entrylo0(ptep->pte_high);
+ ptep++;
+ write_c0_entrylo1(ptep->pte_high);
+#else
+ write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
+ write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
+#endif
+ mtc0_tlbw_hazard();
+ if (idx < 0)
+ tlb_write_random();
+ else
+ tlb_write_indexed();
+ }
tlbw_use_hazard();
+ flush_itlb_vm(vma);
local_irq_restore(flags);
}
-#endif
-void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
- unsigned long entryhi, unsigned long pagemask)
+void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
+ unsigned long entryhi, unsigned long pagemask)
{
unsigned long flags;
unsigned long wired;
@@ -329,7 +355,7 @@ void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
wired = read_c0_wired();
write_c0_wired(wired + 1);
write_c0_index(wired);
- BARRIER;
+ tlbw_use_hazard(); /* What is the hazard here? */
write_c0_pagemask(pagemask);
write_c0_entryhi(entryhi);
write_c0_entrylo0(entrylo0);
@@ -339,93 +365,114 @@ void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
tlbw_use_hazard();
write_c0_entryhi(old_ctx);
- BARRIER;
+ tlbw_use_hazard(); /* What is the hazard here? */
write_c0_pagemask(old_pagemask);
local_flush_tlb_all();
local_irq_restore(flags);
}
-/*
- * Used for loading TLB entries before trap_init() has started, when we
- * don't actually want to add a wired entry which remains throughout the
- * lifetime of the system
- */
-
-static int temp_tlb_entry __initdata;
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
-__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
- unsigned long entryhi, unsigned long pagemask)
+int __init has_transparent_hugepage(void)
{
- int ret = 0;
+ unsigned int mask;
unsigned long flags;
- unsigned long wired;
- unsigned long old_pagemask;
- unsigned long old_ctx;
local_irq_save(flags);
- /* Save old context and create impossible VPN2 value */
- old_ctx = read_c0_entryhi();
- old_pagemask = read_c0_pagemask();
- wired = read_c0_wired();
- if (--temp_tlb_entry < wired) {
- printk(KERN_WARNING
- "No TLB space left for add_temporary_entry\n");
- ret = -ENOSPC;
- goto out;
- }
-
- write_c0_index(temp_tlb_entry);
- write_c0_pagemask(pagemask);
- write_c0_entryhi(entryhi);
- write_c0_entrylo0(entrylo0);
- write_c0_entrylo1(entrylo1);
- mtc0_tlbw_hazard();
- tlb_write_indexed();
- tlbw_use_hazard();
+ write_c0_pagemask(PM_HUGE_MASK);
+ back_to_back_c0_hazard();
+ mask = read_c0_pagemask();
+ write_c0_pagemask(PM_DEFAULT_MASK);
- write_c0_entryhi(old_ctx);
- write_c0_pagemask(old_pagemask);
-out:
local_irq_restore(flags);
- return ret;
-}
-
-static void __init probe_tlb(unsigned long config)
-{
- struct cpuinfo_mips *c = &current_cpu_data;
- unsigned int reg;
- /*
- * If this isn't a MIPS32 / MIPS64 compliant CPU. Config 1 register
- * is not supported, we assume R4k style. Cpu probing already figured
- * out the number of tlb entries.
- */
- if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY)
- return;
+ return mask == PM_HUGE_MASK;
+}
- reg = read_c0_config1();
- if (!((config >> 7) & 3))
- panic("No TLB present");
+#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
- c->tlbsize = ((reg >> 25) & 0x3f) + 1;
+static int ntlb;
+static int __init set_ntlb(char *str)
+{
+ get_option(&str, &ntlb);
+ return 1;
}
-void __init tlb_init(void)
-{
- unsigned int config = read_c0_config();
+__setup("ntlb=", set_ntlb);
+/*
+ * Configure TLB (for init or after a CPU has been powered off).
+ */
+static void r4k_tlb_configure(void)
+{
/*
* You should never change this register:
* - On R4600 1.7 the tlbp never hits for pages smaller than
* the value in the c0_pagemask register.
* - The entire mm handling assumes the c0_pagemask register to
- * be set for 4kb pages.
+ * be set to fixed-size pages.
*/
- probe_tlb(config);
write_c0_pagemask(PM_DEFAULT_MASK);
write_c0_wired(0);
- temp_tlb_entry = current_cpu_data.tlbsize - 1;
+ if (current_cpu_type() == CPU_R10000 ||
+ current_cpu_type() == CPU_R12000 ||
+ current_cpu_type() == CPU_R14000)
+ write_c0_framemask(0);
+
+ if (cpu_has_rixi) {
+ /*
+ * Enable the no read, no exec bits, and enable large virtual
+ * address.
+ */
+ u32 pg = PG_RIE | PG_XIE;
+#ifdef CONFIG_64BIT
+ pg |= PG_ELPA;
+#endif
+ write_c0_pagegrain(pg);
+ }
+
+ /* From this point on the ARC firmware is dead. */
local_flush_tlb_all();
+ /* Did I tell you that ARC SUCKS? */
+}
+
+void tlb_init(void)
+{
+ r4k_tlb_configure();
+
+ if (ntlb) {
+ if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
+ int wired = current_cpu_data.tlbsize - ntlb;
+ write_c0_wired(wired);
+ write_c0_index(wired-1);
+ printk("Restricting TLB to %d entries\n", ntlb);
+ } else
+ printk("Ignoring invalid argument ntlb=%d\n", ntlb);
+ }
+
build_tlb_refill_handler();
}
+
+static int r4k_tlb_pm_notifier(struct notifier_block *self, unsigned long cmd,
+ void *v)
+{
+ switch (cmd) {
+ case CPU_PM_ENTER_FAILED:
+ case CPU_PM_EXIT:
+ r4k_tlb_configure();
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block r4k_tlb_pm_notifier_block = {
+ .notifier_call = r4k_tlb_pm_notifier,
+};
+
+static int __init r4k_tlb_init_pm(void)
+{
+ return cpu_pm_register_notifier(&r4k_tlb_pm_notifier_block);
+}
+arch_initcall(r4k_tlb_init_pm);
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-12-05 17:56:31 +0000