diff options
Diffstat (limited to 'arch/mips/loongson/common/cs5536/cs5536_isa.c')
| -rw-r--r-- | arch/mips/loongson/common/cs5536/cs5536_isa.c | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c index b6f17f538e4..924be39e773 100644 --- a/arch/mips/loongson/common/cs5536/cs5536_isa.c +++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c @@ -5,14 +5,15 @@ * Author : jlliu, liujl@lemote.com * * Copyright (C) 2009 Lemote, Inc. - * Author: Wu Zhangjin, wuzj@lemote.com + * Author: Wu Zhangjin, wuzhangjin@gmail.com * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ +#include <linux/pci.h> #include <cs5536/cs5536.h> #include <cs5536/cs5536_pci.h> @@ -61,7 +62,7 @@ static void divil_lbar_enable(void) for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) { _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); hi |= 0x01; - _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo); + _wrmsr(DIVIL_MSR_REG(offset), hi, lo); } } @@ -76,7 +77,7 @@ static void divil_lbar_disable(void) for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) { _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); hi &= ~0x01; - _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo); + _wrmsr(DIVIL_MSR_REG(offset), hi, lo); } } @@ -314,3 +315,16 @@ u32 pci_isa_read_reg(int reg) return conf_data; } + +/* + * The mfgpt timer interrupt is running early, so we must keep the south bridge + * mmio always enabled. Otherwise we may race with the PCI configuration which + * may temporarily disable it. When that happens and the timer interrupt fires, + * we are not able to clear it and the system will hang. + */ +static void cs5536_isa_mmio_always_on(struct pci_dev *dev) +{ + dev->mmio_always_on = 1; +} +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, + PCI_CLASS_BRIDGE_ISA, 8, cs5536_isa_mmio_always_on); |