diff options
Diffstat (limited to 'arch/mips/jz4740')
| -rw-r--r-- | arch/mips/jz4740/Kconfig | 3 | ||||
| -rw-r--r-- | arch/mips/jz4740/Makefile | 6 | ||||
| -rw-r--r-- | arch/mips/jz4740/board-qi_lb60.c | 67 | ||||
| -rw-r--r-- | arch/mips/jz4740/clock-debugfs.c | 2 | ||||
| -rw-r--r-- | arch/mips/jz4740/clock.c | 6 | ||||
| -rw-r--r-- | arch/mips/jz4740/dma.c | 289 | ||||
| -rw-r--r-- | arch/mips/jz4740/gpio.c | 225 | ||||
| -rw-r--r-- | arch/mips/jz4740/irq.c | 94 | ||||
| -rw-r--r-- | arch/mips/jz4740/irq.h | 8 | ||||
| -rw-r--r-- | arch/mips/jz4740/platform.c | 112 | ||||
| -rw-r--r-- | arch/mips/jz4740/pm.c | 5 | ||||
| -rw-r--r-- | arch/mips/jz4740/prom.c | 2 | ||||
| -rw-r--r-- | arch/mips/jz4740/pwm.c | 177 | ||||
| -rw-r--r-- | arch/mips/jz4740/reset.c | 51 | ||||
| -rw-r--r-- | arch/mips/jz4740/serial.h | 3 | ||||
| -rw-r--r-- | arch/mips/jz4740/setup.c | 34 | ||||
| -rw-r--r-- | arch/mips/jz4740/time.c | 9 | ||||
| -rw-r--r-- | arch/mips/jz4740/timer.c | 8 | ||||
| -rw-r--r-- | arch/mips/jz4740/timer.h | 136 |
19 files changed, 363 insertions, 874 deletions
diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig index 3e7141f0746..46890305388 100644 --- a/arch/mips/jz4740/Kconfig +++ b/arch/mips/jz4740/Kconfig @@ -7,6 +7,3 @@ config JZ4740_QI_LB60 bool "Qi Hardware Ben NanoNote" endchoice - -config HAVE_PWM - bool diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile index a604eaeb6c0..28e5535dfa9 100644 --- a/arch/mips/jz4740/Makefile +++ b/arch/mips/jz4740/Makefile @@ -4,8 +4,8 @@ # Object file lists. -obj-y += prom.o irq.o time.o reset.o setup.o dma.o \ - gpio.o clock.o platform.o timer.o pwm.o serial.o +obj-y += prom.o irq.o time.o reset.o setup.o \ + gpio.o clock.o platform.o timer.o serial.o obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o @@ -16,5 +16,3 @@ obj-$(CONFIG_JZ4740_QI_LB60) += board-qi_lb60.o # PM support obj-$(CONFIG_PM) += pm.o - -EXTRA_CFLAGS += -Werror -Wall diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index 2c0e107966a..088e92a79ae 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -23,6 +23,7 @@ #include <linux/spi/spi_gpio.h> #include <linux/power_supply.h> #include <linux/power/jz4740-battery.h> +#include <linux/power/gpio-charger.h> #include <asm/mach-jz4740/jz4740_fb.h> #include <asm/mach-jz4740/jz4740_mmc.h> @@ -49,14 +50,14 @@ static bool is_avt2; /* NAND */ static struct nand_ecclayout qi_lb60_ecclayout_1gb = { -/* .eccbytes = 36, + .eccbytes = 36, .eccpos = { - 6, 7, 8, 9, 10, 11, 12, 13, + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41 - },*/ + }, .oobfree = { { .offset = 2, .length = 4 }, { .offset = 42, .length = 22 } @@ -64,7 +65,7 @@ static struct nand_ecclayout qi_lb60_ecclayout_1gb = { }; /* Early prototypes of the QI LB60 had only 1GB of NAND. - * In order to support these devices aswell the partition and ecc layout is + * In order to support these devices as well the partition and ecc layout is * initialized depending on the NAND size */ static struct mtd_partition qi_lb60_partitions_1gb[] = { { @@ -85,7 +86,7 @@ static struct mtd_partition qi_lb60_partitions_1gb[] = { }; static struct nand_ecclayout qi_lb60_ecclayout_2gb = { -/* .eccbytes = 72, + .eccbytes = 72, .eccpos = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, @@ -96,7 +97,7 @@ static struct nand_ecclayout qi_lb60_ecclayout_2gb = { 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83 - },*/ + }, .oobfree = { { .offset = 2, .length = 10 }, { .offset = 84, .length = 44 }, @@ -139,6 +140,7 @@ static void qi_lb60_nand_ident(struct platform_device *pdev, static struct jz_nand_platform_data qi_lb60_nand_pdata = { .ident_callback = qi_lb60_nand_ident, .busy_gpio = 94, + .banks = { 1 }, }; /* Keyboard*/ @@ -208,7 +210,7 @@ static const uint32_t qi_lb60_keymap[] = { KEY(6, 7, KEY_RIGHT), /* S57 */ KEY(7, 0, KEY_LEFTSHIFT), /* S58 */ - KEY(7, 1, KEY_LEFTALT), /* S59 */ + KEY(7, 1, KEY_LEFTALT), /* S59 */ KEY(7, 2, KEY_QI_FN), /* S60 */ }; @@ -315,7 +317,7 @@ static struct spi_board_info qi_lb60_spi_board_info[] = { /* Battery */ static struct jz_battery_platform_data qi_lb60_battery_pdata = { - .gpio_charge = JZ_GPIO_PORTC(27), + .gpio_charge = JZ_GPIO_PORTC(27), .gpio_charge_active_low = 1, .info = { .name = "battery", @@ -342,7 +344,7 @@ static struct gpio_keys_platform_data qi_lb60_gpio_keys_data = { }; static struct platform_device qi_lb60_gpio_keys = { - .name = "gpio-keys", + .name = "gpio-keys", .id = -1, .dev = { .platform_data = &qi_lb60_gpio_keys_data, @@ -396,8 +398,45 @@ static struct platform_device qi_lb60_pwm_beeper = { }, }; +/* charger */ +static char *qi_lb60_batteries[] = { + "battery", +}; + +static struct gpio_charger_platform_data qi_lb60_charger_pdata = { + .name = "usb", + .type = POWER_SUPPLY_TYPE_USB, + .gpio = JZ_GPIO_PORTD(28), + .gpio_active_low = 1, + .supplied_to = qi_lb60_batteries, + .num_supplicants = ARRAY_SIZE(qi_lb60_batteries), +}; + +static struct platform_device qi_lb60_charger_device = { + .name = "gpio-charger", + .dev = { + .platform_data = &qi_lb60_charger_pdata, + }, +}; + +/* audio */ +static struct platform_device qi_lb60_audio_device = { + .name = "qi-lb60-audio", + .id = -1, +}; + +static struct gpiod_lookup_table qi_lb60_audio_gpio_table = { + .dev_id = "qi-lb60-audio", + .table = { + GPIO_LOOKUP("Bank B", 29, "snd", 0), + GPIO_LOOKUP("Bank D", 4, "amp", 0), + { }, + }, +}; + static struct platform_device *jz_platform_devices[] __initdata = { &jz4740_udc_device, + &jz4740_udc_xceiv_device, &jz4740_mmc_device, &jz4740_nand_device, &qi_lb60_keypad, @@ -408,14 +447,18 @@ static struct platform_device *jz_platform_devices[] __initdata = { &jz4740_codec_device, &jz4740_rtc_device, &jz4740_adc_device, + &jz4740_pwm_device, + &jz4740_dma_device, &qi_lb60_gpio_keys, &qi_lb60_pwm_beeper, + &qi_lb60_charger_device, + &qi_lb60_audio_device, }; static void __init board_gpio_setup(void) { /* We only need to enable/disable pullup here for pins used in generic - * drivers. Everything else is done by the drivers themselfs. */ + * drivers. Everything else is done by the drivers themselves. */ jz_gpio_disable_pullup(QI_LB60_GPIO_SD_VCC_EN_N); jz_gpio_disable_pullup(QI_LB60_GPIO_SD_CD); } @@ -427,6 +470,8 @@ static int __init qi_lb60_init_platform_devices(void) jz4740_adc_device.dev.platform_data = &qi_lb60_battery_pdata; jz4740_mmc_device.dev.platform_data = &qi_lb60_mmc_pdata; + gpiod_add_lookup_table(&qi_lb60_audio_gpio_table); + jz4740_serial_device_register(); spi_register_board_info(qi_lb60_spi_board_info, @@ -464,7 +509,7 @@ static int __init qi_lb60_board_setup(void) board_gpio_setup(); if (qi_lb60_init_platform_devices()) - panic("Failed to initialize platform devices\n"); + panic("Failed to initialize platform devices"); return 0; } diff --git a/arch/mips/jz4740/clock-debugfs.c b/arch/mips/jz4740/clock-debugfs.c index 330a0f2bf17..a8acdeff267 100644 --- a/arch/mips/jz4740/clock-debugfs.c +++ b/arch/mips/jz4740/clock-debugfs.c @@ -3,7 +3,7 @@ * JZ4740 SoC clock support debugfs entries * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * diff --git a/arch/mips/jz4740/clock.c b/arch/mips/jz4740/clock.c index 118a8a5562d..1b5f55426ca 100644 --- a/arch/mips/jz4740/clock.c +++ b/arch/mips/jz4740/clock.c @@ -3,7 +3,7 @@ * JZ4740 SoC clock support * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * @@ -31,7 +31,7 @@ #define JZ_REG_CLOCK_LOW_POWER 0x04 #define JZ_REG_CLOCK_PLL 0x10 #define JZ_REG_CLOCK_GATE 0x20 -#define JZ_REG_CLOCK_SLEEP_CTRL 0x24 +#define JZ_REG_CLOCK_SLEEP_CTRL 0x24 #define JZ_REG_CLOCK_I2S 0x60 #define JZ_REG_CLOCK_LCD 0x64 #define JZ_REG_CLOCK_MMC 0x68 @@ -687,7 +687,7 @@ static struct clk jz4740_clock_simple_clks[] = { [3] = { .name = "dma", .parent = &jz_clk_high_speed_peripheral.clk, - .gate_bit = JZ_CLOCK_GATE_UART0, + .gate_bit = JZ_CLOCK_GATE_DMAC, .ops = &jz_clk_simple_ops, }, [4] = { diff --git a/arch/mips/jz4740/dma.c b/arch/mips/jz4740/dma.c deleted file mode 100644 index 5ebe75a6835..00000000000 --- a/arch/mips/jz4740/dma.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> - * JZ4740 SoC DMA support - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/spinlock.h> -#include <linux/interrupt.h> - -#include <linux/dma-mapping.h> -#include <asm/mach-jz4740/dma.h> -#include <asm/mach-jz4740/base.h> - -#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20) -#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20) -#define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20) -#define JZ_REG_DMA_REQ_TYPE(x) (0x0C + (x) * 0x20) -#define JZ_REG_DMA_STATUS_CTRL(x) (0x10 + (x) * 0x20) -#define JZ_REG_DMA_CMD(x) (0x14 + (x) * 0x20) -#define JZ_REG_DMA_DESC_ADDR(x) (0x18 + (x) * 0x20) - -#define JZ_REG_DMA_CTRL 0x300 -#define JZ_REG_DMA_IRQ 0x304 -#define JZ_REG_DMA_DOORBELL 0x308 -#define JZ_REG_DMA_DOORBELL_SET 0x30C - -#define JZ_DMA_STATUS_CTRL_NO_DESC BIT(31) -#define JZ_DMA_STATUS_CTRL_DESC_INV BIT(6) -#define JZ_DMA_STATUS_CTRL_ADDR_ERR BIT(4) -#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE BIT(3) -#define JZ_DMA_STATUS_CTRL_HALT BIT(2) -#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE BIT(1) -#define JZ_DMA_STATUS_CTRL_ENABLE BIT(0) - -#define JZ_DMA_CMD_SRC_INC BIT(23) -#define JZ_DMA_CMD_DST_INC BIT(22) -#define JZ_DMA_CMD_RDIL_MASK (0xf << 16) -#define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14) -#define JZ_DMA_CMD_DST_WIDTH_MASK (0x3 << 12) -#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK (0x7 << 8) -#define JZ_DMA_CMD_BLOCK_MODE BIT(7) -#define JZ_DMA_CMD_DESC_VALID BIT(4) -#define JZ_DMA_CMD_DESC_VALID_MODE BIT(3) -#define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2) -#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1) -#define JZ_DMA_CMD_LINK_ENABLE BIT(0) - -#define JZ_DMA_CMD_FLAGS_OFFSET 22 -#define JZ_DMA_CMD_RDIL_OFFSET 16 -#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14 -#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12 -#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8 -#define JZ_DMA_CMD_MODE_OFFSET 7 - -#define JZ_DMA_CTRL_PRIORITY_MASK (0x3 << 8) -#define JZ_DMA_CTRL_HALT BIT(3) -#define JZ_DMA_CTRL_ADDRESS_ERROR BIT(2) -#define JZ_DMA_CTRL_ENABLE BIT(0) - - -static void __iomem *jz4740_dma_base; -static spinlock_t jz4740_dma_lock; - -static inline uint32_t jz4740_dma_read(size_t reg) -{ - return readl(jz4740_dma_base + reg); -} - -static inline void jz4740_dma_write(size_t reg, uint32_t val) -{ - writel(val, jz4740_dma_base + reg); -} - -static inline void jz4740_dma_write_mask(size_t reg, uint32_t val, uint32_t mask) -{ - uint32_t val2; - val2 = jz4740_dma_read(reg); - val2 &= ~mask; - val2 |= val; - jz4740_dma_write(reg, val2); -} - -struct jz4740_dma_chan { - unsigned int id; - void *dev; - const char *name; - - enum jz4740_dma_flags flags; - uint32_t transfer_shift; - - jz4740_dma_complete_callback_t complete_cb; - - unsigned used:1; -}; - -#define JZ4740_DMA_CHANNEL(_id) { .id = _id } - -struct jz4740_dma_chan jz4740_dma_channels[] = { - JZ4740_DMA_CHANNEL(0), - JZ4740_DMA_CHANNEL(1), - JZ4740_DMA_CHANNEL(2), - JZ4740_DMA_CHANNEL(3), - JZ4740_DMA_CHANNEL(4), - JZ4740_DMA_CHANNEL(5), -}; - -struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name) -{ - unsigned int i; - struct jz4740_dma_chan *dma = NULL; - - spin_lock(&jz4740_dma_lock); - - for (i = 0; i < ARRAY_SIZE(jz4740_dma_channels); ++i) { - if (!jz4740_dma_channels[i].used) { - dma = &jz4740_dma_channels[i]; - dma->used = 1; - break; - } - } - - spin_unlock(&jz4740_dma_lock); - - if (!dma) - return NULL; - - dma->dev = dev; - dma->name = name; - - return dma; -} -EXPORT_SYMBOL_GPL(jz4740_dma_request); - -void jz4740_dma_configure(struct jz4740_dma_chan *dma, - const struct jz4740_dma_config *config) -{ - uint32_t cmd; - - switch (config->transfer_size) { - case JZ4740_DMA_TRANSFER_SIZE_2BYTE: - dma->transfer_shift = 1; - break; - case JZ4740_DMA_TRANSFER_SIZE_4BYTE: - dma->transfer_shift = 2; - break; - case JZ4740_DMA_TRANSFER_SIZE_16BYTE: - dma->transfer_shift = 4; - break; - case JZ4740_DMA_TRANSFER_SIZE_32BYTE: - dma->transfer_shift = 5; - break; - default: - dma->transfer_shift = 0; - break; - } - - cmd = config->flags << JZ_DMA_CMD_FLAGS_OFFSET; - cmd |= config->src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET; - cmd |= config->dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET; - cmd |= config->transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET; - cmd |= config->mode << JZ_DMA_CMD_MODE_OFFSET; - cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE; - - jz4740_dma_write(JZ_REG_DMA_CMD(dma->id), cmd); - jz4740_dma_write(JZ_REG_DMA_STATUS_CTRL(dma->id), 0); - jz4740_dma_write(JZ_REG_DMA_REQ_TYPE(dma->id), config->request_type); -} -EXPORT_SYMBOL_GPL(jz4740_dma_configure); - -void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src) -{ - jz4740_dma_write(JZ_REG_DMA_SRC_ADDR(dma->id), src); -} -EXPORT_SYMBOL_GPL(jz4740_dma_set_src_addr); - -void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst) -{ - jz4740_dma_write(JZ_REG_DMA_DST_ADDR(dma->id), dst); -} -EXPORT_SYMBOL_GPL(jz4740_dma_set_dst_addr); - -void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count) -{ - count >>= dma->transfer_shift; - jz4740_dma_write(JZ_REG_DMA_TRANSFER_COUNT(dma->id), count); -} -EXPORT_SYMBOL_GPL(jz4740_dma_set_transfer_count); - -void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma, - jz4740_dma_complete_callback_t cb) -{ - dma->complete_cb = cb; -} -EXPORT_SYMBOL_GPL(jz4740_dma_set_complete_cb); - -void jz4740_dma_free(struct jz4740_dma_chan *dma) -{ - dma->dev = NULL; - dma->complete_cb = NULL; - dma->used = 0; -} -EXPORT_SYMBOL_GPL(jz4740_dma_free); - -void jz4740_dma_enable(struct jz4740_dma_chan *dma) -{ - jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), - JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE, - JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC | - JZ_DMA_STATUS_CTRL_ENABLE); - - jz4740_dma_write_mask(JZ_REG_DMA_CTRL, - JZ_DMA_CTRL_ENABLE, - JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE); -} -EXPORT_SYMBOL_GPL(jz4740_dma_enable); - -void jz4740_dma_disable(struct jz4740_dma_chan *dma) -{ - jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0, - JZ_DMA_STATUS_CTRL_ENABLE); -} -EXPORT_SYMBOL_GPL(jz4740_dma_disable); - -uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma) -{ - uint32_t residue; - residue = jz4740_dma_read(JZ_REG_DMA_TRANSFER_COUNT(dma->id)); - return residue << dma->transfer_shift; -} -EXPORT_SYMBOL_GPL(jz4740_dma_get_residue); - -static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma) -{ - uint32_t status; - - status = jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id)); - - jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0, - JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE); - - if (dma->complete_cb) - dma->complete_cb(dma, 0, dma->dev); -} - -static irqreturn_t jz4740_dma_irq(int irq, void *dev_id) -{ - uint32_t irq_status; - unsigned int i; - - irq_status = readl(jz4740_dma_base + JZ_REG_DMA_IRQ); - - for (i = 0; i < 6; ++i) { - if (irq_status & (1 << i)) - jz4740_dma_chan_irq(&jz4740_dma_channels[i]); - } - - return IRQ_HANDLED; -} - -static int jz4740_dma_init(void) -{ - unsigned int ret; - - jz4740_dma_base = ioremap(JZ4740_DMAC_BASE_ADDR, 0x400); - - if (!jz4740_dma_base) - return -EBUSY; - - spin_lock_init(&jz4740_dma_lock); - - ret = request_irq(JZ4740_IRQ_DMAC, jz4740_dma_irq, 0, "DMA", NULL); - - if (ret) - printk(KERN_ERR "JZ4740 DMA: Failed to request irq: %d\n", ret); - - return ret; -} -arch_initcall(jz4740_dma_init); diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c index 88e6aeda5bf..00b798d2fb7 100644 --- a/arch/mips/jz4740/gpio.c +++ b/arch/mips/jz4740/gpio.c @@ -3,7 +3,7 @@ * JZ4740 platform GPIO support * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * @@ -17,8 +17,6 @@ #include <linux/module.h> #include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/sysdev.h> #include <linux/io.h> #include <linux/gpio.h> #include <linux/delay.h> @@ -30,6 +28,8 @@ #include <asm/mach-jz4740/base.h> +#include "irq.h" + #define JZ4740_GPIO_BASE_A (32*0) #define JZ4740_GPIO_BASE_B (32*1) #define JZ4740_GPIO_BASE_C (32*2) @@ -77,17 +77,11 @@ struct jz_gpio_chip { unsigned int irq; unsigned int irq_base; - uint32_t wakeup; - uint32_t suspend_mask; uint32_t edge_trigger_both; void __iomem *base; - spinlock_t lock; - struct gpio_chip gpio_chip; - struct irq_chip irq_chip; - struct sys_device sysdev; }; static struct jz_gpio_chip jz4740_gpio_chips[]; @@ -102,9 +96,10 @@ static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *g return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip); } -static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(unsigned int irq) +static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data) { - return get_irq_chip_data(irq); + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); + return gc->private; } static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg) @@ -306,81 +301,54 @@ static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc) { uint32_t flag; unsigned int gpio_irq; - unsigned int gpio_bank; - struct jz_gpio_chip *chip = get_irq_desc_data(desc); - - gpio_bank = JZ4740_IRQ_GPIO0 - irq; + struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc); flag = readl(chip->base + JZ_REG_GPIO_FLAG); - if (!flag) return; - gpio_irq = __fls(flag); + gpio_irq = chip->irq_base + __fls(flag); - jz_gpio_check_trigger_both(chip, irq); - - gpio_irq += (gpio_bank << 5) + JZ4740_IRQ_GPIO(0); + jz_gpio_check_trigger_both(chip, gpio_irq); generic_handle_irq(gpio_irq); }; -static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg) +static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg) { - struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); - writel(IRQ_TO_BIT(irq), chip->base + reg); + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); + writel(IRQ_TO_BIT(data->irq), chip->base + reg); } -static void jz_gpio_irq_mask(unsigned int irq) +static void jz_gpio_irq_unmask(struct irq_data *data) { - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET); -}; + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); -static void jz_gpio_irq_unmask(unsigned int irq) -{ - struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); - - jz_gpio_check_trigger_both(chip, irq); - - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR); + jz_gpio_check_trigger_both(chip, data->irq); + irq_gc_unmask_enable_reg(data); }; /* TODO: Check if function is gpio */ -static unsigned int jz_gpio_irq_startup(unsigned int irq) +static unsigned int jz_gpio_irq_startup(struct irq_data *data) { - struct irq_desc *desc = irq_to_desc(irq); - - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET); - - desc->status &= ~IRQ_MASKED; - jz_gpio_irq_unmask(irq); - + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET); + jz_gpio_irq_unmask(data); return 0; } -static void jz_gpio_irq_shutdown(unsigned int irq) +static void jz_gpio_irq_shutdown(struct irq_data *data) { - struct irq_desc *desc = irq_to_desc(irq); - - jz_gpio_irq_mask(irq); - desc->status |= IRQ_MASKED; + irq_gc_mask_disable_reg(data); /* Set direction to input */ - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR); } -static void jz_gpio_irq_ack(unsigned int irq) +static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) { - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR); -}; - -static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) -{ - struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); - struct irq_desc *desc = irq_to_desc(irq); - - jz_gpio_irq_mask(irq); + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); + unsigned int irq = data->irq; if (flow_type == IRQ_TYPE_EDGE_BOTH) { uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN); @@ -395,51 +363,38 @@ static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) switch (flow_type) { case IRQ_TYPE_EDGE_RISING: - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET); break; case IRQ_TYPE_EDGE_FALLING: - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET); break; case IRQ_TYPE_LEVEL_HIGH: - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR); break; case IRQ_TYPE_LEVEL_LOW: - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); - jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR); break; default: return -EINVAL; } - if (!(desc->status & IRQ_MASKED)) - jz_gpio_irq_unmask(irq); - return 0; } -static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on) +static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on) { - struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); - spin_lock(&chip->lock); - if (on) - chip->wakeup |= IRQ_TO_BIT(irq); - else - chip->wakeup &= ~IRQ_TO_BIT(irq); - spin_unlock(&chip->lock); + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); + + irq_gc_set_wake(data, on); + irq_set_irq_wake(chip->irq, on); - set_irq_wake(chip->irq, on); return 0; } -/* - * This lock class tells lockdep that GPIO irqs are in a different - * category than their parents, so it won't report false recursion. - */ -static struct lock_class_key gpio_lock_class; - #define JZ4740_GPIO_CHIP(_bank) { \ .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \ .gpio_chip = { \ @@ -452,16 +407,6 @@ static struct lock_class_key gpio_lock_class; .base = JZ4740_GPIO_BASE_ ## _bank, \ .ngpio = JZ4740_GPIO_NUM_ ## _bank, \ }, \ - .irq_chip = { \ - .name = "GPIO Bank " # _bank, \ - .mask = jz_gpio_irq_mask, \ - .unmask = jz_gpio_irq_unmask, \ - .ack = jz_gpio_irq_ack, \ - .startup = jz_gpio_irq_startup, \ - .shutdown = jz_gpio_irq_shutdown, \ - .set_type = jz_gpio_irq_set_type, \ - .set_wake = jz_gpio_irq_set_wake, \ - }, \ } static struct jz_gpio_chip jz4740_gpio_chips[] = { @@ -471,77 +416,49 @@ static struct jz_gpio_chip jz4740_gpio_chips[] = { JZ4740_GPIO_CHIP(D), }; -static inline struct jz_gpio_chip *sysdev_to_chip(struct sys_device *dev) -{ - return container_of(dev, struct jz_gpio_chip, sysdev); -} - -static int jz4740_gpio_suspend(struct sys_device *dev, pm_message_t state) -{ - struct jz_gpio_chip *chip = sysdev_to_chip(dev); - - chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK); - writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET); - writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR); - - return 0; -} - -static int jz4740_gpio_resume(struct sys_device *dev) -{ - struct jz_gpio_chip *chip = sysdev_to_chip(dev); - uint32_t mask = chip->suspend_mask; - - writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR); - writel(mask, chip->base + JZ_REG_GPIO_MASK_SET); - - return 0; -} - -static struct sysdev_class jz4740_gpio_sysdev_class = { - .name = "gpio", - .suspend = jz4740_gpio_suspend, - .resume = jz4740_gpio_resume, -}; - -static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id) +static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id) { - int ret, irq; - - chip->sysdev.id = id; - chip->sysdev.cls = &jz4740_gpio_sysdev_class; - ret = sysdev_register(&chip->sysdev); - - if (ret) - return ret; - - spin_lock_init(&chip->lock); + struct irq_chip_generic *gc; + struct irq_chip_type *ct; chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100); - gpiochip_add(&chip->gpio_chip); - chip->irq = JZ4740_IRQ_INTC_GPIO(id); - set_irq_data(chip->irq, chip); - set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler); + irq_set_handler_data(chip->irq, chip); + irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler); + + gc = irq_alloc_generic_chip(chip->gpio_chip.label, 1, chip->irq_base, + chip->base, handle_level_irq); + + gc->wake_enabled = IRQ_MSK(chip->gpio_chip.ngpio); + gc->private = chip; + + ct = gc->chip_types; + ct->regs.enable = JZ_REG_GPIO_MASK_CLEAR; + ct->regs.disable = JZ_REG_GPIO_MASK_SET; + ct->regs.ack = JZ_REG_GPIO_FLAG_CLEAR; + + ct->chip.name = "GPIO"; + ct->chip.irq_mask = irq_gc_mask_disable_reg; + ct->chip.irq_unmask = jz_gpio_irq_unmask; + ct->chip.irq_ack = irq_gc_ack_set_bit; + ct->chip.irq_suspend = jz4740_irq_suspend; + ct->chip.irq_resume = jz4740_irq_resume; + ct->chip.irq_startup = jz_gpio_irq_startup; + ct->chip.irq_shutdown = jz_gpio_irq_shutdown; + ct->chip.irq_set_type = jz_gpio_irq_set_type; + ct->chip.irq_set_wake = jz_gpio_irq_set_wake; + ct->chip.flags = IRQCHIP_SET_TYPE_MASKED; + + irq_setup_generic_chip(gc, IRQ_MSK(chip->gpio_chip.ngpio), + IRQ_GC_INIT_NESTED_LOCK, 0, IRQ_NOPROBE | IRQ_LEVEL); - for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) { - lockdep_set_class(&irq_desc[irq].lock, &gpio_lock_class); - set_irq_chip_data(irq, chip); - set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq); - } - - return 0; + gpiochip_add(&chip->gpio_chip); } static int __init jz4740_gpio_init(void) { unsigned int i; - int ret; - - ret = sysdev_class_register(&jz4740_gpio_sysdev_class); - if (ret) - return ret; for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i) jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i); diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c index 7d33ff83580..2531da1d3ad 100644 --- a/arch/mips/jz4740/irq.c +++ b/arch/mips/jz4740/irq.c @@ -3,7 +3,7 @@ * JZ4740 platform IRQ support * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * @@ -32,8 +32,6 @@ #include <asm/mach-jz4740/base.h> static void __iomem *jz_intc_base; -static uint32_t jz_intc_wakeup; -static uint32_t jz_intc_saved; #define JZ_REG_INTC_STATUS 0x00 #define JZ_REG_INTC_MASK 0x04 @@ -41,36 +39,6 @@ static uint32_t jz_intc_saved; #define JZ_REG_INTC_CLEAR_MASK 0x0c #define JZ_REG_INTC_PENDING 0x10 -#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE) - -static void intc_irq_unmask(unsigned int irq) -{ - writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK); -} - -static void intc_irq_mask(unsigned int irq) -{ - writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK); -} - -static int intc_irq_set_wake(unsigned int irq, unsigned int on) -{ - if (on) - jz_intc_wakeup |= IRQ_BIT(irq); - else - jz_intc_wakeup &= ~IRQ_BIT(irq); - - return 0; -} - -static struct irq_chip intc_irq_type = { - .name = "INTC", - .mask = intc_irq_mask, - .mask_ack = intc_irq_mask, - .unmask = intc_irq_unmask, - .set_wake = intc_irq_set_wake, -}; - static irqreturn_t jz4740_cascade(int irq, void *data) { uint32_t irq_reg; @@ -83,6 +51,26 @@ static irqreturn_t jz4740_cascade(int irq, void *data) return IRQ_HANDLED; } +static void jz4740_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask) +{ + struct irq_chip_regs *regs = &gc->chip_types->regs; + + writel(mask, gc->reg_base + regs->enable); + writel(~mask, gc->reg_base + regs->disable); +} + +void jz4740_irq_suspend(struct irq_data *data) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); + jz4740_irq_set_mask(gc, gc->wake_active); +} + +void jz4740_irq_resume(struct irq_data *data) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); + jz4740_irq_set_mask(gc, gc->mask_cache); +} + static struct irqaction jz4740_cascade_action = { .handler = jz4740_cascade, .name = "JZ4740 cascade interrupt", @@ -90,15 +78,32 @@ static struct irqaction jz4740_cascade_action = { void __init arch_init_irq(void) { - int i; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + mips_cpu_irq_init(); jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14); - for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) { - intc_irq_mask(i); - set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq); - } + /* Mask all irqs */ + writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK); + + gc = irq_alloc_generic_chip("INTC", 1, JZ4740_IRQ_BASE, jz_intc_base, + handle_level_irq); + + gc->wake_enabled = IRQ_MSK(32); + + ct = gc->chip_types; + ct->regs.enable = JZ_REG_INTC_CLEAR_MASK; + ct->regs.disable = JZ_REG_INTC_SET_MASK; + ct->chip.irq_unmask = irq_gc_unmask_enable_reg; + ct->chip.irq_mask = irq_gc_mask_disable_reg; + ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; + ct->chip.irq_set_wake = irq_gc_set_wake; + ct->chip.irq_suspend = jz4740_irq_suspend; + ct->chip.irq_resume = jz4740_irq_resume; + + irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL); setup_irq(2, &jz4740_cascade_action); } @@ -114,19 +119,6 @@ asmlinkage void plat_irq_dispatch(void) spurious_interrupt(); } -void jz4740_intc_suspend(void) -{ - jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK); - writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK); - writel(jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_CLEAR_MASK); -} - -void jz4740_intc_resume(void) -{ - writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK); - writel(jz_intc_saved, jz_intc_base + JZ_REG_INTC_SET_MASK); -} - #ifdef CONFIG_DEBUG_FS static inline void intc_seq_reg(struct seq_file *s, const char *name, diff --git a/arch/mips/jz4740/irq.h b/arch/mips/jz4740/irq.h index 56b5eadd1fa..0f48720b5b6 100644 --- a/arch/mips/jz4740/irq.h +++ b/arch/mips/jz4740/irq.h @@ -2,7 +2,7 @@ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * @@ -15,7 +15,9 @@ #ifndef __MIPS_JZ4740_IRQ_H__ #define __MIPS_JZ4740_IRQ_H__ -extern void jz4740_intc_suspend(void); -extern void jz4740_intc_resume(void); +#include <linux/irq.h> + +extern void jz4740_irq_suspend(struct irq_data *data); +extern void jz4740_irq_resume(struct irq_data *data); #endif diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c index 1cc9e544d16..a447101cf9f 100644 --- a/arch/mips/jz4740/platform.c +++ b/arch/mips/jz4740/platform.c @@ -3,7 +3,7 @@ * JZ4740 platform devices * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * @@ -14,13 +14,14 @@ */ #include <linux/device.h> -#include <linux/init.h> #include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/resource.h> #include <linux/dma-mapping.h> +#include <linux/usb/musb.h> + #include <asm/mach-jz4740/platform.h> #include <asm/mach-jz4740/base.h> #include <asm/mach-jz4740/irq.h> @@ -56,29 +57,35 @@ struct platform_device jz4740_usb_ohci_device = { .resource = jz4740_usb_ohci_resources, }; -/* UDC (USB gadget controller) */ -static struct resource jz4740_usb_gdt_resources[] = { - { - .start = JZ4740_UDC_BASE_ADDR, - .end = JZ4740_UDC_BASE_ADDR + 0x1000 - 1, - .flags = IORESOURCE_MEM, +/* USB Device Controller */ +struct platform_device jz4740_udc_xceiv_device = { + .name = "usb_phy_gen_xceiv", + .id = 0, +}; + +static struct resource jz4740_udc_resources[] = { + [0] = { + .start = JZ4740_UDC_BASE_ADDR, + .end = JZ4740_UDC_BASE_ADDR + 0x10000 - 1, + .flags = IORESOURCE_MEM, }, - { - .start = JZ4740_IRQ_UDC, - .end = JZ4740_IRQ_UDC, - .flags = IORESOURCE_IRQ, + [1] = { + .start = JZ4740_IRQ_UDC, + .end = JZ4740_IRQ_UDC, + .flags = IORESOURCE_IRQ, + .name = "mc", }, }; struct platform_device jz4740_udc_device = { - .name = "jz-udc", - .id = -1, - .dev = { - .dma_mask = &jz4740_udc_device.dev.coherent_dma_mask, + .name = "musb-jz4740", + .id = -1, + .dev = { + .dma_mask = &jz4740_udc_device.dev.coherent_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, - .num_resources = ARRAY_SIZE(jz4740_usb_gdt_resources), - .resource = jz4740_usb_gdt_resources, + .num_resources = ARRAY_SIZE(jz4740_udc_resources), + .resource = jz4740_udc_resources, }; /* MMC/SD controller */ @@ -102,7 +109,7 @@ struct platform_device jz4740_mmc_device = { .dma_mask = &jz4740_mmc_device.dev.coherent_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, - .num_resources = ARRAY_SIZE(jz4740_mmc_resources), + .num_resources = ARRAY_SIZE(jz4740_mmc_resources), .resource = jz4740_mmc_resources, }; @@ -114,7 +121,7 @@ static struct resource jz4740_rtc_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = JZ4740_IRQ_RTC, + .start = JZ4740_IRQ_RTC, .end = JZ4740_IRQ_RTC, .flags = IORESOURCE_IRQ, }, @@ -144,7 +151,7 @@ static struct resource jz4740_i2c_resources[] = { struct platform_device jz4740_i2c_device = { .name = "jz4740-i2c", .id = 0, - .num_resources = ARRAY_SIZE(jz4740_i2c_resources), + .num_resources = ARRAY_SIZE(jz4740_i2c_resources), .resource = jz4740_i2c_resources, }; @@ -157,11 +164,29 @@ static struct resource jz4740_nand_resources[] = { .flags = IORESOURCE_MEM, }, { - .name = "bank", + .name = "bank1", .start = 0x18000000, .end = 0x180C0000 - 1, .flags = IORESOURCE_MEM, }, + { + .name = "bank2", + .start = 0x14000000, + .end = 0x140C0000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "bank3", + .start = 0x0C000000, + .end = 0x0C0C0000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "bank4", + .start = 0x08000000, + .end = 0x080C0000 - 1, + .flags = IORESOURCE_MEM, + }, }; struct platform_device jz4740_nand_device = { @@ -289,3 +314,46 @@ void jz4740_serial_device_register(void) platform_device_register(&jz4740_uart_device); } + +/* Watchdog */ +static struct resource jz4740_wdt_resources[] = { + { + .start = JZ4740_WDT_BASE_ADDR, + .end = JZ4740_WDT_BASE_ADDR + 0x10 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device jz4740_wdt_device = { + .name = "jz4740-wdt", + .id = -1, + .num_resources = ARRAY_SIZE(jz4740_wdt_resources), + .resource = jz4740_wdt_resources, +}; + +/* PWM */ +struct platform_device jz4740_pwm_device = { + .name = "jz4740-pwm", + .id = -1, +}; + +/* DMA */ +static struct resource jz4740_dma_resources[] = { + { + .start = JZ4740_DMAC_BASE_ADDR, + .end = JZ4740_DMAC_BASE_ADDR + 0x400 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = JZ4740_IRQ_DMAC, + .end = JZ4740_IRQ_DMAC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device jz4740_dma_device = { + .name = "jz4740-dma", + .id = -1, + .num_resources = ARRAY_SIZE(jz4740_dma_resources), + .resource = jz4740_dma_resources, +}; diff --git a/arch/mips/jz4740/pm.c b/arch/mips/jz4740/pm.c index 902d5b50124..d8e21301016 100644 --- a/arch/mips/jz4740/pm.c +++ b/arch/mips/jz4740/pm.c @@ -3,7 +3,7 @@ * JZ4740 SoC power management support * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * @@ -21,11 +21,9 @@ #include <asm/mach-jz4740/clock.h> #include "clock.h" -#include "irq.h" static int jz4740_pm_enter(suspend_state_t state) { - jz4740_intc_suspend(); jz4740_clock_suspend(); jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_SLEEP); @@ -37,7 +35,6 @@ static int jz4740_pm_enter(suspend_state_t state) jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_IDLE); jz4740_clock_resume(); - jz4740_intc_resume(); return 0; } diff --git a/arch/mips/jz4740/prom.c b/arch/mips/jz4740/prom.c index 4a70407f55b..5a93f381590 100644 --- a/arch/mips/jz4740/prom.c +++ b/arch/mips/jz4740/prom.c @@ -3,7 +3,7 @@ * JZ4740 SoC prom code * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * diff --git a/arch/mips/jz4740/pwm.c b/arch/mips/jz4740/pwm.c deleted file mode 100644 index a26a6faec9a..00000000000 --- a/arch/mips/jz4740/pwm.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> - * JZ4740 platform PWM support - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#include <linux/kernel.h> - -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/pwm.h> -#include <linux/gpio.h> - -#include <asm/mach-jz4740/gpio.h> -#include "timer.h" - -static struct clk *jz4740_pwm_clk; - -DEFINE_MUTEX(jz4740_pwm_mutex); - -struct pwm_device { - unsigned int id; - unsigned int gpio; - bool used; -}; - -static struct pwm_device jz4740_pwm_list[] = { - { 2, JZ_GPIO_PWM2, false }, - { 3, JZ_GPIO_PWM3, false }, - { 4, JZ_GPIO_PWM4, false }, - { 5, JZ_GPIO_PWM5, false }, - { 6, JZ_GPIO_PWM6, false }, - { 7, JZ_GPIO_PWM7, false }, -}; - -struct pwm_device *pwm_request(int id, const char *label) -{ - int ret = 0; - struct pwm_device *pwm; - - if (id < 2 || id > 7 || !jz4740_pwm_clk) - return ERR_PTR(-ENODEV); - - mutex_lock(&jz4740_pwm_mutex); - - pwm = &jz4740_pwm_list[id - 2]; - if (pwm->used) - ret = -EBUSY; - else - pwm->used = true; - - mutex_unlock(&jz4740_pwm_mutex); - - if (ret) - return ERR_PTR(ret); - - ret = gpio_request(pwm->gpio, label); - - if (ret) { - printk(KERN_ERR "Failed to request pwm gpio: %d\n", ret); - pwm->used = false; - return ERR_PTR(ret); - } - - jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_PWM); - - jz4740_timer_start(id); - - return pwm; -} - -void pwm_free(struct pwm_device *pwm) -{ - pwm_disable(pwm); - jz4740_timer_set_ctrl(pwm->id, 0); - - jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_NONE); - gpio_free(pwm->gpio); - - jz4740_timer_stop(pwm->id); - - pwm->used = false; -} - -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) -{ - unsigned long long tmp; - unsigned long period, duty; - unsigned int prescaler = 0; - unsigned int id = pwm->id; - uint16_t ctrl; - bool is_enabled; - - if (duty_ns < 0 || duty_ns > period_ns) - return -EINVAL; - - tmp = (unsigned long long)clk_get_rate(jz4740_pwm_clk) * period_ns; - do_div(tmp, 1000000000); - period = tmp; - - while (period > 0xffff && prescaler < 6) { - period >>= 2; - ++prescaler; - } - - if (prescaler == 6) - return -EINVAL; - - tmp = (unsigned long long)period * duty_ns; - do_div(tmp, period_ns); - duty = period - tmp; - - if (duty >= period) - duty = period - 1; - - is_enabled = jz4740_timer_is_enabled(id); - if (is_enabled) - pwm_disable(pwm); - - jz4740_timer_set_count(id, 0); - jz4740_timer_set_duty(id, duty); - jz4740_timer_set_period(id, period); - - ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT | - JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN; - - jz4740_timer_set_ctrl(id, ctrl); - - if (is_enabled) - pwm_enable(pwm); - - return 0; -} - -int pwm_enable(struct pwm_device *pwm) -{ - uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id); - - ctrl |= JZ_TIMER_CTRL_PWM_ENABLE; - jz4740_timer_set_ctrl(pwm->id, ctrl); - jz4740_timer_enable(pwm->id); - - return 0; -} - -void pwm_disable(struct pwm_device *pwm) -{ - uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id); - - ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE; - jz4740_timer_disable(pwm->id); - jz4740_timer_set_ctrl(pwm->id, ctrl); -} - -static int __init jz4740_pwm_init(void) -{ - int ret = 0; - - jz4740_pwm_clk = clk_get(NULL, "ext"); - - if (IS_ERR(jz4740_pwm_clk)) { - ret = PTR_ERR(jz4740_pwm_clk); - jz4740_pwm_clk = NULL; - } - - return ret; -} -subsys_initcall(jz4740_pwm_init); diff --git a/arch/mips/jz4740/reset.c b/arch/mips/jz4740/reset.c index 5f1fb95c0d0..b6c6343d283 100644 --- a/arch/mips/jz4740/reset.c +++ b/arch/mips/jz4740/reset.c @@ -2,7 +2,7 @@ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * @@ -21,6 +21,9 @@ #include <asm/mach-jz4740/base.h> #include <asm/mach-jz4740/timer.h> +#include "reset.h" +#include "clock.h" + static void jz4740_halt(void) { while (1) { @@ -53,21 +56,57 @@ static void jz4740_restart(char *command) jz4740_halt(); } -#define JZ_REG_RTC_CTRL 0x00 -#define JZ_REG_RTC_HIBERNATE 0x20 +#define JZ_REG_RTC_CTRL 0x00 +#define JZ_REG_RTC_HIBERNATE 0x20 +#define JZ_REG_RTC_WAKEUP_FILTER 0x24 +#define JZ_REG_RTC_RESET_COUNTER 0x28 -#define JZ_RTC_CTRL_WRDY BIT(7) +#define JZ_RTC_CTRL_WRDY BIT(7) +#define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0 +#define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0 -static void jz4740_power_off(void) +static inline void jz4740_rtc_wait_ready(void __iomem *rtc_base) { - void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x24); uint32_t ctrl; do { ctrl = readl(rtc_base + JZ_REG_RTC_CTRL); } while (!(ctrl & JZ_RTC_CTRL_WRDY)); +} +static void jz4740_power_off(void) +{ + void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x38); + unsigned long wakeup_filter_ticks; + unsigned long reset_counter_ticks; + + /* + * Set minimum wakeup pin assertion time: 100 ms. + * Range is 0 to 2 sec if RTC is clocked at 32 kHz. + */ + wakeup_filter_ticks = (100 * jz4740_clock_bdata.rtc_rate) / 1000; + if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK) + wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK; + else + wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK; + jz4740_rtc_wait_ready(rtc_base); + writel(wakeup_filter_ticks, rtc_base + JZ_REG_RTC_WAKEUP_FILTER); + + /* + * Set reset pin low-level assertion time after wakeup: 60 ms. + * Range is 0 to 125 ms if RTC is clocked at 32 kHz. + */ + reset_counter_ticks = (60 * jz4740_clock_bdata.rtc_rate) / 1000; + if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK) + reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK; + else + reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK; + jz4740_rtc_wait_ready(rtc_base); + writel(reset_counter_ticks, rtc_base + JZ_REG_RTC_RESET_COUNTER); + + jz4740_rtc_wait_ready(rtc_base); writel(1, rtc_base + JZ_REG_RTC_HIBERNATE); + jz4740_halt(); } diff --git a/arch/mips/jz4740/serial.h b/arch/mips/jz4740/serial.h index b9fe3ade028..8eb715bb1ea 100644 --- a/arch/mips/jz4740/serial.h +++ b/arch/mips/jz4740/serial.h @@ -14,6 +14,9 @@ */ #ifndef __MIPS_JZ4740_SERIAL_H__ +#define __MIPS_JZ4740_SERIAL_H__ + +struct uart_port; void jz4740_serial_out(struct uart_port *p, int offset, int value); diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c index 6a9e14dab91..76eafcb79c8 100644 --- a/arch/mips/jz4740/setup.c +++ b/arch/mips/jz4740/setup.c @@ -1,9 +1,10 @@ /* * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> + * Copyright (C) 2011, Maarten ter Huurne <maarten@treewalker.org> * JZ4740 setup code * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * @@ -14,13 +15,44 @@ */ #include <linux/init.h> +#include <linux/io.h> #include <linux/kernel.h> +#include <asm/bootinfo.h> + +#include <asm/mach-jz4740/base.h> + #include "reset.h" + +#define JZ4740_EMC_SDRAM_CTRL 0x80 + + +static void __init jz4740_detect_mem(void) +{ + void __iomem *jz_emc_base; + u32 ctrl, bus, bank, rows, cols; + phys_t size; + + jz_emc_base = ioremap(JZ4740_EMC_BASE_ADDR, 0x100); + ctrl = readl(jz_emc_base + JZ4740_EMC_SDRAM_CTRL); + bus = 2 - ((ctrl >> 31) & 1); + bank = 1 + ((ctrl >> 19) & 1); + cols = 8 + ((ctrl >> 26) & 7); + rows = 11 + ((ctrl >> 20) & 3); + printk(KERN_DEBUG + "SDRAM preconfigured: bus:%u bank:%u rows:%u cols:%u\n", + bus, bank, rows, cols); + iounmap(jz_emc_base); + + size = 1 << (bus + bank + cols + rows); + add_memory_region(0, size, BOOT_MEM_RAM); +} + void __init plat_mem_setup(void) { jz4740_reset_init(); + jz4740_detect_mem(); } const char *get_system_type(void) diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c index fe01678d94f..5e430ce9ac7 100644 --- a/arch/mips/jz4740/time.c +++ b/arch/mips/jz4740/time.c @@ -3,7 +3,7 @@ * JZ4740 platform time support * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * @@ -20,10 +20,10 @@ #include <linux/clockchips.h> #include <asm/mach-jz4740/irq.h> +#include <asm/mach-jz4740/timer.h> #include <asm/time.h> #include "clock.h" -#include "timer.h" #define TIMER_CLOCKEVENT 0 #define TIMER_CLOCKSOURCE 1 @@ -89,7 +89,7 @@ static int jz4740_clockevent_set_next(unsigned long evt, static struct clock_event_device jz4740_clockevent = { .name = "jz4740-timer", - .features = CLOCK_EVT_FEAT_PERIODIC, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .set_next_event = jz4740_clockevent_set_next, .set_mode = jz4740_clockevent_set_mode, .rating = 200, @@ -121,8 +121,7 @@ void __init plat_time_init(void) clockevents_register_device(&jz4740_clockevent); - clocksource_set_clock(&jz4740_clocksource, clk_rate); - ret = clocksource_register(&jz4740_clocksource); + ret = clocksource_register_hz(&jz4740_clocksource, clk_rate); if (ret) printk(KERN_ERR "Failed to register clocksource: %d\n", ret); diff --git a/arch/mips/jz4740/timer.c b/arch/mips/jz4740/timer.c index b2c01512905..4992461787a 100644 --- a/arch/mips/jz4740/timer.c +++ b/arch/mips/jz4740/timer.c @@ -3,7 +3,7 @@ * JZ4740 platform timer support * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * @@ -17,21 +17,23 @@ #include <linux/kernel.h> #include <linux/module.h> -#include "timer.h" - #include <asm/mach-jz4740/base.h> +#include <asm/mach-jz4740/timer.h> void __iomem *jz4740_timer_base; +EXPORT_SYMBOL_GPL(jz4740_timer_base); void jz4740_timer_enable_watchdog(void) { writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); } +EXPORT_SYMBOL_GPL(jz4740_timer_enable_watchdog); void jz4740_timer_disable_watchdog(void) { writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); } +EXPORT_SYMBOL_GPL(jz4740_timer_disable_watchdog); void __init jz4740_timer_init(void) { diff --git a/arch/mips/jz4740/timer.h b/arch/mips/jz4740/timer.h deleted file mode 100644 index fca3994f2e6..00000000000 --- a/arch/mips/jz4740/timer.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> - * JZ4740 platform timer support - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef __MIPS_JZ4740_TIMER_H__ -#define __MIPS_JZ4740_TIMER_H__ - -#include <linux/module.h> -#include <linux/io.h> - -#define JZ_REG_TIMER_STOP 0x0C -#define JZ_REG_TIMER_STOP_SET 0x1C -#define JZ_REG_TIMER_STOP_CLEAR 0x2C -#define JZ_REG_TIMER_ENABLE 0x00 -#define JZ_REG_TIMER_ENABLE_SET 0x04 -#define JZ_REG_TIMER_ENABLE_CLEAR 0x08 -#define JZ_REG_TIMER_FLAG 0x10 -#define JZ_REG_TIMER_FLAG_SET 0x14 -#define JZ_REG_TIMER_FLAG_CLEAR 0x18 -#define JZ_REG_TIMER_MASK 0x20 -#define JZ_REG_TIMER_MASK_SET 0x24 -#define JZ_REG_TIMER_MASK_CLEAR 0x28 - -#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30) -#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34) -#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38) -#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C) - -#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10) -#define JZ_TIMER_IRQ_FULL(x) BIT(x) - -#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9) -#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8) -#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7) -#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c -#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3 -#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3) -#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3) -#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3) -#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3) -#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3) -#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3) - -#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET) - -#define JZ_TIMER_CTRL_SRC_EXT BIT(2) -#define JZ_TIMER_CTRL_SRC_RTC BIT(1) -#define JZ_TIMER_CTRL_SRC_PCLK BIT(0) - -extern void __iomem *jz4740_timer_base; -void __init jz4740_timer_init(void); - -static inline void jz4740_timer_stop(unsigned int timer) -{ - writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); -} - -static inline void jz4740_timer_start(unsigned int timer) -{ - writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); -} - -static inline bool jz4740_timer_is_enabled(unsigned int timer) -{ - return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer); -} - -static inline void jz4740_timer_enable(unsigned int timer) -{ - writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET); -} - -static inline void jz4740_timer_disable(unsigned int timer) -{ - writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR); -} - - -static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period) -{ - writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer)); -} - -static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty) -{ - writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer)); -} - -static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count) -{ - writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer)); -} - -static inline uint16_t jz4740_timer_get_count(unsigned int timer) -{ - return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer)); -} - -static inline void jz4740_timer_ack_full(unsigned int timer) -{ - writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); -} - -static inline void jz4740_timer_irq_full_enable(unsigned int timer) -{ - writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); - writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR); -} - -static inline void jz4740_timer_irq_full_disable(unsigned int timer) -{ - writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET); -} - -static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl) -{ - writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer)); -} - -static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer) -{ - return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer)); -} - -#endif |