diff options
Diffstat (limited to 'arch/mips/include')
485 files changed, 18952 insertions, 14435 deletions
diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild index 9b54b7a403d..05439187891 100644 --- a/arch/mips/include/asm/Kbuild +++ b/arch/mips/include/asm/Kbuild @@ -1,2 +1,18 @@ # MIPS headers +generic-y += cputime.h +generic-y += current.h +generic-y += emergency-restart.h +generic-y += hash.h +generic-y += local64.h +generic-y += mcs_spinlock.h +generic-y += mutex.h +generic-y += parport.h +generic-y += percpu.h +generic-y += preempt.h +generic-y += scatterlist.h +generic-y += sections.h +generic-y += segment.h +generic-y += serial.h generic-y += trace_clock.h +generic-y += ucontext.h +generic-y += xor.h diff --git a/arch/mips/include/asm/abi.h b/arch/mips/include/asm/abi.h index 9252d9b50e5..909bb698486 100644 --- a/arch/mips/include/asm/abi.h +++ b/arch/mips/include/asm/abi.h @@ -14,12 +14,12 @@ struct mips_abi { int (* const setup_frame)(void *sig_return, struct k_sigaction *ka, - struct pt_regs *regs, int signr, - sigset_t *set); + struct pt_regs *regs, int signr, + sigset_t *set); const unsigned long signal_return_offset; int (* const setup_rt_frame)(void *sig_return, struct k_sigaction *ka, - struct pt_regs *regs, int signr, - sigset_t *set, siginfo_t *info); + struct pt_regs *regs, int signr, + sigset_t *set, siginfo_t *info); const unsigned long rt_signal_return_offset; const unsigned long restart; }; diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 569f80aacbd..3f745459fdb 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -51,7 +51,7 @@ * Returns the physical address of a CKSEGx / XKPHYS address */ #define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) -#define XPHYSADDR(a) ((_ACAST64_(a)) & \ +#define XPHYSADDR(a) ((_ACAST64_(a)) & \ _CONST64_(0x000000ffffffffff)) #ifdef CONFIG_64BIT diff --git a/arch/mips/include/asm/amon.h b/arch/mips/include/asm/amon.h index c3dc1a68dd8..3cc03c64a9c 100644 --- a/arch/mips/include/asm/amon.h +++ b/arch/mips/include/asm/amon.h @@ -1,7 +1,12 @@ /* - * Amon support + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2013 Imagination Technologies Ltd. + * + * Arbitrary Monitor Support (AMON) */ - -int amon_cpu_avail(int); -void amon_cpu_start(int, unsigned long, unsigned long, - unsigned long, unsigned long); +int amon_cpu_avail(int cpu); +int amon_cpu_start(int cpu, unsigned long pc, unsigned long sp, + unsigned long gp, unsigned long a0); diff --git a/arch/mips/include/asm/asm-eva.h b/arch/mips/include/asm/asm-eva.h new file mode 100644 index 00000000000..e41c56e375b --- /dev/null +++ b/arch/mips/include/asm/asm-eva.h @@ -0,0 +1,135 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2014 Imagination Technologies Ltd. + * + */ + +#ifndef __ASM_ASM_EVA_H +#define __ASM_ASM_EVA_H + +#ifndef __ASSEMBLY__ +#ifdef CONFIG_EVA + +#define __BUILD_EVA_INSN(insn, reg, addr) \ + " .set push\n" \ + " .set mips0\n" \ + " .set eva\n" \ + " "insn" "reg", "addr "\n" \ + " .set pop\n" + +#define user_cache(op, base) __BUILD_EVA_INSN("cachee", op, base) +#define user_ll(reg, addr) __BUILD_EVA_INSN("lle", reg, addr) +#define user_sc(reg, addr) __BUILD_EVA_INSN("sce", reg, addr) +#define user_lw(reg, addr) __BUILD_EVA_INSN("lwe", reg, addr) +#define user_lwl(reg, addr) __BUILD_EVA_INSN("lwle", reg, addr) +#define user_lwr(reg, addr) __BUILD_EVA_INSN("lwre", reg, addr) +#define user_lh(reg, addr) __BUILD_EVA_INSN("lhe", reg, addr) +#define user_lb(reg, addr) __BUILD_EVA_INSN("lbe", reg, addr) +#define user_lbu(reg, addr) __BUILD_EVA_INSN("lbue", reg, addr) +/* No 64-bit EVA instruction for loading double words */ +#define user_ld(reg, addr) user_lw(reg, addr) +#define user_sw(reg, addr) __BUILD_EVA_INSN("swe", reg, addr) +#define user_swl(reg, addr) __BUILD_EVA_INSN("swle", reg, addr) +#define user_swr(reg, addr) __BUILD_EVA_INSN("swre", reg, addr) +#define user_sh(reg, addr) __BUILD_EVA_INSN("she", reg, addr) +#define user_sb(reg, addr) __BUILD_EVA_INSN("sbe", reg, addr) +/* No 64-bit EVA instruction for storing double words */ +#define user_sd(reg, addr) user_sw(reg, addr) + +#else + +#define user_cache(op, base) "cache " op ", " base "\n" +#define user_ll(reg, addr) "ll " reg ", " addr "\n" +#define user_sc(reg, addr) "sc " reg ", " addr "\n" +#define user_lw(reg, addr) "lw " reg ", " addr "\n" +#define user_lwl(reg, addr) "lwl " reg ", " addr "\n" +#define user_lwr(reg, addr) "lwr " reg ", " addr "\n" +#define user_lh(reg, addr) "lh " reg ", " addr "\n" +#define user_lb(reg, addr) "lb " reg ", " addr "\n" +#define user_lbu(reg, addr) "lbu " reg ", " addr "\n" +#define user_sw(reg, addr) "sw " reg ", " addr "\n" +#define user_swl(reg, addr) "swl " reg ", " addr "\n" +#define user_swr(reg, addr) "swr " reg ", " addr "\n" +#define user_sh(reg, addr) "sh " reg ", " addr "\n" +#define user_sb(reg, addr) "sb " reg ", " addr "\n" + +#ifdef CONFIG_32BIT +/* + * No 'sd' or 'ld' instructions in 32-bit but the code will + * do the correct thing + */ +#define user_sd(reg, addr) user_sw(reg, addr) +#define user_ld(reg, addr) user_lw(reg, addr) +#else +#define user_sd(reg, addr) "sd " reg", " addr "\n" +#define user_ld(reg, addr) "ld " reg", " addr "\n" +#endif /* CONFIG_32BIT */ + +#endif /* CONFIG_EVA */ + +#else /* __ASSEMBLY__ */ + +#ifdef CONFIG_EVA + +#define __BUILD_EVA_INSN(insn, reg, addr) \ + .set push; \ + .set mips0; \ + .set eva; \ + insn reg, addr; \ + .set pop; + +#define user_cache(op, base) __BUILD_EVA_INSN(cachee, op, base) +#define user_ll(reg, addr) __BUILD_EVA_INSN(lle, reg, addr) +#define user_sc(reg, addr) __BUILD_EVA_INSN(sce, reg, addr) +#define user_lw(reg, addr) __BUILD_EVA_INSN(lwe, reg, addr) +#define user_lwl(reg, addr) __BUILD_EVA_INSN(lwle, reg, addr) +#define user_lwr(reg, addr) __BUILD_EVA_INSN(lwre, reg, addr) +#define user_lh(reg, addr) __BUILD_EVA_INSN(lhe, reg, addr) +#define user_lb(reg, addr) __BUILD_EVA_INSN(lbe, reg, addr) +#define user_lbu(reg, addr) __BUILD_EVA_INSN(lbue, reg, addr) +/* No 64-bit EVA instruction for loading double words */ +#define user_ld(reg, addr) user_lw(reg, addr) +#define user_sw(reg, addr) __BUILD_EVA_INSN(swe, reg, addr) +#define user_swl(reg, addr) __BUILD_EVA_INSN(swle, reg, addr) +#define user_swr(reg, addr) __BUILD_EVA_INSN(swre, reg, addr) +#define user_sh(reg, addr) __BUILD_EVA_INSN(she, reg, addr) +#define user_sb(reg, addr) __BUILD_EVA_INSN(sbe, reg, addr) +/* No 64-bit EVA instruction for loading double words */ +#define user_sd(reg, addr) user_sw(reg, addr) +#else + +#define user_cache(op, base) cache op, base +#define user_ll(reg, addr) ll reg, addr +#define user_sc(reg, addr) sc reg, addr +#define user_lw(reg, addr) lw reg, addr +#define user_lwl(reg, addr) lwl reg, addr +#define user_lwr(reg, addr) lwr reg, addr +#define user_lh(reg, addr) lh reg, addr +#define user_lb(reg, addr) lb reg, addr +#define user_lbu(reg, addr) lbu reg, addr +#define user_sw(reg, addr) sw reg, addr +#define user_swl(reg, addr) swl reg, addr +#define user_swr(reg, addr) swr reg, addr +#define user_sh(reg, addr) sh reg, addr +#define user_sb(reg, addr) sb reg, addr + +#ifdef CONFIG_32BIT +/* + * No 'sd' or 'ld' instructions in 32-bit but the code will + * do the correct thing + */ +#define user_sd(reg, addr) user_sw(reg, addr) +#define user_ld(reg, addr) user_lw(reg, addr) +#else +#define user_sd(reg, addr) sd reg, addr +#define user_ld(reg, addr) ld reg, addr +#endif /* CONFIG_32BIT */ + +#endif /* CONFIG_EVA */ + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ASM_EVA_H */ diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index 608cfcfbb3e..7c26b28bf25 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -18,6 +18,7 @@ #define __ASM_ASM_H #include <asm/sgidefs.h> +#include <asm/asm-eva.h> #ifndef CAT #ifdef __STDC__ @@ -33,12 +34,12 @@ * Not used for the kernel but here seems to be the right place. */ #ifdef __PIC__ -#define CPRESTORE(register) \ +#define CPRESTORE(register) \ .cprestore register -#define CPADD(register) \ +#define CPADD(register) \ .cpadd register -#define CPLOAD(register) \ - .cpload register +#define CPLOAD(register) \ + .cpload register #else #define CPRESTORE(register) #define CPADD(register) @@ -48,35 +49,35 @@ /* * LEAF - declare leaf routine */ -#define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .ent symbol, 0; \ +#define LEAF(symbol) \ + .globl symbol; \ + .align 2; \ + .type symbol, @function; \ + .ent symbol, 0; \ symbol: .frame sp, 0, ra /* * NESTED - declare nested routine entry point */ -#define NESTED(symbol, framesize, rpc) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .ent symbol, 0; \ +#define NESTED(symbol, framesize, rpc) \ + .globl symbol; \ + .align 2; \ + .type symbol, @function; \ + .ent symbol, 0; \ symbol: .frame sp, framesize, rpc /* * END - mark end of function */ -#define END(function) \ - .end function; \ +#define END(function) \ + .end function; \ .size function, .-function /* * EXPORT - export definition of symbol */ #define EXPORT(symbol) \ - .globl symbol; \ + .globl symbol; \ symbol: /* @@ -90,16 +91,16 @@ symbol: /* * ABS - export absolute symbol */ -#define ABS(symbol,value) \ - .globl symbol; \ +#define ABS(symbol,value) \ + .globl symbol; \ symbol = value -#define PANIC(msg) \ +#define PANIC(msg) \ .set push; \ - .set reorder; \ - PTR_LA a0, 8f; \ - jal panic; \ -9: b 9b; \ + .set reorder; \ + PTR_LA a0, 8f; \ + jal panic; \ +9: b 9b; \ .set pop; \ TEXT(msg) @@ -107,31 +108,31 @@ symbol = value * Print formatted string */ #ifdef CONFIG_PRINTK -#define PRINT(string) \ +#define PRINT(string) \ .set push; \ - .set reorder; \ - PTR_LA a0, 8f; \ - jal printk; \ + .set reorder; \ + PTR_LA a0, 8f; \ + jal printk; \ .set pop; \ TEXT(string) #else #define PRINT(string) #endif -#define TEXT(msg) \ +#define TEXT(msg) \ .pushsection .data; \ -8: .asciiz msg; \ +8: .asciiz msg; \ .popsection; /* * Build text tables */ -#define TTABLE(string) \ +#define TTABLE(string) \ .pushsection .text; \ - .word 1f; \ + .word 1f; \ .popsection \ .pushsection .data; \ -1: .asciiz string; \ +1: .asciiz string; \ .popsection /* @@ -143,21 +144,29 @@ symbol = value */ #ifdef CONFIG_CPU_HAS_PREFETCH -#define PREF(hint,addr) \ +#define PREF(hint,addr) \ .set push; \ - .set mips4; \ + .set arch=r5000; \ pref hint, addr; \ .set pop -#define PREFX(hint,addr) \ +#define PREFE(hint, addr) \ + .set push; \ + .set mips0; \ + .set eva; \ + prefe hint, addr; \ + .set pop + +#define PREFX(hint,addr) \ .set push; \ - .set mips4; \ + .set arch=r5000; \ prefx hint, addr; \ .set pop #else /* !CONFIG_CPU_HAS_PREFETCH */ #define PREF(hint, addr) +#define PREFE(hint, addr) #define PREFX(hint, addr) #endif /* !CONFIG_CPU_HAS_PREFETCH */ @@ -166,42 +175,42 @@ symbol = value * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. */ #if (_MIPS_ISA == _MIPS_ISA_MIPS1) -#define MOVN(rd, rs, rt) \ +#define MOVN(rd, rs, rt) \ .set push; \ .set reorder; \ - beqz rt, 9f; \ - move rd, rs; \ + beqz rt, 9f; \ + move rd, rs; \ .set pop; \ 9: -#define MOVZ(rd, rs, rt) \ +#define MOVZ(rd, rs, rt) \ .set push; \ .set reorder; \ - bnez rt, 9f; \ - move rd, rs; \ + bnez rt, 9f; \ + move rd, rs; \ .set pop; \ 9: #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) -#define MOVN(rd, rs, rt) \ +#define MOVN(rd, rs, rt) \ .set push; \ .set noreorder; \ - bnezl rt, 9f; \ - move rd, rs; \ + bnezl rt, 9f; \ + move rd, rs; \ .set pop; \ 9: -#define MOVZ(rd, rs, rt) \ +#define MOVZ(rd, rs, rt) \ .set push; \ .set noreorder; \ - beqzl rt, 9f; \ - move rd, rs; \ + beqzl rt, 9f; \ + move rd, rs; \ .set pop; \ 9: #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) -#define MOVN(rd, rs, rt) \ +#define MOVN(rd, rs, rt) \ movn rd, rs, rt -#define MOVZ(rd, rs, rt) \ +#define MOVZ(rd, rs, rt) \ movz rd, rs, rt #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ @@ -296,6 +305,7 @@ symbol = value #define LONG_SUBU subu #define LONG_L lw #define LONG_S sw +#define LONG_SP swp #define LONG_SLL sll #define LONG_SLLV sllv #define LONG_SRL srl @@ -318,6 +328,7 @@ symbol = value #define LONG_SUBU dsubu #define LONG_L ld #define LONG_S sd +#define LONG_SP sdp #define LONG_SLL dsll #define LONG_SLLV dsllv #define LONG_SRL dsrl diff --git a/arch/mips/include/asm/asmmacro-32.h b/arch/mips/include/asm/asmmacro-32.h index 2413afe21b3..e38c2811d4e 100644 --- a/arch/mips/include/asm/asmmacro-32.h +++ b/arch/mips/include/asm/asmmacro-32.h @@ -12,119 +12,77 @@ #include <asm/fpregdef.h> #include <asm/mipsregs.h> - .macro fpu_save_double thread status tmp1=t0 - cfc1 \tmp1, fcr31 - sdc1 $f0, THREAD_FPR0(\thread) - sdc1 $f2, THREAD_FPR2(\thread) - sdc1 $f4, THREAD_FPR4(\thread) - sdc1 $f6, THREAD_FPR6(\thread) - sdc1 $f8, THREAD_FPR8(\thread) - sdc1 $f10, THREAD_FPR10(\thread) - sdc1 $f12, THREAD_FPR12(\thread) - sdc1 $f14, THREAD_FPR14(\thread) - sdc1 $f16, THREAD_FPR16(\thread) - sdc1 $f18, THREAD_FPR18(\thread) - sdc1 $f20, THREAD_FPR20(\thread) - sdc1 $f22, THREAD_FPR22(\thread) - sdc1 $f24, THREAD_FPR24(\thread) - sdc1 $f26, THREAD_FPR26(\thread) - sdc1 $f28, THREAD_FPR28(\thread) - sdc1 $f30, THREAD_FPR30(\thread) - sw \tmp1, THREAD_FCR31(\thread) - .endm - .macro fpu_save_single thread tmp=t0 cfc1 \tmp, fcr31 - swc1 $f0, THREAD_FPR0(\thread) - swc1 $f1, THREAD_FPR1(\thread) - swc1 $f2, THREAD_FPR2(\thread) - swc1 $f3, THREAD_FPR3(\thread) - swc1 $f4, THREAD_FPR4(\thread) - swc1 $f5, THREAD_FPR5(\thread) - swc1 $f6, THREAD_FPR6(\thread) - swc1 $f7, THREAD_FPR7(\thread) - swc1 $f8, THREAD_FPR8(\thread) - swc1 $f9, THREAD_FPR9(\thread) - swc1 $f10, THREAD_FPR10(\thread) - swc1 $f11, THREAD_FPR11(\thread) - swc1 $f12, THREAD_FPR12(\thread) - swc1 $f13, THREAD_FPR13(\thread) - swc1 $f14, THREAD_FPR14(\thread) - swc1 $f15, THREAD_FPR15(\thread) - swc1 $f16, THREAD_FPR16(\thread) - swc1 $f17, THREAD_FPR17(\thread) - swc1 $f18, THREAD_FPR18(\thread) - swc1 $f19, THREAD_FPR19(\thread) - swc1 $f20, THREAD_FPR20(\thread) - swc1 $f21, THREAD_FPR21(\thread) - swc1 $f22, THREAD_FPR22(\thread) - swc1 $f23, THREAD_FPR23(\thread) - swc1 $f24, THREAD_FPR24(\thread) - swc1 $f25, THREAD_FPR25(\thread) - swc1 $f26, THREAD_FPR26(\thread) - swc1 $f27, THREAD_FPR27(\thread) - swc1 $f28, THREAD_FPR28(\thread) - swc1 $f29, THREAD_FPR29(\thread) - swc1 $f30, THREAD_FPR30(\thread) - swc1 $f31, THREAD_FPR31(\thread) + swc1 $f0, THREAD_FPR0_LS64(\thread) + swc1 $f1, THREAD_FPR1_LS64(\thread) + swc1 $f2, THREAD_FPR2_LS64(\thread) + swc1 $f3, THREAD_FPR3_LS64(\thread) + swc1 $f4, THREAD_FPR4_LS64(\thread) + swc1 $f5, THREAD_FPR5_LS64(\thread) + swc1 $f6, THREAD_FPR6_LS64(\thread) + swc1 $f7, THREAD_FPR7_LS64(\thread) + swc1 $f8, THREAD_FPR8_LS64(\thread) + swc1 $f9, THREAD_FPR9_LS64(\thread) + swc1 $f10, THREAD_FPR10_LS64(\thread) + swc1 $f11, THREAD_FPR11_LS64(\thread) + swc1 $f12, THREAD_FPR12_LS64(\thread) + swc1 $f13, THREAD_FPR13_LS64(\thread) + swc1 $f14, THREAD_FPR14_LS64(\thread) + swc1 $f15, THREAD_FPR15_LS64(\thread) + swc1 $f16, THREAD_FPR16_LS64(\thread) + swc1 $f17, THREAD_FPR17_LS64(\thread) + swc1 $f18, THREAD_FPR18_LS64(\thread) + swc1 $f19, THREAD_FPR19_LS64(\thread) + swc1 $f20, THREAD_FPR20_LS64(\thread) + swc1 $f21, THREAD_FPR21_LS64(\thread) + swc1 $f22, THREAD_FPR22_LS64(\thread) + swc1 $f23, THREAD_FPR23_LS64(\thread) + swc1 $f24, THREAD_FPR24_LS64(\thread) + swc1 $f25, THREAD_FPR25_LS64(\thread) + swc1 $f26, THREAD_FPR26_LS64(\thread) + swc1 $f27, THREAD_FPR27_LS64(\thread) + swc1 $f28, THREAD_FPR28_LS64(\thread) + swc1 $f29, THREAD_FPR29_LS64(\thread) + swc1 $f30, THREAD_FPR30_LS64(\thread) + swc1 $f31, THREAD_FPR31_LS64(\thread) sw \tmp, THREAD_FCR31(\thread) .endm - .macro fpu_restore_double thread status tmp=t0 - lw \tmp, THREAD_FCR31(\thread) - ldc1 $f0, THREAD_FPR0(\thread) - ldc1 $f2, THREAD_FPR2(\thread) - ldc1 $f4, THREAD_FPR4(\thread) - ldc1 $f6, THREAD_FPR6(\thread) - ldc1 $f8, THREAD_FPR8(\thread) - ldc1 $f10, THREAD_FPR10(\thread) - ldc1 $f12, THREAD_FPR12(\thread) - ldc1 $f14, THREAD_FPR14(\thread) - ldc1 $f16, THREAD_FPR16(\thread) - ldc1 $f18, THREAD_FPR18(\thread) - ldc1 $f20, THREAD_FPR20(\thread) - ldc1 $f22, THREAD_FPR22(\thread) - ldc1 $f24, THREAD_FPR24(\thread) - ldc1 $f26, THREAD_FPR26(\thread) - ldc1 $f28, THREAD_FPR28(\thread) - ldc1 $f30, THREAD_FPR30(\thread) - ctc1 \tmp, fcr31 - .endm - .macro fpu_restore_single thread tmp=t0 lw \tmp, THREAD_FCR31(\thread) - lwc1 $f0, THREAD_FPR0(\thread) - lwc1 $f1, THREAD_FPR1(\thread) - lwc1 $f2, THREAD_FPR2(\thread) - lwc1 $f3, THREAD_FPR3(\thread) - lwc1 $f4, THREAD_FPR4(\thread) - lwc1 $f5, THREAD_FPR5(\thread) - lwc1 $f6, THREAD_FPR6(\thread) - lwc1 $f7, THREAD_FPR7(\thread) - lwc1 $f8, THREAD_FPR8(\thread) - lwc1 $f9, THREAD_FPR9(\thread) - lwc1 $f10, THREAD_FPR10(\thread) - lwc1 $f11, THREAD_FPR11(\thread) - lwc1 $f12, THREAD_FPR12(\thread) - lwc1 $f13, THREAD_FPR13(\thread) - lwc1 $f14, THREAD_FPR14(\thread) - lwc1 $f15, THREAD_FPR15(\thread) - lwc1 $f16, THREAD_FPR16(\thread) - lwc1 $f17, THREAD_FPR17(\thread) - lwc1 $f18, THREAD_FPR18(\thread) - lwc1 $f19, THREAD_FPR19(\thread) - lwc1 $f20, THREAD_FPR20(\thread) - lwc1 $f21, THREAD_FPR21(\thread) - lwc1 $f22, THREAD_FPR22(\thread) - lwc1 $f23, THREAD_FPR23(\thread) - lwc1 $f24, THREAD_FPR24(\thread) - lwc1 $f25, THREAD_FPR25(\thread) - lwc1 $f26, THREAD_FPR26(\thread) - lwc1 $f27, THREAD_FPR27(\thread) - lwc1 $f28, THREAD_FPR28(\thread) - lwc1 $f29, THREAD_FPR29(\thread) - lwc1 $f30, THREAD_FPR30(\thread) - lwc1 $f31, THREAD_FPR31(\thread) + lwc1 $f0, THREAD_FPR0_LS64(\thread) + lwc1 $f1, THREAD_FPR1_LS64(\thread) + lwc1 $f2, THREAD_FPR2_LS64(\thread) + lwc1 $f3, THREAD_FPR3_LS64(\thread) + lwc1 $f4, THREAD_FPR4_LS64(\thread) + lwc1 $f5, THREAD_FPR5_LS64(\thread) + lwc1 $f6, THREAD_FPR6_LS64(\thread) + lwc1 $f7, THREAD_FPR7_LS64(\thread) + lwc1 $f8, THREAD_FPR8_LS64(\thread) + lwc1 $f9, THREAD_FPR9_LS64(\thread) + lwc1 $f10, THREAD_FPR10_LS64(\thread) + lwc1 $f11, THREAD_FPR11_LS64(\thread) + lwc1 $f12, THREAD_FPR12_LS64(\thread) + lwc1 $f13, THREAD_FPR13_LS64(\thread) + lwc1 $f14, THREAD_FPR14_LS64(\thread) + lwc1 $f15, THREAD_FPR15_LS64(\thread) + lwc1 $f16, THREAD_FPR16_LS64(\thread) + lwc1 $f17, THREAD_FPR17_LS64(\thread) + lwc1 $f18, THREAD_FPR18_LS64(\thread) + lwc1 $f19, THREAD_FPR19_LS64(\thread) + lwc1 $f20, THREAD_FPR20_LS64(\thread) + lwc1 $f21, THREAD_FPR21_LS64(\thread) + lwc1 $f22, THREAD_FPR22_LS64(\thread) + lwc1 $f23, THREAD_FPR23_LS64(\thread) + lwc1 $f24, THREAD_FPR24_LS64(\thread) + lwc1 $f25, THREAD_FPR25_LS64(\thread) + lwc1 $f26, THREAD_FPR26_LS64(\thread) + lwc1 $f27, THREAD_FPR27_LS64(\thread) + lwc1 $f28, THREAD_FPR28_LS64(\thread) + lwc1 $f29, THREAD_FPR29_LS64(\thread) + lwc1 $f30, THREAD_FPR30_LS64(\thread) + lwc1 $f31, THREAD_FPR31_LS64(\thread) ctc1 \tmp, fcr31 .endm diff --git a/arch/mips/include/asm/asmmacro-64.h b/arch/mips/include/asm/asmmacro-64.h index 08a527dfe4a..38ea609465b 100644 --- a/arch/mips/include/asm/asmmacro-64.h +++ b/arch/mips/include/asm/asmmacro-64.h @@ -13,102 +13,6 @@ #include <asm/fpregdef.h> #include <asm/mipsregs.h> - .macro fpu_save_16even thread tmp=t0 - cfc1 \tmp, fcr31 - sdc1 $f0, THREAD_FPR0(\thread) - sdc1 $f2, THREAD_FPR2(\thread) - sdc1 $f4, THREAD_FPR4(\thread) - sdc1 $f6, THREAD_FPR6(\thread) - sdc1 $f8, THREAD_FPR8(\thread) - sdc1 $f10, THREAD_FPR10(\thread) - sdc1 $f12, THREAD_FPR12(\thread) - sdc1 $f14, THREAD_FPR14(\thread) - sdc1 $f16, THREAD_FPR16(\thread) - sdc1 $f18, THREAD_FPR18(\thread) - sdc1 $f20, THREAD_FPR20(\thread) - sdc1 $f22, THREAD_FPR22(\thread) - sdc1 $f24, THREAD_FPR24(\thread) - sdc1 $f26, THREAD_FPR26(\thread) - sdc1 $f28, THREAD_FPR28(\thread) - sdc1 $f30, THREAD_FPR30(\thread) - sw \tmp, THREAD_FCR31(\thread) - .endm - - .macro fpu_save_16odd thread - sdc1 $f1, THREAD_FPR1(\thread) - sdc1 $f3, THREAD_FPR3(\thread) - sdc1 $f5, THREAD_FPR5(\thread) - sdc1 $f7, THREAD_FPR7(\thread) - sdc1 $f9, THREAD_FPR9(\thread) - sdc1 $f11, THREAD_FPR11(\thread) - sdc1 $f13, THREAD_FPR13(\thread) - sdc1 $f15, THREAD_FPR15(\thread) - sdc1 $f17, THREAD_FPR17(\thread) - sdc1 $f19, THREAD_FPR19(\thread) - sdc1 $f21, THREAD_FPR21(\thread) - sdc1 $f23, THREAD_FPR23(\thread) - sdc1 $f25, THREAD_FPR25(\thread) - sdc1 $f27, THREAD_FPR27(\thread) - sdc1 $f29, THREAD_FPR29(\thread) - sdc1 $f31, THREAD_FPR31(\thread) - .endm - - .macro fpu_save_double thread status tmp - sll \tmp, \status, 5 - bgez \tmp, 2f - fpu_save_16odd \thread -2: - fpu_save_16even \thread \tmp - .endm - - .macro fpu_restore_16even thread tmp=t0 - lw \tmp, THREAD_FCR31(\thread) - ldc1 $f0, THREAD_FPR0(\thread) - ldc1 $f2, THREAD_FPR2(\thread) - ldc1 $f4, THREAD_FPR4(\thread) - ldc1 $f6, THREAD_FPR6(\thread) - ldc1 $f8, THREAD_FPR8(\thread) - ldc1 $f10, THREAD_FPR10(\thread) - ldc1 $f12, THREAD_FPR12(\thread) - ldc1 $f14, THREAD_FPR14(\thread) - ldc1 $f16, THREAD_FPR16(\thread) - ldc1 $f18, THREAD_FPR18(\thread) - ldc1 $f20, THREAD_FPR20(\thread) - ldc1 $f22, THREAD_FPR22(\thread) - ldc1 $f24, THREAD_FPR24(\thread) - ldc1 $f26, THREAD_FPR26(\thread) - ldc1 $f28, THREAD_FPR28(\thread) - ldc1 $f30, THREAD_FPR30(\thread) - ctc1 \tmp, fcr31 - .endm - - .macro fpu_restore_16odd thread - ldc1 $f1, THREAD_FPR1(\thread) - ldc1 $f3, THREAD_FPR3(\thread) - ldc1 $f5, THREAD_FPR5(\thread) - ldc1 $f7, THREAD_FPR7(\thread) - ldc1 $f9, THREAD_FPR9(\thread) - ldc1 $f11, THREAD_FPR11(\thread) - ldc1 $f13, THREAD_FPR13(\thread) - ldc1 $f15, THREAD_FPR15(\thread) - ldc1 $f17, THREAD_FPR17(\thread) - ldc1 $f19, THREAD_FPR19(\thread) - ldc1 $f21, THREAD_FPR21(\thread) - ldc1 $f23, THREAD_FPR23(\thread) - ldc1 $f25, THREAD_FPR25(\thread) - ldc1 $f27, THREAD_FPR27(\thread) - ldc1 $f29, THREAD_FPR29(\thread) - ldc1 $f31, THREAD_FPR31(\thread) - .endm - - .macro fpu_restore_double thread status tmp - sll \tmp, \status, 5 - bgez \tmp, 1f # 16 register mode? - - fpu_restore_16odd \thread -1: fpu_restore_16even \thread \tmp - .endm - .macro cpu_save_nonscratch thread LONG_S s0, THREAD_REG16(\thread) LONG_S s1, THREAD_REG17(\thread) diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h index 6c8342ae74d..935543f1453 100644 --- a/arch/mips/include/asm/asmmacro.h +++ b/arch/mips/include/asm/asmmacro.h @@ -9,6 +9,7 @@ #define _ASM_ASMMACRO_H #include <asm/hazards.h> +#include <asm/asm-offsets.h> #ifdef CONFIG_32BIT #include <asm/asmmacro-32.h> @@ -16,26 +17,8 @@ #ifdef CONFIG_64BIT #include <asm/asmmacro-64.h> #endif -#ifdef CONFIG_MIPS_MT_SMTC -#include <asm/mipsmtregs.h> -#endif - -#ifdef CONFIG_MIPS_MT_SMTC - .macro local_irq_enable reg=t0 - mfc0 \reg, CP0_TCSTATUS - ori \reg, \reg, TCSTATUS_IXMT - xori \reg, \reg, TCSTATUS_IXMT - mtc0 \reg, CP0_TCSTATUS - _ehb - .endm - .macro local_irq_disable reg=t0 - mfc0 \reg, CP0_TCSTATUS - ori \reg, \reg, TCSTATUS_IXMT - mtc0 \reg, CP0_TCSTATUS - _ehb - .endm -#elif defined(CONFIG_CPU_MIPSR2) +#ifdef CONFIG_CPU_MIPSR2 .macro local_irq_enable reg=t0 ei irq_enable_hazard @@ -54,13 +37,141 @@ .endm .macro local_irq_disable reg=t0 +#ifdef CONFIG_PREEMPT + lw \reg, TI_PRE_COUNT($28) + addi \reg, \reg, 1 + sw \reg, TI_PRE_COUNT($28) +#endif mfc0 \reg, CP0_STATUS ori \reg, \reg, 1 xori \reg, \reg, 1 mtc0 \reg, CP0_STATUS irq_disable_hazard +#ifdef CONFIG_PREEMPT + lw \reg, TI_PRE_COUNT($28) + addi \reg, \reg, -1 + sw \reg, TI_PRE_COUNT($28) +#endif + .endm +#endif /* CONFIG_CPU_MIPSR2 */ + + .macro fpu_save_16even thread tmp=t0 + cfc1 \tmp, fcr31 + sdc1 $f0, THREAD_FPR0_LS64(\thread) + sdc1 $f2, THREAD_FPR2_LS64(\thread) + sdc1 $f4, THREAD_FPR4_LS64(\thread) + sdc1 $f6, THREAD_FPR6_LS64(\thread) + sdc1 $f8, THREAD_FPR8_LS64(\thread) + sdc1 $f10, THREAD_FPR10_LS64(\thread) + sdc1 $f12, THREAD_FPR12_LS64(\thread) + sdc1 $f14, THREAD_FPR14_LS64(\thread) + sdc1 $f16, THREAD_FPR16_LS64(\thread) + sdc1 $f18, THREAD_FPR18_LS64(\thread) + sdc1 $f20, THREAD_FPR20_LS64(\thread) + sdc1 $f22, THREAD_FPR22_LS64(\thread) + sdc1 $f24, THREAD_FPR24_LS64(\thread) + sdc1 $f26, THREAD_FPR26_LS64(\thread) + sdc1 $f28, THREAD_FPR28_LS64(\thread) + sdc1 $f30, THREAD_FPR30_LS64(\thread) + sw \tmp, THREAD_FCR31(\thread) + .endm + + .macro fpu_save_16odd thread + .set push + .set mips64r2 + sdc1 $f1, THREAD_FPR1_LS64(\thread) + sdc1 $f3, THREAD_FPR3_LS64(\thread) + sdc1 $f5, THREAD_FPR5_LS64(\thread) + sdc1 $f7, THREAD_FPR7_LS64(\thread) + sdc1 $f9, THREAD_FPR9_LS64(\thread) + sdc1 $f11, THREAD_FPR11_LS64(\thread) + sdc1 $f13, THREAD_FPR13_LS64(\thread) + sdc1 $f15, THREAD_FPR15_LS64(\thread) + sdc1 $f17, THREAD_FPR17_LS64(\thread) + sdc1 $f19, THREAD_FPR19_LS64(\thread) + sdc1 $f21, THREAD_FPR21_LS64(\thread) + sdc1 $f23, THREAD_FPR23_LS64(\thread) + sdc1 $f25, THREAD_FPR25_LS64(\thread) + sdc1 $f27, THREAD_FPR27_LS64(\thread) + sdc1 $f29, THREAD_FPR29_LS64(\thread) + sdc1 $f31, THREAD_FPR31_LS64(\thread) + .set pop + .endm + + .macro fpu_save_double thread status tmp +#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) + sll \tmp, \status, 5 + bgez \tmp, 10f + fpu_save_16odd \thread +10: +#endif + fpu_save_16even \thread \tmp + .endm + + .macro fpu_restore_16even thread tmp=t0 + lw \tmp, THREAD_FCR31(\thread) + ldc1 $f0, THREAD_FPR0_LS64(\thread) + ldc1 $f2, THREAD_FPR2_LS64(\thread) + ldc1 $f4, THREAD_FPR4_LS64(\thread) + ldc1 $f6, THREAD_FPR6_LS64(\thread) + ldc1 $f8, THREAD_FPR8_LS64(\thread) + ldc1 $f10, THREAD_FPR10_LS64(\thread) + ldc1 $f12, THREAD_FPR12_LS64(\thread) + ldc1 $f14, THREAD_FPR14_LS64(\thread) + ldc1 $f16, THREAD_FPR16_LS64(\thread) + ldc1 $f18, THREAD_FPR18_LS64(\thread) + ldc1 $f20, THREAD_FPR20_LS64(\thread) + ldc1 $f22, THREAD_FPR22_LS64(\thread) + ldc1 $f24, THREAD_FPR24_LS64(\thread) + ldc1 $f26, THREAD_FPR26_LS64(\thread) + ldc1 $f28, THREAD_FPR28_LS64(\thread) + ldc1 $f30, THREAD_FPR30_LS64(\thread) + ctc1 \tmp, fcr31 + .endm + + .macro fpu_restore_16odd thread + .set push + .set mips64r2 + ldc1 $f1, THREAD_FPR1_LS64(\thread) + ldc1 $f3, THREAD_FPR3_LS64(\thread) + ldc1 $f5, THREAD_FPR5_LS64(\thread) + ldc1 $f7, THREAD_FPR7_LS64(\thread) + ldc1 $f9, THREAD_FPR9_LS64(\thread) + ldc1 $f11, THREAD_FPR11_LS64(\thread) + ldc1 $f13, THREAD_FPR13_LS64(\thread) + ldc1 $f15, THREAD_FPR15_LS64(\thread) + ldc1 $f17, THREAD_FPR17_LS64(\thread) + ldc1 $f19, THREAD_FPR19_LS64(\thread) + ldc1 $f21, THREAD_FPR21_LS64(\thread) + ldc1 $f23, THREAD_FPR23_LS64(\thread) + ldc1 $f25, THREAD_FPR25_LS64(\thread) + ldc1 $f27, THREAD_FPR27_LS64(\thread) + ldc1 $f29, THREAD_FPR29_LS64(\thread) + ldc1 $f31, THREAD_FPR31_LS64(\thread) + .set pop + .endm + + .macro fpu_restore_double thread status tmp +#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) + sll \tmp, \status, 5 + bgez \tmp, 10f # 16 register mode? + + fpu_restore_16odd \thread +10: +#endif + fpu_restore_16even \thread \tmp + .endm + +#ifdef CONFIG_CPU_MIPSR2 + .macro _EXT rd, rs, p, s + ext \rd, \rs, \p, \s + .endm +#else /* !CONFIG_CPU_MIPSR2 */ + .macro _EXT rd, rs, p, s + srl \rd, \rs, \p + andi \rd, \rd, (1 << \s) - 1 .endm -#endif /* CONFIG_MIPS_MT_SMTC */ +#endif /* !CONFIG_CPU_MIPSR2 */ /* * Temporary until all gas have MT ASE support @@ -89,4 +200,219 @@ .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) .endm +#ifdef TOOLCHAIN_SUPPORTS_MSA + .macro ld_d wd, off, base + .set push + .set mips32r2 + .set msa + ld.d $w\wd, \off(\base) + .set pop + .endm + + .macro st_d wd, off, base + .set push + .set mips32r2 + .set msa + st.d $w\wd, \off(\base) + .set pop + .endm + + .macro copy_u_w rd, ws, n + .set push + .set mips32r2 + .set msa + copy_u.w \rd, $w\ws[\n] + .set pop + .endm + + .macro copy_u_d rd, ws, n + .set push + .set mips64r2 + .set msa + copy_u.d \rd, $w\ws[\n] + .set pop + .endm + + .macro insert_w wd, n, rs + .set push + .set mips32r2 + .set msa + insert.w $w\wd[\n], \rs + .set pop + .endm + + .macro insert_d wd, n, rs + .set push + .set mips64r2 + .set msa + insert.d $w\wd[\n], \rs + .set pop + .endm +#else + +#ifdef CONFIG_CPU_MICROMIPS +#define CFC_MSA_INSN 0x587e0056 +#define CTC_MSA_INSN 0x583e0816 +#define LDD_MSA_INSN 0x58000837 +#define STD_MSA_INSN 0x5800083f +#define COPY_UW_MSA_INSN 0x58f00056 +#define COPY_UD_MSA_INSN 0x58f80056 +#define INSERT_W_MSA_INSN 0x59300816 +#define INSERT_D_MSA_INSN 0x59380816 +#else +#define CFC_MSA_INSN 0x787e0059 +#define CTC_MSA_INSN 0x783e0819 +#define LDD_MSA_INSN 0x78000823 +#define STD_MSA_INSN 0x78000827 +#define COPY_UW_MSA_INSN 0x78f00059 +#define COPY_UD_MSA_INSN 0x78f80059 +#define INSERT_W_MSA_INSN 0x79300819 +#define INSERT_D_MSA_INSN 0x79380819 +#endif + + /* + * Temporary until all toolchains in use include MSA support. + */ + .macro cfcmsa rd, cs + .set push + .set noat + .insn + .word CFC_MSA_INSN | (\cs << 11) + move \rd, $1 + .set pop + .endm + + .macro ctcmsa cd, rs + .set push + .set noat + move $1, \rs + .word CTC_MSA_INSN | (\cd << 6) + .set pop + .endm + + .macro ld_d wd, off, base + .set push + .set noat + add $1, \base, \off + .word LDD_MSA_INSN | (\wd << 6) + .set pop + .endm + + .macro st_d wd, off, base + .set push + .set noat + add $1, \base, \off + .word STD_MSA_INSN | (\wd << 6) + .set pop + .endm + + .macro copy_u_w rd, ws, n + .set push + .set noat + .insn + .word COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11) + /* move triggers an assembler bug... */ + or \rd, $1, zero + .set pop + .endm + + .macro copy_u_d rd, ws, n + .set push + .set noat + .insn + .word COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11) + /* move triggers an assembler bug... */ + or \rd, $1, zero + .set pop + .endm + + .macro insert_w wd, n, rs + .set push + .set noat + /* move triggers an assembler bug... */ + or $1, \rs, zero + .word INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6) + .set pop + .endm + + .macro insert_d wd, n, rs + .set push + .set noat + /* move triggers an assembler bug... */ + or $1, \rs, zero + .word INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6) + .set pop + .endm +#endif + + .macro msa_save_all thread + st_d 0, THREAD_FPR0, \thread + st_d 1, THREAD_FPR1, \thread + st_d 2, THREAD_FPR2, \thread + st_d 3, THREAD_FPR3, \thread + st_d 4, THREAD_FPR4, \thread + st_d 5, THREAD_FPR5, \thread + st_d 6, THREAD_FPR6, \thread + st_d 7, THREAD_FPR7, \thread + st_d 8, THREAD_FPR8, \thread + st_d 9, THREAD_FPR9, \thread + st_d 10, THREAD_FPR10, \thread + st_d 11, THREAD_FPR11, \thread + st_d 12, THREAD_FPR12, \thread + st_d 13, THREAD_FPR13, \thread + st_d 14, THREAD_FPR14, \thread + st_d 15, THREAD_FPR15, \thread + st_d 16, THREAD_FPR16, \thread + st_d 17, THREAD_FPR17, \thread + st_d 18, THREAD_FPR18, \thread + st_d 19, THREAD_FPR19, \thread + st_d 20, THREAD_FPR20, \thread + st_d 21, THREAD_FPR21, \thread + st_d 22, THREAD_FPR22, \thread + st_d 23, THREAD_FPR23, \thread + st_d 24, THREAD_FPR24, \thread + st_d 25, THREAD_FPR25, \thread + st_d 26, THREAD_FPR26, \thread + st_d 27, THREAD_FPR27, \thread + st_d 28, THREAD_FPR28, \thread + st_d 29, THREAD_FPR29, \thread + st_d 30, THREAD_FPR30, \thread + st_d 31, THREAD_FPR31, \thread + .endm + + .macro msa_restore_all thread + ld_d 0, THREAD_FPR0, \thread + ld_d 1, THREAD_FPR1, \thread + ld_d 2, THREAD_FPR2, \thread + ld_d 3, THREAD_FPR3, \thread + ld_d 4, THREAD_FPR4, \thread + ld_d 5, THREAD_FPR5, \thread + ld_d 6, THREAD_FPR6, \thread + ld_d 7, THREAD_FPR7, \thread + ld_d 8, THREAD_FPR8, \thread + ld_d 9, THREAD_FPR9, \thread + ld_d 10, THREAD_FPR10, \thread + ld_d 11, THREAD_FPR11, \thread + ld_d 12, THREAD_FPR12, \thread + ld_d 13, THREAD_FPR13, \thread + ld_d 14, THREAD_FPR14, \thread + ld_d 15, THREAD_FPR15, \thread + ld_d 16, THREAD_FPR16, \thread + ld_d 17, THREAD_FPR17, \thread + ld_d 18, THREAD_FPR18, \thread + ld_d 19, THREAD_FPR19, \thread + ld_d 20, THREAD_FPR20, \thread + ld_d 21, THREAD_FPR21, \thread + ld_d 22, THREAD_FPR22, \thread + ld_d 23, THREAD_FPR23, \thread + ld_d 24, THREAD_FPR24, \thread + ld_d 25, THREAD_FPR25, \thread + ld_d 26, THREAD_FPR26, \thread + ld_d 27, THREAD_FPR27, \thread + ld_d 28, THREAD_FPR28, \thread + ld_d 29, THREAD_FPR29, \thread + ld_d 30, THREAD_FPR30, \thread + ld_d 31, THREAD_FPR31, \thread + .endm + #endif /* _ASM_ASMMACRO_H */ diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index 01cc6ba6483..37b2befe651 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -21,7 +21,7 @@ #include <asm/cmpxchg.h> #include <asm/war.h> -#define ATOMIC_INIT(i) { (i) } +#define ATOMIC_INIT(i) { (i) } /* * atomic_read - read atomic variable @@ -53,7 +53,7 @@ static __inline__ void atomic_add(int i, atomic_t * v) int temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: ll %0, %1 # atomic_add \n" " addu %0, %2 \n" " sc %0, %1 \n" @@ -66,7 +66,7 @@ static __inline__ void atomic_add(int i, atomic_t * v) do { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" " ll %0, %1 # atomic_add \n" " addu %0, %2 \n" " sc %0, %1 \n" @@ -96,7 +96,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v) int temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: ll %0, %1 # atomic_sub \n" " subu %0, %2 \n" " sc %0, %1 \n" @@ -109,7 +109,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v) do { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" " ll %0, %1 # atomic_sub \n" " subu %0, %2 \n" " sc %0, %1 \n" @@ -139,7 +139,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) int temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: ll %1, %2 # atomic_add_return \n" " addu %0, %1, %3 \n" " sc %0, %2 \n" @@ -153,7 +153,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) do { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" " ll %1, %2 # atomic_add_return \n" " addu %0, %1, %3 \n" " sc %0, %2 \n" @@ -188,7 +188,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) int temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: ll %1, %2 # atomic_sub_return \n" " subu %0, %1, %3 \n" " sc %0, %2 \n" @@ -205,7 +205,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) do { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" " ll %1, %2 # atomic_sub_return \n" " subu %0, %1, %3 \n" " sc %0, %2 \n" @@ -248,7 +248,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) int temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: ll %1, %2 # atomic_sub_if_positive\n" " subu %0, %1, %3 \n" " bltz %0, 1f \n" @@ -266,7 +266,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) int temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: ll %1, %2 # atomic_sub_if_positive\n" " subu %0, %1, %3 \n" " bltz %0, 1f \n" @@ -420,7 +420,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v) long temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: lld %0, %1 # atomic64_add \n" " daddu %0, %2 \n" " scd %0, %1 \n" @@ -433,7 +433,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v) do { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" " lld %0, %1 # atomic64_add \n" " daddu %0, %2 \n" " scd %0, %1 \n" @@ -463,7 +463,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v) long temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: lld %0, %1 # atomic64_sub \n" " dsubu %0, %2 \n" " scd %0, %1 \n" @@ -476,7 +476,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v) do { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" " lld %0, %1 # atomic64_sub \n" " dsubu %0, %2 \n" " scd %0, %1 \n" @@ -506,7 +506,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) long temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: lld %1, %2 # atomic64_add_return \n" " daddu %0, %1, %3 \n" " scd %0, %2 \n" @@ -520,7 +520,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) do { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" " lld %1, %2 # atomic64_add_return \n" " daddu %0, %1, %3 \n" " scd %0, %2 \n" @@ -556,7 +556,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) long temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: lld %1, %2 # atomic64_sub_return \n" " dsubu %0, %1, %3 \n" " scd %0, %2 \n" @@ -571,7 +571,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) do { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" " lld %1, %2 # atomic64_sub_return \n" " dsubu %0, %1, %3 \n" " scd %0, %2 \n" @@ -615,7 +615,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) long temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: lld %1, %2 # atomic64_sub_if_positive\n" " dsubu %0, %1, %3 \n" " bltz %0, 1f \n" @@ -633,7 +633,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) long temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: lld %1, %2 # atomic64_sub_if_positive\n" " dsubu %0, %1, %3 \n" " bltz %0, 1f \n" @@ -761,13 +761,4 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) #endif /* CONFIG_64BIT */ -/* - * atomic*_return operations are serializing but not the non-*_return - * versions. - */ -#define smp_mb__before_atomic_dec() smp_mb__before_llsc() -#define smp_mb__after_atomic_dec() smp_llsc_mb() -#define smp_mb__before_atomic_inc() smp_mb__before_llsc() -#define smp_mb__after_atomic_inc() smp_llsc_mb() - #endif /* _ASM_ATOMIC_H */ diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h index f7fdc24e972..d0101dd0575 100644 --- a/arch/mips/include/asm/barrier.h +++ b/arch/mips/include/asm/barrier.h @@ -92,7 +92,7 @@ : "memory") #ifdef CONFIG_CPU_CAVIUM_OCTEON # define OCTEON_SYNCW_STR ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n" -# define __syncw() __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory") +# define __syncw() __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory") # define fast_wmb() __syncw() # define fast_rmb() barrier() @@ -158,7 +158,7 @@ #endif #if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP) -#define __WEAK_LLSC_MB " sync \n" +#define __WEAK_LLSC_MB " sync \n" #else #define __WEAK_LLSC_MB " \n" #endif @@ -180,4 +180,22 @@ #define nudge_writes() mb() #endif +#define smp_store_release(p, v) \ +do { \ + compiletime_assert_atomic_type(*p); \ + smp_mb(); \ + ACCESS_ONCE(*p) = (v); \ +} while (0) + +#define smp_load_acquire(p) \ +({ \ + typeof(*p) ___p1 = ACCESS_ONCE(*p); \ + compiletime_assert_atomic_type(*p); \ + smp_mb(); \ + ___p1; \ +}) + +#define smp_mb__before_atomic() smp_mb__before_llsc() +#define smp_mb__after_atomic() smp_llsc_mb() + #endif /* __ASM_BARRIER_H */ diff --git a/arch/mips/include/asm/bcache.h b/arch/mips/include/asm/bcache.h index 0ba9d6ef76a..8c34484cea8 100644 --- a/arch/mips/include/asm/bcache.h +++ b/arch/mips/include/asm/bcache.h @@ -11,7 +11,7 @@ /* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent, - chipset implemented caches. On machines with other CPUs the CPU does the + chipset implemented caches. On machines with other CPUs the CPU does the cache thing itself. */ struct bcache_ops { void (*bc_enable)(void); diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 46ac73abd5e..7c8816f7b7c 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -26,25 +26,18 @@ #define SZLONG_MASK 31UL #define __LL "ll " #define __SC "sc " -#define __INS "ins " -#define __EXT "ext " +#define __INS "ins " +#define __EXT "ext " #elif _MIPS_SZLONG == 64 #define SZLONG_LOG 6 #define SZLONG_MASK 63UL #define __LL "lld " #define __SC "scd " -#define __INS "dins " -#define __EXT "dext " +#define __INS "dins " +#define __EXT "dext " #endif /* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() smp_mb__before_llsc() -#define smp_mb__after_clear_bit() smp_llsc_mb() - - -/* * These are the "slower" versions of the functions and are in bitops.c. * These functions call raw_local_irq_{save,restore}(). */ @@ -79,7 +72,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) if (kernel_uses_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: " __LL "%0, %1 # set_bit \n" " or %0, %2 \n" " " __SC "%0, %1 \n" @@ -101,7 +94,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) } else if (kernel_uses_llsc) { do { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" " " __LL "%0, %1 # set_bit \n" " or %0, %2 \n" " " __SC "%0, %1 \n" @@ -120,7 +113,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) * * clear_bit() is atomic and may not be reordered. However, it does * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic() * in order to ensure changes are visible on other processors. */ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) @@ -131,7 +124,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) if (kernel_uses_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: " __LL "%0, %1 # clear_bit \n" " and %0, %2 \n" " " __SC "%0, %1 \n" @@ -153,7 +146,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) } else if (kernel_uses_llsc) { do { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" " " __LL "%0, %1 # clear_bit \n" " and %0, %2 \n" " " __SC "%0, %1 \n" @@ -175,7 +168,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) */ static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *addr) { - smp_mb__before_clear_bit(); + smp_mb__before_atomic(); clear_bit(nr, addr); } @@ -197,7 +190,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) unsigned long temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: " __LL "%0, %1 # change_bit \n" " xor %0, %2 \n" " " __SC "%0, %1 \n" @@ -211,7 +204,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) do { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" " " __LL "%0, %1 # change_bit \n" " xor %0, %2 \n" " " __SC "%0, %1 \n" @@ -244,7 +237,7 @@ static inline int test_and_set_bit(unsigned long nr, unsigned long temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: " __LL "%0, %1 # test_and_set_bit \n" " or %2, %0, %3 \n" " " __SC "%2, %1 \n" @@ -260,7 +253,7 @@ static inline int test_and_set_bit(unsigned long nr, do { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" " " __LL "%0, %1 # test_and_set_bit \n" " or %2, %0, %3 \n" " " __SC "%2, %1 \n" @@ -298,7 +291,7 @@ static inline int test_and_set_bit_lock(unsigned long nr, unsigned long temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: " __LL "%0, %1 # test_and_set_bit \n" " or %2, %0, %3 \n" " " __SC "%2, %1 \n" @@ -314,7 +307,7 @@ static inline int test_and_set_bit_lock(unsigned long nr, do { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" " " __LL "%0, %1 # test_and_set_bit \n" " or %2, %0, %3 \n" " " __SC "%2, %1 \n" @@ -353,11 +346,11 @@ static inline int test_and_clear_bit(unsigned long nr, unsigned long temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: " __LL "%0, %1 # test_and_clear_bit \n" " or %2, %0, %3 \n" " xor %2, %3 \n" - " " __SC "%2, %1 \n" + " " __SC "%2, %1 \n" " beqzl %2, 1b \n" " and %2, %0, %3 \n" " .set mips0 \n" @@ -371,10 +364,10 @@ static inline int test_and_clear_bit(unsigned long nr, do { __asm__ __volatile__( - " " __LL "%0, %1 # test_and_clear_bit \n" + " " __LL "%0, %1 # test_and_clear_bit \n" " " __EXT "%2, %0, %3, 1 \n" - " " __INS "%0, $0, %3, 1 \n" - " " __SC "%0, %1 \n" + " " __INS "%0, $0, %3, 1 \n" + " " __SC "%0, %1 \n" : "=&r" (temp), "+m" (*m), "=&r" (res) : "ir" (bit) : "memory"); @@ -386,11 +379,11 @@ static inline int test_and_clear_bit(unsigned long nr, do { __asm__ __volatile__( - " .set mips3 \n" - " " __LL "%0, %1 # test_and_clear_bit \n" + " .set arch=r4000 \n" + " " __LL "%0, %1 # test_and_clear_bit \n" " or %2, %0, %3 \n" " xor %2, %3 \n" - " " __SC "%2, %1 \n" + " " __SC "%2, %1 \n" " .set mips0 \n" : "=&r" (temp), "+m" (*m), "=&r" (res) : "r" (1UL << bit) @@ -427,7 +420,7 @@ static inline int test_and_change_bit(unsigned long nr, unsigned long temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: " __LL "%0, %1 # test_and_change_bit \n" " xor %2, %0, %3 \n" " " __SC "%2, %1 \n" @@ -443,8 +436,8 @@ static inline int test_and_change_bit(unsigned long nr, do { __asm__ __volatile__( - " .set mips3 \n" - " " __LL "%0, %1 # test_and_change_bit \n" + " .set arch=r4000 \n" + " " __LL "%0, %1 # test_and_change_bit \n" " xor %2, %0, %3 \n" " " __SC "\t%2, %1 \n" " .set mips0 \n" diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h index 552a65a0cf2..cbaccebf506 100644 --- a/arch/mips/include/asm/bmips.h +++ b/arch/mips/include/asm/bmips.h @@ -46,8 +46,35 @@ #include <linux/cpumask.h> #include <asm/r4kcache.h> +#include <asm/smp-ops.h> + +extern struct plat_smp_ops bmips43xx_smp_ops; +extern struct plat_smp_ops bmips5000_smp_ops; + +static inline int register_bmips_smp_ops(void) +{ +#if IS_ENABLED(CONFIG_CPU_BMIPS) && IS_ENABLED(CONFIG_SMP) + switch (current_cpu_type()) { + case CPU_BMIPS32: + case CPU_BMIPS3300: + return register_up_smp_ops(); + case CPU_BMIPS4350: + case CPU_BMIPS4380: + register_smp_ops(&bmips43xx_smp_ops); + break; + case CPU_BMIPS5000: + register_smp_ops(&bmips5000_smp_ops); + break; + default: + return -ENODEV; + } + + return 0; +#else + return -ENODEV; +#endif +} -extern struct plat_smp_ops bmips_smp_ops; extern char bmips_reset_nmi_vec; extern char bmips_reset_nmi_vec_end; extern char bmips_smp_movevec; @@ -65,44 +92,33 @@ static inline unsigned long bmips_read_zscm_reg(unsigned int offset) { unsigned long ret; - __asm__ __volatile__( - ".set push\n" - ".set noreorder\n" - "cache %1, 0(%2)\n" - "sync\n" - "_ssnop\n" - "_ssnop\n" - "_ssnop\n" - "_ssnop\n" - "_ssnop\n" - "_ssnop\n" - "_ssnop\n" - "mfc0 %0, $28, 3\n" - "_ssnop\n" - ".set pop\n" - : "=&r" (ret) - : "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset) - : "memory"); + barrier(); + cache_op(Index_Load_Tag_S, ZSCM_REG_BASE + offset); + __sync(); + _ssnop(); + _ssnop(); + _ssnop(); + _ssnop(); + _ssnop(); + _ssnop(); + _ssnop(); + ret = read_c0_ddatalo(); + _ssnop(); + return ret; } static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data) { - __asm__ __volatile__( - ".set push\n" - ".set noreorder\n" - "mtc0 %0, $28, 3\n" - "_ssnop\n" - "_ssnop\n" - "_ssnop\n" - "cache %1, 0(%2)\n" - "_ssnop\n" - "_ssnop\n" - "_ssnop\n" - : /* no outputs */ - : "r" (data), - "i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset) - : "memory"); + write_c0_ddatalo(data); + _ssnop(); + _ssnop(); + _ssnop(); + cache_op(Index_Store_Tag_S, ZSCM_REG_BASE + offset); + _ssnop(); + _ssnop(); + _ssnop(); + barrier(); } #endif /* !defined(__ASSEMBLY__) */ diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h index 7a51d879e6c..1f7ca8b0040 100644 --- a/arch/mips/include/asm/bootinfo.h +++ b/arch/mips/include/asm/bootinfo.h @@ -44,32 +44,38 @@ /* * Valid machtype for group PMC-MSP */ -#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */ -#define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */ -#define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */ -#define MACH_MSP7120_EVAL 3 /* PMC-Sierra MSP7120 Evaluation */ -#define MACH_MSP7120_GW 4 /* PMC-Sierra MSP7120 Residential GW */ -#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ -#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ +#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */ +#define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */ +#define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */ +#define MACH_MSP7120_EVAL 3 /* PMC-Sierra MSP7120 Evaluation */ +#define MACH_MSP7120_GW 4 /* PMC-Sierra MSP7120 Residential GW */ +#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ +#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ /* * Valid machtype for group Mikrotik */ -#define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */ -#define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */ +#define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */ +#define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */ /* * Valid machtype for Loongson family */ -#define MACH_LOONGSON_UNKNOWN 0 -#define MACH_LEMOTE_FL2E 1 -#define MACH_LEMOTE_FL2F 2 -#define MACH_LEMOTE_ML2F7 3 -#define MACH_LEMOTE_YL2F89 4 -#define MACH_DEXXON_GDIUM2F10 5 -#define MACH_LEMOTE_NAS 6 -#define MACH_LEMOTE_LL2F 7 -#define MACH_LOONGSON_END 8 +enum loongson_machine_type { + MACH_LOONGSON_UNKNOWN, + MACH_LEMOTE_FL2E, + MACH_LEMOTE_FL2F, + MACH_LEMOTE_ML2F7, + MACH_LEMOTE_YL2F89, + MACH_DEXXON_GDIUM2F10, + MACH_LEMOTE_NAS, + MACH_LEMOTE_LL2F, + MACH_LEMOTE_A1004, + MACH_LEMOTE_A1101, + MACH_LEMOTE_A1201, + MACH_LEMOTE_A1205, + MACH_LOONGSON_END +}; /* * Valid machtype for group INGENIC @@ -104,6 +110,7 @@ struct boot_mem_map { extern struct boot_mem_map boot_mem_map; extern void add_memory_region(phys_t start, phys_t size, long type); +extern void detect_memory_region(phys_t start, phys_t sz_min, phys_t sz_max); extern void prom_init(void); extern void prom_free_prom_memory(void); @@ -111,6 +118,8 @@ extern void prom_free_prom_memory(void); extern void free_init_pages(const char *what, unsigned long begin, unsigned long end); +extern void (*free_init_pages_eva)(void *begin, void *end); + /* * Initial kernel command line, usually setup by prom_init() */ diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h index 888766ae1f8..de781cf54bc 100644 --- a/arch/mips/include/asm/branch.h +++ b/arch/mips/include/asm/branch.h @@ -8,30 +8,75 @@ #ifndef _ASM_BRANCH_H #define _ASM_BRANCH_H +#include <asm/cpu-features.h> +#include <asm/mipsregs.h> #include <asm/ptrace.h> #include <asm/inst.h> +extern int __isa_exception_epc(struct pt_regs *regs); +extern int __compute_return_epc(struct pt_regs *regs); +extern int __compute_return_epc_for_insn(struct pt_regs *regs, + union mips_instruction insn); +extern int __microMIPS_compute_return_epc(struct pt_regs *regs); +extern int __MIPS16e_compute_return_epc(struct pt_regs *regs); + +/* + * microMIPS bitfields + */ +#define MM_POOL32A_MINOR_MASK 0x3f +#define MM_POOL32A_MINOR_SHIFT 0x6 +#define MM_MIPS32_COND_FC 0x30 + +extern int __mm_isBranchInstr(struct pt_regs *regs, + struct mm_decoded_insn dec_insn, unsigned long *contpc); + +static inline int mm_isBranchInstr(struct pt_regs *regs, + struct mm_decoded_insn dec_insn, unsigned long *contpc) +{ + if (!cpu_has_mmips) + return 0; + + return __mm_isBranchInstr(regs, dec_insn, contpc); +} + static inline int delay_slot(struct pt_regs *regs) { return regs->cp0_cause & CAUSEF_BD; } +static inline void clear_delay_slot(struct pt_regs *regs) +{ + regs->cp0_cause &= ~CAUSEF_BD; +} + +static inline void set_delay_slot(struct pt_regs *regs) +{ + regs->cp0_cause |= CAUSEF_BD; +} + static inline unsigned long exception_epc(struct pt_regs *regs) { - if (!delay_slot(regs)) + if (likely(!delay_slot(regs))) return regs->cp0_epc; + if (get_isa16_mode(regs->cp0_epc)) + return __isa_exception_epc(regs); + return regs->cp0_epc + 4; } #define BRANCH_LIKELY_TAKEN 0x0001 -extern int __compute_return_epc(struct pt_regs *regs); -extern int __compute_return_epc_for_insn(struct pt_regs *regs, - union mips_instruction insn); - static inline int compute_return_epc(struct pt_regs *regs) { + if (get_isa16_mode(regs->cp0_epc)) { + if (cpu_has_mmips) + return __microMIPS_compute_return_epc(regs); + if (cpu_has_mips16) + return __MIPS16e_compute_return_epc(regs); + return regs->cp0_epc; + } + if (!delay_slot(regs)) { regs->cp0_epc += 4; return 0; @@ -40,4 +85,19 @@ static inline int compute_return_epc(struct pt_regs *regs) return __compute_return_epc(regs); } +static inline int MIPS16e_compute_return_epc(struct pt_regs *regs, + union mips16e_instruction *inst) +{ + if (likely(!delay_slot(regs))) { + if (inst->ri.opcode == MIPS16e_extend_op) { + regs->cp0_epc += 4; + return 0; + } + regs->cp0_epc += 2; + return 0; + } + + return __MIPS16e_compute_return_epc(regs); +} + #endif /* _ASM_BRANCH_H */ diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h index 9161e684cb4..0ef11429a70 100644 --- a/arch/mips/include/asm/break.h +++ b/arch/mips/include/asm/break.h @@ -9,25 +9,14 @@ #ifndef __ASM_BREAK_H #define __ASM_BREAK_H +#ifdef __UAPI_ASM_BREAK_H +#error "Error: Do not directly include <uapi/asm/break.h>" +#endif +#include <uapi/asm/break.h> + /* - * The following break codes are or were in use for specific purposes in - * other MIPS operating systems. Linux/MIPS doesn't use all of them. The - * unused ones are here as placeholders; we might encounter them in - * non-Linux/MIPS object files or make use of them in the future. + * Break codes used internally to the kernel. */ -#define BRK_USERBP 0 /* User bp (used by debuggers) */ -#define BRK_KERNELBP 1 /* Break in the kernel */ -#define BRK_ABORT 2 /* Sometimes used by abort(3) to SIGIOT */ -#define BRK_BD_TAKEN 3 /* For bd slot emulation - not implemented */ -#define BRK_BD_NOTTAKEN 4 /* For bd slot emulation - not implemented */ -#define BRK_SSTEPBP 5 /* User bp (used by debuggers) */ -#define BRK_OVERFLOW 6 /* Overflow check */ -#define BRK_DIVZERO 7 /* Divide by zero check */ -#define BRK_RANGE 8 /* Range error check */ -#define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */ -#define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ -#define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ -#define BRK_BUG 512 /* Used by BUG() */ #define BRK_KDB 513 /* Used in KDB_ENTER() */ #define BRK_MEMU 514 /* Used by FPU emulator */ #define BRK_KPROBE_BP 515 /* Kprobe break */ diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h index 69468ded282..e08381a37f8 100644 --- a/arch/mips/include/asm/cacheflush.h +++ b/arch/mips/include/asm/cacheflush.h @@ -113,6 +113,12 @@ unsigned long run_uncached(void *func); extern void *kmap_coherent(struct page *page, unsigned long addr); extern void kunmap_coherent(void); +extern void *kmap_noncoherent(struct page *page, unsigned long addr); + +static inline void kunmap_noncoherent(void) +{ + kunmap_coherent(); +} #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE static inline void flush_kernel_dcache_page(struct page *page) diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 8f99c11ab66..06b9bc7ea14 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -8,62 +8,58 @@ * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle * (C) Copyright 1999 Silicon Graphics, Inc. */ -#ifndef __ASM_CACHEOPS_H -#define __ASM_CACHEOPS_H +#ifndef __ASM_CACHEOPS_H +#define __ASM_CACHEOPS_H /* * Cache Operations available on all MIPS processors with R4000-style caches */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#if defined(CONFIG_CPU_LOONGSON2) -#define Hit_Invalidate_I 0x00 -#else -#define Hit_Invalidate_I 0x10 -#endif -#define Hit_Invalidate_D 0x11 -#define Hit_Writeback_Inv_D 0x15 +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Writeback_Inv_D 0x15 /* * R4000-specific cacheops */ -#define Create_Dirty_Excl_D 0x0d -#define Fill 0x14 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 +#define Create_Dirty_Excl_D 0x0d +#define Fill 0x14 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 /* * R4000SC and R4400SC-specific cacheops */ -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_SD 0x1b -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_SD 0x1b +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f /* * R5000-specific cacheops */ -#define R5K_Page_Invalidate_S 0x17 +#define R5K_Page_Invalidate_S 0x17 /* * RM7000-specific cacheops */ -#define Page_Invalidate_T 0x16 -#define Index_Store_Tag_T 0x0a -#define Index_Load_Tag_T 0x06 +#define Page_Invalidate_T 0x16 +#define Index_Store_Tag_T 0x0a +#define Index_Load_Tag_T 0x06 /* * R10000-specific cacheops @@ -71,17 +67,22 @@ * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. * Most of the _S cacheops are identical to the R4000SC _SD cacheops. */ -#define Index_Writeback_Inv_S 0x03 -#define Index_Load_Tag_S 0x07 -#define Index_Store_Tag_S 0x0B -#define Hit_Invalidate_S 0x13 -#define Cache_Barrier 0x14 -#define Hit_Writeback_Inv_S 0x17 -#define Index_Load_Data_I 0x18 -#define Index_Load_Data_D 0x19 -#define Index_Load_Data_S 0x1b -#define Index_Store_Data_I 0x1c -#define Index_Store_Data_D 0x1d -#define Index_Store_Data_S 0x1f +#define Index_Writeback_Inv_S 0x03 +#define Index_Load_Tag_S 0x07 +#define Index_Store_Tag_S 0x0B +#define Hit_Invalidate_S 0x13 +#define Cache_Barrier 0x14 +#define Hit_Writeback_Inv_S 0x17 +#define Index_Load_Data_I 0x18 +#define Index_Load_Data_D 0x19 +#define Index_Load_Data_S 0x1b +#define Index_Store_Data_I 0x1c +#define Index_Store_Data_D 0x1d +#define Index_Store_Data_S 0x1f + +/* + * Loongson2-specific cacheops + */ +#define Hit_Invalidate_I_Loongson2 0x00 #endif /* __ASM_CACHEOPS_H */ diff --git a/arch/mips/include/asm/checksum.h b/arch/mips/include/asm/checksum.h index f2f7c6c264d..3418c51e115 100644 --- a/arch/mips/include/asm/checksum.h +++ b/arch/mips/include/asm/checksum.h @@ -7,6 +7,7 @@ * Copyright (C) 1999 Silicon Graphics, Inc. * Copyright (C) 2001 Thiemo Seufer. * Copyright (C) 2002 Maciej W. Rozycki + * Copyright (C) 2014 Imagination Technologies Ltd. */ #ifndef _ASM_CHECKSUM_H #define _ASM_CHECKSUM_H @@ -29,9 +30,13 @@ */ __wsum csum_partial(const void *buff, int len, __wsum sum); -__wsum __csum_partial_copy_user(const void *src, void *dst, - int len, __wsum sum, int *err_ptr); +__wsum __csum_partial_copy_kernel(const void *src, void *dst, + int len, __wsum sum, int *err_ptr); +__wsum __csum_partial_copy_from_user(const void *src, void *dst, + int len, __wsum sum, int *err_ptr); +__wsum __csum_partial_copy_to_user(const void *src, void *dst, + int len, __wsum sum, int *err_ptr); /* * this is a new version of the above that records errors it finds in *errp, * but continues and zeros the rest of the buffer. @@ -41,8 +46,26 @@ __wsum csum_partial_copy_from_user(const void __user *src, void *dst, int len, __wsum sum, int *err_ptr) { might_fault(); - return __csum_partial_copy_user((__force void *)src, dst, - len, sum, err_ptr); + if (segment_eq(get_fs(), get_ds())) + return __csum_partial_copy_kernel((__force void *)src, dst, + len, sum, err_ptr); + else + return __csum_partial_copy_from_user((__force void *)src, dst, + len, sum, err_ptr); +} + +#define _HAVE_ARCH_COPY_AND_CSUM_FROM_USER +static inline +__wsum csum_and_copy_from_user(const void __user *src, void *dst, + int len, __wsum sum, int *err_ptr) +{ + if (access_ok(VERIFY_READ, src, len)) + return csum_partial_copy_from_user(src, dst, len, sum, + err_ptr); + if (len) + *err_ptr = -EFAULT; + + return sum; } /* @@ -54,9 +77,16 @@ __wsum csum_and_copy_to_user(const void *src, void __user *dst, int len, __wsum sum, int *err_ptr) { might_fault(); - if (access_ok(VERIFY_WRITE, dst, len)) - return __csum_partial_copy_user(src, (__force void *)dst, - len, sum, err_ptr); + if (access_ok(VERIFY_WRITE, dst, len)) { + if (segment_eq(get_fs(), get_ds())) + return __csum_partial_copy_kernel(src, + (__force void *)dst, + len, sum, err_ptr); + else + return __csum_partial_copy_to_user(src, + (__force void *)dst, + len, sum, err_ptr); + } if (len) *err_ptr = -EFAULT; @@ -194,7 +224,7 @@ static inline __sum16 ip_compute_csum(const void *buff, int len) #define _HAVE_ARCH_IPV6_CSUM static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, - const struct in6_addr *daddr, + const struct in6_addr *daddr, __u32 len, unsigned short proto, __wsum sum) { diff --git a/arch/mips/include/asm/clkdev.h b/arch/mips/include/asm/clkdev.h index 262475414e5..1b3ad7b09dc 100644 --- a/arch/mips/include/asm/clkdev.h +++ b/arch/mips/include/asm/clkdev.h @@ -14,8 +14,10 @@ #include <linux/slab.h> +#ifndef CONFIG_COMMON_CLK #define __clk_get(clk) ({ 1; }) #define __clk_put(clk) do { } while (0) +#endif static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) { diff --git a/arch/mips/include/asm/clock.h b/arch/mips/include/asm/clock.h index c9456e7a728..778e32d817b 100644 --- a/arch/mips/include/asm/clock.h +++ b/arch/mips/include/asm/clock.h @@ -6,8 +6,6 @@ #include <linux/seq_file.h> #include <linux/clk.h> -extern void (*cpu_wait) (void); - struct clk; struct clk_ops { diff --git a/arch/mips/include/asm/cmp.h b/arch/mips/include/asm/cmp.h index 89a73fb93ae..033d97303c8 100644 --- a/arch/mips/include/asm/cmp.h +++ b/arch/mips/include/asm/cmp.h @@ -10,7 +10,6 @@ extern void cmp_smp_setup(void); extern void cmp_smp_finish(void); extern void cmp_boot_secondary(int cpu, struct task_struct *t); extern void cmp_init_secondary(void); -extern void cmp_cpus_done(void); extern void cmp_prepare_cpus(unsigned int max_cpus); /* This is platform specific */ diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h index eee10dc07ac..eefcaa363a8 100644 --- a/arch/mips/include/asm/cmpxchg.h +++ b/arch/mips/include/asm/cmpxchg.h @@ -22,11 +22,11 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) unsigned long dummy; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: ll %0, %3 # xchg_u32 \n" " .set mips0 \n" " move %2, %z4 \n" - " .set mips3 \n" + " .set arch=r4000 \n" " sc %2, %1 \n" " beqzl %2, 1b \n" " .set mips0 \n" @@ -38,11 +38,11 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) do { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" " ll %0, %3 # xchg_u32 \n" " .set mips0 \n" " move %2, %z4 \n" - " .set mips3 \n" + " .set arch=r4000 \n" " sc %2, %1 \n" " .set mips0 \n" : "=&r" (retval), "=m" (*m), "=&r" (dummy) @@ -74,7 +74,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) unsigned long dummy; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1: lld %0, %3 # xchg_u64 \n" " move %2, %z4 \n" " scd %2, %1 \n" @@ -88,7 +88,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) do { __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" " lld %0, %3 # xchg_u64 \n" " move %2, %z4 \n" " scd %2, %1 \n" @@ -145,12 +145,12 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " .set mips3 \n" \ - "1: " ld " %0, %2 # __cmpxchg_asm \n" \ + " .set arch=r4000 \n" \ + "1: " ld " %0, %2 # __cmpxchg_asm \n" \ " bne %0, %z3, 2f \n" \ " .set mips0 \n" \ " move $1, %z4 \n" \ - " .set mips3 \n" \ + " .set arch=r4000 \n" \ " " st " $1, %1 \n" \ " beqzl $1, 1b \n" \ "2: \n" \ @@ -162,12 +162,12 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " .set mips3 \n" \ - "1: " ld " %0, %2 # __cmpxchg_asm \n" \ + " .set arch=r4000 \n" \ + "1: " ld " %0, %2 # __cmpxchg_asm \n" \ " bne %0, %z3, 2f \n" \ " .set mips0 \n" \ " move $1, %z4 \n" \ - " .set mips3 \n" \ + " .set arch=r4000 \n" \ " " st " $1, %1 \n" \ " beqz $1, 1b \n" \ " .set pop \n" \ @@ -205,7 +205,7 @@ extern void __cmpxchg_called_with_bad_pointer(void); \ switch (sizeof(*(__ptr))) { \ case 4: \ - __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); \ + __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); \ break; \ case 8: \ if (sizeof(long) == 8) { \ diff --git a/arch/mips/include/asm/compat-signal.h b/arch/mips/include/asm/compat-signal.h index 6599a901b63..64e0b9343b8 100644 --- a/arch/mips/include/asm/compat-signal.h +++ b/arch/mips/include/asm/compat-signal.h @@ -18,9 +18,9 @@ static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d, BUG_ON(sizeof(*d) != sizeof(*s)); BUG_ON(_NSIG_WORDS != 2); - err = __put_user(s->sig[0], &d->sig[0]); + err = __put_user(s->sig[0], &d->sig[0]); err |= __put_user(s->sig[0] >> 32, &d->sig[1]); - err |= __put_user(s->sig[1], &d->sig[2]); + err |= __put_user(s->sig[1], &d->sig[2]); err |= __put_user(s->sig[1] >> 32, &d->sig[3]); return err; diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h index 3c5d1464b7b..c4bd54a7f5c 100644 --- a/arch/mips/include/asm/compat.h +++ b/arch/mips/include/asm/compat.h @@ -120,7 +120,7 @@ struct compat_statfs { typedef u32 compat_old_sigset_t; /* at least 32 bits */ -#define _COMPAT_NSIG 128 /* Don't ask !$@#% ... */ +#define _COMPAT_NSIG 128 /* Don't ask !$@#% ... */ #define _COMPAT_NSIG_BPW 32 typedef u32 compat_sigset_word; @@ -168,7 +168,7 @@ typedef struct compat_siginfo { s32 _addr; /* faulting insn/memory ref. */ } _sigfault; - /* SIGPOLL, SIGXFSZ (To do ...) */ + /* SIGPOLL, SIGXFSZ (To do ...) */ struct { int _band; /* POLL_IN, POLL_OUT, POLL_MSG */ int _fd; @@ -179,7 +179,7 @@ typedef struct compat_siginfo { timer_t _tid; /* timer id */ int _overrun; /* overrun count */ compat_sigval_t _sigval;/* same as below */ - int _sys_private; /* not to be passed to user */ + int _sys_private; /* not to be passed to user */ } _timer; /* POSIX.1b signals */ @@ -288,6 +288,14 @@ struct compat_shmid64_ds { compat_ulong_t __unused2; }; +/* MIPS has unusual order of fields in stack_t */ +typedef struct compat_sigaltstack { + compat_uptr_t ss_sp; + compat_size_t ss_size; + int ss_flags; +} compat_stack_t; +#define compat_sigaltstack compat_sigaltstack + static inline int is_compat_task(void) { return test_thread_flag(TIF_32BIT_ADDR); diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h index 3532e2c5f09..c1516cc0285 100644 --- a/arch/mips/include/asm/cop2.h +++ b/arch/mips/include/asm/cop2.h @@ -11,6 +11,35 @@ #include <linux/notifier.h> +#if defined(CONFIG_CPU_CAVIUM_OCTEON) + +extern void octeon_cop2_save(struct octeon_cop2_state *); +extern void octeon_cop2_restore(struct octeon_cop2_state *); + +#define cop2_save(r) octeon_cop2_save(r) +#define cop2_restore(r) octeon_cop2_restore(r) + +#define cop2_present 1 +#define cop2_lazy_restore 1 + +#elif defined(CONFIG_CPU_XLP) + +extern void nlm_cop2_save(struct nlm_cop2_state *); +extern void nlm_cop2_restore(struct nlm_cop2_state *); +#define cop2_save(r) nlm_cop2_save(r) +#define cop2_restore(r) nlm_cop2_restore(r) + +#define cop2_present 1 +#define cop2_lazy_restore 0 + +#else + +#define cop2_present 0 +#define cop2_lazy_restore 0 +#define cop2_save(r) +#define cop2_restore(r) +#endif + enum cu2_ops { CU2_EXCEPTION, CU2_LWC2_OP, diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index c507b931b48..c7d8c997d93 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -13,10 +13,6 @@ #include <asm/cpu-info.h> #include <cpu-feature-overrides.h> -#ifndef current_cpu_type -#define current_cpu_type() current_cpu_data.cputype -#endif - /* * SMP assumption: Options of CPU 0 are a superset of all processors. * This is true for all known MIPS systems. @@ -24,6 +20,25 @@ #ifndef cpu_has_tlb #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) #endif +#ifndef cpu_has_tlbinv +#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV) +#endif +#ifndef cpu_has_segments +#define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS) +#endif +#ifndef cpu_has_eva +#define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA) +#endif + +/* + * For the moment we don't consider R6000 and R8000 so we can assume that + * anything that doesn't support R4000-style exceptions and interrupts is + * R3000-like. Users should still treat these two macro definitions as + * opaque. + */ +#ifndef cpu_has_3kex +#define cpu_has_3kex (!cpu_has_4kex) +#endif #ifndef cpu_has_4kex #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) #endif @@ -87,17 +102,31 @@ #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) #endif #ifndef cpu_has_mdmx -#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) +#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) #endif #ifndef cpu_has_mips3d -#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) +#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) #endif #ifndef cpu_has_smartmips -#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) +#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) #endif + #ifndef cpu_has_rixi -#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) +# ifdef CONFIG_64BIT +# define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) +# else /* CONFIG_32BIT */ +# define cpu_has_rixi ((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits) +# endif #endif + +#ifndef cpu_has_mmips +# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS +# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) +# else +# define cpu_has_mmips 0 +# endif +#endif + #ifndef cpu_has_vtag_icache #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) #endif @@ -110,9 +139,12 @@ #ifndef cpu_has_pindexed_dcache #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) #endif +#ifndef cpu_has_local_ebase +#define cpu_has_local_ebase 1 +#endif /* - * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors + * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors * such as the R10000 have I-Caches that snoop local stores; the embedded ones * don't. For maintaining I-cache coherency this means we need to flush the * D-cache all the way back to whever the I-cache does refills from, so the @@ -130,26 +162,49 @@ #endif #endif -# ifndef cpu_has_mips32r1 +#ifndef cpu_has_mips_2 +# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) +#endif +#ifndef cpu_has_mips_3 +# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III) +#endif +#ifndef cpu_has_mips_4 +# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV) +#endif +#ifndef cpu_has_mips_5 +# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) +#endif +#ifndef cpu_has_mips32r1 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) -# endif -# ifndef cpu_has_mips32r2 +#endif +#ifndef cpu_has_mips32r2 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) -# endif -# ifndef cpu_has_mips64r1 +#endif +#ifndef cpu_has_mips64r1 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) -# endif -# ifndef cpu_has_mips64r2 +#endif +#ifndef cpu_has_mips64r2 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) -# endif +#endif /* * Shortcuts ... */ +#define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5) +#define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5) +#define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5) + +#define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r) +#define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r) +#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r) +#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r) + +#define cpu_has_mips_4_5_r2 (cpu_has_mips_4_5 | cpu_has_mips_r2) + #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2) #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) -#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) -#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) +#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) +#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ cpu_has_mips64r1 | cpu_has_mips64r2) @@ -159,13 +214,13 @@ /* * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other - * pre-MIPS32/MIPS53 processors have CLO, CLZ. The IDT RC64574 is 64-bit and + * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. */ -# ifndef cpu_has_clo_clz -# define cpu_has_clo_clz cpu_has_mips_r -# endif +#ifndef cpu_has_clo_clz +#define cpu_has_clo_clz cpu_has_mips_r +#endif #ifndef cpu_has_dsp #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) @@ -260,4 +315,14 @@ #define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI) #endif +#ifndef cpu_has_vz +#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ) +#endif + +#if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa) +# define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA) +#elif !defined(cpu_has_msa) +# define cpu_has_msa 0 +#endif + #endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index c454550eb0c..47d5967ce7e 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h @@ -39,41 +39,40 @@ struct cache_desc { #define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */ struct cpuinfo_mips { - unsigned int udelay_val; - unsigned int asid_cache; + unsigned long asid_cache; /* * Capability and feature descriptor structure for MIPS CPU */ unsigned long options; unsigned long ases; + unsigned int udelay_val; unsigned int processor_id; unsigned int fpu_id; + unsigned int msa_id; unsigned int cputype; int isa_level; int tlbsize; - struct cache_desc icache; /* Primary I-cache */ - struct cache_desc dcache; /* Primary D or combined I/D cache */ - struct cache_desc scache; /* Secondary cache */ - struct cache_desc tcache; /* Tertiary/split secondary cache */ - int srsets; /* Shadow register sets */ + int tlbsizevtlb; + int tlbsizeftlbsets; + int tlbsizeftlbways; + struct cache_desc icache; /* Primary I-cache */ + struct cache_desc dcache; /* Primary D or combined I/D cache */ + struct cache_desc scache; /* Secondary cache */ + struct cache_desc tcache; /* Tertiary/split secondary cache */ + int srsets; /* Shadow register sets */ int core; /* physical core number */ #ifdef CONFIG_64BIT - int vmbits; /* Virtual memory size in bits */ + int vmbits; /* Virtual memory size in bits */ #endif -#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) +#ifdef CONFIG_MIPS_MT_SMP /* - * In the MIPS MT "SMTC" model, each TC is considered - * to be a "CPU" for the purposes of scheduling, but - * exception resources, ASID spaces, etc, are common - * to all TCs within the same VPE. + * There is not necessarily a 1:1 mapping of VPE num to CPU number + * in particular on multi-core systems. */ - int vpe_id; /* Virtual Processor number */ -#endif -#ifdef CONFIG_MIPS_MT_SMTC - int tc_id; /* Thread Context number */ + int vpe_id; /* Virtual Processor number */ #endif - void *data; /* Additional data */ + void *data; /* Additional data */ unsigned int watch_reg_count; /* Number that exist */ unsigned int watch_reg_use_cnt; /* Usable by ptrace */ #define NUM_WATCH_REGS 4 @@ -84,6 +83,7 @@ struct cpuinfo_mips { extern struct cpuinfo_mips cpu_data[]; #define current_cpu_data cpu_data[smp_processor_id()] #define raw_current_cpu_data cpu_data[raw_smp_processor_id()] +#define boot_cpu_data cpu_data[0] extern void cpu_probe(void); extern void cpu_report(void); @@ -91,4 +91,31 @@ extern void cpu_report(void); extern const char *__cpu_name[]; #define cpu_name_string() __cpu_name[smp_processor_id()] +struct seq_file; +struct notifier_block; + +extern int register_proc_cpuinfo_notifier(struct notifier_block *nb); +extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v); + +#define proc_cpuinfo_notifier(fn, pri) \ +({ \ + static struct notifier_block fn##_nb = { \ + .notifier_call = fn, \ + .priority = pri \ + }; \ + \ + register_proc_cpuinfo_notifier(&fn##_nb); \ +}) + +struct proc_cpuinfo_notifier_args { + struct seq_file *m; + unsigned long n; +}; + +#ifdef CONFIG_MIPS_MT_SMP +# define cpu_vpe_id(cpuinfo) ((cpuinfo)->vpe_id) +#else +# define cpu_vpe_id(cpuinfo) 0 +#endif + #endif /* __ASM_CPU_INFO_H */ diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h new file mode 100644 index 00000000000..b4e2bd87df5 --- /dev/null +++ b/arch/mips/include/asm/cpu-type.h @@ -0,0 +1,216 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + */ +#ifndef __ASM_CPU_TYPE_H +#define __ASM_CPU_TYPE_H + +#include <linux/smp.h> +#include <linux/compiler.h> + +static inline int __pure __get_cpu_type(const int cpu_type) +{ + switch (cpu_type) { +#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \ + defined(CONFIG_SYS_HAS_CPU_LOONGSON2F) + case CPU_LOONGSON2: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_LOONGSON3 + case CPU_LOONGSON3: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B + case CPU_LOONGSON1: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1 + case CPU_4KC: + case CPU_ALCHEMY: + case CPU_PR4450: + case CPU_JZRISC: +#endif + +#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) || \ + defined(CONFIG_SYS_HAS_CPU_MIPS32_R2) + case CPU_4KEC: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2 + case CPU_4KSC: + case CPU_24K: + case CPU_34K: + case CPU_1004K: + case CPU_74K: + case CPU_M14KC: + case CPU_M14KEC: + case CPU_INTERAPTIV: + case CPU_PROAPTIV: + case CPU_P5600: + case CPU_M5150: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1 + case CPU_5KC: + case CPU_5KE: + case CPU_20KC: + case CPU_25KF: + case CPU_SB1: + case CPU_SB1A: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R2 + /* + * All MIPS64 R2 processors have their own special symbols. That is, + * there currently is no pure R2 core + */ +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R3000 + case CPU_R2000: + case CPU_R3000: + case CPU_R3000A: + case CPU_R3041: + case CPU_R3051: + case CPU_R3052: + case CPU_R3081: + case CPU_R3081E: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_TX39XX + case CPU_TX3912: + case CPU_TX3922: + case CPU_TX3927: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_VR41XX + case CPU_VR41XX: + case CPU_VR4111: + case CPU_VR4121: + case CPU_VR4122: + case CPU_VR4131: + case CPU_VR4133: + case CPU_VR4181: + case CPU_VR4181A: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R4300 + case CPU_R4300: + case CPU_R4310: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R4X00 + case CPU_R4000PC: + case CPU_R4000SC: + case CPU_R4000MC: + case CPU_R4200: + case CPU_R4400PC: + case CPU_R4400SC: + case CPU_R4400MC: + case CPU_R4600: + case CPU_R4700: + case CPU_R4640: + case CPU_R4650: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_TX49XX + case CPU_TX49XX: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R5000 + case CPU_R5000: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R5432 + case CPU_R5432: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R5500 + case CPU_R5500: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R6000 + case CPU_R6000: + case CPU_R6000A: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_NEVADA + case CPU_NEVADA: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R8000 + case CPU_R8000: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_R10000 + case CPU_R10000: + case CPU_R12000: + case CPU_R14000: +#endif +#ifdef CONFIG_SYS_HAS_CPU_RM7000 + case CPU_RM7000: + case CPU_SR71000: +#endif +#ifdef CONFIG_SYS_HAS_CPU_SB1 + case CPU_SB1: + case CPU_SB1A: +#endif +#ifdef CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON + case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: + case CPU_CAVIUM_OCTEON2: + case CPU_CAVIUM_OCTEON3: +#endif + +#if defined(CONFIG_SYS_HAS_CPU_BMIPS32_3300) || \ + defined (CONFIG_SYS_HAS_CPU_MIPS32_R1) + case CPU_BMIPS32: + case CPU_BMIPS3300: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_BMIPS4350 + case CPU_BMIPS4350: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380 + case CPU_BMIPS4380: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_BMIPS5000 + case CPU_BMIPS5000: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_XLP + case CPU_XLP: +#endif + +#ifdef CONFIG_SYS_HAS_CPU_XLR + case CPU_XLR: +#endif + break; + default: + unreachable(); + } + + return cpu_type; +} + +static inline int __pure current_cpu_type(void) +{ + const int cpu_type = current_cpu_data.cputype; + + return __get_cpu_type(cpu_type); +} + +static inline int __pure boot_cpu_type(void) +{ + const int cpu_type = cpu_data[0].cputype; + + return __get_cpu_type(cpu_type); +} + +#endif /* __ASM_CPU_TYPE_H */ diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 90112adb194..129d08701e9 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -1,35 +1,42 @@ /* * cpu.h: Values of the PRId register used to match up - * various MIPS cpu types. + * various MIPS cpu types. * * Copyright (C) 1996 David S. Miller (davem@davemloft.net) - * Copyright (C) 2004 Maciej W. Rozycki + * Copyright (C) 2004, 2013 Maciej W. Rozycki */ #ifndef _ASM_CPU_H #define _ASM_CPU_H -/* Assigned Company values for bits 23:16 of the PRId Register - (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from - MTI, the PRId register is defined in this (backwards compatible) - way: +/* + As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0 + register 15, select 0) is defined in this (backwards compatible) way: +----------------+----------------+----------------+----------------+ - | Company Options| Company ID | Processor ID | Revision | + | Company Options| Company ID | Processor ID | Revision | +----------------+----------------+----------------+----------------+ - 31 24 23 16 15 8 7 + 31 24 23 16 15 8 7 I don't have docs for all the previous processors, but my impression is that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 spec. */ +#define PRID_OPT_MASK 0xff000000 + +/* + * Assigned Company values for bits 23:16 of the PRId register. + */ + +#define PRID_COMP_MASK 0xff0000 + #define PRID_COMP_LEGACY 0x000000 #define PRID_COMP_MIPS 0x010000 #define PRID_COMP_BROADCOM 0x020000 #define PRID_COMP_ALCHEMY 0x030000 #define PRID_COMP_SIBYTE 0x040000 #define PRID_COMP_SANDCRAFT 0x050000 -#define PRID_COMP_NXP 0x060000 +#define PRID_COMP_NXP 0x060000 #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 @@ -38,10 +45,17 @@ #define PRID_COMP_INGENIC 0xd00000 /* - * Assigned values for the product ID register. In order to detect a - * certain CPU type exactly eventually additional registers may need to - * be examined. These are valid when 23:16 == PRID_COMP_LEGACY + * Assigned Processor ID (implementation) values for bits 15:8 of the PRId + * register. In order to detect a certain CPU type exactly eventually + * additional registers may need to be examined. + */ + +#define PRID_IMP_MASK 0xff00 + +/* + * These are valid when 23:16 == PRID_COMP_LEGACY */ + #define PRID_IMP_R2000 0x0100 #define PRID_IMP_AU1_REV1 0x0100 #define PRID_IMP_AU1_REV2 0x0200 @@ -68,10 +82,10 @@ #define PRID_IMP_RM7000 0x2700 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ #define PRID_IMP_RM9000 0x3400 -#define PRID_IMP_LOONGSON1 0x4200 +#define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */ #define PRID_IMP_R5432 0x5400 #define PRID_IMP_R5500 0x5500 -#define PRID_IMP_LOONGSON2 0x6300 +#define PRID_IMP_LOONGSON_64 0x6300 /* Loongson-2/3 */ #define PRID_IMP_UNKNOWN 0xff00 @@ -96,19 +110,26 @@ #define PRID_IMP_1004K 0x9900 #define PRID_IMP_1074K 0x9a00 #define PRID_IMP_M14KC 0x9c00 +#define PRID_IMP_M14KEC 0x9e00 +#define PRID_IMP_INTERAPTIV_UP 0xa000 +#define PRID_IMP_INTERAPTIV_MP 0xa100 +#define PRID_IMP_PROAPTIV_UP 0xa200 +#define PRID_IMP_PROAPTIV_MP 0xa300 +#define PRID_IMP_M5150 0xa700 +#define PRID_IMP_P5600 0xa800 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE */ -#define PRID_IMP_SB1 0x0100 -#define PRID_IMP_SB1A 0x1100 +#define PRID_IMP_SB1 0x0100 +#define PRID_IMP_SB1A 0x1100 /* * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT */ -#define PRID_IMP_SR71000 0x0400 +#define PRID_IMP_SR71000 0x0400 /* * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM @@ -140,12 +161,15 @@ #define PRID_IMP_CAVIUM_CN68XX 0x9100 #define PRID_IMP_CAVIUM_CN66XX 0x9200 #define PRID_IMP_CAVIUM_CN61XX 0x9300 +#define PRID_IMP_CAVIUM_CNF71XX 0x9400 +#define PRID_IMP_CAVIUM_CN78XX 0x9500 +#define PRID_IMP_CAVIUM_CN70XX 0x9600 /* * These are the PRID's for when 23:16 == PRID_COMP_INGENIC */ -#define PRID_IMP_JZRISC 0x0200 +#define PRID_IMP_JZRISC 0x0200 /* * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC @@ -175,22 +199,29 @@ #define PRID_IMP_NETLOGIC_XLP8XX 0x1000 #define PRID_IMP_NETLOGIC_XLP3XX 0x1100 +#define PRID_IMP_NETLOGIC_XLP2XX 0x1200 +#define PRID_IMP_NETLOGIC_XLP9XX 0x1500 +#define PRID_IMP_NETLOGIC_XLP5XX 0x1300 /* - * Definitions for 7:0 on legacy processors + * Particular Revision values for bits 7:0 of the PRId register. */ #define PRID_REV_MASK 0x00ff +/* + * Definitions for 7:0 on legacy processors + */ + #define PRID_REV_TX4927 0x0022 #define PRID_REV_TX4937 0x0030 #define PRID_REV_R4400 0x0040 #define PRID_REV_R3000A 0x0030 #define PRID_REV_R3000 0x0020 #define PRID_REV_R2000A 0x0010 -#define PRID_REV_TX3912 0x0010 -#define PRID_REV_TX3922 0x0030 -#define PRID_REV_TX3927 0x0040 +#define PRID_REV_TX3912 0x0010 +#define PRID_REV_TX3922 0x0030 +#define PRID_REV_TX3927 0x0040 #define PRID_REV_VR4111 0x0050 #define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ #define PRID_REV_VR4121 0x0060 @@ -201,6 +232,7 @@ #define PRID_REV_LOONGSON1B 0x0020 #define PRID_REV_LOONGSON2E 0x0002 #define PRID_REV_LOONGSON2F 0x0003 +#define PRID_REV_LOONGSON3A 0x0005 /* * Older processors used to encode processor version and revision in two @@ -217,13 +249,17 @@ * FPU implementation/revision register (CP1 control register 0). * * +---------------------------------+----------------+----------------+ - * | 0 | Implementation | Revision | + * | 0 | Implementation | Revision | * +---------------------------------+----------------+----------------+ - * 31 16 15 8 7 0 + * 31 16 15 8 7 0 */ +#define FPIR_IMP_MASK 0xff00 + #define FPIR_IMP_NONE 0x0000 +#if !defined(__ASSEMBLY__) + enum cpu_type_enum { CPU_UNKNOWN, @@ -246,7 +282,7 @@ enum cpu_type_enum { CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, - CPU_SR71000, CPU_RM9000, CPU_TX49XX, + CPU_SR71000, CPU_TX49XX, /* * R8000 class processors @@ -264,34 +300,35 @@ enum cpu_type_enum { CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, + CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, CPU_M5150, /* * MIPS64 class processors */ CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, - CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, - CPU_XLR, CPU_XLP, + CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, + CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_LAST }; +#endif /* !__ASSEMBLY */ /* * ISA Level encodings * */ -#define MIPS_CPU_ISA_I 0x00000001 -#define MIPS_CPU_ISA_II 0x00000002 -#define MIPS_CPU_ISA_III 0x00000004 -#define MIPS_CPU_ISA_IV 0x00000008 -#define MIPS_CPU_ISA_V 0x00000010 -#define MIPS_CPU_ISA_M32R1 0x00000020 -#define MIPS_CPU_ISA_M32R2 0x00000040 -#define MIPS_CPU_ISA_M64R1 0x00000080 -#define MIPS_CPU_ISA_M64R2 0x00000100 - -#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ - MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2) +#define MIPS_CPU_ISA_II 0x00000001 +#define MIPS_CPU_ISA_III 0x00000002 +#define MIPS_CPU_ISA_IV 0x00000004 +#define MIPS_CPU_ISA_V 0x00000008 +#define MIPS_CPU_ISA_M32R1 0x00000010 +#define MIPS_CPU_ISA_M32R2 0x00000020 +#define MIPS_CPU_ISA_M64R1 0x00000040 +#define MIPS_CPU_ISA_M64R2 0x00000080 + +#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \ + MIPS_CPU_ISA_M32R2) #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) @@ -322,6 +359,10 @@ enum cpu_type_enum { #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ #define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ #define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */ +#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */ +#define MIPS_CPU_TLBINV 0x02000000 /* CPU supports TLBINV/F */ +#define MIPS_CPU_SEGMENTS 0x04000000 /* CPU supports Segmentation Control registers */ +#define MIPS_CPU_EVA 0x80000000 /* CPU supports Enhanced Virtual Addressing */ /* * CPU ASE encodings @@ -333,6 +374,7 @@ enum cpu_type_enum { #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ #define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ - +#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */ +#define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */ #endif /* _ASM_CPU_H */ diff --git a/arch/mips/include/asm/cputime.h b/arch/mips/include/asm/cputime.h deleted file mode 100644 index c00eacbdd97..00000000000 --- a/arch/mips/include/asm/cputime.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __MIPS_CPUTIME_H -#define __MIPS_CPUTIME_H - -#include <asm-generic/cputime.h> - -#endif /* __MIPS_CPUTIME_H */ diff --git a/arch/mips/include/asm/current.h b/arch/mips/include/asm/current.h deleted file mode 100644 index 4c51401b553..00000000000 --- a/arch/mips/include/asm/current.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/current.h> diff --git a/arch/mips/include/asm/dec/ioasic.h b/arch/mips/include/asm/dec/ioasic.h index 98badd6bf22..be4d62a5a10 100644 --- a/arch/mips/include/asm/dec/ioasic.h +++ b/arch/mips/include/asm/dec/ioasic.h @@ -33,6 +33,6 @@ static inline u32 ioasic_read(unsigned int reg) extern void init_ioasic_irqs(int base); -extern void dec_ioasic_clocksource_init(void); +extern int dec_ioasic_clocksource_init(void); #endif /* __ASM_DEC_IOASIC_H */ diff --git a/arch/mips/include/asm/dec/ioasic_addrs.h b/arch/mips/include/asm/dec/ioasic_addrs.h index 4cbc1f8a112..8bd95971fe2 100644 --- a/arch/mips/include/asm/dec/ioasic_addrs.h +++ b/arch/mips/include/asm/dec/ioasic_addrs.h @@ -25,20 +25,20 @@ */ #define IOASIC_SYS_ROM (0*IOASIC_SLOT_SIZE) /* system board ROM */ #define IOASIC_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */ -#define IOASIC_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ -#define IOASIC_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ -#define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE) /* SCC #0 */ +#define IOASIC_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ +#define IOASIC_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ +#define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE) /* SCC #0 */ #define IOASIC_VDAC_HI (5*IOASIC_SLOT_SIZE) /* VDAC (maxine) */ -#define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE) /* SCC #1 (3min, 3max+) */ +#define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE) /* SCC #1 (3min, 3max+) */ #define IOASIC_VDAC_LO (7*IOASIC_SLOT_SIZE) /* VDAC (maxine) */ -#define IOASIC_TOY (8*IOASIC_SLOT_SIZE) /* RTC */ -#define IOASIC_ISDN (9*IOASIC_SLOT_SIZE) /* ISDN (maxine) */ +#define IOASIC_TOY (8*IOASIC_SLOT_SIZE) /* RTC */ +#define IOASIC_ISDN (9*IOASIC_SLOT_SIZE) /* ISDN (maxine) */ #define IOASIC_ERRADDR (9*IOASIC_SLOT_SIZE) /* bus error address (3max+) */ -#define IOASIC_CHKSYN (10*IOASIC_SLOT_SIZE) /* ECC syndrome (3max+) */ +#define IOASIC_CHKSYN (10*IOASIC_SLOT_SIZE) /* ECC syndrome (3max+) */ #define IOASIC_ACC_BUS (10*IOASIC_SLOT_SIZE) /* ACCESS.bus (maxine) */ -#define IOASIC_MCR (11*IOASIC_SLOT_SIZE) /* memory control (3max+) */ -#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */ -#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ +#define IOASIC_MCR (11*IOASIC_SLOT_SIZE) /* memory control (3max+) */ +#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */ +#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ #define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */ #define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */ #define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ diff --git a/arch/mips/include/asm/dec/kn05.h b/arch/mips/include/asm/dec/kn05.h index 56d22dc8803..8e14f677e5e 100644 --- a/arch/mips/include/asm/dec/kn05.h +++ b/arch/mips/include/asm/dec/kn05.h @@ -49,12 +49,20 @@ #define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ /* + * MB ASIC interrupt bits. + */ +#define KN4K_MB_INR_MB 4 /* ??? */ +#define KN4K_MB_INR_MT 3 /* memory, I/O bus read/write errors */ +#define KN4K_MB_INR_RES_2 2 /* unused */ +#define KN4K_MB_INR_RTC 1 /* RTC */ +#define KN4K_MB_INR_TC 0 /* I/O ASIC cascade */ + +/* * Bits for the MB interrupt register. * The register appears read-only. */ -#define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */ -#define KN4K_MB_INT_RTC (1<<1) /* RTC? */ -#define KN4K_MB_INT_MT (1<<3) /* I/O ASIC cascade */ +#define KN4K_MB_INT_IRQ (0x1f<<0) /* CPU Int[4:0] status. */ +#define KN4K_MB_INT_IRQ_N(n) (1<<(n)) /* Individual status bits. */ /* * Bits for the MB control & status register. @@ -70,6 +78,7 @@ #define KN4K_MB_CSR_NC (1<<14) /* ??? */ #define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ #define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */ +#define KN4K_MB_CSR_MSK_N(n) (1<<((n)+16)) /* Individual mask bits. */ #define KN4K_MB_CSR_FW (1<<21) /* ??? */ #define KN4K_MB_CSR_W (1<<31) /* ??? */ diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h index c0ead631384..b59a2103b61 100644 --- a/arch/mips/include/asm/dec/prom.h +++ b/arch/mips/include/asm/dec/prom.h @@ -113,31 +113,31 @@ extern int (*__pmax_close)(int); #define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \ __asm__(#fun " = call_o32") -int __DEC_PROM_O32(_rex_bootinit, (int (*)(void))); -int __DEC_PROM_O32(_rex_bootread, (int (*)(void))); -int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), memmap *)); +int __DEC_PROM_O32(_rex_bootinit, (int (*)(void), void *)); +int __DEC_PROM_O32(_rex_bootread, (int (*)(void), void *)); +int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), void *, memmap *)); unsigned long *__DEC_PROM_O32(_rex_slot_address, - (unsigned long *(*)(int), int)); -void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void))); -int __DEC_PROM_O32(_rex_getsysid, (int (*)(void))); -void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void))); - -int __DEC_PROM_O32(_prom_getchar, (int (*)(void))); -char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), char *)); -int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), char *, ...)); - - -#define rex_bootinit() _rex_bootinit(__rex_bootinit) -#define rex_bootread() _rex_bootread(__rex_bootread) -#define rex_getbitmap(x) _rex_getbitmap(__rex_getbitmap, x) -#define rex_slot_address(x) _rex_slot_address(__rex_slot_address, x) -#define rex_gettcinfo() _rex_gettcinfo(__rex_gettcinfo) -#define rex_getsysid() _rex_getsysid(__rex_getsysid) -#define rex_clear_cache() _rex_clear_cache(__rex_clear_cache) - -#define prom_getchar() _prom_getchar(__prom_getchar) -#define prom_getenv(x) _prom_getenv(__prom_getenv, x) -#define prom_printf(x...) _prom_printf(__prom_printf, x) + (unsigned long *(*)(int), void *, int)); +void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void), void *)); +int __DEC_PROM_O32(_rex_getsysid, (int (*)(void), void *)); +void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void), void *)); + +int __DEC_PROM_O32(_prom_getchar, (int (*)(void), void *)); +char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), void *, char *)); +int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), void *, char *, ...)); + + +#define rex_bootinit() _rex_bootinit(__rex_bootinit, NULL) +#define rex_bootread() _rex_bootread(__rex_bootread, NULL) +#define rex_getbitmap(x) _rex_getbitmap(__rex_getbitmap, NULL, x) +#define rex_slot_address(x) _rex_slot_address(__rex_slot_address, NULL, x) +#define rex_gettcinfo() _rex_gettcinfo(__rex_gettcinfo, NULL) +#define rex_getsysid() _rex_getsysid(__rex_getsysid, NULL) +#define rex_clear_cache() _rex_clear_cache(__rex_clear_cache, NULL) + +#define prom_getchar() _prom_getchar(__prom_getchar, NULL) +#define prom_getenv(x) _prom_getenv(__prom_getenv, NULL, x) +#define prom_printf(x...) _prom_printf(__prom_printf, NULL, x) #else /* !CONFIG_64BIT */ diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h new file mode 100644 index 00000000000..bc5e85d579e --- /dev/null +++ b/arch/mips/include/asm/dma-coherence.h @@ -0,0 +1,24 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> + * + */ +#ifndef __ASM_DMA_COHERENCE_H +#define __ASM_DMA_COHERENCE_H + +#ifdef CONFIG_DMA_MAYBE_COHERENT +extern int coherentio; +extern int hw_coherentio; +#else +#ifdef CONFIG_DMA_COHERENT +#define coherentio 1 +#else +#define coherentio 0 +#endif +#define hw_coherentio 0 +#endif /* CONFIG_DMA_MAYBE_COHERENT */ + +#endif diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h index 006b43e38a9..06412aa9e3f 100644 --- a/arch/mips/include/asm/dma-mapping.h +++ b/arch/mips/include/asm/dma-mapping.h @@ -2,10 +2,11 @@ #define _ASM_DMA_MAPPING_H #include <asm/scatterlist.h> +#include <asm/dma-coherence.h> #include <asm/cache.h> #include <asm-generic/dma-coherent.h> -#ifndef CONFIG_SGI_IP27 /* Kludge to fix 2.6.39 build for IP27 */ +#ifndef CONFIG_SGI_IP27 /* Kludge to fix 2.6.39 build for IP27 */ #include <dma-coherence.h> #endif @@ -48,9 +49,14 @@ static inline int dma_mapping_error(struct device *dev, u64 mask) static inline int dma_set_mask(struct device *dev, u64 mask) { + struct dma_map_ops *ops = get_dma_ops(dev); + if(!dev->dma_mask || !dma_supported(dev, mask)) return -EIO; + if (ops->set_dma_mask) + return ops->set_dma_mask(dev, mask); + *dev->dma_mask = mask; return 0; diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h index f5097f65a8a..5b9ed1bffdb 100644 --- a/arch/mips/include/asm/dma.h +++ b/arch/mips/include/asm/dma.h @@ -47,21 +47,21 @@ * * Address mapping for channels 0-3: * - * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) - * | ... | | ... | | ... | - * | ... | | ... | | ... | - * | ... | | ... | | ... | - * P7 ... P0 A7 ... A0 A7 ... A0 - * | Page | Addr MSB | Addr LSB | (DMA registers) + * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) + * | ... | | ... | | ... | + * | ... | | ... | | ... | + * | ... | | ... | | ... | + * P7 ... P0 A7 ... A0 A7 ... A0 + * | Page | Addr MSB | Addr LSB | (DMA registers) * * Address mapping for channels 5-7: * - * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) - * | ... | \ \ ... \ \ \ ... \ \ - * | ... | \ \ ... \ \ \ ... \ (not used) - * | ... | \ \ ... \ \ \ ... \ - * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 - * | Page | Addr MSB | Addr LSB | (DMA registers) + * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) + * | ... | \ \ ... \ \ \ ... \ \ + * | ... | \ \ ... \ \ \ ... \ (not used) + * | ... | \ \ ... \ \ \ ... \ + * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 + * | Page | Addr MSB | Addr LSB | (DMA registers) * * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at @@ -102,55 +102,55 @@ /* DMA controller registers */ #define DMA1_CMD_REG 0x08 /* command register (w) */ #define DMA1_STAT_REG 0x08 /* status register (r) */ -#define DMA1_REQ_REG 0x09 /* request register (w) */ +#define DMA1_REQ_REG 0x09 /* request register (w) */ #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ #define DMA1_MODE_REG 0x0B /* mode register (w) */ #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ -#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ +#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ -#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ -#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ +#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ +#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ #define DMA2_CMD_REG 0xD0 /* command register (w) */ #define DMA2_STAT_REG 0xD0 /* status register (r) */ -#define DMA2_REQ_REG 0xD2 /* request register (w) */ +#define DMA2_REQ_REG 0xD2 /* request register (w) */ #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ #define DMA2_MODE_REG 0xD6 /* mode register (w) */ #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ -#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ +#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ #define DMA2_RESET_REG 0xDA /* Master Clear (w) */ -#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ -#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ - -#define DMA_ADDR_0 0x00 /* DMA address registers */ -#define DMA_ADDR_1 0x02 -#define DMA_ADDR_2 0x04 -#define DMA_ADDR_3 0x06 -#define DMA_ADDR_4 0xC0 -#define DMA_ADDR_5 0xC4 -#define DMA_ADDR_6 0xC8 -#define DMA_ADDR_7 0xCC - -#define DMA_CNT_0 0x01 /* DMA count registers */ -#define DMA_CNT_1 0x03 -#define DMA_CNT_2 0x05 -#define DMA_CNT_3 0x07 -#define DMA_CNT_4 0xC2 -#define DMA_CNT_5 0xC6 -#define DMA_CNT_6 0xCA -#define DMA_CNT_7 0xCE - -#define DMA_PAGE_0 0x87 /* DMA page registers */ -#define DMA_PAGE_1 0x83 -#define DMA_PAGE_2 0x81 -#define DMA_PAGE_3 0x82 -#define DMA_PAGE_5 0x8B -#define DMA_PAGE_6 0x89 -#define DMA_PAGE_7 0x8A +#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ +#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ + +#define DMA_ADDR_0 0x00 /* DMA address registers */ +#define DMA_ADDR_1 0x02 +#define DMA_ADDR_2 0x04 +#define DMA_ADDR_3 0x06 +#define DMA_ADDR_4 0xC0 +#define DMA_ADDR_5 0xC4 +#define DMA_ADDR_6 0xC8 +#define DMA_ADDR_7 0xCC + +#define DMA_CNT_0 0x01 /* DMA count registers */ +#define DMA_CNT_1 0x03 +#define DMA_CNT_2 0x05 +#define DMA_CNT_3 0x07 +#define DMA_CNT_4 0xC2 +#define DMA_CNT_5 0xC6 +#define DMA_CNT_6 0xCA +#define DMA_CNT_7 0xCE + +#define DMA_PAGE_0 0x87 /* DMA page registers */ +#define DMA_PAGE_1 0x83 +#define DMA_PAGE_2 0x81 +#define DMA_PAGE_3 0x82 +#define DMA_PAGE_5 0x8B +#define DMA_PAGE_6 0x89 +#define DMA_PAGE_7 0x8A #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ -#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ +#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ #define DMA_AUTOINIT 0x10 @@ -172,7 +172,7 @@ static __inline__ void release_dma_lock(unsigned long flags) static __inline__ void enable_dma(unsigned int dmanr) { if (dmanr<=3) - dma_outb(dmanr, DMA1_MASK_REG); + dma_outb(dmanr, DMA1_MASK_REG); else dma_outb(dmanr & 3, DMA2_MASK_REG); } @@ -204,7 +204,7 @@ static __inline__ void clear_dma_ff(unsigned int dmanr) static __inline__ void set_dma_mode(unsigned int dmanr, char mode) { if (dmanr<=3) - dma_outb(mode | dmanr, DMA1_MODE_REG); + dma_outb(mode | dmanr, DMA1_MODE_REG); else dma_outb(mode | (dmanr&3), DMA2_MODE_REG); } @@ -248,10 +248,10 @@ static __inline__ void set_dma_page(unsigned int dmanr, char pagenr) static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) { set_dma_page(dmanr, a>>16); - if (dmanr <= 3) { + if (dmanr <= 3) { dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); - dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); - } else { + dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); + } else { dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); } @@ -268,14 +268,14 @@ static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) */ static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) { - count--; - if (dmanr <= 3) { + count--; + if (dmanr <= 3) { dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); - } else { + } else { dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); - } + } } diff --git a/arch/mips/include/asm/dsp.h b/arch/mips/include/asm/dsp.h index e9bfc0813c7..7bfad0520e2 100644 --- a/arch/mips/include/asm/dsp.h +++ b/arch/mips/include/asm/dsp.h @@ -16,7 +16,7 @@ #include <asm/mipsregs.h> #define DSP_DEFAULT 0x00000000 -#define DSP_MASK 0x3ff +#define DSP_MASK 0x3f #define __enable_dsp_hazard() \ do { \ diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h index 455c0ac7d4e..d4144056e92 100644 --- a/arch/mips/include/asm/elf.h +++ b/arch/mips/include/asm/elf.h @@ -11,13 +11,13 @@ /* ELF header e_flags defines. */ /* MIPS architecture level. */ -#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ -#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ -#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ -#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ -#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -#define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */ -#define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */ +#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ +#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ +#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ +#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ +#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ +#define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */ +#define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */ #define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32 R2 code. */ #define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64 R2 code. */ @@ -36,6 +36,7 @@ #define EF_MIPS_ABI2 0x00000020 #define EF_MIPS_OPTIONS_FIRST 0x00000080 #define EF_MIPS_32BITMODE 0x00000100 +#define EF_MIPS_FP64 0x00000200 #define EF_MIPS_ABI 0x0000f000 #define EF_MIPS_ARCH 0xf0000000 @@ -74,7 +75,7 @@ #define R_MIPS_CALL16 11 #define R_MIPS_GPREL32 12 /* The remaining relocs are defined on Irix, although they are not - in the MIPS ELF ABI. */ + in the MIPS ELF ABI. */ #define R_MIPS_UNUSED1 13 #define R_MIPS_UNUSED2 14 #define R_MIPS_UNUSED3 15 @@ -176,6 +177,18 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; #ifdef CONFIG_32BIT /* + * In order to be sure that we don't attempt to execute an O32 binary which + * requires 64 bit FP (FR=1) on a system which does not support it we refuse + * to execute any binary which has bits specified by the following macro set + * in its ELF header flags. + */ +#ifdef CONFIG_MIPS_O32_FP64_SUPPORT +# define __MIPS_O32_FP64_MUST_BE_ZERO 0 +#else +# define __MIPS_O32_FP64_MUST_BE_ZERO EF_MIPS_FP64 +#endif + +/* * This is used to ensure we don't load something for the wrong architecture. */ #define elf_check_arch(hdr) \ @@ -192,6 +205,8 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ __res = 0; \ + if (__h->e_flags & __MIPS_O32_FP64_MUST_BE_ZERO) \ + __res = 0; \ \ __res; \ }) @@ -214,7 +229,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; \ if (__h->e_machine != EM_MIPS) \ __res = 0; \ - if (__h->e_ident[EI_CLASS] != ELFCLASS64) \ + if (__h->e_ident[EI_CLASS] != ELFCLASS64) \ __res = 0; \ \ __res; \ @@ -249,6 +264,11 @@ extern struct mips_abi mips_abi_n32; #define SET_PERSONALITY(ex) \ do { \ + if ((ex).e_flags & EF_MIPS_FP64) \ + clear_thread_flag(TIF_32BIT_FPREGS); \ + else \ + set_thread_flag(TIF_32BIT_FPREGS); \ + \ if (personality(current->personality) != PER_LINUX) \ set_personality(PER_LINUX); \ \ @@ -271,14 +291,18 @@ do { \ #endif #ifdef CONFIG_MIPS32_O32 -#define __SET_PERSONALITY32_O32() \ +#define __SET_PERSONALITY32_O32(ex) \ do { \ set_thread_flag(TIF_32BIT_REGS); \ set_thread_flag(TIF_32BIT_ADDR); \ + \ + if (!((ex).e_flags & EF_MIPS_FP64)) \ + set_thread_flag(TIF_32BIT_FPREGS); \ + \ current->thread.abi = &mips_abi_32; \ } while (0) #else -#define __SET_PERSONALITY32_O32() \ +#define __SET_PERSONALITY32_O32(ex) \ do { } while (0) #endif @@ -289,10 +313,10 @@ do { \ ((ex).e_flags & EF_MIPS_ABI) == 0) \ __SET_PERSONALITY32_N32(); \ else \ - __SET_PERSONALITY32_O32(); \ + __SET_PERSONALITY32_O32(ex); \ } while (0) #else -#define __SET_PERSONALITY32(ex) do { } while (0) +#define __SET_PERSONALITY32(ex) do { } while (0) #endif #define SET_PERSONALITY(ex) \ @@ -300,6 +324,7 @@ do { \ unsigned int p; \ \ clear_thread_flag(TIF_32BIT_REGS); \ + clear_thread_flag(TIF_32BIT_FPREGS); \ clear_thread_flag(TIF_32BIT_ADDR); \ \ if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ @@ -331,17 +356,18 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \ dump_task_fpu(tsk, elf_fpregs) +#define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE PAGE_SIZE /* This yields a mask that user programs can use to figure out what instruction set this cpu supports. This could be done in userspace, but it's not easy, and we've already done it here. */ -#define ELF_HWCAP (0) +#define ELF_HWCAP (0) /* * This yields a string that ld.so will use to load implementation - * specific libraries for optimization. This is more specific in + * specific libraries for optimization. This is more specific in * intent than poking at uname or /proc/cpuinfo. */ @@ -365,11 +391,11 @@ extern const char *__elf_platform; /* This is the location that an ET_DYN program is loaded if exec'ed. Typical use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ #ifndef ELF_ET_DYN_BASE -#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) +#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) #endif #define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1 diff --git a/arch/mips/include/asm/emergency-restart.h b/arch/mips/include/asm/emergency-restart.h deleted file mode 100644 index 108d8c48e42..00000000000 --- a/arch/mips/include/asm/emergency-restart.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_EMERGENCY_RESTART_H -#define _ASM_EMERGENCY_RESTART_H - -#include <asm-generic/emergency-restart.h> - -#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/arch/mips/include/asm/emma/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h index c1449d20ef0..ecf059608bd 100644 --- a/arch/mips/include/asm/emma/emma2rh.h +++ b/arch/mips/include/asm/emma/emma2rh.h @@ -2,7 +2,7 @@ * Copyright (C) NEC Electronics Corporation 2005-2006 * * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h - * Copyright 2001 MontaVista Software Inc. + * Copyright 2001 MontaVista Software Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -40,7 +40,7 @@ #define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE) #define EMMA2RH_BHIF_SW_INT (0x000070+REGBASE) #define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE) -#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE) +#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE) #define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE) #define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS (0x0000c0+REGBASE) #define EMMA2RH_GPIO_DIR (0x110d20+REGBASE) @@ -73,7 +73,7 @@ * Memory map (physical address) * * Note most of the following address must be properly aligned by the - * corresponding size. For example, if PCI_IO_SIZE is 16MB, then + * corresponding size. For example, if PCI_IO_SIZE is 16MB, then * PCI_IO_BASE must be aligned along 16MB boundary. */ @@ -96,8 +96,8 @@ #define EMMA2RH_ROM_BASE 0x1c000000 #define EMMA2RH_ROM_SIZE 0x04000000 /* 64 MB */ -#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE -#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE +#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE +#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE #define NUM_EMMA2RH_IRQ 96 @@ -169,51 +169,51 @@ static inline u8 emma2rh_in8(u32 offset) **/ /*---------------------------------------------------------------------------*/ -/* CNT - Control register (00H R/W) */ +/* CNT - Control register (00H R/W) */ /*---------------------------------------------------------------------------*/ -#define SPT 0x00000001 -#define STT 0x00000002 -#define ACKE 0x00000004 -#define WTIM 0x00000008 -#define SPIE 0x00000010 -#define WREL 0x00000020 -#define LREL 0x00000040 -#define IICE 0x00000080 -#define CNT_RESERVED 0x000000ff /* reserved bit 0 */ - -#define I2C_EMMA_START (IICE | STT) -#define I2C_EMMA_STOP (IICE | SPT) +#define SPT 0x00000001 +#define STT 0x00000002 +#define ACKE 0x00000004 +#define WTIM 0x00000008 +#define SPIE 0x00000010 +#define WREL 0x00000020 +#define LREL 0x00000040 +#define IICE 0x00000080 +#define CNT_RESERVED 0x000000ff /* reserved bit 0 */ + +#define I2C_EMMA_START (IICE | STT) +#define I2C_EMMA_STOP (IICE | SPT) #define I2C_EMMA_REPSTART I2C_EMMA_START /*---------------------------------------------------------------------------*/ -/* STA - Status register (10H Read) */ +/* STA - Status register (10H Read) */ /*---------------------------------------------------------------------------*/ -#define MSTS 0x00000080 -#define ALD 0x00000040 -#define EXC 0x00000020 -#define COI 0x00000010 -#define TRC 0x00000008 -#define ACKD 0x00000004 -#define STD 0x00000002 -#define SPD 0x00000001 +#define MSTS 0x00000080 +#define ALD 0x00000040 +#define EXC 0x00000020 +#define COI 0x00000010 +#define TRC 0x00000008 +#define ACKD 0x00000004 +#define STD 0x00000002 +#define SPD 0x00000001 /*---------------------------------------------------------------------------*/ -/* CSEL - Clock select register (20H R/W) */ +/* CSEL - Clock select register (20H R/W) */ /*---------------------------------------------------------------------------*/ -#define FCL 0x00000080 -#define ND50 0x00000040 -#define CLD 0x00000020 -#define DAD 0x00000010 -#define SMC 0x00000008 -#define DFC 0x00000004 -#define CL 0x00000003 -#define CSEL_RESERVED 0x000000ff /* reserved bit 0 */ - -#define FAST397 0x0000008b -#define FAST297 0x0000008a -#define FAST347 0x0000000b -#define FAST260 0x0000000a -#define FAST130 0x00000008 +#define FCL 0x00000080 +#define ND50 0x00000040 +#define CLD 0x00000020 +#define DAD 0x00000010 +#define SMC 0x00000008 +#define DFC 0x00000004 +#define CL 0x00000003 +#define CSEL_RESERVED 0x000000ff /* reserved bit 0 */ + +#define FAST397 0x0000008b +#define FAST297 0x0000008a +#define FAST347 0x0000000b +#define FAST260 0x0000000a +#define FAST130 0x00000008 #define STANDARD108 0x00000083 #define STANDARD83 0x00000082 #define STANDARD95 0x00000003 @@ -222,32 +222,32 @@ static inline u8 emma2rh_in8(u32 offset) #define STANDARD71 0x00000000 /*---------------------------------------------------------------------------*/ -/* SVA - Slave address register (30H R/W) */ +/* SVA - Slave address register (30H R/W) */ /*---------------------------------------------------------------------------*/ -#define SVA 0x000000fe +#define SVA 0x000000fe /*---------------------------------------------------------------------------*/ -/* SHR - Shift register (40H R/W) */ +/* SHR - Shift register (40H R/W) */ /*---------------------------------------------------------------------------*/ -#define SR 0x000000ff +#define SR 0x000000ff /*---------------------------------------------------------------------------*/ -/* INT - Interrupt register (50H R/W) */ -/* INTM - Interrupt mask register (60H R/W) */ +/* INT - Interrupt register (50H R/W) */ +/* INTM - Interrupt mask register (60H R/W) */ /*---------------------------------------------------------------------------*/ -#define INTE0 0x00000001 +#define INTE0 0x00000001 /*********************************************************************** * I2C registers *********************************************************************** */ -#define I2C_EMMA_CNT 0x00 -#define I2C_EMMA_STA 0x10 -#define I2C_EMMA_CSEL 0x20 -#define I2C_EMMA_SVA 0x30 -#define I2C_EMMA_SHR 0x40 -#define I2C_EMMA_INT 0x50 -#define I2C_EMMA_INTM 0x60 +#define I2C_EMMA_CNT 0x00 +#define I2C_EMMA_STA 0x10 +#define I2C_EMMA_CSEL 0x20 +#define I2C_EMMA_SVA 0x30 +#define I2C_EMMA_SHR 0x40 +#define I2C_EMMA_INT 0x50 +#define I2C_EMMA_INTM 0x60 /* * include the board dependent part diff --git a/arch/mips/include/asm/emma/markeins.h b/arch/mips/include/asm/emma/markeins.h index bf2d229c2da..e55a6747782 100644 --- a/arch/mips/include/asm/emma/markeins.h +++ b/arch/mips/include/asm/emma/markeins.h @@ -2,7 +2,7 @@ * Copyright (C) NEC Electronics Corporation 2005-2006 * * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h - * Copyright 2001 MontaVista Software Inc. + * Copyright 2001 MontaVista Software Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h index 98bcc98cf29..6842ffafd1e 100644 --- a/arch/mips/include/asm/fixmap.h +++ b/arch/mips/include/asm/fixmap.h @@ -48,11 +48,7 @@ enum fixed_addresses { #define FIX_N_COLOURS 8 FIX_CMAP_BEGIN, -#ifdef CONFIG_MIPS_MT_SMTC - FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS * 2), -#else FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * 2), -#endif #ifdef CONFIG_HIGHMEM /* reserved pte's for temporary kernel mappings */ FIX_KMAP_BEGIN = FIX_CMAP_END + 1, @@ -71,38 +67,7 @@ enum fixed_addresses { #define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) -#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT)) -#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT) - -extern void __this_fixmap_does_not_exist(void); - -/* - * 'index to address' translation. If anyone tries to use the idx - * directly without tranlation, we catch the bug with a NULL-deference - * kernel oops. Illegal ranges of incoming indices are caught too. - */ -static inline unsigned long fix_to_virt(const unsigned int idx) -{ - /* - * this branch gets completely eliminated after inlining, - * except when someone tries to use fixaddr indices in an - * illegal way. (such as mixing up address types or using - * out-of-range indices). - * - * If it doesn't get removed, the linker will complain - * loudly with a reasonably clear error message.. - */ - if (idx >= __end_of_fixed_addresses) - __this_fixmap_does_not_exist(); - - return __fix_to_virt(idx); -} - -static inline unsigned long virt_to_fix(const unsigned long vaddr) -{ - BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START); - return __virt_to_fix(vaddr); -} +#include <asm-generic/fixmap.h> #define kmap_get_fixmap_pte(vaddr) \ pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) @@ -111,7 +76,7 @@ static inline unsigned long virt_to_fix(const unsigned long vaddr) * Called from pgtable_init() */ extern void fixrange_init(unsigned long start, unsigned long end, - pgd_t *pgd_base); + pgd_t *pgd_base); #endif diff --git a/arch/mips/include/asm/floppy.h b/arch/mips/include/asm/floppy.h index 4456c9c47e2..d75aed36480 100644 --- a/arch/mips/include/asm/floppy.h +++ b/arch/mips/include/asm/floppy.h @@ -24,9 +24,9 @@ static inline void fd_cacheflush(char * addr, long size) * And on Mips's the CMOS info fails also ... * * FIXME: This information should come from the ARC configuration tree - * or wherever a particular machine has stored this ... + * or wherever a particular machine has stored this ... */ -#define FLOPPY0_TYPE fd_drive_type(0) +#define FLOPPY0_TYPE fd_drive_type(0) #define FLOPPY1_TYPE fd_drive_type(1) #define FDC1 fd_getfdaddr1() diff --git a/arch/mips/include/asm/fpregdef.h b/arch/mips/include/asm/fpregdef.h index 2b5fddc8f48..429481f9028 100644 --- a/arch/mips/include/asm/fpregdef.h +++ b/arch/mips/include/asm/fpregdef.h @@ -20,15 +20,15 @@ * These definitions only cover the R3000-ish 16/32 register model. * But we're trying to be R3000 friendly anyway ... */ -#define fv0 $f0 /* return value */ +#define fv0 $f0 /* return value */ #define fv0f $f1 #define fv1 $f2 #define fv1f $f3 -#define fa0 $f12 /* argument registers */ +#define fa0 $f12 /* argument registers */ #define fa0f $f13 #define fa1 $f14 #define fa1f $f15 -#define ft0 $f4 /* caller saved */ +#define ft0 $f4 /* caller saved */ #define ft0f $f5 #define ft1 $f6 #define ft1f $f7 @@ -40,7 +40,7 @@ #define ft4f $f17 #define ft5 $f18 #define ft5f $f19 -#define fs0 $f20 /* callee saved */ +#define fs0 $f20 /* callee saved */ #define fs0f $f21 #define fs1 $f22 #define fs1f $f23 @@ -53,7 +53,7 @@ #define fs5 $f30 #define fs5f $f31 -#define fcr31 $31 /* FPU status register */ +#define fcr31 $31 /* FPU status register */ #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h index 7fcef8ef3fa..a939574f829 100644 --- a/arch/mips/include/asm/fpu.h +++ b/arch/mips/include/asm/fpu.h @@ -17,6 +17,7 @@ #include <asm/mipsregs.h> #include <asm/cpu.h> #include <asm/cpu-features.h> +#include <asm/fpu_emulator.h> #include <asm/hazards.h> #include <asm/processor.h> #include <asm/current.h> @@ -28,36 +29,61 @@ struct sigcontext; struct sigcontext32; -extern void fpu_emulator_init_fpu(void); extern void _init_fpu(void); extern void _save_fp(struct task_struct *); extern void _restore_fp(struct task_struct *); -#define __enable_fpu() \ -do { \ - set_c0_status(ST0_CU1); \ - enable_fpu_hazard(); \ -} while (0) +/* + * This enum specifies a mode in which we want the FPU to operate, for cores + * which implement the Status.FR bit. Note that FPU_32BIT & FPU_64BIT + * purposefully have the values 0 & 1 respectively, so that an integer value + * of Status.FR can be trivially casted to the corresponding enum fpu_mode. + */ +enum fpu_mode { + FPU_32BIT = 0, /* FR = 0 */ + FPU_64BIT, /* FR = 1 */ + FPU_AS_IS, +}; -#define __disable_fpu() \ -do { \ - clear_c0_status(ST0_CU1); \ - disable_fpu_hazard(); \ -} while (0) +static inline int __enable_fpu(enum fpu_mode mode) +{ + int fr; + + switch (mode) { + case FPU_AS_IS: + /* just enable the FPU in its current mode */ + set_c0_status(ST0_CU1); + enable_fpu_hazard(); + return 0; + + case FPU_64BIT: +#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_64BIT)) + /* we only have a 32-bit FPU */ + return SIGFPE; +#endif + /* fall through */ + case FPU_32BIT: + /* set CU1 & change FR appropriately */ + fr = (int)mode; + change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0)); + enable_fpu_hazard(); + + /* check FR has the desired value */ + return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE; + + default: + BUG(); + } -#define enable_fpu() \ -do { \ - if (cpu_has_fpu) \ - __enable_fpu(); \ -} while (0) + return SIGFPE; +} -#define disable_fpu() \ +#define __disable_fpu() \ do { \ - if (cpu_has_fpu) \ - __disable_fpu(); \ + clear_c0_status(ST0_CU1); \ + disable_fpu_hazard(); \ } while (0) - #define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU) static inline int __is_fpu_owner(void) @@ -70,27 +96,46 @@ static inline int is_fpu_owner(void) return cpu_has_fpu && __is_fpu_owner(); } -static inline void __own_fpu(void) +static inline int __own_fpu(void) { - __enable_fpu(); + enum fpu_mode mode; + int ret; + + mode = !test_thread_flag(TIF_32BIT_FPREGS); + ret = __enable_fpu(mode); + if (ret) + return ret; + KSTK_STATUS(current) |= ST0_CU1; + if (mode == FPU_64BIT) + KSTK_STATUS(current) |= ST0_FR; + else /* mode == FPU_32BIT */ + KSTK_STATUS(current) &= ~ST0_FR; + set_thread_flag(TIF_USEDFPU); + return 0; } -static inline void own_fpu_inatomic(int restore) +static inline int own_fpu_inatomic(int restore) { + int ret = 0; + if (cpu_has_fpu && !__is_fpu_owner()) { - __own_fpu(); - if (restore) + ret = __own_fpu(); + if (restore && !ret) _restore_fp(current); } + return ret; } -static inline void own_fpu(int restore) +static inline int own_fpu(int restore) { + int ret; + preempt_disable(); - own_fpu_inatomic(restore); + ret = own_fpu_inatomic(restore); preempt_enable(); + return ret; } static inline void lose_fpu(int save) @@ -106,16 +151,22 @@ static inline void lose_fpu(int save) preempt_enable(); } -static inline void init_fpu(void) +static inline int init_fpu(void) { + int ret = 0; + preempt_disable(); + if (cpu_has_fpu) { - __own_fpu(); - _init_fpu(); - } else { + ret = __own_fpu(); + if (!ret) + _init_fpu(); + } else fpu_emulator_init_fpu(); - } + preempt_enable(); + + return ret; } static inline void save_fp(struct task_struct *tsk) @@ -130,7 +181,7 @@ static inline void restore_fp(struct task_struct *tsk) _restore_fp(tsk); } -static inline fpureg_t *get_fpu_regs(struct task_struct *tsk) +static inline union fpureg *get_fpu_regs(struct task_struct *tsk) { if (tsk == current) { preempt_disable(); diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h index 3b409270556..0195745b4b1 100644 --- a/arch/mips/include/asm/fpu_emulator.h +++ b/arch/mips/include/asm/fpu_emulator.h @@ -23,9 +23,12 @@ #ifndef _ASM_FPU_EMULATOR_H #define _ASM_FPU_EMULATOR_H +#include <linux/sched.h> #include <asm/break.h> +#include <asm/thread_info.h> #include <asm/inst.h> #include <asm/local.h> +#include <asm/processor.h> #ifdef CONFIG_DEBUG_FS @@ -36,6 +39,11 @@ struct mips_fpu_emulator_stats { local_t cp1ops; local_t cp1xops; local_t errors; + local_t ieee754_inexact; + local_t ieee754_underflow; + local_t ieee754_overflow; + local_t ieee754_zerodiv; + local_t ieee754_invalidop; }; DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats); @@ -54,6 +62,12 @@ do { \ extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc); extern int do_dsemulret(struct pt_regs *xcp); +extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, + struct mips_fpu_struct *ctx, int has_fpu, + void *__user *fault_addr); +int process_fpemu_return(int sig, void __user *fault_addr); +int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, + unsigned long *contpc); /* * Instruction inserted following the badinst to further tag the sequence @@ -65,4 +79,17 @@ extern int do_dsemulret(struct pt_regs *xcp); */ #define BREAK_MATH (0x0000000d | (BRK_MEMU << 16)) +#define SIGNALLING_NAN 0x7ff800007ff80000LL + +static inline void fpu_emulator_init_fpu(void) +{ + struct task_struct *t = current; + int i; + + t->thread.fpu.fcr31 = 0; + + for (i = 0; i < 32; i++) + set_fpr64(&t->thread.fpu.fpr[i], 0, SIGNALLING_NAN); +} + #endif /* _ASM_FPU_EMULATOR_H */ diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h index ce35c9af0c2..992aaba603b 100644 --- a/arch/mips/include/asm/ftrace.h +++ b/arch/mips/include/asm/ftrace.h @@ -22,12 +22,12 @@ extern void _mcount(void); #define safe_load(load, src, dst, error) \ do { \ asm volatile ( \ - "1: " load " %[" STR(dst) "], 0(%[" STR(src) "])\n"\ - " li %[" STR(error) "], 0\n" \ + "1: " load " %[tmp_dst], 0(%[tmp_src])\n" \ + " li %[tmp_err], 0\n" \ "2:\n" \ \ ".section .fixup, \"ax\"\n" \ - "3: li %[" STR(error) "], 1\n" \ + "3: li %[tmp_err], 1\n" \ " j 2b\n" \ ".previous\n" \ \ @@ -35,8 +35,8 @@ do { \ STR(PTR) "\t1b, 3b\n\t" \ ".previous\n" \ \ - : [dst] "=&r" (dst), [error] "=r" (error)\ - : [src] "r" (src) \ + : [tmp_dst] "=&r" (dst), [tmp_err] "=r" (error)\ + : [tmp_src] "r" (src) \ : "memory" \ ); \ } while (0) @@ -44,12 +44,12 @@ do { \ #define safe_store(store, src, dst, error) \ do { \ asm volatile ( \ - "1: " store " %[" STR(src) "], 0(%[" STR(dst) "])\n"\ - " li %[" STR(error) "], 0\n" \ + "1: " store " %[tmp_src], 0(%[tmp_dst])\n"\ + " li %[tmp_err], 0\n" \ "2:\n" \ \ ".section .fixup, \"ax\"\n" \ - "3: li %[" STR(error) "], 1\n" \ + "3: li %[tmp_err], 1\n" \ " j 2b\n" \ ".previous\n" \ \ @@ -57,8 +57,8 @@ do { \ STR(PTR) "\t1b, 3b\n\t" \ ".previous\n" \ \ - : [error] "=r" (error) \ - : [dst] "r" (dst), [src] "r" (src)\ + : [tmp_err] "=r" (error) \ + : [tmp_dst] "r" (dst), [tmp_src] "r" (src)\ : "memory" \ ); \ } while (0) diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h index 6ebf1734b41..194cda0396a 100644 --- a/arch/mips/include/asm/futex.h +++ b/arch/mips/include/asm/futex.h @@ -12,6 +12,7 @@ #include <linux/futex.h> #include <linux/uaccess.h> +#include <asm/asm-eva.h> #include <asm/barrier.h> #include <asm/errno.h> #include <asm/war.h> @@ -22,11 +23,11 @@ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " .set mips3 \n" \ + " .set arch=r4000 \n" \ "1: ll %1, %4 # __futex_atomic_op \n" \ " .set mips0 \n" \ " " insn " \n" \ - " .set mips3 \n" \ + " .set arch=r4000 \n" \ "2: sc $1, %2 \n" \ " beqzl $1, 1b \n" \ __WEAK_LLSC_MB \ @@ -48,12 +49,12 @@ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " .set mips3 \n" \ - "1: ll %1, %4 # __futex_atomic_op \n" \ + " .set arch=r4000 \n" \ + "1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \ " .set mips0 \n" \ " " insn " \n" \ - " .set mips3 \n" \ - "2: sc $1, %2 \n" \ + " .set arch=r4000 \n" \ + "2: "user_sc("$1", "%2")" \n" \ " beqz $1, 1b \n" \ __WEAK_LLSC_MB \ "3: \n" \ @@ -92,24 +93,24 @@ futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr) switch (op) { case FUTEX_OP_SET: - __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg); + __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg); break; case FUTEX_OP_ADD: - __futex_atomic_op("addu $1, %1, %z5", - ret, oldval, uaddr, oparg); + __futex_atomic_op("addu $1, %1, %z5", + ret, oldval, uaddr, oparg); break; case FUTEX_OP_OR: __futex_atomic_op("or $1, %1, %z5", - ret, oldval, uaddr, oparg); + ret, oldval, uaddr, oparg); break; case FUTEX_OP_ANDN: __futex_atomic_op("and $1, %1, %z5", - ret, oldval, uaddr, ~oparg); + ret, oldval, uaddr, ~oparg); break; case FUTEX_OP_XOR: __futex_atomic_op("xor $1, %1, %z5", - ret, oldval, uaddr, oparg); + ret, oldval, uaddr, oparg); break; default: ret = -ENOSYS; @@ -146,12 +147,12 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, "# futex_atomic_cmpxchg_inatomic \n" " .set push \n" " .set noat \n" - " .set mips3 \n" + " .set arch=r4000 \n" "1: ll %1, %3 \n" " bne %1, %z4, 3f \n" " .set mips0 \n" " move $1, %z5 \n" - " .set mips3 \n" + " .set arch=r4000 \n" "2: sc $1, %2 \n" " beqzl $1, 1b \n" __WEAK_LLSC_MB @@ -173,13 +174,13 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, "# futex_atomic_cmpxchg_inatomic \n" " .set push \n" " .set noat \n" - " .set mips3 \n" - "1: ll %1, %3 \n" + " .set arch=r4000 \n" + "1: "user_ll("%1", "%3")" \n" " bne %1, %z4, 3f \n" " .set mips0 \n" " move $1, %z5 \n" - " .set mips3 \n" - "2: sc $1, %2 \n" + " .set arch=r4000 \n" + "2: "user_sc("$1", "%2")" \n" " beqz $1, 1b \n" __WEAK_LLSC_MB "3: \n" diff --git a/arch/mips/include/asm/fw/arc/hinv.h b/arch/mips/include/asm/fw/arc/hinv.h index e6ff4add04e..f8d37d1df5d 100644 --- a/arch/mips/include/asm/fw/arc/hinv.h +++ b/arch/mips/include/asm/fw/arc/hinv.h @@ -12,7 +12,7 @@ typedef enum configclass { SystemClass, ProcessorClass, CacheClass, -#ifndef _NT_PROM +#ifndef _NT_PROM MemoryClass, AdapterClass, ControllerClass, @@ -34,7 +34,7 @@ typedef enum configtype { SecondaryICache, SecondaryDCache, SecondaryCache, -#ifndef _NT_PROM +#ifndef _NT_PROM Memory, #endif EISAAdapter, @@ -93,7 +93,7 @@ typedef enum { } IDENTIFIERFLAG; #ifndef NULL /* for GetChild(NULL); */ -#define NULL 0 +#define NULL 0 #endif union key_u { @@ -125,7 +125,7 @@ typedef struct component { IDENTIFIERFLAG Flags; USHORT Version; USHORT Revision; - ULONG Key; + ULONG Key; ULONG AffinityMask; ULONG ConfigurationDataSize; ULONG IdentifierLength; @@ -149,7 +149,7 @@ typedef struct systemid { typedef enum memorytype { ExceptionBlock, SPBPage, /* ARCS == SystemParameterBlock */ -#ifndef _NT_PROM +#ifndef _NT_PROM FreeContiguous, FreeMemory, BadMemory, diff --git a/arch/mips/include/asm/fw/arc/types.h b/arch/mips/include/asm/fw/arc/types.h index 2b11f87d6fb..ad163806148 100644 --- a/arch/mips/include/asm/fw/arc/types.h +++ b/arch/mips/include/asm/fw/arc/types.h @@ -15,7 +15,7 @@ typedef char CHAR; typedef short SHORT; typedef long LARGE_INTEGER __attribute__ ((__mode__ (__DI__))); -typedef long LONG __attribute__ ((__mode__ (__SI__))); +typedef long LONG __attribute__ ((__mode__ (__SI__))); typedef unsigned char UCHAR; typedef unsigned short USHORT; typedef unsigned long ULONG __attribute__ ((__mode__ (__SI__))); @@ -23,11 +23,11 @@ typedef void VOID; /* The pointer types. Note that we're using a 64-bit compiler but all pointer in the ARC structures are only 32-bit, so we need some disgusting - workarounds. Keep your vomit bag handy. */ + workarounds. Keep your vomit bag handy. */ typedef LONG _PCHAR; typedef LONG _PSHORT; typedef LONG _PLARGE_INTEGER; -typedef LONG _PLONG; +typedef LONG _PLONG; typedef LONG _PUCHAR; typedef LONG _PUSHORT; typedef LONG _PULONG; @@ -40,7 +40,7 @@ typedef LONG _PVOID; typedef char CHAR; typedef short SHORT; typedef long LARGE_INTEGER __attribute__ ((__mode__ (__DI__))); -typedef long LONG __attribute__ ((__mode__ (__DI__))); +typedef long LONG __attribute__ ((__mode__ (__DI__))); typedef unsigned char UCHAR; typedef unsigned short USHORT; typedef unsigned long ULONG __attribute__ ((__mode__ (__DI__))); @@ -51,7 +51,7 @@ typedef void VOID; typedef CHAR *_PCHAR; typedef SHORT *_PSHORT; typedef LARGE_INTEGER *_PLARGE_INTEGER; -typedef LONG *_PLONG; +typedef LONG *_PLONG; typedef UCHAR *_PUCHAR; typedef USHORT *_PUSHORT; typedef ULONG *_PULONG; @@ -62,7 +62,7 @@ typedef VOID *_PVOID; typedef CHAR *PCHAR; typedef SHORT *PSHORT; typedef LARGE_INTEGER *PLARGE_INTEGER; -typedef LONG *PLONG; +typedef LONG *PLONG; typedef UCHAR *PUCHAR; typedef USHORT *PUSHORT; typedef ULONG *PULONG; diff --git a/arch/mips/include/asm/fw/cfe/cfe_api.h b/arch/mips/include/asm/fw/cfe/cfe_api.h index 0995575db32..a0ea69e91e2 100644 --- a/arch/mips/include/asm/fw/cfe/cfe_api.h +++ b/arch/mips/include/asm/fw/cfe/cfe_api.h @@ -40,7 +40,7 @@ typedef long intptr_t; /* Seal indicating CFE's presence, passed to user program. */ #define CFE_EPTSEAL 0x43464531 -#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */ +#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */ #define CFE_MI_AVAILABLE 1 /* memory is available */ #define CFE_FLG_WARMSTART 0x00000001 @@ -52,13 +52,13 @@ typedef long intptr_t; #define CFE_STDHANDLE_CONSOLE 0 -#define CFE_DEV_NETWORK 1 +#define CFE_DEV_NETWORK 1 #define CFE_DEV_DISK 2 #define CFE_DEV_FLASH 3 #define CFE_DEV_SERIAL 4 #define CFE_DEV_CPU 5 #define CFE_DEV_NVRAM 6 -#define CFE_DEV_CLOCK 7 +#define CFE_DEV_CLOCK 7 #define CFE_DEV_OTHER 8 #define CFE_DEV_MASK 0x0F @@ -115,8 +115,8 @@ int cfe_read(int handle, unsigned char *buffer, int length); int cfe_readblk(int handle, int64_t offset, unsigned char *buffer, int length); int cfe_setenv(char *name, char *val); -int cfe_write(int handle, unsigned char *buffer, int length); -int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer, +int cfe_write(int handle, const char *buffer, int length); +int cfe_writeblk(int handle, int64_t offset, const char *buffer, int length); #endif /* CFE_API_H */ diff --git a/arch/mips/include/asm/fw/cfe/cfe_error.h b/arch/mips/include/asm/fw/cfe/cfe_error.h index b8037463627..fc0e91f07e2 100644 --- a/arch/mips/include/asm/fw/cfe/cfe_error.h +++ b/arch/mips/include/asm/fw/cfe/cfe_error.h @@ -25,7 +25,7 @@ */ #define CFE_OK 0 -#define CFE_ERR -1 /* generic error */ +#define CFE_ERR -1 /* generic error */ #define CFE_ERR_INV_COMMAND -2 #define CFE_ERR_EOF -3 #define CFE_ERR_IOERR -4 @@ -37,12 +37,12 @@ #define CFE_ERR_ENVREADONLY -10 #define CFE_ERR_NOTELF -11 -#define CFE_ERR_NOT32BIT -12 -#define CFE_ERR_WRONGENDIAN -13 -#define CFE_ERR_BADELFVERS -14 -#define CFE_ERR_NOTMIPS -15 -#define CFE_ERR_BADELFFMT -16 -#define CFE_ERR_BADADDR -17 +#define CFE_ERR_NOT32BIT -12 +#define CFE_ERR_WRONGENDIAN -13 +#define CFE_ERR_BADELFVERS -14 +#define CFE_ERR_NOTMIPS -15 +#define CFE_ERR_BADELFFMT -16 +#define CFE_ERR_BADADDR -17 #define CFE_ERR_FILENOTFOUND -18 #define CFE_ERR_UNSUPPORTED -19 @@ -73,8 +73,8 @@ #define CFE_ERR_NOTREADY -36 -#define CFE_ERR_GETMEM -37 -#define CFE_ERR_SETMEM -38 +#define CFE_ERR_GETMEM -37 +#define CFE_ERR_SETMEM -38 #define CFE_ERR_NOTCONN -39 #define CFE_ERR_ADDRINUSE -40 diff --git a/arch/mips/include/asm/fw/fw.h b/arch/mips/include/asm/fw/fw.h new file mode 100644 index 00000000000..f3e6978aad7 --- /dev/null +++ b/arch/mips/include/asm/fw/fw.h @@ -0,0 +1,47 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. + */ +#ifndef __ASM_FW_H_ +#define __ASM_FW_H_ + +#include <asm/bootinfo.h> /* For cleaner code... */ + +enum fw_memtypes { + fw_dontuse, + fw_code, + fw_free, +}; + +typedef struct { + unsigned long base; /* Within KSEG0 */ + unsigned int size; /* bytes */ + enum fw_memtypes type; /* fw_memtypes */ +} fw_memblock_t; + +/* Maximum number of memory block descriptors. */ +#define FW_MAX_MEMBLOCKS 32 + +extern int fw_argc; +extern int *_fw_argv; +extern int *_fw_envp; + +/* + * Most firmware like YAMON, PMON, etc. pass arguments and environment + * variables as 32-bit pointers. These take care of sign extension. + */ +#define fw_argv(index) ((char *)(long)_fw_argv[(index)]) +#define fw_envp(index) ((char *)(long)_fw_envp[(index)]) + +extern void fw_init_cmdline(void); +extern char *fw_getcmdline(void); +extern fw_memblock_t *fw_getmdesc(int); +extern void fw_meminit(void); +extern char *fw_getenv(char *name); +extern unsigned long fw_getenvl(char *name); +extern void fw_init_early_console(char port); + +#endif /* __ASM_FW_H_ */ diff --git a/arch/mips/include/asm/gcmpregs.h b/arch/mips/include/asm/gcmpregs.h deleted file mode 100644 index c0cf76a2ca8..00000000000 --- a/arch/mips/include/asm/gcmpregs.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000, 07 MIPS Technologies, Inc. - * - * Multiprocessor Subsystem Register Definitions - * - */ -#ifndef _ASM_GCMPREGS_H -#define _ASM_GCMPREGS_H - - -/* Offsets to major blocks within GCMP from GCMP base */ -#define GCMP_GCB_OFS 0x0000 /* Global Control Block */ -#define GCMP_CLCB_OFS 0x2000 /* Core Local Control Block */ -#define GCMP_COCB_OFS 0x4000 /* Core Other Control Block */ -#define GCMP_GDB_OFS 0x8000 /* Global Debug Block */ - -/* Offsets to individual GCMP registers from GCMP base */ -#define GCMPOFS(block, tag, reg) \ - (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) -#define GCMPOFSn(block, tag, reg, n) \ - (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n)) - -#define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg) -#define GCMPGCBOFSn(reg, n) GCMPOFSn(GCB, GCB, reg, n) -#define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg) -#define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg) -#define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg) - -/* GCMP register access */ -#define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg)) -#define GCMPGCBn(reg, n) REGP(_gcmp_base, GCMPGCBOFSn(reg, n)) -#define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg)) -#define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg)) -#define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg)) - -/* Mask generation */ -#define GCMPMSK(block, reg, bits) (MSK(bits)<<GCMP_##block##_##reg##_SHF) -#define GCMPGCBMSK(reg, bits) GCMPMSK(GCB, reg, bits) -#define GCMPCCBMSK(reg, bits) GCMPMSK(CCB, reg, bits) -#define GCMPGDBMSK(reg, bits) GCMPMSK(GDB, reg, bits) - -/* GCB registers */ -#define GCMP_GCB_GC_OFS 0x0000 /* Global Config Register */ -#define GCMP_GCB_GC_NUMIOCU_SHF 8 -#define GCMP_GCB_GC_NUMIOCU_MSK GCMPGCBMSK(GC_NUMIOCU, 4) -#define GCMP_GCB_GC_NUMCORES_SHF 0 -#define GCMP_GCB_GC_NUMCORES_MSK GCMPGCBMSK(GC_NUMCORES, 8) -#define GCMP_GCB_GCMPB_OFS 0x0008 /* Global GCMP Base */ -#define GCMP_GCB_GCMPB_GCMPBASE_SHF 15 -#define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17) -#define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0 -#define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2) -#define GCMP_GCB_GCMPB_CMDEFTGT_DISABLED 0 -#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 1 -#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 -#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 -#define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */ -#define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */ -#define GCMP_GCB_GCSRAP_CMACCESS_SHF 0 -#define GCMP_GCB_GCSRAP_CMACCESS_MSK GCMPGCBMSK(GCSRAP_CMACCESS, 8) -#define GCMP_GCB_GCMPREV_OFS 0x0030 /* GCMP Revision Register */ -#define GCMP_GCB_GCMEM_OFS 0x0040 /* Global CM Error Mask */ -#define GCMP_GCB_GCMEC_OFS 0x0048 /* Global CM Error Cause */ -#define GCMP_GCB_GMEC_ERROR_TYPE_SHF 27 -#define GCMP_GCB_GMEC_ERROR_TYPE_MSK GCMPGCBMSK(GMEC_ERROR_TYPE, 5) -#define GCMP_GCB_GMEC_ERROR_INFO_SHF 0 -#define GCMP_GCB_GMEC_ERROR_INFO_MSK GCMPGCBMSK(GMEC_ERROR_INFO, 27) -#define GCMP_GCB_GCMEA_OFS 0x0050 /* Global CM Error Address */ -#define GCMP_GCB_GCMEO_OFS 0x0058 /* Global CM Error Multiple */ -#define GCMP_GCB_GMEO_ERROR_2ND_SHF 0 -#define GCMP_GCB_GMEO_ERROR_2ND_MSK GCMPGCBMSK(GMEO_ERROR_2ND, 5) -#define GCMP_GCB_GICBA_OFS 0x0080 /* Global Interrupt Controller Base Address */ -#define GCMP_GCB_GICBA_BASE_SHF 17 -#define GCMP_GCB_GICBA_BASE_MSK GCMPGCBMSK(GICBA_BASE, 15) -#define GCMP_GCB_GICBA_EN_SHF 0 -#define GCMP_GCB_GICBA_EN_MSK GCMPGCBMSK(GICBA_EN, 1) - -/* GCB Regions */ -#define GCMP_GCB_CMxBASE_OFS(n) (0x0090+16*(n)) /* Global Region[0-3] Base Address */ -#define GCMP_GCB_CMxBASE_BASE_SHF 16 -#define GCMP_GCB_CMxBASE_BASE_MSK GCMPGCBMSK(CMxBASE_BASE, 16) -#define GCMP_GCB_CMxMASK_OFS(n) (0x0098+16*(n)) /* Global Region[0-3] Address Mask */ -#define GCMP_GCB_CMxMASK_MASK_SHF 16 -#define GCMP_GCB_CMxMASK_MASK_MSK GCMPGCBMSK(CMxMASK_MASK, 16) -#define GCMP_GCB_CMxMASK_CMREGTGT_SHF 0 -#define GCMP_GCB_CMxMASK_CMREGTGT_MSK GCMPGCBMSK(CMxMASK_CMREGTGT, 2) -#define GCMP_GCB_CMxMASK_CMREGTGT_MEM 0 -#define GCMP_GCB_CMxMASK_CMREGTGT_MEM1 1 -#define GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2 -#define GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3 - - -/* Core local/Core other control block registers */ -#define GCMP_CCB_RESETR_OFS 0x0000 /* Reset Release */ -#define GCMP_CCB_RESETR_INRESET_SHF 0 -#define GCMP_CCB_RESETR_INRESET_MSK GCMPCCBMSK(RESETR_INRESET, 16) -#define GCMP_CCB_COHCTL_OFS 0x0008 /* Coherence Control */ -#define GCMP_CCB_COHCTL_DOMAIN_SHF 0 -#define GCMP_CCB_COHCTL_DOMAIN_MSK GCMPCCBMSK(COHCTL_DOMAIN, 8) -#define GCMP_CCB_CFG_OFS 0x0010 /* Config */ -#define GCMP_CCB_CFG_IOCUTYPE_SHF 10 -#define GCMP_CCB_CFG_IOCUTYPE_MSK GCMPCCBMSK(CFG_IOCUTYPE, 2) -#define GCMP_CCB_CFG_IOCUTYPE_CPU 0 -#define GCMP_CCB_CFG_IOCUTYPE_NCIOCU 1 -#define GCMP_CCB_CFG_IOCUTYPE_CIOCU 2 -#define GCMP_CCB_CFG_NUMVPE_SHF 0 -#define GCMP_CCB_CFG_NUMVPE_MSK GCMPCCBMSK(CFG_NUMVPE, 10) -#define GCMP_CCB_OTHER_OFS 0x0018 /* Other Address */ -#define GCMP_CCB_OTHER_CORENUM_SHF 16 -#define GCMP_CCB_OTHER_CORENUM_MSK GCMPCCBMSK(OTHER_CORENUM, 16) -#define GCMP_CCB_RESETBASE_OFS 0x0020 /* Reset Exception Base */ -#define GCMP_CCB_RESETBASE_BEV_SHF 12 -#define GCMP_CCB_RESETBASE_BEV_MSK GCMPCCBMSK(RESETBASE_BEV, 20) -#define GCMP_CCB_ID_OFS 0x0028 /* Identification */ -#define GCMP_CCB_DINTGROUP_OFS 0x0030 /* DINT Group Participate */ -#define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */ - -extern int __init gcmp_probe(unsigned long, unsigned long); -extern int __init gcmp_niocu(void); -extern void __init gcmp_setregion(int, unsigned long, unsigned long, int); -#endif /* _ASM_GCMPREGS_H */ diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index 37620db588b..10f6a99f92c 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h @@ -11,6 +11,9 @@ #ifndef _ASM_GICREGS_H #define _ASM_GICREGS_H +#include <linux/bitmap.h> +#include <linux/threads.h> + #undef GICISBYTELITTLEENDIAN /* Constants */ @@ -66,7 +69,7 @@ /* Register Map for Shared Section */ -#define GIC_SH_CONFIG_OFS 0x0000 +#define GIC_SH_CONFIG_OFS 0x0000 /* Shared Global Counter */ #define GIC_SH_COUNTER_31_00_OFS 0x0010 @@ -146,13 +149,13 @@ #define GIC_SH_PEND_223_192_OFS 0x0498 #define GIC_SH_PEND_255_224_OFS 0x049c -#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500 +#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500 /* Maps Interrupt X to a Pin */ #define GIC_SH_MAP_TO_PIN(intr) \ (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr)) -#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000 +#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000 /* Maps Interrupt X to a VPE */ #define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \ @@ -202,7 +205,7 @@ #define GIC_VPE_WD_COUNT0_OFS 0x0094 #define GIC_VPE_WD_INITIAL0_OFS 0x0098 #define GIC_VPE_COMPARE_LO_OFS 0x00a0 -#define GIC_VPE_COMPARE_HI 0x00a4 +#define GIC_VPE_COMPARE_HI_OFS 0x00a4 #define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 #define GIC_VPE_EIC_SS(intr) \ @@ -326,7 +329,7 @@ struct gic_intr_map { unsigned int polarity; /* Polarity : +/- */ unsigned int trigtype; /* Trigger : Edge/Levl */ unsigned int flags; /* Misc flags */ -#define GIC_FLAG_IPI 0x01 +#define GIC_FLAG_IPI 0x01 #define GIC_FLAG_TRANSPARENT 0x02 }; @@ -343,11 +346,11 @@ struct gic_shared_intr_map { /* GIC nomenclature for Core Interrupt Pins. */ #define GIC_CPU_INT0 0 /* Core Interrupt 2 */ -#define GIC_CPU_INT1 1 /* . */ -#define GIC_CPU_INT2 2 /* . */ -#define GIC_CPU_INT3 3 /* . */ -#define GIC_CPU_INT4 4 /* . */ -#define GIC_CPU_INT5 5 /* Core Interrupt 5 */ +#define GIC_CPU_INT1 1 /* . */ +#define GIC_CPU_INT2 2 /* . */ +#define GIC_CPU_INT3 3 /* . */ +#define GIC_CPU_INT4 4 /* . */ +#define GIC_CPU_INT5 5 /* Core Interrupt 7 */ /* Local GIC interrupts. */ #define GIC_INT_TMR (GIC_CPU_INT5) @@ -359,6 +362,11 @@ struct gic_shared_intr_map { /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ #define GIC_PIN_TO_VEC_OFFSET (1) +#include <linux/clocksource.h> +#include <linux/irq.h> + +extern unsigned int gic_present; +extern unsigned int gic_frequency; extern unsigned long _gic_base; extern unsigned int gic_irq_base; extern unsigned int gic_irq_flags[]; @@ -367,18 +375,21 @@ extern struct gic_shared_intr_map gic_shared_intr_map[]; extern void gic_init(unsigned long gic_base_addr, unsigned long gic_addrspace_size, struct gic_intr_map *intrmap, unsigned int intrmap_size, unsigned int irqbase); - extern void gic_clocksource_init(unsigned int); -extern unsigned int gic_get_int(void); +extern unsigned int gic_compare_int (void); +extern cycle_t gic_read_count(void); +extern cycle_t gic_read_compare(void); +extern void gic_write_compare(cycle_t cnt); +extern void gic_write_cpu_compare(cycle_t cnt, int cpu); extern void gic_send_ipi(unsigned int intr); extern unsigned int plat_ipi_call_int_xlate(unsigned int); extern unsigned int plat_ipi_resched_int_xlate(unsigned int); extern void gic_bind_eic_interrupt(int irq, int set); extern unsigned int gic_get_timer_pending(void); +extern unsigned int gic_get_int(void); extern void gic_enable_interrupt(int irq_vec); extern void gic_disable_interrupt(int irq_vec); extern void gic_irq_ack(struct irq_data *d); extern void gic_finish_irq(struct irq_data *d); extern void gic_platform_init(int irqs, struct irq_chip *irq_controller); - #endif /* _ASM_GICREGS_H */ diff --git a/arch/mips/include/asm/gio_device.h b/arch/mips/include/asm/gio_device.h index 5437c84664b..4be1a57cdbb 100644 --- a/arch/mips/include/asm/gio_device.h +++ b/arch/mips/include/asm/gio_device.h @@ -6,15 +6,15 @@ struct gio_device_id { }; struct gio_device { - struct device dev; + struct device dev; struct resource resource; - unsigned int irq; - unsigned int slotno; + unsigned int irq; + unsigned int slotno; - const char *name; + const char *name; struct gio_device_id id; - unsigned id32:1; - unsigned gio64:1; + unsigned id32:1; + unsigned gio64:1; }; #define to_gio_device(d) container_of(d, struct gio_device, dev) @@ -50,7 +50,7 @@ static inline void gio_device_free(struct gio_device *dev) extern int gio_register_driver(struct gio_driver *); extern void gio_unregister_driver(struct gio_driver *); -#define gio_get_drvdata(_dev) drv_get_drvdata(&(_dev)->dev) -#define gio_set_drvdata(_dev, data) drv_set_drvdata(&(_dev)->dev, (data)) +#define gio_get_drvdata(_dev) dev_get_drvdata(&(_dev)->dev) +#define gio_set_drvdata(_dev, data) dev_set_drvdata(&(_dev)->dev, (data)) extern void gio_set_master(struct gio_device *); diff --git a/arch/mips/include/asm/gt64120.h b/arch/mips/include/asm/gt64120.h index 0aa44abc77f..2e72abb9440 100644 --- a/arch/mips/include/asm/gt64120.h +++ b/arch/mips/include/asm/gt64120.h @@ -34,7 +34,7 @@ #define GT_MULTI_OFS 0x120 -/* CPU Address Decode. */ +/* CPU Address Decode. */ #define GT_SCS10LD_OFS 0x008 #define GT_SCS10HD_OFS 0x010 #define GT_SCS32LD_OFS 0x018 @@ -106,12 +106,12 @@ #define GT_ADERR_OFS 0x470 -/* SDRAM Configuration. */ +/* SDRAM Configuration. */ #define GT_SDRAM_CFG_OFS 0x448 #define GT_SDRAM_OPMODE_OFS 0x474 #define GT_SDRAM_BM_OFS 0x478 -#define GT_SDRAM_ADDRDECODE_OFS 0x47c +#define GT_SDRAM_ADDRDECODE_OFS 0x47c /* SDRAM Parameters. */ #define GT_SDRAM_B0_OFS 0x44c @@ -126,14 +126,14 @@ #define GT_DEV_B3_OFS 0x468 #define GT_DEV_BOOT_OFS 0x46c -/* ECC. */ +/* ECC. */ #define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */ #define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */ #define GT_ECC_MEM 0x488 /* GT-64120A only */ #define GT_ECC_CALC 0x48c /* GT-64120A only */ #define GT_ECC_ERRADDR 0x490 /* GT-64120A only */ -/* DMA Record. */ +/* DMA Record. */ #define GT_DMA0_CNT_OFS 0x800 #define GT_DMA1_CNT_OFS 0x804 #define GT_DMA2_CNT_OFS 0x808 @@ -156,13 +156,13 @@ #define GT_DMA2_CUR_OFS 0x878 #define GT_DMA3_CUR_OFS 0x87c -/* DMA Channel Control. */ +/* DMA Channel Control. */ #define GT_DMA0_CTRL_OFS 0x840 #define GT_DMA1_CTRL_OFS 0x844 #define GT_DMA2_CTRL_OFS 0x848 #define GT_DMA3_CTRL_OFS 0x84c -/* DMA Arbiter. */ +/* DMA Arbiter. */ #define GT_DMA_ARB_OFS 0x860 /* Timer/Counter. */ @@ -220,7 +220,7 @@ #define GT_PCI0_CFGADDR_OFS 0xcf8 #define GT_PCI0_CFGDATA_OFS 0xcfc -/* Interrupts. */ +/* Interrupts. */ #define GT_INTRCAUSE_OFS 0xc18 #define GT_INTRMASK_OFS 0xc1c @@ -547,15 +547,15 @@ #define GT_DEF_BASE 0x14000000UL #define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ -#define GT_LATTIM_MIN 6 /* Minimum lat */ +#define GT_LATTIM_MIN 6 /* Minimum lat */ /* * The gt64120_dep.h file must define the following macros * * GT_READ(ofs, data_pointer) - * GT_WRITE(ofs, data) - read/write GT64120 registers in 32bit + * GT_WRITE(ofs, data) - read/write GT64120 registers in 32bit * - * TIMER - gt64120 timer irq, temporary solution until + * TIMER - gt64120 timer irq, temporary solution until * full gt64120 cascade interrupt support is in place */ diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index f0324e92d08..e3ee92d4dbe 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -10,34 +10,13 @@ #ifndef _ASM_HAZARDS_H #define _ASM_HAZARDS_H -#ifdef __ASSEMBLY__ -#define ASMMACRO(name, code...) .macro name; code; .endm -#else - -#include <asm/cpu-features.h> - -#define ASMMACRO(name, code...) \ -__asm__(".macro " #name "; " #code "; .endm"); \ - \ -static inline void name(void) \ -{ \ - __asm__ __volatile__ (#name); \ -} - -/* - * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine. - */ -extern void mips_ihb(void); +#include <linux/stringify.h> -#endif +#define ___ssnop \ + sll $0, $0, 1 -ASMMACRO(_ssnop, - sll $0, $0, 1 - ) - -ASMMACRO(_ehb, - sll $0, $0, 3 - ) +#define ___ehb \ + sll $0, $0, 3 /* * TLB hazards @@ -48,27 +27,27 @@ ASMMACRO(_ehb, * MIPSR2 defines ehb for hazard avoidance */ -ASMMACRO(mtc0_tlbw_hazard, - _ehb - ) -ASMMACRO(tlbw_use_hazard, - _ehb - ) -ASMMACRO(tlb_probe_hazard, - _ehb - ) -ASMMACRO(irq_enable_hazard, - _ehb - ) -ASMMACRO(irq_disable_hazard, - _ehb - ) -ASMMACRO(back_to_back_c0_hazard, - _ehb - ) +#define __mtc0_tlbw_hazard \ + ___ehb + +#define __tlbw_use_hazard \ + ___ehb + +#define __tlb_probe_hazard \ + ___ehb + +#define __irq_enable_hazard \ + ___ehb + +#define __irq_disable_hazard \ + ___ehb + +#define __back_to_back_c0_hazard \ + ___ehb + /* * gcc has a tradition of misscompiling the previous construct using the - * address of a label as argument to inline assembler. Gas otoh has the + * address of a label as argument to inline assembler. Gas otoh has the * annoying difference between la and dla which are only usable for 32-bit * rsp. 64-bit code, so can't be used without conditional compilation. * The alterantive is switching the assembler to 64-bit code which happens @@ -94,27 +73,45 @@ do { \ * These are slightly complicated by the fact that we guarantee R1 kernels to * run fine on R2 processors. */ -ASMMACRO(mtc0_tlbw_hazard, - _ssnop; _ssnop; _ehb - ) -ASMMACRO(tlbw_use_hazard, - _ssnop; _ssnop; _ssnop; _ehb - ) -ASMMACRO(tlb_probe_hazard, - _ssnop; _ssnop; _ssnop; _ehb - ) -ASMMACRO(irq_enable_hazard, - _ssnop; _ssnop; _ssnop; _ehb - ) -ASMMACRO(irq_disable_hazard, - _ssnop; _ssnop; _ssnop; _ehb - ) -ASMMACRO(back_to_back_c0_hazard, - _ssnop; _ssnop; _ssnop; _ehb - ) + +#define __mtc0_tlbw_hazard \ + ___ssnop; \ + ___ssnop; \ + ___ehb + +#define __tlbw_use_hazard \ + ___ssnop; \ + ___ssnop; \ + ___ssnop; \ + ___ehb + +#define __tlb_probe_hazard \ + ___ssnop; \ + ___ssnop; \ + ___ssnop; \ + ___ehb + +#define __irq_enable_hazard \ + ___ssnop; \ + ___ssnop; \ + ___ssnop; \ + ___ehb + +#define __irq_disable_hazard \ + ___ssnop; \ + ___ssnop; \ + ___ssnop; \ + ___ehb + +#define __back_to_back_c0_hazard \ + ___ssnop; \ + ___ssnop; \ + ___ssnop; \ + ___ehb + /* * gcc has a tradition of misscompiling the previous construct using the - * address of a label as argument to inline assembler. Gas otoh has the + * address of a label as argument to inline assembler. Gas otoh has the * annoying difference between la and dla which are only usable for 32-bit * rsp. 64-bit code, so can't be used without conditional compilation. * The alterantive is switching the assembler to 64-bit code which happens @@ -141,24 +138,24 @@ do { \ #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ - defined(CONFIG_CPU_R5500) + defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. */ -ASMMACRO(mtc0_tlbw_hazard, - ) -ASMMACRO(tlbw_use_hazard, - ) -ASMMACRO(tlb_probe_hazard, - ) -ASMMACRO(irq_enable_hazard, - ) -ASMMACRO(irq_disable_hazard, - ) -ASMMACRO(back_to_back_c0_hazard, - ) +#define __mtc0_tlbw_hazard + +#define __tlbw_use_hazard + +#define __tlb_probe_hazard + +#define __irq_enable_hazard + +#define __irq_disable_hazard + +#define __back_to_back_c0_hazard + #define instruction_hazard() do { } while (0) #elif defined(CONFIG_CPU_SB1) @@ -166,19 +163,21 @@ ASMMACRO(back_to_back_c0_hazard, /* * Mostly like R4000 for historic reasons */ -ASMMACRO(mtc0_tlbw_hazard, - ) -ASMMACRO(tlbw_use_hazard, - ) -ASMMACRO(tlb_probe_hazard, - ) -ASMMACRO(irq_enable_hazard, - ) -ASMMACRO(irq_disable_hazard, - _ssnop; _ssnop; _ssnop - ) -ASMMACRO(back_to_back_c0_hazard, - ) +#define __mtc0_tlbw_hazard + +#define __tlbw_use_hazard + +#define __tlb_probe_hazard + +#define __irq_enable_hazard + +#define __irq_disable_hazard \ + ___ssnop; \ + ___ssnop; \ + ___ssnop + +#define __back_to_back_c0_hazard + #define instruction_hazard() do { } while (0) #else @@ -192,24 +191,35 @@ ASMMACRO(back_to_back_c0_hazard, * hazard so this is nice trick to have an optimal code for a range of * processors. */ -ASMMACRO(mtc0_tlbw_hazard, - nop; nop - ) -ASMMACRO(tlbw_use_hazard, - nop; nop; nop - ) -ASMMACRO(tlb_probe_hazard, - nop; nop; nop - ) -ASMMACRO(irq_enable_hazard, - _ssnop; _ssnop; _ssnop; - ) -ASMMACRO(irq_disable_hazard, - nop; nop; nop - ) -ASMMACRO(back_to_back_c0_hazard, - _ssnop; _ssnop; _ssnop; - ) +#define __mtc0_tlbw_hazard \ + nop; \ + nop + +#define __tlbw_use_hazard \ + nop; \ + nop; \ + nop + +#define __tlb_probe_hazard \ + nop; \ + nop; \ + nop + +#define __irq_enable_hazard \ + ___ssnop; \ + ___ssnop; \ + ___ssnop + +#define __irq_disable_hazard \ + nop; \ + nop; \ + nop + +#define __back_to_back_c0_hazard \ + ___ssnop; \ + ___ssnop; \ + ___ssnop + #define instruction_hazard() do { } while (0) #endif @@ -218,32 +228,137 @@ ASMMACRO(back_to_back_c0_hazard, /* FPU hazards */ #if defined(CONFIG_CPU_SB1) -ASMMACRO(enable_fpu_hazard, - .set push; - .set mips64; - .set noreorder; - _ssnop; - bnezl $0, .+4; - _ssnop; - .set pop -) -ASMMACRO(disable_fpu_hazard, -) + +#define __enable_fpu_hazard \ + .set push; \ + .set mips64; \ + .set noreorder; \ + ___ssnop; \ + bnezl $0, .+4; \ + ___ssnop; \ + .set pop + +#define __disable_fpu_hazard #elif defined(CONFIG_CPU_MIPSR2) -ASMMACRO(enable_fpu_hazard, - _ehb -) -ASMMACRO(disable_fpu_hazard, - _ehb -) + +#define __enable_fpu_hazard \ + ___ehb + +#define __disable_fpu_hazard \ + ___ehb + #else -ASMMACRO(enable_fpu_hazard, - nop; nop; nop; nop -) -ASMMACRO(disable_fpu_hazard, - _ehb -) + +#define __enable_fpu_hazard \ + nop; \ + nop; \ + nop; \ + nop + +#define __disable_fpu_hazard \ + ___ehb + #endif +#ifdef __ASSEMBLY__ + +#define _ssnop ___ssnop +#define _ehb ___ehb +#define mtc0_tlbw_hazard __mtc0_tlbw_hazard +#define tlbw_use_hazard __tlbw_use_hazard +#define tlb_probe_hazard __tlb_probe_hazard +#define irq_enable_hazard __irq_enable_hazard +#define irq_disable_hazard __irq_disable_hazard +#define back_to_back_c0_hazard __back_to_back_c0_hazard +#define enable_fpu_hazard __enable_fpu_hazard +#define disable_fpu_hazard __disable_fpu_hazard + +#else + +#define _ssnop() \ +do { \ + __asm__ __volatile__( \ + __stringify(___ssnop) \ + ); \ +} while (0) + +#define _ehb() \ +do { \ + __asm__ __volatile__( \ + __stringify(___ehb) \ + ); \ +} while (0) + + +#define mtc0_tlbw_hazard() \ +do { \ + __asm__ __volatile__( \ + __stringify(__mtc0_tlbw_hazard) \ + ); \ +} while (0) + + +#define tlbw_use_hazard() \ +do { \ + __asm__ __volatile__( \ + __stringify(__tlbw_use_hazard) \ + ); \ +} while (0) + + +#define tlb_probe_hazard() \ +do { \ + __asm__ __volatile__( \ + __stringify(__tlb_probe_hazard) \ + ); \ +} while (0) + + +#define irq_enable_hazard() \ +do { \ + __asm__ __volatile__( \ + __stringify(__irq_enable_hazard) \ + ); \ +} while (0) + + +#define irq_disable_hazard() \ +do { \ + __asm__ __volatile__( \ + __stringify(__irq_disable_hazard) \ + ); \ +} while (0) + + +#define back_to_back_c0_hazard() \ +do { \ + __asm__ __volatile__( \ + __stringify(__back_to_back_c0_hazard) \ + ); \ +} while (0) + + +#define enable_fpu_hazard() \ +do { \ + __asm__ __volatile__( \ + __stringify(__enable_fpu_hazard) \ + ); \ +} while (0) + + +#define disable_fpu_hazard() \ +do { \ + __asm__ __volatile__( \ + __stringify(__disable_fpu_hazard) \ + ); \ +} while (0) + +/* + * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine. + */ +extern void mips_ihb(void); + +#endif /* __ASSEMBLY__ */ + #endif /* _ASM_HAZARDS_H */ diff --git a/arch/mips/include/asm/highmem.h b/arch/mips/include/asm/highmem.h index 2d91888c9b7..572e63ec2a3 100644 --- a/arch/mips/include/asm/highmem.h +++ b/arch/mips/include/asm/highmem.h @@ -19,7 +19,6 @@ #ifdef __KERNEL__ -#include <linux/init.h> #include <linux/interrupt.h> #include <linux/uaccess.h> #include <asm/kmap_types.h> @@ -39,8 +38,8 @@ extern pte_t *pkmap_page_table; */ #define LAST_PKMAP 1024 #define LAST_PKMAP_MASK (LAST_PKMAP-1) -#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT) -#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) +#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT) +#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) extern void * kmap_high(struct page *page); extern void kunmap_high(struct page *page); diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h index ef99db994c2..fe0d15d3266 100644 --- a/arch/mips/include/asm/hugetlb.h +++ b/arch/mips/include/asm/hugetlb.h @@ -10,6 +10,7 @@ #define __ASM_HUGETLB_H #include <asm/page.h> +#include <asm-generic/hugetlb.h> static inline int is_hugepage_only_range(struct mm_struct *mm, diff --git a/arch/mips/include/asm/idle.h b/arch/mips/include/asm/idle.h new file mode 100644 index 00000000000..d9f932de80e --- /dev/null +++ b/arch/mips/include/asm/idle.h @@ -0,0 +1,37 @@ +#ifndef __ASM_IDLE_H +#define __ASM_IDLE_H + +#include <linux/cpuidle.h> +#include <linux/linkage.h> + +extern void (*cpu_wait)(void); +extern void r4k_wait(void); +extern asmlinkage void __r4k_wait(void); +extern void r4k_wait_irqoff(void); +extern void __pastwait(void); + +static inline int using_rollback_handler(void) +{ + return cpu_wait == r4k_wait; +} + +static inline int address_is_in_r4k_wait_irqoff(unsigned long addr) +{ + return addr >= (unsigned long)r4k_wait_irqoff && + addr < (unsigned long)__pastwait; +} + +extern int mips_cpuidle_wait_enter(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index); + +#define MIPS_CPUIDLE_WAIT_STATE {\ + .enter = mips_cpuidle_wait_enter,\ + .exit_latency = 1,\ + .target_residency = 1,\ + .power_usage = UINT_MAX,\ + .flags = CPUIDLE_FLAG_TIME_VALID,\ + .name = "wait",\ + .desc = "MIPS wait",\ +} + +#endif /* __ASM_IDLE_H */ diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index ab84064283d..22912f78401 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h @@ -11,352 +11,7 @@ #ifndef _ASM_INST_H #define _ASM_INST_H -/* - * Major opcodes; before MIPS IV cop1x was called cop3. - */ -enum major_op { - spec_op, bcond_op, j_op, jal_op, - beq_op, bne_op, blez_op, bgtz_op, - addi_op, addiu_op, slti_op, sltiu_op, - andi_op, ori_op, xori_op, lui_op, - cop0_op, cop1_op, cop2_op, cop1x_op, - beql_op, bnel_op, blezl_op, bgtzl_op, - daddi_op, daddiu_op, ldl_op, ldr_op, - spec2_op, jalx_op, mdmx_op, spec3_op, - lb_op, lh_op, lwl_op, lw_op, - lbu_op, lhu_op, lwr_op, lwu_op, - sb_op, sh_op, swl_op, sw_op, - sdl_op, sdr_op, swr_op, cache_op, - ll_op, lwc1_op, lwc2_op, pref_op, - lld_op, ldc1_op, ldc2_op, ld_op, - sc_op, swc1_op, swc2_op, major_3b_op, - scd_op, sdc1_op, sdc2_op, sd_op -}; - -/* - * func field of spec opcode. - */ -enum spec_op { - sll_op, movc_op, srl_op, sra_op, - sllv_op, pmon_op, srlv_op, srav_op, - jr_op, jalr_op, movz_op, movn_op, - syscall_op, break_op, spim_op, sync_op, - mfhi_op, mthi_op, mflo_op, mtlo_op, - dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, - mult_op, multu_op, div_op, divu_op, - dmult_op, dmultu_op, ddiv_op, ddivu_op, - add_op, addu_op, sub_op, subu_op, - and_op, or_op, xor_op, nor_op, - spec3_unused_op, spec4_unused_op, slt_op, sltu_op, - dadd_op, daddu_op, dsub_op, dsubu_op, - tge_op, tgeu_op, tlt_op, tltu_op, - teq_op, spec5_unused_op, tne_op, spec6_unused_op, - dsll_op, spec7_unused_op, dsrl_op, dsra_op, - dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op -}; - -/* - * func field of spec2 opcode. - */ -enum spec2_op { - madd_op, maddu_op, mul_op, spec2_3_unused_op, - msub_op, msubu_op, /* more unused ops */ - clz_op = 0x20, clo_op, - dclz_op = 0x24, dclo_op, - sdbpp_op = 0x3f -}; - -/* - * func field of spec3 opcode. - */ -enum spec3_op { - ext_op, dextm_op, dextu_op, dext_op, - ins_op, dinsm_op, dinsu_op, dins_op, - lx_op = 0x0a, - bshfl_op = 0x20, - dbshfl_op = 0x24, - rdhwr_op = 0x3b -}; - -/* - * rt field of bcond opcodes. - */ -enum rt_op { - bltz_op, bgez_op, bltzl_op, bgezl_op, - spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, - tgei_op, tgeiu_op, tlti_op, tltiu_op, - teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, - bltzal_op, bgezal_op, bltzall_op, bgezall_op, - rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17, - rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b, - bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f -}; - -/* - * rs field of cop opcodes. - */ -enum cop_op { - mfc_op = 0x00, dmfc_op = 0x01, - cfc_op = 0x02, mtc_op = 0x04, - dmtc_op = 0x05, ctc_op = 0x06, - bc_op = 0x08, cop_op = 0x10, - copm_op = 0x18 -}; - -/* - * rt field of cop.bc_op opcodes - */ -enum bcop_op { - bcf_op, bct_op, bcfl_op, bctl_op -}; - -/* - * func field of cop0 coi opcodes. - */ -enum cop0_coi_func { - tlbr_op = 0x01, tlbwi_op = 0x02, - tlbwr_op = 0x06, tlbp_op = 0x08, - rfe_op = 0x10, eret_op = 0x18 -}; - -/* - * func field of cop0 com opcodes. - */ -enum cop0_com_func { - tlbr1_op = 0x01, tlbw_op = 0x02, - tlbp1_op = 0x08, dctr_op = 0x09, - dctw_op = 0x0a -}; - -/* - * fmt field of cop1 opcodes. - */ -enum cop1_fmt { - s_fmt, d_fmt, e_fmt, q_fmt, - w_fmt, l_fmt -}; - -/* - * func field of cop1 instructions using d, s or w format. - */ -enum cop1_sdw_func { - fadd_op = 0x00, fsub_op = 0x01, - fmul_op = 0x02, fdiv_op = 0x03, - fsqrt_op = 0x04, fabs_op = 0x05, - fmov_op = 0x06, fneg_op = 0x07, - froundl_op = 0x08, ftruncl_op = 0x09, - fceill_op = 0x0a, ffloorl_op = 0x0b, - fround_op = 0x0c, ftrunc_op = 0x0d, - fceil_op = 0x0e, ffloor_op = 0x0f, - fmovc_op = 0x11, fmovz_op = 0x12, - fmovn_op = 0x13, frecip_op = 0x15, - frsqrt_op = 0x16, fcvts_op = 0x20, - fcvtd_op = 0x21, fcvte_op = 0x22, - fcvtw_op = 0x24, fcvtl_op = 0x25, - fcmp_op = 0x30 -}; - -/* - * func field of cop1x opcodes (MIPS IV). - */ -enum cop1x_func { - lwxc1_op = 0x00, ldxc1_op = 0x01, - pfetch_op = 0x07, swxc1_op = 0x08, - sdxc1_op = 0x09, madd_s_op = 0x20, - madd_d_op = 0x21, madd_e_op = 0x22, - msub_s_op = 0x28, msub_d_op = 0x29, - msub_e_op = 0x2a, nmadd_s_op = 0x30, - nmadd_d_op = 0x31, nmadd_e_op = 0x32, - nmsub_s_op = 0x38, nmsub_d_op = 0x39, - nmsub_e_op = 0x3a -}; - -/* - * func field for mad opcodes (MIPS IV). - */ -enum mad_func { - madd_fp_op = 0x08, msub_fp_op = 0x0a, - nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e -}; - -/* - * func field for special3 lx opcodes (Cavium Octeon). - */ -enum lx_func { - lwx_op = 0x00, - lhx_op = 0x04, - lbux_op = 0x06, - ldx_op = 0x08, - lwux_op = 0x10, - lhux_op = 0x14, - lbx_op = 0x16, -}; - -/* - * Damn ... bitfields depend from byteorder :-( - */ -#ifdef __MIPSEB__ -struct j_format { /* Jump format */ - unsigned int opcode : 6; - unsigned int target : 26; -}; - -struct i_format { /* Immediate format (addi, lw, ...) */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - signed int simmediate : 16; -}; - -struct u_format { /* Unsigned immediate format (ori, xori, ...) */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int uimmediate : 16; -}; - -struct c_format { /* Cache (>= R6000) format */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int c_op : 3; - unsigned int cache : 2; - unsigned int simmediate : 16; -}; - -struct r_format { /* Register format */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; -}; - -struct p_format { /* Performance counter format (R10000) */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; -}; - -struct f_format { /* FPU register format */ - unsigned int opcode : 6; - unsigned int : 1; - unsigned int fmt : 4; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; -}; - -struct ma_format { /* FPU multiply and add format (MIPS IV) */ - unsigned int opcode : 6; - unsigned int fr : 5; - unsigned int ft : 5; - unsigned int fs : 5; - unsigned int fd : 5; - unsigned int func : 4; - unsigned int fmt : 2; -}; - -struct b_format { /* BREAK and SYSCALL */ - unsigned int opcode:6; - unsigned int code:20; - unsigned int func:6; -}; - -#elif defined(__MIPSEL__) - -struct j_format { /* Jump format */ - unsigned int target : 26; - unsigned int opcode : 6; -}; - -struct i_format { /* Immediate format */ - signed int simmediate : 16; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct u_format { /* Unsigned immediate format */ - unsigned int uimmediate : 16; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct c_format { /* Cache (>= R6000) format */ - unsigned int simmediate : 16; - unsigned int cache : 2; - unsigned int c_op : 3; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct r_format { /* Register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct p_format { /* Performance counter format (R10000) */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct f_format { /* FPU register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int fmt : 4; - unsigned int : 1; - unsigned int opcode : 6; -}; - -struct ma_format { /* FPU multiply and add format (MIPS IV) */ - unsigned int fmt : 2; - unsigned int func : 4; - unsigned int fd : 5; - unsigned int fs : 5; - unsigned int ft : 5; - unsigned int fr : 5; - unsigned int opcode : 6; -}; - -struct b_format { /* BREAK and SYSCALL */ - unsigned int func:6; - unsigned int code:20; - unsigned int opcode:6; -}; - -#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */ -#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" -#endif - -union mips_instruction { - unsigned int word; - unsigned short halfword[2]; - unsigned char byte[4]; - struct j_format j_format; - struct i_format i_format; - struct u_format u_format; - struct c_format c_format; - struct r_format r_format; - struct f_format f_format; - struct ma_format ma_format; - struct b_format b_format; -}; +#include <uapi/asm/inst.h> /* HACHACHAHCAHC ... */ @@ -418,4 +73,16 @@ union mips_instruction { typedef unsigned int mips_instruction; +/* microMIPS instruction decode structure. Do NOT export!!! */ +struct mm_decoded_insn { + mips_instruction insn; + mips_instruction next_insn; + int pc_inc; + int next_pc_inc; + int micro_mips_mode; +}; + +/* Recode table from 16-bit register notation to 32-bit GPR. Do NOT export!!! */ +extern const int reg16to32[]; + #endif /* _ASM_INST_H */ diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index ff2e0345e01..933b50e125a 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -7,7 +7,7 @@ * Copyright (C) 1994 - 2000, 06 Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. - * Author: Maciej W. Rozycki <macro@mips.com> + * Author: Maciej W. Rozycki <macro@mips.com> */ #ifndef _ASM_IO_H #define _ASM_IO_H @@ -118,7 +118,7 @@ static inline void set_io_port_base(unsigned long base) */ static inline unsigned long virt_to_phys(volatile const void *address) { - return (unsigned long)address - PAGE_OFFSET + PHYS_OFFSET; + return __pa(address); } /* @@ -170,6 +170,11 @@ static inline void * isa_bus_to_virt(unsigned long address) extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags); extern void __iounmap(const volatile void __iomem *addr); +#ifndef CONFIG_PCI +struct pci_dev; +static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {} +#endif + static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, unsigned long flags) { @@ -253,9 +258,9 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, __ioremap_mode((offset), (size), _CACHE_UNCACHED) /* - * ioremap_cachable - map bus memory into CPU space - * @offset: bus address of the memory - * @size: size of the resource to map + * ioremap_cachable - map bus memory into CPU space + * @offset: bus address of the memory + * @size: size of the resource to map * * ioremap_nocache performs a platform specific sequence of operations to * make bus memory CPU accessible via the readb/readw/readl/writeb/ @@ -264,14 +269,14 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, * address. * * This version of ioremap ensures that the memory is marked cachable by - * the CPU. Also enables full write-combining. Useful for some + * the CPU. Also enables full write-combining. Useful for some * memory-like regions on I/O busses. */ #define ioremap_cachable(offset, size) \ __ioremap_mode((offset), (size), _page_cachable_default) /* - * These two are MIPS specific ioremap variant. ioremap_cacheable_cow + * These two are MIPS specific ioremap variant. ioremap_cacheable_cow * requests a cachable mapping, ioremap_uncached_accelerated requests a * mapping using the uncached accelerated mode which isn't supported on * all processors. @@ -298,7 +303,7 @@ static inline void iounmap(const volatile void __iomem *addr) } #ifdef CONFIG_CPU_CAVIUM_OCTEON -#define war_octeon_io_reorder_wmb() wmb() +#define war_octeon_io_reorder_wmb() wmb() #else #define war_octeon_io_reorder_wmb() do { } while (0) #endif @@ -317,7 +322,7 @@ static inline void pfx##write##bwlq(type val, \ \ __val = pfx##ioswab##bwlq(__mem, val); \ \ - if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ + if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ *__mem = __val; \ else if (cpu_has_64bits) { \ unsigned long __flags; \ @@ -326,10 +331,10 @@ static inline void pfx##write##bwlq(type val, \ if (irq) \ local_irq_save(__flags); \ __asm__ __volatile__( \ - ".set mips3" "\t\t# __writeq""\n\t" \ - "dsll32 %L0, %L0, 0" "\n\t" \ - "dsrl32 %L0, %L0, 0" "\n\t" \ - "dsll32 %M0, %M0, 0" "\n\t" \ + ".set arch=r4000" "\t\t# __writeq""\n\t" \ + "dsll32 %L0, %L0, 0" "\n\t" \ + "dsrl32 %L0, %L0, 0" "\n\t" \ + "dsll32 %M0, %M0, 0" "\n\t" \ "or %L0, %L0, %M0" "\n\t" \ "sd %L0, %2" "\n\t" \ ".set mips0" "\n" \ @@ -348,7 +353,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ \ __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ \ - if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ + if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ __val = *__mem; \ else if (cpu_has_64bits) { \ unsigned long __flags; \ @@ -356,9 +361,9 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ if (irq) \ local_irq_save(__flags); \ __asm__ __volatile__( \ - ".set mips3" "\t\t# __readq" "\n\t" \ + ".set arch=r4000" "\t\t# __readq" "\n\t" \ "ld %L0, %1" "\n\t" \ - "dsra32 %M0, %L0, 0" "\n\t" \ + "dsra32 %M0, %L0, 0" "\n\t" \ "sll %L0, %L0, 0" "\n\t" \ ".set mips0" "\n" \ : "=r" (__val) \ @@ -449,6 +454,11 @@ __BUILDIO(q, u64) #define readl_relaxed readl #define readq_relaxed readq +#define writeb_relaxed writeb +#define writew_relaxed writew +#define writel_relaxed writel +#define writeq_relaxed writeq + #define readb_be(addr) \ __raw_readb((__force unsigned *)(addr)) #define readw_be(addr) \ @@ -574,7 +584,7 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int * * This API used to be exported; it now is for arch code internal use only. */ -#ifdef CONFIG_DMA_NONCOHERENT +#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); @@ -586,14 +596,14 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); #else /* Sane hardware */ -#define dma_cache_wback_inv(start,size) \ +#define dma_cache_wback_inv(start,size) \ do { (void) (start); (void) (size); } while (0) #define dma_cache_wback(start,size) \ do { (void) (start); (void) (size); } while (0) #define dma_cache_inv(start,size) \ do { (void) (start); (void) (size); } while (0) -#endif /* CONFIG_DMA_NONCOHERENT */ +#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ /* * Read a 32-bit register that requires a 64-bit read cycle on the bus. diff --git a/arch/mips/include/asm/ip32/crime.h b/arch/mips/include/asm/ip32/crime.h index 7c36b0e5b1c..16c94a27beb 100644 --- a/arch/mips/include/asm/ip32/crime.h +++ b/arch/mips/include/asm/ip32/crime.h @@ -74,7 +74,7 @@ struct sgi_crime { #define CRIME_RE_IDLE_E_INT BIT(24) #define CRIME_RE_EMPTY_L_INT BIT(25) #define CRIME_RE_FULL_L_INT BIT(26) -#define CRIME_RE_IDLE_L_INT BIT(27) +#define CRIME_RE_IDLE_L_INT BIT(27) #define CRIME_SOFT0_INT BIT(28) #define CRIME_SOFT1_INT BIT(29) #define CRIME_SOFT2_INT BIT(30) @@ -118,7 +118,7 @@ struct sgi_crime { #define CRIME_MEM_REF_COUNTER_MASK 0x3ff /* 10bit */ volatile unsigned long mem_error_stat; -#define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff /* 28-bit register */ +#define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff /* 28-bit register */ #define CRIME_MEM_ERROR_MACE_ID 0x0000007f #define CRIME_MEM_ERROR_MACE_ACCESS 0x00000080 #define CRIME_MEM_ERROR_RE_ID 0x00007f00 @@ -134,8 +134,8 @@ struct sgi_crime { #define CRIME_MEM_ERROR_MEM_ECC_RD 0x00800000 #define CRIME_MEM_ERROR_MEM_ECC_RMW 0x01000000 #define CRIME_MEM_ERROR_INV 0x0e000000 -#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000 -#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000 +#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000 +#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000 #define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000 volatile unsigned long mem_error_addr; diff --git a/arch/mips/include/asm/ip32/ip32_ints.h b/arch/mips/include/asm/ip32/ip32_ints.h index 85bc5302bce..72e3368de11 100644 --- a/arch/mips/include/asm/ip32/ip32_ints.h +++ b/arch/mips/include/asm/ip32/ip32_ints.h @@ -13,7 +13,7 @@ /* * This list reflects the assignment of interrupt numbers to - * interrupting events. Order is fairly irrelevant to handling + * interrupting events. Order is fairly irrelevant to handling * priority. This differs from irix. */ diff --git a/arch/mips/include/asm/ip32/mace.h b/arch/mips/include/asm/ip32/mace.h index c523123df38..253ed7ea80b 100644 --- a/arch/mips/include/asm/ip32/mace.h +++ b/arch/mips/include/asm/ip32/mace.h @@ -250,12 +250,12 @@ struct mace_ps2 { * -> drivers/i2c/algos/i2c-algo-sgi.c */ struct mace_i2c { volatile unsigned long config; -#define MACEI2C_RESET BIT(0) -#define MACEI2C_FAST BIT(1) -#define MACEI2C_DATA_OVERRIDE BIT(2) -#define MACEI2C_CLOCK_OVERRIDE BIT(3) -#define MACEI2C_DATA_STATUS BIT(4) -#define MACEI2C_CLOCK_STATUS BIT(5) +#define MACEI2C_RESET BIT(0) +#define MACEI2C_FAST BIT(1) +#define MACEI2C_DATA_OVERRIDE BIT(2) +#define MACEI2C_CLOCK_OVERRIDE BIT(3) +#define MACEI2C_DATA_STATUS BIT(4) +#define MACEI2C_CLOCK_STATUS BIT(5) volatile unsigned long control; volatile unsigned long data; }; diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index 78dbb8a86da..ae1f7b24dd1 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -26,104 +26,8 @@ static inline int irq_canonicalize(int irq) #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ #endif -#ifdef CONFIG_MIPS_MT_SMTC - -struct irqaction; - -extern unsigned long irq_hwmask[]; -extern int setup_irq_smtc(unsigned int irq, struct irqaction * new, - unsigned long hwmask); - -static inline void smtc_im_ack_irq(unsigned int irq) -{ - if (irq_hwmask[irq] & ST0_IM) - set_c0_status(irq_hwmask[irq] & ST0_IM); -} - -#else - -static inline void smtc_im_ack_irq(unsigned int irq) -{ -} - -#endif /* CONFIG_MIPS_MT_SMTC */ - -#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF -#include <linux/cpumask.h> - -extern int plat_set_irq_affinity(struct irq_data *d, - const struct cpumask *affinity, bool force); -extern void smtc_forward_irq(struct irq_data *d); - -/* - * IRQ affinity hook invoked at the beginning of interrupt dispatch - * if option is enabled. - * - * Up through Linux 2.6.22 (at least) cpumask operations are very - * inefficient on MIPS. Initial prototypes of SMTC IRQ affinity - * used a "fast path" per-IRQ-descriptor cache of affinity information - * to reduce latency. As there is a project afoot to optimize the - * cpumask implementations, this version is optimistically assuming - * that cpumask.h macro overhead is reasonable during interrupt dispatch. - */ -static inline int handle_on_other_cpu(unsigned int irq) -{ - struct irq_data *d = irq_get_irq_data(irq); - - if (cpumask_test_cpu(smp_processor_id(), d->affinity)) - return 0; - smtc_forward_irq(d); - return 1; -} - -#else /* Not doing SMTC affinity */ - -static inline int handle_on_other_cpu(unsigned int irq) { return 0; } - -#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ - -#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP - -static inline void smtc_im_backstop(unsigned int irq) -{ - if (irq_hwmask[irq] & 0x0000ff00) - write_c0_tccontext(read_c0_tccontext() & - ~(irq_hwmask[irq] & 0x0000ff00)); -} - -/* - * Clear interrupt mask handling "backstop" if irq_hwmask - * entry so indicates. This implies that the ack() or end() - * functions will take over re-enabling the low-level mask. - * Otherwise it will be done on return from exception. - */ -static inline int smtc_handle_on_other_cpu(unsigned int irq) -{ - int ret = handle_on_other_cpu(irq); - - if (!ret) - smtc_im_backstop(irq); - return ret; -} - -#else - -static inline void smtc_im_backstop(unsigned int irq) { } -static inline int smtc_handle_on_other_cpu(unsigned int irq) -{ - return handle_on_other_cpu(irq); -} - -#endif - extern void do_IRQ(unsigned int irq); -#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF - -extern void do_IRQ_no_affinity(unsigned int irq); - -#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ - extern void arch_init_irq(void); extern void spurious_interrupt(void); @@ -133,7 +37,7 @@ extern void free_irqno(unsigned int irq); /* * Before R2 the timer and performance counter interrupts were both fixed to - * IE7. Since R2 their number has to be read from the c0_intctl register. + * IE7. Since R2 their number has to be read from the c0_intctl register. */ #define CP0_LEGACY_COMPARE_IRQ 7 #define CP0_LEGACY_PERFCNT_IRQ 7 diff --git a/arch/mips/include/asm/irq_cpu.h b/arch/mips/include/asm/irq_cpu.h index ef6a07cddb2..3f11fdb3ed8 100644 --- a/arch/mips/include/asm/irq_cpu.h +++ b/arch/mips/include/asm/irq_cpu.h @@ -17,4 +17,10 @@ extern void mips_cpu_irq_init(void); extern void rm7k_cpu_irq_init(void); extern void rm9k_cpu_irq_init(void); +#ifdef CONFIG_IRQ_DOMAIN +struct device_node; +extern int mips_cpu_intc_init(struct device_node *of_node, + struct device_node *parent); +#endif + #endif /* _ASM_IRQ_CPU_H */ diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h index 9f3384c789d..0fa5fdcd1f0 100644 --- a/arch/mips/include/asm/irqflags.h +++ b/arch/mips/include/asm/irqflags.h @@ -14,53 +14,48 @@ #ifndef __ASSEMBLY__ #include <linux/compiler.h> +#include <linux/stringify.h> #include <asm/hazards.h> -#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC) +#ifdef CONFIG_CPU_MIPSR2 -__asm__( - " .macro arch_local_irq_disable\n" +static inline void arch_local_irq_disable(void) +{ + __asm__ __volatile__( " .set push \n" " .set noat \n" " di \n" - " irq_disable_hazard \n" + " " __stringify(__irq_disable_hazard) " \n" " .set pop \n" - " .endm \n"); - -static inline void arch_local_irq_disable(void) -{ - __asm__ __volatile__( - "arch_local_irq_disable" - : /* no outputs */ - : /* no inputs */ - : "memory"); + : /* no outputs */ + : /* no inputs */ + : "memory"); } +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags; -__asm__( - " .macro arch_local_irq_save result \n" + asm __volatile__( " .set push \n" " .set reorder \n" " .set noat \n" - " di \\result \n" - " andi \\result, 1 \n" - " irq_disable_hazard \n" + " di %[flags] \n" + " andi %[flags], 1 \n" + " " __stringify(__irq_disable_hazard) " \n" " .set pop \n" - " .endm \n"); + : [flags] "=r" (flags) + : /* no inputs */ + : "memory"); -static inline unsigned long arch_local_irq_save(void) -{ - unsigned long flags; - asm volatile("arch_local_irq_save\t%0" - : "=r" (flags) - : /* no inputs */ - : "memory"); return flags; } +static inline void arch_local_irq_restore(unsigned long flags) +{ + unsigned long __tmp1; -__asm__( - " .macro arch_local_irq_restore flags \n" + __asm__ __volatile__( " .set push \n" " .set noreorder \n" " .set noat \n" @@ -69,7 +64,7 @@ __asm__( * Slow, but doesn't suffer from a relatively unlikely race * condition we're having since days 1. */ - " beqz \\flags, 1f \n" + " beqz %[flags], 1f \n" " di \n" " ei \n" "1: \n" @@ -78,33 +73,44 @@ __asm__( * Fast, dangerous. Life is fun, life is good. */ " mfc0 $1, $12 \n" - " ins $1, \\flags, 0, 1 \n" + " ins $1, %[flags], 0, 1 \n" " mtc0 $1, $12 \n" #endif - " irq_disable_hazard \n" + " " __stringify(__irq_disable_hazard) " \n" " .set pop \n" - " .endm \n"); - -static inline void arch_local_irq_restore(unsigned long flags) -{ - unsigned long __tmp1; - - __asm__ __volatile__( - "arch_local_irq_restore\t%0" - : "=r" (__tmp1) - : "0" (flags) - : "memory"); + : [flags] "=r" (__tmp1) + : "0" (flags) + : "memory"); } static inline void __arch_local_irq_restore(unsigned long flags) { - unsigned long __tmp1; - __asm__ __volatile__( - "arch_local_irq_restore\t%0" - : "=r" (__tmp1) - : "0" (flags) - : "memory"); + " .set push \n" + " .set noreorder \n" + " .set noat \n" +#if defined(CONFIG_IRQ_CPU) + /* + * Slow, but doesn't suffer from a relatively unlikely race + * condition we're having since days 1. + */ + " beqz %[flags], 1f \n" + " di \n" + " ei \n" + "1: \n" +#else + /* + * Fast, dangerous. Life is fun, life is good. + */ + " mfc0 $1, $12 \n" + " ins $1, %[flags], 0, 1 \n" + " mtc0 $1, $12 \n" +#endif + " " __stringify(__irq_disable_hazard) " \n" + " .set pop \n" + : [flags] "=r" (flags) + : "0" (flags) + : "memory"); } #else /* Functions that require preempt_{dis,en}able() are in mips-atomic.c */ @@ -112,20 +118,15 @@ void arch_local_irq_disable(void); unsigned long arch_local_irq_save(void); void arch_local_irq_restore(unsigned long flags); void __arch_local_irq_restore(unsigned long flags); -#endif /* if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC) */ - +#endif /* CONFIG_CPU_MIPSR2 */ -__asm__( - " .macro arch_local_irq_enable \n" +static inline void arch_local_irq_enable(void) +{ + __asm__ __volatile__( " .set push \n" " .set reorder \n" " .set noat \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n" - " ori $1, 0x400 \n" - " xori $1, 0x400 \n" - " mtc0 $1, $2, 1 \n" -#elif defined(CONFIG_CPU_MIPSR2) +#if defined(CONFIG_CPU_MIPSR2) " ei \n" #else " mfc0 $1,$12 \n" @@ -133,59 +134,31 @@ __asm__( " xori $1,0x1e \n" " mtc0 $1,$12 \n" #endif - " irq_enable_hazard \n" + " " __stringify(__irq_enable_hazard) " \n" " .set pop \n" - " .endm"); - -extern void smtc_ipi_replay(void); - -static inline void arch_local_irq_enable(void) -{ -#ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC kernel needs to do a software replay of queued - * IPIs, at the cost of call overhead on each local_irq_enable() - */ - smtc_ipi_replay(); -#endif - __asm__ __volatile__( - "arch_local_irq_enable" - : /* no outputs */ - : /* no inputs */ - : "memory"); + : /* no outputs */ + : /* no inputs */ + : "memory"); } +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; -__asm__( - " .macro arch_local_save_flags flags \n" + asm __volatile__( " .set push \n" " .set reorder \n" -#ifdef CONFIG_MIPS_MT_SMTC - " mfc0 \\flags, $2, 1 \n" -#else - " mfc0 \\flags, $12 \n" -#endif + " mfc0 %[flags], $12 \n" " .set pop \n" - " .endm \n"); + : [flags] "=r" (flags)); -static inline unsigned long arch_local_save_flags(void) -{ - unsigned long flags; - asm volatile("arch_local_save_flags %0" : "=r" (flags)); return flags; } static inline int arch_irqs_disabled_flags(unsigned long flags) { -#ifdef CONFIG_MIPS_MT_SMTC - /* - * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU - */ - return flags & 0x400; -#else return !(flags & 1); -#endif } #endif /* #ifndef __ASSEMBLY__ */ diff --git a/arch/mips/include/asm/isadep.h b/arch/mips/include/asm/isadep.h index 24c6cda7937..b4af6eb24ab 100644 --- a/arch/mips/include/asm/isadep.h +++ b/arch/mips/include/asm/isadep.h @@ -18,7 +18,7 @@ * kernel or user mode? (CP0_STATUS) */ #define KU_MASK 0x08 -#define KU_USER 0x08 +#define KU_USER 0x08 #define KU_KERN 0x00 #else @@ -26,7 +26,7 @@ * kernel or user mode? */ #define KU_MASK 0x18 -#define KU_USER 0x10 +#define KU_USER 0x10 #define KU_KERN 0x00 #endif diff --git a/arch/mips/include/asm/jazz.h b/arch/mips/include/asm/jazz.h index 83f449dec95..a61970d01a8 100644 --- a/arch/mips/include/asm/jazz.h +++ b/arch/mips/include/asm/jazz.h @@ -16,7 +16,7 @@ * instead of 0xe0000000. */ -#define JAZZ_LOCAL_IO_SPACE 0xe0000000 +#define JAZZ_LOCAL_IO_SPACE 0xe0000000 /* * Revision numbers in PICA_ASIC_REVISION @@ -25,24 +25,24 @@ * 0xf0000001 - Rev2 * 0xf0000002 - Rev3 */ -#define PICA_ASIC_REVISION 0xe0000008 +#define PICA_ASIC_REVISION 0xe0000008 /* * The segments of the seven segment LED are mapped * to the control bits as follows: * - * (7) - * --------- - * | | - * (2) | | (6) - * | (1) | - * --------- - * | | - * (3) | | (5) - * | (4) | - * --------- . (0) + * (7) + * --------- + * | | + * (2) | | (6) + * | (1) | + * --------- + * | | + * (3) | | (5) + * | (4) | + * --------- . (0) */ -#define PICA_LED 0xe000f000 +#define PICA_LED 0xe000f000 /* * Some characters for the LED control registers @@ -51,24 +51,24 @@ * control each of the seven segments and the dot independently. * It's only a toy, anyway... */ -#define LED_DOT 0x01 -#define LED_SPACE 0x00 -#define LED_0 0xfc -#define LED_1 0x60 -#define LED_2 0xda -#define LED_3 0xf2 -#define LED_4 0x66 -#define LED_5 0xb6 -#define LED_6 0xbe -#define LED_7 0xe0 -#define LED_8 0xfe -#define LED_9 0xf6 -#define LED_A 0xee -#define LED_b 0x3e -#define LED_C 0x9c -#define LED_d 0x7a -#define LED_E 0x9e -#define LED_F 0x8e +#define LED_DOT 0x01 +#define LED_SPACE 0x00 +#define LED_0 0xfc +#define LED_1 0x60 +#define LED_2 0xda +#define LED_3 0xf2 +#define LED_4 0x66 +#define LED_5 0xb6 +#define LED_6 0xbe +#define LED_7 0xe0 +#define LED_8 0xfe +#define LED_9 0xf6 +#define LED_A 0xee +#define LED_b 0x3e +#define LED_C 0x9c +#define LED_d 0x7a +#define LED_E 0x9e +#define LED_F 0x8e #ifndef __ASSEMBLY__ @@ -96,9 +96,9 @@ static __inline__ void pica_set_led(unsigned int bits) * This address is just a guess and seems to differ from * other mips machines such as RC3xxx... */ -#define JAZZ_KEYBOARD_ADDRESS 0xe0005000 -#define JAZZ_KEYBOARD_DATA 0xe0005000 -#define JAZZ_KEYBOARD_COMMAND 0xe0005001 +#define JAZZ_KEYBOARD_ADDRESS 0xe0005000 +#define JAZZ_KEYBOARD_DATA 0xe0005000 +#define JAZZ_KEYBOARD_COMMAND 0xe0005001 #ifndef __ASSEMBLY__ @@ -119,28 +119,28 @@ typedef struct { /* * For now. Needs to be changed for RC3xxx support. See below. */ -#define keyboard_hardware jazz_keyboard_hardware +#define keyboard_hardware jazz_keyboard_hardware #endif /* !__ASSEMBLY__ */ /* * i8042 keyboard controller for most other Mips machines. */ -#define MIPS_KEYBOARD_ADDRESS 0xb9005000 -#define MIPS_KEYBOARD_DATA 0xb9005003 -#define MIPS_KEYBOARD_COMMAND 0xb9005007 +#define MIPS_KEYBOARD_ADDRESS 0xb9005000 +#define MIPS_KEYBOARD_DATA 0xb9005003 +#define MIPS_KEYBOARD_COMMAND 0xb9005007 /* * Serial and parallel ports (WD 16C552) on the Mips JAZZ */ -#define JAZZ_SERIAL1_BASE (unsigned int)0xe0006000 -#define JAZZ_SERIAL2_BASE (unsigned int)0xe0007000 -#define JAZZ_PARALLEL_BASE (unsigned int)0xe0008000 +#define JAZZ_SERIAL1_BASE (unsigned int)0xe0006000 +#define JAZZ_SERIAL2_BASE (unsigned int)0xe0007000 +#define JAZZ_PARALLEL_BASE (unsigned int)0xe0008000 /* * Dummy Device Address. Used in jazzdma.c */ -#define JAZZ_DUMMY_DEVICE 0xe000d000 +#define JAZZ_DUMMY_DEVICE 0xe000d000 /* * JAZZ timer registers and interrupt no. @@ -148,8 +148,8 @@ typedef struct { * cpu level 6, but to keep compatibility with PC stuff * it is remapped to vector 0. See arch/mips/kernel/entry.S. */ -#define JAZZ_TIMER_INTERVAL 0xe0000228 -#define JAZZ_TIMER_REGISTER 0xe0000230 +#define JAZZ_TIMER_INTERVAL 0xe0000228 +#define JAZZ_TIMER_REGISTER 0xe0000230 /* * DRAM configuration register @@ -176,13 +176,13 @@ typedef struct { #endif #endif /* !__ASSEMBLY__ */ -#define PICA_DRAM_CONFIG 0xe00fffe0 +#define PICA_DRAM_CONFIG 0xe00fffe0 /* * JAZZ interrupt control registers */ -#define JAZZ_IO_IRQ_SOURCE 0xe0010000 -#define JAZZ_IO_IRQ_ENABLE 0xe0010002 +#define JAZZ_IO_IRQ_SOURCE 0xe0010000 +#define JAZZ_IO_IRQ_ENABLE 0xe0010002 /* * JAZZ Interrupt Level definitions @@ -190,20 +190,20 @@ typedef struct { * This is somewhat broken. For reasons which nobody can remember anymore * we remap the Jazz interrupts to the usual ISA style interrupt numbers. */ -#define JAZZ_IRQ_START 24 -#define JAZZ_IRQ_END (24 + 9) -#define JAZZ_PARALLEL_IRQ (JAZZ_IRQ_START + 0) -#define JAZZ_FLOPPY_IRQ (JAZZ_IRQ_START + 1) -#define JAZZ_SOUND_IRQ (JAZZ_IRQ_START + 2) -#define JAZZ_VIDEO_IRQ (JAZZ_IRQ_START + 3) -#define JAZZ_ETHERNET_IRQ (JAZZ_IRQ_START + 4) -#define JAZZ_SCSI_IRQ (JAZZ_IRQ_START + 5) -#define JAZZ_KEYBOARD_IRQ (JAZZ_IRQ_START + 6) -#define JAZZ_MOUSE_IRQ (JAZZ_IRQ_START + 7) -#define JAZZ_SERIAL1_IRQ (JAZZ_IRQ_START + 8) -#define JAZZ_SERIAL2_IRQ (JAZZ_IRQ_START + 9) - -#define JAZZ_TIMER_IRQ (MIPS_CPU_IRQ_BASE+6) +#define JAZZ_IRQ_START 24 +#define JAZZ_IRQ_END (24 + 9) +#define JAZZ_PARALLEL_IRQ (JAZZ_IRQ_START + 0) +#define JAZZ_FLOPPY_IRQ (JAZZ_IRQ_START + 1) +#define JAZZ_SOUND_IRQ (JAZZ_IRQ_START + 2) +#define JAZZ_VIDEO_IRQ (JAZZ_IRQ_START + 3) +#define JAZZ_ETHERNET_IRQ (JAZZ_IRQ_START + 4) +#define JAZZ_SCSI_IRQ (JAZZ_IRQ_START + 5) +#define JAZZ_KEYBOARD_IRQ (JAZZ_IRQ_START + 6) +#define JAZZ_MOUSE_IRQ (JAZZ_IRQ_START + 7) +#define JAZZ_SERIAL1_IRQ (JAZZ_IRQ_START + 8) +#define JAZZ_SERIAL2_IRQ (JAZZ_IRQ_START + 9) + +#define JAZZ_TIMER_IRQ (MIPS_CPU_IRQ_BASE+6) /* @@ -211,46 +211,46 @@ typedef struct { * Note: Channels 4...7 are not used with respect to the Acer PICA-61 * chipset which does not provide these DMA channels. */ -#define JAZZ_SCSI_DMA 0 /* SCSI */ -#define JAZZ_FLOPPY_DMA 1 /* FLOPPY */ -#define JAZZ_AUDIOL_DMA 2 /* AUDIO L */ -#define JAZZ_AUDIOR_DMA 3 /* AUDIO R */ +#define JAZZ_SCSI_DMA 0 /* SCSI */ +#define JAZZ_FLOPPY_DMA 1 /* FLOPPY */ +#define JAZZ_AUDIOL_DMA 2 /* AUDIO L */ +#define JAZZ_AUDIOR_DMA 3 /* AUDIO R */ /* * JAZZ R4030 MCT_ADR chip (DMA controller) * Note: Virtual Addresses ! */ #define JAZZ_R4030_CONFIG 0xE0000000 /* R4030 config register */ -#define JAZZ_R4030_REVISION 0xE0000008 /* same as PICA_ASIC_REVISION */ +#define JAZZ_R4030_REVISION 0xE0000008 /* same as PICA_ASIC_REVISION */ #define JAZZ_R4030_INV_ADDR 0xE0000010 /* Invalid Address register */ -#define JAZZ_R4030_TRSTBL_BASE 0xE0000018 /* Translation Table Base */ -#define JAZZ_R4030_TRSTBL_LIM 0xE0000020 /* Translation Table Limit */ -#define JAZZ_R4030_TRSTBL_INV 0xE0000028 /* Translation Table Invalidate */ +#define JAZZ_R4030_TRSTBL_BASE 0xE0000018 /* Translation Table Base */ +#define JAZZ_R4030_TRSTBL_LIM 0xE0000020 /* Translation Table Limit */ +#define JAZZ_R4030_TRSTBL_INV 0xE0000028 /* Translation Table Invalidate */ -#define JAZZ_R4030_CACHE_MTNC 0xE0000030 /* Cache Maintenance */ -#define JAZZ_R4030_R_FAIL_ADDR 0xE0000038 /* Remote Failed Address */ -#define JAZZ_R4030_M_FAIL_ADDR 0xE0000040 /* Memory Failed Address */ +#define JAZZ_R4030_CACHE_MTNC 0xE0000030 /* Cache Maintenance */ +#define JAZZ_R4030_R_FAIL_ADDR 0xE0000038 /* Remote Failed Address */ +#define JAZZ_R4030_M_FAIL_ADDR 0xE0000040 /* Memory Failed Address */ -#define JAZZ_R4030_CACHE_PTAG 0xE0000048 /* I/O Cache Physical Tag */ -#define JAZZ_R4030_CACHE_LTAG 0xE0000050 /* I/O Cache Logical Tag */ -#define JAZZ_R4030_CACHE_BMASK 0xE0000058 /* I/O Cache Byte Mask */ -#define JAZZ_R4030_CACHE_BWIN 0xE0000060 /* I/O Cache Buffer Window */ +#define JAZZ_R4030_CACHE_PTAG 0xE0000048 /* I/O Cache Physical Tag */ +#define JAZZ_R4030_CACHE_LTAG 0xE0000050 /* I/O Cache Logical Tag */ +#define JAZZ_R4030_CACHE_BMASK 0xE0000058 /* I/O Cache Byte Mask */ +#define JAZZ_R4030_CACHE_BWIN 0xE0000060 /* I/O Cache Buffer Window */ /* * Remote Speed Registers. * - * 0: free, 1: Ethernet, 2: SCSI, 3: Floppy, - * 4: RTC, 5: Kb./Mouse 6: serial 1, 7: serial 2, - * 8: parallel, 9: NVRAM, 10: CPU, 11: PROM, + * 0: free, 1: Ethernet, 2: SCSI, 3: Floppy, + * 4: RTC, 5: Kb./Mouse 6: serial 1, 7: serial 2, + * 8: parallel, 9: NVRAM, 10: CPU, 11: PROM, * 12: reserved, 13: free, 14: 7seg LED, 15: ??? */ #define JAZZ_R4030_REM_SPEED 0xE0000070 /* 16 Remote Speed Registers */ /* 0xE0000070,78,80... 0xE00000E8 */ -#define JAZZ_R4030_IRQ_ENABLE 0xE00000E8 /* Internal Interrupt Enable */ -#define JAZZ_R4030_INVAL_ADDR 0xE0000010 /* Invalid address Register */ -#define JAZZ_R4030_IRQ_SOURCE 0xE0000200 /* Interrupt Source Register */ -#define JAZZ_R4030_I386_ERROR 0xE0000208 /* i386/EISA Bus Error */ +#define JAZZ_R4030_IRQ_ENABLE 0xE00000E8 /* Internal Interrupt Enable */ +#define JAZZ_R4030_INVAL_ADDR 0xE0000010 /* Invalid address Register */ +#define JAZZ_R4030_IRQ_SOURCE 0xE0000200 /* Interrupt Source Register */ +#define JAZZ_R4030_I386_ERROR 0xE0000208 /* i386/EISA Bus Error */ /* * Virtual (E)ISA controller address diff --git a/arch/mips/include/asm/jazzdma.h b/arch/mips/include/asm/jazzdma.h index 8bb37bba68f..2cefc3c4724 100644 --- a/arch/mips/include/asm/jazzdma.h +++ b/arch/mips/include/asm/jazzdma.h @@ -10,7 +10,7 @@ extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size); extern int vdma_free(unsigned long laddr); extern int vdma_remap(unsigned long laddr, unsigned long paddr, - unsigned long size); + unsigned long size); extern unsigned long vdma_phys2log(unsigned long paddr); extern unsigned long vdma_log2phys(unsigned long laddr); extern void vdma_stats(void); /* for debugging only */ @@ -35,14 +35,14 @@ extern int vdma_get_enable(int channel); * Macros to get page no. and offset of a given address * Note that VDMA_PAGE() works for physical addresses only */ -#define VDMA_PAGE(a) ((unsigned int)(a) >> 12) -#define VDMA_OFFSET(a) ((unsigned int)(a) & (VDMA_PAGESIZE-1)) +#define VDMA_PAGE(a) ((unsigned int)(a) >> 12) +#define VDMA_OFFSET(a) ((unsigned int)(a) & (VDMA_PAGESIZE-1)) /* * error code returned by vdma_alloc() * (See also arch/mips/kernel/jazzdma.c) */ -#define VDMA_ERROR 0xffffffff +#define VDMA_ERROR 0xffffffff /* * VDMA pagetable entry description @@ -59,37 +59,37 @@ typedef volatile struct VDMA_PGTBL_ENTRY { */ #define JAZZ_R4030_CHNL_MODE 0xE0000100 /* 8 DMA Channel Mode Registers, */ /* 0xE0000100,120,140... */ -#define JAZZ_R4030_CHNL_ENABLE 0xE0000108 /* 8 DMA Channel Enable Regs, */ +#define JAZZ_R4030_CHNL_ENABLE 0xE0000108 /* 8 DMA Channel Enable Regs, */ /* 0xE0000108,128,148... */ -#define JAZZ_R4030_CHNL_COUNT 0xE0000110 /* 8 DMA Channel Byte Cnt Regs, */ +#define JAZZ_R4030_CHNL_COUNT 0xE0000110 /* 8 DMA Channel Byte Cnt Regs, */ /* 0xE0000110,130,150... */ #define JAZZ_R4030_CHNL_ADDR 0xE0000118 /* 8 DMA Channel Address Regs, */ /* 0xE0000118,138,158... */ /* channel enable register bits */ -#define R4030_CHNL_ENABLE (1<<0) -#define R4030_CHNL_WRITE (1<<1) -#define R4030_TC_INTR (1<<8) -#define R4030_MEM_INTR (1<<9) -#define R4030_ADDR_INTR (1<<10) +#define R4030_CHNL_ENABLE (1<<0) +#define R4030_CHNL_WRITE (1<<1) +#define R4030_TC_INTR (1<<8) +#define R4030_MEM_INTR (1<<9) +#define R4030_ADDR_INTR (1<<10) /* * Channel mode register bits */ -#define R4030_MODE_ATIME_40 (0) /* device access time on remote bus */ -#define R4030_MODE_ATIME_80 (1) -#define R4030_MODE_ATIME_120 (2) -#define R4030_MODE_ATIME_160 (3) -#define R4030_MODE_ATIME_200 (4) -#define R4030_MODE_ATIME_240 (5) -#define R4030_MODE_ATIME_280 (6) -#define R4030_MODE_ATIME_320 (7) -#define R4030_MODE_WIDTH_8 (1<<3) /* device data bus width */ -#define R4030_MODE_WIDTH_16 (2<<3) -#define R4030_MODE_WIDTH_32 (3<<3) -#define R4030_MODE_INTR_EN (1<<5) -#define R4030_MODE_BURST (1<<6) /* Rev. 2 only */ -#define R4030_MODE_FAST_ACK (1<<7) /* Rev. 2 only */ +#define R4030_MODE_ATIME_40 (0) /* device access time on remote bus */ +#define R4030_MODE_ATIME_80 (1) +#define R4030_MODE_ATIME_120 (2) +#define R4030_MODE_ATIME_160 (3) +#define R4030_MODE_ATIME_200 (4) +#define R4030_MODE_ATIME_240 (5) +#define R4030_MODE_ATIME_280 (6) +#define R4030_MODE_ATIME_320 (7) +#define R4030_MODE_WIDTH_8 (1<<3) /* device data bus width */ +#define R4030_MODE_WIDTH_16 (2<<3) +#define R4030_MODE_WIDTH_32 (3<<3) +#define R4030_MODE_INTR_EN (1<<5) +#define R4030_MODE_BURST (1<<6) /* Rev. 2 only */ +#define R4030_MODE_FAST_ACK (1<<7) /* Rev. 2 only */ #endif /* _ASM_JAZZDMA_H */ diff --git a/arch/mips/include/asm/jump_label.h b/arch/mips/include/asm/jump_label.h index 4d6d77ed9b9..e194f957ca8 100644 --- a/arch/mips/include/asm/jump_label.h +++ b/arch/mips/include/asm/jump_label.h @@ -22,7 +22,7 @@ static __always_inline bool arch_static_branch(struct static_key *key) { - asm goto("1:\tnop\n\t" + asm_volatile_goto("1:\tnop\n\t" "nop\n\t" ".pushsection __jump_table, \"aw\"\n\t" WORD_INSN " 1b, %l[l_yes], %0\n\t" diff --git a/arch/mips/include/asm/kmap_types.h b/arch/mips/include/asm/kmap_types.h index 58e91ed0388..c1909dcada3 100644 --- a/arch/mips/include/asm/kmap_types.h +++ b/arch/mips/include/asm/kmap_types.h @@ -2,7 +2,7 @@ #define _ASM_KMAP_TYPES_H #ifdef CONFIG_DEBUG_HIGHMEM -#define __WITH_KM_FENCE +#define __WITH_KM_FENCE #endif #include <asm-generic/kmap_types.h> diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h index 1fbbca01e68..daba1f9a4f7 100644 --- a/arch/mips/include/asm/kprobes.h +++ b/arch/mips/include/asm/kprobes.h @@ -29,7 +29,7 @@ #include <asm/kdebug.h> #include <asm/inst.h> -#define __ARCH_WANT_KPROBES_INSN_SLOT +#define __ARCH_WANT_KPROBES_INSN_SLOT struct kprobe; struct pt_regs; diff --git a/arch/mips/include/asm/kspd.h b/arch/mips/include/asm/kspd.h deleted file mode 100644 index ec6832950ac..00000000000 --- a/arch/mips/include/asm/kspd.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - */ - -#ifndef _ASM_KSPD_H -#define _ASM_KSPD_H - -struct kspd_notifications { - void (*kspd_sp_exit)(int sp_id); - - struct list_head list; -}; - -static inline void kspd_notify(struct kspd_notifications *notify) -{ -} - -#endif diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h new file mode 100644 index 00000000000..b0aa9556575 --- /dev/null +++ b/arch/mips/include/asm/kvm_host.h @@ -0,0 +1,767 @@ +/* +* This file is subject to the terms and conditions of the GNU General Public +* License. See the file "COPYING" in the main directory of this archive +* for more details. +* +* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. +* Authors: Sanjay Lal <sanjayl@kymasys.com> +*/ + +#ifndef __MIPS_KVM_HOST_H__ +#define __MIPS_KVM_HOST_H__ + +#include <linux/mutex.h> +#include <linux/hrtimer.h> +#include <linux/interrupt.h> +#include <linux/types.h> +#include <linux/kvm.h> +#include <linux/kvm_types.h> +#include <linux/threads.h> +#include <linux/spinlock.h> + +/* MIPS KVM register ids */ +#define MIPS_CP0_32(_R, _S) \ + (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S))) + +#define MIPS_CP0_64(_R, _S) \ + (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S))) + +#define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) +#define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0) +#define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0) +#define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) +#define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) +#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) +#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) +#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) +#define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) +#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) +#define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) +#define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) +#define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) +#define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) +#define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) +#define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) +#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) +#define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) +#define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) +#define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) +#define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) +#define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7) +#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) +#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) + + +#define KVM_MAX_VCPUS 1 +#define KVM_USER_MEM_SLOTS 8 +/* memory slots that does not exposed to userspace */ +#define KVM_PRIVATE_MEM_SLOTS 0 + +#define KVM_COALESCED_MMIO_PAGE_OFFSET 1 + + + +/* Special address that contains the comm page, used for reducing # of traps */ +#define KVM_GUEST_COMMPAGE_ADDR 0x0 + +#define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \ + ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0)) + +#define KVM_GUEST_KUSEG 0x00000000UL +#define KVM_GUEST_KSEG0 0x40000000UL +#define KVM_GUEST_KSEG23 0x60000000UL +#define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000) +#define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) + +#define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) +#define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1) +#define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23) + +/* + * Map an address to a certain kernel segment + */ +#define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) +#define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1) +#define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23) + +#define KVM_INVALID_PAGE 0xdeadbeef +#define KVM_INVALID_INST 0xdeadbeef +#define KVM_INVALID_ADDR 0xdeadbeef + +#define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL + +#define GUEST_TICKS_PER_JIFFY (40000000/HZ) +#define MS_TO_NS(x) (x * 1E6L) + +#define CAUSEB_DC 27 +#define CAUSEF_DC (_ULCAST_(1) << 27) + +struct kvm; +struct kvm_run; +struct kvm_vcpu; +struct kvm_interrupt; + +extern atomic_t kvm_mips_instance; +extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn); +extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn); +extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn); + +struct kvm_vm_stat { + u32 remote_tlb_flush; +}; + +struct kvm_vcpu_stat { + u32 wait_exits; + u32 cache_exits; + u32 signal_exits; + u32 int_exits; + u32 cop_unusable_exits; + u32 tlbmod_exits; + u32 tlbmiss_ld_exits; + u32 tlbmiss_st_exits; + u32 addrerr_st_exits; + u32 addrerr_ld_exits; + u32 syscall_exits; + u32 resvd_inst_exits; + u32 break_inst_exits; + u32 flush_dcache_exits; + u32 halt_wakeup; +}; + +enum kvm_mips_exit_types { + WAIT_EXITS, + CACHE_EXITS, + SIGNAL_EXITS, + INT_EXITS, + COP_UNUSABLE_EXITS, + TLBMOD_EXITS, + TLBMISS_LD_EXITS, + TLBMISS_ST_EXITS, + ADDRERR_ST_EXITS, + ADDRERR_LD_EXITS, + SYSCALL_EXITS, + RESVD_INST_EXITS, + BREAK_INST_EXITS, + FLUSH_DCACHE_EXITS, + MAX_KVM_MIPS_EXIT_TYPES +}; + +struct kvm_arch_memory_slot { +}; + +struct kvm_arch { + /* Guest GVA->HPA page table */ + unsigned long *guest_pmap; + unsigned long guest_pmap_npages; + + /* Wired host TLB used for the commpage */ + int commpage_tlb; +}; + +#define N_MIPS_COPROC_REGS 32 +#define N_MIPS_COPROC_SEL 8 + +struct mips_coproc { + unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; +#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS + unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; +#endif +}; + +/* + * Coprocessor 0 register names + */ +#define MIPS_CP0_TLB_INDEX 0 +#define MIPS_CP0_TLB_RANDOM 1 +#define MIPS_CP0_TLB_LOW 2 +#define MIPS_CP0_TLB_LO0 2 +#define MIPS_CP0_TLB_LO1 3 +#define MIPS_CP0_TLB_CONTEXT 4 +#define MIPS_CP0_TLB_PG_MASK 5 +#define MIPS_CP0_TLB_WIRED 6 +#define MIPS_CP0_HWRENA 7 +#define MIPS_CP0_BAD_VADDR 8 +#define MIPS_CP0_COUNT 9 +#define MIPS_CP0_TLB_HI 10 +#define MIPS_CP0_COMPARE 11 +#define MIPS_CP0_STATUS 12 +#define MIPS_CP0_CAUSE 13 +#define MIPS_CP0_EXC_PC 14 +#define MIPS_CP0_PRID 15 +#define MIPS_CP0_CONFIG 16 +#define MIPS_CP0_LLADDR 17 +#define MIPS_CP0_WATCH_LO 18 +#define MIPS_CP0_WATCH_HI 19 +#define MIPS_CP0_TLB_XCONTEXT 20 +#define MIPS_CP0_ECC 26 +#define MIPS_CP0_CACHE_ERR 27 +#define MIPS_CP0_TAG_LO 28 +#define MIPS_CP0_TAG_HI 29 +#define MIPS_CP0_ERROR_PC 30 +#define MIPS_CP0_DEBUG 23 +#define MIPS_CP0_DEPC 24 +#define MIPS_CP0_PERFCNT 25 +#define MIPS_CP0_ERRCTL 26 +#define MIPS_CP0_DATA_LO 28 +#define MIPS_CP0_DATA_HI 29 +#define MIPS_CP0_DESAVE 31 + +#define MIPS_CP0_CONFIG_SEL 0 +#define MIPS_CP0_CONFIG1_SEL 1 +#define MIPS_CP0_CONFIG2_SEL 2 +#define MIPS_CP0_CONFIG3_SEL 3 + +/* Config0 register bits */ +#define CP0C0_M 31 +#define CP0C0_K23 28 +#define CP0C0_KU 25 +#define CP0C0_MDU 20 +#define CP0C0_MM 17 +#define CP0C0_BM 16 +#define CP0C0_BE 15 +#define CP0C0_AT 13 +#define CP0C0_AR 10 +#define CP0C0_MT 7 +#define CP0C0_VI 3 +#define CP0C0_K0 0 + +/* Config1 register bits */ +#define CP0C1_M 31 +#define CP0C1_MMU 25 +#define CP0C1_IS 22 +#define CP0C1_IL 19 +#define CP0C1_IA 16 +#define CP0C1_DS 13 +#define CP0C1_DL 10 +#define CP0C1_DA 7 +#define CP0C1_C2 6 +#define CP0C1_MD 5 +#define CP0C1_PC 4 +#define CP0C1_WR 3 +#define CP0C1_CA 2 +#define CP0C1_EP 1 +#define CP0C1_FP 0 + +/* Config2 Register bits */ +#define CP0C2_M 31 +#define CP0C2_TU 28 +#define CP0C2_TS 24 +#define CP0C2_TL 20 +#define CP0C2_TA 16 +#define CP0C2_SU 12 +#define CP0C2_SS 8 +#define CP0C2_SL 4 +#define CP0C2_SA 0 + +/* Config3 Register bits */ +#define CP0C3_M 31 +#define CP0C3_ISA_ON_EXC 16 +#define CP0C3_ULRI 13 +#define CP0C3_DSPP 10 +#define CP0C3_LPA 7 +#define CP0C3_VEIC 6 +#define CP0C3_VInt 5 +#define CP0C3_SP 4 +#define CP0C3_MT 2 +#define CP0C3_SM 1 +#define CP0C3_TL 0 + +/* Have config1, Cacheable, noncoherent, write-back, write allocate*/ +#define MIPS_CONFIG0 \ + ((1 << CP0C0_M) | (0x3 << CP0C0_K0)) + +/* Have config2, no coprocessor2 attached, no MDMX support attached, + no performance counters, watch registers present, + no code compression, EJTAG present, no FPU, no watch registers */ +#define MIPS_CONFIG1 \ +((1 << CP0C1_M) | \ + (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ + (0 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ + (0 << CP0C1_FP)) + +/* Have config3, no tertiary/secondary caches implemented */ +#define MIPS_CONFIG2 \ +((1 << CP0C2_M)) + +/* No config4, no DSP ASE, no large physaddr (PABITS), + no external interrupt controller, no vectored interrupts, + no 1kb pages, no SmartMIPS ASE, no trace logic */ +#define MIPS_CONFIG3 \ +((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ + (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ + (0 << CP0C3_SM) | (0 << CP0C3_TL)) + +/* MMU types, the first four entries have the same layout as the + CP0C0_MT field. */ +enum mips_mmu_types { + MMU_TYPE_NONE, + MMU_TYPE_R4000, + MMU_TYPE_RESERVED, + MMU_TYPE_FMT, + MMU_TYPE_R3000, + MMU_TYPE_R6000, + MMU_TYPE_R8000 +}; + +/* + * Trap codes + */ +#define T_INT 0 /* Interrupt pending */ +#define T_TLB_MOD 1 /* TLB modified fault */ +#define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */ +#define T_TLB_ST_MISS 3 /* TLB miss on a store */ +#define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */ +#define T_ADDR_ERR_ST 5 /* Address error on a store */ +#define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */ +#define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */ +#define T_SYSCALL 8 /* System call */ +#define T_BREAK 9 /* Breakpoint */ +#define T_RES_INST 10 /* Reserved instruction exception */ +#define T_COP_UNUSABLE 11 /* Coprocessor unusable */ +#define T_OVFLOW 12 /* Arithmetic overflow */ + +/* + * Trap definitions added for r4000 port. + */ +#define T_TRAP 13 /* Trap instruction */ +#define T_VCEI 14 /* Virtual coherency exception */ +#define T_FPE 15 /* Floating point exception */ +#define T_WATCH 23 /* Watch address reference */ +#define T_VCED 31 /* Virtual coherency data */ + +/* Resume Flags */ +#define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */ +#define RESUME_FLAG_HOST (1<<1) /* Resume host? */ + +#define RESUME_GUEST 0 +#define RESUME_GUEST_DR RESUME_FLAG_DR +#define RESUME_HOST RESUME_FLAG_HOST + +enum emulation_result { + EMULATE_DONE, /* no further processing */ + EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */ + EMULATE_FAIL, /* can't emulate this instruction */ + EMULATE_WAIT, /* WAIT instruction */ + EMULATE_PRIV_FAIL, +}; + +#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */ +#define MIPS3_PG_V 0x00000002 /* Valid */ +#define MIPS3_PG_NV 0x00000000 +#define MIPS3_PG_D 0x00000004 /* Dirty */ + +#define mips3_paddr_to_tlbpfn(x) \ + (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME) +#define mips3_tlbpfn_to_paddr(x) \ + ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT) + +#define MIPS3_PG_SHIFT 6 +#define MIPS3_PG_FRAME 0x3fffffc0 + +#define VPN2_MASK 0xffffe000 +#define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \ + ((x).tlb_lo1 & MIPS3_PG_G)) +#define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK) +#define TLB_ASID(x) ((x).tlb_hi & ASID_MASK) +#define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \ + ? ((x).tlb_lo1 & MIPS3_PG_V) \ + : ((x).tlb_lo0 & MIPS3_PG_V)) + +struct kvm_mips_tlb { + long tlb_mask; + long tlb_hi; + long tlb_lo0; + long tlb_lo1; +}; + +#define KVM_MIPS_GUEST_TLB_SIZE 64 +struct kvm_vcpu_arch { + void *host_ebase, *guest_ebase; + unsigned long host_stack; + unsigned long host_gp; + + /* Host CP0 registers used when handling exits from guest */ + unsigned long host_cp0_badvaddr; + unsigned long host_cp0_cause; + unsigned long host_cp0_epc; + unsigned long host_cp0_entryhi; + uint32_t guest_inst; + + /* GPRS */ + unsigned long gprs[32]; + unsigned long hi; + unsigned long lo; + unsigned long pc; + + /* FPU State */ + struct mips_fpu_struct fpu; + + /* COP0 State */ + struct mips_coproc *cop0; + + /* Host KSEG0 address of the EI/DI offset */ + void *kseg0_commpage; + + u32 io_gpr; /* GPR used as IO source/target */ + + struct hrtimer comparecount_timer; + /* Count timer control KVM register */ + uint32_t count_ctl; + /* Count bias from the raw time */ + uint32_t count_bias; + /* Frequency of timer in Hz */ + uint32_t count_hz; + /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */ + s64 count_dyn_bias; + /* Resume time */ + ktime_t count_resume; + /* Period of timer tick in ns */ + u64 count_period; + + /* Bitmask of exceptions that are pending */ + unsigned long pending_exceptions; + + /* Bitmask of pending exceptions to be cleared */ + unsigned long pending_exceptions_clr; + + unsigned long pending_load_cause; + + /* Save/Restore the entryhi register when are are preempted/scheduled back in */ + unsigned long preempt_entryhi; + + /* S/W Based TLB for guest */ + struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE]; + + /* Cached guest kernel/user ASIDs */ + uint32_t guest_user_asid[NR_CPUS]; + uint32_t guest_kernel_asid[NR_CPUS]; + struct mm_struct guest_kernel_mm, guest_user_mm; + + int last_sched_cpu; + + /* WAIT executed */ + int wait; +}; + + +#define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0]) +#define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val) +#define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0]) +#define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0]) +#define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0]) +#define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val)) +#define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2]) +#define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val)) +#define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0]) +#define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val)) +#define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0]) +#define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val)) +#define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0]) +#define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val)) +#define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0]) +#define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val)) +#define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0]) +#define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val)) +#define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0]) +#define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val)) +#define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0]) +#define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val)) +#define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0]) +#define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val)) +#define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1]) +#define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val)) +#define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0]) +#define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val)) +#define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0]) +#define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val)) +#define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0]) +#define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val)) +#define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1]) +#define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val)) +#define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0]) +#define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1]) +#define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2]) +#define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3]) +#define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7]) +#define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val)) +#define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val)) +#define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val)) +#define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val)) +#define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val)) +#define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0]) +#define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val)) + +/* + * Some of the guest registers may be modified asynchronously (e.g. from a + * hrtimer callback in hard irq context) and therefore need stronger atomicity + * guarantees than other registers. + */ + +static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg, + unsigned long val) +{ + unsigned long temp; + do { + __asm__ __volatile__( + " .set mips3 \n" + " " __LL "%0, %1 \n" + " or %0, %2 \n" + " " __SC "%0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*reg) + : "r" (val)); + } while (unlikely(!temp)); +} + +static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg, + unsigned long val) +{ + unsigned long temp; + do { + __asm__ __volatile__( + " .set mips3 \n" + " " __LL "%0, %1 \n" + " and %0, %2 \n" + " " __SC "%0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*reg) + : "r" (~val)); + } while (unlikely(!temp)); +} + +static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg, + unsigned long change, + unsigned long val) +{ + unsigned long temp; + do { + __asm__ __volatile__( + " .set mips3 \n" + " " __LL "%0, %1 \n" + " and %0, %2 \n" + " or %0, %3 \n" + " " __SC "%0, %1 \n" + " .set mips0 \n" + : "=&r" (temp), "+m" (*reg) + : "r" (~change), "r" (val & change)); + } while (unlikely(!temp)); +} + +#define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val)) +#define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val)) + +/* Cause can be modified asynchronously from hardirq hrtimer callback */ +#define kvm_set_c0_guest_cause(cop0, val) \ + _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val) +#define kvm_clear_c0_guest_cause(cop0, val) \ + _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val) +#define kvm_change_c0_guest_cause(cop0, change, val) \ + _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \ + change, val) + +#define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val)) +#define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val)) +#define kvm_change_c0_guest_ebase(cop0, change, val) \ +{ \ + kvm_clear_c0_guest_ebase(cop0, change); \ + kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \ +} + + +struct kvm_mips_callbacks { + int (*handle_cop_unusable)(struct kvm_vcpu *vcpu); + int (*handle_tlb_mod)(struct kvm_vcpu *vcpu); + int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu); + int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu); + int (*handle_addr_err_st)(struct kvm_vcpu *vcpu); + int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu); + int (*handle_syscall)(struct kvm_vcpu *vcpu); + int (*handle_res_inst)(struct kvm_vcpu *vcpu); + int (*handle_break)(struct kvm_vcpu *vcpu); + int (*vm_init)(struct kvm *kvm); + int (*vcpu_init)(struct kvm_vcpu *vcpu); + int (*vcpu_setup)(struct kvm_vcpu *vcpu); + gpa_t (*gva_to_gpa)(gva_t gva); + void (*queue_timer_int)(struct kvm_vcpu *vcpu); + void (*dequeue_timer_int)(struct kvm_vcpu *vcpu); + void (*queue_io_int)(struct kvm_vcpu *vcpu, + struct kvm_mips_interrupt *irq); + void (*dequeue_io_int)(struct kvm_vcpu *vcpu, + struct kvm_mips_interrupt *irq); + int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority, + uint32_t cause); + int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority, + uint32_t cause); + int (*get_one_reg)(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, s64 *v); + int (*set_one_reg)(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, s64 v); +}; +extern struct kvm_mips_callbacks *kvm_mips_callbacks; +int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks); + +/* Debug: dump vcpu state */ +int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu); + +/* Trampoline ASM routine to start running in "Guest" context */ +extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu); + +/* TLB handling */ +uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu); + +uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu); + +uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu); + +extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr, + struct kvm_vcpu *vcpu); + +extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr, + struct kvm_vcpu *vcpu); + +extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu, + struct kvm_mips_tlb *tlb, + unsigned long *hpa0, + unsigned long *hpa1); + +extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause, + uint32_t *opc, + struct kvm_run *run, + struct kvm_vcpu *vcpu); + +extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause, + uint32_t *opc, + struct kvm_run *run, + struct kvm_vcpu *vcpu); + +extern void kvm_mips_dump_host_tlbs(void); +extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu); +extern void kvm_mips_flush_host_tlb(int skip_kseg0); +extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi); +extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index); + +extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, + unsigned long entryhi); +extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr); +extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu, + unsigned long gva); +extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu, + struct kvm_vcpu *vcpu); +extern void kvm_local_flush_tlb_all(void); +extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu); +extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu); +extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu); + +/* Emulation */ +uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu); +enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause); + +extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause, + uint32_t *opc, + struct kvm_run *run, + struct kvm_vcpu *vcpu); + +extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause, + uint32_t *opc, + struct kvm_run *run, + struct kvm_vcpu *vcpu); + +extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause, + uint32_t *opc, + struct kvm_run *run, + struct kvm_vcpu *vcpu); + +extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause, + uint32_t *opc, + struct kvm_run *run, + struct kvm_vcpu *vcpu); + +extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause, + uint32_t *opc, + struct kvm_run *run, + struct kvm_vcpu *vcpu); + +extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause, + uint32_t *opc, + struct kvm_run *run, + struct kvm_vcpu *vcpu); + +extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause, + uint32_t *opc, + struct kvm_run *run, + struct kvm_vcpu *vcpu); + +extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause, + uint32_t *opc, + struct kvm_run *run, + struct kvm_vcpu *vcpu); + +extern enum emulation_result kvm_mips_handle_ri(unsigned long cause, + uint32_t *opc, + struct kvm_run *run, + struct kvm_vcpu *vcpu); + +extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause, + uint32_t *opc, + struct kvm_run *run, + struct kvm_vcpu *vcpu); + +extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause, + uint32_t *opc, + struct kvm_run *run, + struct kvm_vcpu *vcpu); + +extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu, + struct kvm_run *run); + +uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu); +void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count); +void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare); +void kvm_mips_init_count(struct kvm_vcpu *vcpu); +int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl); +int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume); +int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz); +void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu); +void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu); +enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu); + +enum emulation_result kvm_mips_check_privilege(unsigned long cause, + uint32_t *opc, + struct kvm_run *run, + struct kvm_vcpu *vcpu); + +enum emulation_result kvm_mips_emulate_cache(uint32_t inst, + uint32_t *opc, + uint32_t cause, + struct kvm_run *run, + struct kvm_vcpu *vcpu); +enum emulation_result kvm_mips_emulate_CP0(uint32_t inst, + uint32_t *opc, + uint32_t cause, + struct kvm_run *run, + struct kvm_vcpu *vcpu); +enum emulation_result kvm_mips_emulate_store(uint32_t inst, + uint32_t cause, + struct kvm_run *run, + struct kvm_vcpu *vcpu); +enum emulation_result kvm_mips_emulate_load(uint32_t inst, + uint32_t cause, + struct kvm_run *run, + struct kvm_vcpu *vcpu); + +/* Dynamic binary translation */ +extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc, + struct kvm_vcpu *vcpu); +extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc, + struct kvm_vcpu *vcpu); +extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc, + struct kvm_vcpu *vcpu); +extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc, + struct kvm_vcpu *vcpu); + +/* Misc */ +extern int kvm_mips_dump_stats(struct kvm_vcpu *vcpu); +extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm); + + +#endif /* __MIPS_KVM_HOST_H__ */ diff --git a/arch/mips/include/asm/kvm_para.h b/arch/mips/include/asm/kvm_para.h new file mode 100644 index 00000000000..5a9aa918abe --- /dev/null +++ b/arch/mips/include/asm/kvm_para.h @@ -0,0 +1,109 @@ +#ifndef _ASM_MIPS_KVM_PARA_H +#define _ASM_MIPS_KVM_PARA_H + +#include <uapi/asm/kvm_para.h> + +#define KVM_HYPERCALL ".word 0x42000028" + +/* + * Hypercalls for KVM. + * + * Hypercall number is passed in v0. + * Return value will be placed in v0. + * Up to 3 arguments are passed in a0, a1, and a2. + */ +static inline unsigned long kvm_hypercall0(unsigned long num) +{ + register unsigned long n asm("v0"); + register unsigned long r asm("v0"); + + n = num; + __asm__ __volatile__( + KVM_HYPERCALL + : "=r" (r) : "r" (n) : "memory" + ); + + return r; +} + +static inline unsigned long kvm_hypercall1(unsigned long num, + unsigned long arg0) +{ + register unsigned long n asm("v0"); + register unsigned long r asm("v0"); + register unsigned long a0 asm("a0"); + + n = num; + a0 = arg0; + __asm__ __volatile__( + KVM_HYPERCALL + : "=r" (r) : "r" (n), "r" (a0) : "memory" + ); + + return r; +} + +static inline unsigned long kvm_hypercall2(unsigned long num, + unsigned long arg0, unsigned long arg1) +{ + register unsigned long n asm("v0"); + register unsigned long r asm("v0"); + register unsigned long a0 asm("a0"); + register unsigned long a1 asm("a1"); + + n = num; + a0 = arg0; + a1 = arg1; + __asm__ __volatile__( + KVM_HYPERCALL + : "=r" (r) : "r" (n), "r" (a0), "r" (a1) : "memory" + ); + + return r; +} + +static inline unsigned long kvm_hypercall3(unsigned long num, + unsigned long arg0, unsigned long arg1, unsigned long arg2) +{ + register unsigned long n asm("v0"); + register unsigned long r asm("v0"); + register unsigned long a0 asm("a0"); + register unsigned long a1 asm("a1"); + register unsigned long a2 asm("a2"); + + n = num; + a0 = arg0; + a1 = arg1; + a2 = arg2; + __asm__ __volatile__( + KVM_HYPERCALL + : "=r" (r) : "r" (n), "r" (a0), "r" (a1), "r" (a2) : "memory" + ); + + return r; +} + +static inline bool kvm_check_and_clear_guest_paused(void) +{ + return false; +} + +static inline unsigned int kvm_arch_para_features(void) +{ + return 0; +} + +#ifdef CONFIG_MIPS_PARAVIRT +static inline bool kvm_para_available(void) +{ + return true; +} +#else +static inline bool kvm_para_available(void) +{ + return false; +} +#endif + + +#endif /* _ASM_MIPS_KVM_PARA_H */ diff --git a/arch/mips/include/asm/lasat/eeprom.h b/arch/mips/include/asm/lasat/eeprom.h index 3dac203697f..d918b822e37 100644 --- a/arch/mips/include/asm/lasat/eeprom.h +++ b/arch/mips/include/asm/lasat/eeprom.h @@ -1,12 +1,12 @@ #include <asm/addrspace.h> /* lasat 100 */ -#define AT93C_REG_100 KSEG1ADDR(0x1c810000) -#define AT93C_RDATA_REG_100 AT93C_REG_100 -#define AT93C_RDATA_SHIFT_100 4 -#define AT93C_WDATA_SHIFT_100 4 -#define AT93C_CS_M_100 (1 << 5) -#define AT93C_CLK_M_100 (1 << 3) +#define AT93C_REG_100 KSEG1ADDR(0x1c810000) +#define AT93C_RDATA_REG_100 AT93C_REG_100 +#define AT93C_RDATA_SHIFT_100 4 +#define AT93C_WDATA_SHIFT_100 4 +#define AT93C_CS_M_100 (1 << 5) +#define AT93C_CLK_M_100 (1 << 3) /* lasat 200 */ #define AT93C_REG_200 KSEG1ADDR(0x11000000) diff --git a/arch/mips/include/asm/lasat/lasat.h b/arch/mips/include/asm/lasat/lasat.h index e8ff70f80e1..9e32b4da99e 100644 --- a/arch/mips/include/asm/lasat/lasat.h +++ b/arch/mips/include/asm/lasat/lasat.h @@ -100,7 +100,7 @@ struct lasat_eeprom_struct_pre7 { /* Configuration descriptor encoding - see the doc for details */ -#define LASAT_W0_DSCTYPE(v) (((v)) & 0xf) +#define LASAT_W0_DSCTYPE(v) (((v)) & 0xf) #define LASAT_W0_BMID(v) (((v) >> 0x04) & 0xf) #define LASAT_W0_CPUTYPE(v) (((v) >> 0x08) & 0xf) #define LASAT_W0_BUSSPEED(v) (((v) >> 0x0c) & 0xf) @@ -109,7 +109,7 @@ struct lasat_eeprom_struct_pre7 { #define LASAT_W0_SDRAMBANKS(v) (((v) >> 0x18) & 0xf) #define LASAT_W0_L2CACHE(v) (((v) >> 0x1c) & 0xf) -#define LASAT_W1_EDHAC(v) (((v)) & 0xf) +#define LASAT_W1_EDHAC(v) (((v)) & 0xf) #define LASAT_W1_HIFN(v) (((v) >> 0x04) & 0x1) #define LASAT_W1_ISDN(v) (((v) >> 0x05) & 0x1) #define LASAT_W1_IDE(v) (((v) >> 0x06) & 0x1) @@ -239,7 +239,7 @@ static inline void lasat_ndelay(unsigned int ns) __delay(ns / lasat_ndelay_divider); } -#define IS_LASAT_200() (current_cpu_data.cputype == CPU_R5000) +#define IS_LASAT_200() (current_cpu_data.cputype == CPU_R5000) #endif /* !defined (_LANGUAGE_ASSEMBLY) */ @@ -247,11 +247,11 @@ static inline void lasat_ndelay(unsigned int ns) #define LASAT_SERVICEMODE_MAGIC_2 0xfedeabba /* Lasat 100 boards */ -#define LASAT_GT_BASE (KSEG1ADDR(0x14000000)) +#define LASAT_GT_BASE (KSEG1ADDR(0x14000000)) /* Lasat 200 boards */ -#define Vrc5074_PHYS_BASE 0x1fa00000 -#define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE)) -#define PCI_WINDOW1 0x1a000000 +#define Vrc5074_PHYS_BASE 0x1fa00000 +#define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE)) +#define PCI_WINDOW1 0x1a000000 #endif /* _LASAT_H */ diff --git a/arch/mips/include/asm/lasat/serial.h b/arch/mips/include/asm/lasat/serial.h index 1c37d70579b..a2f6c7a9cfe 100644 --- a/arch/mips/include/asm/lasat/serial.h +++ b/arch/mips/include/asm/lasat/serial.h @@ -1,7 +1,7 @@ #include <asm/lasat/lasat.h> /* Lasat 100 boards serial configuration */ -#define LASAT_BASE_BAUD_100 (7372800 / 16) +#define LASAT_BASE_BAUD_100 (7372800 / 16) #define LASAT_UART_REGS_BASE_100 0x1c8b0000 #define LASAT_UART_REGS_SHIFT_100 2 #define LASATINT_UART_100 16 diff --git a/arch/mips/include/asm/linkage.h b/arch/mips/include/asm/linkage.h index e9a940d1b0c..2767dda9e30 100644 --- a/arch/mips/include/asm/linkage.h +++ b/arch/mips/include/asm/linkage.h @@ -6,5 +6,8 @@ #endif #define __weak __attribute__((weak)) +#define cond_syscall(x) asm(".weak\t" #x "\n" #x "\t=\tsys_ni_syscall") +#define SYSCALL_ALIAS(alias, name) \ + asm ( #alias " = " #name "\n\t.globl " #alias) #endif diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h index 94fde8d0fac..46dfc3c1fd4 100644 --- a/arch/mips/include/asm/local.h +++ b/arch/mips/include/asm/local.h @@ -15,10 +15,10 @@ typedef struct #define LOCAL_INIT(i) { ATOMIC_LONG_INIT(i) } #define local_read(l) atomic_long_read(&(l)->a) -#define local_set(l, i) atomic_long_set(&(l)->a, (i)) +#define local_set(l, i) atomic_long_set(&(l)->a, (i)) -#define local_add(i, l) atomic_long_add((i), (&(l)->a)) -#define local_sub(i, l) atomic_long_sub((i), (&(l)->a)) +#define local_add(i, l) atomic_long_add((i), (&(l)->a)) +#define local_sub(i, l) atomic_long_sub((i), (&(l)->a)) #define local_inc(l) atomic_long_inc(&(l)->a) #define local_dec(l) atomic_long_dec(&(l)->a) @@ -33,7 +33,7 @@ static __inline__ long local_add_return(long i, local_t * l) unsigned long temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1:" __LL "%1, %2 # local_add_return \n" " addu %0, %1, %3 \n" __SC "%0, %2 \n" @@ -47,7 +47,7 @@ static __inline__ long local_add_return(long i, local_t * l) unsigned long temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1:" __LL "%1, %2 # local_add_return \n" " addu %0, %1, %3 \n" __SC "%0, %2 \n" @@ -78,7 +78,7 @@ static __inline__ long local_sub_return(long i, local_t * l) unsigned long temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1:" __LL "%1, %2 # local_sub_return \n" " subu %0, %1, %3 \n" __SC "%0, %2 \n" @@ -92,7 +92,7 @@ static __inline__ long local_sub_return(long i, local_t * l) unsigned long temp; __asm__ __volatile__( - " .set mips3 \n" + " .set arch=r4000 \n" "1:" __LL "%1, %2 # local_sub_return \n" " subu %0, %1, %3 \n" __SC "%0, %2 \n" diff --git a/arch/mips/include/asm/local64.h b/arch/mips/include/asm/local64.h deleted file mode 100644 index 36c93b5cc23..00000000000 --- a/arch/mips/include/asm/local64.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/local64.h> diff --git a/arch/mips/include/asm/m48t37.h b/arch/mips/include/asm/m48t37.h index cabf86264f3..e6eaf5339e4 100644 --- a/arch/mips/include/asm/m48t37.h +++ b/arch/mips/include/asm/m48t37.h @@ -9,7 +9,7 @@ extern spinlock_t rtc_lock; struct m48t37_rtc { - volatile u8 pad[0x7ff0]; /* NVRAM */ + volatile u8 pad[0x7ff0]; /* NVRAM */ volatile u8 flags; volatile u8 century; volatile u8 alarm_sec; diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h index 07d3fadb244..a47ea0c8524 100644 --- a/arch/mips/include/asm/mach-ar7/ar7.h +++ b/arch/mips/include/asm/mach-ar7/ar7.h @@ -40,9 +40,9 @@ #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200) #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600) #define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C) -#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800) +#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800) #define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00) -#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00) +#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00) #define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00) #define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400) #define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800) @@ -52,7 +52,7 @@ #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00) /* Titan registers */ -#define TITAN_REGS_ESWITCH_BASE (0x08640000) +#define TITAN_REGS_ESWITCH_BASE (0x08640000) #define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE) #define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800) #define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000) @@ -72,9 +72,9 @@ /* GPIO control registers */ #define AR7_GPIO_INPUT 0x0 -#define AR7_GPIO_OUTPUT 0x4 +#define AR7_GPIO_OUTPUT 0x4 #define AR7_GPIO_DIR 0x8 -#define AR7_GPIO_ENABLE 0xc +#define AR7_GPIO_ENABLE 0xc #define TITAN_GPIO_INPUT_0 0x0 #define TITAN_GPIO_INPUT_1 0x4 #define TITAN_GPIO_OUTPUT_0 0x8 @@ -88,10 +88,10 @@ #define AR7_CHIP_7200 0x2b #define AR7_CHIP_7300 0x05 #define AR7_CHIP_TITAN 0x07 -#define TITAN_CHIP_1050 0x0f -#define TITAN_CHIP_1055 0x0e -#define TITAN_CHIP_1056 0x0d -#define TITAN_CHIP_1060 0x07 +#define TITAN_CHIP_1050 0x0f +#define TITAN_CHIP_1055 0x0e +#define TITAN_CHIP_1056 0x0d +#define TITAN_CHIP_1060 0x07 /* Interrupts */ #define AR7_IRQ_UART0 15 diff --git a/arch/mips/include/asm/mach-ar7/irq.h b/arch/mips/include/asm/mach-ar7/irq.h index 39e9757e3d9..7ad10e379e2 100644 --- a/arch/mips/include/asm/mach-ar7/irq.h +++ b/arch/mips/include/asm/mach-ar7/irq.h @@ -9,7 +9,7 @@ #ifndef __ASM_AR7_IRQ_H #define __ASM_AR7_IRQ_H -#define NR_IRQS 256 +#define NR_IRQS 256 #include_next <irq.h> diff --git a/arch/mips/include/asm/mach-ar7/spaces.h b/arch/mips/include/asm/mach-ar7/spaces.h index ac28f273449..660ab64c0fc 100644 --- a/arch/mips/include/asm/mach-ar7/spaces.h +++ b/arch/mips/include/asm/mach-ar7/spaces.h @@ -14,8 +14,11 @@ * This handles the memory map. * We handle pages at KSEG0 for kernels with 32 bit address space. */ -#define PAGE_OFFSET 0x94000000UL -#define PHYS_OFFSET 0x14000000UL +#define PAGE_OFFSET _AC(0x94000000, UL) +#define PHYS_OFFSET _AC(0x14000000, UL) + +#define UNCAC_BASE _AC(0xb4000000, UL) /* 0xa0000000 + PHYS_OFFSET */ +#define IO_BASE UNCAC_BASE #include <asm/mach-generic/spaces.h> diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index a5e0f17ea77..cd41e93bc1d 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -16,7 +16,6 @@ #define __ASM_MACH_AR71XX_REGS_H #include <linux/types.h> -#include <linux/init.h> #include <linux/io.h> #include <linux/bitops.h> @@ -34,18 +33,44 @@ #define AR71XX_UART_SIZE 0x100 #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) #define AR71XX_USB_CTRL_SIZE 0x100 -#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) -#define AR71XX_GPIO_SIZE 0x100 +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) #define AR71XX_PLL_SIZE 0x100 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) #define AR71XX_RESET_SIZE 0x100 +#define AR71XX_PCI_MEM_BASE 0x10000000 +#define AR71XX_PCI_MEM_SIZE 0x07000000 + +#define AR71XX_PCI_WIN0_OFFS 0x10000000 +#define AR71XX_PCI_WIN1_OFFS 0x11000000 +#define AR71XX_PCI_WIN2_OFFS 0x12000000 +#define AR71XX_PCI_WIN3_OFFS 0x13000000 +#define AR71XX_PCI_WIN4_OFFS 0x14000000 +#define AR71XX_PCI_WIN5_OFFS 0x15000000 +#define AR71XX_PCI_WIN6_OFFS 0x16000000 +#define AR71XX_PCI_WIN7_OFFS 0x07000000 + +#define AR71XX_PCI_CFG_BASE \ + (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) +#define AR71XX_PCI_CFG_SIZE 0x100 + #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) #define AR7240_USB_CTRL_SIZE 0x100 #define AR7240_OHCI_BASE 0x1b000000 #define AR7240_OHCI_SIZE 0x1000 +#define AR724X_PCI_MEM_BASE 0x10000000 +#define AR724X_PCI_MEM_SIZE 0x04000000 + +#define AR724X_PCI_CFG_BASE 0x14000000 +#define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) +#define AR724X_PCI_CRP_SIZE 0x1000 +#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + #define AR724X_EHCI_BASE 0x1b000000 #define AR724X_EHCI_SIZE 0x1000 @@ -68,6 +93,25 @@ #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) #define AR934X_SRIF_SIZE 0x1000 +#define QCA955X_PCI_MEM_BASE0 0x10000000 +#define QCA955X_PCI_MEM_BASE1 0x12000000 +#define QCA955X_PCI_MEM_SIZE 0x02000000 +#define QCA955X_PCI_CFG_BASE0 0x14000000 +#define QCA955X_PCI_CFG_BASE1 0x16000000 +#define QCA955X_PCI_CFG_SIZE 0x1000 +#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA955X_PCI_CRP_SIZE 0x1000 +#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA955X_PCI_CTRL_SIZE 0x100 + +#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA955X_WMAC_SIZE 0x20000 +#define QCA955X_EHCI0_BASE 0x1b000000 +#define QCA955X_EHCI1_BASE 0x1b400000 +#define QCA955X_EHCI_SIZE 0x1000 + /* * DDR_CTRL block */ @@ -199,6 +243,41 @@ #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) +#define QCA955X_PLL_CPU_CONFIG_REG 0x00 +#define QCA955X_PLL_DDR_CONFIG_REG 0x04 +#define QCA955X_PLL_CLK_CTRL_REG 0x08 + +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + /* * USB_CONFIG block */ @@ -238,6 +317,10 @@ #define AR934X_RESET_REG_BOOTSTRAP 0xb0 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac +#define QCA955X_RESET_REG_RESET_MODULE 0x1c +#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + #define MISC_INT_ETHSW BIT(12) #define MISC_INT_TIMER4 BIT(10) #define MISC_INT_TIMER3 BIT(9) @@ -312,9 +395,11 @@ #define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) #define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) -#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) #define AR934X_BOOTSTRAP_DDR1 BIT(0) +#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) @@ -333,6 +418,37 @@ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ AR934X_PCIE_WMAC_INT_PCIE_RC3) +#define QCA955X_EXT_INT_WMAC_MISC BIT(0) +#define QCA955X_EXT_INT_WMAC_TX BIT(1) +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA955X_EXT_INT_USB1 BIT(24) +#define QCA955X_EXT_INT_USB2 BIT(28) + +#define QCA955X_EXT_INT_WMAC_ALL \ + (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ + QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) + +#define QCA955X_EXT_INT_PCIE_RC1_ALL \ + (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ + QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ + QCA955X_EXT_INT_PCIE_RC1_INT3) + +#define QCA955X_EXT_INT_PCIE_RC2_ALL \ + (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ + QCA955X_EXT_INT_PCIE_RC2_INT3) + #define REV_ID_MAJOR_MASK 0xfff0 #define REV_ID_MAJOR_AR71XX 0x00a0 #define REV_ID_MAJOR_AR913X 0x00b0 @@ -344,6 +460,8 @@ #define REV_ID_MAJOR_AR9341 0x0120 #define REV_ID_MAJOR_AR9342 0x1120 #define REV_ID_MAJOR_AR9344 0x2120 +#define REV_ID_MAJOR_QCA9556 0x0130 +#define REV_ID_MAJOR_QCA9558 0x1130 #define AR71XX_REV_ID_MINOR_MASK 0x3 #define AR71XX_REV_ID_MINOR_AR7130 0x0 @@ -362,7 +480,9 @@ #define AR724X_REV_ID_REVISION_MASK 0x3 -#define AR934X_REV_ID_REVISION_MASK 0xf +#define AR934X_REV_ID_REVISION_MASK 0xf + +#define QCA955X_REV_ID_REVISION_MASK 0xf /* * SPI block @@ -401,12 +521,15 @@ #define AR71XX_GPIO_REG_INT_ENABLE 0x24 #define AR71XX_GPIO_REG_FUNC 0x28 +#define AR934X_GPIO_REG_FUNC 0x6c + #define AR71XX_GPIO_COUNT 16 #define AR7240_GPIO_COUNT 18 #define AR7241_GPIO_COUNT 20 #define AR913X_GPIO_COUNT 22 #define AR933X_GPIO_COUNT 30 #define AR934X_GPIO_COUNT 23 +#define QCA955X_GPIO_COUNT 24 /* * SRIF block diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart.h b/arch/mips/include/asm/mach-ath79/ar933x_uart.h index 52730555937..c2917b39966 100644 --- a/arch/mips/include/asm/mach-ath79/ar933x_uart.h +++ b/arch/mips/include/asm/mach-ath79/ar933x_uart.h @@ -26,14 +26,14 @@ #define AR933X_UART_CS_PARITY_S 0 #define AR933X_UART_CS_PARITY_M 0x3 -#define AR933X_UART_CS_PARITY_NONE 0 -#define AR933X_UART_CS_PARITY_ODD 1 -#define AR933X_UART_CS_PARITY_EVEN 2 +#define AR933X_UART_CS_PARITY_NONE 0 +#define AR933X_UART_CS_PARITY_ODD 1 +#define AR933X_UART_CS_PARITY_EVEN 2 #define AR933X_UART_CS_IF_MODE_S 2 #define AR933X_UART_CS_IF_MODE_M 0x3 -#define AR933X_UART_CS_IF_MODE_NONE 0 -#define AR933X_UART_CS_IF_MODE_DTE 1 -#define AR933X_UART_CS_IF_MODE_DCE 2 +#define AR933X_UART_CS_IF_MODE_NONE 0 +#define AR933X_UART_CS_IF_MODE_DTE 1 +#define AR933X_UART_CS_IF_MODE_DCE 2 #define AR933X_UART_CS_FLOW_CTRL_S 4 #define AR933X_UART_CS_FLOW_CTRL_M 0x3 #define AR933X_UART_CS_DMA_EN BIT(6) diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h deleted file mode 100644 index 6cb30f2b719..00000000000 --- a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Platform data definition for Atheros AR933X UART - * - * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _AR933X_UART_PLATFORM_H -#define _AR933X_UART_PLATFORM_H - -struct ar933x_uart_platform_data { - unsigned uartclk; -}; - -#endif /* _AR933X_UART_PLATFORM_H */ diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h index 4f248c3d7b2..1557934aaca 100644 --- a/arch/mips/include/asm/mach-ath79/ath79.h +++ b/arch/mips/include/asm/mach-ath79/ath79.h @@ -32,6 +32,8 @@ enum ath79_soc_type { ATH79_SOC_AR9341, ATH79_SOC_AR9342, ATH79_SOC_AR9344, + ATH79_SOC_QCA9556, + ATH79_SOC_QCA9558, }; extern enum ath79_soc_type ath79_soc; @@ -98,6 +100,21 @@ static inline int soc_is_ar934x(void) return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); } +static inline int soc_is_qca9556(void) +{ + return ath79_soc == ATH79_SOC_QCA9556; +} + +static inline int soc_is_qca9558(void) +{ + return ath79_soc == ATH79_SOC_QCA9558; +} + +static inline int soc_is_qca955x(void) +{ + return soc_is_qca9556() || soc_is_qca9558(); +} + extern void __iomem *ath79_ddr_base; extern void __iomem *ath79_pll_base; extern void __iomem *ath79_reset_base; diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h index ea4b66dccf6..0089a740e5a 100644 --- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h @@ -42,14 +42,12 @@ #define cpu_has_mips64r1 0 #define cpu_has_mips64r2 0 -#define cpu_has_dsp 0 -#define cpu_has_dsp2 0 #define cpu_has_mipsmt 0 #define cpu_has_64bits 0 #define cpu_has_64bit_zero_reg 0 #define cpu_has_64bit_gp_regs 0 -#define cpu_has_64bit_addresses 0 +#define cpu_has_64bit_addresses 0 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h index 0968f69e201..5c9ca76a7eb 100644 --- a/arch/mips/include/asm/mach-ath79/irq.h +++ b/arch/mips/include/asm/mach-ath79/irq.h @@ -10,10 +10,13 @@ #define __ASM_MACH_ATH79_IRQ_H #define MIPS_CPU_IRQ_BASE 0 -#define NR_IRQS 48 +#define NR_IRQS 51 + +#define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x)) #define ATH79_MISC_IRQ_BASE 8 #define ATH79_MISC_IRQ_COUNT 32 +#define ATH79_MISC_IRQ(_x) (ATH79_MISC_IRQ_BASE + (_x)) #define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT) #define ATH79_PCI_IRQ_COUNT 6 @@ -23,25 +26,9 @@ #define ATH79_IP2_IRQ_COUNT 2 #define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x)) -#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) -#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) -#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) -#define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5) -#define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) -#define ATH79_CPU_IRQ_TIMER (MIPS_CPU_IRQ_BASE + 7) - -#define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0) -#define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1) -#define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2) -#define ATH79_MISC_IRQ_UART (ATH79_MISC_IRQ_BASE + 3) -#define ATH79_MISC_IRQ_WDOG (ATH79_MISC_IRQ_BASE + 4) -#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5) -#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6) -#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7) -#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8) -#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9) -#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10) -#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12) +#define ATH79_IP3_IRQ_BASE (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT) +#define ATH79_IP3_IRQ_COUNT 3 +#define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x)) #include_next <irq.h> diff --git a/arch/mips/include/asm/mach-ath79/pci.h b/arch/mips/include/asm/mach-ath79/pci.h deleted file mode 100644 index 7868f7fa028..00000000000 --- a/arch/mips/include/asm/mach-ath79/pci.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Atheros AR71XX/AR724X PCI support - * - * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> - * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef __ASM_MACH_ATH79_PCI_H -#define __ASM_MACH_ATH79_PCI_H - -#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX) -int ar71xx_pcibios_init(void); -#else -static inline int ar71xx_pcibios_init(void) { return 0; } -#endif - -#if defined(CONFIG_PCI_AR724X) -int ar724x_pcibios_init(int irq); -#else -static inline int ar724x_pcibios_init(int irq) { return 0; } -#endif - -#endif /* __ASM_MACH_ATH79_PCI_H */ diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 569828d3cca..b4c3ecb17d4 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -43,6 +43,8 @@ #include <linux/io.h> #include <linux/irq.h> +#include <asm/cpu.h> + /* cpu pipeline flush */ void static inline au_sync(void) { @@ -140,7 +142,7 @@ static inline int au1xxx_cpu_needs_config_od(void) static inline int alchemy_get_cputype(void) { - switch (read_c0_prid() & 0xffff0000) { + switch (read_c0_prid() & (PRID_OPT_MASK | PRID_COMP_MASK)) { case 0x00030000: return ALCHEMY_CPU_AU1000; break; @@ -349,7 +351,7 @@ extern void au1300_vss_block_control(int block, int enable); #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) -#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST +#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST /* Au1300-style (GPIC): 1 controller with up to 128 sources */ #define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8) @@ -589,7 +591,7 @@ enum soc_au1550_ints { AU1550_GPIO14_INT, AU1550_GPIO15_INT, AU1550_GPIO200_INT, - AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */ + AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */ AU1550_GPIO16_INT, AU1550_GPIO17_INT, AU1550_GPIO20_INT, @@ -603,7 +605,7 @@ enum soc_au1550_ints { AU1550_GPIO28_INT, AU1550_GPIO206_INT, AU1550_GPIO207_INT, - AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */ + AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */ }; enum soc_au1200_ints { @@ -636,7 +638,7 @@ enum soc_au1200_ints { AU1200_GPIO205_INT, AU1200_GPIO206_INT, AU1200_GPIO207_INT, - AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */ + AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */ AU1200_USB_INT, AU1200_LCD_INT, AU1200_MAE_BOTH_INT, @@ -823,7 +825,7 @@ enum soc_au1200_ints { #define GPIC_GPIO_TO_BIT(gpio) \ (1 << ((gpio) & 0x1f)) -#define GPIC_GPIO_BANKOFF(gpio) \ +#define GPIC_GPIO_BANKOFF(gpio) \ (((gpio) >> 5) * 4) /* Pin Control bits: who owns the pin, what does it do */ @@ -958,32 +960,32 @@ enum soc_au1200_ints { #define MEM_STSTAT 0xB4001104 #define MEM_STNAND_CMD 0x0 -#define MEM_STNAND_ADDR 0x4 -#define MEM_STNAND_DATA 0x20 +#define MEM_STNAND_ADDR 0x4 +#define MEM_STNAND_DATA 0x20 /* Programmable Counters 0 and 1 */ #define SYS_BASE 0xB1900000 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) -# define SYS_CNTRL_E1S (1 << 23) -# define SYS_CNTRL_T1S (1 << 20) -# define SYS_CNTRL_M21 (1 << 19) -# define SYS_CNTRL_M11 (1 << 18) -# define SYS_CNTRL_M01 (1 << 17) -# define SYS_CNTRL_C1S (1 << 16) +# define SYS_CNTRL_E1S (1 << 23) +# define SYS_CNTRL_T1S (1 << 20) +# define SYS_CNTRL_M21 (1 << 19) +# define SYS_CNTRL_M11 (1 << 18) +# define SYS_CNTRL_M01 (1 << 17) +# define SYS_CNTRL_C1S (1 << 16) # define SYS_CNTRL_BP (1 << 14) -# define SYS_CNTRL_EN1 (1 << 13) -# define SYS_CNTRL_BT1 (1 << 12) -# define SYS_CNTRL_EN0 (1 << 11) -# define SYS_CNTRL_BT0 (1 << 10) +# define SYS_CNTRL_EN1 (1 << 13) +# define SYS_CNTRL_BT1 (1 << 12) +# define SYS_CNTRL_EN0 (1 << 11) +# define SYS_CNTRL_BT0 (1 << 10) # define SYS_CNTRL_E0 (1 << 8) -# define SYS_CNTRL_E0S (1 << 7) -# define SYS_CNTRL_32S (1 << 5) -# define SYS_CNTRL_T0S (1 << 4) -# define SYS_CNTRL_M20 (1 << 3) -# define SYS_CNTRL_M10 (1 << 2) -# define SYS_CNTRL_M00 (1 << 1) -# define SYS_CNTRL_C0S (1 << 0) +# define SYS_CNTRL_E0S (1 << 7) +# define SYS_CNTRL_32S (1 << 5) +# define SYS_CNTRL_T0S (1 << 4) +# define SYS_CNTRL_M20 (1 << 3) +# define SYS_CNTRL_M10 (1 << 2) +# define SYS_CNTRL_M00 (1 << 1) +# define SYS_CNTRL_C0S (1 << 0) /* Programmable Counter 0 Registers */ #define SYS_TOYTRIM (SYS_BASE + 0) @@ -1003,33 +1005,33 @@ enum soc_au1200_ints { /* I2S Controller */ #define I2S_DATA 0xB1000000 -# define I2S_DATA_MASK 0xffffff +# define I2S_DATA_MASK 0xffffff #define I2S_CONFIG 0xB1000004 -# define I2S_CONFIG_XU (1 << 25) -# define I2S_CONFIG_XO (1 << 24) -# define I2S_CONFIG_RU (1 << 23) -# define I2S_CONFIG_RO (1 << 22) -# define I2S_CONFIG_TR (1 << 21) -# define I2S_CONFIG_TE (1 << 20) -# define I2S_CONFIG_TF (1 << 19) -# define I2S_CONFIG_RR (1 << 18) -# define I2S_CONFIG_RE (1 << 17) -# define I2S_CONFIG_RF (1 << 16) -# define I2S_CONFIG_PD (1 << 11) -# define I2S_CONFIG_LB (1 << 10) -# define I2S_CONFIG_IC (1 << 9) +# define I2S_CONFIG_XU (1 << 25) +# define I2S_CONFIG_XO (1 << 24) +# define I2S_CONFIG_RU (1 << 23) +# define I2S_CONFIG_RO (1 << 22) +# define I2S_CONFIG_TR (1 << 21) +# define I2S_CONFIG_TE (1 << 20) +# define I2S_CONFIG_TF (1 << 19) +# define I2S_CONFIG_RR (1 << 18) +# define I2S_CONFIG_RE (1 << 17) +# define I2S_CONFIG_RF (1 << 16) +# define I2S_CONFIG_PD (1 << 11) +# define I2S_CONFIG_LB (1 << 10) +# define I2S_CONFIG_IC (1 << 9) # define I2S_CONFIG_FM_BIT 7 # define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) # define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) # define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) # define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) -# define I2S_CONFIG_TN (1 << 6) -# define I2S_CONFIG_RN (1 << 5) +# define I2S_CONFIG_TN (1 << 6) +# define I2S_CONFIG_RN (1 << 5) # define I2S_CONFIG_SZ_BIT 0 # define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) #define I2S_CONTROL 0xB1000008 -# define I2S_CONTROL_D (1 << 1) +# define I2S_CONTROL_D (1 << 1) # define I2S_CONTROL_CE (1 << 0) @@ -1037,16 +1039,16 @@ enum soc_au1200_ints { /* 4 byte offsets from AU1000_ETH_BASE */ #define MAC_CONTROL 0x0 -# define MAC_RX_ENABLE (1 << 2) -# define MAC_TX_ENABLE (1 << 3) -# define MAC_DEF_CHECK (1 << 5) -# define MAC_SET_BL(X) (((X) & 0x3) << 6) +# define MAC_RX_ENABLE (1 << 2) +# define MAC_TX_ENABLE (1 << 3) +# define MAC_DEF_CHECK (1 << 5) +# define MAC_SET_BL(X) (((X) & 0x3) << 6) # define MAC_AUTO_PAD (1 << 8) # define MAC_DISABLE_RETRY (1 << 10) # define MAC_DISABLE_BCAST (1 << 11) # define MAC_LATE_COL (1 << 12) -# define MAC_HASH_MODE (1 << 13) -# define MAC_HASH_ONLY (1 << 15) +# define MAC_HASH_MODE (1 << 13) +# define MAC_HASH_ONLY (1 << 15) # define MAC_PASS_ALL (1 << 16) # define MAC_INVERSE_FILTER (1 << 17) # define MAC_PROMISCUOUS (1 << 18) @@ -1083,9 +1085,9 @@ enum soc_au1200_ints { # define MAC_EN_RESET0 (1 << 1) # define MAC_EN_TOSS (0 << 2) # define MAC_EN_CACHEABLE (1 << 3) -# define MAC_EN_RESET1 (1 << 4) -# define MAC_EN_RESET2 (1 << 5) -# define MAC_DMA_RESET (1 << 6) +# define MAC_EN_RESET1 (1 << 4) +# define MAC_EN_RESET2 (1 << 5) +# define MAC_DMA_RESET (1 << 6) /* Ethernet Controller DMA Channels */ @@ -1095,7 +1097,7 @@ enum soc_au1200_ints { #define MAC_TX_BUFF0_STATUS 0x0 # define TX_FRAME_ABORTED (1 << 0) # define TX_JAB_TIMEOUT (1 << 1) -# define TX_NO_CARRIER (1 << 2) +# define TX_NO_CARRIER (1 << 2) # define TX_LOSS_CARRIER (1 << 3) # define TX_EXC_DEF (1 << 4) # define TX_LATE_COLL_ABORT (1 << 5) @@ -1106,7 +1108,7 @@ enum soc_au1200_ints { # define TX_COLL_CNT_MASK (0xF << 10) # define TX_PKT_RETRY (1 << 31) #define MAC_TX_BUFF0_ADDR 0x4 -# define TX_DMA_ENABLE (1 << 0) +# define TX_DMA_ENABLE (1 << 0) # define TX_T_DONE (1 << 1) # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) #define MAC_TX_BUFF0_LEN 0x8 @@ -1125,7 +1127,7 @@ enum soc_au1200_ints { /* offsets from MAC_RX_RING_ADDR */ #define MAC_RX_BUFF0_STATUS 0x0 # define RX_FRAME_LEN_MASK 0x3fff -# define RX_WDOG_TIMER (1 << 14) +# define RX_WDOG_TIMER (1 << 14) # define RX_RUNT (1 << 15) # define RX_OVERLEN (1 << 16) # define RX_COLL (1 << 17) @@ -1148,7 +1150,7 @@ enum soc_au1200_ints { RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) #define MAC_RX_BUFF0_ADDR 0x4 -# define RX_DMA_ENABLE (1 << 0) +# define RX_DMA_ENABLE (1 << 0) # define RX_T_DONE (1 << 1) # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0) @@ -1159,48 +1161,36 @@ enum soc_au1200_ints { #define MAC_RX_BUFF3_STATUS 0x30 #define MAC_RX_BUFF3_ADDR 0x34 -#define UART_RX 0 /* Receive buffer */ -#define UART_TX 4 /* Transmit buffer */ -#define UART_IER 8 /* Interrupt Enable Register */ -#define UART_IIR 0xC /* Interrupt ID Register */ -#define UART_FCR 0x10 /* FIFO Control Register */ -#define UART_LCR 0x14 /* Line Control Register */ -#define UART_MCR 0x18 /* Modem Control Register */ -#define UART_LSR 0x1C /* Line Status Register */ -#define UART_MSR 0x20 /* Modem Status Register */ -#define UART_CLK 0x28 /* Baud Rate Clock Divider */ -#define UART_MOD_CNTRL 0x100 /* Module Control */ - /* SSIO */ #define SSI0_STATUS 0xB1600000 -# define SSI_STATUS_BF (1 << 4) -# define SSI_STATUS_OF (1 << 3) -# define SSI_STATUS_UF (1 << 2) +# define SSI_STATUS_BF (1 << 4) +# define SSI_STATUS_OF (1 << 3) +# define SSI_STATUS_UF (1 << 2) # define SSI_STATUS_D (1 << 1) # define SSI_STATUS_B (1 << 0) #define SSI0_INT 0xB1600004 # define SSI_INT_OI (1 << 3) # define SSI_INT_UI (1 << 2) # define SSI_INT_DI (1 << 1) -#define SSI0_INT_ENABLE 0xB1600008 +#define SSI0_INT_ENABLE 0xB1600008 # define SSI_INTE_OIE (1 << 3) # define SSI_INTE_UIE (1 << 2) # define SSI_INTE_DIE (1 << 1) #define SSI0_CONFIG 0xB1600020 -# define SSI_CONFIG_AO (1 << 24) -# define SSI_CONFIG_DO (1 << 23) +# define SSI_CONFIG_AO (1 << 24) +# define SSI_CONFIG_DO (1 << 23) # define SSI_CONFIG_ALEN_BIT 20 # define SSI_CONFIG_ALEN_MASK (0x7 << 20) # define SSI_CONFIG_DLEN_BIT 16 # define SSI_CONFIG_DLEN_MASK (0x7 << 16) -# define SSI_CONFIG_DD (1 << 11) -# define SSI_CONFIG_AD (1 << 10) +# define SSI_CONFIG_DD (1 << 11) +# define SSI_CONFIG_AD (1 << 10) # define SSI_CONFIG_BM_BIT 8 # define SSI_CONFIG_BM_MASK (0x3 << 8) -# define SSI_CONFIG_CE (1 << 7) -# define SSI_CONFIG_DP (1 << 6) -# define SSI_CONFIG_DL (1 << 5) -# define SSI_CONFIG_EP (1 << 4) +# define SSI_CONFIG_CE (1 << 7) +# define SSI_CONFIG_DP (1 << 6) +# define SSI_CONFIG_DL (1 << 5) +# define SSI_CONFIG_EP (1 << 4) #define SSI0_ADATA 0xB1600024 # define SSI_AD_D (1 << 24) # define SSI_AD_ADDR_BIT 16 @@ -1210,12 +1200,12 @@ enum soc_au1200_ints { #define SSI0_CLKDIV 0xB1600028 #define SSI0_CONTROL 0xB1600100 # define SSI_CONTROL_CD (1 << 1) -# define SSI_CONTROL_E (1 << 0) +# define SSI_CONTROL_E (1 << 0) /* SSI1 */ #define SSI1_STATUS 0xB1680000 #define SSI1_INT 0xB1680004 -#define SSI1_INT_ENABLE 0xB1680008 +#define SSI1_INT_ENABLE 0xB1680008 #define SSI1_CONFIG 0xB1680020 #define SSI1_ADATA 0xB1680024 #define SSI1_CLKDIV 0xB1680028 @@ -1242,8 +1232,8 @@ enum soc_au1200_ints { #define SSI_CONFIG_AO (1 << 24) #define SSI_CONFIG_DO (1 << 23) -#define SSI_CONFIG_ALEN (7 << 20) -#define SSI_CONFIG_DLEN (15 << 16) +#define SSI_CONFIG_ALEN (7 << 20) +#define SSI_CONFIG_DLEN (15 << 16) #define SSI_CONFIG_DD (1 << 11) #define SSI_CONFIG_AD (1 << 10) #define SSI_CONFIG_BM (3 << 8) @@ -1305,7 +1295,7 @@ struct au1k_irda_platform_data { # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */ # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */ -/* Au1550 only. Redefines lots of pins */ +/* Au1550 only. Redefines lots of pins */ # define SYS_PF_PSC2_MASK (7 << 17) # define SYS_PF_PSC2_AC97 0 # define SYS_PF_PSC2_SPI 0 @@ -1322,33 +1312,33 @@ struct au1k_irda_platform_data { # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) /* Au1200 only */ -#define SYS_PINFUNC_DMA (1 << 31) -#define SYS_PINFUNC_S0A (1 << 30) -#define SYS_PINFUNC_S1A (1 << 29) -#define SYS_PINFUNC_LP0 (1 << 28) -#define SYS_PINFUNC_LP1 (1 << 27) -#define SYS_PINFUNC_LD16 (1 << 26) -#define SYS_PINFUNC_LD8 (1 << 25) -#define SYS_PINFUNC_LD1 (1 << 24) -#define SYS_PINFUNC_LD0 (1 << 23) -#define SYS_PINFUNC_P1A (3 << 21) -#define SYS_PINFUNC_P1B (1 << 20) -#define SYS_PINFUNC_FS3 (1 << 19) -#define SYS_PINFUNC_P0A (3 << 17) +#define SYS_PINFUNC_DMA (1 << 31) +#define SYS_PINFUNC_S0A (1 << 30) +#define SYS_PINFUNC_S1A (1 << 29) +#define SYS_PINFUNC_LP0 (1 << 28) +#define SYS_PINFUNC_LP1 (1 << 27) +#define SYS_PINFUNC_LD16 (1 << 26) +#define SYS_PINFUNC_LD8 (1 << 25) +#define SYS_PINFUNC_LD1 (1 << 24) +#define SYS_PINFUNC_LD0 (1 << 23) +#define SYS_PINFUNC_P1A (3 << 21) +#define SYS_PINFUNC_P1B (1 << 20) +#define SYS_PINFUNC_FS3 (1 << 19) +#define SYS_PINFUNC_P0A (3 << 17) #define SYS_PINFUNC_CS (1 << 16) -#define SYS_PINFUNC_CIM (1 << 15) -#define SYS_PINFUNC_P1C (1 << 14) -#define SYS_PINFUNC_U1T (1 << 12) -#define SYS_PINFUNC_U1R (1 << 11) -#define SYS_PINFUNC_EX1 (1 << 10) -#define SYS_PINFUNC_EX0 (1 << 9) -#define SYS_PINFUNC_U0R (1 << 8) +#define SYS_PINFUNC_CIM (1 << 15) +#define SYS_PINFUNC_P1C (1 << 14) +#define SYS_PINFUNC_U1T (1 << 12) +#define SYS_PINFUNC_U1R (1 << 11) +#define SYS_PINFUNC_EX1 (1 << 10) +#define SYS_PINFUNC_EX0 (1 << 9) +#define SYS_PINFUNC_U0R (1 << 8) #define SYS_PINFUNC_MC (1 << 7) -#define SYS_PINFUNC_S0B (1 << 6) -#define SYS_PINFUNC_S0C (1 << 5) -#define SYS_PINFUNC_P0B (1 << 4) -#define SYS_PINFUNC_U0T (1 << 3) -#define SYS_PINFUNC_S1B (1 << 2) +#define SYS_PINFUNC_S0B (1 << 6) +#define SYS_PINFUNC_S0C (1 << 5) +#define SYS_PINFUNC_P0B (1 << 4) +#define SYS_PINFUNC_U0T (1 << 3) +#define SYS_PINFUNC_S1B (1 << 2) /* Power Management */ #define SYS_SCRATCH0 0xB1900018 @@ -1405,7 +1395,7 @@ struct au1k_irda_platform_data { # define SYS_CS_DI2 (1 << 16) # define SYS_CS_CI2 (1 << 15) -# define SYS_CS_ML_BIT 7 +# define SYS_CS_ML_BIT 7 # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT) # define SYS_CS_DL (1 << 6) # define SYS_CS_CL (1 << 5) @@ -1554,8 +1544,8 @@ struct au1k_irda_platform_data { #define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16) #define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff) #define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16) -#define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8) -#define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff) +#define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8) +#define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff) #define PCI_ID_DID(x) (((x) & 0xffff) << 16) #define PCI_ID_VID(x) ((x) & 0xffff) #define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16) diff --git a/arch/mips/include/asm/mach-au1x00/au1000_dma.h b/arch/mips/include/asm/mach-au1x00/au1000_dma.h index ba4cf0e91c8..7cedca5a305 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000_dma.h +++ b/arch/mips/include/asm/mach-au1x00/au1000_dma.h @@ -34,7 +34,7 @@ #include <linux/spinlock.h> /* And spinlocks */ #include <linux/delay.h> -#define NUM_AU1000_DMA_CHANNELS 8 +#define NUM_AU1000_DMA_CHANNELS 8 /* DMA Channel Register Offsets */ #define DMA_MODE_SET 0x00000000 @@ -47,7 +47,7 @@ #define DMA_DS (1 << 15) #define DMA_BE (1 << 13) #define DMA_DR (1 << 12) -#define DMA_TS8 (1 << 11) +#define DMA_TS8 (1 << 11) #define DMA_DW_BIT 9 #define DMA_DW_MASK (0x03 << DMA_DW_BIT) #define DMA_DW8 (0 << DMA_DW_BIT) @@ -59,9 +59,9 @@ #define DMA_GO (1 << 5) #define DMA_AB (1 << 4) #define DMA_D1 (1 << 3) -#define DMA_BE1 (1 << 2) +#define DMA_BE1 (1 << 2) #define DMA_D0 (1 << 1) -#define DMA_BE0 (1 << 0) +#define DMA_BE0 (1 << 0) #define DMA_PERIPHERAL_ADDR 0x00000008 #define DMA_BUFFER0_START 0x0000000C @@ -246,7 +246,7 @@ static inline void init_dma(unsigned int dmanr) mode |= DMA_IE; au_writel(~mode, chan->io + DMA_MODE_CLEAR); - au_writel(mode, chan->io + DMA_MODE_SET); + au_writel(mode, chan->io + DMA_MODE_SET); } /* diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h index e221659f1bc..cadab91cee2 100644 --- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h +++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h @@ -148,7 +148,7 @@ struct au1xmmc_platform_data { /* * SD_STATUS bit definitions. */ -#define SD_STATUS_DCRCW (0x00000007) +#define SD_STATUS_DCRCW (0x00000007) #define SD_STATUS_xx1 (0x00000008) #define SD_STATUS_CB (0x00000010) #define SD_STATUS_DB (0x00000020) diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index 217810e1836..ca8077afac4 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -103,7 +103,7 @@ typedef volatile struct au1xxx_ddma_desc { * Lets have some SW data following -- make sure it's 32 bytes. */ u32 sw_status; - u32 sw_context; + u32 sw_context; u32 sw_reserved[6]; } au1x_ddma_desc_t; @@ -123,7 +123,7 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */ #define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */ -#define SW_STATUS_INUSE (1 << 0) +#define SW_STATUS_INUSE (1 << 0) /* Command 0 device IDs. */ #define AU1550_DSCR_CMD0_UART0_TX 0 @@ -195,8 +195,8 @@ typedef volatile struct au1xxx_ddma_desc { #define AU1300_DSCR_CMD0_SDMS_RX0 9 #define AU1300_DSCR_CMD0_SDMS_TX1 10 #define AU1300_DSCR_CMD0_SDMS_RX1 11 -#define AU1300_DSCR_CMD0_AES_TX 12 -#define AU1300_DSCR_CMD0_AES_RX 13 +#define AU1300_DSCR_CMD0_AES_TX 12 +#define AU1300_DSCR_CMD0_AES_RX 13 #define AU1300_DSCR_CMD0_PSC0_TX 14 #define AU1300_DSCR_CMD0_PSC0_RX 15 #define AU1300_DSCR_CMD0_PSC1_TX 16 @@ -205,12 +205,12 @@ typedef volatile struct au1xxx_ddma_desc { #define AU1300_DSCR_CMD0_PSC2_RX 19 #define AU1300_DSCR_CMD0_PSC3_TX 20 #define AU1300_DSCR_CMD0_PSC3_RX 21 -#define AU1300_DSCR_CMD0_LCD 22 +#define AU1300_DSCR_CMD0_LCD 22 #define AU1300_DSCR_CMD0_NAND_FLASH 23 #define AU1300_DSCR_CMD0_SDMS_TX2 24 #define AU1300_DSCR_CMD0_SDMS_RX2 25 #define AU1300_DSCR_CMD0_CIM_SYNC 26 -#define AU1300_DSCR_CMD0_UDMA 27 +#define AU1300_DSCR_CMD0_UDMA 27 #define AU1300_DSCR_CMD0_DMA_REQ0 28 #define AU1300_DSCR_CMD0_DMA_REQ1 29 @@ -298,7 +298,7 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_NXTPTR_MS (1 << 27) /* The number of DBDMA channels. */ -#define NUM_DBDMA_CHANS 16 +#define NUM_DBDMA_CHANS 16 /* * DDMA API definitions @@ -316,7 +316,7 @@ typedef struct dbdma_device_table { typedef struct dbdma_chan_config { - spinlock_t lock; + spinlock_t lock; u32 chan_flags; u32 chan_index; diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h index e306384b141..bb91b8923a4 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h @@ -1,5 +1,5 @@ /* - * include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005 + * include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005 * * BRIEF MODULE DESCRIPTION * AMD Alchemy Au1xxx IDE interface routines over the Static Bus @@ -27,14 +27,14 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. * * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE - * Interface and Linux Device Driver" Application Note. + * Interface and Linux Device Driver" Application Note. */ #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA #define DMA_WAIT_TIMEOUT 100 -#define NUM_DESCRIPTORS PRD_ENTRIES +#define NUM_DESCRIPTORS PRD_ENTRIES #else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */ -#define NUM_DESCRIPTORS 2 +#define NUM_DESCRIPTORS 2 #endif #ifndef AU1XXX_ATA_RQSIZE @@ -84,8 +84,8 @@ typedef struct { #define TWP_MASK (0x3F << 14) #define TCSW_MASK (0x0F << 10) #define TPM_MASK (0x0F << 6) -#define TA_MASK (0x3F << 0) -#define TS_MASK (1 << 8) +#define TA_MASK (0x3F << 0) +#define TS_MASK (1 << 8) /* Timing parameters PIO mode 0 */ #define SBC_IDE_PIO0_TCSOE (0x04 << 29) @@ -96,7 +96,7 @@ typedef struct { #define SBC_IDE_PIO0_TWP (0x10 << 14) #define SBC_IDE_PIO0_TCSW (0x04 << 10) #define SBC_IDE_PIO0_TPM (0x00 << 6) -#define SBC_IDE_PIO0_TA (0x15 << 0) +#define SBC_IDE_PIO0_TA (0x15 << 0) /* Timing parameters PIO mode 1 */ #define SBC_IDE_PIO1_TCSOE (0x03 << 29) #define SBC_IDE_PIO1_TOECS (0x01 << 26) @@ -106,7 +106,7 @@ typedef struct { #define SBC_IDE_PIO1_TWP (0x08 << 14) #define SBC_IDE_PIO1_TCSW (0x03 << 10) #define SBC_IDE_PIO1_TPM (0x00 << 6) -#define SBC_IDE_PIO1_TA (0x0B << 0) +#define SBC_IDE_PIO1_TA (0x0B << 0) /* Timing parameters PIO mode 2 */ #define SBC_IDE_PIO2_TCSOE (0x05 << 29) #define SBC_IDE_PIO2_TOECS (0x01 << 26) @@ -116,7 +116,7 @@ typedef struct { #define SBC_IDE_PIO2_TWP (0x1F << 14) #define SBC_IDE_PIO2_TCSW (0x05 << 10) #define SBC_IDE_PIO2_TPM (0x00 << 6) -#define SBC_IDE_PIO2_TA (0x22 << 0) +#define SBC_IDE_PIO2_TA (0x22 << 0) /* Timing parameters PIO mode 3 */ #define SBC_IDE_PIO3_TCSOE (0x05 << 29) #define SBC_IDE_PIO3_TOECS (0x01 << 26) @@ -126,7 +126,7 @@ typedef struct { #define SBC_IDE_PIO3_TWP (0x15 << 14) #define SBC_IDE_PIO3_TCSW (0x05 << 10) #define SBC_IDE_PIO3_TPM (0x00 << 6) -#define SBC_IDE_PIO3_TA (0x1A << 0) +#define SBC_IDE_PIO3_TA (0x1A << 0) /* Timing parameters PIO mode 4 */ #define SBC_IDE_PIO4_TCSOE (0x04 << 29) #define SBC_IDE_PIO4_TOECS (0x01 << 26) @@ -136,7 +136,7 @@ typedef struct { #define SBC_IDE_PIO4_TWP (0x0D << 14) #define SBC_IDE_PIO4_TCSW (0x03 << 10) #define SBC_IDE_PIO4_TPM (0x00 << 6) -#define SBC_IDE_PIO4_TA (0x12 << 0) +#define SBC_IDE_PIO4_TA (0x12 << 0) /* Timing parameters MDMA mode 0 */ #define SBC_IDE_MDMA0_TCSOE (0x03 << 29) #define SBC_IDE_MDMA0_TOECS (0x01 << 26) diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h index 4e3f3bc26c6..8a9cd754be2 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h @@ -53,7 +53,7 @@ #define PSC_CTRL_DISABLE 0 #define PSC_CTRL_SUSPEND 2 -#define PSC_CTRL_ENABLE 3 +#define PSC_CTRL_ENABLE 3 /* AC97 Registers. */ #define PSC_AC97CFG_OFFSET 0x00000008 @@ -85,8 +85,8 @@ #define PSC_AC97CFG_SE_ENABLE (1 << 25) #define PSC_AC97CFG_LEN_MASK (0xf << 21) -#define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11) -#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1) +#define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11) +#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1) #define PSC_AC97CFG_GE_ENABLE (1) /* Enable slots 3-12. */ @@ -95,7 +95,7 @@ /* * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately. - * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the + * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the * arithmetic in the macro. */ #define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21) diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h index 73853b5a2a3..796afd051c3 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h @@ -12,14 +12,14 @@ #include <asm/mach-au1x00/au1000.h> /* The default GPIO numberspace as documented in the Alchemy manuals. - * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block. + * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block. */ #define ALCHEMY_GPIO1_BASE 0 #define ALCHEMY_GPIO2_BASE 200 #define ALCHEMY_GPIO1_NUM 32 #define ALCHEMY_GPIO2_NUM 16 -#define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1) +#define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1) #define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1) #define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off)) @@ -67,7 +67,7 @@ static inline int au1500_gpio1_to_irq(int gpio) switch (gpio) { case 0 ... 15: case 20: - case 23 ... 28: return MAKE_IRQ(1, gpio); + case 23 ... 28: return MAKE_IRQ(1, gpio); } return -ENXIO; @@ -139,8 +139,8 @@ static inline int au1550_gpio1_to_irq(int gpio) switch (gpio) { case 0 ... 15: - case 20 ... 28: return MAKE_IRQ(1, gpio); - case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16); + case 20 ... 28: return MAKE_IRQ(1, gpio); + case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16); } return -ENXIO; @@ -152,9 +152,9 @@ static inline int au1550_gpio2_to_irq(int gpio) switch (gpio) { case 0: return MAKE_IRQ(1, 16); - case 1 ... 5: return MAKE_IRQ(1, 17); /* shared GPIO201_205 */ + case 1 ... 5: return MAKE_IRQ(1, 17); /* shared GPIO201_205 */ case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6); - case 8 ... 15: return MAKE_IRQ(1, 31); /* shared GPIO208_215 */ + case 8 ... 15: return MAKE_IRQ(1, 31); /* shared GPIO208_215 */ } return -ENXIO; @@ -190,7 +190,7 @@ static inline int au1200_gpio2_to_irq(int gpio) case 0 ... 2: return MAKE_IRQ(0, 5 + gpio - 0); case 3: return MAKE_IRQ(0, 22); case 4 ... 7: return MAKE_IRQ(0, 24 + gpio - 4); - case 8 ... 15: return MAKE_IRQ(0, 28); /* shared GPIO208_215 */ + case 8 ... 15: return MAKE_IRQ(0, 28); /* shared GPIO208_215 */ } return -ENXIO; @@ -428,7 +428,7 @@ static inline void alchemy_gpio2_disable_int(int gpio2) /** * alchemy_gpio2_enable - Activate GPIO2 block. * - * The GPIO2 block must be enabled excplicitly to work. On systems + * The GPIO2 block must be enabled excplicitly to work. On systems * where this isn't done by the bootloader, this macro can be used. */ static inline void alchemy_gpio2_enable(void) @@ -533,7 +533,7 @@ static inline int alchemy_irq_to_gpio(int irq) * 2 (1 for Au1000) gpio_chips are registered. * *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y: - * the boards' gpio.h must provide the linux gpio wrapper functions, + * the boards' gpio.h must provide the linux gpio wrapper functions, * *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n: * inlinable gpio functions are provided which enable access to the diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h index fb9975c74c5..ce02894271c 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h @@ -130,7 +130,7 @@ static inline int au1300_gpio_getinitlvl(unsigned int gpio) * A gpiochip for the 75 GPIOs is registered. * *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y: -* the boards' gpio.h must provide the linux gpio wrapper functions, +* the boards' gpio.h must provide the linux gpio wrapper functions, * *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n: * inlinable gpio functions are provided which enable access to the diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h index cc7563ba1cb..7527c1d33d0 100644 --- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h +++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h @@ -56,4 +56,6 @@ void bcm47xx_fill_bcma_boardinfo(struct bcma_boardinfo *boardinfo, const char *prefix); #endif +void bcm47xx_set_system_type(u16 chip_id); + #endif /* __ASM_BCM47XX_H */ diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h new file mode 100644 index 00000000000..bba7399a49a --- /dev/null +++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h @@ -0,0 +1,117 @@ +#ifndef __BCM47XX_BOARD_H +#define __BCM47XX_BOARD_H + +enum bcm47xx_board { + BCM47XX_BOARD_ASUS_RTAC66U, + BCM47XX_BOARD_ASUS_RTN10, + BCM47XX_BOARD_ASUS_RTN10D, + BCM47XX_BOARD_ASUS_RTN10U, + BCM47XX_BOARD_ASUS_RTN12, + BCM47XX_BOARD_ASUS_RTN12B1, + BCM47XX_BOARD_ASUS_RTN12C1, + BCM47XX_BOARD_ASUS_RTN12D1, + BCM47XX_BOARD_ASUS_RTN12HP, + BCM47XX_BOARD_ASUS_RTN15U, + BCM47XX_BOARD_ASUS_RTN16, + BCM47XX_BOARD_ASUS_RTN53, + BCM47XX_BOARD_ASUS_RTN66U, + BCM47XX_BOARD_ASUS_WL300G, + BCM47XX_BOARD_ASUS_WL320GE, + BCM47XX_BOARD_ASUS_WL330GE, + BCM47XX_BOARD_ASUS_WL500GD, + BCM47XX_BOARD_ASUS_WL500GPV1, + BCM47XX_BOARD_ASUS_WL500GPV2, + BCM47XX_BOARD_ASUS_WL500W, + BCM47XX_BOARD_ASUS_WL520GC, + BCM47XX_BOARD_ASUS_WL520GU, + BCM47XX_BOARD_ASUS_WL700GE, + BCM47XX_BOARD_ASUS_WLHDD, + + BCM47XX_BOARD_BELKIN_F7D3301, + BCM47XX_BOARD_BELKIN_F7D3302, + BCM47XX_BOARD_BELKIN_F7D4301, + BCM47XX_BOARD_BELKIN_F7D4302, + BCM47XX_BOARD_BELKIN_F7D4401, + + BCM47XX_BOARD_BUFFALO_WBR2_G54, + BCM47XX_BOARD_BUFFALO_WHR2_A54G54, + BCM47XX_BOARD_BUFFALO_WHR_G125, + BCM47XX_BOARD_BUFFALO_WHR_G54S, + BCM47XX_BOARD_BUFFALO_WHR_HP_G54, + BCM47XX_BOARD_BUFFALO_WLA2_G54L, + BCM47XX_BOARD_BUFFALO_WZR_G300N, + BCM47XX_BOARD_BUFFALO_WZR_RS_G54, + BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP, + + BCM47XX_BOARD_CISCO_M10V1, + BCM47XX_BOARD_CISCO_M20V1, + + BCM47XX_BOARD_DELL_TM2300, + + BCM47XX_BOARD_DLINK_DIR130, + BCM47XX_BOARD_DLINK_DIR330, + + BCM47XX_BOARD_HUAWEI_E970, + + BCM47XX_BOARD_LINKSYS_E900V1, + BCM47XX_BOARD_LINKSYS_E1000V1, + BCM47XX_BOARD_LINKSYS_E1000V2, + BCM47XX_BOARD_LINKSYS_E1000V21, + BCM47XX_BOARD_LINKSYS_E1200V2, + BCM47XX_BOARD_LINKSYS_E2000V1, + BCM47XX_BOARD_LINKSYS_E3000V1, + BCM47XX_BOARD_LINKSYS_E3200V1, + BCM47XX_BOARD_LINKSYS_E4200V1, + BCM47XX_BOARD_LINKSYS_WRT150NV1, + BCM47XX_BOARD_LINKSYS_WRT150NV11, + BCM47XX_BOARD_LINKSYS_WRT160NV1, + BCM47XX_BOARD_LINKSYS_WRT160NV3, + BCM47XX_BOARD_LINKSYS_WRT300NV11, + BCM47XX_BOARD_LINKSYS_WRT310NV1, + BCM47XX_BOARD_LINKSYS_WRT310NV2, + BCM47XX_BOARD_LINKSYS_WRT54G3GV2, + BCM47XX_BOARD_LINKSYS_WRT54G, + BCM47XX_BOARD_LINKSYS_WRT610NV1, + BCM47XX_BOARD_LINKSYS_WRT610NV2, + BCM47XX_BOARD_LINKSYS_WRTSL54GS, + + BCM47XX_BOARD_MOTOROLA_WE800G, + BCM47XX_BOARD_MOTOROLA_WR850GP, + BCM47XX_BOARD_MOTOROLA_WR850GV2V3, + + BCM47XX_BOARD_NETGEAR_WGR614V8, + BCM47XX_BOARD_NETGEAR_WGR614V9, + BCM47XX_BOARD_NETGEAR_WNDR3300, + BCM47XX_BOARD_NETGEAR_WNDR3400V1, + BCM47XX_BOARD_NETGEAR_WNDR3400V2, + BCM47XX_BOARD_NETGEAR_WNDR3400VCNA, + BCM47XX_BOARD_NETGEAR_WNDR3700V3, + BCM47XX_BOARD_NETGEAR_WNDR4000, + BCM47XX_BOARD_NETGEAR_WNDR4500V1, + BCM47XX_BOARD_NETGEAR_WNDR4500V2, + BCM47XX_BOARD_NETGEAR_WNR2000, + BCM47XX_BOARD_NETGEAR_WNR3500L, + BCM47XX_BOARD_NETGEAR_WNR3500U, + BCM47XX_BOARD_NETGEAR_WNR3500V2, + BCM47XX_BOARD_NETGEAR_WNR3500V2VC, + BCM47XX_BOARD_NETGEAR_WNR834BV2, + + BCM47XX_BOARD_PHICOMM_M1, + + BCM47XX_BOARD_SIEMENS_SE505V2, + + BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE, + + BCM47XX_BOARD_ZTE_H218N, + + BCM47XX_BOARD_UNKNOWN, + BCM47XX_BOARD_NO, +}; + +#define BCM47XX_BOARD_MAX_NAME 30 + +void bcm47xx_board_detect(void); +enum bcm47xx_board bcm47xx_board_get(void); +const char *bcm47xx_board_get_name(void); + +#endif /* __BCM47XX_BOARD_H */ diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h index 69ef3efe06e..36a3fc1aa3a 100644 --- a/arch/mips/include/asm/mach-bcm47xx/nvram.h +++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h @@ -8,8 +8,8 @@ * option) any later version. */ -#ifndef __NVRAM_H -#define __NVRAM_H +#ifndef __BCM47XX_NVRAM_H +#define __BCM47XX_NVRAM_H #include <linux/types.h> #include <linux/kernel.h> @@ -32,12 +32,9 @@ struct nvram_header { #define NVRAM_MAX_VALUE_LEN 255 #define NVRAM_MAX_PARAM_LEN 64 -#define NVRAM_ERR_INV_PARAM -8 -#define NVRAM_ERR_ENVNOTFOUND -9 +extern int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len); -extern int nvram_getenv(char *name, char *val, size_t val_len); - -static inline void nvram_parse_macaddr(char *buf, u8 macaddr[6]) +static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6]) { if (strchr(buf, ':')) sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], @@ -51,4 +48,6 @@ static inline void nvram_parse_macaddr(char *buf, u8 macaddr[6]) printk(KERN_WARNING "Can not parse mac address: %s\n", buf); } -#endif +int bcm47xx_nvram_gpio_pin(const char *name); + +#endif /* __BCM47XX_NVRAM_H */ diff --git a/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h new file mode 100644 index 00000000000..b7992cd4aaf --- /dev/null +++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h @@ -0,0 +1,82 @@ +#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB) +#define cpu_has_watch 1 +#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA) +#define cpu_has_watch 0 +#endif +#define cpu_has_divec 1 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 +#define cpu_has_mcheck 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +/* cpu_has_mips16 */ +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_rixi 0 +#define cpu_has_mmips 0 +#define cpu_has_smartmips 0 +#define cpu_has_vtag_icache 0 +/* cpu_has_dc_aliases */ +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_pindexed_dcache 0 +#define cpu_icache_snoops_remote_store 0 + +#define cpu_has_mips_2 1 +#define cpu_has_mips_3 0 +#define cpu_has_mips32r1 1 +#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB) +#define cpu_has_mips32r2 1 +#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA) +#define cpu_has_mips32r2 0 +#endif +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB) +#define cpu_has_dsp 1 +#define cpu_has_dsp2 1 +#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA) +#define cpu_has_dsp 0 +#define cpu_has_dsp2 0 +#endif +#define cpu_has_mipsmt 0 +/* cpu_has_userlocal */ + +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB) +#define cpu_has_vint 1 +#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA) +#define cpu_has_vint 0 +#endif +#define cpu_has_veic 0 +#define cpu_has_inclusive_pcaches 0 + +#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB) +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 +#define cpu_has_perf_cntr_intr_bit 1 +#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA) +#define cpu_dcache_line_size() 16 +#define cpu_icache_line_size() 16 +#define cpu_has_perf_cntr_intr_bit 0 +#endif +#define cpu_scache_line_size() 0 +#define cpu_has_vz 0 + +#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h deleted file mode 100644 index 8fcf8df4418..00000000000 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef BCM63XX_CLK_H_ -#define BCM63XX_CLK_H_ - -struct clk { - void (*set)(struct clk *, int); - unsigned int rate; - unsigned int usage; - int id; -}; - -#endif /* ! BCM63XX_CLK_H_ */ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index dbd5b5ad07a..3112f08f0c7 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -9,18 +9,33 @@ * compile time if only one CPU support is enabled (idea stolen from * arm mach-types) */ +#define BCM3368_CPU_ID 0x3368 #define BCM6328_CPU_ID 0x6328 #define BCM6338_CPU_ID 0x6338 #define BCM6345_CPU_ID 0x6345 #define BCM6348_CPU_ID 0x6348 #define BCM6358_CPU_ID 0x6358 +#define BCM6362_CPU_ID 0x6362 #define BCM6368_CPU_ID 0x6368 void __init bcm63xx_cpu_init(void); u16 __bcm63xx_get_cpu_id(void); -u16 bcm63xx_get_cpu_rev(void); +u8 bcm63xx_get_cpu_rev(void); unsigned int bcm63xx_get_cpu_freq(void); +#ifdef CONFIG_BCM63XX_CPU_3368 +# ifdef bcm63xx_get_cpu_id +# undef bcm63xx_get_cpu_id +# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +# define BCMCPU_RUNTIME_DETECT +# else +# define bcm63xx_get_cpu_id() BCM3368_CPU_ID +# endif +# define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID) +#else +# define BCMCPU_IS_3368() (0) +#endif + #ifdef CONFIG_BCM63XX_CPU_6328 # ifdef bcm63xx_get_cpu_id # undef bcm63xx_get_cpu_id @@ -86,6 +101,20 @@ unsigned int bcm63xx_get_cpu_freq(void); # define BCMCPU_IS_6358() (0) #endif +#ifdef CONFIG_BCM63XX_CPU_6362 +# ifdef bcm63xx_get_cpu_id +# undef bcm63xx_get_cpu_id +# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +# define BCMCPU_RUNTIME_DETECT +# else +# define bcm63xx_get_cpu_id() BCM6362_CPU_ID +# endif +# define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) +#else +# define BCMCPU_IS_6362() (0) +#endif + + #ifdef CONFIG_BCM63XX_CPU_6368 # ifdef bcm63xx_get_cpu_id # undef bcm63xx_get_cpu_id @@ -116,6 +145,7 @@ enum bcm63xx_regs_set { RSET_UART1, RSET_GPIO, RSET_SPI, + RSET_HSSPI, RSET_UDC0, RSET_OHCI0, RSET_OHCI_PRIV, @@ -158,9 +188,13 @@ enum bcm63xx_regs_set { #define BCM_6358_RSET_SPI_SIZE 1804 #define BCM_6368_RSET_SPI_SIZE 1804 #define RSET_ENET_SIZE 2048 -#define RSET_ENETDMA_SIZE 2048 +#define RSET_ENETDMA_SIZE 256 +#define RSET_6345_ENETDMA_SIZE 64 +#define RSET_ENETDMAC_SIZE(chans) (16 * (chans)) +#define RSET_ENETDMAS_SIZE(chans) (16 * (chans)) #define RSET_ENETSW_SIZE 65536 #define RSET_UART_SIZE 24 +#define RSET_HSSPI_SIZE 1536 #define RSET_UDC_SIZE 256 #define RSET_OHCI_SIZE 256 #define RSET_EHCI_SIZE 256 @@ -176,16 +210,64 @@ enum bcm63xx_regs_set { #define RSET_RNG_SIZE 20 /* + * 3368 register sets base address + */ +#define BCM_3368_DSL_LMEM_BASE (0xdeadbeef) +#define BCM_3368_PERF_BASE (0xfff8c000) +#define BCM_3368_TIMER_BASE (0xfff8c040) +#define BCM_3368_WDT_BASE (0xfff8c080) +#define BCM_3368_UART0_BASE (0xfff8c100) +#define BCM_3368_UART1_BASE (0xfff8c120) +#define BCM_3368_GPIO_BASE (0xfff8c080) +#define BCM_3368_SPI_BASE (0xfff8c800) +#define BCM_3368_HSSPI_BASE (0xdeadbeef) +#define BCM_3368_UDC0_BASE (0xdeadbeef) +#define BCM_3368_USBDMA_BASE (0xdeadbeef) +#define BCM_3368_OHCI0_BASE (0xdeadbeef) +#define BCM_3368_OHCI_PRIV_BASE (0xdeadbeef) +#define BCM_3368_USBH_PRIV_BASE (0xdeadbeef) +#define BCM_3368_USBD_BASE (0xdeadbeef) +#define BCM_3368_MPI_BASE (0xfff80000) +#define BCM_3368_PCMCIA_BASE (0xfff80054) +#define BCM_3368_PCIE_BASE (0xdeadbeef) +#define BCM_3368_SDRAM_REGS_BASE (0xdeadbeef) +#define BCM_3368_DSL_BASE (0xdeadbeef) +#define BCM_3368_UBUS_BASE (0xdeadbeef) +#define BCM_3368_ENET0_BASE (0xfff98000) +#define BCM_3368_ENET1_BASE (0xfff98800) +#define BCM_3368_ENETDMA_BASE (0xfff99800) +#define BCM_3368_ENETDMAC_BASE (0xfff99900) +#define BCM_3368_ENETDMAS_BASE (0xfff99a00) +#define BCM_3368_ENETSW_BASE (0xdeadbeef) +#define BCM_3368_EHCI0_BASE (0xdeadbeef) +#define BCM_3368_SDRAM_BASE (0xdeadbeef) +#define BCM_3368_MEMC_BASE (0xfff84000) +#define BCM_3368_DDR_BASE (0xdeadbeef) +#define BCM_3368_M2M_BASE (0xdeadbeef) +#define BCM_3368_ATM_BASE (0xdeadbeef) +#define BCM_3368_XTM_BASE (0xdeadbeef) +#define BCM_3368_XTMDMA_BASE (0xdeadbeef) +#define BCM_3368_XTMDMAC_BASE (0xdeadbeef) +#define BCM_3368_XTMDMAS_BASE (0xdeadbeef) +#define BCM_3368_PCM_BASE (0xfff9c200) +#define BCM_3368_PCMDMA_BASE (0xdeadbeef) +#define BCM_3368_PCMDMAC_BASE (0xdeadbeef) +#define BCM_3368_PCMDMAS_BASE (0xdeadbeef) +#define BCM_3368_RNG_BASE (0xdeadbeef) +#define BCM_3368_MISC_BASE (0xdeadbeef) + +/* * 6328 register sets base address */ #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef) #define BCM_6328_PERF_BASE (0xb0000000) #define BCM_6328_TIMER_BASE (0xb0000040) #define BCM_6328_WDT_BASE (0xb000005c) -#define BCM_6328_UART0_BASE (0xb0000100) +#define BCM_6328_UART0_BASE (0xb0000100) #define BCM_6328_UART1_BASE (0xb0000120) #define BCM_6328_GPIO_BASE (0xb0000080) #define BCM_6328_SPI_BASE (0xdeadbeef) +#define BCM_6328_HSSPI_BASE (0xb0001000) #define BCM_6328_UDC0_BASE (0xdeadbeef) #define BCM_6328_USBDMA_BASE (0xb000c000) #define BCM_6328_OHCI0_BASE (0xb0002600) @@ -220,6 +302,8 @@ enum bcm63xx_regs_set { #define BCM_6328_PCMDMAS_BASE (0xdeadbeef) #define BCM_6328_RNG_BASE (0xdeadbeef) #define BCM_6328_MISC_BASE (0xb0001800) +#define BCM_6328_OTP_BASE (0xb0000600) + /* * 6338 register sets base address */ @@ -232,6 +316,7 @@ enum bcm63xx_regs_set { #define BCM_6338_UART1_BASE (0xdeadbeef) #define BCM_6338_GPIO_BASE (0xfffe0400) #define BCM_6338_SPI_BASE (0xfffe0c00) +#define BCM_6338_HSSPI_BASE (0xdeadbeef) #define BCM_6338_UDC0_BASE (0xdeadbeef) #define BCM_6338_USBDMA_BASE (0xfffe2400) #define BCM_6338_OHCI0_BASE (0xdeadbeef) @@ -279,11 +364,12 @@ enum bcm63xx_regs_set { #define BCM_6345_UART1_BASE (0xdeadbeef) #define BCM_6345_GPIO_BASE (0xfffe0400) #define BCM_6345_SPI_BASE (0xdeadbeef) +#define BCM_6345_HSSPI_BASE (0xdeadbeef) #define BCM_6345_UDC0_BASE (0xdeadbeef) #define BCM_6345_USBDMA_BASE (0xfffe2800) #define BCM_6345_ENET0_BASE (0xfffe1800) #define BCM_6345_ENETDMA_BASE (0xfffe2800) -#define BCM_6345_ENETDMAC_BASE (0xfffe2900) +#define BCM_6345_ENETDMAC_BASE (0xfffe2840) #define BCM_6345_ENETDMAS_BASE (0xfffe2a00) #define BCM_6345_ENETSW_BASE (0xdeadbeef) #define BCM_6345_PCMCIA_BASE (0xfffe2028) @@ -325,6 +411,7 @@ enum bcm63xx_regs_set { #define BCM_6348_UART1_BASE (0xdeadbeef) #define BCM_6348_GPIO_BASE (0xfffe0400) #define BCM_6348_SPI_BASE (0xfffe0c00) +#define BCM_6348_HSSPI_BASE (0xdeadbeef) #define BCM_6348_UDC0_BASE (0xfffe1000) #define BCM_6348_USBDMA_BASE (0xdeadbeef) #define BCM_6348_OHCI0_BASE (0xfffe1b00) @@ -370,6 +457,7 @@ enum bcm63xx_regs_set { #define BCM_6358_UART1_BASE (0xfffe0120) #define BCM_6358_GPIO_BASE (0xfffe0080) #define BCM_6358_SPI_BASE (0xfffe0800) +#define BCM_6358_HSSPI_BASE (0xdeadbeef) #define BCM_6358_UDC0_BASE (0xfffe0800) #define BCM_6358_USBDMA_BASE (0xdeadbeef) #define BCM_6358_OHCI0_BASE (0xfffe1400) @@ -406,6 +494,62 @@ enum bcm63xx_regs_set { /* + * 6362 register sets base address + */ +#define BCM_6362_DSL_LMEM_BASE (0xdeadbeef) +#define BCM_6362_PERF_BASE (0xb0000000) +#define BCM_6362_TIMER_BASE (0xb0000040) +#define BCM_6362_WDT_BASE (0xb000005c) +#define BCM_6362_UART0_BASE (0xb0000100) +#define BCM_6362_UART1_BASE (0xb0000120) +#define BCM_6362_GPIO_BASE (0xb0000080) +#define BCM_6362_SPI_BASE (0xb0000800) +#define BCM_6362_HSSPI_BASE (0xb0001000) +#define BCM_6362_UDC0_BASE (0xdeadbeef) +#define BCM_6362_USBDMA_BASE (0xb000c000) +#define BCM_6362_OHCI0_BASE (0xb0002600) +#define BCM_6362_OHCI_PRIV_BASE (0xdeadbeef) +#define BCM_6362_USBH_PRIV_BASE (0xb0002700) +#define BCM_6362_USBD_BASE (0xb0002400) +#define BCM_6362_MPI_BASE (0xdeadbeef) +#define BCM_6362_PCMCIA_BASE (0xdeadbeef) +#define BCM_6362_PCIE_BASE (0xb0e40000) +#define BCM_6362_SDRAM_REGS_BASE (0xdeadbeef) +#define BCM_6362_DSL_BASE (0xdeadbeef) +#define BCM_6362_UBUS_BASE (0xdeadbeef) +#define BCM_6362_ENET0_BASE (0xdeadbeef) +#define BCM_6362_ENET1_BASE (0xdeadbeef) +#define BCM_6362_ENETDMA_BASE (0xb000d800) +#define BCM_6362_ENETDMAC_BASE (0xb000da00) +#define BCM_6362_ENETDMAS_BASE (0xb000dc00) +#define BCM_6362_ENETSW_BASE (0xb0e00000) +#define BCM_6362_EHCI0_BASE (0xb0002500) +#define BCM_6362_SDRAM_BASE (0xdeadbeef) +#define BCM_6362_MEMC_BASE (0xdeadbeef) +#define BCM_6362_DDR_BASE (0xb0003000) +#define BCM_6362_M2M_BASE (0xdeadbeef) +#define BCM_6362_ATM_BASE (0xdeadbeef) +#define BCM_6362_XTM_BASE (0xb0007800) +#define BCM_6362_XTMDMA_BASE (0xb000b800) +#define BCM_6362_XTMDMAC_BASE (0xdeadbeef) +#define BCM_6362_XTMDMAS_BASE (0xdeadbeef) +#define BCM_6362_PCM_BASE (0xb000a800) +#define BCM_6362_PCMDMA_BASE (0xdeadbeef) +#define BCM_6362_PCMDMAC_BASE (0xdeadbeef) +#define BCM_6362_PCMDMAS_BASE (0xdeadbeef) +#define BCM_6362_RNG_BASE (0xdeadbeef) +#define BCM_6362_MISC_BASE (0xb0001800) + +#define BCM_6362_NAND_REG_BASE (0xb0000200) +#define BCM_6362_NAND_CACHE_BASE (0xb0000600) +#define BCM_6362_LED_BASE (0xb0001900) +#define BCM_6362_IPSEC_BASE (0xb0002800) +#define BCM_6362_IPSEC_DMA_BASE (0xb000d000) +#define BCM_6362_WLAN_CHIPCOMMON_BASE (0xb0004000) +#define BCM_6362_WLAN_D11_BASE (0xb0005000) +#define BCM_6362_WLAN_SHIM_BASE (0xb0007000) + +/* * 6368 register sets base address */ #define BCM_6368_DSL_LMEM_BASE (0xdeadbeef) @@ -416,6 +560,7 @@ enum bcm63xx_regs_set { #define BCM_6368_UART1_BASE (0xb0000120) #define BCM_6368_GPIO_BASE (0xb0000080) #define BCM_6368_SPI_BASE (0xb0000800) +#define BCM_6368_HSSPI_BASE (0xdeadbeef) #define BCM_6368_UDC0_BASE (0xdeadbeef) #define BCM_6368_USBDMA_BASE (0xb0004800) #define BCM_6368_OHCI0_BASE (0xb0001600) @@ -467,6 +612,7 @@ extern const unsigned long *bcm63xx_regs_base; __GEN_RSET_BASE(__cpu, UART1) \ __GEN_RSET_BASE(__cpu, GPIO) \ __GEN_RSET_BASE(__cpu, SPI) \ + __GEN_RSET_BASE(__cpu, HSSPI) \ __GEN_RSET_BASE(__cpu, UDC0) \ __GEN_RSET_BASE(__cpu, OHCI0) \ __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ @@ -510,6 +656,7 @@ extern const unsigned long *bcm63xx_regs_base; [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ + [RSET_HSSPI] = BCM_## __cpu ##_HSSPI_BASE, \ [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ @@ -549,6 +696,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) #ifdef BCMCPU_RUNTIME_DETECT return bcm63xx_regs_base[set]; #else +#ifdef CONFIG_BCM63XX_CPU_3368 + __GEN_RSET(3368) +#endif #ifdef CONFIG_BCM63XX_CPU_6328 __GEN_RSET(6328) #endif @@ -564,6 +714,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) #ifdef CONFIG_BCM63XX_CPU_6358 __GEN_RSET(6358) #endif +#ifdef CONFIG_BCM63XX_CPU_6362 + __GEN_RSET(6362) +#endif #ifdef CONFIG_BCM63XX_CPU_6368 __GEN_RSET(6368) #endif @@ -584,6 +737,7 @@ enum bcm63xx_irq { IRQ_ENET0, IRQ_ENET1, IRQ_ENET_PHY, + IRQ_HSSPI, IRQ_OHCI0, IRQ_EHCI0, IRQ_USBD, @@ -613,6 +767,52 @@ enum bcm63xx_irq { }; /* + * 3368 irqs + */ +#define BCM_3368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) +#define BCM_3368_SPI_IRQ (IRQ_INTERNAL_BASE + 1) +#define BCM_3368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) +#define BCM_3368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) +#define BCM_3368_DSL_IRQ 0 +#define BCM_3368_UDC0_IRQ 0 +#define BCM_3368_OHCI0_IRQ 0 +#define BCM_3368_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_3368_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) +#define BCM_3368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) +#define BCM_3368_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) +#define BCM_3368_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) +#define BCM_3368_HSSPI_IRQ 0 +#define BCM_3368_EHCI0_IRQ 0 +#define BCM_3368_USBD_IRQ 0 +#define BCM_3368_USBD_RXDMA0_IRQ 0 +#define BCM_3368_USBD_TXDMA0_IRQ 0 +#define BCM_3368_USBD_RXDMA1_IRQ 0 +#define BCM_3368_USBD_TXDMA1_IRQ 0 +#define BCM_3368_USBD_RXDMA2_IRQ 0 +#define BCM_3368_USBD_TXDMA2_IRQ 0 +#define BCM_3368_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) +#define BCM_3368_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) +#define BCM_3368_PCI_IRQ (IRQ_INTERNAL_BASE + 31) +#define BCM_3368_PCMCIA_IRQ 0 +#define BCM_3368_ATM_IRQ 0 +#define BCM_3368_ENETSW_RXDMA0_IRQ 0 +#define BCM_3368_ENETSW_RXDMA1_IRQ 0 +#define BCM_3368_ENETSW_RXDMA2_IRQ 0 +#define BCM_3368_ENETSW_RXDMA3_IRQ 0 +#define BCM_3368_ENETSW_TXDMA0_IRQ 0 +#define BCM_3368_ENETSW_TXDMA1_IRQ 0 +#define BCM_3368_ENETSW_TXDMA2_IRQ 0 +#define BCM_3368_ENETSW_TXDMA3_IRQ 0 +#define BCM_3368_XTM_IRQ 0 +#define BCM_3368_XTM_DMA0_IRQ 0 + +#define BCM_3368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25) +#define BCM_3368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26) +#define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) +#define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) + + +/* * 6328 irqs */ #define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) @@ -626,6 +826,7 @@ enum bcm63xx_irq { #define BCM_6328_ENET0_IRQ 0 #define BCM_6328_ENET1_IRQ 0 #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) +#define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29) #define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9) #define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10) #define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4) @@ -671,6 +872,7 @@ enum bcm63xx_irq { #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) #define BCM_6338_ENET1_IRQ 0 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) +#define BCM_6338_HSSPI_IRQ 0 #define BCM_6338_OHCI0_IRQ 0 #define BCM_6338_EHCI0_IRQ 0 #define BCM_6338_USBD_IRQ 0 @@ -709,6 +911,7 @@ enum bcm63xx_irq { #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) #define BCM_6345_ENET1_IRQ 0 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) +#define BCM_6345_HSSPI_IRQ 0 #define BCM_6345_OHCI0_IRQ 0 #define BCM_6345_EHCI0_IRQ 0 #define BCM_6345_USBD_IRQ 0 @@ -747,6 +950,7 @@ enum bcm63xx_irq { #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) +#define BCM_6348_HSSPI_IRQ 0 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) #define BCM_6348_EHCI0_IRQ 0 #define BCM_6348_USBD_IRQ 0 @@ -785,6 +989,7 @@ enum bcm63xx_irq { #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) +#define BCM_6358_HSSPI_IRQ 0 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) #define BCM_6358_USBD_IRQ 0 @@ -820,6 +1025,71 @@ enum bcm63xx_irq { #define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) /* + * 6362 irqs + */ +#define BCM_6362_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) + +#define BCM_6362_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) +#define BCM_6362_SPI_IRQ (IRQ_INTERNAL_BASE + 2) +#define BCM_6362_UART0_IRQ (IRQ_INTERNAL_BASE + 3) +#define BCM_6362_UART1_IRQ (IRQ_INTERNAL_BASE + 4) +#define BCM_6362_DSL_IRQ (IRQ_INTERNAL_BASE + 28) +#define BCM_6362_UDC0_IRQ 0 +#define BCM_6362_ENET0_IRQ 0 +#define BCM_6362_ENET1_IRQ 0 +#define BCM_6362_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 14) +#define BCM_6362_HSSPI_IRQ (IRQ_INTERNAL_BASE + 5) +#define BCM_6362_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) +#define BCM_6362_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) +#define BCM_6362_USBD_IRQ (IRQ_INTERNAL_BASE + 11) +#define BCM_6362_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 20) +#define BCM_6362_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 21) +#define BCM_6362_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 22) +#define BCM_6362_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 23) +#define BCM_6362_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 24) +#define BCM_6362_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 25) +#define BCM_6362_PCMCIA_IRQ 0 +#define BCM_6362_ENET0_RXDMA_IRQ 0 +#define BCM_6362_ENET0_TXDMA_IRQ 0 +#define BCM_6362_ENET1_RXDMA_IRQ 0 +#define BCM_6362_ENET1_TXDMA_IRQ 0 +#define BCM_6362_PCI_IRQ (IRQ_INTERNAL_BASE + 30) +#define BCM_6362_ATM_IRQ 0 +#define BCM_6362_ENETSW_RXDMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 0) +#define BCM_6362_ENETSW_RXDMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 1) +#define BCM_6362_ENETSW_RXDMA2_IRQ (BCM_6362_HIGH_IRQ_BASE + 2) +#define BCM_6362_ENETSW_RXDMA3_IRQ (BCM_6362_HIGH_IRQ_BASE + 3) +#define BCM_6362_ENETSW_TXDMA0_IRQ 0 +#define BCM_6362_ENETSW_TXDMA1_IRQ 0 +#define BCM_6362_ENETSW_TXDMA2_IRQ 0 +#define BCM_6362_ENETSW_TXDMA3_IRQ 0 +#define BCM_6362_XTM_IRQ 0 +#define BCM_6362_XTM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 12) + +#define BCM_6362_RING_OSC_IRQ (IRQ_INTERNAL_BASE + 1) +#define BCM_6362_WLAN_GPIO_IRQ (IRQ_INTERNAL_BASE + 6) +#define BCM_6362_WLAN_IRQ (IRQ_INTERNAL_BASE + 7) +#define BCM_6362_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_6362_NAND_IRQ (IRQ_INTERNAL_BASE + 12) +#define BCM_6362_PCM_IRQ (IRQ_INTERNAL_BASE + 13) +#define BCM_6362_DG_IRQ (IRQ_INTERNAL_BASE + 15) +#define BCM_6362_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16) +#define BCM_6362_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17) +#define BCM_6362_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18) +#define BCM_6362_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19) +#define BCM_6362_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 26) +#define BCM_6362_IPSEC_DMA1_IRQ (IRQ_INTERNAL_BASE + 27) +#define BCM_6362_FAP0_IRQ (IRQ_INTERNAL_BASE + 29) +#define BCM_6362_PCM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 4) +#define BCM_6362_PCM_DMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 5) +#define BCM_6362_DECT0_IRQ (BCM_6362_HIGH_IRQ_BASE + 6) +#define BCM_6362_DECT1_IRQ (BCM_6362_HIGH_IRQ_BASE + 7) +#define BCM_6362_EXT_IRQ0 (BCM_6362_HIGH_IRQ_BASE + 8) +#define BCM_6362_EXT_IRQ1 (BCM_6362_HIGH_IRQ_BASE + 9) +#define BCM_6362_EXT_IRQ2 (BCM_6362_HIGH_IRQ_BASE + 10) +#define BCM_6362_EXT_IRQ3 (BCM_6362_HIGH_IRQ_BASE + 11) + +/* * 6368 irqs */ #define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) @@ -832,6 +1102,7 @@ enum bcm63xx_irq { #define BCM_6368_ENET0_IRQ 0 #define BCM_6368_ENET1_IRQ 0 #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) +#define BCM_6368_HSSPI_IRQ 0 #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) #define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8) @@ -879,6 +1150,7 @@ extern const int *bcm63xx_irqs; [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \ [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \ [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ + [IRQ_HSSPI] = BCM_## __cpu ##_HSSPI_IRQ, \ [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h index d53f611184b..753953e8624 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h @@ -4,6 +4,8 @@ #include <linux/if_ether.h> #include <linux/init.h> +#include <bcm63xx_regs.h> + /* * on board ethernet platform data */ @@ -37,9 +39,129 @@ struct bcm63xx_enet_platform_data { int phy_id, int reg), void (*mii_write)(struct net_device *dev, int phy_id, int reg, int val)); + + /* DMA channel enable mask */ + u32 dma_chan_en_mask; + + /* DMA channel interrupt mask */ + u32 dma_chan_int_mask; + + /* DMA engine has internal SRAM */ + bool dma_has_sram; + + /* DMA channel register width */ + unsigned int dma_chan_width; + + /* DMA descriptor shift */ + unsigned int dma_desc_shift; +}; + +/* + * on board ethernet switch platform data + */ +#define ENETSW_MAX_PORT 8 +#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */ +#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */ + +#define ENETSW_RGMII_PORT0 4 + +struct bcm63xx_enetsw_port { + int used; + int phy_id; + + int bypass_link; + int force_speed; + int force_duplex_full; + + const char *name; +}; + +struct bcm63xx_enetsw_platform_data { + char mac_addr[ETH_ALEN]; + int num_ports; + struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT]; + + /* DMA channel enable mask */ + u32 dma_chan_en_mask; + + /* DMA channel interrupt mask */ + u32 dma_chan_int_mask; + + /* DMA channel register width */ + unsigned int dma_chan_width; + + /* DMA engine has internal SRAM */ + bool dma_has_sram; }; int __init bcm63xx_enet_register(int unit, const struct bcm63xx_enet_platform_data *pd); +int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd); + +enum bcm63xx_regs_enetdmac { + ENETDMAC_CHANCFG, + ENETDMAC_IR, + ENETDMAC_IRMASK, + ENETDMAC_MAXBURST, + ENETDMAC_BUFALLOC, + ENETDMAC_RSTART, + ENETDMAC_FC, + ENETDMAC_LEN, +}; + +static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg) +{ +#ifdef BCMCPU_RUNTIME_DETECT + extern const unsigned long *bcm63xx_regs_enetdmac; + + return bcm63xx_regs_enetdmac[reg]; +#else +#ifdef CONFIG_BCM63XX_CPU_6345 + switch (reg) { + case ENETDMAC_CHANCFG: + return ENETDMA_6345_CHANCFG_REG; + case ENETDMAC_IR: + return ENETDMA_6345_IR_REG; + case ENETDMAC_IRMASK: + return ENETDMA_6345_IRMASK_REG; + case ENETDMAC_MAXBURST: + return ENETDMA_6345_MAXBURST_REG; + case ENETDMAC_BUFALLOC: + return ENETDMA_6345_BUFALLOC_REG; + case ENETDMAC_RSTART: + return ENETDMA_6345_RSTART_REG; + case ENETDMAC_FC: + return ENETDMA_6345_FC_REG; + case ENETDMAC_LEN: + return ENETDMA_6345_LEN_REG; + } +#endif +#if defined(CONFIG_BCM63XX_CPU_6328) || \ + defined(CONFIG_BCM63XX_CPU_6338) || \ + defined(CONFIG_BCM63XX_CPU_6348) || \ + defined(CONFIG_BCM63XX_CPU_6358) || \ + defined(CONFIG_BCM63XX_CPU_6362) || \ + defined(CONFIG_BCM63XX_CPU_6368) + switch (reg) { + case ENETDMAC_CHANCFG: + return ENETDMAC_CHANCFG_REG; + case ENETDMAC_IR: + return ENETDMAC_IR_REG; + case ENETDMAC_IRMASK: + return ENETDMAC_IRMASK_REG; + case ENETDMAC_MAXBURST: + return ENETDMAC_MAXBURST_REG; + case ENETDMAC_BUFALLOC: + case ENETDMAC_RSTART: + case ENETDMAC_FC: + case ENETDMAC_LEN: + return 0; + } +#endif +#endif + return 0; +} + + #endif /* ! BCM63XX_DEV_ENET_H_ */ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h new file mode 100644 index 00000000000..1b1acafb3d7 --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h @@ -0,0 +1,8 @@ +#ifndef BCM63XX_DEV_HSSPI_H +#define BCM63XX_DEV_HSSPI_H + +#include <linux/types.h> + +int bcm63xx_hsspi_register(void); + +#endif /* BCM63XX_DEV_HSSPI_H */ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h index c9bae136260..c426cabc620 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h @@ -13,7 +13,6 @@ struct bcm63xx_spi_pdata { unsigned int msg_ctl_width; int bus_num; int num_chipselect; - u32 speed_hz; }; enum bcm63xx_regs_spi { @@ -72,18 +71,13 @@ static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg) return bcm63xx_regs_spi[reg]; #else -#ifdef CONFIG_BCM63XX_CPU_6338 - __GEN_SPI_RSET(6338) -#endif -#ifdef CONFIG_BCM63XX_CPU_6348 +#if defined(CONFIG_BCM63XX_CPU_6338) || defined(CONFIG_BCM63XX_CPU_6348) __GEN_SPI_RSET(6348) #endif -#ifdef CONFIG_BCM63XX_CPU_6358 +#if defined(CONFIG_BCM63XX_CPU_6358) || defined(CONFIG_BCM63XX_CPU_6362) || \ + defined(CONFIG_BCM63XX_CPU_6368) __GEN_SPI_RSET(6358) #endif -#ifdef CONFIG_BCM63XX_CPU_6368 - __GEN_SPI_RSET(6368) -#endif #endif return 0; } diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h index 0a9891f7580..565ff36a111 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h @@ -11,12 +11,15 @@ static inline unsigned long bcm63xx_gpio_count(void) switch (bcm63xx_get_cpu_id()) { case BCM6328_CPU_ID: return 32; + case BCM3368_CPU_ID: case BCM6358_CPU_ID: return 40; case BCM6338_CPU_ID: return 8; case BCM6345_CPU_ID: return 16; + case BCM6362_CPU_ID: + return 48; case BCM6368_CPU_ID: return 38; case BCM6348_CPU_ID: diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h index 03a54df5fb8..7033144aab2 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h @@ -88,7 +88,7 @@ #define bcm_mpi_readl(o) bcm_rset_readl(RSET_MPI, (o)) #define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o)) #define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o)) -#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o)) +#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o)) #define bcm_pcie_readl(o) bcm_rset_readl(RSET_PCIE, (o)) #define bcm_pcie_writel(v, o) bcm_rset_writel(RSET_PCIE, (v), (o)) #define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o)) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h index a5bbff31c89..1e89df7244b 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h @@ -19,7 +19,7 @@ struct bcm_enet_desc { #define DMADESC_SOP_MASK (1 << 13) #define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK) #define DMADESC_WRAP_MASK (1 << 12) -#define DMADESC_USB_NOZERO_MASK (1 << 1) +#define DMADESC_USB_NOZERO_MASK (1 << 1) #define DMADESC_USB_ZERO_MASK (1 << 0) /* status */ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h index 62d6a3b4d3b..348df49dcc9 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h @@ -9,10 +9,8 @@ * * Initialized the local nvram copy from the target address and checks * its checksum. - * - * Returns 0 on success. */ -int __init bcm63xx_nvram_init(void *nvram); +void bcm63xx_nvram_init(void *nvram); /** * bcm63xx_nvram_get_name() - returns the board name according to nvram @@ -32,4 +30,6 @@ u8 *bcm63xx_nvram_get_name(void); */ int bcm63xx_nvram_get_mac_address(u8 *mac); +int bcm63xx_nvram_get_psi_size(void); + #endif /* BCM63XX_NVRAM_H */ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index c3eeb90b480..ab427f8814e 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -10,11 +10,44 @@ #define REV_CHIPID_SHIFT 16 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) #define REV_REVID_SHIFT 0 -#define REV_REVID_MASK (0xffff << REV_REVID_SHIFT) +#define REV_REVID_MASK (0xff << REV_REVID_SHIFT) /* Clock Control register */ #define PERF_CKCTL_REG 0x4 +#define CKCTL_3368_MAC_EN (1 << 3) +#define CKCTL_3368_TC_EN (1 << 5) +#define CKCTL_3368_US_TOP_EN (1 << 6) +#define CKCTL_3368_DS_TOP_EN (1 << 7) +#define CKCTL_3368_APM_EN (1 << 8) +#define CKCTL_3368_SPI_EN (1 << 9) +#define CKCTL_3368_USBS_EN (1 << 10) +#define CKCTL_3368_BMU_EN (1 << 11) +#define CKCTL_3368_PCM_EN (1 << 12) +#define CKCTL_3368_NTP_EN (1 << 13) +#define CKCTL_3368_ACP_B_EN (1 << 14) +#define CKCTL_3368_ACP_A_EN (1 << 15) +#define CKCTL_3368_EMUSB_EN (1 << 17) +#define CKCTL_3368_ENET0_EN (1 << 18) +#define CKCTL_3368_ENET1_EN (1 << 19) +#define CKCTL_3368_USBU_EN (1 << 20) +#define CKCTL_3368_EPHY_EN (1 << 21) + +#define CKCTL_3368_ALL_SAFE_EN (CKCTL_3368_MAC_EN | \ + CKCTL_3368_TC_EN | \ + CKCTL_3368_US_TOP_EN | \ + CKCTL_3368_DS_TOP_EN | \ + CKCTL_3368_APM_EN | \ + CKCTL_3368_SPI_EN | \ + CKCTL_3368_USBS_EN | \ + CKCTL_3368_BMU_EN | \ + CKCTL_3368_PCM_EN | \ + CKCTL_3368_NTP_EN | \ + CKCTL_3368_ACP_B_EN | \ + CKCTL_3368_ACP_A_EN | \ + CKCTL_3368_EMUSB_EN | \ + CKCTL_3368_USBU_EN) + #define CKCTL_6328_PHYMIPS_EN (1 << 0) #define CKCTL_6328_ADSL_QPROC_EN (1 << 1) #define CKCTL_6328_ADSL_AFE_EN (1 << 2) @@ -112,6 +145,39 @@ CKCTL_6358_USBSU_EN | \ CKCTL_6358_EPHY_EN) +#define CKCTL_6362_ADSL_QPROC_EN (1 << 1) +#define CKCTL_6362_ADSL_AFE_EN (1 << 2) +#define CKCTL_6362_ADSL_EN (1 << 3) +#define CKCTL_6362_MIPS_EN (1 << 4) +#define CKCTL_6362_WLAN_OCP_EN (1 << 5) +#define CKCTL_6362_SWPKT_USB_EN (1 << 7) +#define CKCTL_6362_SWPKT_SAR_EN (1 << 8) +#define CKCTL_6362_SAR_EN (1 << 9) +#define CKCTL_6362_ROBOSW_EN (1 << 10) +#define CKCTL_6362_PCM_EN (1 << 11) +#define CKCTL_6362_USBD_EN (1 << 12) +#define CKCTL_6362_USBH_EN (1 << 13) +#define CKCTL_6362_IPSEC_EN (1 << 14) +#define CKCTL_6362_SPI_EN (1 << 15) +#define CKCTL_6362_HSSPI_EN (1 << 16) +#define CKCTL_6362_PCIE_EN (1 << 17) +#define CKCTL_6362_FAP_EN (1 << 18) +#define CKCTL_6362_PHYMIPS_EN (1 << 19) +#define CKCTL_6362_NAND_EN (1 << 20) + +#define CKCTL_6362_ALL_SAFE_EN (CKCTL_6362_PHYMIPS_EN | \ + CKCTL_6362_ADSL_QPROC_EN | \ + CKCTL_6362_ADSL_AFE_EN | \ + CKCTL_6362_ADSL_EN | \ + CKCTL_6362_SAR_EN | \ + CKCTL_6362_PCM_EN | \ + CKCTL_6362_IPSEC_EN | \ + CKCTL_6362_USBD_EN | \ + CKCTL_6362_USBH_EN | \ + CKCTL_6362_ROBOSW_EN | \ + CKCTL_6362_PCIE_EN) + + #define CKCTL_6368_VDSL_QPROC_EN (1 << 2) #define CKCTL_6368_VDSL_AFE_EN (1 << 3) #define CKCTL_6368_VDSL_BONDING_EN (1 << 4) @@ -143,32 +209,38 @@ CKCTL_6368_NAND_EN | \ CKCTL_6368_IPSEC_EN) -/* System PLL Control register */ +/* System PLL Control register */ #define PERF_SYS_PLL_CTL_REG 0x8 #define SYS_PLL_SOFT_RESET 0x1 /* Interrupt Mask register */ +#define PERF_IRQMASK_3368_REG 0xc #define PERF_IRQMASK_6328_REG 0x20 #define PERF_IRQMASK_6338_REG 0xc #define PERF_IRQMASK_6345_REG 0xc #define PERF_IRQMASK_6348_REG 0xc #define PERF_IRQMASK_6358_REG 0xc +#define PERF_IRQMASK_6362_REG 0x20 #define PERF_IRQMASK_6368_REG 0x20 /* Interrupt Status register */ +#define PERF_IRQSTAT_3368_REG 0x10 #define PERF_IRQSTAT_6328_REG 0x28 #define PERF_IRQSTAT_6338_REG 0x10 #define PERF_IRQSTAT_6345_REG 0x10 #define PERF_IRQSTAT_6348_REG 0x10 #define PERF_IRQSTAT_6358_REG 0x10 +#define PERF_IRQSTAT_6362_REG 0x28 #define PERF_IRQSTAT_6368_REG 0x28 /* External Interrupt Configuration register */ +#define PERF_EXTIRQ_CFG_REG_3368 0x14 #define PERF_EXTIRQ_CFG_REG_6328 0x18 #define PERF_EXTIRQ_CFG_REG_6338 0x14 #define PERF_EXTIRQ_CFG_REG_6345 0x14 #define PERF_EXTIRQ_CFG_REG_6348 0x14 #define PERF_EXTIRQ_CFG_REG_6358 0x14 +#define PERF_EXTIRQ_CFG_REG_6362 0x18 #define PERF_EXTIRQ_CFG_REG_6368 0x18 #define PERF_EXTIRQ_CFG_REG2_6368 0x1c @@ -197,8 +269,16 @@ #define PERF_SOFTRESET_REG 0x28 #define PERF_SOFTRESET_6328_REG 0x10 #define PERF_SOFTRESET_6358_REG 0x34 +#define PERF_SOFTRESET_6362_REG 0x10 #define PERF_SOFTRESET_6368_REG 0x10 +#define SOFTRESET_3368_SPI_MASK (1 << 0) +#define SOFTRESET_3368_ENET_MASK (1 << 2) +#define SOFTRESET_3368_MPI_MASK (1 << 3) +#define SOFTRESET_3368_EPHY_MASK (1 << 6) +#define SOFTRESET_3368_USBS_MASK (1 << 11) +#define SOFTRESET_3368_PCM_MASK (1 << 13) + #define SOFTRESET_6328_SPI_MASK (1 << 0) #define SOFTRESET_6328_EPHY_MASK (1 << 1) #define SOFTRESET_6328_SAR_MASK (1 << 2) @@ -219,7 +299,7 @@ #define SOFTRESET_6338_DMAMEM_MASK (1 << 6) #define SOFTRESET_6338_SAR_MASK (1 << 7) #define SOFTRESET_6338_ACLC_MASK (1 << 8) -#define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10) +#define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10) #define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \ SOFTRESET_6338_ENET_MASK | \ SOFTRESET_6338_USBH_MASK | \ @@ -238,7 +318,7 @@ #define SOFTRESET_6348_DMAMEM_MASK (1 << 6) #define SOFTRESET_6348_SAR_MASK (1 << 7) #define SOFTRESET_6348_ACLC_MASK (1 << 8) -#define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10) +#define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10) #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \ SOFTRESET_6348_ENET_MASK | \ @@ -259,6 +339,22 @@ #define SOFTRESET_6358_PCM_MASK (1 << 13) #define SOFTRESET_6358_ADSL_MASK (1 << 14) +#define SOFTRESET_6362_SPI_MASK (1 << 0) +#define SOFTRESET_6362_IPSEC_MASK (1 << 1) +#define SOFTRESET_6362_EPHY_MASK (1 << 2) +#define SOFTRESET_6362_SAR_MASK (1 << 3) +#define SOFTRESET_6362_ENETSW_MASK (1 << 4) +#define SOFTRESET_6362_USBS_MASK (1 << 5) +#define SOFTRESET_6362_USBH_MASK (1 << 6) +#define SOFTRESET_6362_PCM_MASK (1 << 7) +#define SOFTRESET_6362_PCIE_CORE_MASK (1 << 8) +#define SOFTRESET_6362_PCIE_MASK (1 << 9) +#define SOFTRESET_6362_PCIE_EXT_MASK (1 << 10) +#define SOFTRESET_6362_WLAN_SHIM_MASK (1 << 11) +#define SOFTRESET_6362_DDR_PHY_MASK (1 << 12) +#define SOFTRESET_6362_FAP_MASK (1 << 13) +#define SOFTRESET_6362_WLAN_UBUS_MASK (1 << 14) + #define SOFTRESET_6368_SPI_MASK (1 << 0) #define SOFTRESET_6368_MPI_MASK (1 << 3) #define SOFTRESET_6368_EPHY_MASK (1 << 6) @@ -367,126 +463,6 @@ #define WDT_SOFTRESET_REG 0xc /************************************************************************* - * _REG relative to RSET_UARTx - *************************************************************************/ - -/* UART Control Register */ -#define UART_CTL_REG 0x0 -#define UART_CTL_RXTMOUTCNT_SHIFT 0 -#define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT) -#define UART_CTL_RSTTXDN_SHIFT 5 -#define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT) -#define UART_CTL_RSTRXFIFO_SHIFT 6 -#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT) -#define UART_CTL_RSTTXFIFO_SHIFT 7 -#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT) -#define UART_CTL_STOPBITS_SHIFT 8 -#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT) -#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT) -#define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT) -#define UART_CTL_BITSPERSYM_SHIFT 12 -#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT) -#define UART_CTL_XMITBRK_SHIFT 14 -#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT) -#define UART_CTL_RSVD_SHIFT 15 -#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT) -#define UART_CTL_RXPAREVEN_SHIFT 16 -#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT) -#define UART_CTL_RXPAREN_SHIFT 17 -#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT) -#define UART_CTL_TXPAREVEN_SHIFT 18 -#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT) -#define UART_CTL_TXPAREN_SHIFT 18 -#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT) -#define UART_CTL_LOOPBACK_SHIFT 20 -#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT) -#define UART_CTL_RXEN_SHIFT 21 -#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT) -#define UART_CTL_TXEN_SHIFT 22 -#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT) -#define UART_CTL_BRGEN_SHIFT 23 -#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT) - -/* UART Baudword register */ -#define UART_BAUD_REG 0x4 - -/* UART Misc Control register */ -#define UART_MCTL_REG 0x8 -#define UART_MCTL_DTR_SHIFT 0 -#define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT) -#define UART_MCTL_RTS_SHIFT 1 -#define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT) -#define UART_MCTL_RXFIFOTHRESH_SHIFT 8 -#define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT) -#define UART_MCTL_TXFIFOTHRESH_SHIFT 12 -#define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT) -#define UART_MCTL_RXFIFOFILL_SHIFT 16 -#define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT) -#define UART_MCTL_TXFIFOFILL_SHIFT 24 -#define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT) - -/* UART External Input Configuration register */ -#define UART_EXTINP_REG 0xc -#define UART_EXTINP_RI_SHIFT 0 -#define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT) -#define UART_EXTINP_CTS_SHIFT 1 -#define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT) -#define UART_EXTINP_DCD_SHIFT 2 -#define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT) -#define UART_EXTINP_DSR_SHIFT 3 -#define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT) -#define UART_EXTINP_IRSTAT(x) (1 << (x + 4)) -#define UART_EXTINP_IRMASK(x) (1 << (x + 8)) -#define UART_EXTINP_IR_RI 0 -#define UART_EXTINP_IR_CTS 1 -#define UART_EXTINP_IR_DCD 2 -#define UART_EXTINP_IR_DSR 3 -#define UART_EXTINP_RI_NOSENSE_SHIFT 16 -#define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT) -#define UART_EXTINP_CTS_NOSENSE_SHIFT 17 -#define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT) -#define UART_EXTINP_DCD_NOSENSE_SHIFT 18 -#define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT) -#define UART_EXTINP_DSR_NOSENSE_SHIFT 19 -#define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT) - -/* UART Interrupt register */ -#define UART_IR_REG 0x10 -#define UART_IR_MASK(x) (1 << (x + 16)) -#define UART_IR_STAT(x) (1 << (x)) -#define UART_IR_EXTIP 0 -#define UART_IR_TXUNDER 1 -#define UART_IR_TXOVER 2 -#define UART_IR_TXTRESH 3 -#define UART_IR_TXRDLATCH 4 -#define UART_IR_TXEMPTY 5 -#define UART_IR_RXUNDER 6 -#define UART_IR_RXOVER 7 -#define UART_IR_RXTIMEOUT 8 -#define UART_IR_RXFULL 9 -#define UART_IR_RXTHRESH 10 -#define UART_IR_RXNOTEMPTY 11 -#define UART_IR_RXFRAMEERR 12 -#define UART_IR_RXPARERR 13 -#define UART_IR_RXBRK 14 -#define UART_IR_TXDONE 15 - -/* UART Fifo register */ -#define UART_FIFO_REG 0x14 -#define UART_FIFO_VALID_SHIFT 0 -#define UART_FIFO_VALID_MASK 0xff -#define UART_FIFO_FRAMEERR_SHIFT 8 -#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT) -#define UART_FIFO_PARERR_SHIFT 9 -#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT) -#define UART_FIFO_BRKDET_SHIFT 10 -#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT) -#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \ - UART_FIFO_PARERR_MASK | \ - UART_FIFO_BRKDET_MASK) - - -/************************************************************************* * _REG relative to RSET_GPIO *************************************************************************/ @@ -560,7 +536,7 @@ #define GPIO_PINMUX_OTHR_REG 0x24 -#define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12 +#define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12 #define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) #define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) #define GPIO_PINMUX_OTHR_6328_USB_DEV (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) @@ -572,12 +548,12 @@ /* those bits must be kept as read in gpio basemode register*/ #define GPIO_STRAPBUS_REG 0x40 -#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) +#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1) #define STRAPBUS_6368_BOOT_SEL_MASK 0x3 #define STRAPBUS_6368_BOOT_SEL_NAND 0 #define STRAPBUS_6368_BOOT_SEL_SERIAL 1 -#define STRAPBUS_6368_BOOT_SEL_PARALLEL 3 +#define STRAPBUS_6368_BOOT_SEL_PARALLEL 3 /************************************************************************* @@ -674,6 +650,8 @@ /************************************************************************* * _REG relative to RSET_ENETDMA *************************************************************************/ +#define ENETDMA_CHAN_WIDTH 0x10 +#define ENETDMA_6345_CHAN_WIDTH 0x40 /* Controller Configuration Register */ #define ENETDMA_CFG_REG (0x0) @@ -729,31 +707,56 @@ /* State Ram Word 4 */ #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10) +/* Broadcom 6345 ENET DMA definitions */ +#define ENETDMA_6345_CHANCFG_REG (0x00) + +#define ENETDMA_6345_MAXBURST_REG (0x40) + +#define ENETDMA_6345_RSTART_REG (0x08) + +#define ENETDMA_6345_LEN_REG (0x0C) + +#define ENETDMA_6345_IR_REG (0x14) + +#define ENETDMA_6345_IRMASK_REG (0x18) + +#define ENETDMA_6345_FC_REG (0x1C) + +#define ENETDMA_6345_BUFALLOC_REG (0x20) + +/* Shift down for EOP, SOP and WRAP bits */ +#define ENETDMA_6345_DESC_SHIFT (3) /************************************************************************* * _REG relative to RSET_ENETDMAC *************************************************************************/ /* Channel Configuration register */ -#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10) +#define ENETDMAC_CHANCFG_REG (0x0) #define ENETDMAC_CHANCFG_EN_SHIFT 0 #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT) #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1 #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT) #define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2 #define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT) +#define ENETDMAC_CHANCFG_CHAINING_SHIFT 2 +#define ENETDMAC_CHANCFG_CHAINING_MASK (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT) +#define ENETDMAC_CHANCFG_WRAP_EN_SHIFT 3 +#define ENETDMAC_CHANCFG_WRAP_EN_MASK (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT) +#define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT 4 +#define ENETDMAC_CHANCFG_FLOWC_EN_MASK (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT) /* Interrupt Control/Status register */ -#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10) +#define ENETDMAC_IR_REG (0x4) #define ENETDMAC_IR_BUFDONE_MASK (1 << 0) #define ENETDMAC_IR_PKTDONE_MASK (1 << 1) #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2) /* Interrupt Mask register */ -#define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10) +#define ENETDMAC_IRMASK_REG (0x8) /* Maximum Burst Length */ -#define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10) +#define ENETDMAC_MAXBURST_REG (0xc) /************************************************************************* @@ -761,26 +764,76 @@ *************************************************************************/ /* Ring Start Address register */ -#define ENETDMAS_RSTART_REG(x) ((x) * 0x10) +#define ENETDMAS_RSTART_REG (0x0) /* State Ram Word 2 */ -#define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10) +#define ENETDMAS_SRAM2_REG (0x4) /* State Ram Word 3 */ -#define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10) +#define ENETDMAS_SRAM3_REG (0x8) /* State Ram Word 4 */ -#define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10) +#define ENETDMAS_SRAM4_REG (0xc) /************************************************************************* * _REG relative to RSET_ENETSW *************************************************************************/ +/* Port traffic control */ +#define ENETSW_PTCTRL_REG(x) (0x0 + (x)) +#define ENETSW_PTCTRL_RXDIS_MASK (1 << 0) +#define ENETSW_PTCTRL_TXDIS_MASK (1 << 1) + +/* Switch mode register */ +#define ENETSW_SWMODE_REG (0xb) +#define ENETSW_SWMODE_FWD_EN_MASK (1 << 1) + +/* IMP override Register */ +#define ENETSW_IMPOV_REG (0xe) +#define ENETSW_IMPOV_FORCE_MASK (1 << 7) +#define ENETSW_IMPOV_TXFLOW_MASK (1 << 5) +#define ENETSW_IMPOV_RXFLOW_MASK (1 << 4) +#define ENETSW_IMPOV_1000_MASK (1 << 3) +#define ENETSW_IMPOV_100_MASK (1 << 2) +#define ENETSW_IMPOV_FDX_MASK (1 << 1) +#define ENETSW_IMPOV_LINKUP_MASK (1 << 0) + +/* Port override Register */ +#define ENETSW_PORTOV_REG(x) (0x58 + (x)) +#define ENETSW_PORTOV_ENABLE_MASK (1 << 6) +#define ENETSW_PORTOV_TXFLOW_MASK (1 << 5) +#define ENETSW_PORTOV_RXFLOW_MASK (1 << 4) +#define ENETSW_PORTOV_1000_MASK (1 << 3) +#define ENETSW_PORTOV_100_MASK (1 << 2) +#define ENETSW_PORTOV_FDX_MASK (1 << 1) +#define ENETSW_PORTOV_LINKUP_MASK (1 << 0) + +/* MDIO control register */ +#define ENETSW_MDIOC_REG (0xb0) +#define ENETSW_MDIOC_EXT_MASK (1 << 16) +#define ENETSW_MDIOC_REG_SHIFT 20 +#define ENETSW_MDIOC_PHYID_SHIFT 25 +#define ENETSW_MDIOC_RD_MASK (1 << 30) +#define ENETSW_MDIOC_WR_MASK (1 << 31) + +/* MDIO data register */ +#define ENETSW_MDIOD_REG (0xb4) + +/* Global Management Configuration Register */ +#define ENETSW_GMCR_REG (0x200) +#define ENETSW_GMCR_RST_MIB_MASK (1 << 0) + /* MIB register */ #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4) #define ENETSW_MIB_REG_COUNT 47 +/* Jumbo control register port mask register */ +#define ENETSW_JMBCTL_PORT_REG (0x4004) + +/* Jumbo control mib good frame register */ +#define ENETSW_JMBCTL_MAXSIZE_REG (0x4008) + /************************************************************************* * _REG relative to RSET_OHCI_PRIV @@ -812,7 +865,7 @@ #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) #define USBH_PRIV_UTMI_CTL_6368_REG 0x10 -#define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12 +#define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12 #define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT) #define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0 #define USBH_PRIV_UTMI_CTL_HOSTB_MASK (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT) @@ -841,7 +894,7 @@ #define USBD_CONTROL_INIT_SEL_MASK (0xf << USBD_CONTROL_INIT_SEL_SHIFT) #define USBD_CONTROL_FIFO_RESET_SHIFT 6 #define USBD_CONTROL_FIFO_RESET_MASK (3 << USBD_CONTROL_FIFO_RESET_SHIFT) -#define USBD_CONTROL_SETUPERRLOCK_SHIFT 5 +#define USBD_CONTROL_SETUPERRLOCK_SHIFT 5 #define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT) #define USBD_CONTROL_DONE_CSRS_SHIFT 0 #define USBD_CONTROL_DONE_CSRS_MASK (1 << USBD_CONTROL_DONE_CSRS_SHIFT) @@ -852,7 +905,7 @@ #define USBD_STRAPS_APP_SELF_PWR_MASK (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT) #define USBD_STRAPS_APP_DISCON_SHIFT 9 #define USBD_STRAPS_APP_DISCON_MASK (1 << USBD_STRAPS_APP_DISCON_SHIFT) -#define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8 +#define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8 #define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT) #define USBD_STRAPS_APP_RMTWKUP_SHIFT 6 #define USBD_STRAPS_APP_RMTWKUP_MASK (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT) @@ -943,7 +996,7 @@ #define USBD_EPNUM_TYPEMAP_REG 0x50 #define USBD_EPNUM_TYPEMAP_TYPE_SHIFT 8 #define USBD_EPNUM_TYPEMAP_TYPE_MASK (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT) -#define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0 +#define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0 #define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT) /* Misc per-endpoint settings */ @@ -1048,8 +1101,8 @@ #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2) #define MPI_PCIMODESEL_REG 0x144 -#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0) -#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1) +#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0) +#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1) #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2) #define MPI_PCIMODESEL_PREFETCH_SHIFT 4 #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT) @@ -1223,24 +1276,7 @@ * _REG relative to RSET_SPI *************************************************************************/ -/* BCM 6338 SPI core */ -#define SPI_6338_CMD 0x00 /* 16-bits register */ -#define SPI_6338_INT_STATUS 0x02 -#define SPI_6338_INT_MASK_ST 0x03 -#define SPI_6338_INT_MASK 0x04 -#define SPI_6338_ST 0x05 -#define SPI_6338_CLK_CFG 0x06 -#define SPI_6338_FILL_BYTE 0x07 -#define SPI_6338_MSG_TAIL 0x09 -#define SPI_6338_RX_TAIL 0x0b -#define SPI_6338_MSG_CTL 0x40 /* 8-bits register */ -#define SPI_6338_MSG_CTL_WIDTH 8 -#define SPI_6338_MSG_DATA 0x41 -#define SPI_6338_MSG_DATA_SIZE 0x3f -#define SPI_6338_RX_DATA 0x80 -#define SPI_6338_RX_DATA_SIZE 0x3f - -/* BCM 6348 SPI core */ +/* BCM 6338/6348 SPI core */ #define SPI_6348_CMD 0x00 /* 16-bits register */ #define SPI_6348_INT_STATUS 0x02 #define SPI_6348_INT_MASK_ST 0x03 @@ -1257,7 +1293,7 @@ #define SPI_6348_RX_DATA 0x80 #define SPI_6348_RX_DATA_SIZE 0x3f -/* BCM 6358 SPI core */ +/* BCM 3368/6358/6262/6368 SPI core */ #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ #define SPI_6358_MSG_CTL_WIDTH 16 #define SPI_6358_MSG_DATA 0x02 @@ -1274,23 +1310,6 @@ #define SPI_6358_MSG_TAIL 0x709 #define SPI_6358_RX_TAIL 0x70B -/* BCM 6358 SPI core */ -#define SPI_6368_MSG_CTL 0x00 /* 16-bits register */ -#define SPI_6368_MSG_CTL_WIDTH 16 -#define SPI_6368_MSG_DATA 0x02 -#define SPI_6368_MSG_DATA_SIZE 0x21e -#define SPI_6368_RX_DATA 0x400 -#define SPI_6368_RX_DATA_SIZE 0x220 -#define SPI_6368_CMD 0x700 /* 16-bits register */ -#define SPI_6368_INT_STATUS 0x702 -#define SPI_6368_INT_MASK_ST 0x703 -#define SPI_6368_INT_MASK 0x704 -#define SPI_6368_ST 0x705 -#define SPI_6368_CLK_CFG 0x706 -#define SPI_6368_FILL_BYTE 0x707 -#define SPI_6368_MSG_TAIL 0x709 -#define SPI_6368_RX_TAIL 0x70B - /* Shared SPI definitions */ /* Message configuration */ @@ -1298,10 +1317,8 @@ #define SPI_HD_W 0x01 #define SPI_HD_R 0x02 #define SPI_BYTE_CNT_SHIFT 0 -#define SPI_6338_MSG_TYPE_SHIFT 6 #define SPI_6348_MSG_TYPE_SHIFT 6 #define SPI_6358_MSG_TYPE_SHIFT 14 -#define SPI_6368_MSG_TYPE_SHIFT 14 /* Command */ #define SPI_CMD_NOOP 0x00 @@ -1348,10 +1365,18 @@ /************************************************************************* * _REG relative to RSET_MISC *************************************************************************/ -#define MISC_SERDES_CTRL_REG 0x0 +#define MISC_SERDES_CTRL_6328_REG 0x0 +#define MISC_SERDES_CTRL_6362_REG 0x4 #define SERDES_PCIE_EN (1 << 0) #define SERDES_PCIE_EXD_EN (1 << 15) +#define MISC_STRAPBUS_6362_REG 0x14 +#define STRAPBUS_6362_FCVO_SHIFT 1 +#define STRAPBUS_6362_HSSPI_CLK_FAST (1 << 13) +#define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT) +#define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15) +#define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15) + #define MISC_STRAPBUS_6328_REG 0x240 #define STRAPBUS_6328_FCVO_SHIFT 7 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) @@ -1409,4 +1434,11 @@ #define PCIE_DEVICE_OFFSET 0x8000 +/************************************************************************* + * _REG relative to RSET_OTP + *************************************************************************/ + +#define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4) +#define OTP_6328_REG3_TP1_DISABLED BIT(9) + #endif /* BCM63XX_REGS_H_ */ diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h index 682bcf3b492..b86a0efba66 100644 --- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h @@ -24,6 +24,7 @@ struct board_info { /* enabled feature/device */ unsigned int has_enet0:1; unsigned int has_enet1:1; + unsigned int has_enetsw:1; unsigned int has_pci:1; unsigned int has_pccard:1; unsigned int has_ohci0:1; @@ -36,6 +37,7 @@ struct board_info { /* ethernet config */ struct bcm63xx_enet_platform_data enet0; struct bcm63xx_enet_platform_data enet1; + struct bcm63xx_enetsw_platform_data enetsw; /* USB config */ struct bcm63xx_usbd_platform_data usbd; @@ -45,6 +47,12 @@ struct board_info { /* GPIO LEDs */ struct gpio_led leds[5]; + + /* External PHY reset GPIO */ + unsigned int ephy_reset_gpio; + + /* External PHY reset GPIO flags from gpio.h */ + unsigned long ephy_reset_gpio_flags; }; #endif /* ! BOARD_BCM963XX_H_ */ diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h index 30931c42379..ff15e3b14e7 100644 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h @@ -11,6 +11,10 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) static inline int is_bcm63xx_internal_registers(phys_t offset) { switch (bcm63xx_get_cpu_id()) { + case BCM3368_CPU_ID: + if (offset >= 0xfff80000) + return 1; + break; case BCM6338_CPU_ID: case BCM6345_CPU_ID: case BCM6348_CPU_ID: @@ -19,6 +23,7 @@ static inline int is_bcm63xx_internal_registers(phys_t offset) return 1; break; case BCM6328_CPU_ID: + case BCM6362_CPU_ID: case BCM6368_CPU_ID: if (offset >= 0xb0000000 && offset < 0xb1000000) return 1; diff --git a/arch/mips/include/asm/mach-bcm63xx/irq.h b/arch/mips/include/asm/mach-bcm63xx/irq.h index 9332e788a5c..2bbfc8d1f30 100644 --- a/arch/mips/include/asm/mach-bcm63xx/irq.h +++ b/arch/mips/include/asm/mach-bcm63xx/irq.h @@ -1,7 +1,7 @@ #ifndef __ASM_MACH_BCM63XX_IRQ_H #define __ASM_MACH_BCM63XX_IRQ_H -#define NR_IRQS 128 +#define NR_IRQS 128 #define MIPS_CPU_IRQ_BASE 0 #endif diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h index 94ed063eec9..cf802287289 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h @@ -22,7 +22,6 @@ #define cpu_has_3k_cache 0 #define cpu_has_4k_cache 0 #define cpu_has_tx39_cache 0 -#define cpu_has_fpu 0 #define cpu_has_counter 1 #define cpu_has_watch 1 #define cpu_has_divec 1 diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h index be8fb4240ce..f9f44865050 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h +++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h @@ -13,6 +13,8 @@ #ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H #define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H +#include <linux/bug.h> + struct device; extern void octeon_pci_dma_init(void); @@ -21,18 +23,21 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) { BUG(); + return 0; } static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) { BUG(); + return 0; } static inline unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) { BUG(); + return 0; } static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, @@ -44,11 +49,7 @@ static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, static inline int plat_dma_supported(struct device *dev, u64 mask) { BUG(); -} - -static inline void plat_extra_sync_for_device(struct device *dev) -{ - BUG(); + return 0; } static inline int plat_device_is_coherent(struct device *dev) @@ -56,12 +57,6 @@ static inline int plat_device_is_coherent(struct device *dev) return 1; } -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - BUG(); -} - dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr); phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr); diff --git a/arch/mips/include/asm/mach-cavium-octeon/gpio.h b/arch/mips/include/asm/mach-cavium-octeon/gpio.h new file mode 100644 index 00000000000..34e9f7aabab --- /dev/null +++ b/arch/mips/include/asm/mach-cavium-octeon/gpio.h @@ -0,0 +1,21 @@ +#ifndef __ASM_MACH_CAVIUM_OCTEON_GPIO_H +#define __ASM_MACH_CAVIUM_OCTEON_GPIO_H + +#ifdef CONFIG_GPIOLIB +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#else +int gpio_request(unsigned gpio, const char *label); +void gpio_free(unsigned gpio); +int gpio_direction_input(unsigned gpio); +int gpio_direction_output(unsigned gpio, int value); +int gpio_get_value(unsigned gpio); +void gpio_set_value(unsigned gpio, int value); +#endif + +#include <asm-generic/gpio.h> + +#define gpio_to_irq __gpio_to_irq + +#endif /* __ASM_MACH_GENERIC_GPIO_H */ diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h index 502bb1815ae..cceae32a073 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/irq.h +++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h @@ -35,6 +35,8 @@ enum octeon_irq { OCTEON_IRQ_PCI_MSI2, OCTEON_IRQ_PCI_MSI3, + OCTEON_IRQ_TWSI, + OCTEON_IRQ_TWSI2, OCTEON_IRQ_RML, OCTEON_IRQ_TIMER0, OCTEON_IRQ_TIMER1, @@ -51,8 +53,8 @@ enum octeon_irq { /* 256 - 511 represent the MSI interrupts 0-255 */ #define OCTEON_IRQ_MSI_BIT0 (256) -#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255) -#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) +#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255) +#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) #endif #endif diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h index dedef7d2b01..1668ee57acb 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h @@ -16,7 +16,7 @@ #define CP0_PRID_OCTEON_PASS1 0x000d0000 #define CP0_PRID_OCTEON_CN30XX 0x000d0200 -.macro kernel_entry_setup +.macro kernel_entry_setup # Registers set by bootloader: # (only 32 bits set by bootloader, all addresses are physical # addresses, and need to have the appropriate memory region set @@ -28,21 +28,16 @@ .set push .set arch=octeon # Read the cavium mem control register - dmfc0 v0, CP0_CVMMEMCTL_REG + dmfc0 v0, CP0_CVMMEMCTL_REG # Clear the lower 6 bits, the CVMSEG size - dins v0, $0, 0, 6 - ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE - dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register - dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register -#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED + dins v0, $0, 0, 6 + ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE + dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register + dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register # Disable unaligned load/store support but leave HW fixup enabled + # Needed for octeon specific memcpy or v0, v0, 0x5001 xor v0, v0, 0x1001 -#else - # Disable unaligned load/store and HW fixup support - or v0, v0, 0x5001 - xor v0, v0, 0x5001 -#endif # Read the processor ID register mfc0 v1, CP0_PRID_REG # Disable instruction prefetching (Octeon Pass1 errata) @@ -69,14 +64,14 @@ skip: and v0, v0, v1 ori v0, v0, (6 << 7) # Write the cavium control register - dmtc0 v0, CP0_CVMCTL_REG + dmtc0 v0, CP0_CVMCTL_REG sync # Flush dcache after config change - cache 9, 0($0) + cache 9, 0($0) # Get my core id - rdhwr v0, $0 + rdhwr v0, $0 # Jump the master to kernel_entry - bne a2, zero, octeon_main_processor + bne a2, zero, octeon_main_processor nop #ifdef CONFIG_SMP @@ -87,21 +82,21 @@ skip: # # This is the variable where the next core to boot os stored - PTR_LA t0, octeon_processor_boot + PTR_LA t0, octeon_processor_boot octeon_spin_wait_boot: # Get the core id of the next to be booted - LONG_L t1, (t0) + LONG_L t1, (t0) # Keep looping if it isn't me bne t1, v0, octeon_spin_wait_boot nop # Get my GP from the global variable - PTR_LA t0, octeon_processor_gp - LONG_L gp, (t0) + PTR_LA t0, octeon_processor_gp + LONG_L gp, (t0) # Get my SP from the global variable - PTR_LA t0, octeon_processor_sp - LONG_L sp, (t0) + PTR_LA t0, octeon_processor_sp + LONG_L sp, (t0) # Set the SP global variable to zero so the master knows we've started - LONG_S zero, (t0) + LONG_S zero, (t0) #ifdef __OCTEON__ syncw syncw @@ -130,7 +125,7 @@ octeon_main_processor: /* * Do SMP slave processor setup necessary before we can savely execute C code. */ - .macro smp_slave_setup + .macro smp_slave_setup .endm #endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */ diff --git a/arch/mips/include/asm/mach-cavium-octeon/spaces.h b/arch/mips/include/asm/mach-cavium-octeon/spaces.h new file mode 100644 index 00000000000..daa91accf5a --- /dev/null +++ b/arch/mips/include/asm/mach-cavium-octeon/spaces.h @@ -0,0 +1,24 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 Cavium, Inc. + */ +#ifndef _ASM_MACH_CAVIUM_OCTEON_SPACES_H +#define _ASM_MACH_CAVIUM_OCTEON_SPACES_H + +#include <linux/const.h> + +#ifdef CONFIG_64BIT +/* They are all the same and some OCTEON II cores cannot handle 0xa8.. */ +#define CAC_BASE _AC(0x8000000000000000, UL) +#define UNCAC_BASE _AC(0x8000000000000000, UL) +#define IO_BASE _AC(0x8000000000000000, UL) + + +#endif /* CONFIG_64BIT */ + +#include <asm/mach-generic/spaces.h> + +#endif /* _ASM_MACH_CAVIUM_OCTEON_SPACES_H */ diff --git a/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h index babc8374e37..71d4bface1d 100644 --- a/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h @@ -32,9 +32,9 @@ #define cpu_scache_line_size() 0 #ifdef CONFIG_64BIT -#define cpu_has_llsc 0 +#define cpu_has_llsc 0 #else -#define cpu_has_llsc 1 +#define cpu_has_llsc 1 #endif #define cpu_has_mips16 0 diff --git a/arch/mips/include/asm/mach-cobalt/mach-gt64120.h b/arch/mips/include/asm/mach-cobalt/mach-gt64120.h index f8afec3f294..6fe475b9e96 100644 --- a/arch/mips/include/asm/mach-cobalt/mach-gt64120.h +++ b/arch/mips/include/asm/mach-cobalt/mach-gt64120.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Yoichi Yuasa <yuasa@linux-mips.org> + * Copyright (C) 2006 Yoichi Yuasa <yuasa@linux-mips.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h index 16f1cf5982b..3c3ed4ae45e 100644 --- a/arch/mips/include/asm/mach-db1x00/bcsr.h +++ b/arch/mips/include/asm/mach-db1x00/bcsr.h @@ -110,7 +110,7 @@ enum bcsr_whoami_boards { BCSR_WHOAMI_DB1300, }; -/* STATUS reg. Unless otherwise noted, they're valid on all boards. +/* STATUS reg. Unless otherwise noted, they're valid on all boards. * PB1200 = DB1200. */ #define BCSR_STATUS_PC0VS 0x0003 @@ -190,7 +190,7 @@ enum bcsr_whoami_boards { #define BCSR_RESETS_OTPWRPROT 0x1000 /* DB1300 */ #define BCSR_RESETS_OTPCSB 0x2000 /* DB1300 */ #define BCSR_RESETS_OTGPWR 0x4000 /* DB1300 */ -#define BCSR_RESETS_USBHPWR 0x8000 /* DB1300 */ +#define BCSR_RESETS_USBHPWR 0x8000 /* DB1300 */ #define BCSR_BOARD_LCDVEE 0x0001 #define BCSR_BOARD_LCDVDD 0x0002 diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h deleted file mode 100644 index b2a8319521e..00000000000 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * AMD Alchemy DBAu1200 Reference Board - * Board register defines. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_DB1200_H -#define __ASM_DB1200_H - -#include <linux/types.h> -#include <asm/mach-au1x00/au1000.h> -#include <asm/mach-au1x00/au1xxx_psc.h> - -/* Bit positions for the different interrupt sources */ -#define BCSR_INT_IDE 0x0001 -#define BCSR_INT_ETH 0x0002 -#define BCSR_INT_PC0 0x0004 -#define BCSR_INT_PC0STSCHG 0x0008 -#define BCSR_INT_PC1 0x0010 -#define BCSR_INT_PC1STSCHG 0x0020 -#define BCSR_INT_DC 0x0040 -#define BCSR_INT_FLASHBUSY 0x0080 -#define BCSR_INT_PC0INSERT 0x0100 -#define BCSR_INT_PC0EJECT 0x0200 -#define BCSR_INT_PC1INSERT 0x0400 -#define BCSR_INT_PC1EJECT 0x0800 -#define BCSR_INT_SD0INSERT 0x1000 -#define BCSR_INT_SD0EJECT 0x2000 -#define BCSR_INT_SD1INSERT 0x4000 -#define BCSR_INT_SD1EJECT 0x8000 - -#define IDE_REG_SHIFT 5 - -#define DB1200_IDE_PHYS_ADDR 0x18800000 -#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) -#define DB1200_ETH_PHYS_ADDR 0x19000300 -#define DB1200_NAND_PHYS_ADDR 0x20000000 - -#define PB1200_IDE_PHYS_ADDR 0x0C800000 -#define PB1200_ETH_PHYS_ADDR 0x0D000300 -#define PB1200_NAND_PHYS_ADDR 0x1C000000 - -/* - * External Interrupts for DBAu1200 as of 8/6/2004. - * Bit positions in the CPLD registers can be calculated by taking - * the interrupt define and subtracting the DB1200_INT_BEGIN value. - * - * Example: IDE bis pos is = 64 - 64 - * ETH bit pos is = 65 - 64 - */ -enum external_db1200_ints { - DB1200_INT_BEGIN = AU1000_MAX_INTR + 1, - - DB1200_IDE_INT = DB1200_INT_BEGIN, - DB1200_ETH_INT, - DB1200_PC0_INT, - DB1200_PC0_STSCHG_INT, - DB1200_PC1_INT, - DB1200_PC1_STSCHG_INT, - DB1200_DC_INT, - DB1200_FLASHBUSY_INT, - DB1200_PC0_INSERT_INT, - DB1200_PC0_EJECT_INT, - DB1200_PC1_INSERT_INT, - DB1200_PC1_EJECT_INT, - DB1200_SD0_INSERT_INT, - DB1200_SD0_EJECT_INT, - PB1200_SD1_INSERT_INT, - PB1200_SD1_EJECT_INT, - - DB1200_INT_END = DB1200_INT_BEGIN + 15, -}; - -#endif /* __ASM_DB1200_H */ diff --git a/arch/mips/include/asm/mach-db1x00/db1300.h b/arch/mips/include/asm/mach-db1x00/db1300.h deleted file mode 100644 index 7fe5fb3ba87..00000000000 --- a/arch/mips/include/asm/mach-db1x00/db1300.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * NetLogic DB1300 board constants - */ - -#ifndef _DB1300_H_ -#define _DB1300_H_ - -/* FPGA (external mux) interrupt sources */ -#define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1) -#define DB1300_IDE_INT (DB1300_FIRST_INT + 0) -#define DB1300_ETH_INT (DB1300_FIRST_INT + 1) -#define DB1300_CF_INT (DB1300_FIRST_INT + 2) -#define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4) -#define DB1300_HDMI_INT (DB1300_FIRST_INT + 5) -#define DB1300_DC_INT (DB1300_FIRST_INT + 6) -#define DB1300_FLASH_INT (DB1300_FIRST_INT + 7) -#define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8) -#define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9) -#define DB1300_AC97_INT (DB1300_FIRST_INT + 10) -#define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11) -#define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12) -#define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13) -#define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14) -#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15) -#define DB1300_LAST_INT (DB1300_FIRST_INT + 15) - -/* SMSC9210 CS */ -#define DB1300_ETH_PHYS_ADDR 0x19000000 -#define DB1300_ETH_PHYS_END 0x197fffff - -/* ATA CS */ -#define DB1300_IDE_PHYS_ADDR 0x18800000 -#define DB1300_IDE_REG_SHIFT 5 -#define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT) - -/* NAND CS */ -#define DB1300_NAND_PHYS_ADDR 0x20000000 -#define DB1300_NAND_PHYS_END 0x20000fff - -#endif /* _DB1300_H_ */ diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h new file mode 100644 index 00000000000..acce27fd2bb --- /dev/null +++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h @@ -0,0 +1,87 @@ +/* + * CPU feature overrides for DECstation systems. Two variations + * are generally applicable. + * + * Copyright (C) 2013 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H + +/* Generic ones first. */ +#define cpu_has_tlb 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_fpu 1 +#define cpu_has_divec 0 +#define cpu_has_prefetch 0 +#define cpu_has_mcheck 0 +#define cpu_has_ejtag 0 +#define cpu_has_mips16 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 +#define cpu_has_rixi 0 +#define cpu_has_vtag_icache 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_pindexed_dcache 0 +#define cpu_has_local_ebase 0 +#define cpu_icache_snoops_remote_store 1 +#define cpu_has_mips_4 0 +#define cpu_has_mips_5 0 +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 + +/* R3k-specific ones. */ +#ifdef CONFIG_CPU_R3000 +#define cpu_has_4kex 0 +#define cpu_has_3k_cache 1 +#define cpu_has_4k_cache 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 0 +#define cpu_has_watch 0 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_llsc 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_mips_2 0 +#define cpu_has_mips_3 0 +#define cpu_has_nofpuex 1 +#define cpu_has_inclusive_pcaches 0 +#define cpu_dcache_line_size() 4 +#define cpu_icache_line_size() 4 +#define cpu_scache_line_size() 0 +#endif /* CONFIG_CPU_R3000 */ + +/* R4k-specific ones. */ +#ifdef CONFIG_CPU_R4X00 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_32fpr 1 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_vce 1 +#define cpu_has_cache_cdex_p 1 +#define cpu_has_cache_cdex_s 1 +#define cpu_has_llsc 1 +#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) +#define cpu_has_mips_2 1 +#define cpu_has_mips_3 1 +#define cpu_has_nofpuex 0 +#define cpu_has_inclusive_pcaches 1 +#define cpu_dcache_line_size() 16 +#define cpu_icache_line_size() 16 +#define cpu_scache_line_size() 32 +#endif /* CONFIG_CPU_R4X00 */ + +#endif /* __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-emma2rh/irq.h b/arch/mips/include/asm/mach-emma2rh/irq.h index 5439eb85646..2f7155dade2 100644 --- a/arch/mips/include/asm/mach-emma2rh/irq.h +++ b/arch/mips/include/asm/mach-emma2rh/irq.h @@ -8,7 +8,7 @@ #ifndef __ASM_MACH_EMMA2RH_IRQ_H #define __ASM_MACH_EMMA2RH_IRQ_H -#define NR_IRQS 256 +#define NR_IRQS 256 #include_next <irq.h> diff --git a/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h index 7c185bb06f1..42be9e9ced2 100644 --- a/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h @@ -8,6 +8,6 @@ #ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H -/* Intentionally empty file ... */ +/* Intentionally empty file ... */ #endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 9c95177f7a7..7629c35986f 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -47,24 +47,21 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 1; } -static inline void plat_extra_sync_for_device(struct device *dev) +static inline int plat_device_is_coherent(struct device *dev) { + return coherentio; } -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) +#ifdef CONFIG_SWIOTLB +static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) { - return 0; + return paddr; } -static inline int plat_device_is_coherent(struct device *dev) +static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) { -#ifdef CONFIG_DMA_COHERENT - return 1; -#endif -#ifdef CONFIG_DMA_NONCOHERENT - return 0; -#endif + return daddr; } +#endif #endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ diff --git a/arch/mips/include/asm/mach-generic/floppy.h b/arch/mips/include/asm/mach-generic/floppy.h index a38f4d43e5e..e2561d99a3f 100644 --- a/arch/mips/include/asm/mach-generic/floppy.h +++ b/arch/mips/include/asm/mach-generic/floppy.h @@ -9,7 +9,6 @@ #define __ASM_MACH_GENERIC_FLOPPY_H #include <linux/delay.h> -#include <linux/init.h> #include <linux/ioport.h> #include <linux/sched.h> #include <linux/linkage.h> @@ -98,7 +97,7 @@ static inline void fd_disable_irq(void) static inline int fd_request_irq(void) { return request_irq(FLOPPY_IRQ, floppy_interrupt, - 0, "floppy", NULL); + 0, "floppy", NULL); } static inline void fd_free_irq(void) @@ -106,7 +105,7 @@ static inline void fd_free_irq(void) free_irq(FLOPPY_IRQ, NULL); } -#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL); +#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL); static inline unsigned long fd_getfdaddr1(void) diff --git a/arch/mips/include/asm/mach-generic/ide.h b/arch/mips/include/asm/mach-generic/ide.h index 9c93a5b36f2..4ae5fbcb15a 100644 --- a/arch/mips/include/asm/mach-generic/ide.h +++ b/arch/mips/include/asm/mach-generic/ide.h @@ -23,7 +23,7 @@ static inline void __ide_flush_prologue(void) { #ifdef CONFIG_SMP - if (cpu_has_dc_aliases) + if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) preempt_disable(); #endif } @@ -31,14 +31,14 @@ static inline void __ide_flush_prologue(void) static inline void __ide_flush_epilogue(void) { #ifdef CONFIG_SMP - if (cpu_has_dc_aliases) + if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) preempt_enable(); #endif } static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size) { - if (cpu_has_dc_aliases) { + if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) { unsigned long end = addr + size; while (addr < end) { @@ -51,7 +51,7 @@ static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long si /* * insw() and gang might be called with interrupts disabled, so we can't * send IPIs for flushing due to the potencial of deadlocks, see the comment - * above smp_call_function() in arch/mips/kernel/smp.c. We work around the + * above smp_call_function() in arch/mips/kernel/smp.c. We work around the * problem by disabling preemption so we know we actually perform the flush * on the processor that actually has the lines to be flushed which hopefully * is even better for performance anyway. @@ -123,7 +123,7 @@ static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count) __ide_flush_epilogue(); } -/* ide_insw calls insw, not __ide_insw. Why? */ +/* ide_insw calls insw, not __ide_insw. Why? */ #undef insw #undef insl #undef outsw diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h index e014264b2be..139cd200e79 100644 --- a/arch/mips/include/asm/mach-generic/irq.h +++ b/arch/mips/include/asm/mach-generic/irq.h @@ -9,12 +9,12 @@ #define __ASM_MACH_GENERIC_IRQ_H #ifndef NR_IRQS -#define NR_IRQS 128 +#define NR_IRQS 128 #endif #ifdef CONFIG_I8259 #ifndef I8259A_IRQ_BASE -#define I8259A_IRQ_BASE 0 +#define I8259A_IRQ_BASE 0 #endif #endif diff --git a/arch/mips/include/asm/mach-generic/kernel-entry-init.h b/arch/mips/include/asm/mach-generic/kernel-entry-init.h index 7e66505fa57..13b0751b010 100644 --- a/arch/mips/include/asm/mach-generic/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-generic/kernel-entry-init.h @@ -12,8 +12,8 @@ /* Intentionally empty macro, used in head.S. Override in * arch/mips/mach-xxx/kernel-entry-init.h when necessary. */ -.macro kernel_entry_setup -.endm + .macro kernel_entry_setup + .endm /* * Do SMP slave processor setup necessary before we can savely execute C code. diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h index d7a9efd3a5c..9488fa5f886 100644 --- a/arch/mips/include/asm/mach-generic/spaces.h +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -20,14 +20,25 @@ #endif #ifdef CONFIG_32BIT - +#ifdef CONFIG_KVM_GUEST +#define CAC_BASE _AC(0x40000000, UL) +#else #define CAC_BASE _AC(0x80000000, UL) +#endif +#ifndef IO_BASE #define IO_BASE _AC(0xa0000000, UL) +#endif +#ifndef UNCAC_BASE #define UNCAC_BASE _AC(0xa0000000, UL) +#endif #ifndef MAP_BASE +#ifdef CONFIG_KVM_GUEST +#define MAP_BASE _AC(0x60000000, UL) +#else #define MAP_BASE _AC(0xc0000000, UL) #endif +#endif /* * Memory above this physical address will be considered highmem. @@ -69,7 +80,7 @@ #define HIGHMEM_START (_AC(1, UL) << _AC(59, UL)) #endif -#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) +#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) diff --git a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h index f4caacd2555..1dfe47453ea 100644 --- a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h @@ -8,6 +8,8 @@ #ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H +#include <asm/cpu.h> + /* * IP22 with a variety of processors so we can't use defaults for everything. */ @@ -37,6 +39,10 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mips_2 1 +#define cpu_has_mips_3 1 +#define cpu_has_mips_5 0 + #define cpu_has_mips32r1 0 #define cpu_has_mips32r2 0 #define cpu_has_mips64r1 0 diff --git a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h index 1d2b6ff60d3..d6111aa2e88 100644 --- a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h @@ -8,6 +8,8 @@ #ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H +#include <asm/cpu.h> + /* * IP27 only comes with R10000 family processors all using the same config */ diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h index 06c441968e6..4ffddfdb506 100644 --- a/arch/mips/include/asm/mach-ip27/dma-coherence.h +++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h @@ -58,16 +58,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 1; } -static inline void plat_extra_sync_for_device(struct device *dev) -{ -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - static inline int plat_device_is_coherent(struct device *dev) { return 1; /* IP27 non-cohernet mode is unsupported */ diff --git a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h index 624d66c7f29..b087cb83da3 100644 --- a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h @@ -24,6 +24,53 @@ .endm /* + * TLB bits + */ +#define PAGE_GLOBAL (1 << 6) +#define PAGE_VALID (1 << 7) +#define PAGE_DIRTY (1 << 8) +#define CACHE_CACHABLE_COW (5 << 9) + + /* + * inputs are the text nasid in t1, data nasid in t2. + */ + .macro MAPPED_KERNEL_SETUP_TLB +#ifdef CONFIG_MAPPED_KERNEL + /* + * This needs to read the nasid - assume 0 for now. + * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0, + * 0+DVG in tlblo_1. + */ + dli t0, 0xffffffffc0000000 + dmtc0 t0, CP0_ENTRYHI + li t0, 0x1c000 # Offset of text into node memory + dsll t1, NASID_SHFT # Shift text nasid into place + dsll t2, NASID_SHFT # Same for data nasid + or t1, t1, t0 # Physical load address of kernel text + or t2, t2, t0 # Physical load address of kernel data + dsrl t1, 12 # 4K pfn + dsrl t2, 12 # 4K pfn + dsll t1, 6 # Get pfn into place + dsll t2, 6 # Get pfn into place + li t0, ((PAGE_GLOBAL | PAGE_VALID | CACHE_CACHABLE_COW) >> 6) + or t0, t0, t1 + mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr + li t0, ((PAGE_GLOBAL | PAGE_VALID | PAGE_DIRTY | CACHE_CACHABLE_COW) >> 6) + or t0, t0, t2 + mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr + li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M + mtc0 t0, CP0_PAGEMASK + li t0, 0 # KMAP_INX + mtc0 t0, CP0_INDEX + li t0, 1 + mtc0 t0, CP0_WIRED + tlbwi +#else + mtc0 zero, CP0_WIRED +#endif + .endm + +/* * Intentionally empty macro, used in head.S. Override in * arch/mips/mach-xxx/kernel-entry-init.h when necessary. */ @@ -51,8 +98,8 @@ * We might not get launched at the address the kernel is linked to, * so we jump there. */ - PTR_LA t0, 0f - jr t0 + PTR_LA t0, 0f + jr t0 0: .endm diff --git a/arch/mips/include/asm/mach-ip27/mmzone.h b/arch/mips/include/asm/mach-ip27/mmzone.h index 986a3b9b59a..ebc9377ff87 100644 --- a/arch/mips/include/asm/mach-ip27/mmzone.h +++ b/arch/mips/include/asm/mach-ip27/mmzone.h @@ -7,7 +7,7 @@ #define pa_to_nid(addr) NASID_TO_COMPACT_NODEID(NASID_GET(addr)) -#define LEVELS_PER_SLICE 128 +#define LEVELS_PER_SLICE 128 struct slice_data { unsigned long irq_enable_mask[2]; diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h index b2cf641f206..defd135e7ac 100644 --- a/arch/mips/include/asm/mach-ip27/topology.h +++ b/arch/mips/include/asm/mach-ip27/topology.h @@ -34,7 +34,7 @@ extern int pcibus_to_node(struct pci_bus *); extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES]; -#define node_distance(from, to) (__node_distances[(from)][(to)]) +#define node_distance(from, to) (__node_distances[(from)][(to)]) #include <asm-generic/topology.h> diff --git a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h index 50d344ca60a..4cec06d133d 100644 --- a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h @@ -9,6 +9,8 @@ #ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H +#include <asm/cpu.h> + /* * IP28 only comes with R10000 family processors all using the same config */ @@ -28,7 +30,7 @@ #define cpu_has_ic_fills_f_dc 0 #define cpu_has_dsp 0 #define cpu_has_dsp2 0 -#define cpu_icache_snoops_remote_store 1 +#define cpu_icache_snoops_remote_store 1 #define cpu_has_mipsmt 0 #define cpu_has_userlocal 0 diff --git a/arch/mips/include/asm/mach-ip28/spaces.h b/arch/mips/include/asm/mach-ip28/spaces.h index 05aabb27e5e..5d6a76434d0 100644 --- a/arch/mips/include/asm/mach-ip28/spaces.h +++ b/arch/mips/include/asm/mach-ip28/spaces.h @@ -6,16 +6,19 @@ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle * Copyright (C) 2000, 2002 Maciej W. Rozycki * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. - * 2004 pf + * 2004 pf */ #ifndef _ASM_MACH_IP28_SPACES_H #define _ASM_MACH_IP28_SPACES_H -#define CAC_BASE 0xa800000000000000 +#define CAC_BASE _AC(0xa800000000000000, UL) -#define HIGHMEM_START (~0UL) +#define HIGHMEM_START (~0UL) -#define PHYS_OFFSET _AC(0x20000000, UL) +#define PHYS_OFFSET _AC(0x20000000, UL) + +#define UNCAC_BASE _AC(0xc0000000, UL) /* 0xa0000000 + PHYS_OFFSET */ +#define IO_BASE UNCAC_BASE #include <asm/mach-generic/spaces.h> diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h index c8fb5aacf50..104cfbc3ed6 100644 --- a/arch/mips/include/asm/mach-ip32/dma-coherence.h +++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h @@ -50,7 +50,7 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, return pa; } -/* This is almost certainly wrong but it's what dma-ip32.c used to use */ +/* This is almost certainly wrong but it's what dma-ip32.c used to use */ static inline unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) { @@ -80,17 +80,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 1; } -static inline void plat_extra_sync_for_device(struct device *dev) -{ - return; -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - static inline int plat_device_is_coherent(struct device *dev) { return 0; /* IP32 is non-cohernet */ diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h index 7237a935a13..9807ecda5a8 100644 --- a/arch/mips/include/asm/mach-ip32/war.h +++ b/arch/mips/include/asm/mach-ip32/war.h @@ -17,7 +17,7 @@ #define MIPS4K_ICACHE_REFILL_WAR 0 #define MIPS_CACHE_SYNC_WAR 0 #define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 #define R10000_LLSC_WAR 0 #define MIPS34K_MISSED_ITLB_WAR 0 diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h index 9fc1e9ad703..949003ef97b 100644 --- a/arch/mips/include/asm/mach-jazz/dma-coherence.h +++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h @@ -48,16 +48,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 1; } -static inline void plat_extra_sync_for_device(struct device *dev) -{ -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - static inline int plat_device_is_coherent(struct device *dev) { return 0; diff --git a/arch/mips/include/asm/mach-jazz/floppy.h b/arch/mips/include/asm/mach-jazz/floppy.h index 88b5acb7514..4b86c88a03b 100644 --- a/arch/mips/include/asm/mach-jazz/floppy.h +++ b/arch/mips/include/asm/mach-jazz/floppy.h @@ -9,7 +9,6 @@ #define __ASM_MACH_JAZZ_FLOPPY_H #include <linux/delay.h> -#include <linux/init.h> #include <linux/linkage.h> #include <linux/types.h> #include <linux/mm.h> @@ -90,7 +89,7 @@ static inline void fd_disable_irq(void) static inline int fd_request_irq(void) { return request_irq(FLOPPY_IRQ, floppy_interrupt, - 0, "floppy", NULL); + 0, "floppy", NULL); } static inline void fd_free_irq(void) diff --git a/arch/mips/include/asm/mach-jz4740/clock.h b/arch/mips/include/asm/mach-jz4740/clock.h index 1b7408dd0e2..16659cd76d4 100644 --- a/arch/mips/include/asm/mach-jz4740/clock.h +++ b/arch/mips/include/asm/mach-jz4740/clock.h @@ -2,7 +2,7 @@ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * diff --git a/arch/mips/include/asm/mach-jz4740/dma.h b/arch/mips/include/asm/mach-jz4740/dma.h index a3be1218359..14ecc5313d2 100644 --- a/arch/mips/include/asm/mach-jz4740/dma.h +++ b/arch/mips/include/asm/mach-jz4740/dma.h @@ -3,7 +3,7 @@ * JZ7420/JZ4740 DMA definitions * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * @@ -16,16 +16,12 @@ #ifndef __ASM_MACH_JZ4740_DMA_H__ #define __ASM_MACH_JZ4740_DMA_H__ -struct jz4740_dma_chan; - enum jz4740_dma_request_type { JZ4740_DMA_TYPE_AUTO_REQUEST = 8, JZ4740_DMA_TYPE_UART_TRANSMIT = 20, JZ4740_DMA_TYPE_UART_RECEIVE = 21, JZ4740_DMA_TYPE_SPI_TRANSMIT = 22, JZ4740_DMA_TYPE_SPI_RECEIVE = 23, - JZ4740_DMA_TYPE_AIC_TRANSMIT = 24, - JZ4740_DMA_TYPE_AIC_RECEIVE = 25, JZ4740_DMA_TYPE_MMC_TRANSMIT = 26, JZ4740_DMA_TYPE_MMC_RECEIVE = 27, JZ4740_DMA_TYPE_TCU = 28, @@ -33,58 +29,4 @@ enum jz4740_dma_request_type { JZ4740_DMA_TYPE_SLCD = 30, }; -enum jz4740_dma_width { - JZ4740_DMA_WIDTH_32BIT = 0, - JZ4740_DMA_WIDTH_8BIT = 1, - JZ4740_DMA_WIDTH_16BIT = 2, -}; - -enum jz4740_dma_transfer_size { - JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0, - JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1, - JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2, - JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3, - JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4, -}; - -enum jz4740_dma_flags { - JZ4740_DMA_SRC_AUTOINC = 0x2, - JZ4740_DMA_DST_AUTOINC = 0x1, -}; - -enum jz4740_dma_mode { - JZ4740_DMA_MODE_SINGLE = 0, - JZ4740_DMA_MODE_BLOCK = 1, -}; - -struct jz4740_dma_config { - enum jz4740_dma_width src_width; - enum jz4740_dma_width dst_width; - enum jz4740_dma_transfer_size transfer_size; - enum jz4740_dma_request_type request_type; - enum jz4740_dma_flags flags; - enum jz4740_dma_mode mode; -}; - -typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int, void *); - -struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name); -void jz4740_dma_free(struct jz4740_dma_chan *dma); - -void jz4740_dma_configure(struct jz4740_dma_chan *dma, - const struct jz4740_dma_config *config); - - -void jz4740_dma_enable(struct jz4740_dma_chan *dma); -void jz4740_dma_disable(struct jz4740_dma_chan *dma); - -void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src); -void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst); -void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count); - -uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma); - -void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma, - jz4740_dma_complete_callback_t cb); - -#endif /* __ASM_JZ4740_DMA_H__ */ +#endif /* __ASM_JZ4740_DMA_H__ */ diff --git a/arch/mips/include/asm/mach-jz4740/gpio.h b/arch/mips/include/asm/mach-jz4740/gpio.h index 1a6482ea0bb..eaacba79cf1 100644 --- a/arch/mips/include/asm/mach-jz4740/gpio.h +++ b/arch/mips/include/asm/mach-jz4740/gpio.h @@ -198,7 +198,7 @@ uint32_t jz_gpio_port_get_value(int port, uint32_t mask); #define JZ_GPIO_FUNC_MEM_ADDR14 JZ_GPIO_FUNC1 #define JZ_GPIO_FUNC_MEM_ADDR15 JZ_GPIO_FUNC1 #define JZ_GPIO_FUNC_MEM_ADDR16 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_CLS JZ_GPIO_FUNC1 +#define JZ_GPIO_FUNC_LCD_CLS JZ_GPIO_FUNC1 #define JZ_GPIO_FUNC_LCD_SPL JZ_GPIO_FUNC1 #define JZ_GPIO_FUNC_MEM_DCS JZ_GPIO_FUNC1 #define JZ_GPIO_FUNC_MEM_RAS JZ_GPIO_FUNC1 diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h index 5ad1a9c113c..df50736749c 100644 --- a/arch/mips/include/asm/mach-jz4740/irq.h +++ b/arch/mips/include/asm/mach-jz4740/irq.h @@ -3,7 +3,7 @@ * JZ4740 IRQ definitions * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h index 163e81db880..069b43a9da6 100644 --- a/arch/mips/include/asm/mach-jz4740/platform.h +++ b/arch/mips/include/asm/mach-jz4740/platform.h @@ -3,7 +3,7 @@ * JZ4740 platform device definitions * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * @@ -21,6 +21,7 @@ extern struct platform_device jz4740_usb_ohci_device; extern struct platform_device jz4740_udc_device; +extern struct platform_device jz4740_udc_xceiv_device; extern struct platform_device jz4740_mmc_device; extern struct platform_device jz4740_rtc_device; extern struct platform_device jz4740_i2c_device; @@ -32,6 +33,7 @@ extern struct platform_device jz4740_codec_device; extern struct platform_device jz4740_adc_device; extern struct platform_device jz4740_wdt_device; extern struct platform_device jz4740_pwm_device; +extern struct platform_device jz4740_dma_device; void jz4740_serial_device_register(void); diff --git a/arch/mips/include/asm/mach-jz4740/timer.h b/arch/mips/include/asm/mach-jz4740/timer.h index a7759fb1f73..8750a1d04e2 100644 --- a/arch/mips/include/asm/mach-jz4740/timer.h +++ b/arch/mips/include/asm/mach-jz4740/timer.h @@ -3,7 +3,7 @@ * JZ4740 platform timer support * * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * diff --git a/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h new file mode 100644 index 00000000000..096a1007243 --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h @@ -0,0 +1,58 @@ +/* + * Lantiq FALCON specific CPU feature overrides + * + * Copyright (C) 2013 Thomas Langer, Lantiq Deutschland + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 1 +#define cpu_has_mipsmt 1 + +#define cpu_has_vint 1 +#define cpu_has_veic 1 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h index fccac359265..98d6a2f14aa 100644 --- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h @@ -44,7 +44,7 @@ /* BOOT_SEL - find what boot media we have */ #define BS_FLASH 0x1 -#define BS_SPI 0x4 +#define BS_SPI 0x4 /* global register ranges */ extern __iomem void *ltq_ebu_membase; diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h index 5e8a6e96575..f196cceb732 100644 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h @@ -34,6 +34,7 @@ extern spinlock_t ebu_lock; extern void ltq_disable_irq(struct irq_data *data); extern void ltq_mask_and_ack_irq(struct irq_data *data); extern void ltq_enable_irq(struct irq_data *data); +extern int ltq_eiu_get_irq(int exin); /* clock handling */ extern int clk_activate(struct clk *clk); @@ -41,6 +42,7 @@ extern void clk_deactivate(struct clk *clk); extern struct clk *clk_get_cpu(void); extern struct clk *clk_get_fpi(void); extern struct clk *clk_get_io(void); +extern struct clk *clk_get_ppe(void); /* find out what bootsource we have */ extern unsigned char ltq_boot_select(void); diff --git a/arch/mips/include/asm/mach-lantiq/war.h b/arch/mips/include/asm/mach-lantiq/war.h index b6c568c280e..358ca979c1b 100644 --- a/arch/mips/include/asm/mach-lantiq/war.h +++ b/arch/mips/include/asm/mach-lantiq/war.h @@ -7,17 +7,17 @@ #ifndef __ASM_MIPS_MACH_LANTIQ_WAR_H #define __ASM_MIPS_MACH_LANTIQ_WAR_H -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 #endif diff --git a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h index 872943a4b90..5f8693d5ab1 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h +++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h @@ -21,7 +21,7 @@ #define LTQ_DESC_SIZE 0x08 /* each descriptor is 64bit */ #define LTQ_DESC_NUM 0x40 /* 64 descriptors / channel */ -#define LTQ_DMA_OWN BIT(31) /* owner bit */ +#define LTQ_DMA_OWN BIT(31) /* owner bit */ #define LTQ_DMA_C BIT(30) /* complete bit */ #define LTQ_DMA_SOP BIT(29) /* start of packet */ #define LTQ_DMA_EOP BIT(28) /* end of packet */ @@ -38,7 +38,7 @@ struct ltq_dma_channel { int nr; /* the channel number */ int irq; /* the mapped irq */ int desc; /* the current descriptor */ - struct ltq_dma_desc *desc_base; /* the descriptor base */ + struct ltq_dma_desc *desc_base; /* the descriptor base */ int phys; /* physical addr */ }; diff --git a/arch/mips/include/asm/mach-lasat/mach-gt64120.h b/arch/mips/include/asm/mach-lasat/mach-gt64120.h index 1a9ad45cc13..c253d3fa516 100644 --- a/arch/mips/include/asm/mach-lasat/mach-gt64120.h +++ b/arch/mips/include/asm/mach-lasat/mach-gt64120.h @@ -1,6 +1,6 @@ /* * This is a direct copy of the ev96100.h file, with a global - * search and replace. The numbers are the same. + * search and replace. The numbers are the same. * * The reason I'm duplicating this is so that the 64120/96100 * defines won't be confusing in the source code. @@ -18,8 +18,8 @@ * * (Guessing ...) */ -#define GT_PCI_MEM_BASE 0x12000000UL -#define GT_PCI_MEM_SIZE 0x02000000UL +#define GT_PCI_MEM_BASE 0x12000000UL +#define GT_PCI_MEM_SIZE 0x02000000UL #define GT_PCI_IO_BASE 0x10000000UL #define GT_PCI_IO_SIZE 0x02000000UL #define GT_ISA_IO_BASE PCI_IO_BASE diff --git a/arch/mips/include/asm/mach-loongson/boot_param.h b/arch/mips/include/asm/mach-loongson/boot_param.h new file mode 100644 index 00000000000..829a7ec185f --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/boot_param.h @@ -0,0 +1,163 @@ +#ifndef __ASM_MACH_LOONGSON_BOOT_PARAM_H_ +#define __ASM_MACH_LOONGSON_BOOT_PARAM_H_ + +#define SYSTEM_RAM_LOW 1 +#define SYSTEM_RAM_HIGH 2 +#define MEM_RESERVED 3 +#define PCI_IO 4 +#define PCI_MEM 5 +#define LOONGSON_CFG_REG 6 +#define VIDEO_ROM 7 +#define ADAPTER_ROM 8 +#define ACPI_TABLE 9 +#define MAX_MEMORY_TYPE 10 + +#define LOONGSON3_BOOT_MEM_MAP_MAX 128 +struct efi_memory_map_loongson { + u16 vers; /* version of efi_memory_map */ + u32 nr_map; /* number of memory_maps */ + u32 mem_freq; /* memory frequence */ + struct mem_map { + u32 node_id; /* node_id which memory attached to */ + u32 mem_type; /* system memory, pci memory, pci io, etc. */ + u64 mem_start; /* memory map start address */ + u32 mem_size; /* each memory_map size, not the total size */ + } map[LOONGSON3_BOOT_MEM_MAP_MAX]; +} __packed; + +enum loongson_cpu_type { + Loongson_2E = 0, + Loongson_2F = 1, + Loongson_3A = 2, + Loongson_3B = 3, + Loongson_1A = 4, + Loongson_1B = 5 +}; + +/* + * Capability and feature descriptor structure for MIPS CPU + */ +struct efi_cpuinfo_loongson { + u16 vers; /* version of efi_cpuinfo_loongson */ + u32 processor_id; /* PRID, e.g. 6305, 6306 */ + u32 cputype; /* Loongson_3A/3B, etc. */ + u32 total_node; /* num of total numa nodes */ + u32 cpu_startup_core_id; /* Core id */ + u32 cpu_clock_freq; /* cpu_clock */ + u32 nr_cpus; +} __packed; + +struct system_loongson { + u16 vers; /* version of system_loongson */ + u32 ccnuma_smp; /* 0: no numa; 1: has numa */ + u32 sing_double_channel; /* 1:single; 2:double */ +} __packed; + +struct irq_source_routing_table { + u16 vers; + u16 size; + u16 rtr_bus; + u16 rtr_devfn; + u32 vendor; + u32 device; + u32 PIC_type; /* conform use HT or PCI to route to CPU-PIC */ + u64 ht_int_bit; /* 3A: 1<<24; 3B: 1<<16 */ + u64 ht_enable; /* irqs used in this PIC */ + u32 node_id; /* node id: 0x0-0; 0x1-1; 0x10-2; 0x11-3 */ + u64 pci_mem_start_addr; + u64 pci_mem_end_addr; + u64 pci_io_start_addr; + u64 pci_io_end_addr; + u64 pci_config_addr; + u32 dma_mask_bits; +} __packed; + +struct interface_info { + u16 vers; /* version of the specificition */ + u16 size; + u8 flag; + char description[64]; +} __packed; + +#define MAX_RESOURCE_NUMBER 128 +struct resource_loongson { + u64 start; /* resource start address */ + u64 end; /* resource end address */ + char name[64]; + u32 flags; +}; + +struct archdev_data {}; /* arch specific additions */ + +struct board_devices { + char name[64]; /* hold the device name */ + u32 num_resources; /* number of device_resource */ + /* for each device's resource */ + struct resource_loongson resource[MAX_RESOURCE_NUMBER]; + /* arch specific additions */ + struct archdev_data archdata; +}; + +struct loongson_special_attribute { + u16 vers; /* version of this special */ + char special_name[64]; /* special_atribute_name */ + u32 loongson_special_type; /* type of special device */ + /* for each device's resource */ + struct resource_loongson resource[MAX_RESOURCE_NUMBER]; +}; + +struct loongson_params { + u64 memory_offset; /* efi_memory_map_loongson struct offset */ + u64 cpu_offset; /* efi_cpuinfo_loongson struct offset */ + u64 system_offset; /* system_loongson struct offset */ + u64 irq_offset; /* irq_source_routing_table struct offset */ + u64 interface_offset; /* interface_info struct offset */ + u64 special_offset; /* loongson_special_attribute struct offset */ + u64 boarddev_table_offset; /* board_devices offset */ +}; + +struct smbios_tables { + u16 vers; /* version of smbios */ + u64 vga_bios; /* vga_bios address */ + struct loongson_params lp; +}; + +struct efi_reset_system_t { + u64 ResetCold; + u64 ResetWarm; + u64 ResetType; + u64 Shutdown; + u64 DoSuspend; /* NULL if not support */ +}; + +struct efi_loongson { + u64 mps; /* MPS table */ + u64 acpi; /* ACPI table (IA64 ext 0.71) */ + u64 acpi20; /* ACPI table (ACPI 2.0) */ + struct smbios_tables smbios; /* SM BIOS table */ + u64 sal_systab; /* SAL system table */ + u64 boot_info; /* boot info table */ +}; + +struct boot_params { + struct efi_loongson efi; + struct efi_reset_system_t reset_system; +}; + +struct loongson_system_configuration { + u32 nr_cpus; + enum loongson_cpu_type cputype; + u64 ht_control_base; + u64 pci_mem_start_addr; + u64 pci_mem_end_addr; + u64 pci_io_base; + u64 restart_addr; + u64 poweroff_addr; + u64 suspend_addr; + u64 vgabios_addr; + u32 dma_mask_bits; +}; + +extern struct efi_memory_map_loongson *loongson_memmap; +extern struct loongson_system_configuration loongson_sysconf; +#endif diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h index 1a05d854e34..c0f3ef45c2c 100644 --- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h @@ -8,9 +8,9 @@ * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org> * * reference: /proc/cpuinfo, - * arch/mips/kernel/cpu-probe.c(cpu_probe_legacy), - * arch/mips/kernel/proc.c(show_cpuinfo), - * loongson2f user manual. + * arch/mips/kernel/cpu-probe.c(cpu_probe_legacy), + * arch/mips/kernel/proc.c(show_cpuinfo), + * loongson2f user manual. */ #ifndef __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H @@ -37,7 +37,7 @@ #define cpu_has_fpu 1 #define cpu_has_ic_fills_f_dc 0 #define cpu_has_inclusive_pcaches 1 -#define cpu_has_llsc 1 +#define cpu_has_llsc 1 #define cpu_has_mcheck 0 #define cpu_has_mdmx 0 #define cpu_has_mips16 0 @@ -57,5 +57,6 @@ #define cpu_has_vint 0 #define cpu_has_vtag_icache 0 #define cpu_has_watch 1 +#define cpu_has_local_ebase 0 #endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h index 2a8e2bb5d53..a0ee0cb775a 100644 --- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h @@ -5,8 +5,8 @@ * Author : jlliu <liujl@lemote.com> */ -#ifndef _CS5536_H -#define _CS5536_H +#ifndef _CS5536_H +#define _CS5536_H #include <linux/types.h> @@ -16,237 +16,237 @@ extern void _wrmsr(u32 msr, u32 hi, u32 lo); /* * MSR module base */ -#define CS5536_SB_MSR_BASE (0x00000000) -#define CS5536_GLIU_MSR_BASE (0x10000000) -#define CS5536_ILLEGAL_MSR_BASE (0x20000000) -#define CS5536_USB_MSR_BASE (0x40000000) -#define CS5536_IDE_MSR_BASE (0x60000000) -#define CS5536_DIVIL_MSR_BASE (0x80000000) -#define CS5536_ACC_MSR_BASE (0xa0000000) -#define CS5536_UNUSED_MSR_BASE (0xc0000000) -#define CS5536_GLCP_MSR_BASE (0xe0000000) +#define CS5536_SB_MSR_BASE (0x00000000) +#define CS5536_GLIU_MSR_BASE (0x10000000) +#define CS5536_ILLEGAL_MSR_BASE (0x20000000) +#define CS5536_USB_MSR_BASE (0x40000000) +#define CS5536_IDE_MSR_BASE (0x60000000) +#define CS5536_DIVIL_MSR_BASE (0x80000000) +#define CS5536_ACC_MSR_BASE (0xa0000000) +#define CS5536_UNUSED_MSR_BASE (0xc0000000) +#define CS5536_GLCP_MSR_BASE (0xe0000000) -#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset)) -#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset)) -#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset)) -#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset)) -#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset)) -#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset)) -#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset)) -#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset)) -#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset)) +#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset)) +#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset)) +#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset)) +#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset)) +#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset)) +#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset)) +#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset)) +#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset)) +#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset)) /* * BAR SPACE OF VIRTUAL PCI : * range for pci probe use, length is the actual size. */ /* IO space for all DIVIL modules */ -#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */ -#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */ -#define CS5536_SMB_RANGE 0xfffffff8 -#define CS5536_SMB_LENGTH 0x08 -#define CS5536_GPIO_RANGE 0xffffff00 -#define CS5536_GPIO_LENGTH 0x100 -#define CS5536_MFGPT_RANGE 0xffffffc0 -#define CS5536_MFGPT_LENGTH 0x40 -#define CS5536_ACPI_RANGE 0xffffffe0 -#define CS5536_ACPI_LENGTH 0x20 -#define CS5536_PMS_RANGE 0xffffff80 -#define CS5536_PMS_LENGTH 0x80 +#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */ +#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */ +#define CS5536_SMB_RANGE 0xfffffff8 +#define CS5536_SMB_LENGTH 0x08 +#define CS5536_GPIO_RANGE 0xffffff00 +#define CS5536_GPIO_LENGTH 0x100 +#define CS5536_MFGPT_RANGE 0xffffffc0 +#define CS5536_MFGPT_LENGTH 0x40 +#define CS5536_ACPI_RANGE 0xffffffe0 +#define CS5536_ACPI_LENGTH 0x20 +#define CS5536_PMS_RANGE 0xffffff80 +#define CS5536_PMS_LENGTH 0x80 /* IO space for IDE */ -#define CS5536_IDE_RANGE 0xfffffff0 -#define CS5536_IDE_LENGTH 0x10 +#define CS5536_IDE_RANGE 0xfffffff0 +#define CS5536_IDE_LENGTH 0x10 /* IO space for ACC */ -#define CS5536_ACC_RANGE 0xffffff80 -#define CS5536_ACC_LENGTH 0x80 +#define CS5536_ACC_RANGE 0xffffff80 +#define CS5536_ACC_LENGTH 0x80 /* MEM space for ALL USB modules */ -#define CS5536_OHCI_RANGE 0xfffff000 -#define CS5536_OHCI_LENGTH 0x1000 -#define CS5536_EHCI_RANGE 0xfffff000 -#define CS5536_EHCI_LENGTH 0x1000 +#define CS5536_OHCI_RANGE 0xfffff000 +#define CS5536_OHCI_LENGTH 0x1000 +#define CS5536_EHCI_RANGE 0xfffff000 +#define CS5536_EHCI_LENGTH 0x1000 /* * PCI MSR ACCESS */ -#define PCI_MSR_CTRL 0xF0 -#define PCI_MSR_ADDR 0xF4 -#define PCI_MSR_DATA_LO 0xF8 -#define PCI_MSR_DATA_HI 0xFC +#define PCI_MSR_CTRL 0xF0 +#define PCI_MSR_ADDR 0xF4 +#define PCI_MSR_DATA_LO 0xF8 +#define PCI_MSR_DATA_HI 0xFC /**************** MSR *****************************/ /* * GLIU STANDARD MSR */ -#define GLIU_CAP 0x00 -#define GLIU_CONFIG 0x01 -#define GLIU_SMI 0x02 -#define GLIU_ERROR 0x03 -#define GLIU_PM 0x04 -#define GLIU_DIAG 0x05 +#define GLIU_CAP 0x00 +#define GLIU_CONFIG 0x01 +#define GLIU_SMI 0x02 +#define GLIU_ERROR 0x03 +#define GLIU_PM 0x04 +#define GLIU_DIAG 0x05 /* * GLIU SPEC. MSR */ -#define GLIU_P2D_BM0 0x20 -#define GLIU_P2D_BM1 0x21 -#define GLIU_P2D_BM2 0x22 -#define GLIU_P2D_BMK0 0x23 -#define GLIU_P2D_BMK1 0x24 -#define GLIU_P2D_BM3 0x25 -#define GLIU_P2D_BM4 0x26 -#define GLIU_COH 0x80 -#define GLIU_PAE 0x81 -#define GLIU_ARB 0x82 -#define GLIU_ASMI 0x83 -#define GLIU_AERR 0x84 -#define GLIU_DEBUG 0x85 -#define GLIU_PHY_CAP 0x86 -#define GLIU_NOUT_RESP 0x87 -#define GLIU_NOUT_WDATA 0x88 -#define GLIU_WHOAMI 0x8B -#define GLIU_SLV_DIS 0x8C -#define GLIU_IOD_BM0 0xE0 -#define GLIU_IOD_BM1 0xE1 -#define GLIU_IOD_BM2 0xE2 -#define GLIU_IOD_BM3 0xE3 -#define GLIU_IOD_BM4 0xE4 -#define GLIU_IOD_BM5 0xE5 -#define GLIU_IOD_BM6 0xE6 -#define GLIU_IOD_BM7 0xE7 -#define GLIU_IOD_BM8 0xE8 -#define GLIU_IOD_BM9 0xE9 -#define GLIU_IOD_SC0 0xEA -#define GLIU_IOD_SC1 0xEB -#define GLIU_IOD_SC2 0xEC -#define GLIU_IOD_SC3 0xED -#define GLIU_IOD_SC4 0xEE -#define GLIU_IOD_SC5 0xEF -#define GLIU_IOD_SC6 0xF0 -#define GLIU_IOD_SC7 0xF1 +#define GLIU_P2D_BM0 0x20 +#define GLIU_P2D_BM1 0x21 +#define GLIU_P2D_BM2 0x22 +#define GLIU_P2D_BMK0 0x23 +#define GLIU_P2D_BMK1 0x24 +#define GLIU_P2D_BM3 0x25 +#define GLIU_P2D_BM4 0x26 +#define GLIU_COH 0x80 +#define GLIU_PAE 0x81 +#define GLIU_ARB 0x82 +#define GLIU_ASMI 0x83 +#define GLIU_AERR 0x84 +#define GLIU_DEBUG 0x85 +#define GLIU_PHY_CAP 0x86 +#define GLIU_NOUT_RESP 0x87 +#define GLIU_NOUT_WDATA 0x88 +#define GLIU_WHOAMI 0x8B +#define GLIU_SLV_DIS 0x8C +#define GLIU_IOD_BM0 0xE0 +#define GLIU_IOD_BM1 0xE1 +#define GLIU_IOD_BM2 0xE2 +#define GLIU_IOD_BM3 0xE3 +#define GLIU_IOD_BM4 0xE4 +#define GLIU_IOD_BM5 0xE5 +#define GLIU_IOD_BM6 0xE6 +#define GLIU_IOD_BM7 0xE7 +#define GLIU_IOD_BM8 0xE8 +#define GLIU_IOD_BM9 0xE9 +#define GLIU_IOD_SC0 0xEA +#define GLIU_IOD_SC1 0xEB +#define GLIU_IOD_SC2 0xEC +#define GLIU_IOD_SC3 0xED +#define GLIU_IOD_SC4 0xEE +#define GLIU_IOD_SC5 0xEF +#define GLIU_IOD_SC6 0xF0 +#define GLIU_IOD_SC7 0xF1 /* * SB STANDARD */ -#define SB_CAP 0x00 -#define SB_CONFIG 0x01 -#define SB_SMI 0x02 -#define SB_ERROR 0x03 -#define SB_MAR_ERR_EN 0x00000001 -#define SB_TAR_ERR_EN 0x00000002 -#define SB_RSVD_BIT1 0x00000004 -#define SB_EXCEP_ERR_EN 0x00000008 -#define SB_SYSE_ERR_EN 0x00000010 -#define SB_PARE_ERR_EN 0x00000020 -#define SB_TAS_ERR_EN 0x00000040 -#define SB_MAR_ERR_FLAG 0x00010000 -#define SB_TAR_ERR_FLAG 0x00020000 -#define SB_RSVD_BIT2 0x00040000 -#define SB_EXCEP_ERR_FLAG 0x00080000 -#define SB_SYSE_ERR_FLAG 0x00100000 -#define SB_PARE_ERR_FLAG 0x00200000 -#define SB_TAS_ERR_FLAG 0x00400000 -#define SB_PM 0x04 -#define SB_DIAG 0x05 +#define SB_CAP 0x00 +#define SB_CONFIG 0x01 +#define SB_SMI 0x02 +#define SB_ERROR 0x03 +#define SB_MAR_ERR_EN 0x00000001 +#define SB_TAR_ERR_EN 0x00000002 +#define SB_RSVD_BIT1 0x00000004 +#define SB_EXCEP_ERR_EN 0x00000008 +#define SB_SYSE_ERR_EN 0x00000010 +#define SB_PARE_ERR_EN 0x00000020 +#define SB_TAS_ERR_EN 0x00000040 +#define SB_MAR_ERR_FLAG 0x00010000 +#define SB_TAR_ERR_FLAG 0x00020000 +#define SB_RSVD_BIT2 0x00040000 +#define SB_EXCEP_ERR_FLAG 0x00080000 +#define SB_SYSE_ERR_FLAG 0x00100000 +#define SB_PARE_ERR_FLAG 0x00200000 +#define SB_TAS_ERR_FLAG 0x00400000 +#define SB_PM 0x04 +#define SB_DIAG 0x05 /* * SB SPEC. */ -#define SB_CTRL 0x10 -#define SB_R0 0x20 -#define SB_R1 0x21 -#define SB_R2 0x22 -#define SB_R3 0x23 -#define SB_R4 0x24 -#define SB_R5 0x25 -#define SB_R6 0x26 -#define SB_R7 0x27 -#define SB_R8 0x28 -#define SB_R9 0x29 -#define SB_R10 0x2A -#define SB_R11 0x2B -#define SB_R12 0x2C -#define SB_R13 0x2D -#define SB_R14 0x2E -#define SB_R15 0x2F +#define SB_CTRL 0x10 +#define SB_R0 0x20 +#define SB_R1 0x21 +#define SB_R2 0x22 +#define SB_R3 0x23 +#define SB_R4 0x24 +#define SB_R5 0x25 +#define SB_R6 0x26 +#define SB_R7 0x27 +#define SB_R8 0x28 +#define SB_R9 0x29 +#define SB_R10 0x2A +#define SB_R11 0x2B +#define SB_R12 0x2C +#define SB_R13 0x2D +#define SB_R14 0x2E +#define SB_R15 0x2F /* * GLCP STANDARD */ -#define GLCP_CAP 0x00 -#define GLCP_CONFIG 0x01 -#define GLCP_SMI 0x02 -#define GLCP_ERROR 0x03 -#define GLCP_PM 0x04 -#define GLCP_DIAG 0x05 +#define GLCP_CAP 0x00 +#define GLCP_CONFIG 0x01 +#define GLCP_SMI 0x02 +#define GLCP_ERROR 0x03 +#define GLCP_PM 0x04 +#define GLCP_DIAG 0x05 /* * GLCP SPEC. */ -#define GLCP_CLK_DIS_DELAY 0x08 -#define GLCP_PM_CLK_DISABLE 0x09 -#define GLCP_GLB_PM 0x0B -#define GLCP_DBG_OUT 0x0C -#define GLCP_RSVD1 0x0D -#define GLCP_SOFT_COM 0x0E -#define SOFT_BAR_SMB_FLAG 0x00000001 -#define SOFT_BAR_GPIO_FLAG 0x00000002 -#define SOFT_BAR_MFGPT_FLAG 0x00000004 -#define SOFT_BAR_IRQ_FLAG 0x00000008 -#define SOFT_BAR_PMS_FLAG 0x00000010 -#define SOFT_BAR_ACPI_FLAG 0x00000020 -#define SOFT_BAR_IDE_FLAG 0x00000400 -#define SOFT_BAR_ACC_FLAG 0x00000800 -#define SOFT_BAR_OHCI_FLAG 0x00001000 -#define SOFT_BAR_EHCI_FLAG 0x00002000 -#define GLCP_RSVD2 0x0F -#define GLCP_CLK_OFF 0x10 -#define GLCP_CLK_ACTIVE 0x11 -#define GLCP_CLK_DISABLE 0x12 -#define GLCP_CLK4ACK 0x13 -#define GLCP_SYS_RST 0x14 -#define GLCP_RSVD3 0x15 -#define GLCP_DBG_CLK_CTRL 0x16 -#define GLCP_CHIP_REV_ID 0x17 +#define GLCP_CLK_DIS_DELAY 0x08 +#define GLCP_PM_CLK_DISABLE 0x09 +#define GLCP_GLB_PM 0x0B +#define GLCP_DBG_OUT 0x0C +#define GLCP_RSVD1 0x0D +#define GLCP_SOFT_COM 0x0E +#define SOFT_BAR_SMB_FLAG 0x00000001 +#define SOFT_BAR_GPIO_FLAG 0x00000002 +#define SOFT_BAR_MFGPT_FLAG 0x00000004 +#define SOFT_BAR_IRQ_FLAG 0x00000008 +#define SOFT_BAR_PMS_FLAG 0x00000010 +#define SOFT_BAR_ACPI_FLAG 0x00000020 +#define SOFT_BAR_IDE_FLAG 0x00000400 +#define SOFT_BAR_ACC_FLAG 0x00000800 +#define SOFT_BAR_OHCI_FLAG 0x00001000 +#define SOFT_BAR_EHCI_FLAG 0x00002000 +#define GLCP_RSVD2 0x0F +#define GLCP_CLK_OFF 0x10 +#define GLCP_CLK_ACTIVE 0x11 +#define GLCP_CLK_DISABLE 0x12 +#define GLCP_CLK4ACK 0x13 +#define GLCP_SYS_RST 0x14 +#define GLCP_RSVD3 0x15 +#define GLCP_DBG_CLK_CTRL 0x16 +#define GLCP_CHIP_REV_ID 0x17 /* PIC */ -#define PIC_YSEL_LOW 0x20 -#define PIC_YSEL_LOW_USB_SHIFT 8 -#define PIC_YSEL_LOW_ACC_SHIFT 16 -#define PIC_YSEL_LOW_FLASH_SHIFT 24 -#define PIC_YSEL_HIGH 0x21 -#define PIC_ZSEL_LOW 0x22 -#define PIC_ZSEL_HIGH 0x23 -#define PIC_IRQM_PRIM 0x24 -#define PIC_IRQM_LPC 0x25 -#define PIC_XIRR_STS_LOW 0x26 -#define PIC_XIRR_STS_HIGH 0x27 -#define PCI_SHDW 0x34 +#define PIC_YSEL_LOW 0x20 +#define PIC_YSEL_LOW_USB_SHIFT 8 +#define PIC_YSEL_LOW_ACC_SHIFT 16 +#define PIC_YSEL_LOW_FLASH_SHIFT 24 +#define PIC_YSEL_HIGH 0x21 +#define PIC_ZSEL_LOW 0x22 +#define PIC_ZSEL_HIGH 0x23 +#define PIC_IRQM_PRIM 0x24 +#define PIC_IRQM_LPC 0x25 +#define PIC_XIRR_STS_LOW 0x26 +#define PIC_XIRR_STS_HIGH 0x27 +#define PCI_SHDW 0x34 /* * DIVIL STANDARD */ -#define DIVIL_CAP 0x00 -#define DIVIL_CONFIG 0x01 -#define DIVIL_SMI 0x02 -#define DIVIL_ERROR 0x03 -#define DIVIL_PM 0x04 -#define DIVIL_DIAG 0x05 +#define DIVIL_CAP 0x00 +#define DIVIL_CONFIG 0x01 +#define DIVIL_SMI 0x02 +#define DIVIL_ERROR 0x03 +#define DIVIL_PM 0x04 +#define DIVIL_DIAG 0x05 /* * DIVIL SPEC. */ -#define DIVIL_LBAR_IRQ 0x08 -#define DIVIL_LBAR_KEL 0x09 -#define DIVIL_LBAR_SMB 0x0B -#define DIVIL_LBAR_GPIO 0x0C -#define DIVIL_LBAR_MFGPT 0x0D -#define DIVIL_LBAR_ACPI 0x0E -#define DIVIL_LBAR_PMS 0x0F -#define DIVIL_LEG_IO 0x14 -#define DIVIL_BALL_OPTS 0x15 -#define DIVIL_SOFT_IRQ 0x16 -#define DIVIL_SOFT_RESET 0x17 +#define DIVIL_LBAR_IRQ 0x08 +#define DIVIL_LBAR_KEL 0x09 +#define DIVIL_LBAR_SMB 0x0B +#define DIVIL_LBAR_GPIO 0x0C +#define DIVIL_LBAR_MFGPT 0x0D +#define DIVIL_LBAR_ACPI 0x0E +#define DIVIL_LBAR_PMS 0x0F +#define DIVIL_LEG_IO 0x14 +#define DIVIL_BALL_OPTS 0x15 +#define DIVIL_SOFT_IRQ 0x16 +#define DIVIL_SOFT_RESET 0x17 /* MFGPT */ #define MFGPT_IRQ 0x28 @@ -254,52 +254,52 @@ extern void _wrmsr(u32 msr, u32 hi, u32 lo); /* * IDE STANDARD */ -#define IDE_CAP 0x00 -#define IDE_CONFIG 0x01 -#define IDE_SMI 0x02 -#define IDE_ERROR 0x03 -#define IDE_PM 0x04 -#define IDE_DIAG 0x05 +#define IDE_CAP 0x00 +#define IDE_CONFIG 0x01 +#define IDE_SMI 0x02 +#define IDE_ERROR 0x03 +#define IDE_PM 0x04 +#define IDE_DIAG 0x05 /* * IDE SPEC. */ -#define IDE_IO_BAR 0x08 -#define IDE_CFG 0x10 -#define IDE_DTC 0x12 -#define IDE_CAST 0x13 -#define IDE_ETC 0x14 -#define IDE_INTERNAL_PM 0x15 +#define IDE_IO_BAR 0x08 +#define IDE_CFG 0x10 +#define IDE_DTC 0x12 +#define IDE_CAST 0x13 +#define IDE_ETC 0x14 +#define IDE_INTERNAL_PM 0x15 /* * ACC STANDARD */ -#define ACC_CAP 0x00 -#define ACC_CONFIG 0x01 -#define ACC_SMI 0x02 -#define ACC_ERROR 0x03 -#define ACC_PM 0x04 -#define ACC_DIAG 0x05 +#define ACC_CAP 0x00 +#define ACC_CONFIG 0x01 +#define ACC_SMI 0x02 +#define ACC_ERROR 0x03 +#define ACC_PM 0x04 +#define ACC_DIAG 0x05 /* * USB STANDARD */ -#define USB_CAP 0x00 -#define USB_CONFIG 0x01 -#define USB_SMI 0x02 -#define USB_ERROR 0x03 -#define USB_PM 0x04 -#define USB_DIAG 0x05 +#define USB_CAP 0x00 +#define USB_CONFIG 0x01 +#define USB_SMI 0x02 +#define USB_ERROR 0x03 +#define USB_PM 0x04 +#define USB_DIAG 0x05 /* * USB SPEC. */ -#define USB_OHCI 0x08 -#define USB_EHCI 0x09 +#define USB_OHCI 0x08 +#define USB_EHCI 0x09 /****************** NATIVE ***************************/ /* GPIO : I/O SPACE; REG : 32BITS */ -#define GPIOL_OUT_VAL 0x00 -#define GPIOL_OUT_EN 0x04 +#define GPIOL_OUT_VAL 0x00 +#define GPIOL_OUT_EN 0x04 #endif /* _CS5536_H */ diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h index 4b493d6772c..021d0172dad 100644 --- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h @@ -25,7 +25,7 @@ static inline void __maybe_unused enable_mfgpt0_counter(void) #endif #define MFGPT_TICK_RATE 14318000 -#define COMPARE ((MFGPT_TICK_RATE + HZ/2) / HZ) +#define COMPARE ((MFGPT_TICK_RATE + HZ/2) / HZ) #define MFGPT_BASE mfgpt_base #define MFGPT0_CMP2 (MFGPT_BASE + 2) diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h index 0dca9c89ee7..8a7ecb4d5c6 100644 --- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h @@ -8,8 +8,8 @@ * Author : jlliu, liujl@lemote.com */ -#ifndef _CS5536_PCI_H -#define _CS5536_PCI_H +#ifndef _CS5536_PCI_H +#define _CS5536_PCI_H #include <linux/types.h> #include <linux/pci_regs.h> @@ -17,20 +17,20 @@ extern void cs5536_pci_conf_write4(int function, int reg, u32 value); extern u32 cs5536_pci_conf_read4(int function, int reg); -#define CS5536_ACC_INTR 9 -#define CS5536_IDE_INTR 14 -#define CS5536_USB_INTR 11 -#define CS5536_MFGPT_INTR 5 -#define CS5536_UART1_INTR 4 -#define CS5536_UART2_INTR 3 +#define CS5536_ACC_INTR 9 +#define CS5536_IDE_INTR 14 +#define CS5536_USB_INTR 11 +#define CS5536_MFGPT_INTR 5 +#define CS5536_UART1_INTR 4 +#define CS5536_UART2_INTR 3 /************** PCI BUS DEVICE FUNCTION ***************/ /* * PCI bus device function */ -#define PCI_BUS_CS5536 0 -#define PCI_IDSEL_CS5536 14 +#define PCI_BUS_CS5536 0 +#define PCI_IDSEL_CS5536 14 /********** STANDARD PCI-2.2 EXPANSION ****************/ @@ -45,21 +45,21 @@ extern u32 cs5536_pci_conf_read4(int function, int reg); (((mod_dev_id) << 16) | (sys_vendor_id)) /* VENDOR ID */ -#define CS5536_VENDOR_ID 0x1022 +#define CS5536_VENDOR_ID 0x1022 /* DEVICE ID */ -#define CS5536_ISA_DEVICE_ID 0x2090 -#define CS5536_IDE_DEVICE_ID 0x209a -#define CS5536_ACC_DEVICE_ID 0x2093 -#define CS5536_OHCI_DEVICE_ID 0x2094 -#define CS5536_EHCI_DEVICE_ID 0x2095 +#define CS5536_ISA_DEVICE_ID 0x2090 +#define CS5536_IDE_DEVICE_ID 0x209a +#define CS5536_ACC_DEVICE_ID 0x2093 +#define CS5536_OHCI_DEVICE_ID 0x2094 +#define CS5536_EHCI_DEVICE_ID 0x2095 /* CLASS CODE : CLASS SUB-CLASS INTERFACE */ -#define CS5536_ISA_CLASS_CODE 0x060100 +#define CS5536_ISA_CLASS_CODE 0x060100 #define CS5536_IDE_CLASS_CODE 0x010180 -#define CS5536_ACC_CLASS_CODE 0x040100 -#define CS5536_OHCI_CLASS_CODE 0x0C0310 -#define CS5536_EHCI_CLASS_CODE 0x0C0320 +#define CS5536_ACC_CLASS_CODE 0x040100 +#define CS5536_OHCI_CLASS_CODE 0x0C0310 +#define CS5536_EHCI_CLASS_CODE 0x0C0320 /* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */ @@ -67,40 +67,40 @@ extern u32 cs5536_pci_conf_read4(int function, int reg); ((PCI_NONE_BIST << 24) | ((header_type) << 16) \ | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE); -#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */ -#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */ -#define PCI_NORMAL_HEADER_TYPE 0x00 -#define PCI_NORMAL_LATENCY_TIMER 0x00 -#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */ +#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */ +#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */ +#define PCI_NORMAL_HEADER_TYPE 0x00 +#define PCI_NORMAL_LATENCY_TIMER 0x00 +#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */ /* BAR */ -#define PCI_BAR0_REG 0x10 -#define PCI_BAR1_REG 0x14 -#define PCI_BAR2_REG 0x18 -#define PCI_BAR3_REG 0x1c -#define PCI_BAR4_REG 0x20 -#define PCI_BAR5_REG 0x24 -#define PCI_BAR_COUNT 6 -#define PCI_BAR_RANGE_MASK 0xFFFFFFFF +#define PCI_BAR0_REG 0x10 +#define PCI_BAR1_REG 0x14 +#define PCI_BAR2_REG 0x18 +#define PCI_BAR3_REG 0x1c +#define PCI_BAR4_REG 0x20 +#define PCI_BAR5_REG 0x24 +#define PCI_BAR_COUNT 6 +#define PCI_BAR_RANGE_MASK 0xFFFFFFFF /* CARDBUS CIS POINTER */ -#define PCI_CARDBUS_CIS_POINTER 0x00000000 +#define PCI_CARDBUS_CIS_POINTER 0x00000000 -/* SUBSYSTEM VENDOR ID */ -#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID +/* SUBSYSTEM VENDOR ID */ +#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID /* SUBSYSTEM ID */ -#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID -#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID -#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID -#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID -#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID +#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID +#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID +#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID +#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID +#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID /* EXPANSION ROM BAR */ -#define PCI_EXPANSION_ROM_BAR 0x00000000 +#define PCI_EXPANSION_ROM_BAR 0x00000000 /* CAPABILITIES POINTER */ -#define PCI_CAPLIST_POINTER 0x00000000 +#define PCI_CAPLIST_POINTER 0x00000000 #define PCI_CAPLIST_USB_POINTER 0x40 /* INTERRUPT */ @@ -108,46 +108,46 @@ extern u32 cs5536_pci_conf_read4(int function, int reg); ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \ ((pin) << 8) | (mod_intr)) -#define PCI_MAX_LATENCY 0x40 -#define PCI_MIN_GRANT 0x00 -#define PCI_DEFAULT_PIN 0x01 +#define PCI_MAX_LATENCY 0x40 +#define PCI_MIN_GRANT 0x00 +#define PCI_DEFAULT_PIN 0x01 /*********** EXPANSION PCI REG ************************/ /* * ISA EXPANSION */ -#define PCI_UART1_INT_REG 0x50 +#define PCI_UART1_INT_REG 0x50 #define PCI_UART2_INT_REG 0x54 -#define PCI_ISA_FIXUP_REG 0x58 +#define PCI_ISA_FIXUP_REG 0x58 /* * IDE EXPANSION */ -#define PCI_IDE_CFG_REG 0x40 -#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF -#define PCI_IDE_DTC_REG 0x48 -#define PCI_IDE_CAST_REG 0x4C -#define PCI_IDE_ETC_REG 0x50 -#define PCI_IDE_PM_REG 0x54 -#define PCI_IDE_INT_REG 0x60 +#define PCI_IDE_CFG_REG 0x40 +#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF +#define PCI_IDE_DTC_REG 0x48 +#define PCI_IDE_CAST_REG 0x4C +#define PCI_IDE_ETC_REG 0x50 +#define PCI_IDE_PM_REG 0x54 +#define PCI_IDE_INT_REG 0x60 /* * ACC EXPANSION */ -#define PCI_ACC_INT_REG 0x50 +#define PCI_ACC_INT_REG 0x50 /* * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI */ -#define PCI_OHCI_PM_REG 0x40 -#define PCI_OHCI_INT_REG 0x50 +#define PCI_OHCI_PM_REG 0x40 +#define PCI_OHCI_INT_REG 0x50 /* * EHCI EXPANSION */ -#define PCI_EHCI_LEGSMIEN_REG 0x50 -#define PCI_EHCI_LEGSMISTS_REG 0x54 -#define PCI_EHCI_FLADJ_REG 0x60 +#define PCI_EHCI_LEGSMIEN_REG 0x50 +#define PCI_EHCI_LEGSMISTS_REG 0x54 +#define PCI_EHCI_FLADJ_REG 0x60 #endif /* _CS5536_PCI_H_ */ diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h index 21c4ecedebe..1f17c1815ee 100644 --- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h @@ -5,8 +5,8 @@ * Author: Wu Zhangjin <wuzhangjin@gmail.com> */ -#ifndef _CS5536_VSM_H -#define _CS5536_VSM_H +#ifndef _CS5536_VSM_H +#define _CS5536_VSM_H #include <linux/types.h> diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h index e1433055fe9..6a902751cc7 100644 --- a/arch/mips/include/asm/mach-loongson/dma-coherence.h +++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h @@ -11,24 +11,40 @@ #ifndef __ASM_MACH_LOONGSON_DMA_COHERENCE_H #define __ASM_MACH_LOONGSON_DMA_COHERENCE_H +#ifdef CONFIG_SWIOTLB +#include <linux/swiotlb.h> +#endif + struct device; +extern dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr); +extern phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr); static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) { +#ifdef CONFIG_CPU_LOONGSON3 + return virt_to_phys(addr); +#else return virt_to_phys(addr) | 0x80000000; +#endif } static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) { +#ifdef CONFIG_CPU_LOONGSON3 + return page_to_phys(page); +#else return page_to_phys(page) | 0x80000000; +#endif } static inline unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) { -#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) +#if defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_64BIT) + return dma_addr; +#elif defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff); #else return dma_addr & 0x7fffffff; @@ -53,19 +69,13 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 1; } -static inline void plat_extra_sync_for_device(struct device *dev) -{ -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - static inline int plat_device_is_coherent(struct device *dev) { +#ifdef CONFIG_DMA_NONCOHERENT return 0; +#else + return 1; +#endif /* CONFIG_DMA_NONCOHERENT */ } #endif /* __ASM_MACH_LOONGSON_DMA_COHERENCE_H */ diff --git a/arch/mips/include/asm/mach-loongson/gpio.h b/arch/mips/include/asm/mach-loongson/gpio.h index e30e73d443d..211a7b7138f 100644 --- a/arch/mips/include/asm/mach-loongson/gpio.h +++ b/arch/mips/include/asm/mach-loongson/gpio.h @@ -10,8 +10,8 @@ * (at your option) any later version. */ -#ifndef __STLS2F_GPIO_H -#define __STLS2F_GPIO_H +#ifndef __STLS2F_GPIO_H +#define __STLS2F_GPIO_H #include <asm-generic/gpio.h> diff --git a/arch/mips/include/asm/mach-loongson/irq.h b/arch/mips/include/asm/mach-loongson/irq.h new file mode 100644 index 00000000000..34560bda662 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/irq.h @@ -0,0 +1,44 @@ +#ifndef __ASM_MACH_LOONGSON_IRQ_H_ +#define __ASM_MACH_LOONGSON_IRQ_H_ + +#include <boot_param.h> + +#ifdef CONFIG_CPU_LOONGSON3 + +/* cpu core interrupt numbers */ +#define MIPS_CPU_IRQ_BASE 56 + +#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */ +#define LOONGSON_HT1_IRQ (MIPS_CPU_IRQ_BASE + 3) /* HT1 */ +#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */ + +#define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base +#define LOONGSON_HT1_INT_VECTOR_BASE (LOONGSON_HT1_CFG_BASE + 0x80) +#define LOONGSON_HT1_INT_EN_BASE (LOONGSON_HT1_CFG_BASE + 0xa0) +#define LOONGSON_HT1_INT_VECTOR(n) \ + LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * (n)) +#define LOONGSON_HT1_INTN_EN(n) \ + LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * (n)) + +#define LOONGSON_INT_ROUTER_OFFSET 0x1400 +#define LOONGSON_INT_ROUTER_INTEN \ + LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24) +#define LOONGSON_INT_ROUTER_INTENSET \ + LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28) +#define LOONGSON_INT_ROUTER_INTENCLR \ + LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c) +#define LOONGSON_INT_ROUTER_ENTRY(n) \ + LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n) +#define LOONGSON_INT_ROUTER_LPC LOONGSON_INT_ROUTER_ENTRY(0x0a) +#define LOONGSON_INT_ROUTER_HT1(n) LOONGSON_INT_ROUTER_ENTRY(n + 0x18) + +#define LOONGSON_INT_CORE0_INT0 0x11 /* route to int 0 of core 0 */ +#define LOONGSON_INT_CORE0_INT1 0x21 /* route to int 1 of core 0 */ + +#endif + +extern void fixup_irqs(void); +extern void loongson3_ipi_interrupt(struct pt_regs *regs); + +#include_next <irq.h> +#endif /* __ASM_MACH_LOONGSON_IRQ_H_ */ diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index 5222a007bc2..f3fd1eb8e3d 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -2,8 +2,8 @@ * Copyright (C) 2009 Lemote, Inc. * Author: Wu Zhangjin <wuzhangjin@gmail.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ @@ -15,6 +15,7 @@ #include <linux/init.h> #include <linux/irq.h> #include <linux/kconfig.h> +#include <boot_param.h> /* loongson internal northbridge initialization */ extern void bonito_irq_init(void); @@ -24,8 +25,9 @@ extern void mach_prepare_reboot(void); extern void mach_prepare_shutdown(void); /* environment arguments from bootloader */ -extern unsigned long cpu_clock_freq; -extern unsigned long memsize, highmemsize; +extern u32 cpu_clock_freq; +extern u32 memsize, highmemsize; +extern struct plat_smp_ops loongson3_smp_ops; /* loongson-specific command line, env and memory initialization */ extern void __init prom_init_memory(void); @@ -52,7 +54,7 @@ extern void mach_irq_dispatch(unsigned int pending); extern int mach_i8259_irq(void); /* We need this in some places... */ -#define delay() ({ \ +#define delay() ({ \ int x; \ for (x = 0; x < 100000; x++) \ __asm__ __volatile__(""); \ @@ -61,6 +63,12 @@ extern int mach_i8259_irq(void); #define LOONGSON_REG(x) \ (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x))) +#define LOONGSON3_REG8(base, x) \ + (*(volatile u8 *)((char *)TO_UNCAC(base) + (x))) + +#define LOONGSON3_REG32(base, x) \ + (*(volatile u32 *)((char *)TO_UNCAC(base) + (x))) + #define LOONGSON_IRQ_BASE 32 #define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */ @@ -82,13 +90,17 @@ static inline void do_perfcnt_IRQ(void) #define LOONGSON_BOOT_BASE 0x1fc00000 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */ -#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1) -#define LOONGSON_REG_BASE 0x1fe00000 -#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ +#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1) +#define LOONGSON_REG_BASE 0x1fe00000 +#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ #define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1) +/* Loongson-3 specific registers */ +#define LOONGSON3_REG_BASE 0x3ff00000 +#define LOONGSON3_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ +#define LOONGSON3_REG_TOP (LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1) -#define LOONGSON_LIO1_BASE 0x1ff00000 -#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */ +#define LOONGSON_LIO1_BASE 0x1ff00000 +#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */ #define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1) #define LOONGSON_PCILO0_BASE 0x10000000 @@ -101,7 +113,13 @@ static inline void do_perfcnt_IRQ(void) #define LOONGSON_PCICFG_BASE 0x1fe80000 #define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */ #define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1) + +#if defined(CONFIG_HT_PCI) +#define LOONGSON_PCIIO_BASE loongson_sysconf.pci_io_base +#else #define LOONGSON_PCIIO_BASE 0x1fd00000 +#endif + #define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */ #define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1) @@ -115,13 +133,13 @@ static inline void do_perfcnt_IRQ(void) #define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x)) #define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00) #define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04) -#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08) +#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08) #define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c) -#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10) -#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14) -#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18) -#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c) -#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20) +#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10) +#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14) +#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18) +#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c) +#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20) #define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30) #define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c) @@ -132,7 +150,7 @@ static inline void do_perfcnt_IRQ(void) #define LOONGSON_PCICMD_MABORT_CLR 0x20000000 #define LOONGSON_PCICMD_MTABORT_CLR 0x10000000 #define LOONGSON_PCICMD_TABORT_CLR 0x08000000 -#define LOONGSON_PCICMD_MPERR_CLR 0x01000000 +#define LOONGSON_PCICMD_MPERR_CLR 0x01000000 #define LOONGSON_PCICMD_PERRRESPEN 0x00000040 #define LOONGSON_PCICMD_ASTEPEN 0x00000080 #define LOONGSON_PCICMD_SERREN 0x00000100 @@ -142,7 +160,7 @@ static inline void do_perfcnt_IRQ(void) /* Loongson h/w Configuration */ #define LOONGSON_GENCFG_OFFSET 0x4 -#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET) +#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET) #define LOONGSON_GENCFG_DEBUGMODE 0x00000001 #define LOONGSON_GENCFG_SNOOPEN 0x00000002 @@ -173,25 +191,25 @@ static inline void do_perfcnt_IRQ(void) /* GPIO Regs - r/w */ -#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c) +#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c) #define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20) /* ICU Configuration Regs - r/w */ #define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24) -#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28) +#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28) #define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c) /* ICU Enable Regs - IntEn & IntISR are r/o. */ -#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30) -#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34) +#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30) +#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34) #define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38) #define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c) /* ICU */ #define LOONGSON_ICU_MBOXES 0x0000000f -#define LOONGSON_ICU_MBOXES_SHIFT 0 +#define LOONGSON_ICU_MBOXES_SHIFT 0 #define LOONGSON_ICU_DMARDY 0x00000010 #define LOONGSON_ICU_DMAEMPTY 0x00000020 #define LOONGSON_ICU_COPYRDY 0x00000040 @@ -212,10 +230,10 @@ static inline void do_perfcnt_IRQ(void) /* PCI prefetch window base & mask */ -#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40) -#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44) -#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48) -#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c) +#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40) +#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44) +#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48) +#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c) /* PCI_Hit*_Sel_* */ @@ -231,6 +249,9 @@ static inline void do_perfcnt_IRQ(void) #define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68) #define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c) +/* Chip Config */ +#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80) + /* pcimap */ #define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f @@ -246,9 +267,6 @@ static inline void do_perfcnt_IRQ(void) #ifdef CONFIG_CPU_SUPPORTS_CPUFREQ #include <linux/cpufreq.h> extern struct cpufreq_frequency_table loongson2_clockmod_table[]; - -/* Chip Config */ -#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80) #endif /* diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h index 43213388c17..1b1f592fa2b 100644 --- a/arch/mips/include/asm/mach-loongson/machine.h +++ b/arch/mips/include/asm/mach-loongson/machine.h @@ -2,8 +2,8 @@ * Copyright (C) 2009 Lemote, Inc. * Author: Wu Zhangjin <wuzhangjin@gmail.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ @@ -24,4 +24,10 @@ #endif +#ifdef CONFIG_LEMOTE_MACH3A + +#define LOONGSON_MACHTYPE MACH_LEMOTE_A1101 + +#endif /* CONFIG_LEMOTE_MACH3A */ + #endif /* __ASM_MACH_LOONGSON_MACHINE_H */ diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h index 3b23ee8647d..f4a36d7dbfa 100644 --- a/arch/mips/include/asm/mach-loongson/mem.h +++ b/arch/mips/include/asm/mach-loongson/mem.h @@ -2,8 +2,8 @@ * Copyright (C) 2009 Lemote, Inc. * Author: Wu Zhangjin <wuzhangjin@gmail.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h index bc99dab4ef6..1212774f66e 100644 --- a/arch/mips/include/asm/mach-loongson/pci.h +++ b/arch/mips/include/asm/mach-loongson/pci.h @@ -40,8 +40,13 @@ extern struct pci_ops loongson_pci_ops; #else /* loongson2f/32bit & loongson2e */ /* this pci memory space is mapped by pcimap in pci.c */ +#ifdef CONFIG_CPU_LOONGSON3 +#define LOONGSON_PCI_MEM_START 0x40000000UL +#define LOONGSON_PCI_MEM_END 0x7effffffUL +#else #define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE #define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2) +#endif /* this is an offset from mips_io_port_base */ #define LOONGSON_PCI_IO_START 0x00004000UL diff --git a/arch/mips/include/asm/mach-loongson/spaces.h b/arch/mips/include/asm/mach-loongson/spaces.h new file mode 100644 index 00000000000..e2506ee9004 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/spaces.h @@ -0,0 +1,9 @@ +#ifndef __ASM_MACH_LOONGSON_SPACES_H_ +#define __ASM_MACH_LOONGSON_SPACES_H_ + +#if defined(CONFIG_64BIT) +#define CAC_BASE _AC(0x9800000000000000, UL) +#endif /* CONFIG_64BIT */ + +#include <asm/mach-generic/spaces.h> +#endif diff --git a/arch/mips/include/asm/mach-loongson1/irq.h b/arch/mips/include/asm/mach-loongson1/irq.h index da96ed42f73..96bfb1c1c73 100644 --- a/arch/mips/include/asm/mach-loongson1/irq.h +++ b/arch/mips/include/asm/mach-loongson1/irq.h @@ -3,8 +3,8 @@ * * IRQ mappings for Loongson 1 * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ diff --git a/arch/mips/include/asm/mach-loongson1/loongson1.h b/arch/mips/include/asm/mach-loongson1/loongson1.h index 4e18e88cebb..5c437c2ba6b 100644 --- a/arch/mips/include/asm/mach-loongson1/loongson1.h +++ b/arch/mips/include/asm/mach-loongson1/loongson1.h @@ -3,8 +3,8 @@ * * Register mappings for Loongson 1 * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h index 718a1228a4f..30c13e508ff 100644 --- a/arch/mips/include/asm/mach-loongson1/platform.h +++ b/arch/mips/include/asm/mach-loongson1/platform.h @@ -1,8 +1,8 @@ /* * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ diff --git a/arch/mips/include/asm/mach-loongson1/prom.h b/arch/mips/include/asm/mach-loongson1/prom.h index b871dc41b8d..34859a4d4ac 100644 --- a/arch/mips/include/asm/mach-loongson1/prom.h +++ b/arch/mips/include/asm/mach-loongson1/prom.h @@ -1,8 +1,8 @@ /* * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h index a81fa3d0dc9..fb6a3ff9318 100644 --- a/arch/mips/include/asm/mach-loongson1/regs-clk.h +++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h @@ -3,8 +3,8 @@ * * Loongson 1 Clock Register Definitions. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ diff --git a/arch/mips/include/asm/mach-loongson1/regs-wdt.h b/arch/mips/include/asm/mach-loongson1/regs-wdt.h index f897de68c52..6574568c208 100644 --- a/arch/mips/include/asm/mach-loongson1/regs-wdt.h +++ b/arch/mips/include/asm/mach-loongson1/regs-wdt.h @@ -3,8 +3,8 @@ * * Loongson 1 watchdog register definitions. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ diff --git a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h index 37e3583a9fd..de3b66a3723 100644 --- a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h @@ -23,8 +23,8 @@ /* #define cpu_has_watch ? */ #define cpu_has_divec 1 #define cpu_has_vce 0 -/* #define cpu_has_cache_cdex_p ? */ -/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ /* #define cpu_has_prefetch ? */ #define cpu_has_mcheck 1 /* #define cpu_has_ejtag ? */ @@ -50,8 +50,8 @@ /* #define cpu_has_watch ? */ #define cpu_has_divec 1 #define cpu_has_vce 0 -/* #define cpu_has_cache_cdex_p ? */ -/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ /* #define cpu_has_prefetch ? */ #define cpu_has_mcheck 1 /* #define cpu_has_ejtag ? */ diff --git a/arch/mips/include/asm/mach-malta/irq.h b/arch/mips/include/asm/mach-malta/irq.h index 9b9da26683c..47cfe64efbb 100644 --- a/arch/mips/include/asm/mach-malta/irq.h +++ b/arch/mips/include/asm/mach-malta/irq.h @@ -2,7 +2,7 @@ #define __ASM_MACH_MIPS_IRQ_H -#define NR_IRQS 256 +#define NR_IRQS 256 #include_next <irq.h> diff --git a/arch/mips/include/asm/mach-malta/kernel-entry-init.h b/arch/mips/include/asm/mach-malta/kernel-entry-init.h index 0b793e7bf67..77eeda77e73 100644 --- a/arch/mips/include/asm/mach-malta/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-malta/kernel-entry-init.h @@ -5,27 +5,104 @@ * * Chris Dearman (chris@mips.com) * Copyright (C) 2007 Mips Technologies, Inc. + * Copyright (C) 2014 Imagination Technologies Ltd. */ #ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H #define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H + /* + * Prepare segments for EVA boot: + * + * This is in case the processor boots in legacy configuration + * (SI_EVAReset is de-asserted and CONFIG5.K == 0) + * + * On entry, t1 is loaded with CP0_CONFIG + * + * ========================= Mappings ============================= + * Virtual memory Physical memory Mapping + * 0x00000000 - 0x7fffffff 0x80000000 - 0xfffffffff MUSUK (kuseg) + * Flat 2GB physical memory + * + * 0x80000000 - 0x9fffffff 0x00000000 - 0x1ffffffff MUSUK (kseg0) + * 0xa0000000 - 0xbf000000 0x00000000 - 0x1ffffffff MUSUK (kseg1) + * 0xc0000000 - 0xdfffffff - MK (kseg2) + * 0xe0000000 - 0xffffffff - MK (kseg3) + * + * + * Lowmem is expanded to 2GB + */ + .macro eva_entry + /* + * Get Config.K0 value and use it to program + * the segmentation registers + */ + andi t1, 0x7 /* CCA */ + move t2, t1 + ins t2, t1, 16, 3 + /* SegCtl0 */ + li t0, ((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) | \ + (0 << MIPS_SEGCFG_PA_SHIFT) | \ + (1 << MIPS_SEGCFG_EU_SHIFT)) | \ + (((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) | \ + (0 << MIPS_SEGCFG_PA_SHIFT) | \ + (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) + or t0, t2 + mtc0 t0, $5, 2 + + /* SegCtl1 */ + li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ + (0 << MIPS_SEGCFG_PA_SHIFT) | \ + (2 << MIPS_SEGCFG_C_SHIFT) | \ + (1 << MIPS_SEGCFG_EU_SHIFT)) | \ + (((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ + (0 << MIPS_SEGCFG_PA_SHIFT) | \ + (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) + ins t0, t1, 16, 3 + mtc0 t0, $5, 3 + + /* SegCtl2 */ + li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ + (6 << MIPS_SEGCFG_PA_SHIFT) | \ + (1 << MIPS_SEGCFG_EU_SHIFT)) | \ + (((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ + (4 << MIPS_SEGCFG_PA_SHIFT) | \ + (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) + or t0, t2 + mtc0 t0, $5, 4 + + jal mips_ihb + mfc0 t0, $16, 5 + li t2, 0x40000000 /* K bit */ + or t0, t0, t2 + mtc0 t0, $16, 5 + sync + jal mips_ihb + .endm + .macro kernel_entry_setup -#ifdef CONFIG_MIPS_MT_SMTC - mfc0 t0, CP0_CONFIG - bgez t0, 9f + +#ifdef CONFIG_EVA + sync + ehb + + mfc0 t1, CP0_CONFIG + bgez t1, 9f mfc0 t0, CP0_CONFIG, 1 bgez t0, 9f mfc0 t0, CP0_CONFIG, 2 bgez t0, 9f mfc0 t0, CP0_CONFIG, 3 - and t0, 1<<2 - bnez t0, 0f + sll t0, t0, 6 /* SC bit */ + bgez t0, 9f + + eva_entry + b 0f 9: /* Assume we came from YAMON... */ PTR_LA v0, 0x9fc00534 /* YAMON print */ lw v0, (v0) move a0, zero - PTR_LA a1, nonmt_processor + PTR_LA a1, nonsc_processor jal v0 PTR_LA v0, 0x9fc00520 /* YAMON exit */ @@ -34,19 +111,25 @@ jal v0 1: b 1b - + nop __INITDATA -nonmt_processor: - .asciz "SMTC kernel requires the MT ASE to run\n" +nonsc_processor: + .asciz "EVA kernel requires a MIPS core with Segment Control implemented\n" __FINIT +#endif /* CONFIG_EVA */ 0: -#endif .endm /* * Do SMP slave processor setup necessary before we can safely execute C code. */ .macro smp_slave_setup +#ifdef CONFIG_EVA + sync + ehb + mfc0 t1, CP0_CONFIG + eva_entry +#endif .endm #endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */ diff --git a/arch/mips/include/asm/mach-malta/mach-gt64120.h b/arch/mips/include/asm/mach-malta/mach-gt64120.h index 0f863148f3b..62a4b2889fa 100644 --- a/arch/mips/include/asm/mach-malta/mach-gt64120.h +++ b/arch/mips/include/asm/mach-malta/mach-gt64120.h @@ -1,6 +1,6 @@ /* * This is a direct copy of the ev96100.h file, with a global - * search and replace. The numbers are the same. + * search and replace. The numbers are the same. * * The reason I'm duplicating this is so that the 64120/96100 * defines won't be confusing in the source code. diff --git a/arch/mips/include/asm/mach-malta/malta-pm.h b/arch/mips/include/asm/mach-malta/malta-pm.h new file mode 100644 index 00000000000..c2c2e201013 --- /dev/null +++ b/arch/mips/include/asm/mach-malta/malta-pm.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2014 Imagination Technologies + * Author: Paul Burton <paul.burton@imgtec.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_MIPS_MACH_MALTA_PM_H__ +#define __ASM_MIPS_MACH_MALTA_PM_H__ + +#include <asm/mips-boards/piix4.h> + +#ifdef CONFIG_MIPS_MALTA_PM + +/** + * mips_pm_suspend - enter a suspend state + * @state: the state to enter, one of PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_* + * + * Enters a suspend state via the Malta's PIIX4. If the state to be entered + * is one which loses context (eg. SOFF) then this function will never + * return. + */ +extern int mips_pm_suspend(unsigned state); + +#else /* !CONFIG_MIPS_MALTA_PM */ + +static inline int mips_pm_suspend(unsigned state) +{ + return -EINVAL; +} + +#endif /* !CONFIG_MIPS_MALTA_PM */ + +#endif /* __ASM_MIPS_MACH_MALTA_PM_H__ */ diff --git a/arch/mips/include/asm/mach-malta/spaces.h b/arch/mips/include/asm/mach-malta/spaces.h new file mode 100644 index 00000000000..d7e54971ec6 --- /dev/null +++ b/arch/mips/include/asm/mach-malta/spaces.h @@ -0,0 +1,46 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2014 Imagination Technologies Ltd. + */ + +#ifndef _ASM_MALTA_SPACES_H +#define _ASM_MALTA_SPACES_H + +#ifdef CONFIG_EVA + +/* + * Traditional Malta Board Memory Map for EVA + * + * 0x00000000 - 0x0fffffff: 1st RAM region, 256MB + * 0x10000000 - 0x1bffffff: GIC and CPC Control Registers + * 0x1c000000 - 0x1fffffff: I/O And Flash + * 0x20000000 - 0x7fffffff: 2nd RAM region, 1.5GB + * 0x80000000 - 0xffffffff: Physical memory aliases to 0x0 (2GB) + * + * The kernel is still located in 0x80000000(kseg0). However, + * the physical mask has been shifted to 0x80000000 which exploits the alias + * on the Malta board. As a result of which, we override the __pa_symbol + * to peform direct mapping from virtual to physical addresses. In other + * words, the 0x80000000 virtual address maps to 0x80000000 physical address + * which in turn aliases to 0x0. We do this in order to be able to use a flat + * 2GB of memory (0x80000000 - 0xffffffff) so we can avoid the I/O hole in + * 0x10000000 - 0x1fffffff. + * The last 64KB of physical memory are reserved for correct HIGHMEM + * macros arithmetics. + * + */ + +#define PAGE_OFFSET _AC(0x0, UL) +#define PHYS_OFFSET _AC(0x80000000, UL) +#define HIGHMEM_START _AC(0xffff0000, UL) + +#define __pa_symbol(x) (RELOC_HIDE((unsigned long)(x), 0)) + +#endif /* CONFIG_EVA */ + +#include <asm/mach-generic/spaces.h> + +#endif /* _ASM_MALTA_SPACES_H */ diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h index 868ed8a2ed5..c0dbd530cca 100644 --- a/arch/mips/include/asm/mach-netlogic/irq.h +++ b/arch/mips/include/asm/mach-netlogic/irq.h @@ -9,7 +9,8 @@ #define __ASM_NETLOGIC_IRQ_H #include <asm/mach-netlogic/multi-node.h> -#define NR_IRQS (64 * NLM_NR_NODES) +#define NLM_IRQS_PER_NODE 1024 +#define NR_IRQS (NLM_IRQS_PER_NODE * NLM_NR_NODES) #define MIPS_CPU_IRQ_BASE 0 diff --git a/arch/mips/include/asm/mach-netlogic/multi-node.h b/arch/mips/include/asm/mach-netlogic/multi-node.h index d62fc773f4d..9ed8dacdc37 100644 --- a/arch/mips/include/asm/mach-netlogic/multi-node.h +++ b/arch/mips/include/asm/mach-netlogic/multi-node.h @@ -47,8 +47,37 @@ #endif #endif -#define NLM_CORES_PER_NODE 8 #define NLM_THREADS_PER_CORE 4 -#define NLM_CPUS_PER_NODE (NLM_CORES_PER_NODE * NLM_THREADS_PER_CORE) +#ifdef CONFIG_CPU_XLR +#define nlm_cores_per_node() 8 +#else +extern unsigned int xlp_cores_per_node; +#define nlm_cores_per_node() xlp_cores_per_node +#endif + +#define nlm_threads_per_node() (nlm_cores_per_node() * NLM_THREADS_PER_CORE) +#define nlm_cpuid_to_node(c) ((c) / nlm_threads_per_node()) + +struct nlm_soc_info { + unsigned long coremask; /* cores enabled on the soc */ + unsigned long ebase; /* not used now */ + uint64_t irqmask; /* EIMR for the node */ + uint64_t sysbase; /* only for XLP - sys block base */ + uint64_t picbase; /* PIC block base */ + spinlock_t piclock; /* lock for PIC access */ + cpumask_t cpumask; /* logical cpu mask for node */ + unsigned int socbus; +}; + +extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; +#define nlm_get_node(i) (&nlm_nodes[i]) +#define nlm_node_present(n) ((n) >= 0 && (n) < NLM_NR_NODES && \ + nlm_get_node(n)->coremask != 0) +#ifdef CONFIG_CPU_XLR +#define nlm_current_node() (&nlm_nodes[0]) +#else +#define nlm_current_node() (&nlm_nodes[nlm_nodeid()]) +#endif +void nlm_node_init(int node); #endif diff --git a/arch/mips/include/asm/mach-netlogic/topology.h b/arch/mips/include/asm/mach-netlogic/topology.h new file mode 100644 index 00000000000..ceeb1f5e712 --- /dev/null +++ b/arch/mips/include/asm/mach-netlogic/topology.h @@ -0,0 +1,22 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2013 Broadcom Corporation + */ +#ifndef _ASM_MACH_NETLOGIC_TOPOLOGY_H +#define _ASM_MACH_NETLOGIC_TOPOLOGY_H + +#include <asm/mach-netlogic/multi-node.h> + +#ifdef CONFIG_SMP +#define topology_physical_package_id(cpu) cpu_to_node(cpu) +#define topology_core_id(cpu) (cpu_logical_map(cpu) / NLM_THREADS_PER_CORE) +#define topology_thread_cpumask(cpu) (&cpu_sibling_map[cpu]) +#define topology_core_cpumask(cpu) cpumask_of_node(cpu_to_node(cpu)) +#endif + +#include <asm-generic/topology.h> + +#endif /* _ASM_MACH_NETLOGIC_TOPOLOGY_H */ diff --git a/arch/mips/include/asm/mach-paravirt/cpu-feature-overrides.h b/arch/mips/include/asm/mach-paravirt/cpu-feature-overrides.h new file mode 100644 index 00000000000..725e1ed83f6 --- /dev/null +++ b/arch/mips/include/asm/mach-paravirt/cpu-feature-overrides.h @@ -0,0 +1,36 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2013 Cavium, Inc. + */ +#ifndef __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_tx39_cache 0 +#define cpu_has_counter 1 +#define cpu_has_llsc 1 +/* + * We Disable LL/SC on non SMP systems as it is faster to disable + * interrupts for atomic access than a LL/SC. + */ +#ifdef CONFIG_SMP +# define kernel_uses_llsc 1 +#else +# define kernel_uses_llsc 0 +#endif + +#ifdef CONFIG_CPU_CAVIUM_OCTEON +#define cpu_dcache_line_size() 128 +#define cpu_icache_line_size() 128 +#define cpu_has_octeon_cache 1 +#define cpu_has_4k_cache 0 +#else +#define cpu_has_octeon_cache 0 +#define cpu_has_4k_cache 1 +#endif + +#endif /* __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-paravirt/irq.h b/arch/mips/include/asm/mach-paravirt/irq.h new file mode 100644 index 00000000000..9b4d35eca97 --- /dev/null +++ b/arch/mips/include/asm/mach-paravirt/irq.h @@ -0,0 +1,19 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2013 Cavium, Inc. + */ +#ifndef __ASM_MACH_PARAVIRT_IRQ_H__ +#define __ASM_MACH_PARAVIRT_IRQ_H__ + +#define NR_IRQS 64 +#define MIPS_CPU_IRQ_BASE 1 + +#define MIPS_IRQ_PCIA (MIPS_CPU_IRQ_BASE + 8) + +#define MIPS_IRQ_MBOX0 (MIPS_CPU_IRQ_BASE + 32) +#define MIPS_IRQ_MBOX1 (MIPS_CPU_IRQ_BASE + 33) + +#endif /* __ASM_MACH_PARAVIRT_IRQ_H__ */ diff --git a/arch/mips/include/asm/mach-paravirt/kernel-entry-init.h b/arch/mips/include/asm/mach-paravirt/kernel-entry-init.h new file mode 100644 index 00000000000..2f82bfa3a77 --- /dev/null +++ b/arch/mips/include/asm/mach-paravirt/kernel-entry-init.h @@ -0,0 +1,50 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2013 Cavium, Inc + */ +#ifndef __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H +#define __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H + +#define CP0_EBASE $15, 1 + + .macro kernel_entry_setup + mfc0 t0, CP0_EBASE + andi t0, t0, 0x3ff # CPUNum + beqz t0, 1f + # CPUs other than zero goto smp_bootstrap + j smp_bootstrap + +1: + .endm + +/* + * Do SMP slave processor setup necessary before we can safely execute + * C code. + */ + .macro smp_slave_setup + mfc0 t0, CP0_EBASE + andi t0, t0, 0x3ff # CPUNum + slti t1, t0, NR_CPUS + bnez t1, 1f +2: + di + wait + b 2b # Unknown CPU, loop forever. +1: + PTR_LA t1, paravirt_smp_sp + PTR_SLL t0, PTR_SCALESHIFT + PTR_ADDU t1, t1, t0 +3: + PTR_L sp, 0(t1) + beqz sp, 3b # Spin until told to proceed. + + PTR_LA t1, paravirt_smp_gp + PTR_ADDU t1, t1, t0 + sync + PTR_L gp, 0(t1) + .endm + +#endif /* __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H */ diff --git a/arch/mips/include/asm/mach-wrppmc/war.h b/arch/mips/include/asm/mach-paravirt/war.h index e86084c0bd6..36d3afb9845 100644 --- a/arch/mips/include/asm/mach-wrppmc/war.h +++ b/arch/mips/include/asm/mach-paravirt/war.h @@ -4,9 +4,10 @@ * for more details. * * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + * Copyright (C) 2013 Cavium Networks <support@caviumnetworks.com> */ -#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H -#define __ASM_MIPS_MACH_WRPPMC_WAR_H +#ifndef __ASM_MIPS_MACH_PARAVIRT_WAR_H +#define __ASM_MIPS_MACH_PARAVIRT_WAR_H #define R4600_V1_INDEX_ICACHEOP_WAR 0 #define R4600_V1_HIT_CACHEOP_WAR 0 @@ -17,8 +18,8 @@ #define MIPS4K_ICACHE_REFILL_WAR 0 #define MIPS_CACHE_SYNC_WAR 0 #define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 #define R10000_LLSC_WAR 0 #define MIPS34K_MISSED_ITLB_WAR 0 -#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */ +#endif /* __ASM_MIPS_MACH_PARAVIRT_WAR_H */ diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-pmcs-msp71xx/cpu-feature-overrides.h index 016fa9446ba..016fa9446ba 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-pmcs-msp71xx/cpu-feature-overrides.h diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_cic_int.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_cic_int.h index c84bcf9570b..ac863e2deb6 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_cic_int.h +++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_cic_int.h @@ -43,14 +43,14 @@ * IRQs directly forwarded to the CPU */ #define MSP_MIPS_INTBASE 0 -#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */ -#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */ -#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */ -#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */ -#define MSP_INT_USB 4 /* IRQ for USB, C_IRQ2 */ -#define MSP_INT_SAR 5 /* IRQ for ADSL2+ SAR, C_IRQ3 */ -#define MSP_INT_CIC 6 /* IRQ for CIC block, C_IRQ4 */ -#define MSP_INT_SEC 7 /* IRQ for Sec engine, C_IRQ5 */ +#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */ +#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */ +#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */ +#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */ +#define MSP_INT_USB 4 /* IRQ for USB, C_IRQ2 */ +#define MSP_INT_SAR 5 /* IRQ for ADSL2+ SAR, C_IRQ3 */ +#define MSP_INT_CIC 6 /* IRQ for CIC block, C_IRQ4 */ +#define MSP_INT_SEC 7 /* IRQ for Sec engine, C_IRQ5 */ /* * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4) @@ -59,93 +59,93 @@ */ #define MSP_CIC_INTBASE (MSP_MIPS_INTBASE + 8) #define MSP_INT_EXT0 (MSP_CIC_INTBASE + 0) - /* External interrupt 0 */ + /* External interrupt 0 */ #define MSP_INT_EXT1 (MSP_CIC_INTBASE + 1) - /* External interrupt 1 */ + /* External interrupt 1 */ #define MSP_INT_EXT2 (MSP_CIC_INTBASE + 2) - /* External interrupt 2 */ + /* External interrupt 2 */ #define MSP_INT_EXT3 (MSP_CIC_INTBASE + 3) - /* External interrupt 3 */ + /* External interrupt 3 */ #define MSP_INT_CPUIF (MSP_CIC_INTBASE + 4) - /* CPU interface interrupt */ + /* CPU interface interrupt */ #define MSP_INT_EXT4 (MSP_CIC_INTBASE + 5) - /* External interrupt 4 */ + /* External interrupt 4 */ #define MSP_INT_CIC_USB (MSP_CIC_INTBASE + 6) - /* Cascaded IRQ for USB */ + /* Cascaded IRQ for USB */ #define MSP_INT_MBOX (MSP_CIC_INTBASE + 7) - /* Sec engine mailbox IRQ */ + /* Sec engine mailbox IRQ */ #define MSP_INT_EXT5 (MSP_CIC_INTBASE + 8) - /* External interrupt 5 */ + /* External interrupt 5 */ #define MSP_INT_TDM (MSP_CIC_INTBASE + 9) - /* TDM interrupt */ + /* TDM interrupt */ #define MSP_INT_CIC_MAC0 (MSP_CIC_INTBASE + 10) - /* Cascaded IRQ for MAC 0 */ + /* Cascaded IRQ for MAC 0 */ #define MSP_INT_CIC_MAC1 (MSP_CIC_INTBASE + 11) - /* Cascaded IRQ for MAC 1 */ + /* Cascaded IRQ for MAC 1 */ #define MSP_INT_CIC_SEC (MSP_CIC_INTBASE + 12) - /* Cascaded IRQ for sec engine */ -#define MSP_INT_PER (MSP_CIC_INTBASE + 13) - /* Peripheral interrupt */ -#define MSP_INT_TIMER0 (MSP_CIC_INTBASE + 14) - /* SLP timer 0 */ -#define MSP_INT_TIMER1 (MSP_CIC_INTBASE + 15) - /* SLP timer 1 */ -#define MSP_INT_TIMER2 (MSP_CIC_INTBASE + 16) - /* SLP timer 2 */ -#define MSP_INT_VPE0_TIMER (MSP_CIC_INTBASE + 17) - /* VPE0 MIPS timer */ + /* Cascaded IRQ for sec engine */ +#define MSP_INT_PER (MSP_CIC_INTBASE + 13) + /* Peripheral interrupt */ +#define MSP_INT_TIMER0 (MSP_CIC_INTBASE + 14) + /* SLP timer 0 */ +#define MSP_INT_TIMER1 (MSP_CIC_INTBASE + 15) + /* SLP timer 1 */ +#define MSP_INT_TIMER2 (MSP_CIC_INTBASE + 16) + /* SLP timer 2 */ +#define MSP_INT_VPE0_TIMER (MSP_CIC_INTBASE + 17) + /* VPE0 MIPS timer */ #define MSP_INT_BLKCP (MSP_CIC_INTBASE + 18) - /* Block Copy */ + /* Block Copy */ #define MSP_INT_UART0 (MSP_CIC_INTBASE + 19) - /* UART 0 */ + /* UART 0 */ #define MSP_INT_PCI (MSP_CIC_INTBASE + 20) - /* PCI subsystem */ + /* PCI subsystem */ #define MSP_INT_EXT6 (MSP_CIC_INTBASE + 21) - /* External interrupt 5 */ + /* External interrupt 5 */ #define MSP_INT_PCI_MSI (MSP_CIC_INTBASE + 22) - /* PCI Message Signal */ + /* PCI Message Signal */ #define MSP_INT_CIC_SAR (MSP_CIC_INTBASE + 23) - /* Cascaded ADSL2+ SAR IRQ */ + /* Cascaded ADSL2+ SAR IRQ */ #define MSP_INT_DSL (MSP_CIC_INTBASE + 24) - /* ADSL2+ IRQ */ + /* ADSL2+ IRQ */ #define MSP_INT_CIC_ERR (MSP_CIC_INTBASE + 25) - /* SLP error condition */ + /* SLP error condition */ #define MSP_INT_VPE1_TIMER (MSP_CIC_INTBASE + 26) - /* VPE1 MIPS timer */ + /* VPE1 MIPS timer */ #define MSP_INT_VPE0_PC (MSP_CIC_INTBASE + 27) - /* VPE0 Performance counter */ + /* VPE0 Performance counter */ #define MSP_INT_VPE1_PC (MSP_CIC_INTBASE + 28) - /* VPE1 Performance counter */ + /* VPE1 Performance counter */ #define MSP_INT_EXT7 (MSP_CIC_INTBASE + 29) - /* External interrupt 5 */ + /* External interrupt 5 */ #define MSP_INT_VPE0_SW (MSP_CIC_INTBASE + 30) - /* VPE0 Software interrupt */ + /* VPE0 Software interrupt */ #define MSP_INT_VPE1_SW (MSP_CIC_INTBASE + 31) - /* VPE0 Software interrupt */ + /* VPE0 Software interrupt */ /* * IRQs cascaded on CIC PER interrupt (MSP_INT_PER) */ #define MSP_PER_INTBASE (MSP_CIC_INTBASE + 32) -/* Reserved 0-1 */ +/* Reserved 0-1 */ #define MSP_INT_UART1 (MSP_PER_INTBASE + 2) - /* UART 1 */ -/* Reserved 3-5 */ + /* UART 1 */ +/* Reserved 3-5 */ #define MSP_INT_2WIRE (MSP_PER_INTBASE + 6) - /* 2-wire */ + /* 2-wire */ #define MSP_INT_TM0 (MSP_PER_INTBASE + 7) /* Peripheral timer block out 0 */ #define MSP_INT_TM1 (MSP_PER_INTBASE + 8) /* Peripheral timer block out 1 */ -/* Reserved 9 */ +/* Reserved 9 */ #define MSP_INT_SPRX (MSP_PER_INTBASE + 10) - /* SPI RX complete */ + /* SPI RX complete */ #define MSP_INT_SPTX (MSP_PER_INTBASE + 11) - /* SPI TX complete */ + /* SPI TX complete */ #define MSP_INT_GPIO (MSP_PER_INTBASE + 12) - /* GPIO */ + /* GPIO */ #define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13) - /* Peripheral error */ -/* Reserved 14-31 */ + /* Peripheral error */ +/* Reserved 14-31 */ #endif /* !_MSP_CIC_INT_H */ diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_gpio_macros.h index 156f320c69e..daacebb047c 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h +++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_gpio_macros.h @@ -54,7 +54,7 @@ enum msp_gpio_mode { MSP_GPIO_UART_OUTPUT = 0x9, /* Only GPIO 2 or 3 */ MSP_GPIO_PERIF_TIMERA = 0x9, /* Only GPIO 0 or 1 */ MSP_GPIO_PERIF_TIMERB = 0xa, /* Only GPIO 0 or 1 */ - MSP_GPIO_UNKNOWN = 0xb, /* No such GPIO or mode */ + MSP_GPIO_UNKNOWN = 0xb, /* No such GPIO or mode */ }; /* -- Static Tables -- */ @@ -148,7 +148,7 @@ static unsigned int MSP_GPIO_MODE_ALLOWED[] = { BASIC_MODE_REG_VALUE(mode, OFFSET_GPIO_NUMBER(gpio)) #define BASIC_MODE_SHIFT(gpio) \ BASIC_MODE_REG_SHIFT(OFFSET_GPIO_NUMBER(gpio)) -#define BASIC_MODE_FROM_REG(data, gpio) \ +#define BASIC_MODE_FROM_REG(data, gpio) \ BASIC_MODE_REG_FROM_REG(data, OFFSET_GPIO_NUMBER(gpio)) /* diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_int.h index 1d9f0547482..29f8bf79d7a 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h +++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_int.h @@ -1,7 +1,7 @@ /* * Defines for the MSP interrupt handlers. * - * Copyright (C) 2005, PMC-Sierra, Inc. All rights reserved. + * Copyright (C) 2005, PMC-Sierra, Inc. All rights reserved. * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com * * ######################################################################## @@ -28,7 +28,7 @@ /* * The PMC-Sierra MSP product line has at least two different interrupt * controllers, the SLP register based scheme and the CIC interrupt - * controller block mechanism. This file distinguishes between them + * controller block mechanism. This file distinguishes between them * so that devices see a uniform interface. */ diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_pci.h index 41560690361..24948cc4246 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h +++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_pci.h @@ -26,7 +26,7 @@ #ifndef _MSP_PCI_H_ #define _MSP_PCI_H_ -#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220)) +#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220)) /* * It is convenient to program the OATRAN register so that @@ -96,24 +96,24 @@ enum config_status_command, /* 1 */ config_class_revision, /* 2 */ config_BIST_header_latency_cache, /* 3 */ - config_BAR0, /* 4 */ - config_BAR1, /* 5 */ - config_BAR2, /* 6 */ - config_not_used7, /* 7 */ - config_not_used8, /* 8 */ - config_not_used9, /* 9 */ - config_CIS, /* 10 */ - config_subsystem, /* 11 */ - config_not_used12, /* 12 */ + config_BAR0, /* 4 */ + config_BAR1, /* 5 */ + config_BAR2, /* 6 */ + config_not_used7, /* 7 */ + config_not_used8, /* 8 */ + config_not_used9, /* 9 */ + config_CIS, /* 10 */ + config_subsystem, /* 11 */ + config_not_used12, /* 12 */ config_capabilities, /* 13 */ - config_not_used14, /* 14 */ + config_not_used14, /* 14 */ config_lat_grant_irq, /* 15 */ config_message_control,/* 16 */ config_message_addr, /* 17 */ config_message_data, /* 18 */ - config_VPD_addr, /* 19 */ - config_VPD_data, /* 20 */ - config_maxregs /* 21 - number of registers */ + config_VPD_addr, /* 19 */ + config_VPD_data, /* 20 */ + config_maxregs /* 21 - number of registers */ }; struct msp_pci_regs @@ -132,15 +132,15 @@ struct msp_pci_regs pcireg hop_unused_2C; /* +0x2C */ pcireg hop_unused_30; /* +0x30 */ pcireg hop_unused_34; /* +0x34 */ - pcireg if_control; /* +0x38 */ - pcireg oatran; /* +0x3C */ - pcireg reset_ctl; /* +0x40 */ - pcireg config_addr; /* +0x44 */ + pcireg if_control; /* +0x38 */ + pcireg oatran; /* +0x3C */ + pcireg reset_ctl; /* +0x40 */ + pcireg config_addr; /* +0x44 */ pcireg hop_unused_48; /* +0x48 */ pcireg msg_signaled_int_status; /* +0x4C */ pcireg msg_signaled_int_mask; /* +0x50 */ - pcireg if_status; /* +0x54 */ - pcireg if_mask; /* +0x58 */ + pcireg if_status; /* +0x54 */ + pcireg if_mask; /* +0x58 */ pcireg hop_unused_5C; /* +0x5C */ pcireg hop_unused_60; /* +0x60 */ pcireg hop_unused_64; /* +0x64 */ @@ -190,9 +190,9 @@ struct msp_pci_regs #define BPCI_IFSTATUS_PEI (1<<30) /* Parity error as initiator */ #define BPCI_IFSTATUS_PET (1<<31) /* Parity error as target */ -#define BPCI_RESETCTL_PR (1<<0) /* True if reset asserted */ -#define BPCI_RESETCTL_RT (1<<4) /* Release time */ -#define BPCI_RESETCTL_CT (1<<8) /* Config time */ +#define BPCI_RESETCTL_PR (1<<0) /* True if reset asserted */ +#define BPCI_RESETCTL_RT (1<<4) /* Release time */ +#define BPCI_RESETCTL_CT (1<<8) /* Config time */ #define BPCI_RESETCTL_PE (1<<12) /* PCI enabled */ #define BPCI_RESETCTL_HM (1<<13) /* PCI host mode */ #define BPCI_RESETCTL_RI (1<<14) /* PCI reset in */ diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_prom.h index 786d82daf8d..4d3052ab89a 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h +++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_prom.h @@ -40,7 +40,7 @@ (((revision >= 0xb0) && (revision < 0xd0))) #define FPGA_IS_5000(revision) \ ((revision >= 0x80) && (revision <= 0x90)) -#define FPGA_IS_ZEUS(revision) ((revision < 0x7f)) +#define FPGA_IS_ZEUS(revision) ((revision < 0x7f)) #define FPGA_IS_DUET(revision) \ (((revision >= 0xa0) && (revision < 0xb0))) #define FPGA_IS_MSP4200(revision) ((revision >= 0xd0)) @@ -48,7 +48,7 @@ #define MACHINE_TYPE_POLO "POLO" #define MACHINE_TYPE_DUET "DUET" -#define MACHINE_TYPE_ZEUS "ZEUS" +#define MACHINE_TYPE_ZEUS "ZEUS" #define MACHINE_TYPE_MSP2000REVB "MSP2000REVB" #define MACHINE_TYPE_MSP5000 "MSP5000" #define MACHINE_TYPE_MSP4200 "MSP4200" @@ -58,7 +58,7 @@ #define MACHINE_TYPE_POLO_FPGA "POLO-FPGA" #define MACHINE_TYPE_DUET_FPGA "DUET-FPGA" -#define MACHINE_TYPE_ZEUS_FPGA "ZEUS_FPGA" +#define MACHINE_TYPE_ZEUS_FPGA "ZEUS_FPGA" #define MACHINE_TYPE_MSP2000REVB_FPGA "MSP2000REVB-FPGA" #define MACHINE_TYPE_MSP5000_FPGA "MSP5000-FPGA" #define MACHINE_TYPE_MSP4200_FPGA "MSP4200-FPGA" @@ -95,7 +95,7 @@ #define ENET_MII 'M' #define ENET_RMII 'R' -#define ENETTXD_FALLING 'F' +#define ENETTXD_FALLING 'F' #define ENETTXD_RISING 'R' #define PCI_HOST 'H' diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h index 7d41474e548..fc946c83599 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h +++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h @@ -76,7 +76,7 @@ static inline void set_value_reg32(volatile u32 *const addr, __asm__ __volatile__( " .set push \n" - " .set mips3 \n" + " .set arch=r4000 \n" "1: ll %0, %1 # set_value_reg32 \n" " and %0, %2 \n" " or %0, %3 \n" @@ -98,7 +98,7 @@ static inline void set_reg32(volatile u32 *const addr, __asm__ __volatile__( " .set push \n" - " .set mips3 \n" + " .set arch=r4000 \n" "1: ll %0, %1 # set_reg32 \n" " or %0, %2 \n" " sc %0, %1 \n" @@ -119,7 +119,7 @@ static inline void clear_reg32(volatile u32 *const addr, __asm__ __volatile__( " .set push \n" - " .set mips3 \n" + " .set arch=r4000 \n" "1: ll %0, %1 # clear_reg32 \n" " and %0, %2 \n" " sc %0, %1 \n" @@ -140,7 +140,7 @@ static inline void toggle_reg32(volatile u32 *const addr, __asm__ __volatile__( " .set push \n" - " .set mips3 \n" + " .set arch=r4000 \n" "1: ll %0, %1 # toggle_reg32 \n" " xor %0, %2 \n" " sc %0, %1 \n" @@ -216,7 +216,7 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr) #define custom_read_reg32(address, tmp) \ __asm__ __volatile__( \ " .set push \n" \ - " .set mips3 \n" \ + " .set arch=r4000 \n" \ "1: ll %0, %1 #custom_read_reg32 \n" \ " .set pop \n" \ : "=r" (tmp), "=m" (*address) \ @@ -225,7 +225,7 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr) #define custom_write_reg32(address, tmp) \ __asm__ __volatile__( \ " .set push \n" \ - " .set mips3 \n" \ + " .set arch=r4000 \n" \ " sc %0, %1 #custom_write_reg32 \n" \ " "__beqz"%0, 1b \n" \ " nop \n" \ @@ -233,4 +233,4 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr) : "=&r" (tmp), "=m" (*address) \ : "0" (tmp), "m" (*address)) -#endif /* __ASM_REGOPS_H__ */ +#endif /* __ASM_REGOPS_H__ */ diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h index 692c1b658b9..da3a8dea228 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h +++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h @@ -37,13 +37,13 @@ /* ######################################################################## - # Address space and device base definitions # + # Address space and device base definitions # ######################################################################## */ /* *************************************************************************** - * System Logic and Peripherals (ELB, UART0, etc) device address space * + * System Logic and Peripherals (ELB, UART0, etc) device address space * *************************************************************************** */ #define MSP_SLP_BASE 0x1c000000 @@ -53,69 +53,69 @@ #define MSP_RST_SIZE 0x0C /* System reset register space */ #define MSP_WTIMER_BASE (MSP_SLP_BASE + 0x04C) - /* watchdog timer base */ + /* watchdog timer base */ #define MSP_ITIMER_BASE (MSP_SLP_BASE + 0x054) - /* internal timer base */ + /* internal timer base */ #define MSP_UART0_BASE (MSP_SLP_BASE + 0x100) - /* UART0 controller base */ + /* UART0 controller base */ #define MSP_BCPY_CTRL_BASE (MSP_SLP_BASE + 0x120) - /* Block Copy controller base */ + /* Block Copy controller base */ #define MSP_BCPY_DESC_BASE (MSP_SLP_BASE + 0x160) - /* Block Copy descriptor base */ + /* Block Copy descriptor base */ /* *************************************************************************** - * PCI address space * + * PCI address space * *************************************************************************** */ #define MSP_PCI_BASE 0x19000000 /* *************************************************************************** - * MSbus device address space * + * MSbus device address space * *************************************************************************** */ #define MSP_MSB_BASE 0x18000000 - /* MSbus address start */ + /* MSbus address start */ #define MSP_PER_BASE (MSP_MSB_BASE + 0x400000) - /* Peripheral device registers */ + /* Peripheral device registers */ #define MSP_MAC0_BASE (MSP_MSB_BASE + 0x600000) - /* MAC A device registers */ + /* MAC A device registers */ #define MSP_MAC1_BASE (MSP_MSB_BASE + 0x700000) - /* MAC B device registers */ + /* MAC B device registers */ #define MSP_MAC_SIZE 0xE0 /* MAC register space */ #define MSP_SEC_BASE (MSP_MSB_BASE + 0x800000) - /* Security Engine registers */ + /* Security Engine registers */ #define MSP_MAC2_BASE (MSP_MSB_BASE + 0x900000) - /* MAC C device registers */ + /* MAC C device registers */ #define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000) - /* ADSL2 device registers */ + /* ADSL2 device registers */ #define MSP_USB0_BASE (MSP_MSB_BASE + 0xB00000) - /* USB0 device registers */ + /* USB0 device registers */ #define MSP_USB1_BASE (MSP_MSB_BASE + 0x300000) /* USB1 device registers */ #define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000) - /* CPU interface registers */ + /* CPU interface registers */ /* Devices within the MSbus peripheral block */ #define MSP_UART1_BASE (MSP_PER_BASE + 0x030) - /* UART1 controller base */ + /* UART1 controller base */ #define MSP_SPI_BASE (MSP_PER_BASE + 0x058) - /* SPI/MPI control registers */ + /* SPI/MPI control registers */ #define MSP_TWI_BASE (MSP_PER_BASE + 0x090) - /* Two-wire control registers */ + /* Two-wire control registers */ #define MSP_PTIMER_BASE (MSP_PER_BASE + 0x0F0) - /* Programmable timer control */ + /* Programmable timer control */ /* *************************************************************************** - * Physical Memory configuration address space * + * Physical Memory configuration address space * *************************************************************************** */ #define MSP_MEM_CFG_BASE 0x17f00000 -#define MSP_MEM_INDIRECT_CTL_10 0x10 +#define MSP_MEM_INDIRECT_CTL_10 0x10 /* * Notes: @@ -130,10 +130,10 @@ * 3) These constants are for physical addresses which means that they * work correctly with "ioremap" and friends. This means that device * drivers will need to remap these addresses using ioremap and perhaps - * the readw/writew macros. Or they could use the regptr() macro + * the readw/writew macros. Or they could use the regptr() macro * defined below, but the readw/writew calls are the correct thing. * 4) The UARTs have an additional status register offset from the base - * address. This register isn't used in the standard 8250 driver but + * address. This register isn't used in the standard 8250 driver but * may be used in other software. Consult the hardware datasheet for * offset details. * 5) For some unknown reason the security engine (MSP_SEC_BASE) registers @@ -163,44 +163,44 @@ /* *************************************************************************** - * System Logic and Peripherals (RESET, ELB, etc) registers * + * System Logic and Peripherals (RESET, ELB, etc) registers * *************************************************************************** */ /* System Control register definitions */ -#define DEV_ID_REG regptr(MSP_SLP_BASE + 0x00) - /* Device-ID RO */ -#define FWR_ID_REG regptr(MSP_SLP_BASE + 0x04) - /* Firmware-ID Register RW */ -#define SYS_ID_REG0 regptr(MSP_SLP_BASE + 0x08) - /* System-ID Register-0 RW */ -#define SYS_ID_REG1 regptr(MSP_SLP_BASE + 0x0C) - /* System-ID Register-1 RW */ +#define DEV_ID_REG regptr(MSP_SLP_BASE + 0x00) + /* Device-ID RO */ +#define FWR_ID_REG regptr(MSP_SLP_BASE + 0x04) + /* Firmware-ID Register RW */ +#define SYS_ID_REG0 regptr(MSP_SLP_BASE + 0x08) + /* System-ID Register-0 RW */ +#define SYS_ID_REG1 regptr(MSP_SLP_BASE + 0x0C) + /* System-ID Register-1 RW */ /* System Reset register definitions */ -#define RST_STS_REG regptr(MSP_SLP_BASE + 0x10) - /* System Reset Status RO */ -#define RST_SET_REG regptr(MSP_SLP_BASE + 0x14) - /* System Set Reset WO */ -#define RST_CLR_REG regptr(MSP_SLP_BASE + 0x18) - /* System Clear Reset WO */ +#define RST_STS_REG regptr(MSP_SLP_BASE + 0x10) + /* System Reset Status RO */ +#define RST_SET_REG regptr(MSP_SLP_BASE + 0x14) + /* System Set Reset WO */ +#define RST_CLR_REG regptr(MSP_SLP_BASE + 0x18) + /* System Clear Reset WO */ /* System Clock Registers */ #define PCI_SLP_REG regptr(MSP_SLP_BASE + 0x1C) - /* PCI clock generator RW */ + /* PCI clock generator RW */ #define URT_SLP_REG regptr(MSP_SLP_BASE + 0x20) - /* UART clock generator RW */ -/* reserved (MSP_SLP_BASE + 0x24) */ -/* reserved (MSP_SLP_BASE + 0x28) */ + /* UART clock generator RW */ +/* reserved (MSP_SLP_BASE + 0x24) */ +/* reserved (MSP_SLP_BASE + 0x28) */ #define PLL1_SLP_REG regptr(MSP_SLP_BASE + 0x2C) - /* PLL1 clock generator RW */ + /* PLL1 clock generator RW */ #define PLL0_SLP_REG regptr(MSP_SLP_BASE + 0x30) - /* PLL0 clock generator RW */ + /* PLL0 clock generator RW */ #define MIPS_SLP_REG regptr(MSP_SLP_BASE + 0x34) - /* MIPS clock generator RW */ -#define VE_SLP_REG regptr(MSP_SLP_BASE + 0x38) + /* MIPS clock generator RW */ +#define VE_SLP_REG regptr(MSP_SLP_BASE + 0x38) /* Voice Eng clock generator RW */ -/* reserved (MSP_SLP_BASE + 0x3C) */ +/* reserved (MSP_SLP_BASE + 0x3C) */ #define MSB_SLP_REG regptr(MSP_SLP_BASE + 0x40) /* MS-Bus clock generator RW */ #define SMAC_SLP_REG regptr(MSP_SLP_BASE + 0x44) @@ -216,108 +216,108 @@ #define SE_MBOX_REG regptr(MSP_SLP_BASE + 0x78) /* Security Engine mailbox RW */ #define VE_MBOX_REG regptr(MSP_SLP_BASE + 0x7C) - /* Voice Engine mailbox RW */ + /* Voice Engine mailbox RW */ /* ELB Controller Registers */ #define CS0_CNFG_REG regptr(MSP_SLP_BASE + 0x80) - /* ELB CS0 Configuration Reg */ + /* ELB CS0 Configuration Reg */ #define CS0_ADDR_REG regptr(MSP_SLP_BASE + 0x84) - /* ELB CS0 Base Address Reg */ + /* ELB CS0 Base Address Reg */ #define CS0_MASK_REG regptr(MSP_SLP_BASE + 0x88) - /* ELB CS0 Mask Register */ + /* ELB CS0 Mask Register */ #define CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C) - /* ELB CS0 access register */ + /* ELB CS0 access register */ #define CS1_CNFG_REG regptr(MSP_SLP_BASE + 0x90) - /* ELB CS1 Configuration Reg */ + /* ELB CS1 Configuration Reg */ #define CS1_ADDR_REG regptr(MSP_SLP_BASE + 0x94) - /* ELB CS1 Base Address Reg */ + /* ELB CS1 Base Address Reg */ #define CS1_MASK_REG regptr(MSP_SLP_BASE + 0x98) - /* ELB CS1 Mask Register */ + /* ELB CS1 Mask Register */ #define CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C) - /* ELB CS1 access register */ + /* ELB CS1 access register */ #define CS2_CNFG_REG regptr(MSP_SLP_BASE + 0xA0) - /* ELB CS2 Configuration Reg */ + /* ELB CS2 Configuration Reg */ #define CS2_ADDR_REG regptr(MSP_SLP_BASE + 0xA4) - /* ELB CS2 Base Address Reg */ + /* ELB CS2 Base Address Reg */ #define CS2_MASK_REG regptr(MSP_SLP_BASE + 0xA8) - /* ELB CS2 Mask Register */ + /* ELB CS2 Mask Register */ #define CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC) - /* ELB CS2 access register */ + /* ELB CS2 access register */ #define CS3_CNFG_REG regptr(MSP_SLP_BASE + 0xB0) - /* ELB CS3 Configuration Reg */ + /* ELB CS3 Configuration Reg */ #define CS3_ADDR_REG regptr(MSP_SLP_BASE + 0xB4) - /* ELB CS3 Base Address Reg */ + /* ELB CS3 Base Address Reg */ #define CS3_MASK_REG regptr(MSP_SLP_BASE + 0xB8) - /* ELB CS3 Mask Register */ + /* ELB CS3 Mask Register */ #define CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC) - /* ELB CS3 access register */ + /* ELB CS3 access register */ #define CS4_CNFG_REG regptr(MSP_SLP_BASE + 0xC0) - /* ELB CS4 Configuration Reg */ + /* ELB CS4 Configuration Reg */ #define CS4_ADDR_REG regptr(MSP_SLP_BASE + 0xC4) - /* ELB CS4 Base Address Reg */ + /* ELB CS4 Base Address Reg */ #define CS4_MASK_REG regptr(MSP_SLP_BASE + 0xC8) - /* ELB CS4 Mask Register */ + /* ELB CS4 Mask Register */ #define CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC) - /* ELB CS4 access register */ + /* ELB CS4 access register */ #define CS5_CNFG_REG regptr(MSP_SLP_BASE + 0xD0) - /* ELB CS5 Configuration Reg */ + /* ELB CS5 Configuration Reg */ #define CS5_ADDR_REG regptr(MSP_SLP_BASE + 0xD4) - /* ELB CS5 Base Address Reg */ + /* ELB CS5 Base Address Reg */ #define CS5_MASK_REG regptr(MSP_SLP_BASE + 0xD8) - /* ELB CS5 Mask Register */ + /* ELB CS5 Mask Register */ #define CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC) - /* ELB CS5 access register */ + /* ELB CS5 access register */ -/* reserved 0xE0 - 0xE8 */ +/* reserved 0xE0 - 0xE8 */ #define ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC) - /* ELB single PC card detect */ + /* ELB single PC card detect */ -/* reserved 0xF0 - 0xF8 */ -#define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC) - /* SDRAM read/ELB timing Reg */ +/* reserved 0xF0 - 0xF8 */ +#define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC) + /* SDRAM read/ELB timing Reg */ /* Extended UART status registers */ #define UART0_STATUS_REG regptr(MSP_UART0_BASE + 0x0c0) - /* UART Status Register 0 */ + /* UART Status Register 0 */ #define UART1_STATUS_REG regptr(MSP_UART1_BASE + 0x170) - /* UART Status Register 1 */ + /* UART Status Register 1 */ /* Performance monitoring registers */ #define PERF_MON_CTRL_REG regptr(MSP_SLP_BASE + 0x140) - /* Performance monitor control */ + /* Performance monitor control */ #define PERF_MON_CLR_REG regptr(MSP_SLP_BASE + 0x144) - /* Performance monitor clear */ + /* Performance monitor clear */ #define PERF_MON_CNTH_REG regptr(MSP_SLP_BASE + 0x148) - /* Perf monitor counter high */ + /* Perf monitor counter high */ #define PERF_MON_CNTL_REG regptr(MSP_SLP_BASE + 0x14C) - /* Perf monitor counter low */ + /* Perf monitor counter low */ /* System control registers */ #define SYS_CTRL_REG regptr(MSP_SLP_BASE + 0x150) - /* System control register */ + /* System control register */ #define SYS_ERR1_REG regptr(MSP_SLP_BASE + 0x154) - /* System Error status 1 */ + /* System Error status 1 */ #define SYS_ERR2_REG regptr(MSP_SLP_BASE + 0x158) - /* System Error status 2 */ + /* System Error status 2 */ #define SYS_INT_CFG_REG regptr(MSP_SLP_BASE + 0x15C) - /* System Interrupt config */ + /* System Interrupt config */ /* Voice Engine Memory configuration */ #define VE_MEM_REG regptr(MSP_SLP_BASE + 0x17C) - /* Voice engine memory config */ + /* Voice engine memory config */ /* CPU/SLP Error Status registers */ #define CPU_ERR1_REG regptr(MSP_SLP_BASE + 0x180) - /* CPU/SLP Error status 1 */ + /* CPU/SLP Error status 1 */ #define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184) - /* CPU/SLP Error status 1 */ + /* CPU/SLP Error status 1 */ -/* Extended GPIO registers */ +/* Extended GPIO registers */ #define EXTENDED_GPIO1_REG regptr(MSP_SLP_BASE + 0x188) #define EXTENDED_GPIO2_REG regptr(MSP_SLP_BASE + 0x18c) #define EXTENDED_GPIO_REG EXTENDED_GPIO1_REG @@ -325,182 +325,182 @@ /* System Error registers */ #define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190) - /* Int status for SLP errors */ + /* Int status for SLP errors */ #define SLP_ERR_MSK_REG regptr(MSP_SLP_BASE + 0x194) - /* Int mask for SLP errors */ + /* Int mask for SLP errors */ #define SLP_ELB_ERST_REG regptr(MSP_SLP_BASE + 0x198) - /* External ELB reset */ + /* External ELB reset */ #define SLP_BOOT_STS_REG regptr(MSP_SLP_BASE + 0x19C) - /* Boot Status */ + /* Boot Status */ /* Extended ELB addressing */ #define CS0_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A0) - /* CS0 Extended address */ + /* CS0 Extended address */ #define CS1_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A4) - /* CS1 Extended address */ + /* CS1 Extended address */ #define CS2_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A8) - /* CS2 Extended address */ + /* CS2 Extended address */ #define CS3_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1AC) - /* CS3 Extended address */ -/* reserved 0x1B0 */ + /* CS3 Extended address */ +/* reserved 0x1B0 */ #define CS5_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1B4) - /* CS5 Extended address */ + /* CS5 Extended address */ /* PLL Adjustment registers */ #define PLL_LOCK_REG regptr(MSP_SLP_BASE + 0x200) - /* PLL0 lock status */ + /* PLL0 lock status */ #define PLL_ARST_REG regptr(MSP_SLP_BASE + 0x204) - /* PLL Analog reset status */ + /* PLL Analog reset status */ #define PLL0_ADJ_REG regptr(MSP_SLP_BASE + 0x208) - /* PLL0 Adjustment value */ + /* PLL0 Adjustment value */ #define PLL1_ADJ_REG regptr(MSP_SLP_BASE + 0x20C) - /* PLL1 Adjustment value */ + /* PLL1 Adjustment value */ /* *************************************************************************** - * Peripheral Register definitions * + * Peripheral Register definitions * *************************************************************************** */ /* Peripheral status */ #define PER_CTRL_REG regptr(MSP_PER_BASE + 0x50) - /* Peripheral control register */ + /* Peripheral control register */ #define PER_STS_REG regptr(MSP_PER_BASE + 0x54) - /* Peripheral status register */ + /* Peripheral status register */ /* SPI/MPI Registers */ #define SMPI_TX_SZ_REG regptr(MSP_PER_BASE + 0x58) - /* SPI/MPI Tx Size register */ + /* SPI/MPI Tx Size register */ #define SMPI_RX_SZ_REG regptr(MSP_PER_BASE + 0x5C) - /* SPI/MPI Rx Size register */ + /* SPI/MPI Rx Size register */ #define SMPI_CTL_REG regptr(MSP_PER_BASE + 0x60) - /* SPI/MPI Control register */ + /* SPI/MPI Control register */ #define SMPI_MS_REG regptr(MSP_PER_BASE + 0x64) - /* SPI/MPI Chip Select reg */ + /* SPI/MPI Chip Select reg */ #define SMPI_CORE_DATA_REG regptr(MSP_PER_BASE + 0xC0) - /* SPI/MPI Core Data reg */ + /* SPI/MPI Core Data reg */ #define SMPI_CORE_CTRL_REG regptr(MSP_PER_BASE + 0xC4) - /* SPI/MPI Core Control reg */ + /* SPI/MPI Core Control reg */ #define SMPI_CORE_STAT_REG regptr(MSP_PER_BASE + 0xC8) - /* SPI/MPI Core Status reg */ + /* SPI/MPI Core Status reg */ #define SMPI_CORE_SSEL_REG regptr(MSP_PER_BASE + 0xCC) - /* SPI/MPI Core Ssel reg */ + /* SPI/MPI Core Ssel reg */ #define SMPI_FIFO_REG regptr(MSP_PER_BASE + 0xD0) - /* SPI/MPI Data FIFO reg */ + /* SPI/MPI Data FIFO reg */ -/* Peripheral Block Error Registers */ +/* Peripheral Block Error Registers */ #define PER_ERR_STS_REG regptr(MSP_PER_BASE + 0x70) - /* Error Bit Status Register */ + /* Error Bit Status Register */ #define PER_ERR_MSK_REG regptr(MSP_PER_BASE + 0x74) - /* Error Bit Mask Register */ + /* Error Bit Mask Register */ #define PER_HDR1_REG regptr(MSP_PER_BASE + 0x78) - /* Error Header 1 Register */ + /* Error Header 1 Register */ #define PER_HDR2_REG regptr(MSP_PER_BASE + 0x7C) - /* Error Header 2 Register */ + /* Error Header 2 Register */ -/* Peripheral Block Interrupt Registers */ +/* Peripheral Block Interrupt Registers */ #define PER_INT_STS_REG regptr(MSP_PER_BASE + 0x80) - /* Interrupt status register */ + /* Interrupt status register */ #define PER_INT_MSK_REG regptr(MSP_PER_BASE + 0x84) - /* Interrupt Mask Register */ + /* Interrupt Mask Register */ #define GPIO_INT_STS_REG regptr(MSP_PER_BASE + 0x88) - /* GPIO interrupt status reg */ + /* GPIO interrupt status reg */ #define GPIO_INT_MSK_REG regptr(MSP_PER_BASE + 0x8C) - /* GPIO interrupt MASK Reg */ + /* GPIO interrupt MASK Reg */ -/* POLO GPIO registers */ +/* POLO GPIO registers */ #define POLO_GPIO_DAT1_REG regptr(MSP_PER_BASE + 0x0E0) - /* Polo GPIO[8:0] data reg */ + /* Polo GPIO[8:0] data reg */ #define POLO_GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x0E4) - /* Polo GPIO[7:0] config reg */ + /* Polo GPIO[7:0] config reg */ #define POLO_GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x0E8) - /* Polo GPIO[15:8] config reg */ + /* Polo GPIO[15:8] config reg */ #define POLO_GPIO_OD1_REG regptr(MSP_PER_BASE + 0x0EC) /* Polo GPIO[31:0] output drive */ #define POLO_GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x170) - /* Polo GPIO[23:16] config reg */ + /* Polo GPIO[23:16] config reg */ #define POLO_GPIO_DAT2_REG regptr(MSP_PER_BASE + 0x174) - /* Polo GPIO[15:9] data reg */ + /* Polo GPIO[15:9] data reg */ #define POLO_GPIO_DAT3_REG regptr(MSP_PER_BASE + 0x178) - /* Polo GPIO[23:16] data reg */ + /* Polo GPIO[23:16] data reg */ #define POLO_GPIO_DAT4_REG regptr(MSP_PER_BASE + 0x17C) - /* Polo GPIO[31:24] data reg */ + /* Polo GPIO[31:24] data reg */ #define POLO_GPIO_DAT5_REG regptr(MSP_PER_BASE + 0x180) - /* Polo GPIO[39:32] data reg */ + /* Polo GPIO[39:32] data reg */ #define POLO_GPIO_DAT6_REG regptr(MSP_PER_BASE + 0x184) - /* Polo GPIO[47:40] data reg */ + /* Polo GPIO[47:40] data reg */ #define POLO_GPIO_DAT7_REG regptr(MSP_PER_BASE + 0x188) - /* Polo GPIO[54:48] data reg */ + /* Polo GPIO[54:48] data reg */ #define POLO_GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C) - /* Polo GPIO[31:24] config reg */ + /* Polo GPIO[31:24] config reg */ #define POLO_GPIO_CFG5_REG regptr(MSP_PER_BASE + 0x190) - /* Polo GPIO[39:32] config reg */ + /* Polo GPIO[39:32] config reg */ #define POLO_GPIO_CFG6_REG regptr(MSP_PER_BASE + 0x194) - /* Polo GPIO[47:40] config reg */ + /* Polo GPIO[47:40] config reg */ #define POLO_GPIO_CFG7_REG regptr(MSP_PER_BASE + 0x198) - /* Polo GPIO[54:48] config reg */ + /* Polo GPIO[54:48] config reg */ #define POLO_GPIO_OD2_REG regptr(MSP_PER_BASE + 0x19C) /* Polo GPIO[54:32] output drive */ -/* Generic GPIO registers */ +/* Generic GPIO registers */ #define GPIO_DATA1_REG regptr(MSP_PER_BASE + 0x170) - /* GPIO[1:0] data register */ + /* GPIO[1:0] data register */ #define GPIO_DATA2_REG regptr(MSP_PER_BASE + 0x174) - /* GPIO[5:2] data register */ + /* GPIO[5:2] data register */ #define GPIO_DATA3_REG regptr(MSP_PER_BASE + 0x178) - /* GPIO[9:6] data register */ + /* GPIO[9:6] data register */ #define GPIO_DATA4_REG regptr(MSP_PER_BASE + 0x17C) - /* GPIO[15:10] data register */ + /* GPIO[15:10] data register */ #define GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x180) - /* GPIO[1:0] config register */ + /* GPIO[1:0] config register */ #define GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x184) - /* GPIO[5:2] config register */ + /* GPIO[5:2] config register */ #define GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x188) - /* GPIO[9:6] config register */ + /* GPIO[9:6] config register */ #define GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C) - /* GPIO[15:10] config register */ + /* GPIO[15:10] config register */ #define GPIO_OD_REG regptr(MSP_PER_BASE + 0x190) - /* GPIO[15:0] output drive */ + /* GPIO[15:0] output drive */ /* *************************************************************************** - * CPU Interface register definitions * + * CPU Interface register definitions * *************************************************************************** */ #define PCI_FLUSH_REG regptr(MSP_CPUIF_BASE + 0x00) /* PCI-SDRAM queue flush trigger */ #define OCP_ERR1_REG regptr(MSP_CPUIF_BASE + 0x04) - /* OCP Error Attribute 1 */ + /* OCP Error Attribute 1 */ #define OCP_ERR2_REG regptr(MSP_CPUIF_BASE + 0x08) - /* OCP Error Attribute 2 */ + /* OCP Error Attribute 2 */ #define OCP_STS_REG regptr(MSP_CPUIF_BASE + 0x0C) - /* OCP Error Status */ + /* OCP Error Status */ #define CPUIF_PM_REG regptr(MSP_CPUIF_BASE + 0x10) - /* CPU policy configuration */ + /* CPU policy configuration */ #define CPUIF_CFG_REG regptr(MSP_CPUIF_BASE + 0x10) - /* Misc configuration options */ + /* Misc configuration options */ /* Central Interrupt Controller Registers */ #define MSP_CIC_BASE (MSP_CPUIF_BASE + 0x8000) - /* Central Interrupt registers */ + /* Central Interrupt registers */ #define CIC_EXT_CFG_REG regptr(MSP_CIC_BASE + 0x00) - /* External interrupt config */ + /* External interrupt config */ #define CIC_STS_REG regptr(MSP_CIC_BASE + 0x04) - /* CIC Interrupt Status */ + /* CIC Interrupt Status */ #define CIC_VPE0_MSK_REG regptr(MSP_CIC_BASE + 0x08) - /* VPE0 Interrupt Mask */ + /* VPE0 Interrupt Mask */ #define CIC_VPE1_MSK_REG regptr(MSP_CIC_BASE + 0x0C) - /* VPE1 Interrupt Mask */ + /* VPE1 Interrupt Mask */ #define CIC_TC0_MSK_REG regptr(MSP_CIC_BASE + 0x10) - /* Thread Context 0 Int Mask */ + /* Thread Context 0 Int Mask */ #define CIC_TC1_MSK_REG regptr(MSP_CIC_BASE + 0x14) - /* Thread Context 1 Int Mask */ + /* Thread Context 1 Int Mask */ #define CIC_TC2_MSK_REG regptr(MSP_CIC_BASE + 0x18) - /* Thread Context 2 Int Mask */ + /* Thread Context 2 Int Mask */ #define CIC_TC3_MSK_REG regptr(MSP_CIC_BASE + 0x18) - /* Thread Context 3 Int Mask */ + /* Thread Context 3 Int Mask */ #define CIC_TC4_MSK_REG regptr(MSP_CIC_BASE + 0x18) - /* Thread Context 4 Int Mask */ + /* Thread Context 4 Int Mask */ #define CIC_PCIMSI_STS_REG regptr(MSP_CIC_BASE + 0x18) #define CIC_PCIMSI_MSK_REG regptr(MSP_CIC_BASE + 0x18) #define CIC_PCIFLSH_REG regptr(MSP_CIC_BASE + 0x18) @@ -509,7 +509,7 @@ /* *************************************************************************** - * Memory controller registers * + * Memory controller registers * *************************************************************************** */ #define MEM_CFG1_REG regptr(MSP_MEM_CFG_BASE + 0x00) @@ -519,7 +519,7 @@ /* *************************************************************************** - * PCI controller registers * + * PCI controller registers * *************************************************************************** */ #define PCI_BASE_REG regptr(MSP_PCI_BASE + 0x00) @@ -528,25 +528,25 @@ /* ######################################################################## - # Register content & macro definitions # + # Register content & macro definitions # ######################################################################## */ /* *************************************************************************** - * DEV_ID defines * + * DEV_ID defines * *************************************************************************** */ -#define DEV_ID_PCI_DIS (1 << 26) /* Set if PCI disabled */ -#define DEV_ID_PCI_HOST (1 << 20) /* Set if PCI host */ -#define DEV_ID_SINGLE_PC (1 << 19) /* Set if single PC Card */ -#define DEV_ID_FAMILY (0xff << 8) /* family ID code */ -#define POLO_ZEUS_SUB_FAMILY (0x7 << 16) /* sub family for Polo/Zeus */ +#define DEV_ID_PCI_DIS (1 << 26) /* Set if PCI disabled */ +#define DEV_ID_PCI_HOST (1 << 20) /* Set if PCI host */ +#define DEV_ID_SINGLE_PC (1 << 19) /* Set if single PC Card */ +#define DEV_ID_FAMILY (0xff << 8) /* family ID code */ +#define POLO_ZEUS_SUB_FAMILY (0x7 << 16) /* sub family for Polo/Zeus */ -#define MSPFPGA_ID (0x00 << 8) /* you are on your own here */ +#define MSPFPGA_ID (0x00 << 8) /* you are on your own here */ #define MSP5000_ID (0x50 << 8) -#define MSP4F00_ID (0x4f << 8) /* FPGA version of MSP4200 */ -#define MSP4E00_ID (0x4f << 8) /* FPGA version of MSP7120 */ +#define MSP4F00_ID (0x4f << 8) /* FPGA version of MSP4200 */ +#define MSP4E00_ID (0x4f << 8) /* FPGA version of MSP7120 */ #define MSP4200_ID (0x42 << 8) #define MSP4000_ID (0x40 << 8) #define MSP2XXX_ID (0x20 << 8) @@ -563,27 +563,27 @@ /* *************************************************************************** - * RESET defines * + * RESET defines * *************************************************************************** */ -#define MSP_GR_RST (0x01 << 0) /* Global reset bit */ -#define MSP_MR_RST (0x01 << 1) /* MIPS reset bit */ -#define MSP_PD_RST (0x01 << 2) /* PVC DMA reset bit */ -#define MSP_PP_RST (0x01 << 3) /* PVC reset bit */ -/* reserved */ -#define MSP_EA_RST (0x01 << 6) /* Mac A reset bit */ -#define MSP_EB_RST (0x01 << 7) /* Mac B reset bit */ -#define MSP_SE_RST (0x01 << 8) /* Security Eng reset bit */ -#define MSP_PB_RST (0x01 << 9) /* Per block reset bit */ -#define MSP_EC_RST (0x01 << 10) /* Mac C reset bit */ -#define MSP_TW_RST (0x01 << 11) /* TWI reset bit */ -#define MSP_SPI_RST (0x01 << 12) /* SPI/MPI reset bit */ -#define MSP_U1_RST (0x01 << 13) /* UART1 reset bit */ -#define MSP_U0_RST (0x01 << 14) /* UART0 reset bit */ +#define MSP_GR_RST (0x01 << 0) /* Global reset bit */ +#define MSP_MR_RST (0x01 << 1) /* MIPS reset bit */ +#define MSP_PD_RST (0x01 << 2) /* PVC DMA reset bit */ +#define MSP_PP_RST (0x01 << 3) /* PVC reset bit */ +/* reserved */ +#define MSP_EA_RST (0x01 << 6) /* Mac A reset bit */ +#define MSP_EB_RST (0x01 << 7) /* Mac B reset bit */ +#define MSP_SE_RST (0x01 << 8) /* Security Eng reset bit */ +#define MSP_PB_RST (0x01 << 9) /* Per block reset bit */ +#define MSP_EC_RST (0x01 << 10) /* Mac C reset bit */ +#define MSP_TW_RST (0x01 << 11) /* TWI reset bit */ +#define MSP_SPI_RST (0x01 << 12) /* SPI/MPI reset bit */ +#define MSP_U1_RST (0x01 << 13) /* UART1 reset bit */ +#define MSP_U0_RST (0x01 << 14) /* UART0 reset bit */ /* *************************************************************************** - * UART defines * + * UART defines * *************************************************************************** */ #define MSP_BASE_BAUD 25000000 @@ -591,15 +591,15 @@ /* *************************************************************************** - * ELB defines * + * ELB defines * *************************************************************************** */ -#define PCCARD_32 0x02 /* Set if is PCCARD 32 (Cardbus) */ -#define SINGLE_PCCARD 0x01 /* Set to enable single PC card */ +#define PCCARD_32 0x02 /* Set if is PCCARD 32 (Cardbus) */ +#define SINGLE_PCCARD 0x01 /* Set to enable single PC card */ /* *************************************************************************** - * CIC defines * + * CIC defines * *************************************************************************** */ @@ -625,7 +625,7 @@ /* *************************************************************************** - * Memory Controller defines * + * Memory Controller defines * *************************************************************************** */ @@ -644,17 +644,17 @@ /* *************************************************************************** - * SPI/MPI Mode * + * SPI/MPI Mode * *************************************************************************** */ #define SPI_MPI_RX_BUSY 0x00008000 /* SPI/MPI Receive Busy */ -#define SPI_MPI_FIFO_EMPTY 0x00004000 /* SPI/MPI Fifo Empty */ +#define SPI_MPI_FIFO_EMPTY 0x00004000 /* SPI/MPI Fifo Empty */ #define SPI_MPI_TX_BUSY 0x00002000 /* SPI/MPI Transmit Busy */ -#define SPI_MPI_FIFO_FULL 0x00001000 /* SPI/MPU FIFO full */ +#define SPI_MPI_FIFO_FULL 0x00001000 /* SPI/MPU FIFO full */ /* *************************************************************************** - * SPI/MPI Control Register * + * SPI/MPI Control Register * *************************************************************************** */ #define SPI_MPI_RX_START 0x00000004 /* Start receive command */ diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_slp_int.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_slp_int.h index 96d4c8ce8c8..51a66dcc429 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_slp_int.h +++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_slp_int.h @@ -27,9 +27,9 @@ /* * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded - * hierarchical system. The first level are the direct MIPS interrupts + * hierarchical system. The first level are the direct MIPS interrupts * and are assigned the interrupt range 0-7. The second level is the SLM - * interrupt controller and is assigned the range 8-39. The third level + * interrupt controller and is assigned the range 8-39. The third level * comprises the Peripherial block, the PCI block, the PCI MSI block and * the SLP. The PCI interrupts and the SLP errors are handled by the * relevant subsystems so the core interrupt code needs only concern @@ -41,11 +41,11 @@ * IRQs directly connected to CPU */ #define MSP_MIPS_INTBASE 0 -#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */ -#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */ -#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */ -#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */ -#define MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */ +#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */ +#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */ +#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */ +#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */ +#define MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */ #define MSP_INT_VE 5 /* IRQ for Voice Engine, C_IRQ3 */ #define MSP_INT_SLP 6 /* IRQ for SLM block, C_IRQ4 */ #define MSP_INT_TIMER 7 /* IRQ for the MIPS timer, C_IRQ5 */ @@ -57,85 +57,85 @@ */ #define MSP_SLP_INTBASE (MSP_MIPS_INTBASE + 8) #define MSP_INT_EXT0 (MSP_SLP_INTBASE + 0) - /* External interrupt 0 */ + /* External interrupt 0 */ #define MSP_INT_EXT1 (MSP_SLP_INTBASE + 1) - /* External interrupt 1 */ + /* External interrupt 1 */ #define MSP_INT_EXT2 (MSP_SLP_INTBASE + 2) - /* External interrupt 2 */ + /* External interrupt 2 */ #define MSP_INT_EXT3 (MSP_SLP_INTBASE + 3) - /* External interrupt 3 */ -/* Reserved 4-7 */ + /* External interrupt 3 */ +/* Reserved 4-7 */ /* ************************************************************************* * DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER * - * Some MSP produces have this interrupt labelled as Voice and some are * - * SEC mbox ... * + * Some MSP produces have this interrupt labelled as Voice and some are * + * SEC mbox ... * ************************************************************************* */ #define MSP_INT_SLP_VE (MSP_SLP_INTBASE + 8) /* Cascaded IRQ for Voice Engine*/ #define MSP_INT_SLP_TDM (MSP_SLP_INTBASE + 9) - /* TDM interrupt */ + /* TDM interrupt */ #define MSP_INT_SLP_MAC0 (MSP_SLP_INTBASE + 10) - /* Cascaded IRQ for MAC 0 */ + /* Cascaded IRQ for MAC 0 */ #define MSP_INT_SLP_MAC1 (MSP_SLP_INTBASE + 11) - /* Cascaded IRQ for MAC 1 */ + /* Cascaded IRQ for MAC 1 */ #define MSP_INT_SEC (MSP_SLP_INTBASE + 12) - /* IRQ for security engine */ -#define MSP_INT_PER (MSP_SLP_INTBASE + 13) - /* Peripheral interrupt */ -#define MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14) - /* SLP timer 0 */ -#define MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15) - /* SLP timer 1 */ -#define MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16) - /* SLP timer 2 */ -#define MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17) - /* Cascaded MIPS timer */ + /* IRQ for security engine */ +#define MSP_INT_PER (MSP_SLP_INTBASE + 13) + /* Peripheral interrupt */ +#define MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14) + /* SLP timer 0 */ +#define MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15) + /* SLP timer 1 */ +#define MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16) + /* SLP timer 2 */ +#define MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17) + /* Cascaded MIPS timer */ #define MSP_INT_BLKCP (MSP_SLP_INTBASE + 18) - /* Block Copy */ + /* Block Copy */ #define MSP_INT_UART0 (MSP_SLP_INTBASE + 19) - /* UART 0 */ + /* UART 0 */ #define MSP_INT_PCI (MSP_SLP_INTBASE + 20) - /* PCI subsystem */ + /* PCI subsystem */ #define MSP_INT_PCI_DBELL (MSP_SLP_INTBASE + 21) - /* PCI doorbell */ + /* PCI doorbell */ #define MSP_INT_PCI_MSI (MSP_SLP_INTBASE + 22) - /* PCI Message Signal */ + /* PCI Message Signal */ #define MSP_INT_PCI_BC0 (MSP_SLP_INTBASE + 23) - /* PCI Block Copy 0 */ + /* PCI Block Copy 0 */ #define MSP_INT_PCI_BC1 (MSP_SLP_INTBASE + 24) - /* PCI Block Copy 1 */ + /* PCI Block Copy 1 */ #define MSP_INT_SLP_ERR (MSP_SLP_INTBASE + 25) - /* SLP error condition */ + /* SLP error condition */ #define MSP_INT_MAC2 (MSP_SLP_INTBASE + 26) - /* IRQ for MAC2 */ -/* Reserved 26-31 */ + /* IRQ for MAC2 */ +/* Reserved 26-31 */ /* * IRQs cascaded on SLP PER interrupt (MSP_INT_PER) */ #define MSP_PER_INTBASE (MSP_SLP_INTBASE + 32) -/* Reserved 0-1 */ +/* Reserved 0-1 */ #define MSP_INT_UART1 (MSP_PER_INTBASE + 2) - /* UART 1 */ -/* Reserved 3-5 */ + /* UART 1 */ +/* Reserved 3-5 */ #define MSP_INT_2WIRE (MSP_PER_INTBASE + 6) - /* 2-wire */ + /* 2-wire */ #define MSP_INT_TM0 (MSP_PER_INTBASE + 7) /* Peripheral timer block out 0 */ #define MSP_INT_TM1 (MSP_PER_INTBASE + 8) /* Peripheral timer block out 1 */ -/* Reserved 9 */ +/* Reserved 9 */ #define MSP_INT_SPRX (MSP_PER_INTBASE + 10) - /* SPI RX complete */ + /* SPI RX complete */ #define MSP_INT_SPTX (MSP_PER_INTBASE + 11) - /* SPI TX complete */ + /* SPI TX complete */ #define MSP_INT_GPIO (MSP_PER_INTBASE + 12) - /* GPIO */ + /* GPIO */ #define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13) - /* Peripheral error */ -/* Reserved 14-31 */ + /* Peripheral error */ +/* Reserved 14-31 */ #endif /* !_MSP_SLP_INT_H */ diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_usb.h index 4c9348df9df..fe1566f2913 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h +++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_usb.h @@ -25,11 +25,7 @@ #ifndef MSP_USB_H_ #define MSP_USB_H_ -#ifdef CONFIG_MSP_HAS_DUAL_USB -#define NUM_USB_DEVS 2 -#else #define NUM_USB_DEVS 1 -#endif /* Register spaces for USB host 0 */ #define MSP_USB0_MAB_START (MSP_USB0_BASE + 0x0) @@ -40,7 +36,7 @@ #define MSP_USB0_HS_END (MSP_USB0_BASE + 0x401FF) /* Register spaces for USB host 1 */ -#define MSP_USB1_MAB_START (MSP_USB1_BASE + 0x0) +#define MSP_USB1_MAB_START (MSP_USB1_BASE + 0x0) #define MSP_USB1_MAB_END (MSP_USB1_BASE + 0x17) #define MSP_USB1_ID_START (MSP_USB1_BASE + 0x40000) #define MSP_USB1_ID_END (MSP_USB1_BASE + 0x4008f) diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/war.h b/arch/mips/include/asm/mach-pmcs-msp71xx/war.h index c74eb1657f5..a60bf9dd14a 100644 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/war.h +++ b/arch/mips/include/asm/mach-pmcs-msp71xx/war.h @@ -21,9 +21,9 @@ #define R10000_LLSC_WAR 0 #if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \ defined(CONFIG_PMC_MSP7120_FPGA) -#define MIPS34K_MISSED_ITLB_WAR 1 +#define MIPS34K_MISSED_ITLB_WAR 1 #else -#define MIPS34K_MISSED_ITLB_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 #endif #endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */ diff --git a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h index 6d70264557b..daa85ce03ef 100644 --- a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h +++ b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h @@ -42,15 +42,15 @@ #define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* Interrupts supported by PIC */ -#define PNX833X_PIC_I2C0_INT (PNX833X_PIC_IRQ_BASE + 1) -#define PNX833X_PIC_I2C1_INT (PNX833X_PIC_IRQ_BASE + 2) -#define PNX833X_PIC_UART0_INT (PNX833X_PIC_IRQ_BASE + 3) -#define PNX833X_PIC_UART1_INT (PNX833X_PIC_IRQ_BASE + 4) -#define PNX833X_PIC_TS_IN0_DV_INT (PNX833X_PIC_IRQ_BASE + 5) -#define PNX833X_PIC_TS_IN0_DMA_INT (PNX833X_PIC_IRQ_BASE + 6) -#define PNX833X_PIC_GPIO_INT (PNX833X_PIC_IRQ_BASE + 7) -#define PNX833X_PIC_AUDIO_DEC_INT (PNX833X_PIC_IRQ_BASE + 8) -#define PNX833X_PIC_VIDEO_DEC_INT (PNX833X_PIC_IRQ_BASE + 9) +#define PNX833X_PIC_I2C0_INT (PNX833X_PIC_IRQ_BASE + 1) +#define PNX833X_PIC_I2C1_INT (PNX833X_PIC_IRQ_BASE + 2) +#define PNX833X_PIC_UART0_INT (PNX833X_PIC_IRQ_BASE + 3) +#define PNX833X_PIC_UART1_INT (PNX833X_PIC_IRQ_BASE + 4) +#define PNX833X_PIC_TS_IN0_DV_INT (PNX833X_PIC_IRQ_BASE + 5) +#define PNX833X_PIC_TS_IN0_DMA_INT (PNX833X_PIC_IRQ_BASE + 6) +#define PNX833X_PIC_GPIO_INT (PNX833X_PIC_IRQ_BASE + 7) +#define PNX833X_PIC_AUDIO_DEC_INT (PNX833X_PIC_IRQ_BASE + 8) +#define PNX833X_PIC_VIDEO_DEC_INT (PNX833X_PIC_IRQ_BASE + 9) #define PNX833X_PIC_CONFIG_INT (PNX833X_PIC_IRQ_BASE + 10) #define PNX833X_PIC_AOI_INT (PNX833X_PIC_IRQ_BASE + 11) #define PNX833X_PIC_SYNC_INT (PNX833X_PIC_IRQ_BASE + 12) diff --git a/arch/mips/include/asm/mach-pnx833x/pnx833x.h b/arch/mips/include/asm/mach-pnx833x/pnx833x.h index 100f52870e3..e6fc3a9d594 100644 --- a/arch/mips/include/asm/mach-pnx833x/pnx833x.h +++ b/arch/mips/include/asm/mach-pnx833x/pnx833x.h @@ -73,7 +73,7 @@ #define PNX833X_RESET_CONTROL PNX833X_REG(0x8004) -#define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014) +#define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014) #define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs)) #define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0) @@ -82,10 +82,10 @@ #define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3 #define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq)) -#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228) +#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228) #define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */ #define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */ -#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3 +#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3 #define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020) #define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f @@ -149,7 +149,7 @@ #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14) #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14 -#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7) +#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7) #define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7 #define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9) @@ -160,10 +160,10 @@ #define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3) #define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3 -#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2) +#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2) #define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2 -#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1) +#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1) #define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1 #define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0) diff --git a/arch/mips/include/asm/mach-pnx833x/war.h b/arch/mips/include/asm/mach-pnx833x/war.h index edaa06d9d49..e410df4e1b3 100644 --- a/arch/mips/include/asm/mach-pnx833x/war.h +++ b/arch/mips/include/asm/mach-pnx833x/war.h @@ -21,4 +21,4 @@ #define R10000_LLSC_WAR 0 #define MIPS34K_MISSED_ITLB_WAR 0 -#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */ +#endif /* __ASM_MIPS_MACH_PNX833X_WAR_H */ diff --git a/arch/mips/include/asm/mach-pnx8550/cm.h b/arch/mips/include/asm/mach-pnx8550/cm.h deleted file mode 100644 index bb0a56c7d01..00000000000 --- a/arch/mips/include/asm/mach-pnx8550/cm.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Clock module specific definitions - * - * Author: source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ - -#ifndef __PNX8550_CM_H -#define __PNX8550_CM_H - -#define PNX8550_CM_BASE 0xBBE47000 - -#define PNX8550_CM_PLL0_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000) -#define PNX8550_CM_PLL1_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004) -#define PNX8550_CM_PLL2_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008) -#define PNX8550_CM_PLL3_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C) - -// Table not complete..... - -#define PNX8550_CM_PLL_BLOCKED_MASK 0x80000000 -#define PNX8550_CM_PLL_LOCK_MASK 0x40000000 -#define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000 -#define PNX8550_CM_PLL_N_MASK 0x01ff0000 -#define PNX8550_CM_PLL_M_MASK 0x00003f00 -#define PNX8550_CM_PLL_P_MASK 0x0000000c -#define PNX8550_CM_PLL_PD_MASK 0x00000002 - - -#endif diff --git a/arch/mips/include/asm/mach-pnx8550/glb.h b/arch/mips/include/asm/mach-pnx8550/glb.h deleted file mode 100644 index 07aa85e609b..00000000000 --- a/arch/mips/include/asm/mach-pnx8550/glb.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * PNX8550 global definitions - * - * Author: source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ - -#ifndef __PNX8550_GLB_H -#define __PNX8550_GLB_H - -#define PNX8550_GLB1_BASE 0xBBE63000 -#define PNX8550_GLB2_BASE 0xBBE4d000 -#define PNX8550_RESET_BASE 0xBBE60000 - -/* PCI Inta Output Enable Registers */ -#define PNX8550_GLB2_ENAB_INTA_O *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050) - -/* Bit 1:Enable DAC Powerdown - 0:DACs are enabled and are working normally - 1:DACs are powerdown -*/ -#define PNX8550_GLB_DAC_PD 0x2 -/* Bit 0:Enable of PCI inta output - 0 = Disable PCI inta output - 1 = Enable PCI inta output -*/ -#define PNX8550_GLB_ENABLE_INTA_O 0x1 - -/* PCI Direct Mappings */ -#define PNX8550_PCIMEM 0x12000000 -#define PNX8550_PCIMEM_SIZE 0x08000000 -#define PNX8550_PCIIO 0x1c000000 -#define PNX8550_PCIIO_SIZE 0x02000000 /* 32M */ - -#define PNX8550_PORT_BASE KSEG1 - -// GPIO def -#define PNX8550_GPIO_BASE 0x1Be00000 - -#define PNX8550_GPIO_DIRQ0 (PNX8550_GPIO_BASE + 0x104500) -#define PNX8550_GPIO_MC1 (PNX8550_GPIO_BASE + 0x104004) -#define PNX8550_GPIO_MC_31_BIT 30 -#define PNX8550_GPIO_MC_30_BIT 28 -#define PNX8550_GPIO_MC_29_BIT 26 -#define PNX8550_GPIO_MC_28_BIT 24 -#define PNX8550_GPIO_MC_27_BIT 22 -#define PNX8550_GPIO_MC_26_BIT 20 -#define PNX8550_GPIO_MC_25_BIT 18 -#define PNX8550_GPIO_MC_24_BIT 16 -#define PNX8550_GPIO_MC_23_BIT 14 -#define PNX8550_GPIO_MC_22_BIT 12 -#define PNX8550_GPIO_MC_21_BIT 10 -#define PNX8550_GPIO_MC_20_BIT 8 -#define PNX8550_GPIO_MC_19_BIT 6 -#define PNX8550_GPIO_MC_18_BIT 4 -#define PNX8550_GPIO_MC_17_BIT 2 -#define PNX8550_GPIO_MC_16_BIT 0 - -#define PNX8550_GPIO_MODE_PRIMOP 0x1 -#define PNX8550_GPIO_MODE_NO_OPENDR 0x2 -#define PNX8550_GPIO_MODE_OPENDR 0x3 - -// RESET module -#define PNX8550_RST_CTL *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0) -#define PNX8550_RST_CAUSE *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4) -#define PNX8550_RST_EN_WATCHDOG *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8) - -#define PNX8550_RST_REL_MIPS_RST_N 0x8 -#define PNX8550_RST_DO_SW_RST 0x4 -#define PNX8550_RST_REL_SYS_RST_OUT 0x2 -#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1 -#endif diff --git a/arch/mips/include/asm/mach-pnx8550/int.h b/arch/mips/include/asm/mach-pnx8550/int.h deleted file mode 100644 index 0e0668b524f..00000000000 --- a/arch/mips/include/asm/mach-pnx8550/int.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Interrupt specific definitions - * - * Author: source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ - -#ifndef __PNX8550_INT_H -#define __PNX8550_INT_H - -#define PNX8550_GIC_BASE 0xBBE3E000 - -#define PNX8550_GIC_PRIMASK_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x000) -#define PNX8550_GIC_PRIMASK_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x004) -#define PNX8550_GIC_VECTOR_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x100) -#define PNX8550_GIC_VECTOR_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x104) -#define PNX8550_GIC_PEND_1_31 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x200) -#define PNX8550_GIC_PEND_32_63 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x204) -#define PNX8550_GIC_PEND_64_70 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x208) -#define PNX8550_GIC_FEATURES *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x300) -#define PNX8550_GIC_REQ(x) *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x400 + (x)*4) -#define PNX8550_GIC_MOD_ID *(volatile unsigned long *)(PNX8550_GIC_BASE + 0xFFC) - -// cp0 is two software + six hw exceptions -#define PNX8550_INT_CP0_TOTINT 8 -#define PNX8550_INT_CP0_MIN 0 -#define PNX8550_INT_CP0_MAX (PNX8550_INT_CP0_MIN + PNX8550_INT_CP0_TOTINT - 1) - -#define MIPS_CPU_GIC_IRQ 2 -#define MIPS_CPU_TIMER_IRQ 7 - -// GIC are 71 exceptions connected to cp0's first hardware exception -#define PNX8550_INT_GIC_TOTINT 71 -#define PNX8550_INT_GIC_MIN (PNX8550_INT_CP0_MAX+1) -#define PNX8550_INT_GIC_MAX (PNX8550_INT_GIC_MIN + PNX8550_INT_GIC_TOTINT - 1) - -#define PNX8550_INT_UNDEF (PNX8550_INT_GIC_MIN+0) -#define PNX8550_INT_IPC_TARGET0_MIPS (PNX8550_INT_GIC_MIN+1) -#define PNX8550_INT_IPC_TARGET1_TM32_1 (PNX8550_INT_GIC_MIN+2) -#define PNX8550_INT_IPC_TARGET1_TM32_2 (PNX8550_INT_GIC_MIN+3) -#define PNX8550_INT_RESERVED_4 (PNX8550_INT_GIC_MIN+4) -#define PNX8550_INT_USB (PNX8550_INT_GIC_MIN+5) -#define PNX8550_INT_GPIO_EQ1 (PNX8550_INT_GIC_MIN+6) -#define PNX8550_INT_GPIO_EQ2 (PNX8550_INT_GIC_MIN+7) -#define PNX8550_INT_GPIO_EQ3 (PNX8550_INT_GIC_MIN+8) -#define PNX8550_INT_GPIO_EQ4 (PNX8550_INT_GIC_MIN+9) - -#define PNX8550_INT_GPIO_EQ5 (PNX8550_INT_GIC_MIN+10) -#define PNX8550_INT_GPIO_EQ6 (PNX8550_INT_GIC_MIN+11) -#define PNX8550_INT_RESERVED_12 (PNX8550_INT_GIC_MIN+12) -#define PNX8550_INT_QVCP1 (PNX8550_INT_GIC_MIN+13) -#define PNX8550_INT_QVCP2 (PNX8550_INT_GIC_MIN+14) -#define PNX8550_INT_I2C1 (PNX8550_INT_GIC_MIN+15) -#define PNX8550_INT_I2C2 (PNX8550_INT_GIC_MIN+16) -#define PNX8550_INT_ISO_UART1 (PNX8550_INT_GIC_MIN+17) -#define PNX8550_INT_ISO_UART2 (PNX8550_INT_GIC_MIN+18) -#define PNX8550_INT_UART1 (PNX8550_INT_GIC_MIN+19) - -#define PNX8550_INT_UART2 (PNX8550_INT_GIC_MIN+20) -#define PNX8550_INT_QNTR (PNX8550_INT_GIC_MIN+21) -#define PNX8550_INT_RESERVED22 (PNX8550_INT_GIC_MIN+22) -#define PNX8550_INT_T_DSC (PNX8550_INT_GIC_MIN+23) -#define PNX8550_INT_M_DSC (PNX8550_INT_GIC_MIN+24) -#define PNX8550_INT_RESERVED25 (PNX8550_INT_GIC_MIN+25) -#define PNX8550_INT_2D_DRAW_ENG (PNX8550_INT_GIC_MIN+26) -#define PNX8550_INT_MEM_BASED_SCALAR1 (PNX8550_INT_GIC_MIN+27) -#define PNX8550_INT_VIDEO_MPEG (PNX8550_INT_GIC_MIN+28) -#define PNX8550_INT_VIDEO_INPUT_P1 (PNX8550_INT_GIC_MIN+29) - -#define PNX8550_INT_VIDEO_INPUT_P2 (PNX8550_INT_GIC_MIN+30) -#define PNX8550_INT_SPDI1 (PNX8550_INT_GIC_MIN+31) -#define PNX8550_INT_SPDO (PNX8550_INT_GIC_MIN+32) -#define PNX8550_INT_AUDIO_INPUT1 (PNX8550_INT_GIC_MIN+33) -#define PNX8550_INT_AUDIO_OUTPUT1 (PNX8550_INT_GIC_MIN+34) -#define PNX8550_INT_AUDIO_INPUT2 (PNX8550_INT_GIC_MIN+35) -#define PNX8550_INT_AUDIO_OUTPUT2 (PNX8550_INT_GIC_MIN+36) -#define PNX8550_INT_MEMBASED_SCALAR2 (PNX8550_INT_GIC_MIN+37) -#define PNX8550_INT_VPK (PNX8550_INT_GIC_MIN+38) -#define PNX8550_INT_MPEG1_MIPS (PNX8550_INT_GIC_MIN+39) - -#define PNX8550_INT_MPEG1_TM (PNX8550_INT_GIC_MIN+40) -#define PNX8550_INT_MPEG2_MIPS (PNX8550_INT_GIC_MIN+41) -#define PNX8550_INT_MPEG2_TM (PNX8550_INT_GIC_MIN+42) -#define PNX8550_INT_TS_DMA (PNX8550_INT_GIC_MIN+43) -#define PNX8550_INT_EDMA (PNX8550_INT_GIC_MIN+44) -#define PNX8550_INT_TM_DEBUG1 (PNX8550_INT_GIC_MIN+45) -#define PNX8550_INT_TM_DEBUG2 (PNX8550_INT_GIC_MIN+46) -#define PNX8550_INT_PCI_INTA (PNX8550_INT_GIC_MIN+47) -#define PNX8550_INT_CLOCK_MODULE (PNX8550_INT_GIC_MIN+48) -#define PNX8550_INT_PCI_XIO_INTA_PCI (PNX8550_INT_GIC_MIN+49) - -#define PNX8550_INT_PCI_XIO_INTB_DMA (PNX8550_INT_GIC_MIN+50) -#define PNX8550_INT_PCI_XIO_INTC_GPPM (PNX8550_INT_GIC_MIN+51) -#define PNX8550_INT_PCI_XIO_INTD_GPXIO (PNX8550_INT_GIC_MIN+52) -#define PNX8550_INT_DVD_CSS (PNX8550_INT_GIC_MIN+53) -#define PNX8550_INT_VLD (PNX8550_INT_GIC_MIN+54) -#define PNX8550_INT_GPIO_TSU_7_0 (PNX8550_INT_GIC_MIN+55) -#define PNX8550_INT_GPIO_TSU_15_8 (PNX8550_INT_GIC_MIN+56) -#define PNX8550_INT_GPIO_CTU_IR (PNX8550_INT_GIC_MIN+57) -#define PNX8550_INT_GPIO0 (PNX8550_INT_GIC_MIN+58) -#define PNX8550_INT_GPIO1 (PNX8550_INT_GIC_MIN+59) - -#define PNX8550_INT_GPIO2 (PNX8550_INT_GIC_MIN+60) -#define PNX8550_INT_GPIO3 (PNX8550_INT_GIC_MIN+61) -#define PNX8550_INT_GPIO4 (PNX8550_INT_GIC_MIN+62) -#define PNX8550_INT_GPIO5 (PNX8550_INT_GIC_MIN+63) -#define PNX8550_INT_GPIO6 (PNX8550_INT_GIC_MIN+64) -#define PNX8550_INT_GPIO7 (PNX8550_INT_GIC_MIN+65) -#define PNX8550_INT_PMAN_SECURITY (PNX8550_INT_GIC_MIN+66) -#define PNX8550_INT_I2C3 (PNX8550_INT_GIC_MIN+67) -#define PNX8550_INT_RESERVED_68 (PNX8550_INT_GIC_MIN+68) -#define PNX8550_INT_SPDI2 (PNX8550_INT_GIC_MIN+69) - -#define PNX8550_INT_I2C4 (PNX8550_INT_GIC_MIN+70) - -// Timer are 3 exceptions connected to cp0's 7th hardware exception -#define PNX8550_INT_TIMER_TOTINT 3 -#define PNX8550_INT_TIMER_MIN (PNX8550_INT_GIC_MAX+1) -#define PNX8550_INT_TIMER_MAX (PNX8550_INT_TIMER_MIN + PNX8550_INT_TIMER_TOTINT - 1) - -#define PNX8550_INT_TIMER1 (PNX8550_INT_TIMER_MIN+0) -#define PNX8550_INT_TIMER2 (PNX8550_INT_TIMER_MIN+1) -#define PNX8550_INT_TIMER3 (PNX8550_INT_TIMER_MIN+2) -#define PNX8550_INT_WATCHDOG PNX8550_INT_TIMER3 - -#endif diff --git a/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h b/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h deleted file mode 100644 index bdde00c9199..00000000000 --- a/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2005 Embedded Alley Solutions, Inc - */ -#ifndef __ASM_MACH_KERNEL_ENTRY_INIT_H -#define __ASM_MACH_KERNEL_ENTRY_INIT_H - -#include <asm/cacheops.h> -#include <asm/addrspace.h> - -#define CO_CONFIGPR_VALID 0x3F1F41FF /* valid bits to write to ConfigPR */ -#define HAZARD_CP0 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; -#define CACHE_OPC 0xBC000000 /* MIPS cache instruction opcode */ -#define ICACHE_LINE_SIZE 32 /* Instruction cache line size bytes */ -#define DCACHE_LINE_SIZE 32 /* Data cache line size in bytes */ - -#define ICACHE_SET_COUNT 256 /* Instruction cache set count */ -#define DCACHE_SET_COUNT 128 /* Data cache set count */ - -#define ICACHE_SET_SIZE (ICACHE_SET_COUNT * ICACHE_LINE_SIZE) -#define DCACHE_SET_SIZE (DCACHE_SET_COUNT * DCACHE_LINE_SIZE) - - .macro kernel_entry_setup - .set push - .set noreorder - /* - * PNX8550 entry point, when running a non compressed - * kernel. When loading a zImage, the head.S code in - * arch/mips/zboot/pnx8550 will init the caches and, - * decompress the kernel, and branch to kernel_entry. - */ -cache_begin: li t0, (1<<28) - mtc0 t0, CP0_STATUS /* cp0 usable */ - HAZARD_CP0 - - mtc0 zero, CP0_CAUSE - HAZARD_CP0 - - - /* Set static virtual to phys address translation and TLB disabled */ - mfc0 t0, CP0_CONFIG, 7 - HAZARD_CP0 - - and t0, ~((1<<19) | (1<<20)) /* TLB/MAP cleared */ - mtc0 t0, CP0_CONFIG, 7 - HAZARD_CP0 - - /* CPU boots with kseg0 cache algo set to 0x2 -- uncached */ - - init_icache - nop - init_dcache - nop - - cachePr4450ICReset - nop - - cachePr4450DCReset - nop - - /* read ConfigPR into t0 */ - mfc0 t0, CP0_CONFIG, 7 - HAZARD_CP0 - - /* enable the TLB */ - or t0, (1<<19) - - /* disable the ICACHE: at least 10x slower */ - /* or t0, (1<<26) */ - - /* disable the DCACHE; CONFIG_CPU_HAS_LLSC should not be set */ - /* or t0, (1<<27) */ - - and t0, CO_CONFIGPR_VALID - - /* enable TLB. */ - mtc0 t0, CP0_CONFIG, 7 - HAZARD_CP0 -cache_end: - /* Setup CMEM_0 to MMIO address space, 2MB */ - lui t0, 0x1BE0 - addi t0, t0, 0x3 - mtc0 $8, $22, 4 - nop - - /* Setup CMEM_1, 128MB */ - lui t0, 0x1000 - addi t0, t0, 0xf - mtc0 $8, $22, 5 - nop - - - /* Setup CMEM_2, 32MB */ - lui t0, 0x1C00 - addi t0, t0, 0xb - mtc0 $8, $22, 6 - nop - - /* Setup CMEM_3, 0MB */ - lui t0, 0x0 - addi t0, t0, 0x0 - mtc0 $8, $22, 7 - nop - - /* Enable cache */ - mfc0 t0, CP0_CONFIG - HAZARD_CP0 - and t0, t0, 0xFFFFFFF8 - or t0, t0, 3 - mtc0 t0, CP0_CONFIG - HAZARD_CP0 - .set pop - .endm - - .macro init_icache - .set push - .set noreorder - - /* Get Cache Configuration */ - mfc0 t3, CP0_CONFIG, 1 - HAZARD_CP0 - - /* get cache Line size */ - - srl t1, t3, 19 /* C0_CONFIGPR_IL_SHIFT */ - andi t1, t1, 0x7 /* C0_CONFIGPR_IL_MASK */ - beq t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */ - nop - addiu t0, t1, 1 - ori t1, zero, 1 - sllv t1, t1, t0 - - /* get max cache Index */ - srl t2, t3, 22 /* C0_CONFIGPR_IS_SHIFT */ - andi t2, t2, 0x7 /* C0_CONFIGPR_IS_MASK */ - addiu t0, t2, 6 - ori t2, zero, 1 - sllv t2, t2, t0 - - /* get max cache way */ - srl t3, t3, 16 /* C0_CONFIGPR_IA_SHIFT */ - andi t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */ - addiu t3, t3, 1 - - /* total no of cache lines */ - multu t2, t3 /* max index * max way */ - mflo t2 - addiu t2, t2, -1 - - move t0, zero -pr4450_next_instruction_cache_set: - cache Index_Invalidate_I, 0(t0) - addu t0, t0, t1 /* add bytes in a line */ - bne t2, zero, pr4450_next_instruction_cache_set - addiu t2, t2, -1 /* reduce no of lines to invalidate by one */ -pr4450_instr_cache_invalidated: - .set pop - .endm - - .macro init_dcache - .set push - .set noreorder - move t1, zero - - /* Store Tag Information */ - mtc0 zero, CP0_TAGLO, 0 - HAZARD_CP0 - - mtc0 zero, CP0_TAGHI, 0 - HAZARD_CP0 - - /* Cache size is 16384 = 512 lines x 32 bytes per line */ - or t2, zero, (128*4)-1 /* 512 lines */ - /* Invalidate all lines */ -2: - cache Index_Store_Tag_D, 0(t1) - addiu t2, t2, -1 - bne t2, zero, 2b - addiu t1, t1, 32 /* 32 bytes in a line */ - .set pop - .endm - - .macro cachePr4450ICReset - .set push - .set noreorder - - /* Save CP0 status reg on entry; */ - /* disable interrupts during cache reset */ - mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */ - HAZARD_CP0 - - mtc0 zero, CP0_STATUS /* disable CPU interrupts */ - HAZARD_CP0 - - or t1, zero, zero /* T1 = starting cache index (0) */ - ori t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */ - - icache_invd_loop: - /* 9 == register t1 */ - .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ - (0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */ - .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ - (1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */ - - addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */ - bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */ - addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */ - - /* Initialize the latches in the instruction cache tag */ - /* that drive the way selection tri-state bus drivers, by doing a */ - /* dummy load while the instruction cache is still disabled. */ - /* TODO: Is this needed ? */ - la t1, KSEG0 /* T1 = cached memory base address */ - lw zero, 0x0000(t1) /* (dummy read of first memory word) */ - - mtc0 t0, CP0_STATUS /* restore interrupt status on entry */ - HAZARD_CP0 - .set pop - .endm - - .macro cachePr4450DCReset - .set push - .set noreorder - mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */ - HAZARD_CP0 - mtc0 zero, CP0_STATUS /* disable CPU interrupts */ - HAZARD_CP0 - - /* Writeback/invalidate entire data cache sets/ways/lines */ - or t1, zero, zero /* T1 = starting cache index (0) */ - ori t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */ - - dcache_wbinvd_loop: - /* 9 == register t1 */ - .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ - (0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */ - .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ - (1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */ - .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ - (2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */ - .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ - (3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */ - - addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */ - bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */ - addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */ - - /* Initialize the latches in the data cache tag that drive the way - selection tri-state bus drivers, by doing a dummy load while the - data cache is still in the disabled mode. TODO: Is this needed ? */ - la t1, KSEG0 /* T1 = cached memory base address */ - lw zero, 0x0000(t1) /* (dummy read of first memory word) */ - - mtc0 t0, CP0_STATUS /* restore interrupt status on entry */ - HAZARD_CP0 - .set pop - .endm - -#endif /* __ASM_MACH_KERNEL_ENTRY_INIT_H */ diff --git a/arch/mips/include/asm/mach-pnx8550/nand.h b/arch/mips/include/asm/mach-pnx8550/nand.h deleted file mode 100644 index aefbc514ab0..00000000000 --- a/arch/mips/include/asm/mach-pnx8550/nand.h +++ /dev/null @@ -1,121 +0,0 @@ -#ifndef __PNX8550_NAND_H -#define __PNX8550_NAND_H - -#define PNX8550_NAND_BASE_ADDR 0x10000000 -#define PNX8550_PCIXIO_BASE 0xBBE40000 - -#define PNX8550_DMA_EXT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x800) -#define PNX8550_DMA_INT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x804) -#define PNX8550_DMA_TRANS_SIZE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x808) -#define PNX8550_DMA_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x80c) -#define PNX8550_XIO_SEL0 *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x814) -#define PNX8550_GPXIO_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x820) -#define PNX8550_GPXIO_WR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x824) -#define PNX8550_GPXIO_RD *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x828) -#define PNX8550_GPXIO_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x82C) -#define PNX8550_XIO_FLASH_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x830) -#define PNX8550_GPXIO_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb0) -#define PNX8550_GPXIO_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb4) -#define PNX8550_GPXIO_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb8) -#define PNX8550_DMA_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd0) -#define PNX8550_DMA_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd4) -#define PNX8550_DMA_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd8) - -#define PNX8550_XIO_SEL0_EN_16BIT 0x00800000 -#define PNX8550_XIO_SEL0_USE_ACK 0x00400000 -#define PNX8550_XIO_SEL0_REN_HIGH 0x00100000 -#define PNX8550_XIO_SEL0_REN_LOW 0x00040000 -#define PNX8550_XIO_SEL0_WEN_HIGH 0x00010000 -#define PNX8550_XIO_SEL0_WEN_LOW 0x00004000 -#define PNX8550_XIO_SEL0_WAIT 0x00000200 -#define PNX8550_XIO_SEL0_OFFSET 0x00000020 -#define PNX8550_XIO_SEL0_TYPE_68360 0x00000000 -#define PNX8550_XIO_SEL0_TYPE_NOR 0x00000008 -#define PNX8550_XIO_SEL0_TYPE_NAND 0x00000010 -#define PNX8550_XIO_SEL0_TYPE_IDE 0x00000018 -#define PNX8550_XIO_SEL0_SIZE_8MB 0x00000000 -#define PNX8550_XIO_SEL0_SIZE_16MB 0x00000002 -#define PNX8550_XIO_SEL0_SIZE_32MB 0x00000004 -#define PNX8550_XIO_SEL0_SIZE_64MB 0x00000006 -#define PNX8550_XIO_SEL0_ENAB 0x00000001 - -#define PNX8550_SEL0_DEFAULT ((PNX8550_XIO_SEL0_EN_16BIT) | \ - (PNX8550_XIO_SEL0_REN_HIGH*0)| \ - (PNX8550_XIO_SEL0_REN_LOW*2) | \ - (PNX8550_XIO_SEL0_WEN_HIGH*0)| \ - (PNX8550_XIO_SEL0_WEN_LOW*2) | \ - (PNX8550_XIO_SEL0_WAIT*4) | \ - (PNX8550_XIO_SEL0_OFFSET*0) | \ - (PNX8550_XIO_SEL0_TYPE_NAND) | \ - (PNX8550_XIO_SEL0_SIZE_32MB) | \ - (PNX8550_XIO_SEL0_ENAB)) - -#define PNX8550_GPXIO_PENDING 0x00000200 -#define PNX8550_GPXIO_DONE 0x00000100 -#define PNX8550_GPXIO_CLR_DONE 0x00000080 -#define PNX8550_GPXIO_INIT 0x00000040 -#define PNX8550_GPXIO_READ_CMD 0x00000010 -#define PNX8550_GPXIO_BEN 0x0000000F - -#define PNX8550_XIO_FLASH_64MB 0x00200000 -#define PNX8550_XIO_FLASH_INC_DATA 0x00100000 -#define PNX8550_XIO_FLASH_CMD_PH 0x000C0000 -#define PNX8550_XIO_FLASH_CMD_PH2 0x00080000 -#define PNX8550_XIO_FLASH_CMD_PH1 0x00040000 -#define PNX8550_XIO_FLASH_CMD_PH0 0x00000000 -#define PNX8550_XIO_FLASH_ADR_PH 0x00030000 -#define PNX8550_XIO_FLASH_ADR_PH3 0x00030000 -#define PNX8550_XIO_FLASH_ADR_PH2 0x00020000 -#define PNX8550_XIO_FLASH_ADR_PH1 0x00010000 -#define PNX8550_XIO_FLASH_ADR_PH0 0x00000000 -#define PNX8550_XIO_FLASH_CMD_B(x) ((x<<8) & 0x0000FF00) -#define PNX8550_XIO_FLASH_CMD_A(x) (x & 0x000000FF) - -#define PNX8550_XIO_INT_ACK 0x00004000 -#define PNX8550_XIO_INT_COMPL 0x00002000 -#define PNX8550_XIO_INT_NONSUP 0x00000200 -#define PNX8550_XIO_INT_ABORT 0x00000004 - -#define PNX8550_DMA_CTRL_SINGLE_DATA 0x00000400 -#define PNX8550_DMA_CTRL_SND2XIO 0x00000200 -#define PNX8550_DMA_CTRL_FIX_ADDR 0x00000100 -#define PNX8550_DMA_CTRL_BURST_8 0x00000000 -#define PNX8550_DMA_CTRL_BURST_16 0x00000020 -#define PNX8550_DMA_CTRL_BURST_32 0x00000040 -#define PNX8550_DMA_CTRL_BURST_64 0x00000060 -#define PNX8550_DMA_CTRL_BURST_128 0x00000080 -#define PNX8550_DMA_CTRL_BURST_256 0x000000A0 -#define PNX8550_DMA_CTRL_BURST_512 0x000000C0 -#define PNX8550_DMA_CTRL_BURST_NORES 0x000000E0 -#define PNX8550_DMA_CTRL_INIT_DMA 0x00000010 -#define PNX8550_DMA_CTRL_CMD_TYPE 0x0000000F - -/* see PCI system arch, page 100 for the full list: */ -#define PNX8550_DMA_CTRL_PCI_CMD_READ 0x00000006 -#define PNX8550_DMA_CTRL_PCI_CMD_WRITE 0x00000007 - -#define PNX8550_DMA_INT_STAT_ACK_DONE (1<<14) -#define PNX8550_DMA_INT_STAT_DMA_DONE (1<<12) -#define PNX8550_DMA_INT_STAT_DMA_ERR (1<<9) -#define PNX8550_DMA_INT_STAT_PERR5 (1<<5) -#define PNX8550_DMA_INT_STAT_PERR4 (1<<4) -#define PNX8550_DMA_INT_STAT_M_ABORT (1<<2) -#define PNX8550_DMA_INT_STAT_T_ABORT (1<<1) - -#define PNX8550_DMA_INT_EN_ACK_DONE (1<<14) -#define PNX8550_DMA_INT_EN_DMA_DONE (1<<12) -#define PNX8550_DMA_INT_EN_DMA_ERR (1<<9) -#define PNX8550_DMA_INT_EN_PERR5 (1<<5) -#define PNX8550_DMA_INT_EN_PERR4 (1<<4) -#define PNX8550_DMA_INT_EN_M_ABORT (1<<2) -#define PNX8550_DMA_INT_EN_T_ABORT (1<<1) - -#define PNX8550_DMA_INT_CLR_ACK_DONE (1<<14) -#define PNX8550_DMA_INT_CLR_DMA_DONE (1<<12) -#define PNX8550_DMA_INT_CLR_DMA_ERR (1<<9) -#define PNX8550_DMA_INT_CLR_PERR5 (1<<5) -#define PNX8550_DMA_INT_CLR_PERR4 (1<<4) -#define PNX8550_DMA_INT_CLR_M_ABORT (1<<2) -#define PNX8550_DMA_INT_CLR_T_ABORT (1<<1) - -#endif diff --git a/arch/mips/include/asm/mach-pnx8550/pci.h b/arch/mips/include/asm/mach-pnx8550/pci.h deleted file mode 100644 index b921508d701..00000000000 --- a/arch/mips/include/asm/mach-pnx8550/pci.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * PCI specific definitions - * - * Author: source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ - -#ifndef __PNX8550_PCI_H -#define __PNX8550_PCI_H - -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/init.h> - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -#define PCI_CMD_IOR 0x20 -#define PCI_CMD_IOW 0x30 -#define PCI_CMD_CONFIG_READ 0xa0 -#define PCI_CMD_CONFIG_WRITE 0xb0 - -#define PCI_IO_TIMEOUT 1000 -#define PCI_IO_RETRY 5 -/* Timeout for IO and CFG accesses. - This is in 1/1024 th of a jiffie(=10ms) - i.e. approx 10us */ -#define PCI_IO_JIFFIES_TIMEOUT 40 -#define PCI_IO_JIFFIES_SHIFT 10 - -#define PCI_BYTE_ENABLE_MASK 0x0000000f -#define PCI_CFG_BUS_SHIFT 16 -#define PCI_CFG_FUNC_SHIFT 8 -#define PCI_CFG_REG_SHIFT 2 - -#define PCI_BASE 0x1be00000 -#define PCI_SETUP 0x00040010 -#define PCI_DIS_REQGNT (1<<30) -#define PCI_DIS_REQGNTA (1<<29) -#define PCI_DIS_REQGNTB (1<<28) -#define PCI_D2_SUPPORT (1<<27) -#define PCI_D1_SUPPORT (1<<26) -#define PCI_EN_TA (1<<24) -#define PCI_EN_PCI2MMI (1<<23) -#define PCI_EN_XIO (1<<22) -#define PCI_BASE18_PREF (1<<21) -#define SIZE_16M 0x3 -#define SIZE_32M 0x4 -#define SIZE_64M 0x5 -#define SIZE_128M 0x6 -#define PCI_SETUP_BASE18_SIZE(X) (X<<18) -#define PCI_SETUP_BASE18_EN (1<<17) -#define PCI_SETUP_BASE14_PREF (1<<16) -#define PCI_SETUP_BASE14_SIZE(X) (X<<12) -#define PCI_SETUP_BASE14_EN (1<<11) -#define PCI_SETUP_BASE10_PREF (1<<10) -#define PCI_SETUP_BASE10_SIZE(X) (X<<7) -#define PCI_SETUP_CFGMANAGE_EN (1<<1) -#define PCI_SETUP_PCIARB_EN (1<<0) - -#define PCI_CTRL 0x040014 -#define PCI_SWPB_DCS_PCI (1<<16) -#define PCI_SWPB_PCI_PCI (1<<15) -#define PCI_SWPB_PCI_DCS (1<<14) -#define PCI_REG_WR_POST (1<<13) -#define PCI_XIO_WR_POST (1<<12) -#define PCI_PCI2_WR_POST (1<<13) -#define PCI_PCI1_WR_POST (1<<12) -#define PCI_SERR_SEEN (1<<11) -#define PCI_B10_SPEC_RD (1<<6) -#define PCI_B14_SPEC_RD (1<<5) -#define PCI_B18_SPEC_RD (1<<4) -#define PCI_B10_NOSUBWORD (1<<3) -#define PCI_B14_NOSUBWORD (1<<2) -#define PCI_B18_NOSUBWORD (1<<1) -#define PCI_RETRY_TMREN (1<<0) - -#define PCI_BASE1_LO 0x040018 -#define PCI_BASE1_HI 0x04001C -#define PCI_BASE2_LO 0x040020 -#define PCI_BASE2_HI 0x040024 -#define PCI_RDLIFETIM 0x040028 -#define PCI_GPPM_ADDR 0x04002C -#define PCI_GPPM_WDAT 0x040030 -#define PCI_GPPM_RDAT 0x040034 -#define PCI_GPPM_CTRL 0x040038 -#define GPPM_DONE (1<<10) -#define INIT_PCI_CYCLE (1<<9) -#define GPPM_CMD(X) (((X)&0xf)<<4) -#define GPPM_BYTEEN(X) ((X)&0xf) -#define PCI_UNLOCKREG 0x04003C -#define UNLOCK_SSID(X) (((X)&0xff)<<8) -#define UNLOCK_SETUP(X) (((X)&0xff)<<0) -#define UNLOCK_MAGIC 0xCA -#define PCI_DEV_VEND_ID 0x040040 -#define DEVICE_ID(X) (((X)>>16)&0xffff) -#define VENDOR_ID(X) (((X)&0xffff)) -#define PCI_CFG_CMDSTAT 0x040044 -#define PCI_CFG_STATUS(X) (((X)>>16)&0xffff) -#define PCI_CFG_COMMAND(X) ((X)&0xffff) -#define PCI_CLASS_REV 0x040048 -#define PCI_CLASSCODE(X) (((X)>>8)&0xffffff) -#define PCI_REVID(X) ((X)&0xff) -#define PCI_LAT_TMR 0x04004c -#define PCI_BASE10 0x040050 -#define PCI_BASE14 0x040054 -#define PCI_BASE18 0x040058 -#define PCI_SUBSYS_ID 0x04006c -#define PCI_CAP_PTR 0x040074 -#define PCI_CFG_MISC 0x04007c -#define PCI_PMC 0x040080 -#define PCI_PWR_STATE 0x040084 -#define PCI_IO 0x040088 -#define PCI_SLVTUNING 0x04008C -#define PCI_DMATUNING 0x040090 -#define PCI_DMAEADDR 0x040800 -#define PCI_DMAIADDR 0x040804 -#define PCI_DMALEN 0x040808 -#define PCI_DMACTRL 0x04080C -#define PCI_XIOCTRL 0x040810 -#define PCI_SEL0PROF 0x040814 -#define PCI_SEL1PROF 0x040818 -#define PCI_SEL2PROF 0x04081C -#define PCI_GPXIOADDR 0x040820 -#define PCI_NANDCTRLS 0x400830 -#define PCI_SEL3PROF 0x040834 -#define PCI_SEL4PROF 0x040838 -#define PCI_GPXIO_STAT 0x040FB0 -#define PCI_GPXIO_IMASK 0x040FB4 -#define PCI_GPXIO_ICLR 0x040FB8 -#define PCI_GPXIO_ISET 0x040FBC -#define PCI_GPPM_STATUS 0x040FC0 -#define GPPM_DONE (1<<10) -#define GPPM_ERR (1<<9) -#define GPPM_MPAR_ERR (1<<8) -#define GPPM_PAR_ERR (1<<7) -#define GPPM_R_MABORT (1<<2) -#define GPPM_R_TABORT (1<<1) -#define PCI_GPPM_IMASK 0x040FC4 -#define PCI_GPPM_ICLR 0x040FC8 -#define PCI_GPPM_ISET 0x040FCC -#define PCI_DMA_STATUS 0x040FD0 -#define PCI_DMA_IMASK 0x040FD4 -#define PCI_DMA_ICLR 0x040FD8 -#define PCI_DMA_ISET 0x040FDC -#define PCI_ISTATUS 0x040FE0 -#define PCI_IMASK 0x040FE4 -#define PCI_ICLR 0x040FE8 -#define PCI_ISET 0x040FEC -#define PCI_MOD_ID 0x040FFC - -/* - * PCI configuration cycle AD bus definition - */ -/* Type 0 */ -#define PCI_CFG_TYPE0_REG_SHF 0 -#define PCI_CFG_TYPE0_FUNC_SHF 8 - -/* Type 1 */ -#define PCI_CFG_TYPE1_REG_SHF 0 -#define PCI_CFG_TYPE1_FUNC_SHF 8 -#define PCI_CFG_TYPE1_DEV_SHF 11 -#define PCI_CFG_TYPE1_BUS_SHF 16 - -/* - * Ethernet device DP83816 definition - */ -#define DP83816_IRQ_ETHER 66 - -#endif diff --git a/arch/mips/include/asm/mach-pnx8550/uart.h b/arch/mips/include/asm/mach-pnx8550/uart.h deleted file mode 100644 index ad7608d4487..00000000000 --- a/arch/mips/include/asm/mach-pnx8550/uart.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __IP3106_UART_H -#define __IP3106_UART_H - -#include <int.h> - -/* early macros for kgdb use. fixme: clean this up */ - -#define UART_BASE 0xbbe4a000 /* PNX8550 */ - -#define PNX8550_UART_PORT0 (UART_BASE) -#define PNX8550_UART_PORT1 (UART_BASE + 0x1000) - -#define PNX8550_UART_INT(x) (PNX8550_INT_GIC_MIN+19+x) -#define IRQ_TO_UART(x) (x-PNX8550_INT_GIC_MIN-19) - -/* early macros needed for prom/kgdb */ - -#define ip3106_lcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x000) -#define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004) -#define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008) -#define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C) -#define ip3106_fifo(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x028) -#define ip3106_istat(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE0) -#define ip3106_ien(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE4) -#define ip3106_iclr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE8) -#define ip3106_iset(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFEC) -#define ip3106_pd(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFF4) -#define ip3106_mid(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFFC) - -#endif diff --git a/arch/mips/include/asm/mach-pnx8550/usb.h b/arch/mips/include/asm/mach-pnx8550/usb.h deleted file mode 100644 index 483b7fc65d4..00000000000 --- a/arch/mips/include/asm/mach-pnx8550/usb.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * USB specific definitions - * - * Author: source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ - -#ifndef __PNX8550_USB_H -#define __PNX8550_USB_H - -/* - * USB Host controller - */ - -#define PNX8550_USB_OHCI_OP_BASE 0x1be48000 -#define PNX8550_USB_OHCI_OP_LEN 0x1000 - -#endif diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h deleted file mode 100644 index c7077a64b9a..00000000000 --- a/arch/mips/include/asm/mach-powertv/asic.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _ASM_MACH_POWERTV_ASIC_H -#define _ASM_MACH_POWERTV_ASIC_H - -#include <linux/ioport.h> -#include <linux/platform_device.h> -#include <asm/mach-powertv/asic_regs.h> - -#define DVR_CAPABLE (1<<0) -#define PCIE_CAPABLE (1<<1) -#define FFS_CAPABLE (1<<2) -#define DISPLAY_CAPABLE (1<<3) - -/* Platform Family types - * For compitability, the new value must be added in the end */ -enum family_type { - FAMILY_8500, - FAMILY_8500RNG, - FAMILY_4500, - FAMILY_1500, - FAMILY_8600, - FAMILY_4600, - FAMILY_4600VZA, - FAMILY_8600VZB, - FAMILY_1500VZE, - FAMILY_1500VZF, - FAMILY_8700, - FAMILIES -}; - -/* Register maps for each ASIC */ -extern const struct register_map calliope_register_map; -extern const struct register_map cronus_register_map; -extern const struct register_map gaia_register_map; -extern const struct register_map zeus_register_map; - -extern struct resource dvr_cronus_resources[]; -extern struct resource dvr_gaia_resources[]; -extern struct resource dvr_zeus_resources[]; -extern struct resource non_dvr_calliope_resources[]; -extern struct resource non_dvr_cronus_resources[]; -extern struct resource non_dvr_cronuslite_resources[]; -extern struct resource non_dvr_gaia_resources[]; -extern struct resource non_dvr_vz_calliope_resources[]; -extern struct resource non_dvr_vze_calliope_resources[]; -extern struct resource non_dvr_vzf_calliope_resources[]; -extern struct resource non_dvr_zeus_resources[]; - -extern void powertv_platform_init(void); -extern void platform_alloc_bootmem(void); -extern enum asic_type platform_get_asic(void); -extern enum family_type platform_get_family(void); -extern int platform_supports_dvr(void); -extern int platform_supports_ffs(void); -extern int platform_supports_pcie(void); -extern int platform_supports_display(void); -extern void configure_platform(void); - -/* Platform Resources */ -#define ASIC_RESOURCE_GET_EXISTS 1 -extern struct resource *asic_resource_get(const char *name); -extern void platform_release_memory(void *baddr, int size); - -/* USB configuration */ -struct usb_hcd; /* Forward reference */ -extern void platform_configure_usb_ehci(void); -extern void platform_unconfigure_usb_ehci(void); -extern void platform_configure_usb_ohci(void); -extern void platform_unconfigure_usb_ohci(void); - -/* Resource for ASIC registers */ -extern struct resource asic_resource; -extern int platform_usb_devices_init(struct platform_device **echi_dev, - struct platform_device **ohci_dev); - -/* Reboot Cause */ -extern void set_reboot_cause(char code, unsigned int data, unsigned int data2); -extern void set_locked_reboot_cause(char code, unsigned int data, - unsigned int data2); - -enum sys_reboot_type { - sys_unknown_reboot = 0x00, /* Unknown reboot cause */ - sys_davic_change = 0x01, /* Reboot due to change in DAVIC - * mode */ - sys_user_reboot = 0x02, /* Reboot initiated by user */ - sys_system_reboot = 0x03, /* Reboot initiated by OS */ - sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */ - sys_silent_reboot = 0x05, /* Silent reboot */ - sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */ - sys_power_up_reboot = 0x07, /* Power on bootup. Older - * drivers may report as - * userReboot. */ - sys_code_change = 0x08, /* Reboot to take code change. - * Older drivers may report as - * userReboot. */ - sys_hardware_reset = 0x09, /* HW watchdog or front-panel - * reset button reset. Older - * drivers may report as - * userReboot. */ - sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */ -}; - -#endif /* _ASM_MACH_POWERTV_ASIC_H */ diff --git a/arch/mips/include/asm/mach-powertv/asic_reg_map.h b/arch/mips/include/asm/mach-powertv/asic_reg_map.h deleted file mode 100644 index 20348e817b0..00000000000 --- a/arch/mips/include/asm/mach-powertv/asic_reg_map.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * asic_reg_map.h - * - * A macro-enclosed list of the elements for the register_map structure for - * use in defining and manipulating the structure. - * - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -REGISTER_MAP_ELEMENT(eic_slow0_strt_add) -REGISTER_MAP_ELEMENT(eic_cfg_bits) -REGISTER_MAP_ELEMENT(eic_ready_status) -REGISTER_MAP_ELEMENT(chipver3) -REGISTER_MAP_ELEMENT(chipver2) -REGISTER_MAP_ELEMENT(chipver1) -REGISTER_MAP_ELEMENT(chipver0) -REGISTER_MAP_ELEMENT(uart1_intstat) -REGISTER_MAP_ELEMENT(uart1_inten) -REGISTER_MAP_ELEMENT(uart1_config1) -REGISTER_MAP_ELEMENT(uart1_config2) -REGISTER_MAP_ELEMENT(uart1_divisorhi) -REGISTER_MAP_ELEMENT(uart1_divisorlo) -REGISTER_MAP_ELEMENT(uart1_data) -REGISTER_MAP_ELEMENT(uart1_status) -REGISTER_MAP_ELEMENT(int_stat_3) -REGISTER_MAP_ELEMENT(int_stat_2) -REGISTER_MAP_ELEMENT(int_stat_1) -REGISTER_MAP_ELEMENT(int_stat_0) -REGISTER_MAP_ELEMENT(int_config) -REGISTER_MAP_ELEMENT(int_int_scan) -REGISTER_MAP_ELEMENT(ien_int_3) -REGISTER_MAP_ELEMENT(ien_int_2) -REGISTER_MAP_ELEMENT(ien_int_1) -REGISTER_MAP_ELEMENT(ien_int_0) -REGISTER_MAP_ELEMENT(int_level_3_3) -REGISTER_MAP_ELEMENT(int_level_3_2) -REGISTER_MAP_ELEMENT(int_level_3_1) -REGISTER_MAP_ELEMENT(int_level_3_0) -REGISTER_MAP_ELEMENT(int_level_2_3) -REGISTER_MAP_ELEMENT(int_level_2_2) -REGISTER_MAP_ELEMENT(int_level_2_1) -REGISTER_MAP_ELEMENT(int_level_2_0) -REGISTER_MAP_ELEMENT(int_level_1_3) -REGISTER_MAP_ELEMENT(int_level_1_2) -REGISTER_MAP_ELEMENT(int_level_1_1) -REGISTER_MAP_ELEMENT(int_level_1_0) -REGISTER_MAP_ELEMENT(int_level_0_3) -REGISTER_MAP_ELEMENT(int_level_0_2) -REGISTER_MAP_ELEMENT(int_level_0_1) -REGISTER_MAP_ELEMENT(int_level_0_0) -REGISTER_MAP_ELEMENT(int_docsis_en) -REGISTER_MAP_ELEMENT(mips_pll_setup) -REGISTER_MAP_ELEMENT(fs432x4b4_usb_ctl) -REGISTER_MAP_ELEMENT(test_bus) -REGISTER_MAP_ELEMENT(crt_spare) -REGISTER_MAP_ELEMENT(usb2_ohci_int_mask) -REGISTER_MAP_ELEMENT(usb2_strap) -REGISTER_MAP_ELEMENT(ehci_hcapbase) -REGISTER_MAP_ELEMENT(ohci_hc_revision) -REGISTER_MAP_ELEMENT(bcm1_bs_lmi_steer) -REGISTER_MAP_ELEMENT(usb2_control) -REGISTER_MAP_ELEMENT(usb2_stbus_obc) -REGISTER_MAP_ELEMENT(usb2_stbus_mess_size) -REGISTER_MAP_ELEMENT(usb2_stbus_chunk_size) -REGISTER_MAP_ELEMENT(pcie_regs) -REGISTER_MAP_ELEMENT(tim_ch) -REGISTER_MAP_ELEMENT(tim_cl) -REGISTER_MAP_ELEMENT(gpio_dout) -REGISTER_MAP_ELEMENT(gpio_din) -REGISTER_MAP_ELEMENT(gpio_dir) -REGISTER_MAP_ELEMENT(watchdog) -REGISTER_MAP_ELEMENT(front_panel) -REGISTER_MAP_ELEMENT(misc_clk_ctl1) -REGISTER_MAP_ELEMENT(misc_clk_ctl2) -REGISTER_MAP_ELEMENT(crt_ext_ctl) -REGISTER_MAP_ELEMENT(register_maps) diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h deleted file mode 100644 index deecb26a077..00000000000 --- a/arch/mips/include/asm/mach-powertv/asic_regs.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __ASM_MACH_POWERTV_ASIC_H_ -#define __ASM_MACH_POWERTV_ASIC_H_ -#include <linux/io.h> - -/* ASIC types */ -enum asic_type { - ASIC_UNKNOWN, - ASIC_ZEUS, - ASIC_CALLIOPE, - ASIC_CRONUS, - ASIC_CRONUSLITE, - ASIC_GAIA, - ASICS /* Number of supported ASICs */ -}; - -/* hardcoded values read from Chip Version registers */ -#define CRONUS_10 0x0B4C1C20 -#define CRONUS_11 0x0B4C1C21 -#define CRONUSLITE_10 0x0B4C1C40 - -#define NAND_FLASH_BASE 0x03000000 -#define CALLIOPE_IO_BASE 0x08000000 -#define GAIA_IO_BASE 0x09000000 -#define CRONUS_IO_BASE 0x09000000 -#define ZEUS_IO_BASE 0x09000000 - -#define ASIC_IO_SIZE 0x01000000 - -/* Definitions for backward compatibility */ -#define UART1_INTSTAT uart1_intstat -#define UART1_INTEN uart1_inten -#define UART1_CONFIG1 uart1_config1 -#define UART1_CONFIG2 uart1_config2 -#define UART1_DIVISORHI uart1_divisorhi -#define UART1_DIVISORLO uart1_divisorlo -#define UART1_DATA uart1_data -#define UART1_STATUS uart1_status - -/* ASIC register enumeration */ -union register_map_entry { - unsigned long phys; - u32 *virt; -}; - -#define REGISTER_MAP_ELEMENT(x) union register_map_entry x; -struct register_map { -#include <asm/mach-powertv/asic_reg_map.h> -}; -#undef REGISTER_MAP_ELEMENT - -/** - * register_map_offset_phys - add an offset to the physical address - * @map: Pointer to the &struct register_map - * @offset: Value to add - * - * Only adds the base to non-zero physical addresses - */ -static inline void register_map_offset_phys(struct register_map *map, - unsigned long offset) -{ -#define REGISTER_MAP_ELEMENT(x) do { \ - if (map->x.phys != 0) \ - map->x.phys += offset; \ - } while (false); - -#include <asm/mach-powertv/asic_reg_map.h> -#undef REGISTER_MAP_ELEMENT -} - -/** - * register_map_virtualize - Convert ®ister_map to virtual addresses - * @map: Pointer to ®ister_map to virtualize - */ -static inline void register_map_virtualize(struct register_map *map) -{ -#define REGISTER_MAP_ELEMENT(x) do { \ - map->x.virt = (!map->x.phys) ? NULL : \ - UNCAC_ADDR(phys_to_virt(map->x.phys)); \ - } while (false); - -#include <asm/mach-powertv/asic_reg_map.h> -#undef REGISTER_MAP_ELEMENT -} - -extern struct register_map _asic_register_map; -extern unsigned long asic_phy_base; - -/* - * Macros to interface to registers through their ioremapped address - * asic_reg_phys_addr Returns the physical address of the given register - * asic_reg_addr Returns the iomapped virtual address of the given - * register. - */ -#define asic_reg_addr(x) (_asic_register_map.x.virt) -#define asic_reg_phys_addr(x) (virt_to_phys((void *) CAC_ADDR( \ - (unsigned long) asic_reg_addr(x)))) - -/* - * The asic_reg macro is gone. It should be replaced by either asic_read or - * asic_write, as appropriate. - */ - -#define asic_read(x) readl(asic_reg_addr(x)) -#define asic_write(v, x) writel(v, asic_reg_addr(x)) - -extern void asic_irq_init(void); -#endif diff --git a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h b/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h deleted file mode 100644 index 58c76ec32a1..00000000000 --- a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2010 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_ -#define _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_ -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_3k_cache 0 -#define cpu_has_4k_cache 1 -#define cpu_has_tx39_cache 0 -#define cpu_has_fpu 0 -#define cpu_has_counter 1 -#define cpu_has_watch 1 -#define cpu_has_divec 1 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_mcheck 1 -#define cpu_has_ejtag 1 -#define cpu_has_llsc 1 -#define cpu_has_mips16 0 -#define cpu_has_mdmx 0 -#define cpu_has_mips3d 0 -#define cpu_has_smartmips 0 -#define cpu_has_vtag_icache 0 -#define cpu_has_dc_aliases 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 1 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 -#define cpu_has_dsp 0 -#define cpu_has_dsp2 0 -#define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 0 -#define cpu_has_64bit_zero_reg 0 -#define cpu_has_vint 1 -#define cpu_has_veic 1 -#define cpu_has_inclusive_pcaches 0 - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 32 -#endif diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h deleted file mode 100644 index 35371641575..00000000000 --- a/arch/mips/include/asm/mach-powertv/dma-coherence.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Version from mach-generic modified to support PowerTV port - * Portions Copyright (C) 2009 Cisco Systems, Inc. - * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> - * - */ - -#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H -#define __ASM_MACH_POWERTV_DMA_COHERENCE_H - -#include <linux/sched.h> -#include <linux/device.h> -#include <asm/mach-powertv/asic.h> - -static inline bool is_kseg2(void *addr) -{ - return (unsigned long)addr >= KSEG2; -} - -static inline unsigned long virt_to_phys_from_pte(void *addr) -{ - pgd_t *pgd; - pud_t *pud; - pmd_t *pmd; - pte_t *ptep, pte; - - unsigned long virt_addr = (unsigned long)addr; - unsigned long phys_addr = 0UL; - - /* get the page global directory. */ - pgd = pgd_offset_k(virt_addr); - - if (!pgd_none(*pgd)) { - /* get the page upper directory */ - pud = pud_offset(pgd, virt_addr); - if (!pud_none(*pud)) { - /* get the page middle directory */ - pmd = pmd_offset(pud, virt_addr); - if (!pmd_none(*pmd)) { - /* get a pointer to the page table entry */ - ptep = pte_offset(pmd, virt_addr); - pte = *ptep; - /* check for a valid page */ - if (pte_present(pte)) { - /* get the physical address the page is - * referring to */ - phys_addr = (unsigned long) - page_to_phys(pte_page(pte)); - /* add the offset within the page */ - phys_addr |= (virt_addr & ~PAGE_MASK); - } - } - } - } - - return phys_addr; -} - -static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, - size_t size) -{ - if (is_kseg2(addr)) - return phys_to_dma(virt_to_phys_from_pte(addr)); - else - return phys_to_dma(virt_to_phys(addr)); -} - -static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, - struct page *page) -{ - return phys_to_dma(page_to_phys(page)); -} - -static inline unsigned long plat_dma_addr_to_phys(struct device *dev, - dma_addr_t dma_addr) -{ - return dma_to_phys(dma_addr); -} - -static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, - size_t size, enum dma_data_direction direction) -{ -} - -static inline int plat_dma_supported(struct device *dev, u64 mask) -{ - /* - * we fall back to GFP_DMA when the mask isn't all 1s, - * so we can't guarantee allocations that must be - * within a tighter range than GFP_DMA.. - */ - if (mask < DMA_BIT_MASK(24)) - return 0; - - return 1; -} - -static inline void plat_extra_sync_for_device(struct device *dev) -{ -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - -static inline int plat_device_is_coherent(struct device *dev) -{ - return 0; -} - -#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */ diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h deleted file mode 100644 index 4fd652ceb52..00000000000 --- a/arch/mips/include/asm/mach-powertv/interrupts.h +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_ -#define _ASM_MACH_POWERTV_INTERRUPTS_H_ - -/* - * Defines for all of the interrupt lines - */ - -/* Definitions for backward compatibility */ -#define kIrq_Uart1 irq_uart1 - -#define ibase 0 - -/*------------- Register: int_stat_3 */ -/* 126 unused (bit 31) */ -#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */ -#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */ -#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */ -#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */ -#define irq_fdma_gp (ibase+122) /* FDMA GP Output */ -#define irq_mips_pic (ibase+121) /* MIPS Performance Counter - * Interrupt */ -#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */ -#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt - * -- Ored by glue logic inside - * SPARC ILC (see - * INT_MEM_PROT_STAT, below, - * for individual interrupts) - */ -/* 118 unused (bit 22) */ -#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by - * glue logic inside SPARC ILC - * (see INT_SBAG_STAT, below, - * for individual interrupts) */ -#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */ -#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */ -/* 114 unused (bit 18) */ -#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt -- - * Ored by glue logic inside - * SPARC ILC (see - * INT_MAILBOX_STAT, below, for - * individual interrupts) */ -#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */ -#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */ -#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse - * Status 3 */ -#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse - * Status 3 */ -#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0 - * Interrupt */ -#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1 - * Interrupt */ -#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE - * Interrupt */ -#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0 - * Interrupt */ -#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1 - * Interrupt */ -#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE - * Interrupt */ -#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */ -#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA - * Interrupt */ -#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */ -#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */ -#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */ -#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */ -#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */ -#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */ -/*------------- Register: int_stat_2 */ -#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */ -#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */ -#define irq_timer2 (ibase+93) /* Programmable Timer - * Interrupt 2 */ -#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */ -#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */ -#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */ -#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */ -#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */ -#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */ -#define irq_sata (ibase+87) /* SATA 1 Interrupt */ -#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */ -#define irq_dtcp (ibase+86) /* DTCP Interrupt */ -#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */ -/* 84 unused (bit 20) */ -/* 83 unused (bit 19) */ -/* 82 unused (bit 18) */ -#define irq_sata2 (ibase+81) /* SATA2 Interrupt */ -#define irq_uart2 (ibase+80) /* UART2 Interrupt */ -#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1 - * Host module) */ -#define irq_pod (ibase+78) /* POD Interrupt */ -#define irq_slave_usb (ibase+77) /* Slave USB */ -#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */ -#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */ -#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */ -#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */ -#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */ -#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */ -#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */ -#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */ -#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */ -/* 67 unused (bit 03) */ -/* 66 unused (bit 02) */ -/* 65 unused (bit 01) */ -/* 64 unused (bit 00) */ -/*------------- Register: int_stat_1 */ -/* 63 unused (bit 31) */ -/* 62 unused (bit 30) */ -/* 61 unused (bit 29) */ -/* 60 unused (bit 28) */ -/* 59 unused (bit 27) */ -/* 58 unused (bit 26) */ -/* 57 unused (bit 25) */ -/* 56 unused (bit 24) */ -#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory - * Interrupt */ -#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit - * Interrupt */ -#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit - * Interrupt */ -#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error - * Interrupt */ -#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive - * Interrupt */ -#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive - * Interrupt */ -#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error - * Interrupt */ -#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play - * Interrupt */ -#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error - * Interrupt */ -#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High - * (Chans 63-32) */ -#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low - * (Chans 31-0) */ -#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High - * (Chans 63-32) */ -#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low - * (Chans 31-0) */ -#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error - * Interrupt */ -#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */ -#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready - * Interrupt */ -#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */ -#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O - * Module */ -#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O - * Module (ABE_intN) */ -#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or - * Discontinuity 1 */ -#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or - * Discontinuity 2 */ -#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect - * (PEI) */ -#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error - * detect */ -#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */ -/*------------- Register: int_stat_0 */ -#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O - * Module */ -#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O - * Module */ -#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha - * (chan 3) Transmission - * Completed OK */ -#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2) - * Transmission Completed OK */ -#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation - * (chan 1) Transmission - * Completed OK */ -#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha - * (chan 3)Transmission - * completed with Errors. */ -#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2) - * Transmission completed with - * Errors. */ -#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation - * (chan 1) Transmission - * completed with Errors */ -#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha - * for N times. Aloha retry - * timeout for channel 3. */ -#define irq_timer1 (ibase+22) /* Programmable Timer - * Interrupt */ -#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */ -#define irq_i2c (ibase+20) /* I2C Module Interrupt */ -#define irq_spi (ibase+19) /* SPI Module Interrupt */ -#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */ -#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or - * Splice Detect Interrupt */ -#define irq_se_micro (ibase+16) /* Secure Micro I/F Module - * Interrupt */ -#define irq_uart1 (ibase+15) /* UART Interrupt */ -#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */ -#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */ -#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */ -#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */ -#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error - * Interrupt */ -/* 9 unused (bit 09) */ -/* 8 unused (bit 08) */ -#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error - * Interrupt */ -#define irq_psilength_err (ibase+6) /* QAM PSI Length Error - * Interrupt */ -#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From - * Forward Path Reference - - * every 3ms when forward Mbits - * and forward slot control - * bytes are updated. */ -#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from - * Reverse Path Reference - - * delayed from forward mark by - * the ranging delay plus a - * fixed amount. When reverse - * Mbits and reverse slot - * control bytes are updated. - * Occurs every 3ms for 3.0M and - * 1.554 M upstream rates and - * every 6 ms for 256K upstream - * rate. */ -#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on - * Channel 1. */ -#define irq_reservation (ibase+2) /* Partial (or Incremental) - * Reservation Message Completed - * or Slotted aloha verify for - * channel 1. */ -#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify - * Interrupt or Reservation - * increment completed for - * channel 3. */ -#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */ -#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */ diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h deleted file mode 100644 index c86ef094ec3..00000000000 --- a/arch/mips/include/asm/mach-powertv/ioremap.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Portions Copyright (C) Cisco Systems, Inc. - */ -#ifndef __ASM_MACH_POWERTV_IOREMAP_H -#define __ASM_MACH_POWERTV_IOREMAP_H - -#include <linux/types.h> -#include <linux/log2.h> -#include <linux/compiler.h> - -#include <asm/pgtable-bits.h> -#include <asm/addrspace.h> - -/* We're going to mess with bits, so get sizes */ -#define IOR_BPC 8 /* Bits per char */ -#define IOR_PHYS_BITS (IOR_BPC * sizeof(phys_addr_t)) -#define IOR_DMA_BITS (IOR_BPC * sizeof(dma_addr_t)) - -/* - * Define the granularity of physical/DMA mapping in terms of the number - * of bits that defines the offset within a grain. These will be the - * least significant bits of the address. The rest of a physical or DMA - * address will be used to index into an appropriate table to find the - * offset to add to the address to yield the corresponding DMA or physical - * address, respectively. - */ -#define IOR_LSBITS 22 /* Bits in a grain */ - -/* - * Compute the number of most significant address bits after removing those - * used for the offset within a grain and then compute the number of table - * entries for the conversion. - */ -#define IOR_PHYS_MSBITS (IOR_PHYS_BITS - IOR_LSBITS) -#define IOR_NUM_PHYS_TO_DMA ((phys_addr_t) 1 << IOR_PHYS_MSBITS) - -#define IOR_DMA_MSBITS (IOR_DMA_BITS - IOR_LSBITS) -#define IOR_NUM_DMA_TO_PHYS ((dma_addr_t) 1 << IOR_DMA_MSBITS) - -/* - * Define data structures used as elements in the arrays for the conversion - * between physical and DMA addresses. We do some slightly fancy math to - * compute the width of the offset element of the conversion tables so - * that we can have the smallest conversion tables. Next, round up the - * sizes to the next higher power of two, i.e. the offset element will have - * 8, 16, 32, 64, etc. bits. This eliminates the need to mask off any - * bits. Finally, we compute a shift value that puts the most significant - * bits of the offset into the most significant bits of the offset element. - * This makes it more efficient on processors without barrel shifters and - * easier to see the values if the conversion table is dumped in binary. - */ -#define _IOR_OFFSET_WIDTH(n) (1 << order_base_2(n)) -#define IOR_OFFSET_WIDTH(n) \ - (_IOR_OFFSET_WIDTH(n) < 8 ? 8 : _IOR_OFFSET_WIDTH(n)) - -#define IOR_PHYS_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_PHYS_MSBITS) -#define IOR_PHYS_SHIFT (IOR_PHYS_BITS - IOR_PHYS_OFFSET_BITS) - -#define IOR_DMA_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_DMA_MSBITS) -#define IOR_DMA_SHIFT (IOR_DMA_BITS - IOR_DMA_OFFSET_BITS) - -struct ior_phys_to_dma { - dma_addr_t offset:IOR_DMA_OFFSET_BITS __packed - __aligned((IOR_DMA_OFFSET_BITS / IOR_BPC)); -}; - -struct ior_dma_to_phys { - dma_addr_t offset:IOR_PHYS_OFFSET_BITS __packed - __aligned((IOR_PHYS_OFFSET_BITS / IOR_BPC)); -}; - -extern struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA]; -extern struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS]; - -static inline dma_addr_t _phys_to_dma_offset_raw(phys_addr_t phys) -{ - return (dma_addr_t)_ior_phys_to_dma[phys >> IOR_LSBITS].offset; -} - -static inline dma_addr_t _dma_to_phys_offset_raw(dma_addr_t dma) -{ - return (dma_addr_t)_ior_dma_to_phys[dma >> IOR_LSBITS].offset; -} - -/* These are not portable and should not be used in drivers. Drivers should - * be using ioremap() and friends to map physical addresses to virtual - * addresses and dma_map*() and friends to map virtual addresses into DMA - * addresses and back. - */ -static inline dma_addr_t phys_to_dma(phys_addr_t phys) -{ - return phys + (_phys_to_dma_offset_raw(phys) << IOR_PHYS_SHIFT); -} - -static inline phys_addr_t dma_to_phys(dma_addr_t dma) -{ - return dma + (_dma_to_phys_offset_raw(dma) << IOR_DMA_SHIFT); -} - -extern void ioremap_add_map(dma_addr_t phys, phys_addr_t alias, - dma_addr_t size); - -/* - * Allow physical addresses to be fixed up to help peripherals located - * outside the low 32-bit range -- generic pass-through version. - */ -static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) -{ - return phys_addr; -} - -/* - * Handle the special case of addresses the area aliased into the first - * 512 MiB of the processor's physical address space. These turn into either - * kseg0 or kseg1 addresses, depending on flags. - */ -static inline void __iomem *plat_ioremap(phys_t start, unsigned long size, - unsigned long flags) -{ - phys_addr_t start_offset; - void __iomem *result = NULL; - - /* Start by checking to see whether this is an aliased address */ - start_offset = _dma_to_phys_offset_raw(start); - - /* - * If: - * o the memory is aliased into the first 512 MiB, and - * o the start and end are in the same RAM bank, and - * o we don't have a zero size or wrap around, and - * o we are supposed to create an uncached mapping, - * handle this is a kseg0 or kseg1 address - */ - if (start_offset != 0) { - phys_addr_t last; - dma_addr_t dma_to_phys_offset; - - last = start + size - 1; - dma_to_phys_offset = - _dma_to_phys_offset_raw(last) << IOR_DMA_SHIFT; - - if (dma_to_phys_offset == start_offset && - size != 0 && start <= last) { - phys_t adjusted_start; - adjusted_start = start + start_offset; - if (flags == _CACHE_UNCACHED) - result = (void __iomem *) (unsigned long) - CKSEG1ADDR(adjusted_start); - else - result = (void __iomem *) (unsigned long) - CKSEG0ADDR(adjusted_start); - } - } - - return result; -} - -static inline int plat_iounmap(const volatile void __iomem *addr) -{ - return 0; -} -#endif /* __ASM_MACH_POWERTV_IOREMAP_H */ diff --git a/arch/mips/include/asm/mach-powertv/irq.h b/arch/mips/include/asm/mach-powertv/irq.h deleted file mode 100644 index 4bd5d0c61a9..00000000000 --- a/arch/mips/include/asm/mach-powertv/irq.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _ASM_MACH_POWERTV_IRQ_H -#define _ASM_MACH_POWERTV_IRQ_H -#include <asm/mach-powertv/interrupts.h> - -#define MIPS_CPU_IRQ_BASE ibase -#define NR_IRQS 127 -#endif diff --git a/arch/mips/include/asm/mach-powertv/powertv-clock.h b/arch/mips/include/asm/mach-powertv/powertv-clock.h deleted file mode 100644 index 6f3e9a0fcf8..00000000000 --- a/arch/mips/include/asm/mach-powertv/powertv-clock.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -/* - * Local definitions for the powertv PCI code - */ - -#ifndef _POWERTV_PCI_POWERTV_PCI_H_ -#define _POWERTV_PCI_POWERTV_PCI_H_ -extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); -extern int asic_pcie_init(void); -extern int asic_pcie_init(void); - -extern int log_level; -#endif diff --git a/arch/mips/include/asm/mach-powertv/war.h b/arch/mips/include/asm/mach-powertv/war.h deleted file mode 100644 index c5651c8e58d..00000000000 --- a/arch/mips/include/asm/mach-powertv/war.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * This version for the PowerTV platform copied from the Malta version. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> - * Portions copyright (C) 2009 Cisco Systems, Inc. - */ -#ifndef __ASM_MACH_POWERTV_WAR_H -#define __ASM_MACH_POWERTV_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 1 -#define MIPS_CACHE_SYNC_WAR 1 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 1 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MACH_POWERTV_WAR_H */ diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h new file mode 100644 index 00000000000..6f9b24f5115 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/mt7620.h @@ -0,0 +1,108 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * Copyright (C) 2013 John Crispin <blogic@openwrt.org> + */ + +#ifndef _MT7620_REGS_H_ +#define _MT7620_REGS_H_ + +#define MT7620_SYSC_BASE 0x10000000 + +#define SYSC_REG_CHIP_NAME0 0x00 +#define SYSC_REG_CHIP_NAME1 0x04 +#define SYSC_REG_CHIP_REV 0x0c +#define SYSC_REG_SYSTEM_CONFIG0 0x10 +#define SYSC_REG_SYSTEM_CONFIG1 0x14 +#define SYSC_REG_CLKCFG0 0x2c +#define SYSC_REG_CPU_SYS_CLKCFG 0x3c +#define SYSC_REG_CPLL_CONFIG0 0x54 +#define SYSC_REG_CPLL_CONFIG1 0x58 + +#define MT7620N_CHIP_NAME0 0x33365452 +#define MT7620N_CHIP_NAME1 0x20203235 + +#define MT7620A_CHIP_NAME0 0x3637544d +#define MT7620A_CHIP_NAME1 0x20203032 + +#define SYSCFG0_XTAL_FREQ_SEL BIT(6) + +#define CHIP_REV_PKG_MASK 0x1 +#define CHIP_REV_PKG_SHIFT 16 +#define CHIP_REV_VER_MASK 0xf +#define CHIP_REV_VER_SHIFT 8 +#define CHIP_REV_ECO_MASK 0xf + +#define CLKCFG0_PERI_CLK_SEL BIT(4) + +#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16 +#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf +#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */ +#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */ +#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */ +#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */ +#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */ +#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */ +#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */ +#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */ +#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */ +#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8 +#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f +#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0 +#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f + +#define CPLL_CFG0_SW_CFG BIT(31) +#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16 +#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7 +#define CPLL_CFG0_LC_CURFCK BIT(15) +#define CPLL_CFG0_BYPASS_REF_CLK BIT(14) +#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10 +#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3 + +#define CPLL_CFG1_CPU_AUX1 BIT(25) +#define CPLL_CFG1_CPU_AUX0 BIT(24) + +#define SYSCFG0_DRAM_TYPE_MASK 0x3 +#define SYSCFG0_DRAM_TYPE_SHIFT 4 +#define SYSCFG0_DRAM_TYPE_SDRAM 0 +#define SYSCFG0_DRAM_TYPE_DDR1 1 +#define SYSCFG0_DRAM_TYPE_DDR2 2 + +#define MT7620_DRAM_BASE 0x0 +#define MT7620_SDRAM_SIZE_MIN 2 +#define MT7620_SDRAM_SIZE_MAX 64 +#define MT7620_DDR1_SIZE_MIN 32 +#define MT7620_DDR1_SIZE_MAX 128 +#define MT7620_DDR2_SIZE_MIN 32 +#define MT7620_DDR2_SIZE_MAX 256 + +#define MT7620_GPIO_MODE_I2C BIT(0) +#define MT7620_GPIO_MODE_UART0_SHIFT 2 +#define MT7620_GPIO_MODE_UART0_MASK 0x7 +#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT) +#define MT7620_GPIO_MODE_UARTF 0x0 +#define MT7620_GPIO_MODE_PCM_UARTF 0x1 +#define MT7620_GPIO_MODE_PCM_I2S 0x2 +#define MT7620_GPIO_MODE_I2S_UARTF 0x3 +#define MT7620_GPIO_MODE_PCM_GPIO 0x4 +#define MT7620_GPIO_MODE_GPIO_UARTF 0x5 +#define MT7620_GPIO_MODE_GPIO_I2S 0x6 +#define MT7620_GPIO_MODE_GPIO 0x7 +#define MT7620_GPIO_MODE_UART1 BIT(5) +#define MT7620_GPIO_MODE_MDIO BIT(8) +#define MT7620_GPIO_MODE_RGMII1 BIT(9) +#define MT7620_GPIO_MODE_RGMII2 BIT(10) +#define MT7620_GPIO_MODE_SPI BIT(11) +#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12) +#define MT7620_GPIO_MODE_WLED BIT(13) +#define MT7620_GPIO_MODE_JTAG BIT(15) +#define MT7620_GPIO_MODE_EPHY BIT(15) +#define MT7620_GPIO_MODE_WDT BIT(22) + +#endif diff --git a/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h new file mode 100644 index 00000000000..f7bb8cfc5eb --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h @@ -0,0 +1,57 @@ +/* + * Ralink MT7620 specific CPU feature overrides + * + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef _MT7620_CPU_FEATURE_OVERRIDES_H +#define _MT7620_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 1 +#define cpu_has_dsp2 0 +#define cpu_has_mipsmt 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* _MT7620_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h new file mode 100644 index 00000000000..5a508f9f943 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h @@ -0,0 +1,39 @@ +/* + * Ralink SoC register definitions + * + * Copyright (C) 2013 John Crispin <blogic@openwrt.org> + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RALINK_REGS_H_ +#define _RALINK_REGS_H_ + +extern __iomem void *rt_sysc_membase; +extern __iomem void *rt_memc_membase; + +static inline void rt_sysc_w32(u32 val, unsigned reg) +{ + __raw_writel(val, rt_sysc_membase + reg); +} + +static inline u32 rt_sysc_r32(unsigned reg) +{ + return __raw_readl(rt_sysc_membase + reg); +} + +static inline void rt_memc_w32(u32 val, unsigned reg) +{ + __raw_writel(val, rt_memc_membase + reg); +} + +static inline u32 rt_memc_r32(unsigned reg) +{ + return __raw_readl(rt_memc_membase + reg); +} + +#endif /* _RALINK_REGS_H_ */ diff --git a/arch/mips/include/asm/mach-ralink/rt288x.h b/arch/mips/include/asm/mach-ralink/rt288x.h new file mode 100644 index 00000000000..03ad716acb4 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/rt288x.h @@ -0,0 +1,53 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * Copyright (C) 2013 John Crispin <blogic@openwrt.org> + */ + +#ifndef _RT288X_REGS_H_ +#define _RT288X_REGS_H_ + +#define RT2880_SYSC_BASE 0x00300000 + +#define SYSC_REG_CHIP_NAME0 0x00 +#define SYSC_REG_CHIP_NAME1 0x04 +#define SYSC_REG_CHIP_ID 0x0c +#define SYSC_REG_SYSTEM_CONFIG 0x10 +#define SYSC_REG_CLKCFG 0x30 + +#define RT2880_CHIP_NAME0 0x38325452 +#define RT2880_CHIP_NAME1 0x20203038 + +#define CHIP_ID_ID_MASK 0xff +#define CHIP_ID_ID_SHIFT 8 +#define CHIP_ID_REV_MASK 0xff + +#define SYSTEM_CONFIG_CPUCLK_SHIFT 20 +#define SYSTEM_CONFIG_CPUCLK_MASK 0x3 +#define SYSTEM_CONFIG_CPUCLK_250 0x0 +#define SYSTEM_CONFIG_CPUCLK_266 0x1 +#define SYSTEM_CONFIG_CPUCLK_280 0x2 +#define SYSTEM_CONFIG_CPUCLK_300 0x3 + +#define RT2880_GPIO_MODE_I2C BIT(0) +#define RT2880_GPIO_MODE_UART0 BIT(1) +#define RT2880_GPIO_MODE_SPI BIT(2) +#define RT2880_GPIO_MODE_UART1 BIT(3) +#define RT2880_GPIO_MODE_JTAG BIT(4) +#define RT2880_GPIO_MODE_MDIO BIT(5) +#define RT2880_GPIO_MODE_SDRAM BIT(6) +#define RT2880_GPIO_MODE_PCI BIT(7) + +#define CLKCFG_SRAM_CS_N_WDT BIT(9) + +#define RT2880_SDRAM_BASE 0x08000000 +#define RT2880_MEM_SIZE_MIN 2 +#define RT2880_MEM_SIZE_MAX 128 + +#endif diff --git a/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h new file mode 100644 index 00000000000..72fc1066919 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h @@ -0,0 +1,56 @@ +/* + * Ralink RT288x specific CPU feature overrides + * + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef _RT288X_CPU_FEATURE_OVERRIDES_H +#define _RT288X_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 16 +#define cpu_icache_line_size() 16 + +#endif /* _RT288X_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h new file mode 100644 index 00000000000..069bf37a601 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/rt305x.h @@ -0,0 +1,166 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * Copyright (C) 2013 John Crispin <blogic@openwrt.org> + */ + +#ifndef _RT305X_REGS_H_ +#define _RT305X_REGS_H_ + +enum rt305x_soc_type { + RT305X_SOC_UNKNOWN = 0, + RT305X_SOC_RT3050, + RT305X_SOC_RT3052, + RT305X_SOC_RT3350, + RT305X_SOC_RT3352, + RT305X_SOC_RT5350, +}; + +extern enum rt305x_soc_type rt305x_soc; + +static inline int soc_is_rt3050(void) +{ + return rt305x_soc == RT305X_SOC_RT3050; +} + +static inline int soc_is_rt3052(void) +{ + return rt305x_soc == RT305X_SOC_RT3052; +} + +static inline int soc_is_rt305x(void) +{ + return soc_is_rt3050() || soc_is_rt3052(); +} + +static inline int soc_is_rt3350(void) +{ + return rt305x_soc == RT305X_SOC_RT3350; +} + +static inline int soc_is_rt3352(void) +{ + return rt305x_soc == RT305X_SOC_RT3352; +} + +static inline int soc_is_rt5350(void) +{ + return rt305x_soc == RT305X_SOC_RT5350; +} + +#define RT305X_SYSC_BASE 0x10000000 + +#define SYSC_REG_CHIP_NAME0 0x00 +#define SYSC_REG_CHIP_NAME1 0x04 +#define SYSC_REG_CHIP_ID 0x0c +#define SYSC_REG_SYSTEM_CONFIG 0x10 + +#define RT3052_CHIP_NAME0 0x30335452 +#define RT3052_CHIP_NAME1 0x20203235 + +#define RT3350_CHIP_NAME0 0x33335452 +#define RT3350_CHIP_NAME1 0x20203035 + +#define RT3352_CHIP_NAME0 0x33335452 +#define RT3352_CHIP_NAME1 0x20203235 + +#define RT5350_CHIP_NAME0 0x33355452 +#define RT5350_CHIP_NAME1 0x20203035 + +#define CHIP_ID_ID_MASK 0xff +#define CHIP_ID_ID_SHIFT 8 +#define CHIP_ID_REV_MASK 0xff + +#define RT305X_SYSCFG_CPUCLK_SHIFT 18 +#define RT305X_SYSCFG_CPUCLK_MASK 0x1 +#define RT305X_SYSCFG_CPUCLK_LOW 0x0 +#define RT305X_SYSCFG_CPUCLK_HIGH 0x1 + +#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2 +#define RT305X_SYSCFG_CPUCLK_MASK 0x1 +#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1 + +#define RT3352_SYSCFG0_CPUCLK_SHIFT 8 +#define RT3352_SYSCFG0_CPUCLK_MASK 0x1 +#define RT3352_SYSCFG0_CPUCLK_LOW 0x0 +#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 + +#define RT5350_SYSCFG0_CPUCLK_SHIFT 8 +#define RT5350_SYSCFG0_CPUCLK_MASK 0x3 +#define RT5350_SYSCFG0_CPUCLK_360 0x0 +#define RT5350_SYSCFG0_CPUCLK_320 0x2 +#define RT5350_SYSCFG0_CPUCLK_300 0x3 + +#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12 +#define RT5350_SYSCFG0_DRAM_SIZE_MASK 7 +#define RT5350_SYSCFG0_DRAM_SIZE_2M 0 +#define RT5350_SYSCFG0_DRAM_SIZE_8M 1 +#define RT5350_SYSCFG0_DRAM_SIZE_16M 2 +#define RT5350_SYSCFG0_DRAM_SIZE_32M 3 +#define RT5350_SYSCFG0_DRAM_SIZE_64M 4 + +/* multi function gpio pins */ +#define RT305X_GPIO_I2C_SD 1 +#define RT305X_GPIO_I2C_SCLK 2 +#define RT305X_GPIO_SPI_EN 3 +#define RT305X_GPIO_SPI_CLK 4 +/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */ +#define RT305X_GPIO_7 7 +#define RT305X_GPIO_10 10 +#define RT305X_GPIO_14 14 +#define RT305X_GPIO_UART1_TXD 15 +#define RT305X_GPIO_UART1_RXD 16 +#define RT305X_GPIO_JTAG_TDO 17 +#define RT305X_GPIO_JTAG_TDI 18 +#define RT305X_GPIO_MDIO_MDC 22 +#define RT305X_GPIO_MDIO_MDIO 23 +#define RT305X_GPIO_SDRAM_MD16 24 +#define RT305X_GPIO_SDRAM_MD31 39 +#define RT305X_GPIO_GE0_TXD0 40 +#define RT305X_GPIO_GE0_RXCLK 51 + +#define RT305X_GPIO_MODE_I2C BIT(0) +#define RT305X_GPIO_MODE_SPI BIT(1) +#define RT305X_GPIO_MODE_UART0_SHIFT 2 +#define RT305X_GPIO_MODE_UART0_MASK 0x7 +#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT) +#define RT305X_GPIO_MODE_UARTF 0x0 +#define RT305X_GPIO_MODE_PCM_UARTF 0x1 +#define RT305X_GPIO_MODE_PCM_I2S 0x2 +#define RT305X_GPIO_MODE_I2S_UARTF 0x3 +#define RT305X_GPIO_MODE_PCM_GPIO 0x4 +#define RT305X_GPIO_MODE_GPIO_UARTF 0x5 +#define RT305X_GPIO_MODE_GPIO_I2S 0x6 +#define RT305X_GPIO_MODE_GPIO 0x7 +#define RT305X_GPIO_MODE_UART1 BIT(5) +#define RT305X_GPIO_MODE_JTAG BIT(6) +#define RT305X_GPIO_MODE_MDIO BIT(7) +#define RT305X_GPIO_MODE_SDRAM BIT(8) +#define RT305X_GPIO_MODE_RGMII BIT(9) + +#define RT3352_SYSC_REG_SYSCFG0 0x010 +#define RT3352_SYSC_REG_SYSCFG1 0x014 +#define RT3352_SYSC_REG_CLKCFG1 0x030 +#define RT3352_SYSC_REG_RSTCTRL 0x034 +#define RT3352_SYSC_REG_USB_PS 0x05c + +#define RT3352_CLKCFG0_XTAL_SEL BIT(20) +#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18) +#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20) +#define RT3352_RSTCTRL_UHST BIT(22) +#define RT3352_RSTCTRL_UDEV BIT(25) +#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10) + +#define RT305X_SDRAM_BASE 0x00000000 +#define RT305X_MEM_SIZE_MIN 2 +#define RT305X_MEM_SIZE_MAX 64 +#define RT3352_MEM_SIZE_MIN 2 +#define RT3352_MEM_SIZE_MAX 256 + +#endif diff --git a/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h new file mode 100644 index 00000000000..917c2865455 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h @@ -0,0 +1,56 @@ +/* + * Ralink RT305x specific CPU feature overrides + * + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef _RT305X_CPU_FEATURE_OVERRIDES_H +#define _RT305X_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 1 +#define cpu_has_mipsmt 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* _RT305X_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h new file mode 100644 index 00000000000..058382f37f9 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/rt3883.h @@ -0,0 +1,252 @@ +/* + * Ralink RT3662/RT3883 SoC register definitions + * + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT3883_REGS_H_ +#define _RT3883_REGS_H_ + +#include <linux/bitops.h> + +#define RT3883_SDRAM_BASE 0x00000000 +#define RT3883_SYSC_BASE 0x10000000 +#define RT3883_TIMER_BASE 0x10000100 +#define RT3883_INTC_BASE 0x10000200 +#define RT3883_MEMC_BASE 0x10000300 +#define RT3883_UART0_BASE 0x10000500 +#define RT3883_PIO_BASE 0x10000600 +#define RT3883_FSCC_BASE 0x10000700 +#define RT3883_NANDC_BASE 0x10000810 +#define RT3883_I2C_BASE 0x10000900 +#define RT3883_I2S_BASE 0x10000a00 +#define RT3883_SPI_BASE 0x10000b00 +#define RT3883_UART1_BASE 0x10000c00 +#define RT3883_PCM_BASE 0x10002000 +#define RT3883_GDMA_BASE 0x10002800 +#define RT3883_CODEC1_BASE 0x10003000 +#define RT3883_CODEC2_BASE 0x10003800 +#define RT3883_FE_BASE 0x10100000 +#define RT3883_ROM_BASE 0x10118000 +#define RT3883_USBDEV_BASE 0x10112000 +#define RT3883_PCI_BASE 0x10140000 +#define RT3883_WLAN_BASE 0x10180000 +#define RT3883_USBHOST_BASE 0x101c0000 +#define RT3883_BOOT_BASE 0x1c000000 +#define RT3883_SRAM_BASE 0x1e000000 +#define RT3883_PCIMEM_BASE 0x20000000 + +#define RT3883_EHCI_BASE (RT3883_USBHOST_BASE) +#define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000) + +#define RT3883_SYSC_SIZE 0x100 +#define RT3883_TIMER_SIZE 0x100 +#define RT3883_INTC_SIZE 0x100 +#define RT3883_MEMC_SIZE 0x100 +#define RT3883_UART0_SIZE 0x100 +#define RT3883_UART1_SIZE 0x100 +#define RT3883_PIO_SIZE 0x100 +#define RT3883_FSCC_SIZE 0x100 +#define RT3883_NANDC_SIZE 0x0f0 +#define RT3883_I2C_SIZE 0x100 +#define RT3883_I2S_SIZE 0x100 +#define RT3883_SPI_SIZE 0x100 +#define RT3883_PCM_SIZE 0x800 +#define RT3883_GDMA_SIZE 0x800 +#define RT3883_CODEC1_SIZE 0x800 +#define RT3883_CODEC2_SIZE 0x800 +#define RT3883_FE_SIZE 0x10000 +#define RT3883_ROM_SIZE 0x4000 +#define RT3883_USBDEV_SIZE 0x4000 +#define RT3883_PCI_SIZE 0x40000 +#define RT3883_WLAN_SIZE 0x40000 +#define RT3883_USBHOST_SIZE 0x40000 +#define RT3883_BOOT_SIZE (32 * 1024 * 1024) +#define RT3883_SRAM_SIZE (32 * 1024 * 1024) + +/* SYSC registers */ +#define RT3883_SYSC_REG_CHIPID0_3 0x00 /* Chip ID 0 */ +#define RT3883_SYSC_REG_CHIPID4_7 0x04 /* Chip ID 1 */ +#define RT3883_SYSC_REG_REVID 0x0c /* Chip Revision Identification */ +#define RT3883_SYSC_REG_SYSCFG0 0x10 /* System Configuration 0 */ +#define RT3883_SYSC_REG_SYSCFG1 0x14 /* System Configuration 1 */ +#define RT3883_SYSC_REG_CLKCFG0 0x2c /* Clock Configuration 0 */ +#define RT3883_SYSC_REG_CLKCFG1 0x30 /* Clock Configuration 1 */ +#define RT3883_SYSC_REG_RSTCTRL 0x34 /* Reset Control*/ +#define RT3883_SYSC_REG_RSTSTAT 0x38 /* Reset Status*/ +#define RT3883_SYSC_REG_USB_PS 0x5c /* USB Power saving control */ +#define RT3883_SYSC_REG_GPIO_MODE 0x60 /* GPIO Purpose Select */ +#define RT3883_SYSC_REG_PCIE_CLK_GEN0 0x7c +#define RT3883_SYSC_REG_PCIE_CLK_GEN1 0x80 +#define RT3883_SYSC_REG_PCIE_CLK_GEN2 0x84 +#define RT3883_SYSC_REG_PMU 0x88 +#define RT3883_SYSC_REG_PMU1 0x8c + +#define RT3883_CHIP_NAME0 0x38335452 +#define RT3883_CHIP_NAME1 0x20203338 + +#define RT3883_REVID_VER_ID_MASK 0x0f +#define RT3883_REVID_VER_ID_SHIFT 8 +#define RT3883_REVID_ECO_ID_MASK 0x0f + +#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17) +#define RT3883_SYSCFG0_CPUCLK_SHIFT 8 +#define RT3883_SYSCFG0_CPUCLK_MASK 0x3 +#define RT3883_SYSCFG0_CPUCLK_250 0x0 +#define RT3883_SYSCFG0_CPUCLK_384 0x1 +#define RT3883_SYSCFG0_CPUCLK_480 0x2 +#define RT3883_SYSCFG0_CPUCLK_500 0x3 + +#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10) +#define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8) +#define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7) +#define RT3883_SYSCFG1_PCI_66M_MODE BIT(6) +#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2) + +#define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21) +#define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20) +#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19) +#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18) + +#define RT3883_GPIO_MODE_I2C BIT(0) +#define RT3883_GPIO_MODE_SPI BIT(1) +#define RT3883_GPIO_MODE_UART0_SHIFT 2 +#define RT3883_GPIO_MODE_UART0_MASK 0x7 +#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT) +#define RT3883_GPIO_MODE_UARTF 0x0 +#define RT3883_GPIO_MODE_PCM_UARTF 0x1 +#define RT3883_GPIO_MODE_PCM_I2S 0x2 +#define RT3883_GPIO_MODE_I2S_UARTF 0x3 +#define RT3883_GPIO_MODE_PCM_GPIO 0x4 +#define RT3883_GPIO_MODE_GPIO_UARTF 0x5 +#define RT3883_GPIO_MODE_GPIO_I2S 0x6 +#define RT3883_GPIO_MODE_GPIO 0x7 +#define RT3883_GPIO_MODE_UART1 BIT(5) +#define RT3883_GPIO_MODE_JTAG BIT(6) +#define RT3883_GPIO_MODE_MDIO BIT(7) +#define RT3883_GPIO_MODE_GE1 BIT(9) +#define RT3883_GPIO_MODE_GE2 BIT(10) +#define RT3883_GPIO_MODE_PCI_SHIFT 11 +#define RT3883_GPIO_MODE_PCI_MASK 0x7 +#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT) +#define RT3883_GPIO_MODE_LNA_A_SHIFT 16 +#define RT3883_GPIO_MODE_LNA_A_MASK 0x3 +#define _RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT) +#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3 +#define RT3883_GPIO_MODE_LNA_A _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK) +#define RT3883_GPIO_MODE_LNA_G_SHIFT 18 +#define RT3883_GPIO_MODE_LNA_G_MASK 0x3 +#define _RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT) +#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3 +#define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK) + +#define RT3883_GPIO_I2C_SD 1 +#define RT3883_GPIO_I2C_SCLK 2 +#define RT3883_GPIO_SPI_CS0 3 +#define RT3883_GPIO_SPI_CLK 4 +#define RT3883_GPIO_SPI_MOSI 5 +#define RT3883_GPIO_SPI_MISO 6 +#define RT3883_GPIO_7 7 +#define RT3883_GPIO_10 10 +#define RT3883_GPIO_11 11 +#define RT3883_GPIO_14 14 +#define RT3883_GPIO_UART1_TXD 15 +#define RT3883_GPIO_UART1_RXD 16 +#define RT3883_GPIO_JTAG_TDO 17 +#define RT3883_GPIO_JTAG_TDI 18 +#define RT3883_GPIO_JTAG_TMS 19 +#define RT3883_GPIO_JTAG_TCLK 20 +#define RT3883_GPIO_JTAG_TRST_N 21 +#define RT3883_GPIO_MDIO_MDC 22 +#define RT3883_GPIO_MDIO_MDIO 23 +#define RT3883_GPIO_LNA_PE_A0 32 +#define RT3883_GPIO_LNA_PE_A1 33 +#define RT3883_GPIO_LNA_PE_A2 34 +#define RT3883_GPIO_LNA_PE_G0 35 +#define RT3883_GPIO_LNA_PE_G1 36 +#define RT3883_GPIO_LNA_PE_G2 37 +#define RT3883_GPIO_PCI_AD0 40 +#define RT3883_GPIO_PCI_AD31 71 +#define RT3883_GPIO_GE2_TXD0 72 +#define RT3883_GPIO_GE2_TXD1 73 +#define RT3883_GPIO_GE2_TXD2 74 +#define RT3883_GPIO_GE2_TXD3 75 +#define RT3883_GPIO_GE2_TXEN 76 +#define RT3883_GPIO_GE2_TXCLK 77 +#define RT3883_GPIO_GE2_RXD0 78 +#define RT3883_GPIO_GE2_RXD1 79 +#define RT3883_GPIO_GE2_RXD2 80 +#define RT3883_GPIO_GE2_RXD3 81 +#define RT3883_GPIO_GE2_RXDV 82 +#define RT3883_GPIO_GE2_RXCLK 83 +#define RT3883_GPIO_GE1_TXD0 84 +#define RT3883_GPIO_GE1_TXD1 85 +#define RT3883_GPIO_GE1_TXD2 86 +#define RT3883_GPIO_GE1_TXD3 87 +#define RT3883_GPIO_GE1_TXEN 88 +#define RT3883_GPIO_GE1_TXCLK 89 +#define RT3883_GPIO_GE1_RXD0 90 +#define RT3883_GPIO_GE1_RXD1 91 +#define RT3883_GPIO_GE1_RXD2 92 +#define RT3883_GPIO_GE1_RXD3 93 +#define RT3883_GPIO_GE1_RXDV 94 +#define RT3883_GPIO_GE1_RXCLK 95 + +#define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27) +#define RT3883_RSTCTRL_FLASH BIT(26) +#define RT3883_RSTCTRL_UDEV BIT(25) +#define RT3883_RSTCTRL_PCI BIT(24) +#define RT3883_RSTCTRL_PCIE BIT(23) +#define RT3883_RSTCTRL_UHST BIT(22) +#define RT3883_RSTCTRL_FE BIT(21) +#define RT3883_RSTCTRL_WLAN BIT(20) +#define RT3883_RSTCTRL_UART1 BIT(29) +#define RT3883_RSTCTRL_SPI BIT(18) +#define RT3883_RSTCTRL_I2S BIT(17) +#define RT3883_RSTCTRL_I2C BIT(16) +#define RT3883_RSTCTRL_NAND BIT(15) +#define RT3883_RSTCTRL_DMA BIT(14) +#define RT3883_RSTCTRL_PIO BIT(13) +#define RT3883_RSTCTRL_UART BIT(12) +#define RT3883_RSTCTRL_PCM BIT(11) +#define RT3883_RSTCTRL_MC BIT(10) +#define RT3883_RSTCTRL_INTC BIT(9) +#define RT3883_RSTCTRL_TIMER BIT(8) +#define RT3883_RSTCTRL_SYS BIT(0) + +#define RT3883_INTC_INT_SYSCTL BIT(0) +#define RT3883_INTC_INT_TIMER0 BIT(1) +#define RT3883_INTC_INT_TIMER1 BIT(2) +#define RT3883_INTC_INT_IA BIT(3) +#define RT3883_INTC_INT_PCM BIT(4) +#define RT3883_INTC_INT_UART0 BIT(5) +#define RT3883_INTC_INT_PIO BIT(6) +#define RT3883_INTC_INT_DMA BIT(7) +#define RT3883_INTC_INT_NAND BIT(8) +#define RT3883_INTC_INT_PERFC BIT(9) +#define RT3883_INTC_INT_I2S BIT(10) +#define RT3883_INTC_INT_UART1 BIT(12) +#define RT3883_INTC_INT_UHST BIT(18) +#define RT3883_INTC_INT_UDEV BIT(19) + +/* FLASH/SRAM/Codec Controller registers */ +#define RT3883_FSCC_REG_FLASH_CFG0 0x00 +#define RT3883_FSCC_REG_FLASH_CFG1 0x04 +#define RT3883_FSCC_REG_CODEC_CFG0 0x40 +#define RT3883_FSCC_REG_CODEC_CFG1 0x44 + +#define RT3883_FLASH_CFG_WIDTH_SHIFT 26 +#define RT3883_FLASH_CFG_WIDTH_MASK 0x3 +#define RT3883_FLASH_CFG_WIDTH_8BIT 0x0 +#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1 +#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2 + +#define RT3883_SDRAM_BASE 0x00000000 +#define RT3883_MEM_SIZE_MIN 2 +#define RT3883_MEM_SIZE_MAX 256 + +#endif /* _RT3883_REGS_H_ */ diff --git a/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h new file mode 100644 index 00000000000..181fbf4c976 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h @@ -0,0 +1,55 @@ +/* + * Ralink RT3662/RT3883 specific CPU feature overrides + * + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org> + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef _RT3883_CPU_FEATURE_OVERRIDES_H +#define _RT3883_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 1 +#define cpu_has_mipsmt 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* _RT3883_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-pnx8550/war.h b/arch/mips/include/asm/mach-ralink/war.h index de8894c4668..c074b5dc1f8 100644 --- a/arch/mips/include/asm/mach-pnx8550/war.h +++ b/arch/mips/include/asm/mach-ralink/war.h @@ -5,8 +5,8 @@ * * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> */ -#ifndef __ASM_MIPS_MACH_PNX8550_WAR_H -#define __ASM_MIPS_MACH_PNX8550_WAR_H +#ifndef __ASM_MACH_RALINK_WAR_H +#define __ASM_MACH_RALINK_WAR_H #define R4600_V1_INDEX_ICACHEOP_WAR 0 #define R4600_V1_HIT_CACHEOP_WAR 0 @@ -21,4 +21,4 @@ #define R10000_LLSC_WAR 0 #define MIPS34K_MISSED_ITLB_WAR 0 -#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */ +#endif /* __ASM_MACH_RALINK_WAR_H */ diff --git a/arch/mips/include/asm/mach-rc32434/ddr.h b/arch/mips/include/asm/mach-rc32434/ddr.h index 291e2cf9dde..e1cad0c7fd5 100644 --- a/arch/mips/include/asm/mach-rc32434/ddr.h +++ b/arch/mips/include/asm/mach-rc32434/ddr.h @@ -138,4 +138,4 @@ struct ddr_ram { #define RC32434_DLLED_DBE_BIT 0 #define RC32434_DLLED_DTE_BIT 1 -#endif /* _ASM_RC32434_DDR_H_ */ +#endif /* _ASM_RC32434_DDR_H_ */ diff --git a/arch/mips/include/asm/mach-rc32434/dma.h b/arch/mips/include/asm/mach-rc32434/dma.h index 5f898b5873f..4322191e46b 100644 --- a/arch/mips/include/asm/mach-rc32434/dma.h +++ b/arch/mips/include/asm/mach-rc32434/dma.h @@ -5,7 +5,7 @@ * DMA register definition. * * Author : ryan.holmQVist@idt.com - * Date : 20011005 + * Date : 20011005 */ #ifndef __ASM_RC32434_DMA_H @@ -71,10 +71,10 @@ struct dma_reg { #define DMA_CHAN_DONE_BIT (1 << 1) #define DMA_CHAN_MODE_BIT (1 << 2) #define DMA_CHAN_MODE_MSK 0x0000000c -#define DMA_CHAN_MODE_AUTO 0 -#define DMA_CHAN_MODE_BURST 1 -#define DMA_CHAN_MODE_XFRT 2 -#define DMA_CHAN_MODE_RSVD 3 +#define DMA_CHAN_MODE_AUTO 0 +#define DMA_CHAN_MODE_BURST 1 +#define DMA_CHAN_MODE_XFRT 2 +#define DMA_CHAN_MODE_RSVD 3 #define DMA_CHAN_ACT_BIT (1 << 4) /* DMA status registers */ @@ -100,4 +100,4 @@ struct dma_channel { struct dma_reg ch[DMA_CHAN_COUNT]; }; -#endif /* __ASM_RC32434_DMA_H */ +#endif /* __ASM_RC32434_DMA_H */ diff --git a/arch/mips/include/asm/mach-rc32434/dma_v.h b/arch/mips/include/asm/mach-rc32434/dma_v.h index 173a9f9146c..28c54063a34 100644 --- a/arch/mips/include/asm/mach-rc32434/dma_v.h +++ b/arch/mips/include/asm/mach-rc32434/dma_v.h @@ -5,7 +5,7 @@ * DMA register definition. * * Author : ryan.holmQVist@idt.com - * Date : 20011005 + * Date : 20011005 */ #ifndef _ASM_RC32434_DMA_V_H_ @@ -49,4 +49,4 @@ static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr) __raw_writel(dma_addr, &ch->dmandptr); } -#endif /* _ASM_RC32434_DMA_V_H_ */ +#endif /* _ASM_RC32434_DMA_V_H_ */ diff --git a/arch/mips/include/asm/mach-rc32434/eth.h b/arch/mips/include/asm/mach-rc32434/eth.h index a25cbc56173..c2645faadf5 100644 --- a/arch/mips/include/asm/mach-rc32434/eth.h +++ b/arch/mips/include/asm/mach-rc32434/eth.h @@ -26,8 +26,8 @@ * */ -#ifndef __ASM_RC32434_ETH_H -#define __ASM_RC32434_ETH_H +#ifndef __ASM_RC32434_ETH_H +#define __ASM_RC32434_ETH_H #define ETH0_BASE_ADDR 0x18060000 @@ -217,4 +217,4 @@ struct eth_regs { #define ETH_TX_LE (1 << 16) #define ETH_TX_CC 0x001E0000 -#endif /* __ASM_RC32434_ETH_H */ +#endif /* __ASM_RC32434_ETH_H */ diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h index 12ee8d51016..4dee0a34250 100644 --- a/arch/mips/include/asm/mach-rc32434/gpio.h +++ b/arch/mips/include/asm/mach-rc32434/gpio.h @@ -5,7 +5,7 @@ * GPIO register definition. * * Author : ryan.holmQVist@idt.com - * Date : 20011005 + * Date : 20011005 * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com> * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org> */ @@ -26,9 +26,9 @@ #define irq_to_gpio(irq) (irq - (8 + 4 * 32)) struct rb532_gpio_reg { - u32 gpiofunc; /* GPIO Function Register + u32 gpiofunc; /* GPIO Function Register * gpiofunc[x]==0 bit = gpio - * func[x]==1 bit = altfunc + * func[x]==1 bit = altfunc */ u32 gpiocfg; /* GPIO Configuration Register * gpiocfg[x]==0 bit = input diff --git a/arch/mips/include/asm/mach-rc32434/irq.h b/arch/mips/include/asm/mach-rc32434/irq.h index 023a5b100ed..b76dec95c04 100644 --- a/arch/mips/include/asm/mach-rc32434/irq.h +++ b/arch/mips/include/asm/mach-rc32434/irq.h @@ -1,7 +1,7 @@ #ifndef __ASM_RC32434_IRQ_H #define __ASM_RC32434_IRQ_H -#define NR_IRQS 256 +#define NR_IRQS 256 #include <asm/mach-generic/irq.h> #include <asm/mach-rc32434/rb.h> @@ -25,12 +25,12 @@ #define UART0_IRQ (GROUP3_IRQ_BASE + 0) -#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0) -#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1) -#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9) -#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10) +#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0) +#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1) +#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9) +#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10) #define GPIO_MAPPED_IRQ_BASE GROUP4_IRQ_BASE #define GPIO_MAPPED_IRQ_GROUP 4 -#endif /* __ASM_RC32434_IRQ_H */ +#endif /* __ASM_RC32434_IRQ_H */ diff --git a/arch/mips/include/asm/mach-rc32434/pci.h b/arch/mips/include/asm/mach-rc32434/pci.h index 410638f2af7..6f40d151558 100644 --- a/arch/mips/include/asm/mach-rc32434/pci.h +++ b/arch/mips/include/asm/mach-rc32434/pci.h @@ -151,11 +151,11 @@ struct pci_msu { #define PCI_CFGA_REG_PBA2 (0x18 >> 2) /* use PCIPBA_ */ #define PCI_CFGA_REG_PBA3 (0x1c >> 2) /* use PCIPBA_ */ #define PCI_CFGA_REG_SUBSYS (0x2c >> 2) /* use PCFGSS_ */ -#define PCI_CFGA_REG_3C (0x3C >> 2) /* use PCFG3C_ */ +#define PCI_CFGA_REG_3C (0x3C >> 2) /* use PCFG3C_ */ #define PCI_CFGA_REG_PBBA0C (0x44 >> 2) /* use PCIPBAC_ */ -#define PCI_CFGA_REG_PBA0M (0x48 >> 2) +#define PCI_CFGA_REG_PBA0M (0x48 >> 2) #define PCI_CFGA_REG_PBA1C (0x4c >> 2) /* use PCIPBAC_ */ -#define PCI_CFGA_REG_PBA1M (0x50 >> 2) +#define PCI_CFGA_REG_PBA1M (0x50 >> 2) #define PCI_CFGA_REG_PBA2C (0x54 >> 2) /* use PCIPBAC_ */ #define PCI_CFGA_REG_PBA2M (0x58 >> 2) #define PCI_CFGA_REG_PBA3C (0x5c >> 2) /* use PCIPBAC_ */ @@ -164,9 +164,9 @@ struct pci_msu { #define PCI_CFGA_FUNC_BIT 8 #define PCI_CFGA_FUNC 0x00000700 #define PCI_CFGA_DEV_BIT 11 -#define PCI_CFGA_DEV 0x0000f800 -#define PCI_CFGA_DEV_INTERN 0 -#define PCI_CFGA_BUS_BIT 16 +#define PCI_CFGA_DEV 0x0000f800 +#define PCI_CFGA_DEV_INTERN 0 +#define PCI_CFGA_BUS_BIT 16 #define PCI CFGA_BUS 0x00ff0000 #define PCI_CFGA_BUS_TYPE0 0 #define PCI_CFGA_EN (1 << 31) @@ -201,13 +201,13 @@ struct pci_msu { #define PCI_PBAC_P (1 << 1) #define PCI_PBAC_SIZE_BIT 2 #define PCI_PBAC_SIZE 0x0000007c -#define PCI_PBAC_SB (1 << 7) -#define PCI_PBAC_PP (1 << 8) +#define PCI_PBAC_SB (1 << 7) +#define PCI_PBAC_PP (1 << 8) #define PCI_PBAC_MR_BIT 9 #define PCI_PBAC_MR 0x00000600 #define PCI_PBAC_MR_RD 0 #define PCI_PBAC_MR_RD_LINE 1 -#define PCI_PBAC_MR_RD_MULT 2 +#define PCI_PBAC_MR_RD_MULT 2 #define PCI_PBAC_MRL (1 << 11) #define PCI_PBAC_MRM (1 << 12) #define PCI_PBAC_TRP (1 << 13) @@ -227,14 +227,14 @@ struct pci_msu { */ #define PCI_LBAC_MSI (1 << 0) -#define PCI_LBAC_MSI_MEM 0 -#define PCI_LBAC_MSI_IO 1 +#define PCI_LBAC_MSI_MEM 0 +#define PCI_LBAC_MSI_IO 1 #define PCI_LBAC_SIZE_BIT 2 #define PCI_LBAC_SIZE 0x0000007c #define PCI_LBAC_SB (1 << 7) #define PCI_LBAC_RT (1 << 8) -#define PCI_LBAC_RT_NO_PREF 0 -#define PCI_LBAC_RT_PREF 1 +#define PCI_LBAC_RT_NO_PREF 0 +#define PCI_LBAC_RT_PREF 1 /* * PCI Local Base Address [0|1|2|3] Mapping Register @@ -279,16 +279,16 @@ struct pci_msu { #define PCI_DMAD_PT 0x00c00000 /* preferred transaction field */ /* These are for reads (DMA channel 8) */ #define PCI_DMAD_DEVCMD_MR 0 /* memory read */ -#define PCI_DMAD_DEVCMD_MRL 1 /* memory read line */ -#define PCI_DMAD_DEVCMD_MRM 2 /* memory read multiple */ -#define PCI_DMAD_DEVCMD_IOR 3 /* I/O read */ +#define PCI_DMAD_DEVCMD_MRL 1 /* memory read line */ +#define PCI_DMAD_DEVCMD_MRM 2 /* memory read multiple */ +#define PCI_DMAD_DEVCMD_IOR 3 /* I/O read */ /* These are for writes (DMA channel 9) */ #define PCI_DMAD_DEVCMD_MW 0 /* memory write */ -#define PCI_DMAD_DEVCMD_MWI 1 /* memory write invalidate */ -#define PCI_DMAD_DEVCMD_IOW 3 /* I/O write */ +#define PCI_DMAD_DEVCMD_MWI 1 /* memory write invalidate */ +#define PCI_DMAD_DEVCMD_IOW 3 /* I/O write */ /* Swap byte field applies to both DMA channel 8 and 9 */ -#define PCI_DMAD_SB (1 << 24) /* swap byte field */ +#define PCI_DMAD_SB (1 << 24) /* swap byte field */ /* @@ -309,7 +309,7 @@ struct pci_msu { #define PCI_MSU_M1 (1 << 1) #define PCI_MSU_DB (1 << 2) -#define PCI_MSG_ADDR 0xB8088010 +#define PCI_MSG_ADDR 0xB8088010 #define PCI0_ADDR 0xB8080000 #define rc32434_pci ((struct pci_reg *) PCI0_ADDR) #define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR) @@ -331,9 +331,9 @@ struct pci_msu { #define PCILBA_SIZE_MASK 0x1F #define SIZE_256MB 0x1C #define SIZE_128MB 0x1B -#define SIZE_64MB 0x1A +#define SIZE_64MB 0x1A #define SIZE_32MB 0x19 -#define SIZE_16MB 0x18 +#define SIZE_16MB 0x18 #define SIZE_4MB 0x16 #define SIZE_2MB 0x15 #define SIZE_1MB 0x14 @@ -363,7 +363,7 @@ struct pci_msu { #define KORINA_CONFIG23_ADDR 0x8000005C #define KORINA_CONFIG24_ADDR 0x80000060 #define KORINA_CONFIG25_ADDR 0x80000064 -#define KORINA_CMD (PCI_CFG04_CMD_IO_ENA | \ +#define KORINA_CMD (PCI_CFG04_CMD_IO_ENA | \ PCI_CFG04_CMD_MEM_ENA | \ PCI_CFG04_CMD_BM_ENA | \ PCI_CFG04_CMD_MW_INV | \ @@ -401,8 +401,8 @@ struct pci_msu { #define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */ #define KORINA_CNFG4 KORINA_BAR0 -#define KORINA_CNFG5 KORINA_BAR1 -#define KORINA_CNFG6 KORINA_BAR2 +#define KORINA_CNFG5 KORINA_BAR1 +#define KORINA_CNFG6 KORINA_BAR2 #define KORINA_CNFG7 KORINA_BAR3 #define KORINA_SUBSYS_VENDOR_ID 0x011d @@ -410,20 +410,20 @@ struct pci_msu { #define KORINA_CNFG8 0 #define KORINA_CNFG9 0 #define KORINA_CNFG10 0 -#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \ +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \ KORINA_SUBSYSTEM_ID) #define KORINA_INT_LINE 1 #define KORINA_INT_PIN 1 #define KORINA_MIN_GNT 8 #define KORINA_MAX_LAT 0x38 #define KORINA_CNFG12 0 -#define KORINA_CNFG13 0 +#define KORINA_CNFG13 0 #define KORINA_CNFG14 0 #define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \ (KORINA_MIN_GNT<<16) | \ (KORINA_INT_PIN<<8) | \ KORINA_INT_LINE) -#define KORINA_RETRY_LIMIT 0x80 +#define KORINA_RETRY_LIMIT 0x80 #define KORINA_TRDY_LIMIT 0x80 #define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \ KORINA_TRDY_LIMIT) @@ -475,7 +475,7 @@ struct pci_msu { #define KORINA_PBA3M 0 #define KORINA_CNFG24 KORINA_PBA3M -#define PCITC_DTIMER_VAL 8 +#define PCITC_DTIMER_VAL 8 #define PCITC_RTIMER_VAL 0x10 -#endif /* __ASM_RC32434_PCI_H */ +#endif /* __ASM_RC32434_PCI_H */ diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h index 6dc5f8df1f3..aac8ce8902e 100644 --- a/arch/mips/include/asm/mach-rc32434/rb.h +++ b/arch/mips/include/asm/mach-rc32434/rb.h @@ -18,7 +18,7 @@ #include <linux/genhd.h> #define REGBASE 0x18000000 -#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE)) +#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE)) #define UART0BASE 0x58000 #define RST (1 << 15) #define DEV0BASE 0x010000 @@ -80,10 +80,10 @@ struct cf_device { struct mpmc_device { unsigned char state; spinlock_t lock; - void __iomem *base; + void __iomem *base; }; extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask); extern unsigned char get_latch_u5(void); -#endif /* __ASM_RC32434_RB_H */ +#endif /* __ASM_RC32434_RB_H */ diff --git a/arch/mips/include/asm/mach-rc32434/rc32434.h b/arch/mips/include/asm/mach-rc32434/rc32434.h index fce25d4231f..02fd32b4be1 100644 --- a/arch/mips/include/asm/mach-rc32434/rc32434.h +++ b/arch/mips/include/asm/mach-rc32434/rc32434.h @@ -16,4 +16,4 @@ static inline void rc32434_sync(void) __asm__ volatile ("sync"); } -#endif /* _ASM_RC32434_RC32434_H_ */ +#endif /* _ASM_RC32434_RC32434_H_ */ diff --git a/arch/mips/include/asm/mach-rc32434/timer.h b/arch/mips/include/asm/mach-rc32434/timer.h index e49b1d57a01..cda26bb9eea 100644 --- a/arch/mips/include/asm/mach-rc32434/timer.h +++ b/arch/mips/include/asm/mach-rc32434/timer.h @@ -51,15 +51,15 @@ struct timer { #define RC32434_CTC_TO_BIT 1 /* Real time clock registers */ -#define RC32434_RTC_MSK(x) BIT_TO_MASK(x) -#define RC32434_RTC_CE_BIT 0 -#define RC32434_RTC_TO_BIT 1 -#define RC32434_RTC_RQE_BIT 2 +#define RC32434_RTC_MSK(x) BIT_TO_MASK(x) +#define RC32434_RTC_CE_BIT 0 +#define RC32434_RTC_TO_BIT 1 +#define RC32434_RTC_RQE_BIT 2 /* Counter registers */ -#define RC32434_RCOUNT_BIT 0 -#define RC32434_RCOUNT_MSK 0x0000ffff -#define RC32434_RCOMP_BIT 0 -#define RC32434_RCOMP_MSK 0x0000ffff +#define RC32434_RCOUNT_BIT 0 +#define RC32434_RCOUNT_MSK 0x0000ffff +#define RC32434_RCOMP_BIT 0 +#define RC32434_RCOMP_MSK 0x0000ffff -#endif /* __ASM_RC32434_TIMER_H */ +#endif /* __ASM_RC32434_TIMER_H */ diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h index 7f3e3f9bd23..bfbd7035d4c 100644 --- a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h @@ -23,15 +23,15 @@ /* #define cpu_has_watch ? */ #define cpu_has_divec 1 #define cpu_has_vce 0 -/* #define cpu_has_cache_cdex_p ? */ -/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ /* #define cpu_has_prefetch ? */ #define cpu_has_mcheck 1 /* #define cpu_has_ejtag ? */ -#ifdef CONFIG_CPU_HAS_LLSC -#define cpu_has_llsc 1 -#else +#ifdef CONFIG_CPU_MICROMIPS #define cpu_has_llsc 0 +#else +#define cpu_has_llsc 1 #endif /* #define cpu_has_vtag_icache ? */ /* #define cpu_has_dc_aliases ? */ @@ -53,8 +53,8 @@ /* #define cpu_has_watch ? */ #define cpu_has_divec 1 #define cpu_has_vce 0 -/* #define cpu_has_cache_cdex_p ? */ -/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ /* #define cpu_has_prefetch ? */ #define cpu_has_mcheck 1 /* #define cpu_has_ejtag ? */ diff --git a/arch/mips/include/asm/mach-sead3/irq.h b/arch/mips/include/asm/mach-sead3/irq.h index 652ea4c38cd..5d154cfbcf4 100644 --- a/arch/mips/include/asm/mach-sead3/irq.h +++ b/arch/mips/include/asm/mach-sead3/irq.h @@ -1,7 +1,7 @@ #ifndef __ASM_MACH_MIPS_IRQ_H #define __ASM_MACH_MIPS_IRQ_H -#define NR_IRQS 256 +#define NR_IRQS 256 #include_next <irq.h> diff --git a/arch/mips/include/asm/mach-sead3/kernel-entry-init.h b/arch/mips/include/asm/mach-sead3/kernel-entry-init.h index 3dfbd8e7947..6cccd4d558d 100644 --- a/arch/mips/include/asm/mach-sead3/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-sead3/kernel-entry-init.h @@ -10,37 +10,6 @@ #define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H .macro kernel_entry_setup -#ifdef CONFIG_MIPS_MT_SMTC - mfc0 t0, CP0_CONFIG - bgez t0, 9f - mfc0 t0, CP0_CONFIG, 1 - bgez t0, 9f - mfc0 t0, CP0_CONFIG, 2 - bgez t0, 9f - mfc0 t0, CP0_CONFIG, 3 - and t0, 1<<2 - bnez t0, 0f -9 : - /* Assume we came from YAMON... */ - PTR_LA v0, 0x9fc00534 /* YAMON print */ - lw v0, (v0) - move a0, zero - PTR_LA a1, nonmt_processor - jal v0 - - PTR_LA v0, 0x9fc00520 /* YAMON exit */ - lw v0, (v0) - li a0, 1 - jal v0 - -1 : b 1b - - __INITDATA -nonmt_processor : - .asciz "SMTC kernel requires the MT ASE to run\n" - __FINIT -0 : -#endif .endm /* diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h index 176f5b32dc6..0a227d426b9 100644 --- a/arch/mips/include/asm/mach-sibyte/war.h +++ b/arch/mips/include/asm/mach-sibyte/war.h @@ -21,12 +21,12 @@ extern int sb1250_m3_workaround_needed(void); #endif #define BCM1250_M3_WAR sb1250_m3_workaround_needed() -#define SIBYTE_1956_WAR 1 +#define SIBYTE_1956_WAR 1 #else #define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 +#define SIBYTE_1956_WAR 0 #endif diff --git a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h b/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h deleted file mode 100644 index 83746b84a5e..00000000000 --- a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This is a direct copy of the ev96100.h file, with a global - * search and replace. The numbers are the same. - * - * The reason I'm duplicating this is so that the 64120/96100 - * defines won't be confusing in the source code. - */ -#ifndef __ASM_MIPS_GT64120_H -#define __ASM_MIPS_GT64120_H - -/* - * This is the CPU physical memory map of PPMC Board: - * - * 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#) - * 0x1C000000-0x1C000000 - LED (CS0) - * 0x1C800000-0x1C800007 - UART 16550 port (CS1) - * 0x1F000000-0x1F000000 - MailBox (CS3) - * 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS) - */ - -#define WRPPMC_SDRAM_SCS0_BASE 0x00000000 -#define WRPPMC_SDRAM_SCS0_SIZE 0x04000000 - -#define WRPPMC_UART16550_BASE 0x1C800000 -#define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */ - -#define WRPPMC_LED_BASE 0x1C000000 -#define WRPPMC_MBOX_BASE 0x1F000000 - -#define WRPPMC_BOOTROM_BASE 0x1FC00000 -#define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */ - -#define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */ -#define WRPPMC_UART16550_IRQ 6 -#define WRPPMC_PCI_INTA_IRQ 3 - -/* - * PCI Bus I/O and Memory resources allocation - * - * NOTE: We only have PCI_0 hose interface - */ -#define GT_PCI_MEM_BASE 0x13000000UL -#define GT_PCI_MEM_SIZE 0x02000000UL -#define GT_PCI_IO_BASE 0x11000000UL -#define GT_PCI_IO_SIZE 0x02000000UL - -/* - * PCI interrupts will come in on either the INTA or INTD interrupt lines, - * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our - * boards, they all either come in on IntD or they all come in on IntA, they - * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the - * "requested" interrupt numbers and go through the list whenever we get an - * IntA/D. - * - * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and - * INTD is 11. - */ -#define GT_TIMER 4 -#define GT_INTA 2 -#define GT_INTD 5 - -#ifndef __ASSEMBLY__ - -/* - * GT64120 internal register space base address - */ -extern unsigned long gt64120_base; - -#define GT64120_BASE (gt64120_base) - -/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */ -#undef WRPPMC_EARLY_DEBUG - -#ifdef WRPPMC_EARLY_DEBUG -extern void wrppmc_led_on(int mask); -extern void wrppmc_led_off(int mask); -extern void wrppmc_early_printk(const char *fmt, ...); -#else -#define wrppmc_early_printk(fmt, ...) do {} while (0) -#endif /* WRPPMC_EARLY_DEBUG */ - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_MIPS_GT64120_H */ diff --git a/arch/mips/include/asm/mc146818-time.h b/arch/mips/include/asm/mc146818-time.h index 4a08dbe37db..9e1ad26abdc 100644 --- a/arch/mips/include/asm/mc146818-time.h +++ b/arch/mips/include/asm/mc146818-time.h @@ -26,7 +26,7 @@ * MC146818A or Dallas DS12887 data sheet for details. * * BUG: This routine does not handle hour overflow properly; it just - * sets the minutes. Usually you'll only notice that after reboot! + * sets the minutes. Usually you'll only notice that after reboot! */ static inline int mc146818_set_rtc_mmss(unsigned long nowtime) { @@ -77,7 +77,7 @@ static inline int mc146818_set_rtc_mmss(unsigned long nowtime) * battery and quartz) will not reset the oscillator and will not * update precisely 500 ms later. You won't find this mentioned in * the Dallas Semiconductor data sheets, but who believes data - * sheets anyway ... -- Markus Kuhn + * sheets anyway ... -- Markus Kuhn */ CMOS_WRITE(save_control, RTC_CONTROL); CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h index d14e2adc4be..b2048d1bcc1 100644 --- a/arch/mips/include/asm/mips-boards/bonito64.h +++ b/arch/mips/include/asm/mips-boards/bonito64.h @@ -41,18 +41,18 @@ extern unsigned long _pcictrl_bonito_pcicfg; #define BONITO_BOOT_BASE 0x1fc00000 #define BONITO_BOOT_SIZE 0x00100000 -#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) +#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) #define BONITO_FLASH_BASE 0x1c000000 #define BONITO_FLASH_SIZE 0x03000000 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) #define BONITO_SOCKET_BASE 0x1f800000 #define BONITO_SOCKET_SIZE 0x00400000 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) -#define BONITO_REG_BASE 0x1fe00000 -#define BONITO_REG_SIZE 0x00040000 +#define BONITO_REG_BASE 0x1fe00000 +#define BONITO_REG_SIZE 0x00040000 #define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) -#define BONITO_DEV_BASE 0x1ff00000 -#define BONITO_DEV_SIZE 0x00100000 +#define BONITO_DEV_BASE 0x1ff00000 +#define BONITO_DEV_SIZE 0x00100000 #define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) #define BONITO_PCILO_BASE 0x10000000 #define BONITO_PCILO_SIZE 0x0c000000 @@ -79,14 +79,14 @@ extern unsigned long _pcictrl_bonito_pcicfg; /* PCI Configuration Registers */ -#define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x)) +#define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x)) #define BONITO_PCIDID BONITO_PCI_REG(0x00) #define BONITO_PCICMD BONITO_PCI_REG(0x04) -#define BONITO_PCICLASS BONITO_PCI_REG(0x08) +#define BONITO_PCICLASS BONITO_PCI_REG(0x08) #define BONITO_PCILTIMER BONITO_PCI_REG(0x0c) -#define BONITO_PCIBASE0 BONITO_PCI_REG(0x10) -#define BONITO_PCIBASE1 BONITO_PCI_REG(0x14) -#define BONITO_PCIBASE2 BONITO_PCI_REG(0x18) +#define BONITO_PCIBASE0 BONITO_PCI_REG(0x10) +#define BONITO_PCIBASE1 BONITO_PCI_REG(0x14) +#define BONITO_PCIBASE2 BONITO_PCI_REG(0x18) #define BONITO_PCIEXPRBASE BONITO_PCI_REG(0x30) #define BONITO_PCIINT BONITO_PCI_REG(0x3c) @@ -95,7 +95,7 @@ extern unsigned long _pcictrl_bonito_pcicfg; #define BONITO_PCICMD_MABORT_CLR 0x20000000 #define BONITO_PCICMD_MTABORT_CLR 0x10000000 #define BONITO_PCICMD_TABORT_CLR 0x08000000 -#define BONITO_PCICMD_MPERR_CLR 0x01000000 +#define BONITO_PCICMD_MPERR_CLR 0x01000000 #define BONITO_PCICMD_PERRRESPEN 0x00000040 #define BONITO_PCICMD_ASTEPEN 0x00000080 #define BONITO_PCICMD_SERREN 0x00000100 @@ -139,7 +139,7 @@ extern unsigned long _pcictrl_bonito_pcicfg; /* Other Bonito configuration */ -#define BONITO_BONGENCFG_OFFSET 0x4 +#define BONITO_BONGENCFG_OFFSET 0x4 #define BONITO_BONGENCFG BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET) #define BONITO_BONGENCFG_DEBUGMODE 0x00000001 @@ -165,7 +165,7 @@ extern unsigned long _pcictrl_bonito_pcicfg; /* 2. IO & IDE configuration */ -#define BONITO_IODEVCFG BONITO(BONITO_REGBASE + 0x08) +#define BONITO_IODEVCFG BONITO(BONITO_REGBASE + 0x08) /* 3. IO & IDE configuration */ @@ -181,33 +181,33 @@ extern unsigned long _pcictrl_bonito_pcicfg; /* GPIO Regs - r/w */ -#define BONITO_GPIODATA_OFFSET 0x1c -#define BONITO_GPIODATA BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET) +#define BONITO_GPIODATA_OFFSET 0x1c +#define BONITO_GPIODATA BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET) #define BONITO_GPIOIE BONITO(BONITO_REGBASE + 0x20) /* ICU Configuration Regs - r/w */ #define BONITO_INTEDGE BONITO(BONITO_REGBASE + 0x24) -#define BONITO_INTSTEER BONITO(BONITO_REGBASE + 0x28) +#define BONITO_INTSTEER BONITO(BONITO_REGBASE + 0x28) #define BONITO_INTPOL BONITO(BONITO_REGBASE + 0x2c) /* ICU Enable Regs - IntEn & IntISR are r/o. */ -#define BONITO_INTENSET BONITO(BONITO_REGBASE + 0x30) -#define BONITO_INTENCLR BONITO(BONITO_REGBASE + 0x34) +#define BONITO_INTENSET BONITO(BONITO_REGBASE + 0x30) +#define BONITO_INTENCLR BONITO(BONITO_REGBASE + 0x34) #define BONITO_INTEN BONITO(BONITO_REGBASE + 0x38) #define BONITO_INTISR BONITO(BONITO_REGBASE + 0x3c) /* PCI mail boxes */ -#define BONITO_PCIMAIL0_OFFSET 0x40 -#define BONITO_PCIMAIL1_OFFSET 0x44 -#define BONITO_PCIMAIL2_OFFSET 0x48 -#define BONITO_PCIMAIL3_OFFSET 0x4c -#define BONITO_PCIMAIL0 BONITO(BONITO_REGBASE + 0x40) -#define BONITO_PCIMAIL1 BONITO(BONITO_REGBASE + 0x44) -#define BONITO_PCIMAIL2 BONITO(BONITO_REGBASE + 0x48) -#define BONITO_PCIMAIL3 BONITO(BONITO_REGBASE + 0x4c) +#define BONITO_PCIMAIL0_OFFSET 0x40 +#define BONITO_PCIMAIL1_OFFSET 0x44 +#define BONITO_PCIMAIL2_OFFSET 0x48 +#define BONITO_PCIMAIL3_OFFSET 0x4c +#define BONITO_PCIMAIL0 BONITO(BONITO_REGBASE + 0x40) +#define BONITO_PCIMAIL1 BONITO(BONITO_REGBASE + 0x44) +#define BONITO_PCIMAIL2 BONITO(BONITO_REGBASE + 0x48) +#define BONITO_PCIMAIL3 BONITO(BONITO_REGBASE + 0x4c) /* 6. PCI cache */ @@ -216,7 +216,7 @@ extern unsigned long _pcictrl_bonito_pcicfg; #define BONITO_PCICACHETAG BONITO(BONITO_REGBASE + 0x54) #define BONITO_PCIBADADDR BONITO(BONITO_REGBASE + 0x58) -#define BONITO_PCIMSTAT BONITO(BONITO_REGBASE + 0x5c) +#define BONITO_PCIMSTAT BONITO(BONITO_REGBASE + 0x5c) /* @@ -228,20 +228,20 @@ extern unsigned long _pcictrl_bonito_pcicfg; #define BONITO_CONFIGBASE 0x000 #define BONITO_BONITOBASE 0x100 -#define BONITO_LDMABASE 0x200 +#define BONITO_LDMABASE 0x200 #define BONITO_COPBASE 0x300 #define BONITO_REG_BLOCKMASK 0x300 -#define BONITO_LDMACTRL BONITO(BONITO_LDMABASE + 0x0) -#define BONITO_LDMASTAT BONITO(BONITO_LDMABASE + 0x0) -#define BONITO_LDMAADDR BONITO(BONITO_LDMABASE + 0x4) +#define BONITO_LDMACTRL BONITO(BONITO_LDMABASE + 0x0) +#define BONITO_LDMASTAT BONITO(BONITO_LDMABASE + 0x0) +#define BONITO_LDMAADDR BONITO(BONITO_LDMABASE + 0x4) #define BONITO_LDMAGO BONITO(BONITO_LDMABASE + 0x8) -#define BONITO_LDMADATA BONITO(BONITO_LDMABASE + 0xc) +#define BONITO_LDMADATA BONITO(BONITO_LDMABASE + 0xc) #define BONITO_COPCTRL BONITO(BONITO_COPBASE + 0x0) #define BONITO_COPSTAT BONITO(BONITO_COPBASE + 0x0) -#define BONITO_COPPADDR BONITO(BONITO_COPBASE + 0x4) -#define BONITO_COPDADDR BONITO(BONITO_COPBASE + 0x8) +#define BONITO_COPPADDR BONITO(BONITO_COPBASE + 0x4) +#define BONITO_COPDADDR BONITO(BONITO_COPBASE + 0x8) #define BONITO_COPGO BONITO(BONITO_COPBASE + 0xc) @@ -257,7 +257,7 @@ extern unsigned long _pcictrl_bonito_pcicfg; #define BONITO_IDECOPGO_DMA_SIZE_SHIFT 0 #define BONITO_IDECOPGO_DMA_WRITE 0x00010000 #define BONITO_IDECOPGO_DMAWCOUNT 0x000f0000 -#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16 +#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16 #define BONITO_IDECOPCTRL_DMA_STARTBIT 0x80000000 #define BONITO_IDECOPCTRL_DMA_RSTBIT 0x40000000 @@ -291,11 +291,11 @@ extern unsigned long _pcictrl_bonito_pcicfg; #define BONITO_SDCFG_DRAMMODESET 0x00200000 /* --- */ #define BONITO_SDCFG_DRAMEXTREGS 0x00400000 -#define BONITO_SDCFG_DRAMPARITY 0x00800000 +#define BONITO_SDCFG_DRAMPARITY 0x00800000 /* Added by RPF 11-9-00 */ -#define BONITO_SDCFG_DRAMBURSTLEN 0x03000000 -#define BONITO_SDCFG_DRAMBURSTLEN_SHIFT 24 -#define BONITO_SDCFG_DRAMMODESET_DONE 0x80000000 +#define BONITO_SDCFG_DRAMBURSTLEN 0x03000000 +#define BONITO_SDCFG_DRAMBURSTLEN_SHIFT 24 +#define BONITO_SDCFG_DRAMMODESET_DONE 0x80000000 /* --- */ /* PCI Cache - pciCacheCtrl */ @@ -308,7 +308,7 @@ extern unsigned long _pcictrl_bonito_pcicfg; #define BONITO_PCICACHECTRL_IOBCCOH_PRES 0x00000100 #define BONITO_PCICACHECTRL_IOBCCOH_EN 0x00000200 -#define BONITO_PCICACHECTRL_CPUCOH_PRES 0x00000400 +#define BONITO_PCICACHECTRL_CPUCOH_PRES 0x00000400 #define BONITO_PCICACHECTRL_CPUCOH_EN 0x00000800 #define BONITO_IODEVCFG_BUFFBIT_CS0 0x00000001 @@ -343,18 +343,18 @@ extern unsigned long _pcictrl_bonito_pcicfg; /* gpio */ #define BONITO_GPIO_GPIOW 0x000003ff -#define BONITO_GPIO_GPIOW_SHIFT 0 +#define BONITO_GPIO_GPIOW_SHIFT 0 #define BONITO_GPIO_GPIOR 0x01ff0000 -#define BONITO_GPIO_GPIOR_SHIFT 16 +#define BONITO_GPIO_GPIOR_SHIFT 16 #define BONITO_GPIO_GPINR 0xfe000000 -#define BONITO_GPIO_GPINR_SHIFT 25 +#define BONITO_GPIO_GPINR_SHIFT 25 #define BONITO_GPIO_IOW(N) (1<<(BONITO_GPIO_GPIOW_SHIFT+(N))) #define BONITO_GPIO_IOR(N) (1<<(BONITO_GPIO_GPIOR_SHIFT+(N))) #define BONITO_GPIO_INR(N) (1<<(BONITO_GPIO_GPINR_SHIFT+(N))) /* ICU */ #define BONITO_ICU_MBOXES 0x0000000f -#define BONITO_ICU_MBOXES_SHIFT 0 +#define BONITO_ICU_MBOXES_SHIFT 0 #define BONITO_ICU_DMARDY 0x00000010 #define BONITO_ICU_DMAEMPTY 0x00000020 #define BONITO_ICU_COPYRDY 0x00000040 @@ -384,13 +384,13 @@ extern unsigned long _pcictrl_bonito_pcicfg; #define BONITO_PCIMAP_PCIMAP_2 0x00040000 #define BONITO_PCIMAP_WIN(WIN, ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) -#define BONITO_PCIMAP_WINSIZE (1<<26) +#define BONITO_PCIMAP_WINSIZE (1<<26) #define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1)) #define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26) /* pcimembaseCfg */ -#define BONITO_PCIMEMBASECFG_MASK 0xf0000000 +#define BONITO_PCIMEMBASECFG_MASK 0xf0000000 #define BONITO_PCIMEMBASECFG_MEMBASE0_MASK 0x0000001f #define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT 0 #define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS 0x000003e0 @@ -406,21 +406,21 @@ extern unsigned long _pcictrl_bonito_pcicfg; #define BONITO_PCIMEMBASECFG_MEMBASE1_IO 0x00800000 #define BONITO_PCIMEMBASECFG_ASHIFT 23 -#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff +#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff #define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) #define BONITO_PCIMEMBASECFGBASE(WIN, BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) #define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) -#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) -#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) +#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) +#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) #define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) -#define BONITO_PCITOPHYS(WIN, ADDR, CFG) ( \ - (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \ - (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \ - ) +#define BONITO_PCITOPHYS(WIN, ADDR, CFG) ( \ + (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \ + (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \ + ) /* PCICmd */ diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h index 6e23ceb0ba8..c904c24550f 100644 --- a/arch/mips/include/asm/mips-boards/generic.h +++ b/arch/mips/include/asm/mips-boards/generic.h @@ -1,21 +1,14 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive * for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * * Defines of the MIPS boards specific address-MAP, registers, etc. + * + * Copyright (C) 2000,2012 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard <carstenl@mips.com> + * Steven J. Hill <sjhill@mips.com> */ #ifndef __ASM_MIPS_BOARDS_GENERIC_H #define __ASM_MIPS_BOARDS_GENERIC_H @@ -27,39 +20,26 @@ /* * Display register base. */ -#define ASCII_DISPLAY_WORD_BASE 0x1f000410 -#define ASCII_DISPLAY_POS_BASE 0x1f000418 - - -/* - * Yamon Prom print address. - */ -#define YAMON_PROM_PRINT_ADDR 0x1fc00504 - - -/* - * Reset register. - */ -#define SOFTRES_REG 0x1f000500 -#define GORESET 0x42 +#define ASCII_DISPLAY_WORD_BASE 0x1f000410 +#define ASCII_DISPLAY_POS_BASE 0x1f000418 /* * Revision register. */ -#define MIPS_REVISION_REG 0x1fc00010 -#define MIPS_REVISION_CORID_QED_RM5261 0 -#define MIPS_REVISION_CORID_CORE_LV 1 -#define MIPS_REVISION_CORID_BONITO64 2 -#define MIPS_REVISION_CORID_CORE_20K 3 -#define MIPS_REVISION_CORID_CORE_FPGA 4 -#define MIPS_REVISION_CORID_CORE_MSC 5 -#define MIPS_REVISION_CORID_CORE_EMUL 6 -#define MIPS_REVISION_CORID_CORE_FPGA2 7 -#define MIPS_REVISION_CORID_CORE_FPGAR2 8 -#define MIPS_REVISION_CORID_CORE_FPGA3 9 -#define MIPS_REVISION_CORID_CORE_24K 10 -#define MIPS_REVISION_CORID_CORE_FPGA4 11 -#define MIPS_REVISION_CORID_CORE_FPGA5 12 +#define MIPS_REVISION_REG 0x1fc00010 +#define MIPS_REVISION_CORID_QED_RM5261 0 +#define MIPS_REVISION_CORID_CORE_LV 1 +#define MIPS_REVISION_CORID_BONITO64 2 +#define MIPS_REVISION_CORID_CORE_20K 3 +#define MIPS_REVISION_CORID_CORE_FPGA 4 +#define MIPS_REVISION_CORID_CORE_MSC 5 +#define MIPS_REVISION_CORID_CORE_EMUL 6 +#define MIPS_REVISION_CORID_CORE_FPGA2 7 +#define MIPS_REVISION_CORID_CORE_FPGAR2 8 +#define MIPS_REVISION_CORID_CORE_FPGA3 9 +#define MIPS_REVISION_CORID_CORE_24K 10 +#define MIPS_REVISION_CORID_CORE_FPGA4 11 +#define MIPS_REVISION_CORID_CORE_FPGA5 12 /**** Artificial corid defines ****/ /* @@ -93,4 +73,7 @@ extern void mips_pcibios_init(void); #define mips_pcibios_init() do { } while (0) #endif -#endif /* __ASM_MIPS_BOARDS_GENERIC_H */ +extern void mips_scroll_message(void); +extern void mips_display_message(const char *str); + +#endif /* __ASM_MIPS_BOARDS_GENERIC_H */ diff --git a/arch/mips/include/asm/mips-boards/launch.h b/arch/mips/include/asm/mips-boards/launch.h index d8ae7f95a52..653477e4074 100644 --- a/arch/mips/include/asm/mips-boards/launch.h +++ b/arch/mips/include/asm/mips-boards/launch.h @@ -16,11 +16,11 @@ struct cpulaunch { #else #define LOG2CPULAUNCH 5 -#define LAUNCH_PC 0 -#define LAUNCH_GP 4 -#define LAUNCH_SP 8 -#define LAUNCH_A0 12 -#define LAUNCH_FLAGS 28 +#define LAUNCH_PC 0 +#define LAUNCH_GP 4 +#define LAUNCH_SP 8 +#define LAUNCH_A0 12 +#define LAUNCH_FLAGS 28 #endif diff --git a/arch/mips/include/asm/mips-boards/malta.h b/arch/mips/include/asm/mips-boards/malta.h index c1891578fa6..fd9774269a5 100644 --- a/arch/mips/include/asm/mips-boards/malta.h +++ b/arch/mips/include/asm/mips-boards/malta.h @@ -33,9 +33,9 @@ * Malta I/O ports base address for the Galileo GT64120 and Algorithmics * Bonito system controllers. */ -#define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS) -#define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000)) -#define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL) +#define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS) +#define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000)) +#define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL) static inline unsigned long get_gt_port_base(unsigned long reg) { @@ -64,6 +64,11 @@ static inline unsigned long get_msc_port_base(unsigned long reg) #define GIC_ADDRSPACE_SZ (128 * 1024) /* + * CPC Specific definitions + */ +#define CPC_BASE_ADDR 0x1bde0000 + +/* * MSC01 BIU Specific definitions * FIXME : These should be elsewhere ? */ @@ -77,8 +82,8 @@ static inline unsigned long get_msc_port_base(unsigned long reg) /* * Malta RTC-device indirect register access. */ -#define MALTA_RTC_ADR_REG 0x70 -#define MALTA_RTC_DAT_REG 0x71 +#define MALTA_RTC_ADR_REG 0x70 +#define MALTA_RTC_DAT_REG 0x71 /* * Malta SMSC FDC37M817 Super I/O Controller register. diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h index 66924481575..e330732ddf9 100644 --- a/arch/mips/include/asm/mips-boards/maltaint.h +++ b/arch/mips/include/asm/mips-boards/maltaint.h @@ -4,8 +4,8 @@ * for more details. * * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved. - * Carsten Langgaard <carstenl@mips.com> - * Steven J. Hill <sjhill@mips.com> + * Carsten Langgaard <carstenl@mips.com> + * Steven J. Hill <sjhill@mips.com> */ #ifndef _MIPS_MALTAINT_H #define _MIPS_MALTAINT_H @@ -24,9 +24,9 @@ #define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 #define MIPSCPU_INT_MB1 3 #define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 -#define MIPSCPU_INT_IPI0 MIPSCPU_INT_MB1 /* GIC IPI */ +#define MIPSCPU_INT_IPI0 MIPSCPU_INT_MB1 /* GIC IPI */ #define MIPSCPU_INT_MB2 4 -#define MIPSCPU_INT_IPI1 MIPSCPU_INT_MB2 /* GIC IPI */ +#define MIPSCPU_INT_IPI1 MIPSCPU_INT_MB2 /* GIC IPI */ #define MIPSCPU_INT_MB3 5 #define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 #define MIPSCPU_INT_MB4 6 diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h index 2971d60f2e9..9e340be52a5 100644 --- a/arch/mips/include/asm/mips-boards/piix4.h +++ b/arch/mips/include/asm/mips-boards/piix4.h @@ -1,6 +1,7 @@ /* * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2013 Imagination Technologies Ltd. * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -20,61 +21,50 @@ #ifndef __ASM_MIPS_BOARDS_PIIX4_H #define __ASM_MIPS_BOARDS_PIIX4_H -/************************************************************************ - * IO register offsets - ************************************************************************/ -#define PIIX4_ICTLR1_ICW1 0x20 -#define PIIX4_ICTLR1_ICW2 0x21 -#define PIIX4_ICTLR1_ICW3 0x21 -#define PIIX4_ICTLR1_ICW4 0x21 -#define PIIX4_ICTLR2_ICW1 0xa0 -#define PIIX4_ICTLR2_ICW2 0xa1 -#define PIIX4_ICTLR2_ICW3 0xa1 -#define PIIX4_ICTLR2_ICW4 0xa1 -#define PIIX4_ICTLR1_OCW1 0x21 -#define PIIX4_ICTLR1_OCW2 0x20 -#define PIIX4_ICTLR1_OCW3 0x20 -#define PIIX4_ICTLR1_OCW4 0x20 -#define PIIX4_ICTLR2_OCW1 0xa1 -#define PIIX4_ICTLR2_OCW2 0xa0 -#define PIIX4_ICTLR2_OCW3 0xa0 -#define PIIX4_ICTLR2_OCW4 0xa0 +/* PIRQX Route Control */ +#define PIIX4_FUNC0_PIRQRC 0x60 +#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7) +#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf +#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16 +/* SERIRQ Control */ +#define PIIX4_FUNC0_SERIRQC 0x64 +#define PIIX4_FUNC0_SERIRQC_EN (1 << 7) +#define PIIX4_FUNC0_SERIRQC_CONT (1 << 6) +/* Top Of Memory */ +#define PIIX4_FUNC0_TOM 0x69 +#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0 +/* Deterministic Latency Control */ +#define PIIX4_FUNC0_DLC 0x82 +#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2) +#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1) +#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0) +/* General Configuration */ +#define PIIX4_FUNC0_GENCFG 0xb0 +#define PIIX4_FUNC0_GENCFG_SERIRQ (1 << 16) +/* IDE Timing */ +#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40 +#define PIIX4_FUNC1_IDETIM_PRIMARY_HI 0x41 +#define PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN (1 << 7) +#define PIIX4_FUNC1_IDETIM_SECONDARY_LO 0x42 +#define PIIX4_FUNC1_IDETIM_SECONDARY_HI 0x43 +#define PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7) -/************************************************************************ - * Register encodings. - ************************************************************************/ -#define PIIX4_OCW2_NSEOI (0x1 << 5) -#define PIIX4_OCW2_SEOI (0x3 << 5) -#define PIIX4_OCW2_RNSEOI (0x5 << 5) -#define PIIX4_OCW2_RAEOIS (0x4 << 5) -#define PIIX4_OCW2_RAEOIC (0x0 << 5) -#define PIIX4_OCW2_RSEOI (0x7 << 5) -#define PIIX4_OCW2_SP (0x6 << 5) -#define PIIX4_OCW2_NOP (0x2 << 5) +/* Power Management Configuration Space */ +#define PIIX4_FUNC3_PMBA 0x40 +#define PIIX4_FUNC3_PMREGMISC 0x80 +#define PIIX4_FUNC3_PMREGMISC_EN (1 << 0) -#define PIIX4_OCW2_SEL (0x0 << 3) +/* Power Management IO Space */ +#define PIIX4_FUNC3IO_PMSTS 0x00 +#define PIIX4_FUNC3IO_PMSTS_PWRBTN_STS (1 << 8) +#define PIIX4_FUNC3IO_PMCNTRL 0x04 +#define PIIX4_FUNC3IO_PMCNTRL_SUS_EN (1 << 13) +#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP (0x7 << 10) +#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF (0x0 << 10) +#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_STR (0x1 << 10) -#define PIIX4_OCW2_ILS_0 0 -#define PIIX4_OCW2_ILS_1 1 -#define PIIX4_OCW2_ILS_2 2 -#define PIIX4_OCW2_ILS_3 3 -#define PIIX4_OCW2_ILS_4 4 -#define PIIX4_OCW2_ILS_5 5 -#define PIIX4_OCW2_ILS_6 6 -#define PIIX4_OCW2_ILS_7 7 -#define PIIX4_OCW2_ILS_8 0 -#define PIIX4_OCW2_ILS_9 1 -#define PIIX4_OCW2_ILS_10 2 -#define PIIX4_OCW2_ILS_11 3 -#define PIIX4_OCW2_ILS_12 4 -#define PIIX4_OCW2_ILS_13 5 -#define PIIX4_OCW2_ILS_14 6 -#define PIIX4_OCW2_ILS_15 7 - -#define PIIX4_OCW3_SEL (0x1 << 3) - -#define PIIX4_OCW3_IRR 0x2 -#define PIIX4_OCW3_ISR 0x3 +/* Data for magic special PCI cycle */ +#define PIIX4_SUSPEND_MAGIC 0x00120002 #endif /* __ASM_MIPS_BOARDS_PIIX4_H */ diff --git a/arch/mips/include/asm/mips-boards/prom.h b/arch/mips/include/asm/mips-boards/prom.h deleted file mode 100644 index a9db576a976..00000000000 --- a/arch/mips/include/asm/mips-boards/prom.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * MIPS boards bootprom interface for the Linux kernel. - * - */ - -#ifndef _MIPS_PROM_H -#define _MIPS_PROM_H - -extern char *prom_getcmdline(void); -extern char *prom_getenv(char *name); -extern void prom_init_cmdline(void); -extern void prom_meminit(void); -extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); -extern void mips_display_message(const char *str); -extern void mips_display_word(unsigned int num); -extern void mips_scroll_message(void); -extern int get_ethernet_addr(char *ethernet_addr); - -/* Memory descriptor management. */ -#define PROM_MAX_PMEMBLOCKS 32 -struct prom_pmemblock { - unsigned long base; /* Within KSEG0. */ - unsigned int size; /* In bytes. */ - unsigned int type; /* free or prom memory */ -}; - -#endif /* !(_MIPS_PROM_H) */ diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h index d634d9a807f..6b17aaf7d90 100644 --- a/arch/mips/include/asm/mips-boards/sead3int.h +++ b/arch/mips/include/asm/mips-boards/sead3int.h @@ -4,8 +4,8 @@ * for more details. * * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved. - * Douglas Leung <douglas@mips.com> - * Steven J. Hill <sjhill@mips.com> + * Douglas Leung <douglas@mips.com> + * Steven J. Hill <sjhill@mips.com> */ #ifndef _MIPS_SEAD3INT_H #define _MIPS_SEAD3INT_H diff --git a/arch/mips/include/asm/mips-boards/sim.h b/arch/mips/include/asm/mips-boards/sim.h index acb7c2331d9..b112fdc9f77 100644 --- a/arch/mips/include/asm/mips-boards/sim.h +++ b/arch/mips/include/asm/mips-boards/sim.h @@ -19,18 +19,18 @@ #ifndef _ASM_MIPS_BOARDS_SIM_H #define _ASM_MIPS_BOARDS_SIM_H -#define STATS_ON 1 -#define STATS_OFF 2 -#define STATS_CLEAR 3 -#define STATS_DUMP 4 +#define STATS_ON 1 +#define STATS_OFF 2 +#define STATS_CLEAR 3 +#define STATS_DUMP 4 #define TRACE_ON 5 -#define TRACE_OFF 6 +#define TRACE_OFF 6 #define simcfg(code) \ ({ \ - __asm__ __volatile__( \ - "sltiu $0,$0, %0" \ + __asm__ __volatile__( \ + "sltiu $0,$0, %0" \ ::"i"(code) \ ); \ }) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h new file mode 100644 index 00000000000..6a9d2dd005c --- /dev/null +++ b/arch/mips/include/asm/mips-cm.h @@ -0,0 +1,322 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton <paul.burton@imgtec.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MIPS_ASM_MIPS_CM_H__ +#define __MIPS_ASM_MIPS_CM_H__ + +#include <linux/io.h> +#include <linux/types.h> + +/* The base address of the CM GCR block */ +extern void __iomem *mips_cm_base; + +/* The base address of the CM L2-only sync region */ +extern void __iomem *mips_cm_l2sync_base; + +/** + * __mips_cm_phys_base - retrieve the physical base address of the CM + * + * This function returns the physical base address of the Coherence Manager + * global control block, or 0 if no Coherence Manager is present. It provides + * a default implementation which reads the CMGCRBase register where available, + * and may be overriden by platforms which determine this address in a + * different way by defining a function with the same prototype except for the + * name mips_cm_phys_base (without underscores). + */ +extern phys_t __mips_cm_phys_base(void); + +/** + * mips_cm_probe - probe for a Coherence Manager + * + * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM + * is successfully detected, else -errno. + */ +#ifdef CONFIG_MIPS_CM +extern int mips_cm_probe(void); +#else +static inline int mips_cm_probe(void) +{ + return -ENODEV; +} +#endif + +/** + * mips_cm_present - determine whether a Coherence Manager is present + * + * Returns true if a CM is present in the system, else false. + */ +static inline bool mips_cm_present(void) +{ +#ifdef CONFIG_MIPS_CM + return mips_cm_base != NULL; +#else + return false; +#endif +} + +/** + * mips_cm_has_l2sync - determine whether an L2-only sync region is present + * + * Returns true if the system implements an L2-only sync region, else false. + */ +static inline bool mips_cm_has_l2sync(void) +{ +#ifdef CONFIG_MIPS_CM + return mips_cm_l2sync_base != NULL; +#else + return false; +#endif +} + +/* Offsets to register blocks from the CM base address */ +#define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */ +#define MIPS_CM_CLCB_OFS 0x2000 /* Core Local Control Block */ +#define MIPS_CM_COCB_OFS 0x4000 /* Core Other Control Block */ +#define MIPS_CM_GDB_OFS 0x6000 /* Global Debug Block */ + +/* Total size of the CM memory mapped registers */ +#define MIPS_CM_GCR_SIZE 0x8000 + +/* Size of the L2-only sync region */ +#define MIPS_CM_L2SYNC_SIZE 0x1000 + +/* Macros to ease the creation of register access functions */ +#define BUILD_CM_R_(name, off) \ +static inline u32 *addr_gcr_##name(void) \ +{ \ + return (u32 *)(mips_cm_base + (off)); \ +} \ + \ +static inline u32 read_gcr_##name(void) \ +{ \ + return __raw_readl(addr_gcr_##name()); \ +} + +#define BUILD_CM__W(name, off) \ +static inline void write_gcr_##name(u32 value) \ +{ \ + __raw_writel(value, addr_gcr_##name()); \ +} + +#define BUILD_CM_RW(name, off) \ + BUILD_CM_R_(name, off) \ + BUILD_CM__W(name, off) + +#define BUILD_CM_Cx_R_(name, off) \ + BUILD_CM_R_(cl_##name, MIPS_CM_CLCB_OFS + (off)) \ + BUILD_CM_R_(co_##name, MIPS_CM_COCB_OFS + (off)) + +#define BUILD_CM_Cx__W(name, off) \ + BUILD_CM__W(cl_##name, MIPS_CM_CLCB_OFS + (off)) \ + BUILD_CM__W(co_##name, MIPS_CM_COCB_OFS + (off)) + +#define BUILD_CM_Cx_RW(name, off) \ + BUILD_CM_Cx_R_(name, off) \ + BUILD_CM_Cx__W(name, off) + +/* GCB register accessor functions */ +BUILD_CM_R_(config, MIPS_CM_GCB_OFS + 0x00) +BUILD_CM_RW(base, MIPS_CM_GCB_OFS + 0x08) +BUILD_CM_RW(access, MIPS_CM_GCB_OFS + 0x20) +BUILD_CM_R_(rev, MIPS_CM_GCB_OFS + 0x30) +BUILD_CM_RW(error_mask, MIPS_CM_GCB_OFS + 0x40) +BUILD_CM_RW(error_cause, MIPS_CM_GCB_OFS + 0x48) +BUILD_CM_RW(error_addr, MIPS_CM_GCB_OFS + 0x50) +BUILD_CM_RW(error_mult, MIPS_CM_GCB_OFS + 0x58) +BUILD_CM_RW(l2_only_sync_base, MIPS_CM_GCB_OFS + 0x70) +BUILD_CM_RW(gic_base, MIPS_CM_GCB_OFS + 0x80) +BUILD_CM_RW(cpc_base, MIPS_CM_GCB_OFS + 0x88) +BUILD_CM_RW(reg0_base, MIPS_CM_GCB_OFS + 0x90) +BUILD_CM_RW(reg0_mask, MIPS_CM_GCB_OFS + 0x98) +BUILD_CM_RW(reg1_base, MIPS_CM_GCB_OFS + 0xa0) +BUILD_CM_RW(reg1_mask, MIPS_CM_GCB_OFS + 0xa8) +BUILD_CM_RW(reg2_base, MIPS_CM_GCB_OFS + 0xb0) +BUILD_CM_RW(reg2_mask, MIPS_CM_GCB_OFS + 0xb8) +BUILD_CM_RW(reg3_base, MIPS_CM_GCB_OFS + 0xc0) +BUILD_CM_RW(reg3_mask, MIPS_CM_GCB_OFS + 0xc8) +BUILD_CM_R_(gic_status, MIPS_CM_GCB_OFS + 0xd0) +BUILD_CM_R_(cpc_status, MIPS_CM_GCB_OFS + 0xf0) + +/* Core Local & Core Other register accessor functions */ +BUILD_CM_Cx_RW(reset_release, 0x00) +BUILD_CM_Cx_RW(coherence, 0x08) +BUILD_CM_Cx_R_(config, 0x10) +BUILD_CM_Cx_RW(other, 0x18) +BUILD_CM_Cx_RW(reset_base, 0x20) +BUILD_CM_Cx_R_(id, 0x28) +BUILD_CM_Cx_RW(reset_ext_base, 0x30) +BUILD_CM_Cx_R_(tcid_0_priority, 0x40) +BUILD_CM_Cx_R_(tcid_1_priority, 0x48) +BUILD_CM_Cx_R_(tcid_2_priority, 0x50) +BUILD_CM_Cx_R_(tcid_3_priority, 0x58) +BUILD_CM_Cx_R_(tcid_4_priority, 0x60) +BUILD_CM_Cx_R_(tcid_5_priority, 0x68) +BUILD_CM_Cx_R_(tcid_6_priority, 0x70) +BUILD_CM_Cx_R_(tcid_7_priority, 0x78) +BUILD_CM_Cx_R_(tcid_8_priority, 0x80) + +/* GCR_CONFIG register fields */ +#define CM_GCR_CONFIG_NUMIOCU_SHF 8 +#define CM_GCR_CONFIG_NUMIOCU_MSK (_ULCAST_(0xf) << 8) +#define CM_GCR_CONFIG_PCORES_SHF 0 +#define CM_GCR_CONFIG_PCORES_MSK (_ULCAST_(0xff) << 0) + +/* GCR_BASE register fields */ +#define CM_GCR_BASE_GCRBASE_SHF 15 +#define CM_GCR_BASE_GCRBASE_MSK (_ULCAST_(0x1ffff) << 15) +#define CM_GCR_BASE_CMDEFTGT_SHF 0 +#define CM_GCR_BASE_CMDEFTGT_MSK (_ULCAST_(0x3) << 0) +#define CM_GCR_BASE_CMDEFTGT_DISABLED 0 +#define CM_GCR_BASE_CMDEFTGT_MEM 1 +#define CM_GCR_BASE_CMDEFTGT_IOCU0 2 +#define CM_GCR_BASE_CMDEFTGT_IOCU1 3 + +/* GCR_ACCESS register fields */ +#define CM_GCR_ACCESS_ACCESSEN_SHF 0 +#define CM_GCR_ACCESS_ACCESSEN_MSK (_ULCAST_(0xff) << 0) + +/* GCR_REV register fields */ +#define CM_GCR_REV_MAJOR_SHF 8 +#define CM_GCR_REV_MAJOR_MSK (_ULCAST_(0xff) << 8) +#define CM_GCR_REV_MINOR_SHF 0 +#define CM_GCR_REV_MINOR_MSK (_ULCAST_(0xff) << 0) + +/* GCR_ERROR_CAUSE register fields */ +#define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF 27 +#define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK (_ULCAST_(0x1f) << 27) +#define CM_GCR_ERROR_CAUSE_ERRINFO_SHF 0 +#define CM_GCR_ERROR_CAUSE_ERRINGO_MSK (_ULCAST_(0x7ffffff) << 0) + +/* GCR_ERROR_MULT register fields */ +#define CM_GCR_ERROR_MULT_ERR2ND_SHF 0 +#define CM_GCR_ERROR_MULT_ERR2ND_MSK (_ULCAST_(0x1f) << 0) + +/* GCR_L2_ONLY_SYNC_BASE register fields */ +#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_SHF 12 +#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK (_ULCAST_(0xfffff) << 12) +#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_SHF 0 +#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK (_ULCAST_(0x1) << 0) + +/* GCR_GIC_BASE register fields */ +#define CM_GCR_GIC_BASE_GICBASE_SHF 17 +#define CM_GCR_GIC_BASE_GICBASE_MSK (_ULCAST_(0x7fff) << 17) +#define CM_GCR_GIC_BASE_GICEN_SHF 0 +#define CM_GCR_GIC_BASE_GICEN_MSK (_ULCAST_(0x1) << 0) + +/* GCR_CPC_BASE register fields */ +#define CM_GCR_CPC_BASE_CPCBASE_SHF 17 +#define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x7fff) << 17) +#define CM_GCR_CPC_BASE_CPCEN_SHF 0 +#define CM_GCR_CPC_BASE_CPCEN_MSK (_ULCAST_(0x1) << 0) + +/* GCR_REGn_BASE register fields */ +#define CM_GCR_REGn_BASE_BASEADDR_SHF 16 +#define CM_GCR_REGn_BASE_BASEADDR_MSK (_ULCAST_(0xffff) << 16) + +/* GCR_REGn_MASK register fields */ +#define CM_GCR_REGn_MASK_ADDRMASK_SHF 16 +#define CM_GCR_REGn_MASK_ADDRMASK_MSK (_ULCAST_(0xffff) << 16) +#define CM_GCR_REGn_MASK_CCAOVR_SHF 5 +#define CM_GCR_REGn_MASK_CCAOVR_MSK (_ULCAST_(0x3) << 5) +#define CM_GCR_REGn_MASK_CCAOVREN_SHF 4 +#define CM_GCR_REGn_MASK_CCAOVREN_MSK (_ULCAST_(0x1) << 4) +#define CM_GCR_REGn_MASK_DROPL2_SHF 2 +#define CM_GCR_REGn_MASK_DROPL2_MSK (_ULCAST_(0x1) << 2) +#define CM_GCR_REGn_MASK_CMTGT_SHF 0 +#define CM_GCR_REGn_MASK_CMTGT_MSK (_ULCAST_(0x3) << 0) +#define CM_GCR_REGn_MASK_CMTGT_DISABLED (_ULCAST_(0x0) << 0) +#define CM_GCR_REGn_MASK_CMTGT_MEM (_ULCAST_(0x1) << 0) +#define CM_GCR_REGn_MASK_CMTGT_IOCU0 (_ULCAST_(0x2) << 0) +#define CM_GCR_REGn_MASK_CMTGT_IOCU1 (_ULCAST_(0x3) << 0) + +/* GCR_GIC_STATUS register fields */ +#define CM_GCR_GIC_STATUS_EX_SHF 0 +#define CM_GCR_GIC_STATUS_EX_MSK (_ULCAST_(0x1) << 0) + +/* GCR_CPC_STATUS register fields */ +#define CM_GCR_CPC_STATUS_EX_SHF 0 +#define CM_GCR_CPC_STATUS_EX_MSK (_ULCAST_(0x1) << 0) + +/* GCR_Cx_COHERENCE register fields */ +#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF 0 +#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK (_ULCAST_(0xff) << 0) + +/* GCR_Cx_CONFIG register fields */ +#define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF 10 +#define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK (_ULCAST_(0x3) << 10) +#define CM_GCR_Cx_CONFIG_PVPE_SHF 0 +#define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x1ff) << 0) + +/* GCR_Cx_OTHER register fields */ +#define CM_GCR_Cx_OTHER_CORENUM_SHF 16 +#define CM_GCR_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xffff) << 16) + +/* GCR_Cx_RESET_BASE register fields */ +#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_SHF 12 +#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_MSK (_ULCAST_(0xfffff) << 12) + +/* GCR_Cx_RESET_EXT_BASE register fields */ +#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_SHF 31 +#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_MSK (_ULCAST_(0x1) << 31) +#define CM_GCR_Cx_RESET_EXT_BASE_UEB_SHF 30 +#define CM_GCR_Cx_RESET_EXT_BASE_UEB_MSK (_ULCAST_(0x1) << 30) +#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_SHF 20 +#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_MSK (_ULCAST_(0xff) << 20) +#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_SHF 1 +#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_MSK (_ULCAST_(0x7f) << 1) +#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_SHF 0 +#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK (_ULCAST_(0x1) << 0) + +/** + * mips_cm_numcores - return the number of cores present in the system + * + * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or + * zero if no Coherence Manager is present. + */ +static inline unsigned mips_cm_numcores(void) +{ + if (!mips_cm_present()) + return 0; + + return ((read_gcr_config() & CM_GCR_CONFIG_PCORES_MSK) + >> CM_GCR_CONFIG_PCORES_SHF) + 1; +} + +/** + * mips_cm_numiocu - return the number of IOCUs present in the system + * + * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero + * if no Coherence Manager is present. + */ +static inline unsigned mips_cm_numiocu(void) +{ + if (!mips_cm_present()) + return 0; + + return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU_MSK) + >> CM_GCR_CONFIG_NUMIOCU_SHF; +} + +/** + * mips_cm_l2sync - perform an L2-only sync operation + * + * If an L2-only sync region is present in the system then this function + * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV. + */ +static inline int mips_cm_l2sync(void) +{ + if (!mips_cm_has_l2sync()) + return -ENODEV; + + writel(0, mips_cm_l2sync_base); + return 0; +} + +#endif /* __MIPS_ASM_MIPS_CM_H__ */ diff --git a/arch/mips/include/asm/mips-cpc.h b/arch/mips/include/asm/mips-cpc.h new file mode 100644 index 00000000000..e139a534e0f --- /dev/null +++ b/arch/mips/include/asm/mips-cpc.h @@ -0,0 +1,182 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton <paul.burton@imgtec.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MIPS_ASM_MIPS_CPC_H__ +#define __MIPS_ASM_MIPS_CPC_H__ + +#include <linux/io.h> +#include <linux/types.h> + +/* The base address of the CPC registers */ +extern void __iomem *mips_cpc_base; + +/** + * mips_cpc_default_phys_base - retrieve the default physical base address of + * the CPC + * + * Returns the default physical base address of the Cluster Power Controller + * memory mapped registers. This is platform dependant & must therefore be + * implemented per-platform. + */ +extern phys_t mips_cpc_default_phys_base(void); + +/** + * mips_cpc_phys_base - retrieve the physical base address of the CPC + * + * This function returns the physical base address of the Cluster Power + * Controller memory mapped registers, or 0 if no Cluster Power Controller + * is present. It may be overriden by individual platforms which determine + * this address in a different way. + */ +extern phys_t __weak mips_cpc_phys_base(void); + +/** + * mips_cpc_probe - probe for a Cluster Power Controller + * + * Attempt to detect the presence of a Cluster Power Controller. Returns 0 if + * a CPC is successfully detected, else -errno. + */ +#ifdef CONFIG_MIPS_CPC +extern int mips_cpc_probe(void); +#else +static inline int mips_cpc_probe(void) +{ + return -ENODEV; +} +#endif + +/** + * mips_cpc_present - determine whether a Cluster Power Controller is present + * + * Returns true if a CPC is present in the system, else false. + */ +static inline bool mips_cpc_present(void) +{ +#ifdef CONFIG_MIPS_CPC + return mips_cpc_base != NULL; +#else + return false; +#endif +} + +/* Offsets from the CPC base address to various control blocks */ +#define MIPS_CPC_GCB_OFS 0x0000 +#define MIPS_CPC_CLCB_OFS 0x2000 +#define MIPS_CPC_COCB_OFS 0x4000 + +/* Macros to ease the creation of register access functions */ +#define BUILD_CPC_R_(name, off) \ +static inline u32 *addr_cpc_##name(void) \ +{ \ + return (u32 *)(mips_cpc_base + (off)); \ +} \ + \ +static inline u32 read_cpc_##name(void) \ +{ \ + return __raw_readl(mips_cpc_base + (off)); \ +} + +#define BUILD_CPC__W(name, off) \ +static inline void write_cpc_##name(u32 value) \ +{ \ + __raw_writel(value, mips_cpc_base + (off)); \ +} + +#define BUILD_CPC_RW(name, off) \ + BUILD_CPC_R_(name, off) \ + BUILD_CPC__W(name, off) + +#define BUILD_CPC_Cx_R_(name, off) \ + BUILD_CPC_R_(cl_##name, MIPS_CPC_CLCB_OFS + (off)) \ + BUILD_CPC_R_(co_##name, MIPS_CPC_COCB_OFS + (off)) + +#define BUILD_CPC_Cx__W(name, off) \ + BUILD_CPC__W(cl_##name, MIPS_CPC_CLCB_OFS + (off)) \ + BUILD_CPC__W(co_##name, MIPS_CPC_COCB_OFS + (off)) + +#define BUILD_CPC_Cx_RW(name, off) \ + BUILD_CPC_Cx_R_(name, off) \ + BUILD_CPC_Cx__W(name, off) + +/* GCB register accessor functions */ +BUILD_CPC_RW(access, MIPS_CPC_GCB_OFS + 0x00) +BUILD_CPC_RW(seqdel, MIPS_CPC_GCB_OFS + 0x08) +BUILD_CPC_RW(rail, MIPS_CPC_GCB_OFS + 0x10) +BUILD_CPC_RW(resetlen, MIPS_CPC_GCB_OFS + 0x18) +BUILD_CPC_R_(revision, MIPS_CPC_GCB_OFS + 0x20) + +/* Core Local & Core Other accessor functions */ +BUILD_CPC_Cx_RW(cmd, 0x00) +BUILD_CPC_Cx_RW(stat_conf, 0x08) +BUILD_CPC_Cx_RW(other, 0x10) + +/* CPC_Cx_CMD register fields */ +#define CPC_Cx_CMD_SHF 0 +#define CPC_Cx_CMD_MSK (_ULCAST_(0xf) << 0) +#define CPC_Cx_CMD_CLOCKOFF (_ULCAST_(0x1) << 0) +#define CPC_Cx_CMD_PWRDOWN (_ULCAST_(0x2) << 0) +#define CPC_Cx_CMD_PWRUP (_ULCAST_(0x3) << 0) +#define CPC_Cx_CMD_RESET (_ULCAST_(0x4) << 0) + +/* CPC_Cx_STAT_CONF register fields */ +#define CPC_Cx_STAT_CONF_PWRUPE_SHF 23 +#define CPC_Cx_STAT_CONF_PWRUPE_MSK (_ULCAST_(0x1) << 23) +#define CPC_Cx_STAT_CONF_SEQSTATE_SHF 19 +#define CPC_Cx_STAT_CONF_SEQSTATE_MSK (_ULCAST_(0xf) << 19) +#define CPC_Cx_STAT_CONF_SEQSTATE_D0 (_ULCAST_(0x0) << 19) +#define CPC_Cx_STAT_CONF_SEQSTATE_U0 (_ULCAST_(0x1) << 19) +#define CPC_Cx_STAT_CONF_SEQSTATE_U1 (_ULCAST_(0x2) << 19) +#define CPC_Cx_STAT_CONF_SEQSTATE_U2 (_ULCAST_(0x3) << 19) +#define CPC_Cx_STAT_CONF_SEQSTATE_U3 (_ULCAST_(0x4) << 19) +#define CPC_Cx_STAT_CONF_SEQSTATE_U4 (_ULCAST_(0x5) << 19) +#define CPC_Cx_STAT_CONF_SEQSTATE_U5 (_ULCAST_(0x6) << 19) +#define CPC_Cx_STAT_CONF_SEQSTATE_U6 (_ULCAST_(0x7) << 19) +#define CPC_Cx_STAT_CONF_SEQSTATE_D1 (_ULCAST_(0x8) << 19) +#define CPC_Cx_STAT_CONF_SEQSTATE_D3 (_ULCAST_(0x9) << 19) +#define CPC_Cx_STAT_CONF_SEQSTATE_D2 (_ULCAST_(0xa) << 19) +#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_SHF 17 +#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_MSK (_ULCAST_(0x1) << 17) +#define CPC_Cx_STAT_CONF_PWRDN_IMPL_SHF 16 +#define CPC_Cx_STAT_CONF_PWRDN_IMPL_MSK (_ULCAST_(0x1) << 16) +#define CPC_Cx_STAT_CONF_EJTAG_PROBE_SHF 15 +#define CPC_Cx_STAT_CONF_EJTAG_PROBE_MSK (_ULCAST_(0x1) << 15) + +/* CPC_Cx_OTHER register fields */ +#define CPC_Cx_OTHER_CORENUM_SHF 16 +#define CPC_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xff) << 16) + +#ifdef CONFIG_MIPS_CPC + +/** + * mips_cpc_lock_other - lock access to another core + * core: the other core to be accessed + * + * Call before operating upon a core via the 'other' register region in + * order to prevent the region being moved during access. Must be followed + * by a call to mips_cpc_unlock_other. + */ +extern void mips_cpc_lock_other(unsigned int core); + +/** + * mips_cpc_unlock_other - unlock access to another core + * + * Call after operating upon another core via the 'other' register region. + * Must be called after mips_cpc_lock_other. + */ +extern void mips_cpc_unlock_other(void); + +#else /* !CONFIG_MIPS_CPC */ + +static inline void mips_cpc_lock_other(unsigned int core) { } +static inline void mips_cpc_unlock_other(void) { } + +#endif /* !CONFIG_MIPS_CPC */ + +#endif /* __MIPS_ASM_MIPS_CPC_H__ */ diff --git a/arch/mips/include/asm/mips_machine.h b/arch/mips/include/asm/mips_machine.h index 363bb352c7f..9d00aebe984 100644 --- a/arch/mips/include/asm/mips_machine.h +++ b/arch/mips/include/asm/mips_machine.h @@ -42,13 +42,9 @@ extern long __mips_machines_end; #ifdef CONFIG_MIPS_MACHINE int mips_machtype_setup(char *id) __init; void mips_machine_setup(void) __init; -void mips_set_machine_name(const char *name) __init; -char *mips_get_machine_name(void); #else static inline int mips_machtype_setup(char *id) { return 1; } static inline void mips_machine_setup(void) { } -static inline void mips_set_machine_name(const char *name) { } -static inline char *mips_get_machine_name(void) { return NULL; } #endif /* CONFIG_MIPS_MACHINE */ #endif /* __ASM_MIPS_MACHINE_H */ diff --git a/arch/mips/include/asm/mips_mt.h b/arch/mips/include/asm/mips_mt.h index ac7935203f8..f6ba004a771 100644 --- a/arch/mips/include/asm/mips_mt.h +++ b/arch/mips/include/asm/mips_mt.h @@ -1,7 +1,6 @@ /* - * Definitions and decalrations for MIPS MT support - * that are common between SMTC, VSMP, and/or AP/SP - * kernel models. + * Definitions and decalrations for MIPS MT support that are common between + * the VSMP, and AP/SP kernel models. */ #ifndef __ASM_MIPS_MT_H #define __ASM_MIPS_MT_H @@ -18,7 +17,12 @@ extern cpumask_t mt_fpu_cpumask; extern unsigned long mt_fpemul_threshold; extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value); + +#ifdef CONFIG_MIPS_MT extern void mips_mt_set_cpuoptions(void); +#else +static inline void mips_mt_set_cpuoptions(void) { } +#endif struct class; extern struct class *mt_class; diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h index 5b3cb8553e9..5f8052ce43b 100644 --- a/arch/mips/include/asm/mipsmtregs.h +++ b/arch/mips/include/asm/mipsmtregs.h @@ -36,6 +36,8 @@ #define read_c0_tcbind() __read_32bit_c0_register($2, 2) +#define write_c0_tchalt(val) __write_32bit_c0_register($2, 4, val) + #define read_c0_tccontext() __read_32bit_c0_register($2, 5) #define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val) @@ -176,6 +178,17 @@ #ifndef __ASSEMBLY__ +static inline unsigned core_nvpes(void) +{ + unsigned conf0; + + if (!cpu_has_mipsmt) + return 1; + + conf0 = read_c0_mvpconf0(); + return ((conf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; +} + static inline unsigned int dvpe(void) { int res = 0; @@ -270,14 +283,14 @@ static inline void ehb(void) #define mftc0(rt,sel) \ ({ \ - unsigned long __res; \ + unsigned long __res; \ \ __asm__ __volatile__( \ " .set push \n" \ " .set mips32r2 \n" \ " .set noat \n" \ - " # mftc0 $1, $" #rt ", " #sel " \n" \ - " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \ + " # mftc0 $1, $" #rt ", " #sel " \n" \ + " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \ " move %0, $1 \n" \ " .set pop \n" \ : "=r" (__res)); \ @@ -334,7 +347,7 @@ do { \ " .set noat \n" \ " move $1, %0 \n" \ " # mttc0 %0," #rd ", " #sel " \n" \ - " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \ + " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \ " .set pop \n" \ : \ : "r" (v)); \ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 7e4e6f8fab3..98e9754a4b6 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -14,6 +14,7 @@ #define _ASM_MIPSREGS_H #include <linux/linkage.h> +#include <linux/types.h> #include <asm/hazards.h> #include <asm/war.h> @@ -123,16 +124,16 @@ * Status Register Values */ -#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ -#define FPU_CSR_COND 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ -#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ -#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ -#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ -#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ -#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ -#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ +#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ +#define FPU_CSR_COND 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ +#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ +#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ +#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ +#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ +#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ +#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ /* * Bits 18 - 20 of the FPU Status Register will be read as 0, @@ -145,34 +146,34 @@ * E the exception enable * S the sticky/flag bit */ -#define FPU_CSR_ALL_X 0x0003f000 -#define FPU_CSR_UNI_X 0x00020000 -#define FPU_CSR_INV_X 0x00010000 -#define FPU_CSR_DIV_X 0x00008000 -#define FPU_CSR_OVF_X 0x00004000 -#define FPU_CSR_UDF_X 0x00002000 -#define FPU_CSR_INE_X 0x00001000 - -#define FPU_CSR_ALL_E 0x00000f80 -#define FPU_CSR_INV_E 0x00000800 -#define FPU_CSR_DIV_E 0x00000400 -#define FPU_CSR_OVF_E 0x00000200 -#define FPU_CSR_UDF_E 0x00000100 -#define FPU_CSR_INE_E 0x00000080 - -#define FPU_CSR_ALL_S 0x0000007c -#define FPU_CSR_INV_S 0x00000040 -#define FPU_CSR_DIV_S 0x00000020 -#define FPU_CSR_OVF_S 0x00000010 -#define FPU_CSR_UDF_S 0x00000008 -#define FPU_CSR_INE_S 0x00000004 +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x00020000 +#define FPU_CSR_INV_X 0x00010000 +#define FPU_CSR_DIV_X 0x00008000 +#define FPU_CSR_OVF_X 0x00004000 +#define FPU_CSR_UDF_X 0x00002000 +#define FPU_CSR_INE_X 0x00001000 + +#define FPU_CSR_ALL_E 0x00000f80 +#define FPU_CSR_INV_E 0x00000800 +#define FPU_CSR_DIV_E 0x00000400 +#define FPU_CSR_OVF_E 0x00000200 +#define FPU_CSR_UDF_E 0x00000100 +#define FPU_CSR_INE_E 0x00000080 + +#define FPU_CSR_ALL_S 0x0000007c +#define FPU_CSR_INV_S 0x00000040 +#define FPU_CSR_DIV_S 0x00000020 +#define FPU_CSR_OVF_S 0x00000010 +#define FPU_CSR_UDF_S 0x00000008 +#define FPU_CSR_INE_S 0x00000004 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ #define FPU_CSR_RM 0x00000003 -#define FPU_CSR_RN 0x0 /* nearest */ -#define FPU_CSR_RZ 0x1 /* towards zero */ -#define FPU_CSR_RU 0x2 /* towards +Infinity */ -#define FPU_CSR_RD 0x3 /* towards -Infinity */ +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ /* @@ -214,15 +215,15 @@ * Default page size for a given kernel configuration */ #ifdef CONFIG_PAGE_SIZE_4KB -#define PM_DEFAULT_MASK PM_4K +#define PM_DEFAULT_MASK PM_4K #elif defined(CONFIG_PAGE_SIZE_8KB) -#define PM_DEFAULT_MASK PM_8K +#define PM_DEFAULT_MASK PM_8K #elif defined(CONFIG_PAGE_SIZE_16KB) -#define PM_DEFAULT_MASK PM_16K +#define PM_DEFAULT_MASK PM_16K #elif defined(CONFIG_PAGE_SIZE_32KB) -#define PM_DEFAULT_MASK PM_32K +#define PM_DEFAULT_MASK PM_32K #elif defined(CONFIG_PAGE_SIZE_64KB) -#define PM_DEFAULT_MASK PM_64K +#define PM_DEFAULT_MASK PM_64K #else #error Bad page size configuration! #endif @@ -260,34 +261,34 @@ /* * PageGrain bits */ -#define PG_RIE (_ULCAST_(1) << 31) -#define PG_XIE (_ULCAST_(1) << 30) -#define PG_ELPA (_ULCAST_(1) << 29) -#define PG_ESP (_ULCAST_(1) << 28) +#define PG_RIE (_ULCAST_(1) << 31) +#define PG_XIE (_ULCAST_(1) << 30) +#define PG_ELPA (_ULCAST_(1) << 29) +#define PG_ESP (_ULCAST_(1) << 28) /* * R4x00 interrupt enable / cause bits */ -#define IE_SW0 (_ULCAST_(1) << 8) -#define IE_SW1 (_ULCAST_(1) << 9) -#define IE_IRQ0 (_ULCAST_(1) << 10) -#define IE_IRQ1 (_ULCAST_(1) << 11) -#define IE_IRQ2 (_ULCAST_(1) << 12) -#define IE_IRQ3 (_ULCAST_(1) << 13) -#define IE_IRQ4 (_ULCAST_(1) << 14) -#define IE_IRQ5 (_ULCAST_(1) << 15) +#define IE_SW0 (_ULCAST_(1) << 8) +#define IE_SW1 (_ULCAST_(1) << 9) +#define IE_IRQ0 (_ULCAST_(1) << 10) +#define IE_IRQ1 (_ULCAST_(1) << 11) +#define IE_IRQ2 (_ULCAST_(1) << 12) +#define IE_IRQ3 (_ULCAST_(1) << 13) +#define IE_IRQ4 (_ULCAST_(1) << 14) +#define IE_IRQ5 (_ULCAST_(1) << 15) /* * R4x00 interrupt cause bits */ -#define C_SW0 (_ULCAST_(1) << 8) -#define C_SW1 (_ULCAST_(1) << 9) -#define C_IRQ0 (_ULCAST_(1) << 10) -#define C_IRQ1 (_ULCAST_(1) << 11) -#define C_IRQ2 (_ULCAST_(1) << 12) -#define C_IRQ3 (_ULCAST_(1) << 13) -#define C_IRQ4 (_ULCAST_(1) << 14) -#define C_IRQ5 (_ULCAST_(1) << 15) +#define C_SW0 (_ULCAST_(1) << 8) +#define C_SW1 (_ULCAST_(1) << 9) +#define C_IRQ0 (_ULCAST_(1) << 10) +#define C_IRQ1 (_ULCAST_(1) << 11) +#define C_IRQ2 (_ULCAST_(1) << 12) +#define C_IRQ3 (_ULCAST_(1) << 13) +#define C_IRQ4 (_ULCAST_(1) << 14) +#define C_IRQ5 (_ULCAST_(1) << 15) /* * Bitfields in the R4xx0 cp0 status register @@ -301,7 +302,7 @@ # define KSU_KERNEL 0x00000000 #define ST0_UX 0x00000020 #define ST0_SX 0x00000040 -#define ST0_KX 0x00000080 +#define ST0_KX 0x00000080 #define ST0_DE 0x00010000 #define ST0_CE 0x00020000 @@ -315,7 +316,7 @@ /* * Bitfields in the R[23]000 cp0 status register. */ -#define ST0_IEC 0x00000001 +#define ST0_IEC 0x00000001 #define ST0_KUC 0x00000002 #define ST0_IEP 0x00000004 #define ST0_KUP 0x00000008 @@ -329,7 +330,7 @@ /* * Bits specific to the R4640/R4650 */ -#define ST0_UM (_ULCAST_(1) << 4) +#define ST0_UM (_ULCAST_(1) << 4) #define ST0_IL (_ULCAST_(1) << 23) #define ST0_DL (_ULCAST_(1) << 24) @@ -343,22 +344,22 @@ */ #define TX39_CONF_ICS_SHIFT 19 #define TX39_CONF_ICS_MASK 0x00380000 -#define TX39_CONF_ICS_1KB 0x00000000 -#define TX39_CONF_ICS_2KB 0x00080000 -#define TX39_CONF_ICS_4KB 0x00100000 -#define TX39_CONF_ICS_8KB 0x00180000 -#define TX39_CONF_ICS_16KB 0x00200000 +#define TX39_CONF_ICS_1KB 0x00000000 +#define TX39_CONF_ICS_2KB 0x00080000 +#define TX39_CONF_ICS_4KB 0x00100000 +#define TX39_CONF_ICS_8KB 0x00180000 +#define TX39_CONF_ICS_16KB 0x00200000 #define TX39_CONF_DCS_SHIFT 16 #define TX39_CONF_DCS_MASK 0x00070000 -#define TX39_CONF_DCS_1KB 0x00000000 -#define TX39_CONF_DCS_2KB 0x00010000 -#define TX39_CONF_DCS_4KB 0x00020000 -#define TX39_CONF_DCS_8KB 0x00030000 -#define TX39_CONF_DCS_16KB 0x00040000 - -#define TX39_CONF_CWFON 0x00004000 -#define TX39_CONF_WBON 0x00002000 +#define TX39_CONF_DCS_1KB 0x00000000 +#define TX39_CONF_DCS_2KB 0x00010000 +#define TX39_CONF_DCS_4KB 0x00020000 +#define TX39_CONF_DCS_8KB 0x00030000 +#define TX39_CONF_DCS_16KB 0x00040000 + +#define TX39_CONF_CWFON 0x00004000 +#define TX39_CONF_WBON 0x00002000 #define TX39_CONF_RF_SHIFT 10 #define TX39_CONF_RF_MASK 0x00000c00 #define TX39_CONF_DOZE 0x00000200 @@ -375,38 +376,38 @@ * Status register bits available in all MIPS CPUs. */ #define ST0_IM 0x0000ff00 -#define STATUSB_IP0 8 -#define STATUSF_IP0 (_ULCAST_(1) << 8) -#define STATUSB_IP1 9 -#define STATUSF_IP1 (_ULCAST_(1) << 9) -#define STATUSB_IP2 10 -#define STATUSF_IP2 (_ULCAST_(1) << 10) -#define STATUSB_IP3 11 -#define STATUSF_IP3 (_ULCAST_(1) << 11) -#define STATUSB_IP4 12 -#define STATUSF_IP4 (_ULCAST_(1) << 12) -#define STATUSB_IP5 13 -#define STATUSF_IP5 (_ULCAST_(1) << 13) -#define STATUSB_IP6 14 -#define STATUSF_IP6 (_ULCAST_(1) << 14) -#define STATUSB_IP7 15 -#define STATUSF_IP7 (_ULCAST_(1) << 15) -#define STATUSB_IP8 0 -#define STATUSF_IP8 (_ULCAST_(1) << 0) -#define STATUSB_IP9 1 -#define STATUSF_IP9 (_ULCAST_(1) << 1) -#define STATUSB_IP10 2 -#define STATUSF_IP10 (_ULCAST_(1) << 2) -#define STATUSB_IP11 3 -#define STATUSF_IP11 (_ULCAST_(1) << 3) -#define STATUSB_IP12 4 -#define STATUSF_IP12 (_ULCAST_(1) << 4) -#define STATUSB_IP13 5 -#define STATUSF_IP13 (_ULCAST_(1) << 5) -#define STATUSB_IP14 6 -#define STATUSF_IP14 (_ULCAST_(1) << 6) -#define STATUSB_IP15 7 -#define STATUSF_IP15 (_ULCAST_(1) << 7) +#define STATUSB_IP0 8 +#define STATUSF_IP0 (_ULCAST_(1) << 8) +#define STATUSB_IP1 9 +#define STATUSF_IP1 (_ULCAST_(1) << 9) +#define STATUSB_IP2 10 +#define STATUSF_IP2 (_ULCAST_(1) << 10) +#define STATUSB_IP3 11 +#define STATUSF_IP3 (_ULCAST_(1) << 11) +#define STATUSB_IP4 12 +#define STATUSF_IP4 (_ULCAST_(1) << 12) +#define STATUSB_IP5 13 +#define STATUSF_IP5 (_ULCAST_(1) << 13) +#define STATUSB_IP6 14 +#define STATUSF_IP6 (_ULCAST_(1) << 14) +#define STATUSB_IP7 15 +#define STATUSF_IP7 (_ULCAST_(1) << 15) +#define STATUSB_IP8 0 +#define STATUSF_IP8 (_ULCAST_(1) << 0) +#define STATUSB_IP9 1 +#define STATUSF_IP9 (_ULCAST_(1) << 1) +#define STATUSB_IP10 2 +#define STATUSF_IP10 (_ULCAST_(1) << 2) +#define STATUSB_IP11 3 +#define STATUSF_IP11 (_ULCAST_(1) << 3) +#define STATUSB_IP12 4 +#define STATUSF_IP12 (_ULCAST_(1) << 4) +#define STATUSB_IP13 5 +#define STATUSF_IP13 (_ULCAST_(1) << 5) +#define STATUSB_IP14 6 +#define STATUSF_IP14 (_ULCAST_(1) << 6) +#define STATUSB_IP15 7 +#define STATUSF_IP15 (_ULCAST_(1) << 7) #define ST0_CH 0x00040000 #define ST0_NMI 0x00080000 #define ST0_SR 0x00100000 @@ -436,36 +437,36 @@ * * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. */ -#define CAUSEB_EXCCODE 2 -#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) -#define CAUSEB_IP 8 -#define CAUSEF_IP (_ULCAST_(255) << 8) -#define CAUSEB_IP0 8 -#define CAUSEF_IP0 (_ULCAST_(1) << 8) -#define CAUSEB_IP1 9 -#define CAUSEF_IP1 (_ULCAST_(1) << 9) -#define CAUSEB_IP2 10 -#define CAUSEF_IP2 (_ULCAST_(1) << 10) -#define CAUSEB_IP3 11 -#define CAUSEF_IP3 (_ULCAST_(1) << 11) -#define CAUSEB_IP4 12 -#define CAUSEF_IP4 (_ULCAST_(1) << 12) -#define CAUSEB_IP5 13 -#define CAUSEF_IP5 (_ULCAST_(1) << 13) -#define CAUSEB_IP6 14 -#define CAUSEF_IP6 (_ULCAST_(1) << 14) -#define CAUSEB_IP7 15 -#define CAUSEF_IP7 (_ULCAST_(1) << 15) -#define CAUSEB_IV 23 -#define CAUSEF_IV (_ULCAST_(1) << 23) -#define CAUSEB_PCI 26 -#define CAUSEF_PCI (_ULCAST_(1) << 26) -#define CAUSEB_CE 28 -#define CAUSEF_CE (_ULCAST_(3) << 28) -#define CAUSEB_TI 30 -#define CAUSEF_TI (_ULCAST_(1) << 30) -#define CAUSEB_BD 31 -#define CAUSEF_BD (_ULCAST_(1) << 31) +#define CAUSEB_EXCCODE 2 +#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) +#define CAUSEB_IP 8 +#define CAUSEF_IP (_ULCAST_(255) << 8) +#define CAUSEB_IP0 8 +#define CAUSEF_IP0 (_ULCAST_(1) << 8) +#define CAUSEB_IP1 9 +#define CAUSEF_IP1 (_ULCAST_(1) << 9) +#define CAUSEB_IP2 10 +#define CAUSEF_IP2 (_ULCAST_(1) << 10) +#define CAUSEB_IP3 11 +#define CAUSEF_IP3 (_ULCAST_(1) << 11) +#define CAUSEB_IP4 12 +#define CAUSEF_IP4 (_ULCAST_(1) << 12) +#define CAUSEB_IP5 13 +#define CAUSEF_IP5 (_ULCAST_(1) << 13) +#define CAUSEB_IP6 14 +#define CAUSEF_IP6 (_ULCAST_(1) << 14) +#define CAUSEB_IP7 15 +#define CAUSEF_IP7 (_ULCAST_(1) << 15) +#define CAUSEB_IV 23 +#define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEB_PCI 26 +#define CAUSEF_PCI (_ULCAST_(1) << 26) +#define CAUSEB_CE 28 +#define CAUSEF_CE (_ULCAST_(3) << 28) +#define CAUSEB_TI 30 +#define CAUSEF_TI (_ULCAST_(1) << 30) +#define CAUSEB_BD 31 +#define CAUSEF_BD (_ULCAST_(1) << 31) /* * Bits in the coprocessor 0 config register. @@ -483,11 +484,11 @@ #define CONF_BE (_ULCAST_(1) << 15) /* Bits common to various processors. */ -#define CONF_CU (_ULCAST_(1) << 3) -#define CONF_DB (_ULCAST_(1) << 4) -#define CONF_IB (_ULCAST_(1) << 5) -#define CONF_DC (_ULCAST_(7) << 6) -#define CONF_IC (_ULCAST_(7) << 9) +#define CONF_CU (_ULCAST_(1) << 3) +#define CONF_DB (_ULCAST_(1) << 4) +#define CONF_IB (_ULCAST_(1) << 5) +#define CONF_DC (_ULCAST_(7) << 6) +#define CONF_IC (_ULCAST_(7) << 9) #define CONF_EB (_ULCAST_(1) << 13) #define CONF_EM (_ULCAST_(1) << 14) #define CONF_SM (_ULCAST_(1) << 16) @@ -497,29 +498,29 @@ #define CONF_EC (_ULCAST_(7) << 28) #define CONF_CM (_ULCAST_(1) << 31) -/* Bits specific to the R4xx0. */ +/* Bits specific to the R4xx0. */ #define R4K_CONF_SW (_ULCAST_(1) << 20) #define R4K_CONF_SS (_ULCAST_(1) << 21) #define R4K_CONF_SB (_ULCAST_(3) << 22) -/* Bits specific to the R5000. */ +/* Bits specific to the R5000. */ #define R5K_CONF_SE (_ULCAST_(1) << 12) #define R5K_CONF_SS (_ULCAST_(3) << 20) -/* Bits specific to the RM7000. */ -#define RM7K_CONF_SE (_ULCAST_(1) << 3) +/* Bits specific to the RM7000. */ +#define RM7K_CONF_SE (_ULCAST_(1) << 3) #define RM7K_CONF_TE (_ULCAST_(1) << 12) #define RM7K_CONF_CLK (_ULCAST_(1) << 16) #define RM7K_CONF_TC (_ULCAST_(1) << 17) #define RM7K_CONF_SI (_ULCAST_(3) << 20) #define RM7K_CONF_SC (_ULCAST_(1) << 31) -/* Bits specific to the R10000. */ -#define R10K_CONF_DN (_ULCAST_(3) << 3) -#define R10K_CONF_CT (_ULCAST_(1) << 5) -#define R10K_CONF_PE (_ULCAST_(1) << 6) -#define R10K_CONF_PM (_ULCAST_(3) << 7) -#define R10K_CONF_EC (_ULCAST_(15)<< 9) +/* Bits specific to the R10000. */ +#define R10K_CONF_DN (_ULCAST_(3) << 3) +#define R10K_CONF_CT (_ULCAST_(1) << 5) +#define R10K_CONF_PE (_ULCAST_(1) << 6) +#define R10K_CONF_PM (_ULCAST_(3) << 7) +#define R10K_CONF_EC (_ULCAST_(15)<< 9) #define R10K_CONF_SB (_ULCAST_(1) << 13) #define R10K_CONF_SK (_ULCAST_(1) << 14) #define R10K_CONF_SS (_ULCAST_(7) << 16) @@ -527,14 +528,14 @@ #define R10K_CONF_DC (_ULCAST_(7) << 26) #define R10K_CONF_IC (_ULCAST_(7) << 29) -/* Bits specific to the VR41xx. */ +/* Bits specific to the VR41xx. */ #define VR41_CONF_CS (_ULCAST_(1) << 12) #define VR41_CONF_P4K (_ULCAST_(1) << 13) #define VR41_CONF_BP (_ULCAST_(1) << 16) #define VR41_CONF_M16 (_ULCAST_(1) << 20) #define VR41_CONF_AD (_ULCAST_(1) << 23) -/* Bits specific to the R30xx. */ +/* Bits specific to the R30xx. */ #define R30XX_CONF_FDM (_ULCAST_(1) << 19) #define R30XX_CONF_REV (_ULCAST_(1) << 22) #define R30XX_CONF_AC (_ULCAST_(1) << 23) @@ -551,8 +552,8 @@ #define TX49_CONF_HALT (_ULCAST_(1) << 18) #define TX49_CONF_CWFON (_ULCAST_(1) << 27) -/* Bits specific to the MIPS32/64 PRA. */ -#define MIPS_CONF_MT (_ULCAST_(7) << 7) +/* Bits specific to the MIPS32/64 PRA. */ +#define MIPS_CONF_MT (_ULCAST_(7) << 7) #define MIPS_CONF_AR (_ULCAST_(7) << 10) #define MIPS_CONF_AT (_ULCAST_(3) << 13) #define MIPS_CONF_M (_ULCAST_(1) << 31) @@ -560,52 +561,119 @@ /* * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. */ -#define MIPS_CONF1_FP (_ULCAST_(1) << 0) -#define MIPS_CONF1_EP (_ULCAST_(1) << 1) -#define MIPS_CONF1_CA (_ULCAST_(1) << 2) -#define MIPS_CONF1_WR (_ULCAST_(1) << 3) -#define MIPS_CONF1_PC (_ULCAST_(1) << 4) -#define MIPS_CONF1_MD (_ULCAST_(1) << 5) -#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) -#define MIPS_CONF1_DA (_ULCAST_(7) << 7) +#define MIPS_CONF1_FP (_ULCAST_(1) << 0) +#define MIPS_CONF1_EP (_ULCAST_(1) << 1) +#define MIPS_CONF1_CA (_ULCAST_(1) << 2) +#define MIPS_CONF1_WR (_ULCAST_(1) << 3) +#define MIPS_CONF1_PC (_ULCAST_(1) << 4) +#define MIPS_CONF1_MD (_ULCAST_(1) << 5) +#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) +#define MIPS_CONF1_DA_SHF 7 +#define MIPS_CONF1_DA_SZ 3 +#define MIPS_CONF1_DA (_ULCAST_(7) << 7) +#define MIPS_CONF1_DL_SHF 10 +#define MIPS_CONF1_DL_SZ 3 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) +#define MIPS_CONF1_DS_SHF 13 +#define MIPS_CONF1_DS_SZ 3 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) +#define MIPS_CONF1_IA_SHF 16 +#define MIPS_CONF1_IA_SZ 3 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) +#define MIPS_CONF1_IL_SHF 19 +#define MIPS_CONF1_IL_SZ 3 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) +#define MIPS_CONF1_IS_SHF 22 +#define MIPS_CONF1_IS_SZ 3 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) -#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) +#define MIPS_CONF1_TLBS_SHIFT (25) +#define MIPS_CONF1_TLBS_SIZE (6) +#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT) -#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) -#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) -#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) +#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) +#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) +#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) #define MIPS_CONF2_TU (_ULCAST_(7) << 28) -#define MIPS_CONF3_TL (_ULCAST_(1) << 0) -#define MIPS_CONF3_SM (_ULCAST_(1) << 1) -#define MIPS_CONF3_MT (_ULCAST_(1) << 2) -#define MIPS_CONF3_SP (_ULCAST_(1) << 4) -#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) -#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) -#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) +#define MIPS_CONF3_TL (_ULCAST_(1) << 0) +#define MIPS_CONF3_SM (_ULCAST_(1) << 1) +#define MIPS_CONF3_MT (_ULCAST_(1) << 2) +#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3) +#define MIPS_CONF3_SP (_ULCAST_(1) << 4) +#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) +#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) +#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) +#define MIPS_CONF3_ITL (_ULCAST_(1) << 8) +#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9) #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) - +#define MIPS_CONF3_ISA (_ULCAST_(3) << 14) +#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) +#define MIPS_CONF3_MCU (_ULCAST_(1) << 17) +#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18) +#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21) +#define MIPS_CONF3_VZ (_ULCAST_(1) << 23) +#define MIPS_CONF3_PW (_ULCAST_(1) << 24) +#define MIPS_CONF3_SC (_ULCAST_(1) << 25) +#define MIPS_CONF3_BI (_ULCAST_(1) << 26) +#define MIPS_CONF3_BP (_ULCAST_(1) << 27) +#define MIPS_CONF3_MSA (_ULCAST_(1) << 28) +#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29) +#define MIPS_CONF3_BPG (_ULCAST_(1) << 30) + +#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0) #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) +#define MIPS_CONF4_FTLBSETS_SHIFT (0) +#define MIPS_CONF4_FTLBSETS_SHIFT (0) +#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT) +#define MIPS_CONF4_FTLBWAYS_SHIFT (4) +#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT) +#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8) +/* bits 10:8 in FTLB-only configurations */ +#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) +/* bits 12:8 in VTLB-FTLB only configurations */ +#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) +#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14) +#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14) +#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16) +#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24) +#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT) +#define MIPS_CONF4_AE (_ULCAST_(1) << 28) +#define MIPS_CONF4_IE (_ULCAST_(3) << 29) +#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29) + +#define MIPS_CONF5_NF (_ULCAST_(1) << 0) +#define MIPS_CONF5_UFR (_ULCAST_(1) << 2) +#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) +#define MIPS_CONF5_EVA (_ULCAST_(1) << 28) +#define MIPS_CONF5_CV (_ULCAST_(1) << 29) +#define MIPS_CONF5_K (_ULCAST_(1) << 30) #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) +/* proAptiv FTLB on/off bit */ +#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) #define MIPS_CONF7_WII (_ULCAST_(1) << 31) #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) +#define MIPS_CONF7_IAR (_ULCAST_(1) << 10) +#define MIPS_CONF7_AR (_ULCAST_(1) << 16) + +/* EntryHI bit definition */ +#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) + +/* CMGCRBase bit definitions */ +#define MIPS_CMGCRB_BASE 11 +#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) /* * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. @@ -618,10 +686,68 @@ #define MIPS_FPIR_L (_ULCAST_(1) << 21) #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) +/* + * Bits in the MIPS32 Memory Segmentation registers. + */ +#define MIPS_SEGCFG_PA_SHIFT 9 +#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT) +#define MIPS_SEGCFG_AM_SHIFT 4 +#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT) +#define MIPS_SEGCFG_EU_SHIFT 3 +#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT) +#define MIPS_SEGCFG_C_SHIFT 0 +#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT) + +#define MIPS_SEGCFG_UUSK _ULCAST_(7) +#define MIPS_SEGCFG_USK _ULCAST_(5) +#define MIPS_SEGCFG_MUSUK _ULCAST_(4) +#define MIPS_SEGCFG_MUSK _ULCAST_(3) +#define MIPS_SEGCFG_MSK _ULCAST_(2) +#define MIPS_SEGCFG_MK _ULCAST_(1) +#define MIPS_SEGCFG_UK _ULCAST_(0) + #ifndef __ASSEMBLY__ /* - * Functions to access the R10000 performance counters. These are basically + * Macros for handling the ISA mode bit for MIPS16 and microMIPS. + */ +#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \ + defined(CONFIG_SYS_SUPPORTS_MICROMIPS) +#define get_isa16_mode(x) ((x) & 0x1) +#define msk_isa16_mode(x) ((x) & ~0x1) +#define set_isa16_mode(x) do { (x) |= 0x1; } while(0) +#else +#define get_isa16_mode(x) 0 +#define msk_isa16_mode(x) (x) +#define set_isa16_mode(x) do { } while(0) +#endif + +/* + * microMIPS instructions can be 16-bit or 32-bit in length. This + * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. + */ +static inline int mm_insn_16bit(u16 insn) +{ + u16 opcode = (insn >> 10) & 0x7; + + return (opcode >= 1 && opcode <= 3) ? 1 : 0; +} + +/* + * TLB Invalidate Flush + */ +static inline void tlbinvf(void) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set noreorder\n\t" + ".word 0x42000004\n\t" /* tlbinvf */ + ".set pop"); +} + + +/* + * Functions to access the R10000 performance counters. These are basically * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit * performance counter number encoded into bits 1 ... 5 of the instruction. * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware @@ -632,13 +758,13 @@ unsigned int __res; \ __asm__ __volatile__( \ "mfpc\t%0, %1" \ - : "=r" (__res) \ + : "=r" (__res) \ : "i" (counter)); \ \ - __res; \ + __res; \ }) -#define write_r10k_perf_cntr(counter,val) \ +#define write_r10k_perf_cntr(counter,val) \ do { \ __asm__ __volatile__( \ "mtpc\t%0, %1" \ @@ -651,13 +777,13 @@ do { \ unsigned int __res; \ __asm__ __volatile__( \ "mfps\t%0, %1" \ - : "=r" (__res) \ + : "=r" (__res) \ : "i" (counter)); \ \ - __res; \ + __res; \ }) -#define write_r10k_perf_cntl(counter,val) \ +#define write_r10k_perf_cntl(counter,val) \ do { \ __asm__ __volatile__( \ "mtps\t%0, %1" \ @@ -847,20 +973,20 @@ do { \ #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) #define read_c0_userlocal() __read_ulong_c0_register($4, 2) -#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) +#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) #define read_c0_pagemask() __read_32bit_c0_register($5, 0) #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) #define read_c0_pagegrain() __read_32bit_c0_register($5, 1) -#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) +#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) #define read_c0_wired() __read_32bit_c0_register($6, 0) #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) #define read_c0_info() __read_32bit_c0_register($7, 0) -#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ +#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) @@ -888,19 +1014,8 @@ do { \ #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) #define read_c0_status() __read_32bit_c0_register($12, 0) -#ifdef CONFIG_MIPS_MT_SMTC -#define write_c0_status(val) \ -do { \ - __write_32bit_c0_register($12, 0, val); \ - __ehb(); \ -} while (0) -#else -/* - * Legacy non-SMTC code, which may be hazardous - * but which might not support EHB - */ + #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) -#endif /* CONFIG_MIPS_MT_SMTC */ #define read_c0_cause() __read_32bit_c0_register($13, 0) #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) @@ -910,6 +1025,8 @@ do { \ #define read_c0_prid() __read_32bit_c0_register($15, 0) +#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3) + #define read_c0_config() __read_32bit_c0_register($16, 0) #define read_c0_config1() __read_32bit_c0_register($16, 1) #define read_c0_config2() __read_32bit_c0_register($16, 2) @@ -975,7 +1092,7 @@ do { \ #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) #define read_c0_framemask() __read_32bit_c0_register($21, 0) -#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) +#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) #define read_c0_diag() __read_32bit_c0_register($22, 0) #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) @@ -1005,27 +1122,27 @@ do { \ * MIPS32 / MIPS64 performance counters */ #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) -#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) +#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) -#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) +#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) -#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) +#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) -#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) +#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) -#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) +#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) -#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) +#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) -#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) +#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) -#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) +#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) @@ -1033,12 +1150,12 @@ do { \ #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) -#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) +#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) -#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) +#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) #define read_c0_taglo() __read_32bit_c0_register($28, 0) #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) @@ -1074,6 +1191,15 @@ do { \ #define read_c0_ebase() __read_32bit_c0_register($15, 1) #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) +/* MIPSR3 */ +#define read_c0_segctl0() __read_32bit_c0_register($5, 2) +#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val) + +#define read_c0_segctl1() __read_32bit_c0_register($5, 3) +#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val) + +#define read_c0_segctl2() __read_32bit_c0_register($5, 4) +#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val) /* Cavium OCTEON (cnMIPS) */ #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) @@ -1083,9 +1209,9 @@ do { \ #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) -#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) +#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) /* - * The cacheerr registers are not standardized. On OCTEON, they are + * The cacheerr registers are not standardized. On OCTEON, they are * 64 bits wide. */ #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) @@ -1142,294 +1268,406 @@ do { \ /* * Macros to access the floating point coprocessor control registers */ -#define read_32bit_cp1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - /* gas fails to assemble cfc1 for some archs (octeon).*/ \ - ".set\tmips1\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) +#define read_32bit_cp1_register(source) \ +({ \ + int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set reorder \n" \ + " # gas fails to assemble cfc1 for some archs, \n" \ + " # like Octeon. \n" \ + " .set mips1 \n" \ + " cfc1 %0,"STR(source)" \n" \ + " .set pop \n" \ + : "=r" (__res)); \ + __res; \ +}) +#ifdef HAVE_AS_DSP #define rddsp(mask) \ ({ \ - unsigned int __res; \ + unsigned int __dspctl; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # rddsp $1, %x1 \n" \ - " .word 0x7c000cb8 | (%x1 << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__res) \ + " .set push \n" \ + " .set dsp \n" \ + " rddsp %0, %x1 \n" \ + " .set pop \n" \ + : "=r" (__dspctl) \ : "i" (mask)); \ - __res; \ + __dspctl; \ }) #define wrdsp(val, mask) \ do { \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # wrdsp $1, %x1 \n" \ - " .word 0x7c2004f8 | (%x1 << 11) \n" \ - " .set pop \n" \ - : \ + " .set push \n" \ + " .set dsp \n" \ + " wrdsp %0, %x1 \n" \ + " .set pop \n" \ + : \ : "r" (val), "i" (mask)); \ } while (0) -#if 0 /* Need DSP ASE capable assembler ... */ -#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) -#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) -#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) -#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;}) - -#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;}) -#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;}) -#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;}) -#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;}) +#define mflo0() \ +({ \ + long mflo0; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mflo %0, $ac0 \n" \ + " .set pop \n" \ + : "=r" (mflo0)); \ + mflo0; \ +}) -#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x)) -#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x)) -#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x)) -#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x)) +#define mflo1() \ +({ \ + long mflo1; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mflo %0, $ac1 \n" \ + " .set pop \n" \ + : "=r" (mflo1)); \ + mflo1; \ +}) -#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x)) -#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x)) -#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x)) -#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x)) +#define mflo2() \ +({ \ + long mflo2; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mflo %0, $ac2 \n" \ + " .set pop \n" \ + : "=r" (mflo2)); \ + mflo2; \ +}) -#else +#define mflo3() \ +({ \ + long mflo3; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mflo %0, $ac3 \n" \ + " .set pop \n" \ + : "=r" (mflo3)); \ + mflo3; \ +}) #define mfhi0() \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac0 \n" \ - " .word 0x00000810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + long mfhi0; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mfhi %0, $ac0 \n" \ + " .set pop \n" \ + : "=r" (mfhi0)); \ + mfhi0; \ }) #define mfhi1() \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac1 \n" \ - " .word 0x00200810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + long mfhi1; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mfhi %0, $ac1 \n" \ + " .set pop \n" \ + : "=r" (mfhi1)); \ + mfhi1; \ }) #define mfhi2() \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac2 \n" \ - " .word 0x00400810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + long mfhi2; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mfhi %0, $ac2 \n" \ + " .set pop \n" \ + : "=r" (mfhi2)); \ + mfhi2; \ }) #define mfhi3() \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac3 \n" \ - " .word 0x00600810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + long mfhi3; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mfhi %0, $ac3 \n" \ + " .set pop \n" \ + : "=r" (mfhi3)); \ + mfhi3; \ }) -#define mflo0() \ + +#define mtlo0(x) \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac0 \n" \ - " .word 0x00000812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mtlo %0, $ac0 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ }) -#define mflo1() \ +#define mtlo1(x) \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac1 \n" \ - " .word 0x00200812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mtlo %0, $ac1 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ }) -#define mflo2() \ +#define mtlo2(x) \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac2 \n" \ - " .word 0x00400812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mtlo %0, $ac2 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ }) -#define mflo3() \ +#define mtlo3(x) \ ({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac3 \n" \ - " .word 0x00600812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mtlo %0, $ac3 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ }) #define mthi0(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac0 \n" \ - " .word 0x00200011 \n" \ - " .set pop \n" \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mthi %0, $ac0 \n" \ + " .set pop \n" \ : \ : "r" (x)); \ -} while (0) +}) #define mthi1(x) \ -do { \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mthi %0, $ac1 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) + +#define mthi2(x) \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mthi %0, $ac2 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) + +#define mthi3(x) \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mthi %0, $ac3 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) + +#else + +#ifdef CONFIG_CPU_MICROMIPS +#define rddsp(mask) \ +({ \ + unsigned int __res; \ + \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac1 \n" \ - " .word 0x00200811 \n" \ + " # rddsp $1, %x1 \n" \ + " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ + " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) -#define mthi2(x) \ +#define wrdsp(val, mask) \ do { \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mthi $1, $ac2 \n" \ - " .word 0x00201011 \n" \ + " # wrdsp $1, %x1 \n" \ + " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ + " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ " .set pop \n" \ : \ - : "r" (x)); \ + : "r" (val), "i" (mask)); \ } while (0) -#define mthi3(x) \ -do { \ +#define _umips_dsp_mfxxx(ins) \ +({ \ + unsigned long __treg; \ + \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac3 \n" \ - " .word 0x00201811 \n" \ + " .hword 0x0001 \n" \ + " .hword %x1 \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__treg) \ + : "i" (ins)); \ + __treg; \ +}) -#define mtlo0(x) \ +#define _umips_dsp_mtxxx(val, ins) \ do { \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mtlo $1, $ac0 \n" \ - " .word 0x00200013 \n" \ + " .hword 0x0001 \n" \ + " .hword %x1 \n" \ " .set pop \n" \ : \ - : "r" (x)); \ + : "r" (val), "i" (ins)); \ } while (0) -#define mtlo1(x) \ +#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) +#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) + +#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) +#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) + +#define mflo0() _umips_dsp_mflo(0) +#define mflo1() _umips_dsp_mflo(1) +#define mflo2() _umips_dsp_mflo(2) +#define mflo3() _umips_dsp_mflo(3) + +#define mfhi0() _umips_dsp_mfhi(0) +#define mfhi1() _umips_dsp_mfhi(1) +#define mfhi2() _umips_dsp_mfhi(2) +#define mfhi3() _umips_dsp_mfhi(3) + +#define mtlo0(x) _umips_dsp_mtlo(x, 0) +#define mtlo1(x) _umips_dsp_mtlo(x, 1) +#define mtlo2(x) _umips_dsp_mtlo(x, 2) +#define mtlo3(x) _umips_dsp_mtlo(x, 3) + +#define mthi0(x) _umips_dsp_mthi(x, 0) +#define mthi1(x) _umips_dsp_mthi(x, 1) +#define mthi2(x) _umips_dsp_mthi(x, 2) +#define mthi3(x) _umips_dsp_mthi(x, 3) + +#else /* !CONFIG_CPU_MICROMIPS */ +#define rddsp(mask) \ +({ \ + unsigned int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # rddsp $1, %x1 \n" \ + " .word 0x7c000cb8 | (%x1 << 16) \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) + +#define wrdsp(val, mask) \ do { \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mtlo $1, $ac1 \n" \ - " .word 0x00200813 \n" \ + " # wrdsp $1, %x1 \n" \ + " .word 0x7c2004f8 | (%x1 << 11) \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ + : \ + : "r" (val), "i" (mask)); \ } while (0) -#define mtlo2(x) \ -do { \ +#define _dsp_mfxxx(ins) \ +({ \ + unsigned long __treg; \ + \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac2 \n" \ - " .word 0x00201013 \n" \ + " .word (0x00000810 | %1) \n" \ + " move %0, $1 \n" \ " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) + : "=r" (__treg) \ + : "i" (ins)); \ + __treg; \ +}) -#define mtlo3(x) \ +#define _dsp_mtxxx(val, ins) \ do { \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ " move $1, %0 \n" \ - " # mtlo $1, $ac3 \n" \ - " .word 0x00201813 \n" \ + " .word (0x00200011 | %1) \n" \ " .set pop \n" \ : \ - : "r" (x)); \ + : "r" (val), "i" (ins)); \ } while (0) +#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) +#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) + +#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) +#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) + +#define mflo0() _dsp_mflo(0) +#define mflo1() _dsp_mflo(1) +#define mflo2() _dsp_mflo(2) +#define mflo3() _dsp_mflo(3) + +#define mfhi0() _dsp_mfhi(0) +#define mfhi1() _dsp_mfhi(1) +#define mfhi2() _dsp_mfhi(2) +#define mfhi3() _dsp_mfhi(3) + +#define mtlo0(x) _dsp_mtlo(x, 0) +#define mtlo1(x) _dsp_mtlo(x, 1) +#define mtlo2(x) _dsp_mtlo(x, 2) +#define mtlo3(x) _dsp_mtlo(x, 3) + +#define mthi0(x) _dsp_mthi(x, 0) +#define mthi1(x) _dsp_mthi(x, 1) +#define mthi2(x) _dsp_mthi(x, 2) +#define mthi3(x) _dsp_mthi(x, 3) + +#endif /* CONFIG_CPU_MICROMIPS */ #endif /* @@ -1501,11 +1739,6 @@ static inline void tlb_write_random(void) /* * Manipulate bits in a c0 register. */ -#ifndef CONFIG_MIPS_MT_SMTC -/* - * SMTC Linux requires shutting-down microthread scheduling - * during CP0 register read-modify-write sequences. - */ #define __BUILD_SET_C0(name) \ static inline unsigned int \ set_c0_##name(unsigned int set) \ @@ -1544,124 +1777,10 @@ change_c0_##name(unsigned int change, unsigned int val) \ return res; \ } -#else /* SMTC versions that manage MT scheduling */ - -#include <linux/irqflags.h> - -/* - * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with - * header file recursion. - */ -static inline unsigned int __dmt(void) -{ - int res; - - __asm__ __volatile__( - " .set push \n" - " .set mips32r2 \n" - " .set noat \n" - " .word 0x41610BC1 # dmt $1 \n" - " ehb \n" - " move %0, $1 \n" - " .set pop \n" - : "=r" (res)); - - instruction_hazard(); - - return res; -} - -#define __VPECONTROL_TE_SHIFT 15 -#define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT) - -#define __EMT_ENABLE __VPECONTROL_TE - -static inline void __emt(unsigned int previous) -{ - if ((previous & __EMT_ENABLE)) - __asm__ __volatile__( - " .set mips32r2 \n" - " .word 0x41600be1 # emt \n" - " ehb \n" - " .set mips0 \n"); -} - -static inline void __ehb(void) -{ - __asm__ __volatile__( - " .set mips32r2 \n" - " ehb \n" " .set mips0 \n"); -} - -/* - * Note that local_irq_save/restore affect TC-specific IXMT state, - * not Status.IE as in non-SMTC kernel. - */ - -#define __BUILD_SET_C0(name) \ -static inline unsigned int \ -set_c0_##name(unsigned int set) \ -{ \ - unsigned int res; \ - unsigned int new; \ - unsigned int omt; \ - unsigned long flags; \ - \ - local_irq_save(flags); \ - omt = __dmt(); \ - res = read_c0_##name(); \ - new = res | set; \ - write_c0_##name(new); \ - __emt(omt); \ - local_irq_restore(flags); \ - \ - return res; \ -} \ - \ -static inline unsigned int \ -clear_c0_##name(unsigned int clear) \ -{ \ - unsigned int res; \ - unsigned int new; \ - unsigned int omt; \ - unsigned long flags; \ - \ - local_irq_save(flags); \ - omt = __dmt(); \ - res = read_c0_##name(); \ - new = res & ~clear; \ - write_c0_##name(new); \ - __emt(omt); \ - local_irq_restore(flags); \ - \ - return res; \ -} \ - \ -static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int newbits) \ -{ \ - unsigned int res; \ - unsigned int new; \ - unsigned int omt; \ - unsigned long flags; \ - \ - local_irq_save(flags); \ - \ - omt = __dmt(); \ - res = read_c0_##name(); \ - new = res & ~change; \ - new |= (newbits & change); \ - write_c0_##name(new); \ - __emt(omt); \ - local_irq_restore(flags); \ - \ - return res; \ -} -#endif - __BUILD_SET_C0(status) __BUILD_SET_C0(cause) __BUILD_SET_C0(config) +__BUILD_SET_C0(config5) __BUILD_SET_C0(intcontrol) __BUILD_SET_C0(intctl) __BUILD_SET_C0(srsmap) @@ -1673,6 +1792,15 @@ __BUILD_SET_C0(brcm_cmt_ctrl) __BUILD_SET_C0(brcm_config) __BUILD_SET_C0(brcm_mode) +/* + * Return low 10 bits of ebase. + * Note that under KVM (MIPSVZ) this returns vcpu id. + */ +static inline unsigned int get_ebase_cpunum(void) +{ + return read_c0_ebase() & 0x3ff; +} + #endif /* !__ASSEMBLY__ */ #endif /* _ASM_MIPSREGS_H */ diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index 45cfa1ad86a..2e373da5f8e 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -18,26 +18,27 @@ #include <asm/cacheflush.h> #include <asm/hazards.h> #include <asm/tlbflush.h> -#ifdef CONFIG_MIPS_MT_SMTC -#include <asm/mipsmtregs.h> -#include <asm/smtc.h> -#endif /* SMTC */ #include <asm-generic/mm_hooks.h> -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT +#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ +do { \ + extern void tlbmiss_handler_setup_pgd(unsigned long); \ + tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ +} while (0) -#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ - tlbmiss_handler_setup_pgd((unsigned long)(pgd)) +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT -extern void tlbmiss_handler_setup_pgd(unsigned long pgd); +#define TLBMISS_HANDLER_RESTORE() \ + write_c0_xcontext((unsigned long) smp_processor_id() << \ + SMP_CPUID_REGSHIFT) #define TLBMISS_HANDLER_SETUP() \ do { \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ - write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ + TLBMISS_HANDLER_RESTORE(); \ } while (0) -#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ +#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ /* * For the fast tlb miss handlers, we keep a per cpu array of pointers @@ -46,21 +47,14 @@ extern void tlbmiss_handler_setup_pgd(unsigned long pgd); */ extern unsigned long pgd_current[]; -#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ - pgd_current[smp_processor_id()] = (unsigned long)(pgd) +#define TLBMISS_HANDLER_RESTORE() \ + write_c0_context((unsigned long) smp_processor_id() << \ + SMP_CPUID_REGSHIFT) -#ifdef CONFIG_32BIT #define TLBMISS_HANDLER_SETUP() \ - write_c0_context((unsigned long) smp_processor_id() << 25); \ + TLBMISS_HANDLER_RESTORE(); \ back_to_back_c0_hazard(); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) -#endif -#ifdef CONFIG_64BIT -#define TLBMISS_HANDLER_SETUP() \ - write_c0_context((unsigned long) smp_processor_id() << 26); \ - back_to_back_c0_hazard(); \ - TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) -#endif #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) @@ -72,13 +66,6 @@ extern unsigned long pgd_current[]; #define ASID_INC 0x10 #define ASID_MASK 0xff0 -#elif defined(CONFIG_MIPS_MT_SMTC) - -#define ASID_INC 0x1 -extern unsigned long smtc_asid_mask; -#define ASID_MASK (smtc_asid_mask) -#define HW_ASID_MASK 0xff -/* End SMTC/34K debug hack */ #else /* FIXME: not correct for R6000 */ #define ASID_INC 0x1 @@ -101,29 +88,28 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) -#ifndef CONFIG_MIPS_MT_SMTC /* Normal, classic MIPS get_new_mmu_context */ static inline void get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) { + extern void kvm_local_flush_tlb_all(void); unsigned long asid = asid_cache(cpu); if (! ((asid += ASID_INC) & ASID_MASK) ) { if (cpu_has_vtag_icache) flush_icache_all(); +#ifdef CONFIG_KVM + kvm_local_flush_tlb_all(); /* start new asid cycle */ +#else local_flush_tlb_all(); /* start new asid cycle */ +#endif if (!asid) /* fix version if needed */ asid = ASID_FIRST_VERSION; } + cpu_context(cpu, mm) = asid_cache(cpu) = asid; } -#else /* CONFIG_MIPS_MT_SMTC */ - -#define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu)) - -#endif /* CONFIG_MIPS_MT_SMTC */ - /* * Initialize the context related info for a new mm_struct * instance. @@ -133,57 +119,23 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm) { int i; - for_each_online_cpu(i) + for_each_possible_cpu(i) cpu_context(i, mm) = 0; return 0; } static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) + struct task_struct *tsk) { unsigned int cpu = smp_processor_id(); unsigned long flags; -#ifdef CONFIG_MIPS_MT_SMTC - unsigned long oldasid; - unsigned long mtflags; - int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; - local_irq_save(flags); - mtflags = dvpe(); -#else /* Not SMTC */ local_irq_save(flags); -#endif /* CONFIG_MIPS_MT_SMTC */ /* Check if our ASID is of an older version and thus invalid */ if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) get_new_mmu_context(next, cpu); -#ifdef CONFIG_MIPS_MT_SMTC - /* - * If the EntryHi ASID being replaced happens to be - * the value flagged at ASID recycling time as having - * an extended life, clear the bit showing it being - * in use by this "CPU", and if that's the last bit, - * free up the ASID value for use and flush any old - * instances of it from the TLB. - */ - oldasid = (read_c0_entryhi() & ASID_MASK); - if(smtc_live_asid[mytlb][oldasid]) { - smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); - if(smtc_live_asid[mytlb][oldasid] == 0) - smtc_flush_tlb_asid(oldasid); - } - /* - * Tread softly on EntryHi, and so long as we support - * having ASID_MASK smaller than the hardware maximum, - * make sure no "soft" bits become "hard"... - */ - write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | - cpu_asid(cpu, next)); - ehb(); /* Make sure it propagates to TCStatus */ - evpe(mtflags); -#else write_c0_entryhi(cpu_asid(cpu, next)); -#endif /* CONFIG_MIPS_MT_SMTC */ TLBMISS_HANDLER_SETUP_PGD(next->pgd); /* @@ -216,34 +168,12 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next) unsigned long flags; unsigned int cpu = smp_processor_id(); -#ifdef CONFIG_MIPS_MT_SMTC - unsigned long oldasid; - unsigned long mtflags; - int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; -#endif /* CONFIG_MIPS_MT_SMTC */ - local_irq_save(flags); /* Unconditionally get a new ASID. */ get_new_mmu_context(next, cpu); -#ifdef CONFIG_MIPS_MT_SMTC - /* See comments for similar code above */ - mtflags = dvpe(); - oldasid = read_c0_entryhi() & ASID_MASK; - if(smtc_live_asid[mytlb][oldasid]) { - smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); - if(smtc_live_asid[mytlb][oldasid] == 0) - smtc_flush_tlb_asid(oldasid); - } - /* See comments for similar code above */ - write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | - cpu_asid(cpu, next)); - ehb(); /* Make sure it propagates to TCStatus */ - evpe(mtflags); -#else write_c0_entryhi(cpu_asid(cpu, next)); -#endif /* CONFIG_MIPS_MT_SMTC */ TLBMISS_HANDLER_SETUP_PGD(next->pgd); /* mark mmu ownership change */ @@ -261,48 +191,15 @@ static inline void drop_mmu_context(struct mm_struct *mm, unsigned cpu) { unsigned long flags; -#ifdef CONFIG_MIPS_MT_SMTC - unsigned long oldasid; - /* Can't use spinlock because called from TLB flush within DVPE */ - unsigned int prevvpe; - int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; -#endif /* CONFIG_MIPS_MT_SMTC */ local_irq_save(flags); if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { get_new_mmu_context(mm, cpu); -#ifdef CONFIG_MIPS_MT_SMTC - /* See comments for similar code above */ - prevvpe = dvpe(); - oldasid = (read_c0_entryhi() & ASID_MASK); - if (smtc_live_asid[mytlb][oldasid]) { - smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); - if(smtc_live_asid[mytlb][oldasid] == 0) - smtc_flush_tlb_asid(oldasid); - } - /* See comments for similar code above */ - write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) - | cpu_asid(cpu, mm)); - ehb(); /* Make sure it propagates to TCStatus */ - evpe(prevvpe); -#else /* not CONFIG_MIPS_MT_SMTC */ write_c0_entryhi(cpu_asid(cpu, mm)); -#endif /* CONFIG_MIPS_MT_SMTC */ } else { /* will get a new context next time */ -#ifndef CONFIG_MIPS_MT_SMTC cpu_context(cpu, mm) = 0; -#else /* SMTC */ - int i; - - /* SMTC shares the TLB (and ASIDs) across VPEs */ - for_each_online_cpu(i) { - if((smtc_status & SMTC_TLB_SHARED) - || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) - cpu_context(i, mm) = 0; - } -#endif /* CONFIG_MIPS_MT_SMTC */ } local_irq_restore(flags); } diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index 44b705d0826..800fe578dc9 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -126,6 +126,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "LOONGSON1 " #elif defined CONFIG_CPU_LOONGSON2 #define MODULE_PROC_FAMILY "LOONGSON2 " +#elif defined CONFIG_CPU_LOONGSON3 +#define MODULE_PROC_FAMILY "LOONGSON3 " #elif defined CONFIG_CPU_CAVIUM_OCTEON #define MODULE_PROC_FAMILY "OCTEON " #elif defined CONFIG_CPU_XLR @@ -142,13 +144,7 @@ search_module_dbetables(unsigned long addr) #define MODULE_KERNEL_TYPE "64BIT " #endif -#ifdef CONFIG_MIPS_MT_SMTC -#define MODULE_KERNEL_SMTC "MT_SMTC " -#else -#define MODULE_KERNEL_SMTC "" -#endif - #define MODULE_ARCH_VERMAGIC \ - MODULE_PROC_FAMILY MODULE_KERNEL_TYPE MODULE_KERNEL_SMTC + MODULE_PROC_FAMILY MODULE_KERNEL_TYPE #endif /* _ASM_MODULE_H */ diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h new file mode 100644 index 00000000000..538f6d482db --- /dev/null +++ b/arch/mips/include/asm/msa.h @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton <paul.burton@imgtec.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef _ASM_MSA_H +#define _ASM_MSA_H + +#include <asm/mipsregs.h> + +extern void _save_msa(struct task_struct *); +extern void _restore_msa(struct task_struct *); + +static inline void enable_msa(void) +{ + if (cpu_has_msa) { + set_c0_config5(MIPS_CONF5_MSAEN); + enable_fpu_hazard(); + } +} + +static inline void disable_msa(void) +{ + if (cpu_has_msa) { + clear_c0_config5(MIPS_CONF5_MSAEN); + disable_fpu_hazard(); + } +} + +static inline int is_msa_enabled(void) +{ + if (!cpu_has_msa) + return 0; + + return read_c0_config5() & MIPS_CONF5_MSAEN; +} + +static inline int thread_msa_context_live(void) +{ + /* + * Check cpu_has_msa only if it's a constant. This will allow the + * compiler to optimise out code for CPUs without MSA without adding + * an extra redundant check for CPUs with MSA. + */ + if (__builtin_constant_p(cpu_has_msa) && !cpu_has_msa) + return 0; + + return test_thread_flag(TIF_MSA_CTX_LIVE); +} + +static inline void save_msa(struct task_struct *t) +{ + if (cpu_has_msa) + _save_msa(t); +} + +static inline void restore_msa(struct task_struct *t) +{ + if (cpu_has_msa) + _restore_msa(t); +} + +#ifdef TOOLCHAIN_SUPPORTS_MSA + +#define __BUILD_MSA_CTL_REG(name, cs) \ +static inline unsigned int read_msa_##name(void) \ +{ \ + unsigned int reg; \ + __asm__ __volatile__( \ + " .set push\n" \ + " .set msa\n" \ + " cfcmsa %0, $" #cs "\n" \ + " .set pop\n" \ + : "=r"(reg)); \ + return reg; \ +} \ + \ +static inline void write_msa_##name(unsigned int val) \ +{ \ + __asm__ __volatile__( \ + " .set push\n" \ + " .set msa\n" \ + " ctcmsa $" #cs ", %0\n" \ + " .set pop\n" \ + : : "r"(val)); \ +} + +#else /* !TOOLCHAIN_SUPPORTS_MSA */ + +/* + * Define functions using .word for the c[ft]cmsa instructions in order to + * allow compilation with toolchains that do not support MSA. Once all + * toolchains in use support MSA these can be removed. + */ +#ifdef CONFIG_CPU_MICROMIPS +#define CFC_MSA_INSN 0x587e0056 +#define CTC_MSA_INSN 0x583e0816 +#else +#define CFC_MSA_INSN 0x787e0059 +#define CTC_MSA_INSN 0x783e0819 +#endif + +#define __BUILD_MSA_CTL_REG(name, cs) \ +static inline unsigned int read_msa_##name(void) \ +{ \ + unsigned int reg; \ + __asm__ __volatile__( \ + " .set push\n" \ + " .set noat\n" \ + " .insn\n" \ + " .word #CFC_MSA_INSN | (" #cs " << 11)\n" \ + " move %0, $1\n" \ + " .set pop\n" \ + : "=r"(reg)); \ + return reg; \ +} \ + \ +static inline void write_msa_##name(unsigned int val) \ +{ \ + __asm__ __volatile__( \ + " .set push\n" \ + " .set noat\n" \ + " move $1, %0\n" \ + " .insn\n" \ + " .word #CTC_MSA_INSN | (" #cs " << 6)\n" \ + " .set pop\n" \ + : : "r"(val)); \ +} + +#endif /* !TOOLCHAIN_SUPPORTS_MSA */ + +#define MSA_IR 0 +#define MSA_CSR 1 +#define MSA_ACCESS 2 +#define MSA_SAVE 3 +#define MSA_MODIFY 4 +#define MSA_REQUEST 5 +#define MSA_MAP 6 +#define MSA_UNMAP 7 + +__BUILD_MSA_CTL_REG(ir, 0) +__BUILD_MSA_CTL_REG(csr, 1) +__BUILD_MSA_CTL_REG(access, 2) +__BUILD_MSA_CTL_REG(save, 3) +__BUILD_MSA_CTL_REG(modify, 4) +__BUILD_MSA_CTL_REG(request, 5) +__BUILD_MSA_CTL_REG(map, 6) +__BUILD_MSA_CTL_REG(unmap, 7) + +/* MSA Implementation Register (MSAIR) */ +#define MSA_IR_REVB 0 +#define MSA_IR_REVF (_ULCAST_(0xff) << MSA_IR_REVB) +#define MSA_IR_PROCB 8 +#define MSA_IR_PROCF (_ULCAST_(0xff) << MSA_IR_PROCB) +#define MSA_IR_WRPB 16 +#define MSA_IR_WRPF (_ULCAST_(0x1) << MSA_IR_WRPB) + +/* MSA Control & Status Register (MSACSR) */ +#define MSA_CSR_RMB 0 +#define MSA_CSR_RMF (_ULCAST_(0x3) << MSA_CSR_RMB) +#define MSA_CSR_RM_NEAREST 0 +#define MSA_CSR_RM_TO_ZERO 1 +#define MSA_CSR_RM_TO_POS 2 +#define MSA_CSR_RM_TO_NEG 3 +#define MSA_CSR_FLAGSB 2 +#define MSA_CSR_FLAGSF (_ULCAST_(0x1f) << MSA_CSR_FLAGSB) +#define MSA_CSR_FLAGS_IB 2 +#define MSA_CSR_FLAGS_IF (_ULCAST_(0x1) << MSA_CSR_FLAGS_IB) +#define MSA_CSR_FLAGS_UB 3 +#define MSA_CSR_FLAGS_UF (_ULCAST_(0x1) << MSA_CSR_FLAGS_UB) +#define MSA_CSR_FLAGS_OB 4 +#define MSA_CSR_FLAGS_OF (_ULCAST_(0x1) << MSA_CSR_FLAGS_OB) +#define MSA_CSR_FLAGS_ZB 5 +#define MSA_CSR_FLAGS_ZF (_ULCAST_(0x1) << MSA_CSR_FLAGS_ZB) +#define MSA_CSR_FLAGS_VB 6 +#define MSA_CSR_FLAGS_VF (_ULCAST_(0x1) << MSA_CSR_FLAGS_VB) +#define MSA_CSR_ENABLESB 7 +#define MSA_CSR_ENABLESF (_ULCAST_(0x1f) << MSA_CSR_ENABLESB) +#define MSA_CSR_ENABLES_IB 7 +#define MSA_CSR_ENABLES_IF (_ULCAST_(0x1) << MSA_CSR_ENABLES_IB) +#define MSA_CSR_ENABLES_UB 8 +#define MSA_CSR_ENABLES_UF (_ULCAST_(0x1) << MSA_CSR_ENABLES_UB) +#define MSA_CSR_ENABLES_OB 9 +#define MSA_CSR_ENABLES_OF (_ULCAST_(0x1) << MSA_CSR_ENABLES_OB) +#define MSA_CSR_ENABLES_ZB 10 +#define MSA_CSR_ENABLES_ZF (_ULCAST_(0x1) << MSA_CSR_ENABLES_ZB) +#define MSA_CSR_ENABLES_VB 11 +#define MSA_CSR_ENABLES_VF (_ULCAST_(0x1) << MSA_CSR_ENABLES_VB) +#define MSA_CSR_CAUSEB 12 +#define MSA_CSR_CAUSEF (_ULCAST_(0x3f) << MSA_CSR_CAUSEB) +#define MSA_CSR_CAUSE_IB 12 +#define MSA_CSR_CAUSE_IF (_ULCAST_(0x1) << MSA_CSR_CAUSE_IB) +#define MSA_CSR_CAUSE_UB 13 +#define MSA_CSR_CAUSE_UF (_ULCAST_(0x1) << MSA_CSR_CAUSE_UB) +#define MSA_CSR_CAUSE_OB 14 +#define MSA_CSR_CAUSE_OF (_ULCAST_(0x1) << MSA_CSR_CAUSE_OB) +#define MSA_CSR_CAUSE_ZB 15 +#define MSA_CSR_CAUSE_ZF (_ULCAST_(0x1) << MSA_CSR_CAUSE_ZB) +#define MSA_CSR_CAUSE_VB 16 +#define MSA_CSR_CAUSE_VF (_ULCAST_(0x1) << MSA_CSR_CAUSE_VB) +#define MSA_CSR_CAUSE_EB 17 +#define MSA_CSR_CAUSE_EF (_ULCAST_(0x1) << MSA_CSR_CAUSE_EB) +#define MSA_CSR_NXB 18 +#define MSA_CSR_NXF (_ULCAST_(0x1) << MSA_CSR_NXB) +#define MSA_CSR_FSB 24 +#define MSA_CSR_FSF (_ULCAST_(0x1) << MSA_CSR_FSB) + +#endif /* _ASM_MSA_H */ diff --git a/arch/mips/include/asm/msc01_ic.h b/arch/mips/include/asm/msc01_ic.h index d92406ae284..ff7f074d073 100644 --- a/arch/mips/include/asm/msc01_ic.h +++ b/arch/mips/include/asm/msc01_ic.h @@ -15,45 +15,45 @@ * Register offset addresses *****************************************************************************/ -#define MSC01_IC_RST_OFS 0x00008 /* Software reset */ -#define MSC01_IC_ENAL_OFS 0x00100 /* Int_in enable mask 31:0 */ -#define MSC01_IC_ENAH_OFS 0x00108 /* Int_in enable mask 63:32 */ -#define MSC01_IC_DISL_OFS 0x00120 /* Int_in disable mask 31:0 */ -#define MSC01_IC_DISH_OFS 0x00128 /* Int_in disable mask 63:32 */ -#define MSC01_IC_ISBL_OFS 0x00140 /* Raw int_in 31:0 */ -#define MSC01_IC_ISBH_OFS 0x00148 /* Raw int_in 63:32 */ -#define MSC01_IC_ISAL_OFS 0x00160 /* Masked int_in 31:0 */ -#define MSC01_IC_ISAH_OFS 0x00168 /* Masked int_in 63:32 */ -#define MSC01_IC_LVL_OFS 0x00180 /* Disable priority int_out */ -#define MSC01_IC_RAMW_OFS 0x00180 /* Shadow set RAM (EI) */ -#define MSC01_IC_OSB_OFS 0x00188 /* Raw int_out */ -#define MSC01_IC_OSA_OFS 0x00190 /* Masked int_out */ -#define MSC01_IC_GENA_OFS 0x00198 /* Global HW int enable */ -#define MSC01_IC_BASE_OFS 0x001a0 /* Base address of IC_VEC */ -#define MSC01_IC_VEC_OFS 0x001b0 /* Active int's vector address */ -#define MSC01_IC_EOI_OFS 0x001c0 /* Enable lower level ints */ -#define MSC01_IC_CFG_OFS 0x001c8 /* Configuration register */ -#define MSC01_IC_TRLD_OFS 0x001d0 /* Interval timer reload val */ -#define MSC01_IC_TVAL_OFS 0x001e0 /* Interval timer current val */ -#define MSC01_IC_TCFG_OFS 0x001f0 /* Interval timer config */ -#define MSC01_IC_SUP_OFS 0x00200 /* Set up int_in line 0 */ -#define MSC01_IC_ENA_OFS 0x00800 /* Int_in enable mask 63:0 */ -#define MSC01_IC_DIS_OFS 0x00820 /* Int_in disable mask 63:0 */ -#define MSC01_IC_ISB_OFS 0x00840 /* Raw int_in 63:0 */ -#define MSC01_IC_ISA_OFS 0x00860 /* Masked int_in 63:0 */ +#define MSC01_IC_RST_OFS 0x00008 /* Software reset */ +#define MSC01_IC_ENAL_OFS 0x00100 /* Int_in enable mask 31:0 */ +#define MSC01_IC_ENAH_OFS 0x00108 /* Int_in enable mask 63:32 */ +#define MSC01_IC_DISL_OFS 0x00120 /* Int_in disable mask 31:0 */ +#define MSC01_IC_DISH_OFS 0x00128 /* Int_in disable mask 63:32 */ +#define MSC01_IC_ISBL_OFS 0x00140 /* Raw int_in 31:0 */ +#define MSC01_IC_ISBH_OFS 0x00148 /* Raw int_in 63:32 */ +#define MSC01_IC_ISAL_OFS 0x00160 /* Masked int_in 31:0 */ +#define MSC01_IC_ISAH_OFS 0x00168 /* Masked int_in 63:32 */ +#define MSC01_IC_LVL_OFS 0x00180 /* Disable priority int_out */ +#define MSC01_IC_RAMW_OFS 0x00180 /* Shadow set RAM (EI) */ +#define MSC01_IC_OSB_OFS 0x00188 /* Raw int_out */ +#define MSC01_IC_OSA_OFS 0x00190 /* Masked int_out */ +#define MSC01_IC_GENA_OFS 0x00198 /* Global HW int enable */ +#define MSC01_IC_BASE_OFS 0x001a0 /* Base address of IC_VEC */ +#define MSC01_IC_VEC_OFS 0x001b0 /* Active int's vector address */ +#define MSC01_IC_EOI_OFS 0x001c0 /* Enable lower level ints */ +#define MSC01_IC_CFG_OFS 0x001c8 /* Configuration register */ +#define MSC01_IC_TRLD_OFS 0x001d0 /* Interval timer reload val */ +#define MSC01_IC_TVAL_OFS 0x001e0 /* Interval timer current val */ +#define MSC01_IC_TCFG_OFS 0x001f0 /* Interval timer config */ +#define MSC01_IC_SUP_OFS 0x00200 /* Set up int_in line 0 */ +#define MSC01_IC_ENA_OFS 0x00800 /* Int_in enable mask 63:0 */ +#define MSC01_IC_DIS_OFS 0x00820 /* Int_in disable mask 63:0 */ +#define MSC01_IC_ISB_OFS 0x00840 /* Raw int_in 63:0 */ +#define MSC01_IC_ISA_OFS 0x00860 /* Masked int_in 63:0 */ /***************************************************************************** * Register field encodings *****************************************************************************/ -#define MSC01_IC_RST_RST_SHF 0 -#define MSC01_IC_RST_RST_MSK 0x00000001 -#define MSC01_IC_RST_RST_BIT MSC01_IC_RST_RST_MSK -#define MSC01_IC_LVL_LVL_SHF 0 -#define MSC01_IC_LVL_LVL_MSK 0x000000ff -#define MSC01_IC_LVL_SPUR_SHF 16 -#define MSC01_IC_LVL_SPUR_MSK 0x00010000 -#define MSC01_IC_LVL_SPUR_BIT MSC01_IC_LVL_SPUR_MSK +#define MSC01_IC_RST_RST_SHF 0 +#define MSC01_IC_RST_RST_MSK 0x00000001 +#define MSC01_IC_RST_RST_BIT MSC01_IC_RST_RST_MSK +#define MSC01_IC_LVL_LVL_SHF 0 +#define MSC01_IC_LVL_LVL_MSK 0x000000ff +#define MSC01_IC_LVL_SPUR_SHF 16 +#define MSC01_IC_LVL_SPUR_MSK 0x00010000 +#define MSC01_IC_LVL_SPUR_BIT MSC01_IC_LVL_SPUR_MSK #define MSC01_IC_RAMW_RIPL_SHF 0 #define MSC01_IC_RAMW_RIPL_MSK 0x0000003f #define MSC01_IC_RAMW_DATA_SHF 6 @@ -63,33 +63,33 @@ #define MSC01_IC_RAMW_READ_SHF 31 #define MSC01_IC_RAMW_READ_MSK 0x80000000 #define MSC01_IC_RAMW_READ_BIT MSC01_IC_RAMW_READ_MSK -#define MSC01_IC_OSB_OSB_SHF 0 -#define MSC01_IC_OSB_OSB_MSK 0x000000ff -#define MSC01_IC_OSA_OSA_SHF 0 -#define MSC01_IC_OSA_OSA_MSK 0x000000ff -#define MSC01_IC_GENA_GENA_SHF 0 -#define MSC01_IC_GENA_GENA_MSK 0x00000001 -#define MSC01_IC_GENA_GENA_BIT MSC01_IC_GENA_GENA_MSK -#define MSC01_IC_CFG_DIS_SHF 0 -#define MSC01_IC_CFG_DIS_MSK 0x00000001 -#define MSC01_IC_CFG_DIS_BIT MSC01_IC_CFG_DIS_MSK -#define MSC01_IC_CFG_SHFT_SHF 8 -#define MSC01_IC_CFG_SHFT_MSK 0x00000f00 -#define MSC01_IC_TCFG_ENA_SHF 0 -#define MSC01_IC_TCFG_ENA_MSK 0x00000001 -#define MSC01_IC_TCFG_ENA_BIT MSC01_IC_TCFG_ENA_MSK -#define MSC01_IC_TCFG_INT_SHF 8 -#define MSC01_IC_TCFG_INT_MSK 0x00000100 -#define MSC01_IC_TCFG_INT_BIT MSC01_IC_TCFG_INT_MSK -#define MSC01_IC_TCFG_EDGE_SHF 16 -#define MSC01_IC_TCFG_EDGE_MSK 0x00010000 -#define MSC01_IC_TCFG_EDGE_BIT MSC01_IC_TCFG_EDGE_MSK -#define MSC01_IC_SUP_PRI_SHF 0 -#define MSC01_IC_SUP_PRI_MSK 0x00000007 -#define MSC01_IC_SUP_EDGE_SHF 8 -#define MSC01_IC_SUP_EDGE_MSK 0x00000100 -#define MSC01_IC_SUP_EDGE_BIT MSC01_IC_SUP_EDGE_MSK -#define MSC01_IC_SUP_STEP 8 +#define MSC01_IC_OSB_OSB_SHF 0 +#define MSC01_IC_OSB_OSB_MSK 0x000000ff +#define MSC01_IC_OSA_OSA_SHF 0 +#define MSC01_IC_OSA_OSA_MSK 0x000000ff +#define MSC01_IC_GENA_GENA_SHF 0 +#define MSC01_IC_GENA_GENA_MSK 0x00000001 +#define MSC01_IC_GENA_GENA_BIT MSC01_IC_GENA_GENA_MSK +#define MSC01_IC_CFG_DIS_SHF 0 +#define MSC01_IC_CFG_DIS_MSK 0x00000001 +#define MSC01_IC_CFG_DIS_BIT MSC01_IC_CFG_DIS_MSK +#define MSC01_IC_CFG_SHFT_SHF 8 +#define MSC01_IC_CFG_SHFT_MSK 0x00000f00 +#define MSC01_IC_TCFG_ENA_SHF 0 +#define MSC01_IC_TCFG_ENA_MSK 0x00000001 +#define MSC01_IC_TCFG_ENA_BIT MSC01_IC_TCFG_ENA_MSK +#define MSC01_IC_TCFG_INT_SHF 8 +#define MSC01_IC_TCFG_INT_MSK 0x00000100 +#define MSC01_IC_TCFG_INT_BIT MSC01_IC_TCFG_INT_MSK +#define MSC01_IC_TCFG_EDGE_SHF 16 +#define MSC01_IC_TCFG_EDGE_MSK 0x00010000 +#define MSC01_IC_TCFG_EDGE_BIT MSC01_IC_TCFG_EDGE_MSK +#define MSC01_IC_SUP_PRI_SHF 0 +#define MSC01_IC_SUP_PRI_MSK 0x00000007 +#define MSC01_IC_SUP_EDGE_SHF 8 +#define MSC01_IC_SUP_EDGE_MSK 0x00000100 +#define MSC01_IC_SUP_EDGE_BIT MSC01_IC_SUP_EDGE_MSK +#define MSC01_IC_SUP_STEP 8 /* * MIPS System controller interrupt register base. @@ -100,32 +100,32 @@ * Absolute register addresses *****************************************************************************/ -#define MSC01_IC_RST (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS) -#define MSC01_IC_ENAL (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS) -#define MSC01_IC_ENAH (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS) -#define MSC01_IC_DISL (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS) -#define MSC01_IC_DISH (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS) -#define MSC01_IC_ISBL (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS) -#define MSC01_IC_ISBH (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS) -#define MSC01_IC_ISAL (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS) -#define MSC01_IC_ISAH (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS) -#define MSC01_IC_LVL (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS) -#define MSC01_IC_RAMW (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS) -#define MSC01_IC_OSB (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS) -#define MSC01_IC_OSA (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS) -#define MSC01_IC_GENA (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS) -#define MSC01_IC_BASE (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS) -#define MSC01_IC_VEC (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS) -#define MSC01_IC_EOI (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS) -#define MSC01_IC_CFG (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS) -#define MSC01_IC_TRLD (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS) -#define MSC01_IC_TVAL (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS) -#define MSC01_IC_TCFG (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS) -#define MSC01_IC_SUP (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS) -#define MSC01_IC_ENA (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS) -#define MSC01_IC_DIS (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS) -#define MSC01_IC_ISB (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS) -#define MSC01_IC_ISA (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS) +#define MSC01_IC_RST (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS) +#define MSC01_IC_ENAL (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS) +#define MSC01_IC_ENAH (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS) +#define MSC01_IC_DISL (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS) +#define MSC01_IC_DISH (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS) +#define MSC01_IC_ISBL (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS) +#define MSC01_IC_ISBH (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS) +#define MSC01_IC_ISAL (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS) +#define MSC01_IC_ISAH (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS) +#define MSC01_IC_LVL (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS) +#define MSC01_IC_RAMW (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS) +#define MSC01_IC_OSB (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS) +#define MSC01_IC_OSA (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS) +#define MSC01_IC_GENA (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS) +#define MSC01_IC_BASE (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS) +#define MSC01_IC_VEC (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS) +#define MSC01_IC_EOI (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS) +#define MSC01_IC_CFG (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS) +#define MSC01_IC_TRLD (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS) +#define MSC01_IC_TVAL (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS) +#define MSC01_IC_TCFG (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS) +#define MSC01_IC_SUP (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS) +#define MSC01_IC_ENA (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS) +#define MSC01_IC_DIS (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS) +#define MSC01_IC_ISB (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS) +#define MSC01_IC_ISA (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS) /* * Soc-it interrupts are configurable. diff --git a/arch/mips/include/asm/mutex.h b/arch/mips/include/asm/mutex.h deleted file mode 100644 index 458c1f7fbc1..00000000000 --- a/arch/mips/include/asm/mutex.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Pull in the generic implementation for the mutex fastpath. - * - * TODO: implement optimized primitives instead, or leave the generic - * implementation in place, or pick the atomic_xchg() based generic - * implementation. (see asm-generic/mutex-xchg.h for details) - */ - -#include <asm-generic/mutex-dec.h> diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h index 42bfd5f1eee..c281f03eb31 100644 --- a/arch/mips/include/asm/netlogic/common.h +++ b/arch/mips/include/asm/netlogic/common.h @@ -38,11 +38,17 @@ /* * Common SMP definitions */ -#define RESET_VEC_PHYS 0x1fc00000 -#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10)) -#define BOOT_THREAD_MODE 0 -#define BOOT_NMI_LOCK 4 -#define BOOT_NMI_HANDLER 8 +#define RESET_VEC_PHYS 0x1fc00000 +#define RESET_VEC_SIZE 8192 /* 8KB reset code and data */ +#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10)) + +/* Offsets of parameters in the RESET_DATA_PHYS area */ +#define BOOT_THREAD_MODE 0 +#define BOOT_NMI_LOCK 4 +#define BOOT_NMI_HANDLER 8 + +/* CPU ready flags for each CPU */ +#define BOOT_CPU_READY 2048 #ifndef __ASSEMBLY__ #include <linux/cpumask.h> @@ -59,46 +65,44 @@ int nlm_wakeup_secondary_cpus(void); void nlm_rmiboot_preboot(void); void nlm_percpu_init(int hwcpuid); +static inline void * +nlm_get_boot_data(int offset) +{ + return (void *)(CKSEG1ADDR(RESET_DATA_PHYS) + offset); +} + static inline void nlm_set_nmi_handler(void *handler) { - char *reset_data; + void *nmih = nlm_get_boot_data(BOOT_NMI_HANDLER); - reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS); - *(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler; + *(int64_t *)nmih = (long)handler; } /* * Misc. */ +void nlm_init_boot_cpu(void); unsigned int nlm_get_cpu_frequency(void); -void nlm_node_init(int node); extern struct plat_smp_ops nlm_smp_ops; extern char nlm_reset_entry[], nlm_reset_entry_end[]; +/* SWIOTLB */ +extern struct dma_map_ops nlm_swiotlb_dma_ops; + extern unsigned int nlm_threads_per_core; extern cpumask_t nlm_cpumask; -struct nlm_soc_info { - unsigned long coremask; /* cores enabled on the soc */ - unsigned long ebase; - uint64_t irqmask; - uint64_t sysbase; /* only for XLP */ - uint64_t picbase; - spinlock_t piclock; -}; - -#define nlm_get_node(i) (&nlm_nodes[i]) -#ifdef CONFIG_CPU_XLR -#define nlm_current_node() (&nlm_nodes[0]) -#else -#define nlm_current_node() (&nlm_nodes[nlm_nodeid()]) -#endif - struct irq_data; uint64_t nlm_pci_irqmask(int node); +void nlm_setup_pic_irq(int node, int picirq, int irq, int irt); void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *)); +#ifdef CONFIG_PCI_MSI +void nlm_dispatch_msi(int node, int lirq); +void nlm_dispatch_msix(int node, int msixirq); +#endif + /* * The NR_IRQs is divided between nodes, each of them has a separate irq space */ @@ -107,7 +111,6 @@ static inline int nlm_irq_to_xirq(int node, int irq) return node * NR_IRQS / NLM_NR_NODES + irq; } -extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; extern int nlm_cpu_ready[]; #endif #endif /* _NETLOGIC_COMMON_H_ */ diff --git a/arch/mips/include/asm/netlogic/haldefs.h b/arch/mips/include/asm/netlogic/haldefs.h index 72a0c788b47..79c7cccdc22 100644 --- a/arch/mips/include/asm/netlogic/haldefs.h +++ b/arch/mips/include/asm/netlogic/haldefs.h @@ -35,42 +35,13 @@ #ifndef __NLM_HAL_HALDEFS_H__ #define __NLM_HAL_HALDEFS_H__ +#include <linux/irqflags.h> /* for local_irq_disable */ + /* * This file contains platform specific memory mapped IO implementation * and will provide a way to read 32/64 bit memory mapped registers in * all ABIs */ -#if !defined(CONFIG_64BIT) && defined(CONFIG_CPU_XLP) -#error "o32 compile not supported on XLP yet" -#endif -/* - * For o32 compilation, we have to disable interrupts and enable KX bit to - * access 64 bit addresses or data. - * - * We need to disable interrupts because we save just the lower 32 bits of - * registers in interrupt handling. So if we get hit by an interrupt while - * using the upper 32 bits of a register, we lose. - */ -static inline uint32_t nlm_save_flags_kx(void) -{ - return change_c0_status(ST0_KX | ST0_IE, ST0_KX); -} - -static inline uint32_t nlm_save_flags_cop2(void) -{ - return change_c0_status(ST0_CU2 | ST0_IE, ST0_CU2); -} - -static inline void nlm_restore_flags(uint32_t sr) -{ - write_c0_status(sr); -} - -/* - * The n64 implementations are simple, the o32 implementations when they - * are added, will have to disable interrupts and enable KX before doing - * 64 bit ops. - */ static inline uint32_t nlm_read_reg(uint64_t base, uint32_t reg) { @@ -87,13 +58,40 @@ nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) *addr = val; } +/* + * For o32 compilation, we have to disable interrupts to access 64 bit + * registers + * + * We need to disable interrupts because we save just the lower 32 bits of + * registers in interrupt handling. So if we get hit by an interrupt while + * using the upper 32 bits of a register, we lose. + */ + static inline uint64_t nlm_read_reg64(uint64_t base, uint32_t reg) { uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); volatile uint64_t *ptr = (volatile uint64_t *)(long)addr; - - return *ptr; + uint64_t val; + + if (sizeof(unsigned long) == 4) { + unsigned long flags; + + local_irq_save(flags); + __asm__ __volatile__( + ".set push" "\n\t" + ".set mips64" "\n\t" + "ld %L0, %1" "\n\t" + "dsra32 %M0, %L0, 0" "\n\t" + "sll %L0, %L0, 0" "\n\t" + ".set pop" "\n" + : "=r" (val) + : "m" (*ptr)); + local_irq_restore(flags); + } else + val = *ptr; + + return val; } static inline void @@ -102,7 +100,25 @@ nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val) uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); volatile uint64_t *ptr = (volatile uint64_t *)(long)addr; - *ptr = val; + if (sizeof(unsigned long) == 4) { + unsigned long flags; + uint64_t tmp; + + local_irq_save(flags); + __asm__ __volatile__( + ".set push" "\n\t" + ".set mips64" "\n\t" + "dsll32 %L0, %L0, 0" "\n\t" + "dsrl32 %L0, %L0, 0" "\n\t" + "dsll32 %M0, %M0, 0" "\n\t" + "or %L0, %L0, %M0" "\n\t" + "sd %L0, %2" "\n\t" + ".set pop" "\n" + : "=r" (tmp) + : "0" (val), "m" (*ptr)); + local_irq_restore(flags); + } else + *ptr = val; } /* @@ -143,14 +159,6 @@ nlm_pcicfg_base(uint32_t devoffset) return nlm_io_base + devoffset; } -static inline uint64_t -nlm_xkphys_map_pcibar0(uint64_t pcibase) -{ - uint64_t paddr; - - paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu; - return (uint64_t)0x9000000000000000 | paddr; -} #elif defined(CONFIG_CPU_XLR) static inline uint64_t diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h index 32ba6d95d47..06f1f75bfa9 100644 --- a/arch/mips/include/asm/netlogic/mips-extns.h +++ b/arch/mips/include/asm/netlogic/mips-extns.h @@ -38,21 +38,16 @@ /* * XLR and XLP interrupt request and interrupt mask registers */ -#define read_c0_eirr() __read_64bit_c0_register($9, 6) -#define read_c0_eimr() __read_64bit_c0_register($9, 7) -#define write_c0_eirr(val) __write_64bit_c0_register($9, 6, val) - /* - * Writing EIMR in 32 bit is a special case, the lower 8 bit of the - * EIMR is shadowed in the status register, so we cannot save and - * restore status register for split read. + * NOTE: Do not save/restore flags around write_c0_eimr(). + * On non-R2 platforms the flags has part of EIMR that is shadowed in STATUS + * register. Restoring flags will overwrite the lower 8 bits of EIMR. + * + * Call with interrupts disabled. */ #define write_c0_eimr(val) \ do { \ - if (sizeof(unsigned long) == 4) { \ - unsigned long __flags; \ - \ - local_irq_save(__flags); \ + if (sizeof(unsigned long) == 4) { \ __asm__ __volatile__( \ ".set\tmips64\n\t" \ "dsll\t%L0, %L0, 32\n\t" \ @@ -62,12 +57,88 @@ do { \ "dmtc0\t%L0, $9, 7\n\t" \ ".set\tmips0" \ : : "r" (val)); \ - __flags = (__flags & 0xffff00ff) | (((val) & 0xff) << 8);\ - local_irq_restore(__flags); \ } else \ __write_64bit_c0_register($9, 7, (val)); \ } while (0) +/* + * Handling the 64 bit EIMR and EIRR registers in 32-bit mode with + * standard functions will be very inefficient. This provides + * optimized functions for the normal operations on the registers. + * + * Call with interrupts disabled. + */ +static inline void ack_c0_eirr(int irq) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set mips64\n\t" + ".set noat\n\t" + "li $1, 1\n\t" + "dsllv $1, $1, %0\n\t" + "dmtc0 $1, $9, 6\n\t" + ".set pop" + : : "r" (irq)); +} + +static inline void set_c0_eimr(int irq) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set mips64\n\t" + ".set noat\n\t" + "li $1, 1\n\t" + "dsllv %0, $1, %0\n\t" + "dmfc0 $1, $9, 7\n\t" + "or $1, %0\n\t" + "dmtc0 $1, $9, 7\n\t" + ".set pop" + : "+r" (irq)); +} + +static inline void clear_c0_eimr(int irq) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set mips64\n\t" + ".set noat\n\t" + "li $1, 1\n\t" + "dsllv %0, $1, %0\n\t" + "dmfc0 $1, $9, 7\n\t" + "or $1, %0\n\t" + "xor $1, %0\n\t" + "dmtc0 $1, $9, 7\n\t" + ".set pop" + : "+r" (irq)); +} + +/* + * Read c0 eimr and c0 eirr, do AND of the two values, the result is + * the interrupts which are raised and are not masked. + */ +static inline uint64_t read_c0_eirr_and_eimr(void) +{ + uint64_t val; + +#ifdef CONFIG_64BIT + val = __read_64bit_c0_register($9, 6) & __read_64bit_c0_register($9, 7); +#else + __asm__ __volatile__( + ".set push\n\t" + ".set mips64\n\t" + ".set noat\n\t" + "dmfc0 %M0, $9, 6\n\t" + "dmfc0 %L0, $9, 7\n\t" + "and %M0, %L0\n\t" + "dsll %L0, %M0, 32\n\t" + "dsra %M0, %M0, 32\n\t" + "dsra %L0, %L0, 32\n\t" + ".set pop" + : "=r" (val)); +#endif + return val; +} + static inline int hard_smp_processor_id(void) { return __read_32bit_c0_register($15, 1) & 0x3ff; @@ -75,7 +146,13 @@ static inline int hard_smp_processor_id(void) static inline int nlm_nodeid(void) { - return (__read_32bit_c0_register($15, 1) >> 5) & 0x3; + uint32_t prid = read_c0_prid() & PRID_IMP_MASK; + + if ((prid == PRID_IMP_NETLOGIC_XLP9XX) || + (prid == PRID_IMP_NETLOGIC_XLP5XX)) + return (__read_32bit_c0_register($15, 1) >> 7) & 0x7; + else + return (__read_32bit_c0_register($15, 1) >> 5) & 0x3; } static inline unsigned int nlm_core_id(void) @@ -208,7 +285,7 @@ do { \ ".set\tmips0\n\t" \ : : "Jr" (value)); \ else \ - __asm__ __volatile__( \ + __asm__ __volatile__( \ ".set\tmips32\n\t" \ "mtc2\t%z0, " #reg ", " #sel "\n\t" \ ".set\tmips0\n\t" \ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h index ca95133f1ad..3067f983495 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h @@ -69,41 +69,10 @@ #define BRIDGE_FLASH_LIMIT3 0x13 #define BRIDGE_DRAM_BAR(i) (0x14 + (i)) -#define BRIDGE_DRAM_BAR0 0x14 -#define BRIDGE_DRAM_BAR1 0x15 -#define BRIDGE_DRAM_BAR2 0x16 -#define BRIDGE_DRAM_BAR3 0x17 -#define BRIDGE_DRAM_BAR4 0x18 -#define BRIDGE_DRAM_BAR5 0x19 -#define BRIDGE_DRAM_BAR6 0x1a -#define BRIDGE_DRAM_BAR7 0x1b - #define BRIDGE_DRAM_LIMIT(i) (0x1c + (i)) -#define BRIDGE_DRAM_LIMIT0 0x1c -#define BRIDGE_DRAM_LIMIT1 0x1d -#define BRIDGE_DRAM_LIMIT2 0x1e -#define BRIDGE_DRAM_LIMIT3 0x1f -#define BRIDGE_DRAM_LIMIT4 0x20 -#define BRIDGE_DRAM_LIMIT5 0x21 -#define BRIDGE_DRAM_LIMIT6 0x22 -#define BRIDGE_DRAM_LIMIT7 0x23 +#define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i)) +#define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i)) -#define BRIDGE_DRAM_NODE_TRANSLN0 0x24 -#define BRIDGE_DRAM_NODE_TRANSLN1 0x25 -#define BRIDGE_DRAM_NODE_TRANSLN2 0x26 -#define BRIDGE_DRAM_NODE_TRANSLN3 0x27 -#define BRIDGE_DRAM_NODE_TRANSLN4 0x28 -#define BRIDGE_DRAM_NODE_TRANSLN5 0x29 -#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a -#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b -#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c -#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d -#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e -#define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f -#define BRIDGE_DRAM_CHNL_TRANSLN4 0x30 -#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31 -#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32 -#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33 #define BRIDGE_PCIEMEM_BASE0 0x34 #define BRIDGE_PCIEMEM_BASE1 0x35 #define BRIDGE_PCIEMEM_BASE2 0x36 @@ -174,13 +143,43 @@ #define BRIDGE_GIO_WEIGHT 0x2cb #define BRIDGE_FLASH_WEIGHT 0x2cc +/* FIXME verify */ +#define BRIDGE_9XX_FLASH_BAR(i) (0x11 + (i)) +#define BRIDGE_9XX_FLASH_BAR_LIMIT(i) (0x15 + (i)) + +#define BRIDGE_9XX_DRAM_BAR(i) (0x19 + (i)) +#define BRIDGE_9XX_DRAM_LIMIT(i) (0x29 + (i)) +#define BRIDGE_9XX_DRAM_NODE_TRANSLN(i) (0x39 + (i)) +#define BRIDGE_9XX_DRAM_CHNL_TRANSLN(i) (0x49 + (i)) + +#define BRIDGE_9XX_ADDRESS_ERROR0 0x9d +#define BRIDGE_9XX_ADDRESS_ERROR1 0x9e +#define BRIDGE_9XX_ADDRESS_ERROR2 0x9f + +#define BRIDGE_9XX_PCIEMEM_BASE0 0x59 +#define BRIDGE_9XX_PCIEMEM_BASE1 0x5a +#define BRIDGE_9XX_PCIEMEM_BASE2 0x5b +#define BRIDGE_9XX_PCIEMEM_BASE3 0x5c +#define BRIDGE_9XX_PCIEMEM_LIMIT0 0x5d +#define BRIDGE_9XX_PCIEMEM_LIMIT1 0x5e +#define BRIDGE_9XX_PCIEMEM_LIMIT2 0x5f +#define BRIDGE_9XX_PCIEMEM_LIMIT3 0x60 +#define BRIDGE_9XX_PCIEIO_BASE0 0x61 +#define BRIDGE_9XX_PCIEIO_BASE1 0x62 +#define BRIDGE_9XX_PCIEIO_BASE2 0x63 +#define BRIDGE_9XX_PCIEIO_BASE3 0x64 +#define BRIDGE_9XX_PCIEIO_LIMIT0 0x65 +#define BRIDGE_9XX_PCIEIO_LIMIT1 0x66 +#define BRIDGE_9XX_PCIEIO_LIMIT2 0x67 +#define BRIDGE_9XX_PCIEIO_LIMIT3 0x68 + #ifndef __ASSEMBLY__ #define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r) #define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) -#define nlm_get_bridge_pcibase(node) \ - nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node)) -#define nlm_get_bridge_regbase(node) \ +#define nlm_get_bridge_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \ + XLP9XX_IO_BRIDGE_OFFSET(node) : XLP_IO_BRIDGE_OFFSET(node)) +#define nlm_get_bridge_regbase(node) \ (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ) #endif /* __ASSEMBLY__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h index 7b63a6b722a..6d2e58a9a54 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h @@ -46,6 +46,8 @@ #define CPU_BLOCKID_FPU 9 #define CPU_BLOCKID_MAP 10 +#define ICU_DEFEATURE 0x100 + #define LSU_DEFEATURE 0x304 #define LSU_DEBUG_ADDR 0x305 #define LSU_DEBUG_DATA0 0x306 diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h index 2c63f975464..805bfd21f33 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h @@ -35,12 +35,12 @@ #ifndef __NLM_HAL_IOMAP_H__ #define __NLM_HAL_IOMAP_H__ -#define XLP_DEFAULT_IO_BASE 0x18000000 +#define XLP_DEFAULT_IO_BASE 0x18000000 #define XLP_DEFAULT_PCI_ECFG_BASE XLP_DEFAULT_IO_BASE #define XLP_DEFAULT_PCI_CFG_BASE 0x1c000000 #define NMI_BASE 0xbfc00000 -#define XLP_IO_CLK 133333333 +#define XLP_IO_CLK 133333333 #define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */ #define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE) @@ -48,8 +48,10 @@ #define XLP_IO_SIZE (64 << 20) /* ECFG space size */ #define XLP_IO_PCI_HDRSZ 0x100 #define XLP_IO_DEV(node, dev) ((dev) + (node) * 8) -#define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \ - ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12)) +#define XLP_IO_PCI_OFFSET(b, d, f) (((b) << 20) | ((d) << 15) | ((f) << 12)) + +#define XLP_HDR_OFFSET(node, bus, dev, fn) \ + XLP_IO_PCI_OFFSET(bus, XLP_IO_DEV(node, dev), fn) #define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0) /* coherent inter chip */ @@ -72,6 +74,14 @@ #define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4) #define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5) +#define XLP_IO_SATA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 2) + +/* XLP2xx has an updated USB block */ +#define XLP2XX_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 4, i) +#define XLP2XX_IO_USB_XHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 1) +#define XLP2XX_IO_USB_XHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 2) +#define XLP2XX_IO_USB_XHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 3) + #define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0) #define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1) @@ -88,17 +98,50 @@ #define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2) #define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3) #define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4) +/* on 2XX, all I2C busses are on the same block */ +#define XLP2XX_IO_I2C_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 7) + /* system management */ #define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5) #define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6) +/* Flash */ #define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0) #define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1) #define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2) -/* SD flash */ -#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3) -#define XLP_IO_MMC_OFFSET(node, slot) \ - ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ) +#define XLP_IO_MMC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3) + +/* Things have changed drastically in XLP 9XX */ +#define XLP9XX_HDR_OFFSET(n, d, f) \ + XLP_IO_PCI_OFFSET(xlp9xx_get_socbus(n), d, f) + +#define XLP9XX_IO_BRIDGE_OFFSET(node) XLP_IO_PCI_OFFSET(0, 0, node) +#define XLP9XX_IO_PIC_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 0) +#define XLP9XX_IO_UART_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 2) +#define XLP9XX_IO_SYS_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 0) +#define XLP9XX_IO_FUSE_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 1) +#define XLP9XX_IO_CLOCK_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 2) +#define XLP9XX_IO_POWER_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 3) +#define XLP9XX_IO_JTAG_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 4) + +#define XLP9XX_IO_PCIE_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 1, i) +#define XLP9XX_IO_PCIE0_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 0) +#define XLP9XX_IO_PCIE2_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 2) +#define XLP9XX_IO_PCIE3_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 3) + +/* XLP9xx USB block */ +#define XLP9XX_IO_USB_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 4, i) +#define XLP9XX_IO_USB_XHCI0_OFFSET(node) XLP9XX_HDR_OFFSET(node, 4, 1) +#define XLP9XX_IO_USB_XHCI1_OFFSET(node) XLP9XX_HDR_OFFSET(node, 4, 2) + +/* XLP9XX on-chip SATA controller */ +#define XLP9XX_IO_SATA_OFFSET(node) XLP9XX_HDR_OFFSET(node, 3, 2) + +/* Flash */ +#define XLP9XX_IO_NOR_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 0) +#define XLP9XX_IO_NAND_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 1) +#define XLP9XX_IO_SPI_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 2) +#define XLP9XX_IO_MMC_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 3) /* PCI config header register id's */ #define XLP_PCI_CFGREG0 0x00 @@ -125,32 +168,47 @@ #define XLP_PCI_SBB_WT_REG 0x3f /* PCI IDs for SoC device */ -#define PCI_VENDOR_NETLOGIC 0x184e - -#define PCI_DEVICE_ID_NLM_ROOT 0x1001 -#define PCI_DEVICE_ID_NLM_ICI 0x1002 -#define PCI_DEVICE_ID_NLM_PIC 0x1003 -#define PCI_DEVICE_ID_NLM_PCIE 0x1004 -#define PCI_DEVICE_ID_NLM_EHCI 0x1007 -#define PCI_DEVICE_ID_NLM_OHCI 0x1008 -#define PCI_DEVICE_ID_NLM_NAE 0x1009 -#define PCI_DEVICE_ID_NLM_POE 0x100A -#define PCI_DEVICE_ID_NLM_FMN 0x100B -#define PCI_DEVICE_ID_NLM_RAID 0x100D -#define PCI_DEVICE_ID_NLM_SAE 0x100D -#define PCI_DEVICE_ID_NLM_RSA 0x100E -#define PCI_DEVICE_ID_NLM_CMP 0x100F -#define PCI_DEVICE_ID_NLM_UART 0x1010 -#define PCI_DEVICE_ID_NLM_I2C 0x1011 -#define PCI_DEVICE_ID_NLM_NOR 0x1015 -#define PCI_DEVICE_ID_NLM_NAND 0x1016 -#define PCI_DEVICE_ID_NLM_MMC 0x1018 +#define PCI_VENDOR_NETLOGIC 0x184e + +#define PCI_DEVICE_ID_NLM_ROOT 0x1001 +#define PCI_DEVICE_ID_NLM_ICI 0x1002 +#define PCI_DEVICE_ID_NLM_PIC 0x1003 +#define PCI_DEVICE_ID_NLM_PCIE 0x1004 +#define PCI_DEVICE_ID_NLM_EHCI 0x1007 +#define PCI_DEVICE_ID_NLM_OHCI 0x1008 +#define PCI_DEVICE_ID_NLM_NAE 0x1009 +#define PCI_DEVICE_ID_NLM_POE 0x100A +#define PCI_DEVICE_ID_NLM_FMN 0x100B +#define PCI_DEVICE_ID_NLM_RAID 0x100D +#define PCI_DEVICE_ID_NLM_SAE 0x100D +#define PCI_DEVICE_ID_NLM_RSA 0x100E +#define PCI_DEVICE_ID_NLM_CMP 0x100F +#define PCI_DEVICE_ID_NLM_UART 0x1010 +#define PCI_DEVICE_ID_NLM_I2C 0x1011 +#define PCI_DEVICE_ID_NLM_NOR 0x1015 +#define PCI_DEVICE_ID_NLM_NAND 0x1016 +#define PCI_DEVICE_ID_NLM_MMC 0x1018 +#define PCI_DEVICE_ID_NLM_SATA 0x101A +#define PCI_DEVICE_ID_NLM_XHCI 0x101D + +#define PCI_DEVICE_ID_XLP9XX_MMC 0x9018 +#define PCI_DEVICE_ID_XLP9XX_SATA 0x901A +#define PCI_DEVICE_ID_XLP9XX_XHCI 0x901D #ifndef __ASSEMBLY__ #define nlm_read_pci_reg(b, r) nlm_read_reg(b, r) #define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v) +static inline int xlp9xx_get_socbus(int node) +{ + uint64_t socbridge; + + if (node == 0) + return 1; + socbridge = nlm_pcicfg_base(XLP9XX_IO_BRIDGE_OFFSET(node)); + return (nlm_read_pci_reg(socbridge, 0x6) >> 8) & 0xff; +} #endif /* !__ASSEMBLY */ #endif /* __NLM_HAL_IOMAP_H__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h index 66c323d1bd7..91540f41e1e 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h @@ -33,44 +33,81 @@ */ #ifndef __NLM_HAL_PCIBUS_H__ -#define __NLM_HAL_PCIBUS_H__ +#define __NLM_HAL_PCIBUS_H__ /* PCIE Memory and IO regions */ -#define PCIE_MEM_BASE 0xd0000000ULL -#define PCIE_MEM_LIMIT 0xdfffffffULL -#define PCIE_IO_BASE 0x14000000ULL -#define PCIE_IO_LIMIT 0x15ffffffULL +#define PCIE_MEM_BASE 0xd0000000ULL +#define PCIE_MEM_LIMIT 0xdfffffffULL +#define PCIE_IO_BASE 0x14000000ULL +#define PCIE_IO_LIMIT 0x15ffffffULL -#define PCIE_BRIDGE_CMD 0x1 -#define PCIE_BRIDGE_MSI_CAP 0x14 -#define PCIE_BRIDGE_MSI_ADDRL 0x15 -#define PCIE_BRIDGE_MSI_ADDRH 0x16 -#define PCIE_BRIDGE_MSI_DATA 0x17 +#define PCIE_BRIDGE_CMD 0x1 +#define PCIE_BRIDGE_MSI_CAP 0x14 +#define PCIE_BRIDGE_MSI_ADDRL 0x15 +#define PCIE_BRIDGE_MSI_ADDRH 0x16 +#define PCIE_BRIDGE_MSI_DATA 0x17 /* XLP Global PCIE configuration space registers */ -#define PCIE_BYTE_SWAP_MEM_BASE 0x247 -#define PCIE_BYTE_SWAP_MEM_LIM 0x248 -#define PCIE_BYTE_SWAP_IO_BASE 0x249 -#define PCIE_BYTE_SWAP_IO_LIM 0x24A -#define PCIE_MSI_STATUS 0x25A -#define PCIE_MSI_EN 0x25B -#define PCIE_INT_EN0 0x261 +#define PCIE_BYTE_SWAP_MEM_BASE 0x247 +#define PCIE_BYTE_SWAP_MEM_LIM 0x248 +#define PCIE_BYTE_SWAP_IO_BASE 0x249 +#define PCIE_BYTE_SWAP_IO_LIM 0x24A -/* PCIE_MSI_EN */ -#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF +#define PCIE_BRIDGE_MSIX_ADDR_BASE 0x24F +#define PCIE_BRIDGE_MSIX_ADDR_LIMIT 0x250 +#define PCIE_MSI_STATUS 0x25A +#define PCIE_MSI_EN 0x25B +#define PCIE_MSIX_STATUS 0x25D +#define PCIE_INT_STATUS0 0x25F +#define PCIE_INT_STATUS1 0x260 +#define PCIE_INT_EN0 0x261 +#define PCIE_INT_EN1 0x262 -/* PCIE_INT_EN0 */ -#define PCIE_MSI_INT_EN (1 << 9) +/* XLP9XX has basic changes */ +#define PCIE_9XX_BYTE_SWAP_MEM_BASE 0x25c +#define PCIE_9XX_BYTE_SWAP_MEM_LIM 0x25d +#define PCIE_9XX_BYTE_SWAP_IO_BASE 0x25e +#define PCIE_9XX_BYTE_SWAP_IO_LIM 0x25f +#define PCIE_9XX_BRIDGE_MSIX_ADDR_BASE 0x264 +#define PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT 0x265 +#define PCIE_9XX_MSI_STATUS 0x283 +#define PCIE_9XX_MSI_EN 0x284 +/* 128 MSIX vectors available in 9xx */ +#define PCIE_9XX_MSIX_STATUS0 0x286 +#define PCIE_9XX_MSIX_STATUSX(n) (n + 0x286) +#define PCIE_9XX_MSIX_VEC 0x296 +#define PCIE_9XX_MSIX_VECX(n) (n + 0x296) +#define PCIE_9XX_INT_STATUS0 0x397 +#define PCIE_9XX_INT_STATUS1 0x398 +#define PCIE_9XX_INT_EN0 0x399 +#define PCIE_9XX_INT_EN1 0x39a + +/* other */ +#define PCIE_NLINKS 4 + +/* MSI addresses */ +#define MSI_ADDR_BASE 0xfffee00000ULL +#define MSI_ADDR_SZ 0x10000 +#define MSI_LINK_ADDR(n, l) (MSI_ADDR_BASE + \ + (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ) +#define MSIX_ADDR_BASE 0xfffef00000ULL +#define MSIX_LINK_ADDR(n, l) (MSIX_ADDR_BASE + \ + (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ) #ifndef __ASSEMBLY__ -#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v) -#define nlm_get_pcie_base(node, inst) \ - nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst)) -#define nlm_get_pcie_regbase(node, inst) \ - (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ) +#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r) +#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v) +#define nlm_get_pcie_base(node, inst) nlm_pcicfg_base(cpu_is_xlp9xx() ? \ + XLP9XX_IO_PCIE_OFFSET(node, inst) : XLP_IO_PCIE_OFFSET(node, inst)) + +#ifdef CONFIG_PCI_MSI +void xlp_init_node_msi_irqs(int node, int link); +#else +static inline void xlp_init_node_msi_irqs(int node, int link) {} +#endif + +struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev); -int xlp_pcie_link_irt(int link); #endif #endif /* __NLM_HAL_PCIBUS_H__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h index b2e53a5383a..41cefe94f0c 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h @@ -36,7 +36,7 @@ #define _NLM_HAL_PIC_H /* PIC Specific registers */ -#define PIC_CTRL 0x00 +#define PIC_CTRL 0x00 /* PIC control register defines */ #define PIC_CTRL_ITV 32 /* interrupt timeout value */ @@ -71,41 +71,41 @@ #define PIC_IRT_DB 16 /* Destination base */ #define PIC_IRT_DTE 0 /* Destination thread enables */ -#define PIC_BYTESWAP 0x02 -#define PIC_STATUS 0x04 +#define PIC_BYTESWAP 0x02 +#define PIC_STATUS 0x04 #define PIC_INTR_TIMEOUT 0x06 #define PIC_ICI0_INTR_TIMEOUT 0x08 #define PIC_ICI1_INTR_TIMEOUT 0x0a #define PIC_ICI2_INTR_TIMEOUT 0x0c #define PIC_IPI_CTL 0x0e -#define PIC_INT_ACK 0x10 -#define PIC_INT_PENDING0 0x12 -#define PIC_INT_PENDING1 0x14 -#define PIC_INT_PENDING2 0x16 - -#define PIC_WDOG0_MAXVAL 0x18 -#define PIC_WDOG0_COUNT 0x1a -#define PIC_WDOG0_ENABLE0 0x1c -#define PIC_WDOG0_ENABLE1 0x1e -#define PIC_WDOG0_BEATCMD 0x20 -#define PIC_WDOG0_BEAT0 0x22 -#define PIC_WDOG0_BEAT1 0x24 - -#define PIC_WDOG1_MAXVAL 0x26 -#define PIC_WDOG1_COUNT 0x28 -#define PIC_WDOG1_ENABLE0 0x2a -#define PIC_WDOG1_ENABLE1 0x2c -#define PIC_WDOG1_BEATCMD 0x2e -#define PIC_WDOG1_BEAT0 0x30 -#define PIC_WDOG1_BEAT1 0x32 - -#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0)) -#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0)) -#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0)) -#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0)) -#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0)) -#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0)) -#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0)) +#define PIC_INT_ACK 0x10 +#define PIC_INT_PENDING0 0x12 +#define PIC_INT_PENDING1 0x14 +#define PIC_INT_PENDING2 0x16 + +#define PIC_WDOG0_MAXVAL 0x18 +#define PIC_WDOG0_COUNT 0x1a +#define PIC_WDOG0_ENABLE0 0x1c +#define PIC_WDOG0_ENABLE1 0x1e +#define PIC_WDOG0_BEATCMD 0x20 +#define PIC_WDOG0_BEAT0 0x22 +#define PIC_WDOG0_BEAT1 0x24 + +#define PIC_WDOG1_MAXVAL 0x26 +#define PIC_WDOG1_COUNT 0x28 +#define PIC_WDOG1_ENABLE0 0x2a +#define PIC_WDOG1_ENABLE1 0x2c +#define PIC_WDOG1_BEATCMD 0x2e +#define PIC_WDOG1_BEAT0 0x30 +#define PIC_WDOG1_BEAT1 0x32 + +#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0)) +#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0)) +#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0)) +#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0)) +#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0)) +#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0)) +#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0)) #define PIC_TIMER0_MAXVAL 0x34 #define PIC_TIMER1_MAXVAL 0x36 @@ -127,35 +127,42 @@ #define PIC_TIMER7_COUNT 0x52 #define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2)) -#define PIC_ITE0_N0_N1 0x54 -#define PIC_ITE1_N0_N1 0x58 -#define PIC_ITE2_N0_N1 0x5c -#define PIC_ITE3_N0_N1 0x60 -#define PIC_ITE4_N0_N1 0x64 -#define PIC_ITE5_N0_N1 0x68 -#define PIC_ITE6_N0_N1 0x6c -#define PIC_ITE7_N0_N1 0x70 -#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4)) - -#define PIC_ITE0_N2_N3 0x56 -#define PIC_ITE1_N2_N3 0x5a -#define PIC_ITE2_N2_N3 0x5e -#define PIC_ITE3_N2_N3 0x62 -#define PIC_ITE4_N2_N3 0x66 -#define PIC_ITE5_N2_N3 0x6a -#define PIC_ITE6_N2_N3 0x6e -#define PIC_ITE7_N2_N3 0x72 -#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4)) - -#define PIC_IRT0 0x74 -#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2)) - -#define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL +#define PIC_ITE0_N0_N1 0x54 +#define PIC_ITE1_N0_N1 0x58 +#define PIC_ITE2_N0_N1 0x5c +#define PIC_ITE3_N0_N1 0x60 +#define PIC_ITE4_N0_N1 0x64 +#define PIC_ITE5_N0_N1 0x68 +#define PIC_ITE6_N0_N1 0x6c +#define PIC_ITE7_N0_N1 0x70 +#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4)) + +#define PIC_ITE0_N2_N3 0x56 +#define PIC_ITE1_N2_N3 0x5a +#define PIC_ITE2_N2_N3 0x5e +#define PIC_ITE3_N2_N3 0x62 +#define PIC_ITE4_N2_N3 0x66 +#define PIC_ITE5_N2_N3 0x6a +#define PIC_ITE6_N2_N3 0x6e +#define PIC_ITE7_N2_N3 0x72 +#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4)) + +#define PIC_IRT0 0x74 +#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2)) + +#define PIC_9XX_PENDING_0 0x6 +#define PIC_9XX_PENDING_1 0x8 +#define PIC_9XX_PENDING_2 0xa +#define PIC_9XX_PENDING_3 0xc + +#define PIC_9XX_IRT0 0x1c0 +#define PIC_9XX_IRT(i) (PIC_9XX_IRT0 + ((i) * 2)) /* * IRT Map */ #define PIC_NUM_IRTS 160 +#define PIC_9XX_NUM_IRTS 256 #define PIC_IRT_WD_0_INDEX 0 #define PIC_IRT_WD_1_INDEX 1 @@ -191,69 +198,15 @@ #define PIC_IRT_PCIE_LINK_2_INDEX 80 #define PIC_IRT_PCIE_LINK_3_INDEX 81 #define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX) -/* 78 to 81 */ -#define PIC_NUM_NA_IRTS 32 -/* 82 to 113 */ -#define PIC_IRT_NA_0_INDEX 82 -#define PIC_IRT_NA_INDEX(num) ((num) + PIC_IRT_NA_0_INDEX) -#define PIC_IRT_POE_INDEX 114 - -#define PIC_NUM_USB_IRTS 6 -#define PIC_IRT_USB_0_INDEX 115 -#define PIC_IRT_EHCI_0_INDEX 115 -#define PIC_IRT_OHCI_0_INDEX 116 -#define PIC_IRT_OHCI_1_INDEX 117 -#define PIC_IRT_EHCI_1_INDEX 118 -#define PIC_IRT_OHCI_2_INDEX 119 -#define PIC_IRT_OHCI_3_INDEX 120 -#define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX) -/* 115 to 120 */ -#define PIC_IRT_GDX_INDEX 121 -#define PIC_IRT_SEC_INDEX 122 -#define PIC_IRT_RSA_INDEX 123 - -#define PIC_NUM_COMP_IRTS 4 -#define PIC_IRT_COMP_0_INDEX 124 -#define PIC_IRT_COMP_INDEX(num) ((num) + PIC_IRT_COMP_0_INDEX) -/* 124 to 127 */ -#define PIC_IRT_GBU_INDEX 128 -#define PIC_IRT_ICC_0_INDEX 129 /* ICC - Inter Chip Coherency */ -#define PIC_IRT_ICC_1_INDEX 130 -#define PIC_IRT_ICC_2_INDEX 131 -#define PIC_IRT_CAM_INDEX 132 -#define PIC_IRT_UART_0_INDEX 133 -#define PIC_IRT_UART_1_INDEX 134 -#define PIC_IRT_I2C_0_INDEX 135 -#define PIC_IRT_I2C_1_INDEX 136 -#define PIC_IRT_SYS_0_INDEX 137 -#define PIC_IRT_SYS_1_INDEX 138 -#define PIC_IRT_JTAG_INDEX 139 -#define PIC_IRT_PIC_INDEX 140 -#define PIC_IRT_NBU_INDEX 141 -#define PIC_IRT_TCU_INDEX 142 -#define PIC_IRT_GCU_INDEX 143 /* GBC - Global Coherency */ -#define PIC_IRT_DMC_0_INDEX 144 -#define PIC_IRT_DMC_1_INDEX 145 - -#define PIC_NUM_GPIO_IRTS 4 -#define PIC_IRT_GPIO_0_INDEX 146 -#define PIC_IRT_GPIO_INDEX(num) ((num) + PIC_IRT_GPIO_0_INDEX) - -/* 146 to 149 */ -#define PIC_IRT_NOR_INDEX 150 -#define PIC_IRT_NAND_INDEX 151 -#define PIC_IRT_SPI_INDEX 152 -#define PIC_IRT_MMC_INDEX 153 + +#define PIC_9XX_IRT_PCIE_LINK_0_INDEX 191 +#define PIC_9XX_IRT_PCIE_LINK_INDEX(num) \ + ((num) + PIC_9XX_IRT_PCIE_LINK_0_INDEX) #define PIC_CLOCK_TIMER 7 -#define PIC_IRQ_BASE 8 #if !defined(LOCORE) && !defined(__ASSEMBLY__) -#define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE) -#define PIC_IRT_LAST_IRQ 63 -#define PIC_IRQ_IS_IRT(irq) ((irq) >= PIC_IRT_FIRST_IRQ) - /* * Misc */ @@ -263,27 +216,26 @@ #define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) -#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) +#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \ + XLP9XX_IO_PIC_OFFSET(node) : XLP_IO_PIC_OFFSET(node)) #define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) -/* IRT and h/w interrupt routines */ -static inline int -nlm_pic_read_irt(uint64_t base, int irt_index) -{ - return nlm_read_pic_reg(base, PIC_IRT(irt_index)); -} +/* We use PIC on node 0 as a timer */ +#define pic_timer_freq() nlm_get_pic_frequency(0) +/* IRT and h/w interrupt routines */ static inline void -nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu) +nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, + int sch, int vec, int dt, int db, int cpu) { uint64_t val; - val = nlm_read_pic_reg(base, PIC_IRT(irt)); - /* clear cpuset and mask */ - val &= ~((0x7ull << 16) | 0xffff); - /* set DB, cpuset and cpumask */ - val |= (1 << 19) | ((cpu >> 4) << 16) | (1 << (cpu & 0xf)); - nlm_write_pic_reg(base, PIC_IRT(irt), val); + val = (((uint64_t)en & 0x1) << 22) | ((nmi & 0x1) << 23) | + ((0 /*mc*/) << 20) | ((vec & 0x3f) << 24) | + ((dt & 0x1) << 21) | (0 /*ptr*/ << 16) | + (cpu & 0x3ff); + + nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val); } static inline void @@ -304,9 +256,13 @@ static inline void nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi, int sch, int vec, int cpu) { - nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, - (cpu >> 4), /* thread group */ - 1 << (cpu & 0xf)); /* thread mask */ + if (cpu_is_xlp9xx()) + nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec, + 1, 0, cpu); + else + nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, + (cpu >> 4), /* thread group */ + 1 << (cpu & 0xf)); /* thread mask */ } static inline uint64_t @@ -315,6 +271,12 @@ nlm_pic_read_timer(uint64_t base, int timer) return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); } +static inline uint32_t +nlm_pic_read_timer32(uint64_t base, int timer) +{ + return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); +} + static inline void nlm_pic_write_timer(uint64_t base, int timer, uint64_t value) { @@ -342,8 +304,13 @@ nlm_pic_enable_irt(uint64_t base, int irt) { uint64_t reg; - reg = nlm_read_pic_reg(base, PIC_IRT(irt)); - nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31)); + if (cpu_is_xlp9xx()) { + reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt)); + nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22)); + } else { + reg = nlm_read_pic_reg(base, PIC_IRT(irt)); + nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31)); + } } static inline void @@ -351,8 +318,15 @@ nlm_pic_disable_irt(uint64_t base, int irt) { uint64_t reg; - reg = nlm_read_pic_reg(base, PIC_IRT(irt)); - nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31)); + if (cpu_is_xlp9xx()) { + reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt)); + reg &= ~((uint64_t)1 << 22); + nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg); + } else { + reg = nlm_read_pic_reg(base, PIC_IRT(irt)); + reg &= ~((uint64_t)1 << 31); + nlm_write_pic_reg(base, PIC_IRT(irt), reg); + } } static inline void @@ -360,8 +334,13 @@ nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) { uint64_t ipi; - ipi = (nmi << 31) | (irq << 20); - ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */ + if (cpu_is_xlp9xx()) + ipi = (nmi << 23) | (irq << 24) | + (0/*mcm*/ << 20) | (0/*ptr*/ << 16) | hwt; + else + ipi = ((uint64_t)nmi << 31) | (irq << 20) | + ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); + nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); } @@ -376,9 +355,9 @@ nlm_pic_ack(uint64_t base, int irt_num) } static inline void -nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt) +nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en) { - nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, hwt); + nlm_pic_write_irt_direct(base, irt, en, 0, 0, irq, hwt); } int nlm_irq_to_irt(int irq); diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h index 258e8cc00e9..bc7bddf25be 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h @@ -40,89 +40,171 @@ * @author Netlogic Microsystems * @brief HAL for System configuration registers */ -#define SYS_CHIP_RESET 0x00 -#define SYS_POWER_ON_RESET_CFG 0x01 -#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02 -#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03 -#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04 -#define SYS_EFUSE_DEVICE_CFG3 0x05 -#define SYS_EFUSE_DEVICE_CFG4 0x06 -#define SYS_EFUSE_DEVICE_CFG5 0x07 -#define SYS_EFUSE_DEVICE_CFG6 0x08 -#define SYS_EFUSE_DEVICE_CFG7 0x09 -#define SYS_PLL_CTRL 0x0a -#define SYS_CPU_RESET 0x0b -#define SYS_CPU_NONCOHERENT_MODE 0x0d -#define SYS_CORE_DFS_DIS_CTRL 0x0e -#define SYS_CORE_DFS_RST_CTRL 0x0f -#define SYS_CORE_DFS_BYP_CTRL 0x10 -#define SYS_CORE_DFS_PHA_CTRL 0x11 -#define SYS_CORE_DFS_DIV_INC_CTRL 0x12 -#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13 -#define SYS_CORE_DFS_DIV_VALUE 0x14 -#define SYS_RESET 0x15 -#define SYS_DFS_DIS_CTRL 0x16 -#define SYS_DFS_RST_CTRL 0x17 -#define SYS_DFS_BYP_CTRL 0x18 -#define SYS_DFS_DIV_INC_CTRL 0x19 -#define SYS_DFS_DIV_DEC_CTRL 0x1a -#define SYS_DFS_DIV_VALUE0 0x1b -#define SYS_DFS_DIV_VALUE1 0x1c -#define SYS_SENSE_AMP_DLY 0x1d -#define SYS_SOC_SENSE_AMP_DLY 0x1e -#define SYS_CTRL0 0x1f -#define SYS_CTRL1 0x20 -#define SYS_TIMEOUT_BS1 0x21 -#define SYS_BYTE_SWAP 0x22 -#define SYS_VRM_VID 0x23 -#define SYS_PWR_RAM_CMD 0x24 -#define SYS_PWR_RAM_ADDR 0x25 -#define SYS_PWR_RAM_DATA0 0x26 -#define SYS_PWR_RAM_DATA1 0x27 -#define SYS_PWR_RAM_DATA2 0x28 -#define SYS_PWR_UCODE 0x29 -#define SYS_CPU0_PWR_STATUS 0x2a -#define SYS_CPU1_PWR_STATUS 0x2b -#define SYS_CPU2_PWR_STATUS 0x2c -#define SYS_CPU3_PWR_STATUS 0x2d -#define SYS_CPU4_PWR_STATUS 0x2e -#define SYS_CPU5_PWR_STATUS 0x2f -#define SYS_CPU6_PWR_STATUS 0x30 -#define SYS_CPU7_PWR_STATUS 0x31 -#define SYS_STATUS 0x32 -#define SYS_INT_POL 0x33 -#define SYS_INT_TYPE 0x34 -#define SYS_INT_STATUS 0x35 -#define SYS_INT_MASK0 0x36 -#define SYS_INT_MASK1 0x37 -#define SYS_UCO_S_ECC 0x38 -#define SYS_UCO_M_ECC 0x39 -#define SYS_UCO_ADDR 0x3a -#define SYS_UCO_INSTR 0x3b -#define SYS_MEM_BIST0 0x3c -#define SYS_MEM_BIST1 0x3d -#define SYS_MEM_BIST2 0x3e -#define SYS_MEM_BIST3 0x3f -#define SYS_MEM_BIST4 0x40 -#define SYS_MEM_BIST5 0x41 -#define SYS_MEM_BIST6 0x42 -#define SYS_MEM_BIST7 0x43 -#define SYS_MEM_BIST8 0x44 -#define SYS_MEM_BIST9 0x45 -#define SYS_MEM_BIST10 0x46 -#define SYS_MEM_BIST11 0x47 -#define SYS_MEM_BIST12 0x48 -#define SYS_SCRTCH0 0x49 -#define SYS_SCRTCH1 0x4a -#define SYS_SCRTCH2 0x4b -#define SYS_SCRTCH3 0x4c +#define SYS_CHIP_RESET 0x00 +#define SYS_POWER_ON_RESET_CFG 0x01 +#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02 +#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03 +#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04 +#define SYS_EFUSE_DEVICE_CFG3 0x05 +#define SYS_EFUSE_DEVICE_CFG4 0x06 +#define SYS_EFUSE_DEVICE_CFG5 0x07 +#define SYS_EFUSE_DEVICE_CFG6 0x08 +#define SYS_EFUSE_DEVICE_CFG7 0x09 +#define SYS_PLL_CTRL 0x0a +#define SYS_CPU_RESET 0x0b +#define SYS_CPU_NONCOHERENT_MODE 0x0d +#define SYS_CORE_DFS_DIS_CTRL 0x0e +#define SYS_CORE_DFS_RST_CTRL 0x0f +#define SYS_CORE_DFS_BYP_CTRL 0x10 +#define SYS_CORE_DFS_PHA_CTRL 0x11 +#define SYS_CORE_DFS_DIV_INC_CTRL 0x12 +#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13 +#define SYS_CORE_DFS_DIV_VALUE 0x14 +#define SYS_RESET 0x15 +#define SYS_DFS_DIS_CTRL 0x16 +#define SYS_DFS_RST_CTRL 0x17 +#define SYS_DFS_BYP_CTRL 0x18 +#define SYS_DFS_DIV_INC_CTRL 0x19 +#define SYS_DFS_DIV_DEC_CTRL 0x1a +#define SYS_DFS_DIV_VALUE0 0x1b +#define SYS_DFS_DIV_VALUE1 0x1c +#define SYS_SENSE_AMP_DLY 0x1d +#define SYS_SOC_SENSE_AMP_DLY 0x1e +#define SYS_CTRL0 0x1f +#define SYS_CTRL1 0x20 +#define SYS_TIMEOUT_BS1 0x21 +#define SYS_BYTE_SWAP 0x22 +#define SYS_VRM_VID 0x23 +#define SYS_PWR_RAM_CMD 0x24 +#define SYS_PWR_RAM_ADDR 0x25 +#define SYS_PWR_RAM_DATA0 0x26 +#define SYS_PWR_RAM_DATA1 0x27 +#define SYS_PWR_RAM_DATA2 0x28 +#define SYS_PWR_UCODE 0x29 +#define SYS_CPU0_PWR_STATUS 0x2a +#define SYS_CPU1_PWR_STATUS 0x2b +#define SYS_CPU2_PWR_STATUS 0x2c +#define SYS_CPU3_PWR_STATUS 0x2d +#define SYS_CPU4_PWR_STATUS 0x2e +#define SYS_CPU5_PWR_STATUS 0x2f +#define SYS_CPU6_PWR_STATUS 0x30 +#define SYS_CPU7_PWR_STATUS 0x31 +#define SYS_STATUS 0x32 +#define SYS_INT_POL 0x33 +#define SYS_INT_TYPE 0x34 +#define SYS_INT_STATUS 0x35 +#define SYS_INT_MASK0 0x36 +#define SYS_INT_MASK1 0x37 +#define SYS_UCO_S_ECC 0x38 +#define SYS_UCO_M_ECC 0x39 +#define SYS_UCO_ADDR 0x3a +#define SYS_UCO_INSTR 0x3b +#define SYS_MEM_BIST0 0x3c +#define SYS_MEM_BIST1 0x3d +#define SYS_MEM_BIST2 0x3e +#define SYS_MEM_BIST3 0x3f +#define SYS_MEM_BIST4 0x40 +#define SYS_MEM_BIST5 0x41 +#define SYS_MEM_BIST6 0x42 +#define SYS_MEM_BIST7 0x43 +#define SYS_MEM_BIST8 0x44 +#define SYS_MEM_BIST9 0x45 +#define SYS_MEM_BIST10 0x46 +#define SYS_MEM_BIST11 0x47 +#define SYS_MEM_BIST12 0x48 +#define SYS_SCRTCH0 0x49 +#define SYS_SCRTCH1 0x4a +#define SYS_SCRTCH2 0x4b +#define SYS_SCRTCH3 0x4c + +/* PLL registers XLP2XX */ +#define SYS_CPU_PLL_CTRL0(core) (0x1c0 + (core * 4)) +#define SYS_CPU_PLL_CTRL1(core) (0x1c1 + (core * 4)) +#define SYS_CPU_PLL_CTRL2(core) (0x1c2 + (core * 4)) +#define SYS_CPU_PLL_CTRL3(core) (0x1c3 + (core * 4)) +#define SYS_PLL_CTRL0 0x240 +#define SYS_PLL_CTRL1 0x241 +#define SYS_PLL_CTRL2 0x242 +#define SYS_PLL_CTRL3 0x243 +#define SYS_DMC_PLL_CTRL0 0x244 +#define SYS_DMC_PLL_CTRL1 0x245 +#define SYS_DMC_PLL_CTRL2 0x246 +#define SYS_DMC_PLL_CTRL3 0x247 + +#define SYS_PLL_CTRL0_DEVX(x) (0x248 + (x) * 4) +#define SYS_PLL_CTRL1_DEVX(x) (0x249 + (x) * 4) +#define SYS_PLL_CTRL2_DEVX(x) (0x24a + (x) * 4) +#define SYS_PLL_CTRL3_DEVX(x) (0x24b + (x) * 4) + +#define SYS_CPU_PLL_CHG_CTRL 0x288 +#define SYS_PLL_CHG_CTRL 0x289 +#define SYS_CLK_DEV_DIS 0x28a +#define SYS_CLK_DEV_SEL 0x28b +#define SYS_CLK_DEV_DIV 0x28c +#define SYS_CLK_DEV_CHG 0x28d +#define SYS_CLK_DEV_SEL_REG 0x28e +#define SYS_CLK_DEV_DIV_REG 0x28f +#define SYS_CPU_PLL_LOCK 0x29f +#define SYS_SYS_PLL_LOCK 0x2a0 +#define SYS_PLL_MEM_CMD 0x2a1 +#define SYS_CPU_PLL_MEM_REQ 0x2a2 +#define SYS_SYS_PLL_MEM_REQ 0x2a3 +#define SYS_PLL_MEM_STAT 0x2a4 + +/* PLL registers XLP9XX */ +#define SYS_9XX_CPU_PLL_CTRL0(core) (0xc0 + (core * 4)) +#define SYS_9XX_CPU_PLL_CTRL1(core) (0xc1 + (core * 4)) +#define SYS_9XX_CPU_PLL_CTRL2(core) (0xc2 + (core * 4)) +#define SYS_9XX_CPU_PLL_CTRL3(core) (0xc3 + (core * 4)) +#define SYS_9XX_DMC_PLL_CTRL0 0x140 +#define SYS_9XX_DMC_PLL_CTRL1 0x141 +#define SYS_9XX_DMC_PLL_CTRL2 0x142 +#define SYS_9XX_DMC_PLL_CTRL3 0x143 +#define SYS_9XX_PLL_CTRL0 0x144 +#define SYS_9XX_PLL_CTRL1 0x145 +#define SYS_9XX_PLL_CTRL2 0x146 +#define SYS_9XX_PLL_CTRL3 0x147 + +#define SYS_9XX_PLL_CTRL0_DEVX(x) (0x148 + (x) * 4) +#define SYS_9XX_PLL_CTRL1_DEVX(x) (0x149 + (x) * 4) +#define SYS_9XX_PLL_CTRL2_DEVX(x) (0x14a + (x) * 4) +#define SYS_9XX_PLL_CTRL3_DEVX(x) (0x14b + (x) * 4) + +#define SYS_9XX_CPU_PLL_CHG_CTRL 0x188 +#define SYS_9XX_PLL_CHG_CTRL 0x189 +#define SYS_9XX_CLK_DEV_DIS 0x18a +#define SYS_9XX_CLK_DEV_SEL 0x18b +#define SYS_9XX_CLK_DEV_DIV 0x18d +#define SYS_9XX_CLK_DEV_CHG 0x18f + +/* Registers changed on 9XX */ +#define SYS_9XX_POWER_ON_RESET_CFG 0x00 +#define SYS_9XX_CHIP_RESET 0x01 +#define SYS_9XX_CPU_RESET 0x02 +#define SYS_9XX_CPU_NONCOHERENT_MODE 0x03 + +/* XLP 9XX fuse block registers */ +#define FUSE_9XX_DEVCFG6 0xc6 #ifndef __ASSEMBLY__ -#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v) -#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) -#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) +#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) +#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v) +#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \ + XLP9XX_IO_SYS_OFFSET(node) : XLP_IO_SYS_OFFSET(node)) +#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) + +/* XLP9XX fuse block */ +#define nlm_get_fuse_pcibase(node) \ + nlm_pcicfg_base(XLP9XX_IO_FUSE_OFFSET(node)) +#define nlm_get_fuse_regbase(node) \ + (nlm_get_fuse_pcibase(node) + XLP_IO_PCI_HDRSZ) + +#define nlm_get_clock_pcibase(node) \ + nlm_pcicfg_base(XLP9XX_IO_CLOCK_OFFSET(node)) +#define nlm_get_clock_regbase(node) \ + (nlm_get_clock_pcibase(node) + XLP_IO_PCI_HDRSZ) +unsigned int nlm_get_pic_frequency(int node); #endif #endif diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h index 6a7046ca094..a6c54424dd9 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/uart.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/uart.h @@ -91,10 +91,11 @@ #if !defined(LOCORE) && !defined(__ASSEMBLY__) -#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v) +#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r) +#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v) #define nlm_get_uart_pcibase(node, inst) \ - nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst)) + nlm_pcicfg_base(cpu_is_xlp9xx() ? XLP9XX_IO_UART_OFFSET(node) : \ + XLP_IO_UART_OFFSET(node, inst)) #define nlm_get_uart_regbase(node, inst) \ (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) diff --git a/arch/mips/include/asm/netlogic/xlp-hal/usb.h b/arch/mips/include/asm/netlogic/xlp-hal/usb.h deleted file mode 100644 index a9cd350dfb6..00000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/usb.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2003-2012 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __NLM_HAL_USB_H__ -#define __NLM_HAL_USB_H__ - -#define USB_CTL_0 0x01 -#define USB_PHY_0 0x0A -#define USB_PHY_RESET 0x01 -#define USB_PHY_PORT_RESET_0 0x10 -#define USB_PHY_PORT_RESET_1 0x20 -#define USB_CONTROLLER_RESET 0x01 -#define USB_INT_STATUS 0x0E -#define USB_INT_EN 0x0F -#define USB_PHY_INTERRUPT_EN 0x01 -#define USB_OHCI_INTERRUPT_EN 0x02 -#define USB_OHCI_INTERRUPT1_EN 0x04 -#define USB_OHCI_INTERRUPT2_EN 0x08 -#define USB_CTRL_INTERRUPT_EN 0x10 - -#ifndef __ASSEMBLY__ - -#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v) -#define nlm_get_usb_pcibase(node, inst) \ - nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst)) -#define nlm_get_usb_hcd_base(node, inst) \ - nlm_xkphys_map_pcibar0(nlm_get_usb_pcibase(node, inst)) -#define nlm_get_usb_regbase(node, inst) \ - (nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) - -#endif -#endif /* __NLM_HAL_USB_H__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h index 7e47209327a..a862b93223c 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h @@ -37,19 +37,49 @@ #define PIC_UART_0_IRQ 17 #define PIC_UART_1_IRQ 18 -#define PIC_PCIE_LINK_0_IRQ 19 -#define PIC_PCIE_LINK_1_IRQ 20 -#define PIC_PCIE_LINK_2_IRQ 21 -#define PIC_PCIE_LINK_3_IRQ 22 + +#define PIC_PCIE_LINK_LEGACY_IRQ_BASE 19 +#define PIC_PCIE_LINK_LEGACY_IRQ(i) (19 + (i)) + #define PIC_EHCI_0_IRQ 23 #define PIC_EHCI_1_IRQ 24 #define PIC_OHCI_0_IRQ 25 #define PIC_OHCI_1_IRQ 26 #define PIC_OHCI_2_IRQ 27 #define PIC_OHCI_3_IRQ 28 +#define PIC_2XX_XHCI_0_IRQ 23 +#define PIC_2XX_XHCI_1_IRQ 24 +#define PIC_2XX_XHCI_2_IRQ 25 +#define PIC_9XX_XHCI_0_IRQ 23 +#define PIC_9XX_XHCI_1_IRQ 24 + #define PIC_MMC_IRQ 29 #define PIC_I2C_0_IRQ 30 #define PIC_I2C_1_IRQ 31 +#define PIC_I2C_2_IRQ 32 +#define PIC_I2C_3_IRQ 33 +#define PIC_SPI_IRQ 34 +#define PIC_NAND_IRQ 37 +#define PIC_SATA_IRQ 38 +#define PIC_GPIO_IRQ 39 + +#define PIC_PCIE_LINK_MSI_IRQ_BASE 44 /* 44 - 47 MSI IRQ */ +#define PIC_PCIE_LINK_MSI_IRQ(i) (44 + (i)) + +/* MSI-X with second link-level dispatch */ +#define PIC_PCIE_MSIX_IRQ_BASE 48 /* 48 - 51 MSI-X IRQ */ +#define PIC_PCIE_MSIX_IRQ(i) (48 + (i)) + +/* XLP9xx and XLP8xx has 128 and 32 MSIX vectors respectively */ +#define NLM_MSIX_VEC_BASE 96 /* 96 - 223 - MSIX mapped */ +#define NLM_MSI_VEC_BASE 224 /* 224 -351 - MSI mapped */ + +#define NLM_PIC_INDIRECT_VEC_BASE 512 +#define NLM_GPIO_VEC_BASE 768 + +#define PIC_IRQ_BASE 8 +#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE +#define PIC_IRT_LAST_IRQ 63 #ifndef __ASSEMBLY__ @@ -59,6 +89,30 @@ void xlp_wakeup_secondary_cpus(void); void xlp_mmu_init(void); void nlm_hal_init(void); +int xlp_get_dram_map(int n, uint64_t *dram_map); + +struct pci_dev; +int xlp_socdev_to_node(const struct pci_dev *dev); + +/* Device tree related */ +void xlp_early_init_devtree(void); +void *xlp_dt_init(void *fdtp); + +static inline int cpu_is_xlpii(void) +{ + int chip = read_c0_prid() & PRID_IMP_MASK; + + return chip == PRID_IMP_NETLOGIC_XLP2XX || + chip == PRID_IMP_NETLOGIC_XLP9XX || + chip == PRID_IMP_NETLOGIC_XLP5XX; +} + +static inline int cpu_is_xlp9xx(void) +{ + int chip = read_c0_prid() & PRID_IMP_MASK; + return chip == PRID_IMP_NETLOGIC_XLP9XX || + chip == PRID_IMP_NETLOGIC_XLP5XX; +} #endif /* !__ASSEMBLY__ */ #endif /* _ASM_NLM_XLP_H */ diff --git a/arch/mips/include/asm/netlogic/xlr/fmn.h b/arch/mips/include/asm/netlogic/xlr/fmn.h index 68d5167c86b..5604db3d183 100644 --- a/arch/mips/include/asm/netlogic/xlr/fmn.h +++ b/arch/mips/include/asm/netlogic/xlr/fmn.h @@ -38,108 +38,108 @@ #include <asm/netlogic/mips-extns.h> /* for COP2 access */ /* Station IDs */ -#define FMN_STNID_CPU0 0x00 -#define FMN_STNID_CPU1 0x08 -#define FMN_STNID_CPU2 0x10 -#define FMN_STNID_CPU3 0x18 -#define FMN_STNID_CPU4 0x20 -#define FMN_STNID_CPU5 0x28 -#define FMN_STNID_CPU6 0x30 -#define FMN_STNID_CPU7 0x38 - -#define FMN_STNID_XGS0_TX 64 -#define FMN_STNID_XMAC0_00_TX 64 -#define FMN_STNID_XMAC0_01_TX 65 -#define FMN_STNID_XMAC0_02_TX 66 -#define FMN_STNID_XMAC0_03_TX 67 -#define FMN_STNID_XMAC0_04_TX 68 -#define FMN_STNID_XMAC0_05_TX 69 -#define FMN_STNID_XMAC0_06_TX 70 -#define FMN_STNID_XMAC0_07_TX 71 -#define FMN_STNID_XMAC0_08_TX 72 -#define FMN_STNID_XMAC0_09_TX 73 -#define FMN_STNID_XMAC0_10_TX 74 -#define FMN_STNID_XMAC0_11_TX 75 -#define FMN_STNID_XMAC0_12_TX 76 -#define FMN_STNID_XMAC0_13_TX 77 -#define FMN_STNID_XMAC0_14_TX 78 -#define FMN_STNID_XMAC0_15_TX 79 - -#define FMN_STNID_XGS1_TX 80 -#define FMN_STNID_XMAC1_00_TX 80 -#define FMN_STNID_XMAC1_01_TX 81 -#define FMN_STNID_XMAC1_02_TX 82 -#define FMN_STNID_XMAC1_03_TX 83 -#define FMN_STNID_XMAC1_04_TX 84 -#define FMN_STNID_XMAC1_05_TX 85 -#define FMN_STNID_XMAC1_06_TX 86 -#define FMN_STNID_XMAC1_07_TX 87 -#define FMN_STNID_XMAC1_08_TX 88 -#define FMN_STNID_XMAC1_09_TX 89 -#define FMN_STNID_XMAC1_10_TX 90 -#define FMN_STNID_XMAC1_11_TX 91 -#define FMN_STNID_XMAC1_12_TX 92 -#define FMN_STNID_XMAC1_13_TX 93 -#define FMN_STNID_XMAC1_14_TX 94 -#define FMN_STNID_XMAC1_15_TX 95 - -#define FMN_STNID_GMAC 96 -#define FMN_STNID_GMACJFR_0 96 -#define FMN_STNID_GMACRFR_0 97 -#define FMN_STNID_GMACTX0 98 -#define FMN_STNID_GMACTX1 99 -#define FMN_STNID_GMACTX2 100 -#define FMN_STNID_GMACTX3 101 -#define FMN_STNID_GMACJFR_1 102 -#define FMN_STNID_GMACRFR_1 103 - -#define FMN_STNID_DMA 104 -#define FMN_STNID_DMA_0 104 -#define FMN_STNID_DMA_1 105 -#define FMN_STNID_DMA_2 106 -#define FMN_STNID_DMA_3 107 - -#define FMN_STNID_XGS0FR 112 -#define FMN_STNID_XMAC0JFR 112 -#define FMN_STNID_XMAC0RFR 113 - -#define FMN_STNID_XGS1FR 114 -#define FMN_STNID_XMAC1JFR 114 -#define FMN_STNID_XMAC1RFR 115 -#define FMN_STNID_SEC 120 -#define FMN_STNID_SEC0 120 -#define FMN_STNID_SEC1 121 -#define FMN_STNID_SEC2 122 -#define FMN_STNID_SEC3 123 -#define FMN_STNID_PK0 124 -#define FMN_STNID_SEC_RSA 124 -#define FMN_STNID_SEC_RSVD0 125 -#define FMN_STNID_SEC_RSVD1 126 -#define FMN_STNID_SEC_RSVD2 127 - -#define FMN_STNID_GMAC1 80 -#define FMN_STNID_GMAC1_FR_0 81 -#define FMN_STNID_GMAC1_TX0 82 -#define FMN_STNID_GMAC1_TX1 83 -#define FMN_STNID_GMAC1_TX2 84 -#define FMN_STNID_GMAC1_TX3 85 -#define FMN_STNID_GMAC1_FR_1 87 -#define FMN_STNID_GMAC0 96 -#define FMN_STNID_GMAC0_FR_0 97 -#define FMN_STNID_GMAC0_TX0 98 -#define FMN_STNID_GMAC0_TX1 99 -#define FMN_STNID_GMAC0_TX2 100 -#define FMN_STNID_GMAC0_TX3 101 -#define FMN_STNID_GMAC0_FR_1 103 -#define FMN_STNID_CMP_0 108 -#define FMN_STNID_CMP_1 109 -#define FMN_STNID_CMP_2 110 -#define FMN_STNID_CMP_3 111 -#define FMN_STNID_PCIE_0 116 -#define FMN_STNID_PCIE_1 117 -#define FMN_STNID_PCIE_2 118 -#define FMN_STNID_PCIE_3 119 -#define FMN_STNID_XLS_PK0 121 +#define FMN_STNID_CPU0 0x00 +#define FMN_STNID_CPU1 0x08 +#define FMN_STNID_CPU2 0x10 +#define FMN_STNID_CPU3 0x18 +#define FMN_STNID_CPU4 0x20 +#define FMN_STNID_CPU5 0x28 +#define FMN_STNID_CPU6 0x30 +#define FMN_STNID_CPU7 0x38 + +#define FMN_STNID_XGS0_TX 64 +#define FMN_STNID_XMAC0_00_TX 64 +#define FMN_STNID_XMAC0_01_TX 65 +#define FMN_STNID_XMAC0_02_TX 66 +#define FMN_STNID_XMAC0_03_TX 67 +#define FMN_STNID_XMAC0_04_TX 68 +#define FMN_STNID_XMAC0_05_TX 69 +#define FMN_STNID_XMAC0_06_TX 70 +#define FMN_STNID_XMAC0_07_TX 71 +#define FMN_STNID_XMAC0_08_TX 72 +#define FMN_STNID_XMAC0_09_TX 73 +#define FMN_STNID_XMAC0_10_TX 74 +#define FMN_STNID_XMAC0_11_TX 75 +#define FMN_STNID_XMAC0_12_TX 76 +#define FMN_STNID_XMAC0_13_TX 77 +#define FMN_STNID_XMAC0_14_TX 78 +#define FMN_STNID_XMAC0_15_TX 79 + +#define FMN_STNID_XGS1_TX 80 +#define FMN_STNID_XMAC1_00_TX 80 +#define FMN_STNID_XMAC1_01_TX 81 +#define FMN_STNID_XMAC1_02_TX 82 +#define FMN_STNID_XMAC1_03_TX 83 +#define FMN_STNID_XMAC1_04_TX 84 +#define FMN_STNID_XMAC1_05_TX 85 +#define FMN_STNID_XMAC1_06_TX 86 +#define FMN_STNID_XMAC1_07_TX 87 +#define FMN_STNID_XMAC1_08_TX 88 +#define FMN_STNID_XMAC1_09_TX 89 +#define FMN_STNID_XMAC1_10_TX 90 +#define FMN_STNID_XMAC1_11_TX 91 +#define FMN_STNID_XMAC1_12_TX 92 +#define FMN_STNID_XMAC1_13_TX 93 +#define FMN_STNID_XMAC1_14_TX 94 +#define FMN_STNID_XMAC1_15_TX 95 + +#define FMN_STNID_GMAC 96 +#define FMN_STNID_GMACJFR_0 96 +#define FMN_STNID_GMACRFR_0 97 +#define FMN_STNID_GMACTX0 98 +#define FMN_STNID_GMACTX1 99 +#define FMN_STNID_GMACTX2 100 +#define FMN_STNID_GMACTX3 101 +#define FMN_STNID_GMACJFR_1 102 +#define FMN_STNID_GMACRFR_1 103 + +#define FMN_STNID_DMA 104 +#define FMN_STNID_DMA_0 104 +#define FMN_STNID_DMA_1 105 +#define FMN_STNID_DMA_2 106 +#define FMN_STNID_DMA_3 107 + +#define FMN_STNID_XGS0FR 112 +#define FMN_STNID_XMAC0JFR 112 +#define FMN_STNID_XMAC0RFR 113 + +#define FMN_STNID_XGS1FR 114 +#define FMN_STNID_XMAC1JFR 114 +#define FMN_STNID_XMAC1RFR 115 +#define FMN_STNID_SEC 120 +#define FMN_STNID_SEC0 120 +#define FMN_STNID_SEC1 121 +#define FMN_STNID_SEC2 122 +#define FMN_STNID_SEC3 123 +#define FMN_STNID_PK0 124 +#define FMN_STNID_SEC_RSA 124 +#define FMN_STNID_SEC_RSVD0 125 +#define FMN_STNID_SEC_RSVD1 126 +#define FMN_STNID_SEC_RSVD2 127 + +#define FMN_STNID_GMAC1 80 +#define FMN_STNID_GMAC1_FR_0 81 +#define FMN_STNID_GMAC1_TX0 82 +#define FMN_STNID_GMAC1_TX1 83 +#define FMN_STNID_GMAC1_TX2 84 +#define FMN_STNID_GMAC1_TX3 85 +#define FMN_STNID_GMAC1_FR_1 87 +#define FMN_STNID_GMAC0 96 +#define FMN_STNID_GMAC0_FR_0 97 +#define FMN_STNID_GMAC0_TX0 98 +#define FMN_STNID_GMAC0_TX1 99 +#define FMN_STNID_GMAC0_TX2 100 +#define FMN_STNID_GMAC0_TX3 101 +#define FMN_STNID_GMAC0_FR_1 103 +#define FMN_STNID_CMP_0 108 +#define FMN_STNID_CMP_1 109 +#define FMN_STNID_CMP_2 110 +#define FMN_STNID_CMP_3 111 +#define FMN_STNID_PCIE_0 116 +#define FMN_STNID_PCIE_1 117 +#define FMN_STNID_PCIE_2 118 +#define FMN_STNID_PCIE_3 119 +#define FMN_STNID_XLS_PK0 121 #define nlm_read_c2_cc0(s) __read_32bit_c2_register($16, s) #define nlm_read_c2_cc1(s) __read_32bit_c2_register($17, s) @@ -175,25 +175,29 @@ #define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v) #define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v) -#define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0) -#define nlm_read_c2_config() __read_32bit_c2_register($3, 0) -#define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v) -#define nlm_read_c2_bucksize(b) __read_32bit_c2_register($4, b) -#define nlm_write_c2_bucksize(b, v) __write_32bit_c2_register($4, b, v) - -#define nlm_read_c2_rx_msg0() __read_64bit_c2_register($1, 0) -#define nlm_read_c2_rx_msg1() __read_64bit_c2_register($1, 1) -#define nlm_read_c2_rx_msg2() __read_64bit_c2_register($1, 2) -#define nlm_read_c2_rx_msg3() __read_64bit_c2_register($1, 3) - -#define nlm_write_c2_tx_msg0(v) __write_64bit_c2_register($0, 0, v) -#define nlm_write_c2_tx_msg1(v) __write_64bit_c2_register($0, 1, v) -#define nlm_write_c2_tx_msg2(v) __write_64bit_c2_register($0, 2, v) -#define nlm_write_c2_tx_msg3(v) __write_64bit_c2_register($0, 3, v) - -#define FMN_STN_RX_QSIZE 256 -#define FMN_NSTATIONS 128 -#define FMN_CORE_NBUCKETS 8 +#define nlm_read_c2_status0() __read_32bit_c2_register($2, 0) +#define nlm_write_c2_status0(v) __write_32bit_c2_register($2, 0, v) +#define nlm_read_c2_status1() __read_32bit_c2_register($2, 1) +#define nlm_write_c2_status1(v) __write_32bit_c2_register($2, 1, v) +#define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0) +#define nlm_read_c2_config() __read_32bit_c2_register($3, 0) +#define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v) +#define nlm_read_c2_bucksize(b) __read_32bit_c2_register($4, b) +#define nlm_write_c2_bucksize(b, v) __write_32bit_c2_register($4, b, v) + +#define nlm_read_c2_rx_msg0() __read_64bit_c2_register($1, 0) +#define nlm_read_c2_rx_msg1() __read_64bit_c2_register($1, 1) +#define nlm_read_c2_rx_msg2() __read_64bit_c2_register($1, 2) +#define nlm_read_c2_rx_msg3() __read_64bit_c2_register($1, 3) + +#define nlm_write_c2_tx_msg0(v) __write_64bit_c2_register($0, 0, v) +#define nlm_write_c2_tx_msg1(v) __write_64bit_c2_register($0, 1, v) +#define nlm_write_c2_tx_msg2(v) __write_64bit_c2_register($0, 2, v) +#define nlm_write_c2_tx_msg3(v) __write_64bit_c2_register($0, 3, v) + +#define FMN_STN_RX_QSIZE 256 +#define FMN_NSTATIONS 128 +#define FMN_CORE_NBUCKETS 8 static inline void nlm_msgsnd(unsigned int stid) { @@ -237,7 +241,7 @@ static inline void nlm_msgwait(unsigned int mask) /* * Disable interrupts and enable COP2 access */ -static inline uint32_t nlm_cop2_enable(void) +static inline uint32_t nlm_cop2_enable_irqsave(void) { uint32_t sr = read_c0_status(); @@ -245,7 +249,7 @@ static inline uint32_t nlm_cop2_enable(void) return sr; } -static inline void nlm_cop2_restore(uint32_t sr) +static inline void nlm_cop2_disable_irqrestore(uint32_t sr) { write_c0_status(sr); } @@ -296,7 +300,7 @@ static inline int nlm_fmn_send(unsigned int size, unsigned int code, */ for (i = 0; i < 8; i++) { nlm_msgsnd(dest); - status = nlm_read_c2_status(0); + status = nlm_read_c2_status0(); if ((status & 0x2) == 1) pr_info("Send pending fail!\n"); if ((status & 0x4) == 0) @@ -316,7 +320,7 @@ static inline int nlm_fmn_receive(int bucket, int *size, int *code, int *stid, /* wait for load pending to clear */ do { - status = nlm_read_c2_status(1); + status = nlm_read_c2_status0(); } while ((status & 0x08) != 0); /* receive error bits */ diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h index 2e768f032e8..ff4533d6ee6 100644 --- a/arch/mips/include/asm/netlogic/xlr/iomap.h +++ b/arch/mips/include/asm/netlogic/xlr/iomap.h @@ -35,66 +35,66 @@ #ifndef _ASM_NLM_IOMAP_H #define _ASM_NLM_IOMAP_H -#define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000) -#define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000 -#define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000 -#define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000 -#define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000 -#define NETLOGIC_IO_PIC_OFFSET 0x08000 -#define NETLOGIC_IO_UART_0_OFFSET 0x14000 -#define NETLOGIC_IO_UART_1_OFFSET 0x15100 +#define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000) +#define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000 +#define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000 +#define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000 +#define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000 +#define NETLOGIC_IO_PIC_OFFSET 0x08000 +#define NETLOGIC_IO_UART_0_OFFSET 0x14000 +#define NETLOGIC_IO_UART_1_OFFSET 0x15100 -#define NETLOGIC_IO_SIZE 0x1000 +#define NETLOGIC_IO_SIZE 0x1000 -#define NETLOGIC_IO_BRIDGE_OFFSET 0x00000 +#define NETLOGIC_IO_BRIDGE_OFFSET 0x00000 -#define NETLOGIC_IO_RLD2_CHN0_OFFSET 0x05000 -#define NETLOGIC_IO_RLD2_CHN1_OFFSET 0x06000 +#define NETLOGIC_IO_RLD2_CHN0_OFFSET 0x05000 +#define NETLOGIC_IO_RLD2_CHN1_OFFSET 0x06000 -#define NETLOGIC_IO_SRAM_OFFSET 0x07000 +#define NETLOGIC_IO_SRAM_OFFSET 0x07000 -#define NETLOGIC_IO_PCIX_OFFSET 0x09000 -#define NETLOGIC_IO_HT_OFFSET 0x0A000 +#define NETLOGIC_IO_PCIX_OFFSET 0x09000 +#define NETLOGIC_IO_HT_OFFSET 0x0A000 -#define NETLOGIC_IO_SECURITY_OFFSET 0x0B000 +#define NETLOGIC_IO_SECURITY_OFFSET 0x0B000 -#define NETLOGIC_IO_GMAC_0_OFFSET 0x0C000 -#define NETLOGIC_IO_GMAC_1_OFFSET 0x0D000 -#define NETLOGIC_IO_GMAC_2_OFFSET 0x0E000 -#define NETLOGIC_IO_GMAC_3_OFFSET 0x0F000 +#define NETLOGIC_IO_GMAC_0_OFFSET 0x0C000 +#define NETLOGIC_IO_GMAC_1_OFFSET 0x0D000 +#define NETLOGIC_IO_GMAC_2_OFFSET 0x0E000 +#define NETLOGIC_IO_GMAC_3_OFFSET 0x0F000 /* XLS devices */ -#define NETLOGIC_IO_GMAC_4_OFFSET 0x20000 -#define NETLOGIC_IO_GMAC_5_OFFSET 0x21000 -#define NETLOGIC_IO_GMAC_6_OFFSET 0x22000 -#define NETLOGIC_IO_GMAC_7_OFFSET 0x23000 +#define NETLOGIC_IO_GMAC_4_OFFSET 0x20000 +#define NETLOGIC_IO_GMAC_5_OFFSET 0x21000 +#define NETLOGIC_IO_GMAC_6_OFFSET 0x22000 +#define NETLOGIC_IO_GMAC_7_OFFSET 0x23000 -#define NETLOGIC_IO_PCIE_0_OFFSET 0x1E000 -#define NETLOGIC_IO_PCIE_1_OFFSET 0x1F000 -#define NETLOGIC_IO_SRIO_0_OFFSET 0x1E000 -#define NETLOGIC_IO_SRIO_1_OFFSET 0x1F000 +#define NETLOGIC_IO_PCIE_0_OFFSET 0x1E000 +#define NETLOGIC_IO_PCIE_1_OFFSET 0x1F000 +#define NETLOGIC_IO_SRIO_0_OFFSET 0x1E000 +#define NETLOGIC_IO_SRIO_1_OFFSET 0x1F000 -#define NETLOGIC_IO_USB_0_OFFSET 0x24000 -#define NETLOGIC_IO_USB_1_OFFSET 0x25000 +#define NETLOGIC_IO_USB_0_OFFSET 0x24000 +#define NETLOGIC_IO_USB_1_OFFSET 0x25000 -#define NETLOGIC_IO_COMP_OFFSET 0x1D000 +#define NETLOGIC_IO_COMP_OFFSET 0x1D000 /* end XLS devices */ /* XLR devices */ -#define NETLOGIC_IO_SPI4_0_OFFSET 0x10000 -#define NETLOGIC_IO_XGMAC_0_OFFSET 0x11000 -#define NETLOGIC_IO_SPI4_1_OFFSET 0x12000 -#define NETLOGIC_IO_XGMAC_1_OFFSET 0x13000 +#define NETLOGIC_IO_SPI4_0_OFFSET 0x10000 +#define NETLOGIC_IO_XGMAC_0_OFFSET 0x11000 +#define NETLOGIC_IO_SPI4_1_OFFSET 0x12000 +#define NETLOGIC_IO_XGMAC_1_OFFSET 0x13000 /* end XLR devices */ -#define NETLOGIC_IO_I2C_0_OFFSET 0x16000 -#define NETLOGIC_IO_I2C_1_OFFSET 0x17000 +#define NETLOGIC_IO_I2C_0_OFFSET 0x16000 +#define NETLOGIC_IO_I2C_1_OFFSET 0x17000 -#define NETLOGIC_IO_GPIO_OFFSET 0x18000 -#define NETLOGIC_IO_FLASH_OFFSET 0x19000 -#define NETLOGIC_IO_TB_OFFSET 0x1C000 +#define NETLOGIC_IO_GPIO_OFFSET 0x18000 +#define NETLOGIC_IO_FLASH_OFFSET 0x19000 +#define NETLOGIC_IO_TB_OFFSET 0x1C000 -#define NETLOGIC_CPLD_OFFSET KSEG1ADDR(0x1d840000) +#define NETLOGIC_CPLD_OFFSET KSEG1ADDR(0x1d840000) /* * Base Address (Virtual) of the PCI Config address space @@ -102,8 +102,8 @@ * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes * ie 1<<24 = 16M */ -#define DEFAULT_PCI_CONFIG_BASE 0x18000000 -#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 -#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 +#define DEFAULT_PCI_CONFIG_BASE 0x18000000 +#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 +#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 #endif diff --git a/arch/mips/include/asm/netlogic/xlr/msidef.h b/arch/mips/include/asm/netlogic/xlr/msidef.h index 7e39d40be4f..c95d18edf12 100644 --- a/arch/mips/include/asm/netlogic/xlr/msidef.h +++ b/arch/mips/include/asm/netlogic/xlr/msidef.h @@ -45,21 +45,21 @@ */ #define MSI_DATA_VECTOR_SHIFT 0 -#define MSI_DATA_VECTOR_MASK 0x000000ff +#define MSI_DATA_VECTOR_MASK 0x000000ff #define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & \ MSI_DATA_VECTOR_MASK) #define MSI_DATA_DELIVERY_MODE_SHIFT 8 -#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT) -#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT) +#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT) +#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT) #define MSI_DATA_LEVEL_SHIFT 14 #define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT) #define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT) #define MSI_DATA_TRIGGER_SHIFT 15 -#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT) -#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT) +#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT) +#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT) /* * Shift/mask fields for msi address @@ -69,16 +69,16 @@ #define MSI_ADDR_BASE_LO 0xfee00000 #define MSI_ADDR_DEST_MODE_SHIFT 2 -#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT) +#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT) #define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT) #define MSI_ADDR_REDIRECTION_SHIFT 3 -#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT) -#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT) +#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT) +#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT) #define MSI_ADDR_DEST_ID_SHIFT 12 #define MSI_ADDR_DEST_ID_MASK 0x00ffff0 -#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \ +#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \ MSI_ADDR_DEST_ID_MASK) #endif /* ASM_RMI_MSIDEF_H */ diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h index 9a691b1f91b..3c80a75233b 100644 --- a/arch/mips/include/asm/netlogic/xlr/pic.h +++ b/arch/mips/include/asm/netlogic/xlr/pic.h @@ -35,10 +35,13 @@ #ifndef _ASM_NLM_XLR_PIC_H #define _ASM_NLM_XLR_PIC_H -#define PIC_CLKS_PER_SEC 66666666ULL +#define PIC_CLK_HZ 66666666 +#define pic_timer_freq() PIC_CLK_HZ + /* PIC hardware interrupt numbers */ #define PIC_IRT_WD_INDEX 0 #define PIC_IRT_TIMER_0_INDEX 1 +#define PIC_IRT_TIMER_INDEX(i) ((i) + PIC_IRT_TIMER_0_INDEX) #define PIC_IRT_TIMER_1_INDEX 2 #define PIC_IRT_TIMER_2_INDEX 3 #define PIC_IRT_TIMER_3_INDEX 4 @@ -99,6 +102,7 @@ /* PIC Registers */ #define PIC_CTRL 0x00 +#define PIC_CTRL_STE 8 /* timer enable start bit */ #define PIC_IPI 0x04 #define PIC_INT_ACK 0x06 @@ -116,7 +120,7 @@ #define PIC_TIMER_COUNT_0_BASE 0x120 #define PIC_TIMER_COUNT_1_BASE 0x130 -#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr)) +#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr)) #define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr)) #define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i)) @@ -130,9 +134,9 @@ * 8-39. This leaves the IRQ 0-7 for cpu interrupts like * count/compare and FMN */ -#define PIC_IRQ_BASE 8 -#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i)) -#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE) +#define PIC_IRQ_BASE 8 +#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i)) +#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE) #define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE #define PIC_WD_IRQ PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX) @@ -168,7 +172,7 @@ #define PIC_BRIDGE_AERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX) #define PIC_BRIDGE_BERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX) #define PIC_BRIDGE_TB_XLR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX) -#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX) +#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX) /* XLS defines */ #define PIC_GMAC_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX) #define PIC_GMAC_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX) @@ -251,12 +255,52 @@ nlm_pic_ack(uint64_t base, int irt) } static inline void -nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt) +nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en) { nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt)); /* local scheduling, invalid, level by default */ nlm_write_reg(base, PIC_IRT_1(irt), - (1 << 30) | (1 << 6) | irq); + (en << 30) | (1 << 6) | irq); +} + +static inline uint64_t +nlm_pic_read_timer(uint64_t base, int timer) +{ + uint32_t up1, up2, low; + + up1 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer)); + low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); + up2 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer)); + + if (up1 != up2) /* wrapped, get the new low */ + low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); + return ((uint64_t)up2 << 32) | low; + +} + +static inline uint32_t +nlm_pic_read_timer32(uint64_t base, int timer) +{ + return nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); +} + +static inline void +nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu) +{ + uint32_t up, low; + uint64_t pic_ctrl = nlm_read_reg(base, PIC_CTRL); + int en; + + en = (irq > 0); + up = value >> 32; + low = value & 0xFFFFFFFF; + nlm_write_reg(base, PIC_TIMER_MAXVAL_0(timer), low); + nlm_write_reg(base, PIC_TIMER_MAXVAL_1(timer), up); + nlm_pic_init_irt(base, PIC_IRT_TIMER_INDEX(timer), irq, cpu, 0); + + /* enable the timer */ + pic_ctrl |= (1 << (PIC_CTRL_STE + timer)); + nlm_write_reg(base, PIC_CTRL, pic_ctrl); } #endif #endif /* _ASM_NLM_XLR_PIC_H */ diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h index c1667e0c272..ceb991ca843 100644 --- a/arch/mips/include/asm/netlogic/xlr/xlr.h +++ b/arch/mips/include/asm/netlogic/xlr/xlr.h @@ -35,11 +35,6 @@ #ifndef _ASM_NLM_XLR_H #define _ASM_NLM_XLR_H -/* Platform UART functions */ -struct uart_port; -unsigned int nlm_xlr_uart_in(struct uart_port *, int); -void nlm_xlr_uart_out(struct uart_port *, int, int); - /* SMP helpers */ void xlr_wakeup_secondary_cpus(void); diff --git a/arch/mips/include/asm/nile4.h b/arch/mips/include/asm/nile4.h index af0e51a9f68..99e97f8bfbc 100644 --- a/arch/mips/include/asm/nile4.h +++ b/arch/mips/include/asm/nile4.h @@ -1,8 +1,8 @@ /* * asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions * - * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> - * Sony Software Development Center Europe (SDCE), Brussels + * Copyright (C) 2000 Geert Uytterhoeven <geert@linux-m68k.org> + * Sony Software Development Center Europe (SDCE), Brussels * * This file is based on the following documentation: * @@ -17,7 +17,7 @@ /* - * Physical Device Address Registers (PDARs) + * Physical Device Address Registers (PDARs) */ #define NILE4_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */ @@ -37,7 +37,7 @@ /* - * CPU Interface Registers + * CPU Interface Registers */ #define NILE4_CPUSTAT 0x0080 /* CPU Status [R/W] */ @@ -50,7 +50,7 @@ /* - * Memory-Interface Registers + * Memory-Interface Registers */ #define NILE4_MEMCTRL 0x00C0 /* Memory Control */ @@ -59,7 +59,7 @@ /* - * PCI-Bus Registers + * PCI-Bus Registers */ #define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */ @@ -70,7 +70,7 @@ /* - * Local-Bus Registers + * Local-Bus Registers */ #define NILE4_LCNFG 0x0100 /* Local Bus Configuration [R/W] */ @@ -88,7 +88,7 @@ /* - * DMA Registers + * DMA Registers */ #define NILE4_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */ @@ -100,7 +100,7 @@ /* - * Timer Registers + * Timer Registers */ #define NILE4_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */ @@ -114,7 +114,7 @@ /* - * PCI Configuration Space Registers + * PCI Configuration Space Registers */ #define NILE4_PCI_BASE 0x0200 @@ -153,10 +153,10 @@ /* - * Serial-Port Registers + * Serial-Port Registers */ -#define NILE4_UART_BASE 0x0300 +#define NILE4_UART_BASE 0x0300 #define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */ #define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */ @@ -175,7 +175,7 @@ /* - * Interrupt Lines + * Interrupt Lines */ #define NILE4_INT_CPCE 0 /* CPU-Interface Parity-Error Interrupt */ @@ -185,7 +185,7 @@ #define NILE4_INT_UART 4 /* UART Interrupt */ #define NILE4_INT_WDOG 5 /* Watchdog Timer Interrupt */ #define NILE4_INT_GPT 6 /* General-Purpose Timer Interrupt */ -#define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */ +#define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */ #define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */ #define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */ #define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */ @@ -197,7 +197,7 @@ /* - * Nile 4 Register Access + * Nile 4 Register Access */ static inline void nile4_sync(void) @@ -247,7 +247,7 @@ static inline u8 nile4_in8(u32 offset) /* - * Physical Device Address Registers + * Physical Device Address Registers */ extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width, @@ -255,7 +255,7 @@ extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width, /* - * PCI Master Registers + * PCI Master Registers */ #define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */ @@ -265,9 +265,9 @@ extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width, /* - * PCI Address Spaces + * PCI Address Spaces * - * Note that these are multiplexed using PCIINIT[01]! + * Note that these are multiplexed using PCIINIT[01]! */ #define NILE4_PCI_IO_BASE 0xa6000000 @@ -280,7 +280,7 @@ extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr); /* - * Interrupt Programming + * Interrupt Programming */ #define NUM_I8259_INTERRUPTS 16 diff --git a/arch/mips/include/asm/octeon/cvmx-address.h b/arch/mips/include/asm/octeon/cvmx-address.h index 3c74d826e2e..e2d874e681f 100644 --- a/arch/mips/include/asm/octeon/cvmx-address.h +++ b/arch/mips/include/asm/octeon/cvmx-address.h @@ -84,20 +84,20 @@ typedef enum { * Octeon-I HW never interprets this X (<39:36> reserved * for future expansion), software should set to 0. * - * - 0x0 XXX0 0000 0000 to DRAM Cached + * - 0x0 XXX0 0000 0000 to DRAM Cached * - 0x0 XXX0 0FFF FFFF * - * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000 - * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF) + * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000 + * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF) * - * - 0x0 XXX0 2000 0000 to DRAM Cached + * - 0x0 XXX0 2000 0000 to DRAM Cached * - 0x0 XXXF FFFF FFFF * - * - 0x1 00X0 0000 0000 to Boot Bus Uncached + * - 0x1 00X0 0000 0000 to Boot Bus Uncached * - 0x1 00XF FFFF FFFF * - * - 0x1 01X0 0000 0000 to Other NCB Uncached - * - 0x1 FFXF FFFF FFFF devices + * - 0x1 01X0 0000 0000 to Other NCB Uncached + * - 0x1 FFXF FFFF FFFF devices * * Decode of all Octeon addresses */ @@ -129,9 +129,9 @@ typedef union { */ struct { uint64_t R:2; /* CVMX_MIPS_SPACE_XKPHYS in this case */ - uint64_t cca:3; /* ignored by octeon */ + uint64_t cca:3; /* ignored by octeon */ uint64_t mbz:10; - uint64_t pa:49; /* physical address */ + uint64_t pa:49; /* physical address */ } sxkphys; /* physical address */ @@ -253,22 +253,22 @@ typedef union { #define CVMX_OCT_DID_ASX1 23ULL #define CVMX_OCT_DID_IOB 30ULL -#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL) -#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL) -#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL) -#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL) -#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL) +#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL) +#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL) +#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL) +#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL) +#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL) #define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL) -#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL) -#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL) -#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL) -#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL) -#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL) -#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL) -#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL) -#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL) -#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL) -#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL) -#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL) +#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL) +#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL) +#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL) +#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL) +#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL) +#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL) +#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL) +#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL) +#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL) +#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL) +#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL) #endif /* __CVMX_ADDRESS_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h index 1db1dc2724c..7b7818d1e4d 100644 --- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h +++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h @@ -91,11 +91,11 @@ struct cvmx_bootinfo { #if (CVMX_BOOTINFO_MIN_VER >= 1) /* * Several boards support compact flash on the Octeon boot - * bus. The CF memory spaces may be mapped to different + * bus. The CF memory spaces may be mapped to different * addresses on different boards. These are the physical * addresses, so care must be taken to use the correct * XKPHYS/KSEG0 addressing depending on the application's - * ABI. These values will be 0 if CF is not present. + * ABI. These values will be 0 if CF is not present. */ uint64_t compact_flash_common_base_addr; uint64_t compact_flash_attribute_base_addr; @@ -131,7 +131,7 @@ struct cvmx_bootinfo { #define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC (1ull << 3) /* This flag is set if the TLB mappings are not contained in the * 0x10000000 - 0x20000000 boot bus region. */ -#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING (1ull << 4) +#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING (1ull << 4) #define CVMX_BOOTINFO_CFG_FLAG_BREAK (1ull << 5) #endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */ @@ -164,9 +164,9 @@ enum cvmx_board_types_enum { CVMX_BOARD_TYPE_EBT5600 = 22, CVMX_BOARD_TYPE_EBH5201 = 23, CVMX_BOARD_TYPE_EBT5200 = 24, - CVMX_BOARD_TYPE_CB5600 = 25, - CVMX_BOARD_TYPE_CB5601 = 26, - CVMX_BOARD_TYPE_CB5200 = 27, + CVMX_BOARD_TYPE_CB5600 = 25, + CVMX_BOARD_TYPE_CB5601 = 26, + CVMX_BOARD_TYPE_CB5200 = 27, /* Special 'generic' board type, supports many boards */ CVMX_BOARD_TYPE_GENERIC = 28, CVMX_BOARD_TYPE_EBH5610 = 29, @@ -223,10 +223,11 @@ enum cvmx_board_types_enum { CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000, /* - * Set aside a range for customer private use. The SDK won't + * Set aside a range for customer private use. The SDK won't * use any numbers in this range. */ CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, + CVMX_BOARD_TYPE_UBNT_E100 = 20002, CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, /* The remaining range is reserved for future use. */ @@ -325,6 +326,7 @@ static inline const char *cvmx_board_type_to_string(enum /* Customer private range */ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX) } return "Unsupported Board"; diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h index 42db2be663f..352f1dc2508 100644 --- a/arch/mips/include/asm/octeon/cvmx-bootmem.h +++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h @@ -39,7 +39,7 @@ #define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64 /* minimum alignment of bootmem alloced blocks */ -#define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull) +#define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull) /* Flags for cvmx_bootmem_phy_mem* functions */ /* Allocate from end of block instead of beginning */ @@ -151,8 +151,8 @@ extern void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment); * memory cannot be allocated at the specified address. * * @size: Size in bytes of block to allocate - * @address: Physical address to allocate memory at. If this memory is not - * available, the allocation fails. + * @address: Physical address to allocate memory at. If this memory is not + * available, the allocation fails. * @alignment: Alignment required - must be power of 2 * Returns pointer to block of memory, NULL on error */ @@ -181,7 +181,7 @@ extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment, * @name: name of block to free * * Returns 0 on failure, - * !0 on success + * !0 on success */ @@ -210,9 +210,9 @@ extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, * * @size: Size in bytes of block to allocate * @address: Physical address to allocate memory at. If this - * memory is not available, the allocation fails. + * memory is not available, the allocation fails. * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN - * bytes + * bytes * * Returns a pointer to block of memory, NULL on error */ @@ -249,7 +249,7 @@ extern int cvmx_bootmem_free_named(char *name); * @name: name of block to free * * Returns pointer to named block descriptor on success - * 0 on failure + * 0 on failure */ struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name); @@ -258,20 +258,20 @@ struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name); * (optional) requested address and alignment. * * @req_size: size of region to allocate. All requests are rounded up - * to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size + * to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size * * @address_min: Minimum address that block can occupy. * * @address_max: Specifies the maximum address_min (inclusive) that - * the allocation can use. + * the allocation can use. * * @alignment: Requested alignment of the block. If this alignment - * cannot be met, the allocation fails. This must be a - * power of 2. (Note: Alignment of - * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and - * internally enforced. Requested alignments of less than - * CVMX_BOOTMEM_ALIGNMENT_SIZE are set to - * CVMX_BOOTMEM_ALIGNMENT_SIZE.) + * cannot be met, the allocation fails. This must be a + * power of 2. (Note: Alignment of + * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and + * internally enforced. Requested alignments of less than + * CVMX_BOOTMEM_ALIGNMENT_SIZE are set to + * CVMX_BOOTMEM_ALIGNMENT_SIZE.) * * @flags: Flags to control options for the allocation. * @@ -285,21 +285,21 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, * Allocates a named block of physical memory from the free list, at * (optional) requested address and alignment. * - * @param size size of region to allocate. All requests are rounded - * up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE - * bytes size + * @param size size of region to allocate. All requests are rounded + * up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE + * bytes size * @param min_addr Minimum address that block can occupy. * @param max_addr Specifies the maximum address_min (inclusive) that - * the allocation can use. + * the allocation can use. * @param alignment Requested alignment of the block. If this - * alignment cannot be met, the allocation fails. - * This must be a power of 2. (Note: Alignment of - * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and - * internally enforced. Requested alignments of less - * than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to - * CVMX_BOOTMEM_ALIGNMENT_SIZE.) - * @param name name to assign to named block - * @param flags Flags to control options for the allocation. + * alignment cannot be met, the allocation fails. + * This must be a power of 2. (Note: Alignment of + * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and + * internally enforced. Requested alignments of less + * than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to + * CVMX_BOOTMEM_ALIGNMENT_SIZE.) + * @param name name to assign to named block + * @param flags Flags to control options for the allocation. * * @return physical address of block allocated, or -1 on failure */ @@ -312,14 +312,14 @@ int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr, * Finds a named memory block by name. * Also used for finding an unused entry in the named block table. * - * @name: Name of memory block to find. If NULL pointer given, then - * finds unused descriptor, if available. + * @name: Name of memory block to find. If NULL pointer given, then + * finds unused descriptor, if available. * * @flags: Flags to control options for the allocation. * * Returns Pointer to memory block descriptor, NULL if not found. - * If NULL returned when name parameter is NULL, then no memory - * block descriptors are available. + * If NULL returned when name parameter is NULL, then no memory + * block descriptors are available. */ struct cvmx_bootmem_named_block_desc * cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags); @@ -331,31 +331,31 @@ cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags); * @flags: flags for passing options * * Returns 0 on failure - * 1 on success + * 1 on success */ int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags); /** - * Frees a block to the bootmem allocator list. This must + * Frees a block to the bootmem allocator list. This must * be used with care, as the size provided must match the size * of the block that was allocated, or the list will become * corrupted. * * IMPORTANT: This is only intended to be used as part of named block * frees and initial population of the free memory list. - * * + * * * * @phy_addr: physical address of block * @size: size of block in bytes. * @flags: flags for passing options * * Returns 1 on success, - * 0 on failure + * 0 on failure */ int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags); /** - * Locks the bootmem allocator. This is useful in certain situations + * Locks the bootmem allocator. This is useful in certain situations * where multiple allocations must be made without being interrupted. * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag. * diff --git a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h index fed91125317..024a71b2bff 100644 --- a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h +++ b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h @@ -244,33 +244,33 @@ static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id, ".set noreorder\n" "1:\n" /* Atomic add one to ticket_ptr */ - "ll %[my_ticket], %[ticket_ptr]\n" + "ll %[my_ticket], %[ticket_ptr]\n" /* and store the original value */ - "li %[ticket], 1\n" + "li %[ticket], 1\n" /* in my_ticket */ - "baddu %[ticket], %[my_ticket]\n" - "sc %[ticket], %[ticket_ptr]\n" - "beqz %[ticket], 1b\n" + "baddu %[ticket], %[my_ticket]\n" + "sc %[ticket], %[ticket_ptr]\n" + "beqz %[ticket], 1b\n" " nop\n" /* Load the current now_serving ticket */ - "lbu %[ticket], %[now_serving]\n" + "lbu %[ticket], %[now_serving]\n" "2:\n" /* Jump out if now_serving == my_ticket */ - "beq %[ticket], %[my_ticket], 4f\n" + "beq %[ticket], %[my_ticket], 4f\n" /* Find out how many tickets are in front of me */ - " subu %[ticket], %[my_ticket], %[ticket]\n" + " subu %[ticket], %[my_ticket], %[ticket]\n" /* Use tickets in front of me minus one to delay */ "subu %[ticket], 1\n" /* Delay will be ((tickets in front)-1)*32 loops */ - "cins %[ticket], %[ticket], 5, 7\n" + "cins %[ticket], %[ticket], 5, 7\n" "3:\n" /* Loop here until our ticket might be up */ - "bnez %[ticket], 3b\n" - " subu %[ticket], 1\n" + "bnez %[ticket], 3b\n" + " subu %[ticket], 1\n" /* Jump back up to check out ticket again */ - "b 2b\n" + "b 2b\n" /* Load the current now_serving ticket */ - " lbu %[ticket], %[now_serving]\n" + " lbu %[ticket], %[now_serving]\n" "4:\n" ".set pop\n" : [ticket_ptr] "=m"(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]), @@ -313,9 +313,9 @@ static inline __cvmx_cmd_queue_state_t * * @queue_id: Hardware command queue to write to * @use_locking: - * Use internal locking to ensure exclusive access for queue - * updates. If you don't use this locking you must ensure - * exclusivity some other way. Locking is strongly recommended. + * Use internal locking to ensure exclusive access for queue + * updates. If you don't use this locking you must ensure + * exclusivity some other way. Locking is strongly recommended. * @cmd_count: Number of command words to write * @cmds: Array of commands to write * @@ -411,9 +411,9 @@ static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write(cvmx_cmd_queue_id_t * * @queue_id: Hardware command queue to write to * @use_locking: - * Use internal locking to ensure exclusive access for queue - * updates. If you don't use this locking you must ensure - * exclusivity some other way. Locking is strongly recommended. + * Use internal locking to ensure exclusive access for queue + * updates. If you don't use this locking you must ensure + * exclusivity some other way. Locking is strongly recommended. * @cmd1: Command * @cmd2: Command * @@ -510,9 +510,9 @@ static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t * * @queue_id: Hardware command queue to write to * @use_locking: - * Use internal locking to ensure exclusive access for queue - * updates. If you don't use this locking you must ensure - * exclusivity some other way. Locking is strongly recommended. + * Use internal locking to ensure exclusive access for queue + * updates. If you don't use this locking you must ensure + * exclusivity some other way. Locking is strongly recommended. * @cmd1: Command * @cmd2: Command * @cmd3: Command diff --git a/arch/mips/include/asm/octeon/cvmx-config.h b/arch/mips/include/asm/octeon/cvmx-config.h index 26835d1b43b..f7dd17d0dc2 100644 --- a/arch/mips/include/asm/octeon/cvmx-config.h +++ b/arch/mips/include/asm/octeon/cvmx-config.h @@ -31,13 +31,13 @@ /* Pools in use */ /* Packet buffers */ -#define CVMX_FPA_PACKET_POOL (0) -#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE +#define CVMX_FPA_PACKET_POOL (0) +#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE /* Work queue entrys */ -#define CVMX_FPA_WQE_POOL (1) -#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE +#define CVMX_FPA_WQE_POOL (1) +#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE /* PKO queue command buffers */ -#define CVMX_FPA_OUTPUT_BUFFER_POOL (2) +#define CVMX_FPA_OUTPUT_BUFFER_POOL (2) #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE /************************* FAU allocation ********************************/ @@ -45,7 +45,7 @@ * in order of descending size so that all alignment constraints are * automatically met. The enums are linked so that the following enum * continues allocating where the previous one left off, so the - * numbering within each enum always starts with zero. The macros + * numbering within each enum always starts with zero. The macros * take care of the address increment size, so the values entered * always increase by 1. FAU registers are accessed with byte * addresses. @@ -90,9 +90,9 @@ typedef enum { * be taken into account. */ /* Generic scratch iobdma area */ -#define CVMX_SCR_SCRATCH (0) +#define CVMX_SCR_SCRATCH (0) /* First location available after cvmx-config.h allocated region. */ -#define CVMX_SCR_REG_AVAIL_BASE (8) +#define CVMX_SCR_REG_AVAIL_BASE (8) /* * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve @@ -145,14 +145,14 @@ typedef enum { * 1: include */ #define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP 0 -#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP 0 -#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0 -#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0 -#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0 #define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP 0 -#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP 0 -#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0 -#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0 #define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL 0 #define CVMX_HELPER_INPUT_TAG_INPUT_PORT 1 diff --git a/arch/mips/include/asm/octeon/cvmx-fau.h b/arch/mips/include/asm/octeon/cvmx-fau.h index a6939fc8ba1..ef98f7fc102 100644 --- a/arch/mips/include/asm/octeon/cvmx-fau.h +++ b/arch/mips/include/asm/octeon/cvmx-fau.h @@ -37,13 +37,13 @@ */ #define CVMX_FAU_LOAD_IO_ADDRESS cvmx_build_io_address(0x1e, 0) -#define CVMX_FAU_BITS_SCRADDR 63, 56 -#define CVMX_FAU_BITS_LEN 55, 48 -#define CVMX_FAU_BITS_INEVAL 35, 14 -#define CVMX_FAU_BITS_TAGWAIT 13, 13 -#define CVMX_FAU_BITS_NOADD 13, 13 -#define CVMX_FAU_BITS_SIZE 12, 11 -#define CVMX_FAU_BITS_REGISTER 10, 0 +#define CVMX_FAU_BITS_SCRADDR 63, 56 +#define CVMX_FAU_BITS_LEN 55, 48 +#define CVMX_FAU_BITS_INEVAL 35, 14 +#define CVMX_FAU_BITS_TAGWAIT 13, 13 +#define CVMX_FAU_BITS_NOADD 13, 13 +#define CVMX_FAU_BITS_SIZE 12, 11 +#define CVMX_FAU_BITS_REGISTER 10, 0 typedef enum { CVMX_FAU_OP_SIZE_8 = 0, @@ -109,11 +109,11 @@ typedef union { * Builds a store I/O address for writing to the FAU * * @noadd: 0 = Store value is atomically added to the current value - * 1 = Store value is atomically written over the current value + * 1 = Store value is atomically written over the current value * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. - * - Step by 4 for 32 bit access. - * - Step by 8 for 64 bit access. + * - Step by 2 for 16 bit access. + * - Step by 4 for 32 bit access. + * - Step by 8 for 64 bit access. * Returns Address to store for atomic update */ static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) @@ -127,16 +127,16 @@ static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) * Builds a I/O address for accessing the FAU * * @tagwait: Should the atomic add wait for the current tag switch - * operation to complete. - * - 0 = Don't wait - * - 1 = Wait for tag switch to complete + * operation to complete. + * - 0 = Don't wait + * - 1 = Wait for tag switch to complete * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. - * - Step by 4 for 32 bit access. - * - Step by 8 for 64 bit access. + * - Step by 2 for 16 bit access. + * - Step by 4 for 32 bit access. + * - Step by 8 for 64 bit access. * @value: Signed value to add. - * Note: When performing 32 and 64 bit access, only the low - * 22 bits are available. + * Note: When performing 32 and 64 bit access, only the low + * 22 bits are available. * Returns Address to read from for atomic update */ static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, @@ -152,9 +152,9 @@ static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, * Perform an atomic 64 bit add * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. + * - Step by 8 for 64 bit access. * @value: Signed value to add. - * Note: Only the low 22 bits are available. + * Note: Only the low 22 bits are available. * Returns Value of the register before the update */ static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, @@ -167,9 +167,9 @@ static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, * Perform an atomic 32 bit add * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. + * - Step by 4 for 32 bit access. * @value: Signed value to add. - * Note: Only the low 22 bits are available. + * Note: Only the low 22 bits are available. * Returns Value of the register before the update */ static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, @@ -182,7 +182,7 @@ static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, * Perform an atomic 16 bit add * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. + * - Step by 2 for 16 bit access. * @value: Signed value to add. * Returns Value of the register before the update */ @@ -209,12 +209,12 @@ static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) * completes * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. + * - Step by 8 for 64 bit access. * @value: Signed value to add. - * Note: Only the low 22 bits are available. + * Note: Only the low 22 bits are available. * Returns If a timeout occurs, the error bit will be set. Otherwise - * the value of the register before the update will be - * returned + * the value of the register before the update will be + * returned */ static inline cvmx_fau_tagwait64_t cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value) @@ -233,12 +233,12 @@ cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value) * completes * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. + * - Step by 4 for 32 bit access. * @value: Signed value to add. - * Note: Only the low 22 bits are available. + * Note: Only the low 22 bits are available. * Returns If a timeout occurs, the error bit will be set. Otherwise - * the value of the register before the update will be - * returned + * the value of the register before the update will be + * returned */ static inline cvmx_fau_tagwait32_t cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value) @@ -257,11 +257,11 @@ cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value) * completes * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. + * - Step by 2 for 16 bit access. * @value: Signed value to add. * Returns If a timeout occurs, the error bit will be set. Otherwise - * the value of the register before the update will be - * returned + * the value of the register before the update will be + * returned */ static inline cvmx_fau_tagwait16_t cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value) @@ -282,8 +282,8 @@ cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value) * @reg: FAU atomic register to access. 0 <= reg < 2048. * @value: Signed value to add. * Returns If a timeout occurs, the error bit will be set. Otherwise - * the value of the register before the update will be - * returned + * the value of the register before the update will be + * returned */ static inline cvmx_fau_tagwait8_t cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) @@ -301,21 +301,21 @@ cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) * * @scraddr: Scratch pad byte address to write to. Must be 8 byte aligned * @value: Signed value to add. - * Note: When performing 32 and 64 bit access, only the low - * 22 bits are available. + * Note: When performing 32 and 64 bit access, only the low + * 22 bits are available. * @tagwait: Should the atomic add wait for the current tag switch - * operation to complete. - * - 0 = Don't wait - * - 1 = Wait for tag switch to complete + * operation to complete. + * - 0 = Don't wait + * - 1 = Wait for tag switch to complete * @size: The size of the operation: - * - CVMX_FAU_OP_SIZE_8 (0) = 8 bits - * - CVMX_FAU_OP_SIZE_16 (1) = 16 bits - * - CVMX_FAU_OP_SIZE_32 (2) = 32 bits - * - CVMX_FAU_OP_SIZE_64 (3) = 64 bits + * - CVMX_FAU_OP_SIZE_8 (0) = 8 bits + * - CVMX_FAU_OP_SIZE_16 (1) = 16 bits + * - CVMX_FAU_OP_SIZE_32 (2) = 32 bits + * - CVMX_FAU_OP_SIZE_64 (3) = 64 bits * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. - * - Step by 4 for 32 bit access. - * - Step by 8 for 64 bit access. + * - Step by 2 for 16 bit access. + * - Step by 4 for 32 bit access. + * - Step by 8 for 64 bit access. * Returns Data to write using cvmx_send_single */ static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value, @@ -337,11 +337,11 @@ static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value, * placed in the scratch memory at byte address scraddr. * * @scraddr: Scratch memory byte address to put response in. - * Must be 8 byte aligned. + * Must be 8 byte aligned. * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. + * - Step by 8 for 64 bit access. * @value: Signed value to add. - * Note: Only the low 22 bits are available. + * Note: Only the low 22 bits are available. * Returns Placed in the scratch pad register */ static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr, @@ -357,11 +357,11 @@ static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr, * placed in the scratch memory at byte address scraddr. * * @scraddr: Scratch memory byte address to put response in. - * Must be 8 byte aligned. + * Must be 8 byte aligned. * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. + * - Step by 4 for 32 bit access. * @value: Signed value to add. - * Note: Only the low 22 bits are available. + * Note: Only the low 22 bits are available. * Returns Placed in the scratch pad register */ static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr, @@ -377,9 +377,9 @@ static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr, * placed in the scratch memory at byte address scraddr. * * @scraddr: Scratch memory byte address to put response in. - * Must be 8 byte aligned. + * Must be 8 byte aligned. * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. + * - Step by 2 for 16 bit access. * @value: Signed value to add. * Returns Placed in the scratch pad register */ @@ -396,7 +396,7 @@ static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr, * placed in the scratch memory at byte address scraddr. * * @scraddr: Scratch memory byte address to put response in. - * Must be 8 byte aligned. + * Must be 8 byte aligned. * @reg: FAU atomic register to access. 0 <= reg < 2048. * @value: Signed value to add. * Returns Placed in the scratch pad register @@ -414,14 +414,14 @@ static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr, * switch completes. * * @scraddr: Scratch memory byte address to put response in. Must be - * 8 byte aligned. If a timeout occurs, the error bit (63) - * will be set. Otherwise the value of the register before - * the update will be returned + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. + * - Step by 8 for 64 bit access. * @value: Signed value to add. - * Note: Only the low 22 bits are available. + * Note: Only the low 22 bits are available. * Returns Placed in the scratch pad register */ static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr, @@ -437,14 +437,14 @@ static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr, * switch completes. * * @scraddr: Scratch memory byte address to put response in. Must be - * 8 byte aligned. If a timeout occurs, the error bit (63) - * will be set. Otherwise the value of the register before - * the update will be returned + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. + * - Step by 4 for 32 bit access. * @value: Signed value to add. - * Note: Only the low 22 bits are available. + * Note: Only the low 22 bits are available. * Returns Placed in the scratch pad register */ static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr, @@ -460,12 +460,12 @@ static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr, * switch completes. * * @scraddr: Scratch memory byte address to put response in. Must be - * 8 byte aligned. If a timeout occurs, the error bit (63) - * will be set. Otherwise the value of the register before - * the update will be returned + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. + * - Step by 2 for 16 bit access. * @value: Signed value to add. * * Returns Placed in the scratch pad register @@ -483,9 +483,9 @@ static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr, * switch completes. * * @scraddr: Scratch memory byte address to put response in. Must be - * 8 byte aligned. If a timeout occurs, the error bit (63) - * will be set. Otherwise the value of the register before - * the update will be returned + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned * * @reg: FAU atomic register to access. 0 <= reg < 2048. * @value: Signed value to add. @@ -504,7 +504,7 @@ static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr, * Perform an atomic 64 bit add * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. + * - Step by 8 for 64 bit access. * @value: Signed value to add. */ static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value) @@ -516,7 +516,7 @@ static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value) * Perform an atomic 32 bit add * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. + * - Step by 4 for 32 bit access. * @value: Signed value to add. */ static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value) @@ -528,7 +528,7 @@ static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value) * Perform an atomic 16 bit add * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. + * - Step by 2 for 16 bit access. * @value: Signed value to add. */ static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value) @@ -551,7 +551,7 @@ static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value) * Perform an atomic 64 bit write * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. + * - Step by 8 for 64 bit access. * @value: Signed value to write. */ static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value) @@ -563,7 +563,7 @@ static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value) * Perform an atomic 32 bit write * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. + * - Step by 4 for 32 bit access. * @value: Signed value to write. */ static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value) @@ -575,7 +575,7 @@ static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value) * Perform an atomic 16 bit write * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. + * - Step by 2 for 16 bit access. * @value: Signed value to write. */ static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value) diff --git a/arch/mips/include/asm/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h index 541a1ae02b6..aa26a2ce5a0 100644 --- a/arch/mips/include/asm/octeon/cvmx-fpa.h +++ b/arch/mips/include/asm/octeon/cvmx-fpa.h @@ -39,9 +39,9 @@ #include <asm/octeon/cvmx-address.h> #include <asm/octeon/cvmx-fpa-defs.h> -#define CVMX_FPA_NUM_POOLS 8 +#define CVMX_FPA_NUM_POOLS 8 #define CVMX_FPA_MIN_BLOCK_SIZE 128 -#define CVMX_FPA_ALIGNMENT 128 +#define CVMX_FPA_ALIGNMENT 128 /** * Structure describing the data format used for stores to the FPA. @@ -186,8 +186,8 @@ static inline void *cvmx_fpa_alloc(uint64_t pool) /** * Asynchronously get a new block from the FPA * - * @scr_addr: Local scratch address to put response in. This is a byte address, - * but must be 8 byte aligned. + * @scr_addr: Local scratch address to put response in. This is a byte address, + * but must be 8 byte aligned. * @pool: Pool to get the block from */ static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool) @@ -212,7 +212,7 @@ static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool) * @ptr: Block to free * @pool: Pool to put it in * @num_cache_lines: - * Cache lines to invalidate + * Cache lines to invalidate */ static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool, uint64_t num_cache_lines) @@ -234,7 +234,7 @@ static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool, * @ptr: Block to free * @pool: Pool to put it in * @num_cache_lines: - * Cache lines to invalidate + * Cache lines to invalidate */ static inline void cvmx_fpa_free(void *ptr, uint64_t pool, uint64_t num_cache_lines) @@ -245,7 +245,7 @@ static inline void cvmx_fpa_free(void *ptr, uint64_t pool, CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)); /* * Make sure that any previous writes to memory go out before - * we free this buffer. This also serves as a barrier to + * we free this buffer. This also serves as a barrier to * prevent GCC from reordering operations to after the * free. */ @@ -259,17 +259,17 @@ static inline void cvmx_fpa_free(void *ptr, uint64_t pool, * This can only be called once per pool. Make sure proper * locking enforces this. * - * @pool: Pool to initialize - * 0 <= pool < 8 - * @name: Constant character string to name this pool. - * String is not copied. - * @buffer: Pointer to the block of memory to use. This must be - * accessible by all processors and external hardware. + * @pool: Pool to initialize + * 0 <= pool < 8 + * @name: Constant character string to name this pool. + * String is not copied. + * @buffer: Pointer to the block of memory to use. This must be + * accessible by all processors and external hardware. * @block_size: Size for each block controlled by the FPA * @num_blocks: Number of blocks * * Returns 0 on Success, - * -1 on failure + * -1 on failure */ extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer, uint64_t block_size, uint64_t num_blocks); @@ -282,8 +282,8 @@ extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer, * * @pool: Pool to shutdown * Returns Zero on success - * - Positive is count of missing buffers - * - Negative is too many buffers or corrupted pointers + * - Positive is count of missing buffers + * - Negative is too many buffers or corrupted pointers */ extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool); diff --git a/arch/mips/include/asm/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h index 442f508eaac..893320375ae 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-board.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-board.h @@ -36,6 +36,13 @@ #include <asm/octeon/cvmx-helper.h> +enum cvmx_helper_board_usb_clock_types { + USB_CLOCK_TYPE_REF_12, + USB_CLOCK_TYPE_REF_24, + USB_CLOCK_TYPE_REF_48, + USB_CLOCK_TYPE_CRYSTAL_12, +}; + typedef enum { set_phy_link_flags_autoneg = 0x1, set_phy_link_flags_flow_control_dont_touch = 0x0 << 1, @@ -48,7 +55,7 @@ typedef enum { * Fake IPD port, the RGMII/MII interface may use different PHY, use * this macro to return appropriate MIX address to read the PHY. */ -#define CVMX_HELPER_BOARD_MGMT_IPD_PORT -10 +#define CVMX_HELPER_BOARD_MGMT_IPD_PORT -10 /** * cvmx_override_board_link_get(int ipd_port) is a function @@ -86,10 +93,10 @@ extern int cvmx_helper_board_get_mii_address(int ipd_port); * * @phy_addr: The address of the PHY to program * @link_flags: - * Flags to control autonegotiation. Bit 0 is autonegotiation - * enable/disable to maintain backware compatibility. + * Flags to control autonegotiation. Bit 0 is autonegotiation + * enable/disable to maintain backware compatibility. * @link_info: Link speed to program. If the speed is zero and autonegotiation - * is enabled, all possible negotiation speeds are advertised. + * is enabled, all possible negotiation speeds are advertised. * * Returns Zero on success, negative on failure */ @@ -111,10 +118,10 @@ int cvmx_helper_board_link_set_phy(int phy_addr, * enumeration from the bootloader. * * @ipd_port: IPD input port associated with the port we want to get link - * status for. + * status for. * * Returns The ports link status. If the link isn't fully resolved, this must - * return zero. + * return zero. */ extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port); @@ -134,10 +141,10 @@ extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port); * * @interface: Interface to probe * @supported_ports: - * Number of ports Octeon supports. + * Number of ports Octeon supports. * * Returns Number of ports the actual board supports. Many times this will - * simple be "support_ports". + * simple be "support_ports". */ extern int __cvmx_helper_board_interface_probe(int interface, int supported_ports); @@ -154,4 +161,6 @@ extern int __cvmx_helper_board_interface_probe(int interface, */ extern int __cvmx_helper_board_hardware_enable(int interface); +enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void); + #endif /* __CVMX_HELPER_BOARD_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h index 78295ba0050..4d7a3db3a9f 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h @@ -98,9 +98,9 @@ extern int __cvmx_helper_rgmii_link_set(int ipd_port, * * @ipd_port: IPD/PKO port to loopback. * @enable_internal: - * Non zero if you want internal loopback + * Non zero if you want internal loopback * @enable_external: - * Non zero if you want external loopback + * Non zero if you want external loopback * * Returns Zero on success, negative on failure. */ diff --git a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h index 9a9b6c103ed..4debb1c5153 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h @@ -92,9 +92,9 @@ extern int __cvmx_helper_sgmii_link_set(int ipd_port, * * @ipd_port: IPD/PKO port to loopback. * @enable_internal: - * Non zero if you want internal loopback + * Non zero if you want internal loopback * @enable_external: - * Non zero if you want external loopback + * Non zero if you want external loopback * * Returns Zero on success, negative on failure. */ diff --git a/arch/mips/include/asm/octeon/cvmx-helper-util.h b/arch/mips/include/asm/octeon/cvmx-helper-util.h index 6a6e52fc22c..f446f212bbd 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-util.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-util.h @@ -57,11 +57,11 @@ extern int cvmx_helper_dump_packet(cvmx_wqe_t *work); * * @queue: Input queue to setup RED on (0-7) * @pass_thresh: - * Packets will begin slowly dropping when there are less than - * this many packet buffers free in FPA 0. + * Packets will begin slowly dropping when there are less than + * this many packet buffers free in FPA 0. * @drop_thresh: - * All incomming packets will be dropped when there are less - * than this many free packet buffers in FPA 0. + * All incoming packets will be dropped when there are less + * than this many free packet buffers in FPA 0. * Returns Zero on success. Negative on failure */ extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh, @@ -71,11 +71,11 @@ extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh, * Setup Random Early Drop to automatically begin dropping packets. * * @pass_thresh: - * Packets will begin slowly dropping when there are less than - * this many packet buffers free in FPA 0. + * Packets will begin slowly dropping when there are less than + * this many packet buffers free in FPA 0. * @drop_thresh: - * All incomming packets will be dropped when there are less - * than this many free packet buffers in FPA 0. + * All incoming packets will be dropped when there are less + * than this many free packet buffers in FPA 0. * Returns Zero on success. Negative on failure */ extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh); @@ -84,7 +84,7 @@ extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh); * Get the version of the CVMX libraries. * * Returns Version string. Note this buffer is allocated statically - * and will be shared by all callers. + * and will be shared by all callers. */ extern const char *cvmx_helper_get_version(void); diff --git a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h index f6fbc4f45b5..5e89ed703ea 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h @@ -92,9 +92,9 @@ extern int __cvmx_helper_xaui_link_set(int ipd_port, * * @ipd_port: IPD/PKO port to loopback. * @enable_internal: - * Non zero if you want internal loopback + * Non zero if you want internal loopback * @enable_external: - * Non zero if you want external loopback + * Non zero if you want external loopback * * Returns Zero on success, negative on failure. */ diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h index 691c8142cd4..5a3090dc6f2 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper.h +++ b/arch/mips/include/asm/octeon/cvmx-helper.h @@ -93,12 +93,12 @@ extern void (*cvmx_override_ipd_port_setup) (int ipd_port); /** * This function enables the IPD and also enables the packet interfaces. * The packet interfaces (RGMII and SPI) must be enabled after the - * IPD. This should be called by the user program after any additional + * IPD. This should be called by the user program after any additional * IPD configuration changes are made if CVMX_HELPER_ENABLE_IPD * is not set in the executive-config.h file. * * Returns 0 on success - * -1 on failure + * -1 on failure */ extern int cvmx_helper_ipd_and_packet_input_enable(void); @@ -128,7 +128,7 @@ extern int cvmx_helper_initialize_packet_io_local(void); * @interface: Which interface to return port count for. * * Returns Port count for interface - * -1 for uninitialized interface + * -1 for uninitialized interface */ extern int cvmx_helper_ports_on_interface(int interface); @@ -150,7 +150,7 @@ extern int cvmx_helper_get_number_of_interfaces(void); * @interface: Interface to probe * * Returns Mode of the interface. Unknown or unsupported interfaces return - * DISABLED. + * DISABLED. */ extern cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface); @@ -214,9 +214,9 @@ extern int cvmx_helper_interface_enumerate(int interface); * * @ipd_port: IPD/PKO port to loopback. * @enable_internal: - * Non zero if you want internal loopback + * Non zero if you want internal loopback * @enable_external: - * Non zero if you want external loopback + * Non zero if you want external loopback * * Returns Zero on success, negative on failure. */ diff --git a/arch/mips/include/asm/octeon/cvmx-ipd.h b/arch/mips/include/asm/octeon/cvmx-ipd.h index 115a552c5c7..e13490ebbb2 100644 --- a/arch/mips/include/asm/octeon/cvmx-ipd.h +++ b/arch/mips/include/asm/octeon/cvmx-ipd.h @@ -38,8 +38,8 @@ #include <asm/octeon/cvmx-ipd-defs.h> enum cvmx_ipd_mode { - CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */ - CVMX_IPD_OPC_MODE_STF = 1LL, /* All bloccks into L2 */ + CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */ + CVMX_IPD_OPC_MODE_STF = 1LL, /* All bloccks into L2 */ CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */ CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */ }; @@ -60,17 +60,17 @@ typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t; * * @mbuff_size: Packets buffer size in 8 byte words * @first_mbuff_skip: - * Number of 8 byte words to skip in the first buffer + * Number of 8 byte words to skip in the first buffer * @not_first_mbuff_skip: - * Number of 8 byte words to skip in each following buffer + * Number of 8 byte words to skip in each following buffer * @first_back: Must be same as first_mbuff_skip / 128 * @second_back: - * Must be same as not_first_mbuff_skip / 128 + * Must be same as not_first_mbuff_skip / 128 * @wqe_fpa_pool: - * FPA pool to get work entries from + * FPA pool to get work entries from * @cache_mode: * @back_pres_enable_flag: - * Enable or disable port back pressure + * Enable or disable port back pressure */ static inline void cvmx_ipd_config(uint64_t mbuff_size, uint64_t first_mbuff_skip, diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h index 2c8ff9e33ec..11c0a8fa8eb 100644 --- a/arch/mips/include/asm/octeon/cvmx-l2c.h +++ b/arch/mips/include/asm/octeon/cvmx-l2c.h @@ -33,13 +33,13 @@ #ifndef __CVMX_L2C_H__ #define __CVMX_L2C_H__ -#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */ +#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */ #define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro, use function */ -#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */ +#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */ #define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */ -#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1) +#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1) /* Defines for index aliasing computations */ #define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits()) @@ -67,91 +67,91 @@ union cvmx_l2c_tag { /* L2C Performance Counter events. */ enum cvmx_l2c_event { - CVMX_L2C_EVENT_CYCLES = 0, + CVMX_L2C_EVENT_CYCLES = 0, CVMX_L2C_EVENT_INSTRUCTION_MISS = 1, - CVMX_L2C_EVENT_INSTRUCTION_HIT = 2, - CVMX_L2C_EVENT_DATA_MISS = 3, - CVMX_L2C_EVENT_DATA_HIT = 4, - CVMX_L2C_EVENT_MISS = 5, - CVMX_L2C_EVENT_HIT = 6, - CVMX_L2C_EVENT_VICTIM_HIT = 7, - CVMX_L2C_EVENT_INDEX_CONFLICT = 8, - CVMX_L2C_EVENT_TAG_PROBE = 9, - CVMX_L2C_EVENT_TAG_UPDATE = 10, - CVMX_L2C_EVENT_TAG_COMPLETE = 11, - CVMX_L2C_EVENT_TAG_DIRTY = 12, - CVMX_L2C_EVENT_DATA_STORE_NOP = 13, - CVMX_L2C_EVENT_DATA_STORE_READ = 14, + CVMX_L2C_EVENT_INSTRUCTION_HIT = 2, + CVMX_L2C_EVENT_DATA_MISS = 3, + CVMX_L2C_EVENT_DATA_HIT = 4, + CVMX_L2C_EVENT_MISS = 5, + CVMX_L2C_EVENT_HIT = 6, + CVMX_L2C_EVENT_VICTIM_HIT = 7, + CVMX_L2C_EVENT_INDEX_CONFLICT = 8, + CVMX_L2C_EVENT_TAG_PROBE = 9, + CVMX_L2C_EVENT_TAG_UPDATE = 10, + CVMX_L2C_EVENT_TAG_COMPLETE = 11, + CVMX_L2C_EVENT_TAG_DIRTY = 12, + CVMX_L2C_EVENT_DATA_STORE_NOP = 13, + CVMX_L2C_EVENT_DATA_STORE_READ = 14, CVMX_L2C_EVENT_DATA_STORE_WRITE = 15, - CVMX_L2C_EVENT_FILL_DATA_VALID = 16, - CVMX_L2C_EVENT_WRITE_REQUEST = 17, - CVMX_L2C_EVENT_READ_REQUEST = 18, + CVMX_L2C_EVENT_FILL_DATA_VALID = 16, + CVMX_L2C_EVENT_WRITE_REQUEST = 17, + CVMX_L2C_EVENT_READ_REQUEST = 18, CVMX_L2C_EVENT_WRITE_DATA_VALID = 19, - CVMX_L2C_EVENT_XMC_NOP = 20, - CVMX_L2C_EVENT_XMC_LDT = 21, - CVMX_L2C_EVENT_XMC_LDI = 22, - CVMX_L2C_EVENT_XMC_LDD = 23, - CVMX_L2C_EVENT_XMC_STF = 24, - CVMX_L2C_EVENT_XMC_STT = 25, - CVMX_L2C_EVENT_XMC_STP = 26, - CVMX_L2C_EVENT_XMC_STC = 27, - CVMX_L2C_EVENT_XMC_DWB = 28, - CVMX_L2C_EVENT_XMC_PL2 = 29, - CVMX_L2C_EVENT_XMC_PSL1 = 30, - CVMX_L2C_EVENT_XMC_IOBLD = 31, - CVMX_L2C_EVENT_XMC_IOBST = 32, - CVMX_L2C_EVENT_XMC_IOBDMA = 33, - CVMX_L2C_EVENT_XMC_IOBRSP = 34, - CVMX_L2C_EVENT_XMC_BUS_VALID = 35, - CVMX_L2C_EVENT_XMC_MEM_DATA = 36, - CVMX_L2C_EVENT_XMC_REFL_DATA = 37, - CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38, - CVMX_L2C_EVENT_RSC_NOP = 39, - CVMX_L2C_EVENT_RSC_STDN = 40, - CVMX_L2C_EVENT_RSC_FILL = 41, - CVMX_L2C_EVENT_RSC_REFL = 42, - CVMX_L2C_EVENT_RSC_STIN = 43, - CVMX_L2C_EVENT_RSC_SCIN = 44, - CVMX_L2C_EVENT_RSC_SCFL = 45, - CVMX_L2C_EVENT_RSC_SCDN = 46, - CVMX_L2C_EVENT_RSC_DATA_VALID = 47, - CVMX_L2C_EVENT_RSC_VALID_FILL = 48, - CVMX_L2C_EVENT_RSC_VALID_STRSP = 49, - CVMX_L2C_EVENT_RSC_VALID_REFL = 50, - CVMX_L2C_EVENT_LRF_REQ = 51, - CVMX_L2C_EVENT_DT_RD_ALLOC = 52, - CVMX_L2C_EVENT_DT_WR_INVAL = 53, + CVMX_L2C_EVENT_XMC_NOP = 20, + CVMX_L2C_EVENT_XMC_LDT = 21, + CVMX_L2C_EVENT_XMC_LDI = 22, + CVMX_L2C_EVENT_XMC_LDD = 23, + CVMX_L2C_EVENT_XMC_STF = 24, + CVMX_L2C_EVENT_XMC_STT = 25, + CVMX_L2C_EVENT_XMC_STP = 26, + CVMX_L2C_EVENT_XMC_STC = 27, + CVMX_L2C_EVENT_XMC_DWB = 28, + CVMX_L2C_EVENT_XMC_PL2 = 29, + CVMX_L2C_EVENT_XMC_PSL1 = 30, + CVMX_L2C_EVENT_XMC_IOBLD = 31, + CVMX_L2C_EVENT_XMC_IOBST = 32, + CVMX_L2C_EVENT_XMC_IOBDMA = 33, + CVMX_L2C_EVENT_XMC_IOBRSP = 34, + CVMX_L2C_EVENT_XMC_BUS_VALID = 35, + CVMX_L2C_EVENT_XMC_MEM_DATA = 36, + CVMX_L2C_EVENT_XMC_REFL_DATA = 37, + CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38, + CVMX_L2C_EVENT_RSC_NOP = 39, + CVMX_L2C_EVENT_RSC_STDN = 40, + CVMX_L2C_EVENT_RSC_FILL = 41, + CVMX_L2C_EVENT_RSC_REFL = 42, + CVMX_L2C_EVENT_RSC_STIN = 43, + CVMX_L2C_EVENT_RSC_SCIN = 44, + CVMX_L2C_EVENT_RSC_SCFL = 45, + CVMX_L2C_EVENT_RSC_SCDN = 46, + CVMX_L2C_EVENT_RSC_DATA_VALID = 47, + CVMX_L2C_EVENT_RSC_VALID_FILL = 48, + CVMX_L2C_EVENT_RSC_VALID_STRSP = 49, + CVMX_L2C_EVENT_RSC_VALID_REFL = 50, + CVMX_L2C_EVENT_LRF_REQ = 51, + CVMX_L2C_EVENT_DT_RD_ALLOC = 52, + CVMX_L2C_EVENT_DT_WR_INVAL = 53, CVMX_L2C_EVENT_MAX }; /* L2C Performance Counter events for Octeon2. */ enum cvmx_l2c_tad_event { - CVMX_L2C_TAD_EVENT_NONE = 0, - CVMX_L2C_TAD_EVENT_TAG_HIT = 1, - CVMX_L2C_TAD_EVENT_TAG_MISS = 2, - CVMX_L2C_TAD_EVENT_TAG_NOALLOC = 3, - CVMX_L2C_TAD_EVENT_TAG_VICTIM = 4, - CVMX_L2C_TAD_EVENT_SC_FAIL = 5, - CVMX_L2C_TAD_EVENT_SC_PASS = 6, - CVMX_L2C_TAD_EVENT_LFB_VALID = 7, - CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB = 8, - CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB = 9, - CVMX_L2C_TAD_EVENT_QUAD0_INDEX = 128, - CVMX_L2C_TAD_EVENT_QUAD0_READ = 129, - CVMX_L2C_TAD_EVENT_QUAD0_BANK = 130, - CVMX_L2C_TAD_EVENT_QUAD0_WDAT = 131, - CVMX_L2C_TAD_EVENT_QUAD1_INDEX = 144, - CVMX_L2C_TAD_EVENT_QUAD1_READ = 145, - CVMX_L2C_TAD_EVENT_QUAD1_BANK = 146, - CVMX_L2C_TAD_EVENT_QUAD1_WDAT = 147, - CVMX_L2C_TAD_EVENT_QUAD2_INDEX = 160, - CVMX_L2C_TAD_EVENT_QUAD2_READ = 161, - CVMX_L2C_TAD_EVENT_QUAD2_BANK = 162, - CVMX_L2C_TAD_EVENT_QUAD2_WDAT = 163, - CVMX_L2C_TAD_EVENT_QUAD3_INDEX = 176, - CVMX_L2C_TAD_EVENT_QUAD3_READ = 177, - CVMX_L2C_TAD_EVENT_QUAD3_BANK = 178, - CVMX_L2C_TAD_EVENT_QUAD3_WDAT = 179, + CVMX_L2C_TAD_EVENT_NONE = 0, + CVMX_L2C_TAD_EVENT_TAG_HIT = 1, + CVMX_L2C_TAD_EVENT_TAG_MISS = 2, + CVMX_L2C_TAD_EVENT_TAG_NOALLOC = 3, + CVMX_L2C_TAD_EVENT_TAG_VICTIM = 4, + CVMX_L2C_TAD_EVENT_SC_FAIL = 5, + CVMX_L2C_TAD_EVENT_SC_PASS = 6, + CVMX_L2C_TAD_EVENT_LFB_VALID = 7, + CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB = 8, + CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB = 9, + CVMX_L2C_TAD_EVENT_QUAD0_INDEX = 128, + CVMX_L2C_TAD_EVENT_QUAD0_READ = 129, + CVMX_L2C_TAD_EVENT_QUAD0_BANK = 130, + CVMX_L2C_TAD_EVENT_QUAD0_WDAT = 131, + CVMX_L2C_TAD_EVENT_QUAD1_INDEX = 144, + CVMX_L2C_TAD_EVENT_QUAD1_READ = 145, + CVMX_L2C_TAD_EVENT_QUAD1_BANK = 146, + CVMX_L2C_TAD_EVENT_QUAD1_WDAT = 147, + CVMX_L2C_TAD_EVENT_QUAD2_INDEX = 160, + CVMX_L2C_TAD_EVENT_QUAD2_READ = 161, + CVMX_L2C_TAD_EVENT_QUAD2_BANK = 162, + CVMX_L2C_TAD_EVENT_QUAD2_WDAT = 163, + CVMX_L2C_TAD_EVENT_QUAD3_INDEX = 176, + CVMX_L2C_TAD_EVENT_QUAD3_READ = 177, + CVMX_L2C_TAD_EVENT_QUAD3_BANK = 178, + CVMX_L2C_TAD_EVENT_QUAD3_WDAT = 179, CVMX_L2C_TAD_EVENT_MAX }; @@ -159,10 +159,10 @@ enum cvmx_l2c_tad_event { * Configure one of the four L2 Cache performance counters to capture event * occurrences. * - * @counter: The counter to configure. Range 0..3. - * @event: The type of L2 Cache event occurrence to count. + * @counter: The counter to configure. Range 0..3. + * @event: The type of L2 Cache event occurrence to count. * @clear_on_read: When asserted, any read of the performance counter - * clears the counter. + * clears the counter. * * @note The routine does not clear the counter. */ @@ -184,8 +184,8 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter); * @core: The core processor of interest. * * Returns The mask specifying the partitioning. 0 bits in mask indicates - * the cache 'ways' that a core can evict from. - * -1 on error + * the cache 'ways' that a core can evict from. + * -1 on error */ int cvmx_l2c_get_core_way_partition(uint32_t core); @@ -194,16 +194,16 @@ int cvmx_l2c_get_core_way_partition(uint32_t core); * * @core: The core that the partitioning applies to. * @mask: The partitioning of the ways expressed as a binary - * mask. A 0 bit allows the core to evict cache lines from - * a way, while a 1 bit blocks the core from evicting any - * lines from that way. There must be at least one allowed - * way (0 bit) in the mask. + * mask. A 0 bit allows the core to evict cache lines from + * a way, while a 1 bit blocks the core from evicting any + * lines from that way. There must be at least one allowed + * way (0 bit) in the mask. * * @note If any ways are blocked for all cores and the HW blocks, then - * those ways will never have any cache lines evicted from them. - * All cores and the hardware blocks are free to read from all - * ways regardless of the partitioning. + * those ways will never have any cache lines evicted from them. + * All cores and the hardware blocks are free to read from all + * ways regardless of the partitioning. */ int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask); @@ -211,8 +211,8 @@ int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask); * Return the L2 Cache way partitioning for the hw blocks. * * Returns The mask specifying the reserved way. 0 bits in mask indicates - * the cache 'ways' that a core can evict from. - * -1 on error + * the cache 'ways' that a core can evict from. + * -1 on error */ int cvmx_l2c_get_hw_way_partition(void); @@ -220,16 +220,16 @@ int cvmx_l2c_get_hw_way_partition(void); * Partitions the L2 cache for the hardware blocks. * * @mask: The partitioning of the ways expressed as a binary - * mask. A 0 bit allows the core to evict cache lines from - * a way, while a 1 bit blocks the core from evicting any - * lines from that way. There must be at least one allowed - * way (0 bit) in the mask. + * mask. A 0 bit allows the core to evict cache lines from + * a way, while a 1 bit blocks the core from evicting any + * lines from that way. There must be at least one allowed + * way (0 bit) in the mask. * * @note If any ways are blocked for all cores and the HW blocks, then - * those ways will never have any cache lines evicted from them. - * All cores and the hardware blocks are free to read from all - * ways regardless of the partitioning. + * those ways will never have any cache lines evicted from them. + * All cores and the hardware blocks are free to read from all + * ways regardless of the partitioning. */ int cvmx_l2c_set_hw_way_partition(uint32_t mask); @@ -240,7 +240,7 @@ int cvmx_l2c_set_hw_way_partition(uint32_t mask); * @addr: physical address of line to lock * * Returns 0 on success, - * 1 if line not locked. + * 1 if line not locked. */ int cvmx_l2c_lock_line(uint64_t addr); @@ -258,7 +258,7 @@ int cvmx_l2c_lock_line(uint64_t addr); * @len: Length (in bytes) of region to lock * * Returns Number of requested lines that where not locked. - * 0 on success (all locked) + * 0 on success (all locked) */ int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len); @@ -272,7 +272,7 @@ int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len); * @address: Physical address to unlock * * Returns 0: line not unlocked - * 1: line unlocked + * 1: line unlocked */ int cvmx_l2c_unlock_line(uint64_t address); @@ -290,7 +290,7 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len); * Read the L2 controller tag for a given location in L2 * * @association: - * Which association to read line from + * Which association to read line from * @index: Which way to read from. * * Returns l2c tag structure for line requested. diff --git a/arch/mips/include/asm/octeon/cvmx-mdio.h b/arch/mips/include/asm/octeon/cvmx-mdio.h index 6f0cd182cec..9f6a4f32a83 100644 --- a/arch/mips/include/asm/octeon/cvmx-mdio.h +++ b/arch/mips/include/asm/octeon/cvmx-mdio.h @@ -246,21 +246,21 @@ typedef union { } cvmx_mdio_phy_reg_mmd_address_data_t; /* Operating request encodings. */ -#define MDIO_CLAUSE_22_WRITE 0 -#define MDIO_CLAUSE_22_READ 1 +#define MDIO_CLAUSE_22_WRITE 0 +#define MDIO_CLAUSE_22_READ 1 -#define MDIO_CLAUSE_45_ADDRESS 0 -#define MDIO_CLAUSE_45_WRITE 1 +#define MDIO_CLAUSE_45_ADDRESS 0 +#define MDIO_CLAUSE_45_WRITE 1 #define MDIO_CLAUSE_45_READ_INC 2 -#define MDIO_CLAUSE_45_READ 3 +#define MDIO_CLAUSE_45_READ 3 /* MMD identifiers, mostly for accessing devices within XENPAK modules. */ -#define CVMX_MMD_DEVICE_PMA_PMD 1 -#define CVMX_MMD_DEVICE_WIS 2 -#define CVMX_MMD_DEVICE_PCS 3 -#define CVMX_MMD_DEVICE_PHY_XS 4 -#define CVMX_MMD_DEVICE_DTS_XS 5 -#define CVMX_MMD_DEVICE_TC 6 +#define CVMX_MMD_DEVICE_PMA_PMD 1 +#define CVMX_MMD_DEVICE_WIS 2 +#define CVMX_MMD_DEVICE_PCS 3 +#define CVMX_MMD_DEVICE_PHY_XS 4 +#define CVMX_MMD_DEVICE_DTS_XS 5 +#define CVMX_MMD_DEVICE_TC 6 #define CVMX_MMD_DEVICE_CL22_EXT 29 #define CVMX_MMD_DEVICE_VENDOR_1 30 #define CVMX_MMD_DEVICE_VENDOR_2 31 @@ -291,7 +291,7 @@ static inline void __cvmx_mdio_set_clause22_mode(int bus_id) * registers controlling auto negotiation. * * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) - * support multiple busses. + * support multiple busses. * @phy_id: The MII phy id * @location: Register location to read * @@ -328,13 +328,13 @@ static inline int cvmx_mdio_read(int bus_id, int phy_id, int location) * registers controlling auto negotiation. * * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) - * support multiple busses. + * support multiple busses. * @phy_id: The MII phy id * @location: Register location to write * @val: Value to write * * Returns -1 on error - * 0 on success + * 0 on success */ static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val) { @@ -370,7 +370,7 @@ static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val) * read PHY registers controlling auto negotiation. * * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) - * support multiple busses. + * support multiple busses. * @phy_id: The MII phy id * @device: MDIO Managable Device (MMD) id * @location: Register location to read @@ -407,7 +407,7 @@ static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, } while (smi_wr.s.pending && --timeout); if (timeout <= 0) { cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " - "device %2d register %2d TIME OUT(address)\n", + "device %2d register %2d TIME OUT(address)\n", bus_id, phy_id, device, location); return -1; } @@ -425,7 +425,7 @@ static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, if (timeout <= 0) { cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " - "device %2d register %2d TIME OUT(data)\n", + "device %2d register %2d TIME OUT(data)\n", bus_id, phy_id, device, location); return -1; } @@ -434,7 +434,7 @@ static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, return smi_rd.s.dat; else { cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " - "device %2d register %2d INVALID READ\n", + "device %2d register %2d INVALID READ\n", bus_id, phy_id, device, location); return -1; } @@ -445,14 +445,14 @@ static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, * write PHY registers controlling auto negotiation. * * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) - * support multiple busses. + * support multiple busses. * @phy_id: The MII phy id * @device: MDIO Managable Device (MMD) id * @location: Register location to write * @val: Value to write * * Returns -1 on error - * 0 on success + * 0 on success */ static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device, int location, int val) diff --git a/arch/mips/include/asm/octeon/cvmx-pip-defs.h b/arch/mips/include/asm/octeon/cvmx-pip-defs.h index 05a917d6ebe..e975c7d2e48 100644 --- a/arch/mips/include/asm/octeon/cvmx-pip-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pip-defs.h @@ -44,7 +44,7 @@ enum cvmx_pip_port_parse_mode { */ CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull, /* - * Input packets are assumed to be IP. Results from non IP + * Input packets are assumed to be IP. Results from non IP * packets is undefined. Pointers reference the beginning of * the IP header. */ diff --git a/arch/mips/include/asm/octeon/cvmx-pip.h b/arch/mips/include/asm/octeon/cvmx-pip.h index 9e739a64085..df69bfd2b00 100644 --- a/arch/mips/include/asm/octeon/cvmx-pip.h +++ b/arch/mips/include/asm/octeon/cvmx-pip.h @@ -37,8 +37,8 @@ #include <asm/octeon/cvmx-fpa.h> #include <asm/octeon/cvmx-pip-defs.h> -#define CVMX_PIP_NUM_INPUT_PORTS 40 -#define CVMX_PIP_NUM_WATCHERS 4 +#define CVMX_PIP_NUM_INPUT_PORTS 40 +#define CVMX_PIP_NUM_WATCHERS 4 /* * Encodes the different error and exception codes @@ -92,10 +92,10 @@ typedef enum { /** * NOTES - * late collision (data received before collision) - * late collisions cannot be detected by the receiver - * they would appear as JAM bits which would appear as bad FCS - * or carrier extend error which is CVMX_PIP_EXTEND_ERR + * late collision (data received before collision) + * late collisions cannot be detected by the receiver + * they would appear as JAM bits which would appear as bad FCS + * or carrier extend error which is CVMX_PIP_EXTEND_ERR */ typedef enum { /* No error */ @@ -122,11 +122,11 @@ typedef enum { * error) */ CVMX_PIP_UNDER_FCS_ERR = 6ull, - /* RGM 7 = FCS error */ + /* RGM 7 = FCS error */ CVMX_PIP_GMX_FCS_ERR = 7ull, /* RGM+SPI 8 = min frame error (pkt len < min frame len) */ CVMX_PIP_UNDER_ERR = 8ull, - /* RGM 9 = Frame carrier extend error */ + /* RGM 9 = Frame carrier extend error */ CVMX_PIP_EXTEND_ERR = 9ull, /* * RGM 10 = length mismatch (len did not match len in L2 @@ -161,10 +161,10 @@ typedef enum { CVMX_PIP_PIP_L2_MAL_HDR = 18L /* * NOTES: xx = late collision (data received before collision) - * late collisions cannot be detected by the receiver - * they would appear as JAM bits which would appear as - * bad FCS or carrier extend error which is - * CVMX_PIP_EXTEND_ERR + * late collisions cannot be detected by the receiver + * they would appear as JAM bits which would appear as + * bad FCS or carrier extend error which is + * CVMX_PIP_EXTEND_ERR */ } cvmx_pip_rcv_err_t; @@ -192,13 +192,13 @@ typedef struct { /* Number of packets processed by PIP */ uint32_t packets; /* - * Number of indentified L2 multicast packets. Does not + * Number of identified L2 multicast packets. Does not * include broadcast packets. Only includes packets whose * parse mode is SKIP_TO_L2 */ uint32_t multicast_packets; /* - * Number of indentified L2 broadcast packets. Does not + * Number of identified L2 broadcast packets. Does not * include multicast packets. Only includes packets whose * parse mode is SKIP_TO_L2 */ @@ -287,7 +287,7 @@ typedef union { * @port_num: Port number to configure * @port_cfg: Port hardware configuration * @port_tag_cfg: - * Port POW tagging configuration + * Port POW tagging configuration */ static inline void cvmx_pip_config_port(uint64_t port_num, union cvmx_pip_prt_cfgx port_cfg, @@ -298,20 +298,20 @@ static inline void cvmx_pip_config_port(uint64_t port_num, } #if 0 /** - * @deprecated This function is a thin wrapper around the Pass1 version - * of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for - * setting the group that is incompatible with this function, - * the preferred upgrade path is to use the CSR directly. + * @deprecated This function is a thin wrapper around the Pass1 version + * of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for + * setting the group that is incompatible with this function, + * the preferred upgrade path is to use the CSR directly. * * Configure the global QoS packet watchers. Each watcher is * capable of matching a field in a packet to determine the * QoS queue for scheduling. * - * @watcher: Watcher number to configure (0 - 3). + * @watcher: Watcher number to configure (0 - 3). * @match_type: Watcher match type * @match_value: - * Value the watcher will match against - * @qos: QoS queue for packets matching this watcher + * Value the watcher will match against + * @qos: QoS queue for packets matching this watcher */ static inline void cvmx_pip_config_watcher(uint64_t watcher, cvmx_pip_qos_watch_types match_type, @@ -331,7 +331,7 @@ static inline void cvmx_pip_config_watcher(uint64_t watcher, * Configure the VLAN priority to QoS queue mapping. * * @vlan_priority: - * VLAN priority (0-7) + * VLAN priority (0-7) * @qos: QoS queue for packets matching this watcher */ static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority, @@ -451,10 +451,10 @@ static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear, * * @interface: Interface to configure (0 or 1) * @invert_result: - * Invert the result of the CRC + * Invert the result of the CRC * @reflect: Reflect * @initialization_vector: - * CRC initialization vector + * CRC initialization vector */ static inline void cvmx_pip_config_crc(uint64_t interface, uint64_t invert_result, uint64_t reflect, @@ -500,13 +500,13 @@ static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index) * * @mask_index: Which tag mask to modify (0..3) * @offset: Offset into the bitmask to set bits at. Use the GCC macro - * offsetof() to determine the offsets into packet headers. - * For example, offsetof(ethhdr, protocol) returns the offset - * of the ethernet protocol field. The bitmask selects which - * bytes to include the the tag, with bit offset X selecting - * byte at offset X from the beginning of the packet data. + * offsetof() to determine the offsets into packet headers. + * For example, offsetof(ethhdr, protocol) returns the offset + * of the ethernet protocol field. The bitmask selects which + * bytes to include the the tag, with bit offset X selecting + * byte at offset X from the beginning of the packet data. * @len: Number of bytes to include. Usually this is the sizeof() - * the field. + * the field. */ static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset, uint64_t len) diff --git a/arch/mips/include/asm/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h index c6daeedf1f8..f7d2a671884 100644 --- a/arch/mips/include/asm/octeon/cvmx-pko.h +++ b/arch/mips/include/asm/octeon/cvmx-pko.h @@ -69,16 +69,16 @@ #define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1) #define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256 -#define CVMX_PKO_MAX_OUTPUT_QUEUES ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \ +#define CVMX_PKO_MAX_OUTPUT_QUEUES ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \ OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \ OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \ (OCTEON_IS_MODEL(OCTEON_CN58XX) || \ OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128) -#define CVMX_PKO_NUM_OUTPUT_PORTS 40 +#define CVMX_PKO_NUM_OUTPUT_PORTS 40 /* use this for queues that are not used */ #define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63 -#define CVMX_PKO_QUEUE_STATIC_PRIORITY 9 -#define CVMX_PKO_ILLEGAL_QUEUE 0xFFFF +#define CVMX_PKO_QUEUE_STATIC_PRIORITY 9 +#define CVMX_PKO_ILLEGAL_QUEUE 0xFFFF #define CVMX_PKO_MAX_QUEUE_DEPTH 0 typedef enum { @@ -269,13 +269,13 @@ extern void cvmx_pko_shutdown(void); /** * Configure a output port and the associated queues for use. * - * @port: Port to configure. + * @port: Port to configure. * @base_queue: First queue number to associate with this port. * @num_queues: Number of queues t oassociate with this port - * @priority: Array of priority levels for each queue. Values are - * allowed to be 1-8. A value of 8 get 8 times the traffic - * of a value of 1. There must be num_queues elements in the - * array. + * @priority: Array of priority levels for each queue. Values are + * allowed to be 1-8. A value of 8 get 8 times the traffic + * of a value of 1. There must be num_queues elements in the + * array. */ extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, @@ -285,7 +285,7 @@ extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, /** * Ring the packet output doorbell. This tells the packet * output hardware that "len" command words have been added - * to its pending list. This command includes the required + * to its pending list. This command includes the required * CVMX_SYNCWS before the doorbell ring. * * @port: Port the packet is for @@ -322,18 +322,18 @@ static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue, * The use_locking parameter allows the caller to use three * possible locking modes. * - CVMX_PKO_LOCK_NONE - * - PKO doesn't do any locking. It is the responsibility - * of the application to make sure that no other core - * is accessing the same queue at the same time. + * - PKO doesn't do any locking. It is the responsibility + * of the application to make sure that no other core + * is accessing the same queue at the same time. * - CVMX_PKO_LOCK_ATOMIC_TAG - * - PKO performs an atomic tagswitch to insure exclusive - * access to the output queue. This will maintain - * packet ordering on output. + * - PKO performs an atomic tagswitch to insure exclusive + * access to the output queue. This will maintain + * packet ordering on output. * - CVMX_PKO_LOCK_CMD_QUEUE - * - PKO uses the common command queue locks to insure - * exclusive access to the output queue. This is a - * memory based ll/sc. This is the most portable - * locking mechanism. + * - PKO uses the common command queue locks to insure + * exclusive access to the output queue. This is a + * memory based ll/sc. This is the most portable + * locking mechanism. * * NOTE: If atomic locking is used, the POW entry CANNOT be * descheduled, as it does not contain a valid WQE pointer. @@ -341,7 +341,7 @@ static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue, * @port: Port to send it on * @queue: Queue to use * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or - * CVMX_PKO_LOCK_CMD_QUEUE + * CVMX_PKO_LOCK_CMD_QUEUE */ static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue, @@ -351,11 +351,11 @@ static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue, /* * Must do a full switch here to handle all cases. We * use a fake WQE pointer, as the POW does not access - * this memory. The WQE pointer and group are only + * this memory. The WQE pointer and group are only * used if this work is descheduled, which is not * supported by the * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish - * combination. Note that this is a special case in + * combination. Note that this is a special case in * which these fake values can be used - this is not a * general technique. */ @@ -377,10 +377,10 @@ static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue, * @port: Port to send it on * @queue: Queue to use * @pko_command: - * PKO HW command word + * PKO HW command word * @packet: Packet to send * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or - * CVMX_PKO_LOCK_CMD_QUEUE + * CVMX_PKO_LOCK_CMD_QUEUE * * Returns returns CVMX_PKO_SUCCESS on success, or error code on * failure of output @@ -418,12 +418,12 @@ static inline cvmx_pko_status_t cvmx_pko_send_packet_finish( * @port: Port to send it on * @queue: Queue to use * @pko_command: - * PKO HW command word + * PKO HW command word * @packet: Packet to send * @addr: Plysical address of a work queue entry or physical address - * to zero on complete. + * to zero on complete. * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or - * CVMX_PKO_LOCK_CMD_QUEUE + * CVMX_PKO_LOCK_CMD_QUEUE * * Returns returns CVMX_PKO_SUCCESS on success, or error code on * failure of output @@ -588,7 +588,7 @@ static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear, * @port: Port to rate limit * @packets_s: Maximum packet/sec * @burst: Maximum number of packets to burst in a row before rate - * limiting cuts in. + * limiting cuts in. * * Returns Zero on success, negative on failure */ @@ -601,7 +601,7 @@ extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst); * @port: Port to rate limit * @bits_s: PKO rate limit in bits/sec * @burst: Maximum number of bits to burst before rate - * limiting cuts in. + * limiting cuts in. * * Returns Zero on success, negative on failure */ diff --git a/arch/mips/include/asm/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h index 92742b241a5..4b4d0ecfd9e 100644 --- a/arch/mips/include/asm/octeon/cvmx-pow.h +++ b/arch/mips/include/asm/octeon/cvmx-pow.h @@ -70,7 +70,7 @@ enum cvmx_pow_tag_type { * The work queue entry from the order - NEVER tag switch from * NULL to NULL */ - CVMX_POW_TAG_TYPE_NULL = 2L, + CVMX_POW_TAG_TYPE_NULL = 2L, /* A tag switch to NULL, and there is no space reserved in POW * - NEVER tag switch to NULL_NULL * - NEVER tag switch from NULL_NULL @@ -90,7 +90,7 @@ typedef enum { } cvmx_pow_wait_t; /** - * POW tag operations. These are used in the data stored to the POW. + * POW tag operations. These are used in the data stored to the POW. */ typedef enum { /* @@ -341,14 +341,14 @@ typedef union { * lists. The two memory-input queue lists associated * with each QOS level are: * - * - qosgrp = 0, qosgrp = 8: QOS0 - * - qosgrp = 1, qosgrp = 9: QOS1 - * - qosgrp = 2, qosgrp = 10: QOS2 - * - qosgrp = 3, qosgrp = 11: QOS3 - * - qosgrp = 4, qosgrp = 12: QOS4 - * - qosgrp = 5, qosgrp = 13: QOS5 - * - qosgrp = 6, qosgrp = 14: QOS6 - * - qosgrp = 7, qosgrp = 15: QOS7 + * - qosgrp = 0, qosgrp = 8: QOS0 + * - qosgrp = 1, qosgrp = 9: QOS1 + * - qosgrp = 2, qosgrp = 10: QOS2 + * - qosgrp = 3, qosgrp = 11: QOS3 + * - qosgrp = 4, qosgrp = 12: QOS4 + * - qosgrp = 5, qosgrp = 13: QOS5 + * - qosgrp = 6, qosgrp = 14: QOS6 + * - qosgrp = 7, qosgrp = 15: QOS7 */ uint64_t qosgrp:4; /* @@ -942,11 +942,11 @@ typedef union { * operations. * * NOTE: The following is the behavior of the pending switch bit at the PP - * for POW stores (i.e. when did<7:3> == 0xc) - * - did<2:0> == 0 => pending switch bit is set - * - did<2:0> == 1 => no affect on the pending switch bit - * - did<2:0> == 3 => pending switch bit is cleared - * - did<2:0> == 7 => no affect on the pending switch bit + * for POW stores (i.e. when did<7:3> == 0xc) + * - did<2:0> == 0 => pending switch bit is set + * - did<2:0> == 1 => no affect on the pending switch bit + * - did<2:0> == 3 => pending switch bit is cleared + * - did<2:0> == 7 => no affect on the pending switch bit * - did<2:0> == others => must not be used * - No other loads/stores have an affect on the pending switch bit * - The switch bus from POW can clear the pending switch bit @@ -1053,7 +1053,7 @@ static inline cvmx_wqe_t *cvmx_pow_get_current_wqp(void) } #ifndef CVMX_MF_CHORD -#define CVMX_MF_CHORD(dest) CVMX_RDHWR(dest, 30) +#define CVMX_MF_CHORD(dest) CVMX_RDHWR(dest, 30) #endif /** @@ -1097,7 +1097,7 @@ static inline void cvmx_pow_tag_sw_wait(void) * so the caller must ensure that there is not a pending tag switch. * * @wait: When set, call stalls until work becomes avaiable, or times out. - * If not set, returns immediately. + * If not set, returns immediately. * * Returns Returns the WQE pointer from POW. Returns NULL if no work * was available. @@ -1131,7 +1131,7 @@ static inline cvmx_wqe_t *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_t * requesting the new work. * * @wait: When set, call stalls until work becomes avaiable, or times out. - * If not set, returns immediately. + * If not set, returns immediately. * * Returns Returns the WQE pointer from POW. Returns NULL if no work * was available. @@ -1148,7 +1148,7 @@ static inline cvmx_wqe_t *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait) } /** - * Synchronous null_rd request. Requests a switch out of NULL_NULL POW state. + * Synchronous null_rd request. Requests a switch out of NULL_NULL POW state. * This function waits for any previous tag switch to complete before * requesting the null_rd. * @@ -1183,11 +1183,11 @@ static inline enum cvmx_pow_tag_type cvmx_pow_work_request_null_rd(void) * there is not a pending tag switch. * * @scr_addr: Scratch memory address that response will be returned - * to, which is either a valid WQE, or a response with the - * invalid bit set. Byte address, must be 8 byte aligned. + * to, which is either a valid WQE, or a response with the + * invalid bit set. Byte address, must be 8 byte aligned. * * @wait: 1 to cause response to wait for work to become available (or - * timeout), 0 to cause response to return immediately + * timeout), 0 to cause response to return immediately */ static inline void cvmx_pow_work_request_async_nocheck(int scr_addr, cvmx_pow_wait_t wait) @@ -1212,11 +1212,11 @@ static inline void cvmx_pow_work_request_async_nocheck(int scr_addr, * tag switch to complete before requesting the new work. * * @scr_addr: Scratch memory address that response will be returned - * to, which is either a valid WQE, or a response with the - * invalid bit set. Byte address, must be 8 byte aligned. + * to, which is either a valid WQE, or a response with the + * invalid bit set. Byte address, must be 8 byte aligned. * * @wait: 1 to cause response to wait for work to become available (or - * timeout), 0 to cause response to return immediately + * timeout), 0 to cause response to return immediately */ static inline void cvmx_pow_work_request_async(int scr_addr, cvmx_pow_wait_t wait) @@ -1234,7 +1234,7 @@ static inline void cvmx_pow_work_request_async(int scr_addr, * to wait for the response. * * @scr_addr: Scratch memory address to get result from Byte address, - * must be 8 byte aligned. + * must be 8 byte aligned. * * Returns Returns the WQE from the scratch register, or NULL if no * work was available. @@ -1260,7 +1260,7 @@ static inline cvmx_wqe_t *cvmx_pow_work_response_async(int scr_addr) * @wqe_ptr: pointer to a work queue entry returned by the POW * * Returns 0 if pointer is valid - * 1 if invalid (no work was returned) + * 1 if invalid (no work was returned) */ static inline uint64_t cvmx_pow_work_invalid(cvmx_wqe_t *wqe_ptr) { @@ -1314,7 +1314,7 @@ static inline void cvmx_pow_tag_sw_nocheck(uint32_t tag, /* * Note that WQE in DRAM is not updated here, as the POW does * not read from DRAM once the WQE is in flight. See hardware - * manual for complete details. It is the application's + * manual for complete details. It is the application's * responsibility to keep track of the current tag value if * that is important. */ @@ -1361,7 +1361,7 @@ static inline void cvmx_pow_tag_sw(uint32_t tag, /* * Note that WQE in DRAM is not updated here, as the POW does * not read from DRAM once the WQE is in flight. See hardware - * manual for complete details. It is the application's + * manual for complete details. It is the application's * responsibility to keep track of the current tag value if * that is important. */ @@ -1390,7 +1390,7 @@ static inline void cvmx_pow_tag_sw(uint32_t tag, * previous tag switch has completed. * * @wqp: pointer to work queue entry to submit. This entry is - * updated to match the other parameters + * updated to match the other parameters * @tag: tag value to be assigned to work queue entry * @tag_type: type of tag * @group: group value for the work queue entry. @@ -1429,7 +1429,7 @@ static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag, /* * Note that WQE in DRAM is not updated here, as the POW does * not read from DRAM once the WQE is in flight. See hardware - * manual for complete details. It is the application's + * manual for complete details. It is the application's * responsibility to keep track of the current tag value if * that is important. */ @@ -1468,10 +1468,10 @@ static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag, * before requesting the tag switch. * * @wqp: pointer to work queue entry to submit. This entry is updated - * to match the other parameters + * to match the other parameters * @tag: tag value to be assigned to work queue entry * @tag_type: type of tag - * @group: group value for the work queue entry. + * @group: group value for the work queue entry. */ static inline void cvmx_pow_tag_sw_full(cvmx_wqe_t *wqp, uint32_t tag, enum cvmx_pow_tag_type tag_type, @@ -1560,7 +1560,7 @@ static inline void cvmx_pow_tag_sw_null(void) * unrelated to the tag that the core currently holds. * * @wqp: pointer to work queue entry to submit. This entry is - * updated to match the other parameters + * updated to match the other parameters * @tag: tag value to be assigned to work queue entry * @tag_type: type of tag * @qos: Input queue to add to. @@ -1592,7 +1592,7 @@ static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag, ptr.sio.offset = cvmx_ptr_to_phys(wqp); /* - * SYNC write to memory before the work submit. This is + * SYNC write to memory before the work submit. This is * necessary as POW may read values from DRAM at this time. */ CVMX_SYNCWS; @@ -1604,11 +1604,11 @@ static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag, * indicates which groups each core will accept work from. There are * 16 groups. * - * @core_num: core to apply mask to + * @core_num: core to apply mask to * @mask: Group mask. There are 16 groups, so only bits 0-15 are valid, - * representing groups 0-15. - * Each 1 bit in the mask enables the core to accept work from - * the corresponding group. + * representing groups 0-15. + * Each 1 bit in the mask enables the core to accept work from + * the corresponding group. */ static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask) { @@ -1623,14 +1623,14 @@ static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask) * This function sets POW static priorities for a core. Each input queue has * an associated priority value. * - * @core_num: core to apply priorities to - * @priority: Vector of 8 priorities, one per POW Input Queue (0-7). - * Highest priority is 0 and lowest is 7. A priority value - * of 0xF instructs POW to skip the Input Queue when - * scheduling to this specific core. - * NOTE: priorities should not have gaps in values, meaning - * {0,1,1,1,1,1,1,1} is a valid configuration while - * {0,2,2,2,2,2,2,2} is not. + * @core_num: core to apply priorities to + * @priority: Vector of 8 priorities, one per POW Input Queue (0-7). + * Highest priority is 0 and lowest is 7. A priority value + * of 0xF instructs POW to skip the Input Queue when + * scheduling to this specific core. + * NOTE: priorities should not have gaps in values, meaning + * {0,1,1,1,1,1,1,1} is a valid configuration while + * {0,2,2,2,2,2,2,2} is not. */ static inline void cvmx_pow_set_priority(uint64_t core_num, const uint8_t priority[]) @@ -1708,8 +1708,8 @@ static inline void cvmx_pow_set_priority(uint64_t core_num, * @tag_type: New tag type * @group: New group value * @no_sched: Control whether this work queue entry will be rescheduled. - * - 1 : don't schedule this work - * - 0 : allow this work to be scheduled. + * - 1 : don't schedule this work + * - 0 : allow this work to be scheduled. */ static inline void cvmx_pow_tag_sw_desched_nocheck( uint32_t tag, @@ -1794,8 +1794,8 @@ static inline void cvmx_pow_tag_sw_desched_nocheck( * @tag_type: New tag type * @group: New group value * @no_sched: Control whether this work queue entry will be rescheduled. - * - 1 : don't schedule this work - * - 0 : allow this work to be scheduled. + * - 1 : don't schedule this work + * - 0 : allow this work to be scheduled. */ static inline void cvmx_pow_tag_sw_desched(uint32_t tag, enum cvmx_pow_tag_type tag_type, @@ -1819,8 +1819,8 @@ static inline void cvmx_pow_tag_sw_desched(uint32_t tag, * Descchedules the current work queue entry. * * @no_sched: no schedule flag value to be set on the work queue - * entry. If this is set the entry will not be - * rescheduled. + * entry. If this is set the entry will not be + * rescheduled. */ static inline void cvmx_pow_desched(uint64_t no_sched) { @@ -1863,7 +1863,7 @@ static inline void cvmx_pow_desched(uint64_t no_sched) *****************************************************/ /* - * Number of bits of the tag used by software. The SW bits are always + * Number of bits of the tag used by software. The SW bits are always * a contiguous block of the high starting at bit 31. The hardware * bits are always the low bits. By default, the top 8 bits of the * tag are reserved for software, and the low 24 are set by the IPD @@ -1890,7 +1890,7 @@ static inline void cvmx_pow_desched(uint64_t no_sched) * are defined here. */ /* Mask for the value portion of the tag */ -#define CVMX_TAG_SUBGROUP_MASK 0xFFFF +#define CVMX_TAG_SUBGROUP_MASK 0xFFFF #define CVMX_TAG_SUBGROUP_SHIFT 16 #define CVMX_TAG_SUBGROUP_PKO 0x1 @@ -1905,12 +1905,12 @@ static inline void cvmx_pow_desched(uint64_t no_sched) * This function creates a 32 bit tag value from the two values provided. * * @sw_bits: The upper bits (number depends on configuration) are set - * to this value. The remainder of bits are set by the - * hw_bits parameter. + * to this value. The remainder of bits are set by the + * hw_bits parameter. * * @hw_bits: The lower bits (number depends on configuration) are set - * to this value. The remainder of bits are set by the - * sw_bits parameter. + * to this value. The remainder of bits are set by the + * sw_bits parameter. * * Returns 32 bit value of the combined hw and sw bits. */ @@ -1957,7 +1957,7 @@ static inline uint32_t cvmx_pow_tag_get_hw_bits(uint64_t tag) * * @buffer: Buffer to store capture into * @buffer_size: - * The size of the supplied buffer + * The size of the supplied buffer * * Returns Zero on success, negative on failure */ @@ -1968,7 +1968,7 @@ extern int cvmx_pow_capture(void *buffer, int buffer_size); * * @buffer: POW capture from cvmx_pow_capture() * @buffer_size: - * Size of the buffer + * Size of the buffer */ extern void cvmx_pow_display(void *buffer, int buffer_size); diff --git a/arch/mips/include/asm/octeon/cvmx-scratch.h b/arch/mips/include/asm/octeon/cvmx-scratch.h index 96b70cfd624..8d21cc5e4e4 100644 --- a/arch/mips/include/asm/octeon/cvmx-scratch.h +++ b/arch/mips/include/asm/octeon/cvmx-scratch.h @@ -39,7 +39,7 @@ * Note: This define must be a long, not a long long in order to * compile without warnings for both 32bit and 64bit. */ -#define CVMX_SCRATCH_BASE (-32768l) /* 0xffffffffffff8000 */ +#define CVMX_SCRATCH_BASE (-32768l) /* 0xffffffffffff8000 */ /** * Reads an 8 bit value from the processor local scratchpad memory. diff --git a/arch/mips/include/asm/octeon/cvmx-spi.h b/arch/mips/include/asm/octeon/cvmx-spi.h index 3bf53b537bc..d5038cc4b47 100644 --- a/arch/mips/include/asm/octeon/cvmx-spi.h +++ b/arch/mips/include/asm/octeon/cvmx-spi.h @@ -84,11 +84,11 @@ static inline int cvmx_spi_is_spi_interface(int interface) * Initialize and start the SPI interface. * * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. + * use as a SPI interface. * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). * @timeout: Timeout to wait for clock synchronization in seconds * @num_ports: Number of SPI ports to configure * @@ -102,11 +102,11 @@ extern int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, * with its corespondant system. * * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. + * use as a SPI interface. * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). * @timeout: Timeout to wait for clock synchronization in seconds * Returns Zero on success, negative of failure. */ @@ -154,7 +154,7 @@ static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed( /** * Get current SPI4 initialization callbacks * - * @callbacks: Pointer to the callbacks structure.to fill + * @callbacks: Pointer to the callbacks structure.to fill * * Returns Pointer to cvmx_spi_callbacks_t structure. */ @@ -171,11 +171,11 @@ extern void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks); * Callback to perform SPI4 reset * * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. + * use as a SPI interface. * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). * * Returns Zero on success, non-zero error code on failure (will cause * SPI initialization to abort) @@ -187,11 +187,11 @@ extern int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode); * detection * * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. + * use as a SPI interface. * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). * @num_ports: Number of ports to configure on SPI * * Returns Zero on success, non-zero error code on failure (will cause @@ -204,11 +204,11 @@ extern int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, * Callback to perform clock detection * * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. + * use as a SPI interface. * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). * @timeout: Timeout to wait for clock synchronization in seconds * * Returns Zero on success, non-zero error code on failure (will cause @@ -221,11 +221,11 @@ extern int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, * Callback to perform link training * * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. + * use as a SPI interface. * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). * @timeout: Timeout to wait for link to be trained (in seconds) * * Returns Zero on success, non-zero error code on failure (will cause @@ -238,11 +238,11 @@ extern int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, * Callback to perform calendar data synchronization * * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. + * use as a SPI interface. * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). * @timeout: Timeout to wait for calendar data in seconds * * Returns Zero on success, non-zero error code on failure (will cause @@ -255,11 +255,11 @@ extern int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, * Callback to handle interface up * * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. + * use as a SPI interface. * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). * * Returns Zero on success, non-zero error code on failure (will cause * SPI initialization to abort) diff --git a/arch/mips/include/asm/octeon/cvmx-spinlock.h b/arch/mips/include/asm/octeon/cvmx-spinlock.h index a672abb1bc4..4f09cff8b8c 100644 --- a/arch/mips/include/asm/octeon/cvmx-spinlock.h +++ b/arch/mips/include/asm/octeon/cvmx-spinlock.h @@ -26,7 +26,7 @@ ***********************license end**************************************/ /** - * Implementation of spinlocks for Octeon CVMX. Although similar in + * Implementation of spinlocks for Octeon CVMX. Although similar in * function to Linux kernel spinlocks, they are not compatible. * Octeon CVMX spinlocks are only used to synchronize with the boot * monitor and other non-Linux programs running in the system. @@ -50,8 +50,8 @@ typedef struct { } cvmx_spinlock_t; /* note - macros not expanded in inline ASM, so values hardcoded */ -#define CVMX_SPINLOCK_UNLOCKED_VAL 0 -#define CVMX_SPINLOCK_LOCKED_VAL 1 +#define CVMX_SPINLOCK_UNLOCKED_VAL 0 +#define CVMX_SPINLOCK_LOCKED_VAL 1 #define CVMX_SPINLOCK_UNLOCKED_INITIALIZER {CVMX_SPINLOCK_UNLOCKED_VAL} @@ -96,7 +96,7 @@ static inline void cvmx_spinlock_unlock(cvmx_spinlock_t *lock) * @lock: pointer to lock structure * * Returns 0: lock successfully taken - * 1: lock not taken, held by someone else + * 1: lock not taken, held by someone else * These return values match the Linux semantics. */ @@ -104,16 +104,16 @@ static inline unsigned int cvmx_spinlock_trylock(cvmx_spinlock_t *lock) { unsigned int tmp; - __asm__ __volatile__(".set noreorder \n" + __asm__ __volatile__(".set noreorder \n" "1: ll %[tmp], %[val] \n" /* if lock held, fail immediately */ - " bnez %[tmp], 2f \n" - " li %[tmp], 1 \n" - " sc %[tmp], %[val] \n" - " beqz %[tmp], 1b \n" - " li %[tmp], 0 \n" - "2: \n" - ".set reorder \n" : + " bnez %[tmp], 2f \n" + " li %[tmp], 1 \n" + " sc %[tmp], %[val] \n" + " beqz %[tmp], 1b \n" + " li %[tmp], 0 \n" + "2: \n" + ".set reorder \n" : [val] "+m"(lock->value), [tmp] "=&r"(tmp) : : "memory"); @@ -129,14 +129,14 @@ static inline void cvmx_spinlock_lock(cvmx_spinlock_t *lock) { unsigned int tmp; - __asm__ __volatile__(".set noreorder \n" + __asm__ __volatile__(".set noreorder \n" "1: ll %[tmp], %[val] \n" - " bnez %[tmp], 1b \n" - " li %[tmp], 1 \n" - " sc %[tmp], %[val] \n" - " beqz %[tmp], 1b \n" - " nop \n" - ".set reorder \n" : + " bnez %[tmp], 1b \n" + " li %[tmp], 1 \n" + " sc %[tmp], %[val] \n" + " beqz %[tmp], 1b \n" + " nop \n" + ".set reorder \n" : [val] "+m"(lock->value), [tmp] "=&r"(tmp) : : "memory"); @@ -163,17 +163,17 @@ static inline void cvmx_spinlock_bit_lock(uint32_t *word) unsigned int tmp; unsigned int sav; - __asm__ __volatile__(".set noreorder \n" - ".set noat \n" + __asm__ __volatile__(".set noreorder \n" + ".set noat \n" "1: ll %[tmp], %[val] \n" - " bbit1 %[tmp], 31, 1b \n" - " li $at, 1 \n" - " ins %[tmp], $at, 31, 1 \n" - " sc %[tmp], %[val] \n" - " beqz %[tmp], 1b \n" - " nop \n" - ".set at \n" - ".set reorder \n" : + " bbit1 %[tmp], 31, 1b \n" + " li $at, 1 \n" + " ins %[tmp], $at, 31, 1 \n" + " sc %[tmp], %[val] \n" + " beqz %[tmp], 1b \n" + " nop \n" + ".set at \n" + ".set reorder \n" : [val] "+m"(*word), [tmp] "=&r"(tmp), [sav] "=&r"(sav) : : "memory"); @@ -187,7 +187,7 @@ static inline void cvmx_spinlock_bit_lock(uint32_t *word) * * @word: word to lock bit 31 of * Returns 0: lock successfully taken - * 1: lock not taken, held by someone else + * 1: lock not taken, held by someone else * These return values match the Linux semantics. */ static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word) @@ -198,15 +198,15 @@ static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word) ".set noat\n" "1: ll %[tmp], %[val] \n" /* if lock held, fail immediately */ - " bbit1 %[tmp], 31, 2f \n" - " li $at, 1 \n" - " ins %[tmp], $at, 31, 1 \n" - " sc %[tmp], %[val] \n" - " beqz %[tmp], 1b \n" - " li %[tmp], 0 \n" - "2: \n" - ".set at \n" - ".set reorder \n" : + " bbit1 %[tmp], 31, 2f \n" + " li $at, 1 \n" + " ins %[tmp], $at, 31, 1 \n" + " sc %[tmp], %[val] \n" + " beqz %[tmp], 1b \n" + " li %[tmp], 0 \n" + "2: \n" + ".set at \n" + ".set reorder \n" : [val] "+m"(*word), [tmp] "=&r"(tmp) : : "memory"); diff --git a/arch/mips/include/asm/octeon/cvmx-sysinfo.h b/arch/mips/include/asm/octeon/cvmx-sysinfo.h index 61dd5741afe..2131197422e 100644 --- a/arch/mips/include/asm/octeon/cvmx-sysinfo.h +++ b/arch/mips/include/asm/octeon/cvmx-sysinfo.h @@ -85,7 +85,7 @@ struct cvmx_sysinfo { char board_serial_number[OCTEON_SERIAL_LEN]; /* * Several boards support compact flash on the Octeon boot - * bus. The CF memory spaces may be mapped to different + * bus. The CF memory spaces may be mapped to different * addresses on different boards. These values will be 0 if * CF is not present. Note that these addresses are physical * addresses, and it is up to the application to use the @@ -123,25 +123,25 @@ extern struct cvmx_sysinfo *cvmx_sysinfo_get(void); /** * This function is used in non-simple executive environments (such as - * Linux kernel, u-boot, etc.) to configure the minimal fields that + * Linux kernel, u-boot, etc.) to configure the minimal fields that * are required to use simple executive files directly. * * Locking (if required) must be handled outside of this * function * * @phy_mem_desc_ptr: Pointer to global physical memory descriptor - * (bootmem descriptor) @board_type: Octeon board - * type enumeration + * (bootmem descriptor) @board_type: Octeon board + * type enumeration * * @board_rev_major: - * Board major revision + * Board major revision * @board_rev_minor: - * Board minor revision + * Board minor revision * @cpu_clock_hz: - * CPU clock freqency in hertz + * CPU clock freqency in hertz * * Returns 0: Failure - * 1: success + * 1: success */ extern int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr, uint16_t board_type, diff --git a/arch/mips/include/asm/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h index df762389e27..aa0d3d0de75 100644 --- a/arch/mips/include/asm/octeon/cvmx-wqe.h +++ b/arch/mips/include/asm/octeon/cvmx-wqe.h @@ -101,23 +101,23 @@ typedef union { * - 1 = Malformed L4 * - 2 = L4 Checksum Error: the L4 checksum value is * - 3 = UDP Length Error: The UDP length field would - * make the UDP data longer than what remains in - * the IP packet (as defined by the IP header - * length field). + * make the UDP data longer than what remains in + * the IP packet (as defined by the IP header + * length field). * - 4 = Bad L4 Port: either the source or destination - * TCP/UDP port is 0. + * TCP/UDP port is 0. * - 8 = TCP FIN Only: the packet is TCP and only the - * FIN flag set. + * FIN flag set. * - 9 = TCP No Flags: the packet is TCP and no flags - * are set. + * are set. * - 10 = TCP FIN RST: the packet is TCP and both FIN - * and RST are set. + * and RST are set. * - 11 = TCP SYN URG: the packet is TCP and both SYN - * and URG are set. + * and URG are set. * - 12 = TCP SYN RST: the packet is TCP and both SYN - * and RST are set. + * and RST are set. * - 13 = TCP SYN FIN: the packet is TCP and both SYN - * and FIN are set. + * and FIN are set. */ uint64_t L4_error:1; /* set if the packet is a fragment */ @@ -127,16 +127,16 @@ typedef union { * failure indicated in err_code below, decode: * * - 1 = Not IP: the IP version field is neither 4 nor - * 6. + * 6. * - 2 = IPv4 Header Checksum Error: the IPv4 header - * has a checksum violation. + * has a checksum violation. * - 3 = IP Malformed Header: the packet is not long - * enough to contain the IP header. + * enough to contain the IP header. * - 4 = IP Malformed: the packet is not long enough * to contain the bytes indicated by the IP * header. Pad is allowed. * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 - * Hop Count field are zero. + * Hop Count field are zero. * - 6 = IP Options */ uint64_t IP_exc:1; @@ -243,46 +243,46 @@ typedef union { * decode: * * - 1 = partial error: a packet was partially - * received, but internal buffering / bandwidth - * was not adequate to receive the entire - * packet. + * received, but internal buffering / bandwidth + * was not adequate to receive the entire + * packet. * - 2 = jabber error: the RGMII packet was too large - * and is truncated. + * and is truncated. * - 3 = overrun error: the RGMII packet is longer - * than allowed and had an FCS error. + * than allowed and had an FCS error. * - 4 = oversize error: the RGMII packet is longer - * than allowed. + * than allowed. * - 5 = alignment error: the RGMII packet is not an - * integer number of bytes - * and had an FCS error (100M and 10M only). + * integer number of bytes + * and had an FCS error (100M and 10M only). * - 6 = fragment error: the RGMII packet is shorter - * than allowed and had an FCS error. + * than allowed and had an FCS error. * - 7 = GMX FCS error: the RGMII packet had an FCS - * error. + * error. * - 8 = undersize error: the RGMII packet is shorter - * than allowed. + * than allowed. * - 9 = extend error: the RGMII packet had an extend - * error. + * error. * - 10 = length mismatch error: the RGMII packet had - * a length that did not match the length field - * in the L2 HDR. + * a length that did not match the length field + * in the L2 HDR. * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII - * packet had one or more data reception errors - * (RXERR) or the SPI4 packet had one or more - * DIP4 errors. + * packet had one or more data reception errors + * (RXERR) or the SPI4 packet had one or more + * DIP4 errors. * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII - * packet was not large enough to cover the - * skipped bytes or the SPI4 packet was - * terminated with an About EOPS. + * packet was not large enough to cover the + * skipped bytes or the SPI4 packet was + * terminated with an About EOPS. * - 13 = RGMII nibble error/SPI4 Port NXA Error: the - * RGMII packet had a studder error (data not - * repeated - 10/100M only) or the SPI4 packet - * was sent to an NXA. + * RGMII packet had a studder error (data not + * repeated - 10/100M only) or the SPI4 packet + * was sent to an NXA. * - 16 = FCS error: a SPI4.2 packet had an FCS error. * - 17 = Skip error: a packet was not large enough to - * cover the skipped bytes. + * cover the skipped bytes. * - 18 = L2 header malformed: the packet is not long - * enough to contain the L2. + * enough to contain the L2. */ uint64_t rcv_error:1; @@ -309,7 +309,7 @@ typedef struct { /***************************************************************** * WORD 0 - * HW WRITE: the following 64 bits are filled by HW when a packet arrives + * HW WRITE: the following 64 bits are filled by HW when a packet arrives */ /** @@ -323,14 +323,14 @@ typedef struct { /** * Next pointer used by hardware for list maintenance. * May be written/read by HW before the work queue - * entry is scheduled to a PP + * entry is scheduled to a PP * (Only 36 bits used in Octeon 1) */ uint64_t next_ptr:40; /***************************************************************** * WORD 1 - * HW WRITE: the following 64 bits are filled by HW when a packet arrives + * HW WRITE: the following 64 bits are filled by HW when a packet arrives */ /** @@ -362,8 +362,8 @@ typedef struct { /** * WORD 2 HW WRITE: the following 64-bits are filled in by - * hardware when a packet arrives This indicates a variety of - * status and error conditions. + * hardware when a packet arrives This indicates a variety of + * status and error conditions. */ cvmx_pip_wqe_word2 word2; @@ -373,15 +373,15 @@ typedef struct { union cvmx_buf_ptr packet_ptr; /** - * HW WRITE: octeon will fill in a programmable amount from the - * packet, up to (at most, but perhaps less) the amount - * needed to fill the work queue entry to 128 bytes + * HW WRITE: octeon will fill in a programmable amount from the + * packet, up to (at most, but perhaps less) the amount + * needed to fill the work queue entry to 128 bytes * - * If the packet is recognized to be IP, the hardware starts - * (except that the IPv4 header is padded for appropriate - * alignment) writing here where the IP header starts. If the - * packet is not recognized to be IP, the hardware starts - * writing the beginning of the packet here. + * If the packet is recognized to be IP, the hardware starts + * (except that the IPv4 header is padded for appropriate + * alignment) writing here where the IP header starts. If the + * packet is not recognized to be IP, the hardware starts + * writing the beginning of the packet here. */ uint8_t packet_data[96]; diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h index db58beab6cb..f991e7701d3 100644 --- a/arch/mips/include/asm/octeon/cvmx.h +++ b/arch/mips/include/asm/octeon/cvmx.h @@ -76,14 +76,14 @@ enum cvmx_mips_space { #endif #if CVMX_ENABLE_DEBUG_PRINTS -#define cvmx_dprintf printk +#define cvmx_dprintf printk #else #define cvmx_dprintf(...) {} #endif -#define CVMX_MAX_CORES (16) -#define CVMX_CACHE_LINE_SIZE (128) /* In bytes */ -#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */ +#define CVMX_MAX_CORES (16) +#define CVMX_CACHE_LINE_SIZE (128) /* In bytes */ +#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */ #define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE))) #define CAST64(v) ((long long)(long)(v)) #define CASTPTR(type, v) ((type *)(long)(v)) @@ -133,8 +133,8 @@ static inline uint64_t cvmx_build_io_address(uint64_t major_did, * * Example: cvmx_build_bits(39,24,value) * <pre> - * 6 5 4 3 3 2 1 - * 3 5 7 9 1 3 5 7 0 + * 6 5 4 3 3 2 1 + * 3 5 7 9 1 3 5 7 0 * +-------+-------+-------+-------+-------+-------+-------+------+ * 000000000000000000000000___________value000000000000000000000000 * </pre> @@ -183,7 +183,7 @@ static inline uint64_t cvmx_ptr_to_phys(void *ptr) * memory pointer (void *). * * @physical_address: - * Hardware physical address to memory + * Hardware physical address to memory * Returns Pointer to memory */ static inline void *cvmx_phys_to_ptr(uint64_t physical_address) @@ -207,10 +207,10 @@ static inline void *cvmx_phys_to_ptr(uint64_t physical_address) /* We have a full 64bit ABI. Writing to a 64bit address can be done with a simple volatile pointer */ -#define CVMX_BUILD_WRITE64(TYPE, ST) \ -static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \ -{ \ - *CASTPTR(volatile TYPE##_t, addr) = val; \ +#define CVMX_BUILD_WRITE64(TYPE, ST) \ +static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \ +{ \ + *CASTPTR(volatile TYPE##_t, addr) = val; \ } @@ -221,19 +221,19 @@ static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \ /* We have a full 64bit ABI. Writing to a 64bit address can be done with a simple volatile pointer */ -#define CVMX_BUILD_READ64(TYPE, LT) \ -static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \ -{ \ +#define CVMX_BUILD_READ64(TYPE, LT) \ +static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \ +{ \ return *CASTPTR(volatile TYPE##_t, addr); \ } /* The following defines 8 functions for writing to a 64bit address. Each takes two arguments, the address and the value to write. - cvmx_write64_int64 cvmx_write64_uint64 - cvmx_write64_int32 cvmx_write64_uint32 - cvmx_write64_int16 cvmx_write64_uint16 - cvmx_write64_int8 cvmx_write64_uint8 */ + cvmx_write64_int64 cvmx_write64_uint64 + cvmx_write64_int32 cvmx_write64_uint32 + cvmx_write64_int16 cvmx_write64_uint16 + cvmx_write64_int8 cvmx_write64_uint8 */ CVMX_BUILD_WRITE64(int64, "sd"); CVMX_BUILD_WRITE64(int32, "sw"); CVMX_BUILD_WRITE64(int16, "sh"); @@ -246,10 +246,10 @@ CVMX_BUILD_WRITE64(uint8, "sb"); /* The following defines 8 functions for reading from a 64bit address. Each takes the address as the only argument - cvmx_read64_int64 cvmx_read64_uint64 - cvmx_read64_int32 cvmx_read64_uint32 - cvmx_read64_int16 cvmx_read64_uint16 - cvmx_read64_int8 cvmx_read64_uint8 */ + cvmx_read64_int64 cvmx_read64_uint64 + cvmx_read64_int32 cvmx_read64_uint32 + cvmx_read64_int16 cvmx_read64_uint16 + cvmx_read64_int8 cvmx_read64_uint8 */ CVMX_BUILD_READ64(int64, "ld"); CVMX_BUILD_READ64(int32, "lw"); CVMX_BUILD_READ64(int16, "lh"); @@ -389,7 +389,7 @@ static inline void cvmx_wait(uint64_t cycles) /** * Reads a chip global cycle counter. This counts CPU cycles since - * chip reset. The counter is 64 bit. + * chip reset. The counter is 64 bit. * This register does not exist on CN38XX pass 1 silicion * * Returns Global chip cycle count since chip reset. @@ -453,7 +453,7 @@ static inline uint32_t cvmx_octeon_num_cores(void) /** * Read a byte of fuse data - * @byte_addr: address to read + * @byte_addr: address to read * * Returns fuse value: 0 or 1 */ diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h index 8008da2f877..90e05a8d4b1 100644 --- a/arch/mips/include/asm/octeon/octeon-feature.h +++ b/arch/mips/include/asm/octeon/octeon-feature.h @@ -35,7 +35,7 @@ #include <asm/octeon/cvmx-rnm-defs.h> enum octeon_feature { - /* CN68XX uses port kinds for packet interface */ + /* CN68XX uses port kinds for packet interface */ OCTEON_FEATURE_PKND, /* CN68XX has different fields in word0 - word2 */ OCTEON_FEATURE_CN68XX_WQE, @@ -51,7 +51,7 @@ enum octeon_feature { OCTEON_FEATURE_DORM_CRYPTO, /* Does this Octeon support PCI express? */ OCTEON_FEATURE_PCIE, - /* Does this Octeon support SRIOs */ + /* Does this Octeon support SRIOs */ OCTEON_FEATURE_SRIO, /* Does this Octeon support Interlaken */ OCTEON_FEATURE_ILK, @@ -75,7 +75,7 @@ enum octeon_feature { /* Octeon MDIO block supports clause 45 transactions for 10 * Gig support */ OCTEON_FEATURE_MDIO_CLAUSE_45, - /* + /* * CN52XX and CN56XX used a block named NPEI for PCIe * access. Newer chips replaced this with SLI+DPI. */ @@ -94,10 +94,10 @@ static inline int cvmx_fuse_read(int fuse); * be kept out of fast path code. * * @feature: Feature to check for. This should always be a constant so the - * compiler can remove the switch statement through optimization. + * compiler can remove the switch statement through optimization. * * Returns Non zero if the feature exists. Zero if the feature does not - * exist. + * exist. */ static inline int octeon_has_feature(enum octeon_feature feature) { diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h index 349bb2ba840..e2c122c6a65 100644 --- a/arch/mips/include/asm/octeon/octeon-model.h +++ b/arch/mips/include/asm/octeon/octeon-model.h @@ -29,7 +29,7 @@ /* * The defines below should be used with the OCTEON_IS_MODEL() macro - * to determine what model of chip the software is running on. Models + * to determine what model of chip the software is running on. Models * ending in 'XX' match multiple models (families), while specific * models match only that model. If a pass (revision) is specified, * then only that revision will be matched. Care should be taken when @@ -40,183 +40,183 @@ * subject to change at anytime without notice. * * NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN* - * macros should be used outside of this file. All other macros are + * macros should be used outside of this file. All other macros are * for internal use only, and may change without notice. */ -#define OCTEON_FAMILY_MASK 0x00ffff00 +#define OCTEON_FAMILY_MASK 0x00ffff00 /* Flag bits in top byte */ /* Ignores revision in model checks */ -#define OM_IGNORE_REVISION 0x01000000 +#define OM_IGNORE_REVISION 0x01000000 /* Check submodels */ -#define OM_CHECK_SUBMODEL 0x02000000 +#define OM_CHECK_SUBMODEL 0x02000000 /* Match all models previous than the one specified */ #define OM_MATCH_PREVIOUS_MODELS 0x04000000 /* Ignores the minor revison on newer parts */ #define OM_IGNORE_MINOR_REVISION 0x08000000 -#define OM_FLAG_MASK 0xff000000 +#define OM_FLAG_MASK 0xff000000 /* Match all cn5XXX Octeon models. */ -#define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000 +#define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000 /* Match all cn6XXX Octeon models. */ -#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000 +#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000 /* Match all cnf7XXX Octeon models. */ -#define OM_MATCH_F7XXX_FAMILY_MODELS 0x80000000 +#define OM_MATCH_F7XXX_FAMILY_MODELS 0x80000000 /* * CNF7XXX models with new revision encoding */ -#define OCTEON_CNF71XX_PASS1_0 0x000d9400 +#define OCTEON_CNF71XX_PASS1_0 0x000d9400 -#define OCTEON_CNF71XX (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_REVISION) -#define OCTEON_CNF71XX_PASS1_X (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CNF71XX (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CNF71XX_PASS1_X (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) /* * CN6XXX models with new revision encoding */ -#define OCTEON_CN68XX_PASS1_0 0x000d9100 -#define OCTEON_CN68XX_PASS1_1 0x000d9101 -#define OCTEON_CN68XX_PASS1_2 0x000d9102 -#define OCTEON_CN68XX_PASS2_0 0x000d9108 +#define OCTEON_CN68XX_PASS1_0 0x000d9100 +#define OCTEON_CN68XX_PASS1_1 0x000d9101 +#define OCTEON_CN68XX_PASS1_2 0x000d9102 +#define OCTEON_CN68XX_PASS2_0 0x000d9108 -#define OCTEON_CN68XX (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION) -#define OCTEON_CN68XX_PASS1_X (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN68XX_PASS2_X (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN68XX (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION) +#define OCTEON_CN68XX_PASS1_X (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN68XX_PASS2_X (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) #define OCTEON_CN68XX_PASS1 OCTEON_CN68XX_PASS1_X #define OCTEON_CN68XX_PASS2 OCTEON_CN68XX_PASS2_X -#define OCTEON_CN66XX_PASS1_0 0x000d9200 -#define OCTEON_CN66XX_PASS1_2 0x000d9202 +#define OCTEON_CN66XX_PASS1_0 0x000d9200 +#define OCTEON_CN66XX_PASS1_2 0x000d9202 -#define OCTEON_CN66XX (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_REVISION) -#define OCTEON_CN66XX_PASS1_X (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN66XX (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN66XX_PASS1_X (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN63XX_PASS1_0 0x000d9000 -#define OCTEON_CN63XX_PASS1_1 0x000d9001 -#define OCTEON_CN63XX_PASS1_2 0x000d9002 -#define OCTEON_CN63XX_PASS2_0 0x000d9008 -#define OCTEON_CN63XX_PASS2_1 0x000d9009 -#define OCTEON_CN63XX_PASS2_2 0x000d900a +#define OCTEON_CN63XX_PASS1_0 0x000d9000 +#define OCTEON_CN63XX_PASS1_1 0x000d9001 +#define OCTEON_CN63XX_PASS1_2 0x000d9002 +#define OCTEON_CN63XX_PASS2_0 0x000d9008 +#define OCTEON_CN63XX_PASS2_1 0x000d9009 +#define OCTEON_CN63XX_PASS2_2 0x000d900a -#define OCTEON_CN63XX (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION) -#define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN63XX (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION) +#define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN61XX_PASS1_0 0x000d9300 +#define OCTEON_CN61XX_PASS1_0 0x000d9300 -#define OCTEON_CN61XX (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION) -#define OCTEON_CN61XX_PASS1_X (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN61XX (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN61XX_PASS1_X (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) /* * CN5XXX models with new revision encoding */ -#define OCTEON_CN58XX_PASS1_0 0x000d0300 -#define OCTEON_CN58XX_PASS1_1 0x000d0301 -#define OCTEON_CN58XX_PASS1_2 0x000d0303 -#define OCTEON_CN58XX_PASS2_0 0x000d0308 -#define OCTEON_CN58XX_PASS2_1 0x000d0309 -#define OCTEON_CN58XX_PASS2_2 0x000d030a -#define OCTEON_CN58XX_PASS2_3 0x000d030b - -#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION) -#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X -#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X - -#define OCTEON_CN56XX_PASS1_0 0x000d0400 -#define OCTEON_CN56XX_PASS1_1 0x000d0401 -#define OCTEON_CN56XX_PASS2_0 0x000d0408 -#define OCTEON_CN56XX_PASS2_1 0x000d0409 - -#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION) -#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X -#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X - -#define OCTEON_CN57XX OCTEON_CN56XX -#define OCTEON_CN57XX_PASS1 OCTEON_CN56XX_PASS1 -#define OCTEON_CN57XX_PASS2 OCTEON_CN56XX_PASS2 - -#define OCTEON_CN55XX OCTEON_CN56XX -#define OCTEON_CN55XX_PASS1 OCTEON_CN56XX_PASS1 -#define OCTEON_CN55XX_PASS2 OCTEON_CN56XX_PASS2 - -#define OCTEON_CN54XX OCTEON_CN56XX -#define OCTEON_CN54XX_PASS1 OCTEON_CN56XX_PASS1 -#define OCTEON_CN54XX_PASS2 OCTEON_CN56XX_PASS2 - -#define OCTEON_CN50XX_PASS1_0 0x000d0600 - -#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION) -#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X +#define OCTEON_CN58XX_PASS1_0 0x000d0300 +#define OCTEON_CN58XX_PASS1_1 0x000d0301 +#define OCTEON_CN58XX_PASS1_2 0x000d0303 +#define OCTEON_CN58XX_PASS2_0 0x000d0308 +#define OCTEON_CN58XX_PASS2_1 0x000d0309 +#define OCTEON_CN58XX_PASS2_2 0x000d030a +#define OCTEON_CN58XX_PASS2_3 0x000d030b + +#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X +#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X + +#define OCTEON_CN56XX_PASS1_0 0x000d0400 +#define OCTEON_CN56XX_PASS1_1 0x000d0401 +#define OCTEON_CN56XX_PASS2_0 0x000d0408 +#define OCTEON_CN56XX_PASS2_1 0x000d0409 + +#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION) +#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X +#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X + +#define OCTEON_CN57XX OCTEON_CN56XX +#define OCTEON_CN57XX_PASS1 OCTEON_CN56XX_PASS1 +#define OCTEON_CN57XX_PASS2 OCTEON_CN56XX_PASS2 + +#define OCTEON_CN55XX OCTEON_CN56XX +#define OCTEON_CN55XX_PASS1 OCTEON_CN56XX_PASS1 +#define OCTEON_CN55XX_PASS2 OCTEON_CN56XX_PASS2 + +#define OCTEON_CN54XX OCTEON_CN56XX +#define OCTEON_CN54XX_PASS1 OCTEON_CN56XX_PASS1 +#define OCTEON_CN54XX_PASS2 OCTEON_CN56XX_PASS2 + +#define OCTEON_CN50XX_PASS1_0 0x000d0600 + +#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X /* * NOTE: Octeon CN5000F model is not identifiable using the * OCTEON_IS_MODEL() functions, but are treated as CN50XX. */ -#define OCTEON_CN52XX_PASS1_0 0x000d0700 -#define OCTEON_CN52XX_PASS2_0 0x000d0708 +#define OCTEON_CN52XX_PASS1_0 0x000d0700 +#define OCTEON_CN52XX_PASS2_0 0x000d0708 -#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION) -#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X -#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X +#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION) +#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X +#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X /* * CN3XXX models with old revision enconding */ -#define OCTEON_CN38XX_PASS1 0x000d0000 -#define OCTEON_CN38XX_PASS2 0x000d0001 -#define OCTEON_CN38XX_PASS3 0x000d0003 -#define OCTEON_CN38XX (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION) +#define OCTEON_CN38XX_PASS1 0x000d0000 +#define OCTEON_CN38XX_PASS2 0x000d0001 +#define OCTEON_CN38XX_PASS3 0x000d0003 +#define OCTEON_CN38XX (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION) -#define OCTEON_CN36XX OCTEON_CN38XX -#define OCTEON_CN36XX_PASS2 OCTEON_CN38XX_PASS2 -#define OCTEON_CN36XX_PASS3 OCTEON_CN38XX_PASS3 +#define OCTEON_CN36XX OCTEON_CN38XX +#define OCTEON_CN36XX_PASS2 OCTEON_CN38XX_PASS2 +#define OCTEON_CN36XX_PASS3 OCTEON_CN38XX_PASS3 /* The OCTEON_CN31XX matches CN31XX models and the CN3020 */ -#define OCTEON_CN31XX_PASS1 0x000d0100 -#define OCTEON_CN31XX_PASS1_1 0x000d0102 -#define OCTEON_CN31XX (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION) +#define OCTEON_CN31XX_PASS1 0x000d0100 +#define OCTEON_CN31XX_PASS1_1 0x000d0102 +#define OCTEON_CN31XX (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION) /* * This model is only used for internal checks, it is not a valid * model for the OCTEON_MODEL environment variable. This matches the * CN3010 and CN3005 but NOT the CN3020. */ -#define OCTEON_CN30XX_PASS1 0x000d0200 -#define OCTEON_CN30XX_PASS1_1 0x000d0202 -#define OCTEON_CN30XX (OCTEON_CN30XX_PASS1 | OM_IGNORE_REVISION) +#define OCTEON_CN30XX_PASS1 0x000d0200 +#define OCTEON_CN30XX_PASS1_1 0x000d0202 +#define OCTEON_CN30XX (OCTEON_CN30XX_PASS1 | OM_IGNORE_REVISION) -#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) +#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) -#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) +#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) -#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) +#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) /* * This matches the complete family of CN3xxx CPUs, and not subsequent * models */ -#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION) -#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS) -#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS) +#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION) +#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS) +#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS) /* These are used to cover entire families of OCTEON processors */ #define OCTEON_FAM_1 (OCTEON_CN3XXX) @@ -243,18 +243,18 @@ */ /* Masks used for the various types of model/family/revision matching */ -#define OCTEON_38XX_FAMILY_MASK 0x00ffff00 +#define OCTEON_38XX_FAMILY_MASK 0x00ffff00 #define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f -#define OCTEON_38XX_MODEL_MASK 0x00ffff10 +#define OCTEON_38XX_MODEL_MASK 0x00ffff10 #define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK | OCTEON_38XX_MODEL_MASK) /* CN5XXX and later use different layout of bits in the revision ID field */ -#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK +#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK #define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f -#define OCTEON_58XX_MODEL_MASK 0x00ffffc0 +#define OCTEON_58XX_MODEL_MASK 0x00ffffc0 #define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK) #define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00fffff8) -#define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0 +#define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0 /* forward declarations */ static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure)); @@ -264,7 +264,7 @@ static inline uint64_t cvmx_read_csr(uint64_t csr_addr); /* NOTE: This for internal use only! */ #define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model) \ -((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) && ( \ +((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) && ( \ ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \ && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_MASK)) || \ ((((arg_model) & (OM_FLAG_MASK)) == 0) \ @@ -276,7 +276,7 @@ static inline uint64_t cvmx_read_csr(uint64_t csr_addr); ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \ && (((chip_model) & OCTEON_38XX_MODEL_MASK) < ((arg_model) & OCTEON_38XX_MODEL_MASK))) \ )) || \ - (((arg_model & OCTEON_38XX_FAMILY_MASK) >= OCTEON_CN58XX_PASS1_0) && ( \ + (((arg_model & OCTEON_38XX_FAMILY_MASK) >= OCTEON_CN58XX_PASS1_0) && ( \ ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \ && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \ ((((arg_model) & (OM_FLAG_MASK)) == 0) \ @@ -320,7 +320,7 @@ static inline int __octeon_is_model_runtime__(uint32_t model) * Use of the macro in preprocessor directives ( #if OCTEON_IS_MODEL(...) ) * is NOT SUPPORTED, and should be replaced with CVMX_COMPILED_FOR() * I.e.: - * #if OCTEON_IS_MODEL(OCTEON_CN56XX) -> #if CVMX_COMPILED_FOR(OCTEON_CN56XX) + * #if OCTEON_IS_MODEL(OCTEON_CN56XX) -> #if CVMX_COMPILED_FOR(OCTEON_CN56XX) */ #define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x) #define OCTEON_IS_COMMON_BINARY() 1 diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index 254e9954ed7..d781f9e6688 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -75,15 +75,15 @@ struct octeon_boot_descriptor { uint32_t argc; uint32_t argv[OCTEON_ARGV_MAX_ARGS]; -#define BOOT_FLAG_INIT_CORE (1 << 0) -#define OCTEON_BL_FLAG_DEBUG (1 << 1) -#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2) +#define BOOT_FLAG_INIT_CORE (1 << 0) +#define OCTEON_BL_FLAG_DEBUG (1 << 1) +#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2) /* If set, use uart1 for console */ -#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3) +#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3) /* If set, use PCI console */ -#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4) +#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4) /* Call exit on break on serial port */ -#define OCTEON_BL_FLAG_BREAK (1 << 5) +#define OCTEON_BL_FLAG_BREAK (1 << 5) uint32_t flags; uint32_t core_mask; @@ -211,7 +211,6 @@ union octeon_cvmemctl { extern void octeon_write_lcd(const char *s); extern void octeon_check_cpu_bist(void); -extern int octeon_get_boot_debug_flag(void); extern int octeon_get_boot_uart(void); struct uart_port; @@ -251,4 +250,6 @@ extern void (*octeon_irq_setup_secondary)(void); typedef void (*octeon_irq_ip4_handler_t)(void); void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t); +extern void octeon_fixup_irqs(void); + #endif /* __ASM_OCTEON_OCTEON_H */ diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h index c66734bd338..64ba56a0284 100644 --- a/arch/mips/include/asm/octeon/pci-octeon.h +++ b/arch/mips/include/asm/octeon/pci-octeon.h @@ -22,7 +22,7 @@ #define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28) /* - * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2, + * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2, * place BAR1 so it is the same for both. */ #define CVMX_PCIE_BAR1_RC_BASE (1ull << 41) diff --git a/arch/mips/include/asm/paccess.h b/arch/mips/include/asm/paccess.h index 9ce5a1e7e14..2474fc5d175 100644 --- a/arch/mips/include/asm/paccess.h +++ b/arch/mips/include/asm/paccess.h @@ -43,7 +43,7 @@ struct __large_pstruct { unsigned long buf[100]; }; case 1: __get_dbe_asm("lb"); break; \ case 2: __get_dbe_asm("lh"); break; \ case 4: __get_dbe_asm("lw"); break; \ - case 8: __get_dbe_asm("ld"); break; \ + case 8: __get_dbe_asm("ld"); break; \ default: __get_dbe_unknown(); break; \ } \ x = (__typeof__(*(ptr))) __gu_val; \ diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index dbaec94046d..5699ec3a71a 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -11,6 +11,8 @@ #include <spaces.h> #include <linux/const.h> +#include <linux/kernel.h> +#include <asm/mipsregs.h> /* * PAGE_SHIFT determines the page size @@ -31,7 +33,30 @@ #define PAGE_SHIFT 16 #endif #define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE - 1)) +#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) + +/* + * This is used for calculating the real page sizes + * for FTLB or VTLB + FTLB confugrations. + */ +static inline unsigned int page_size_ftlb(unsigned int mmuextdef) +{ + switch (mmuextdef) { + case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: + if (PAGE_SIZE == (1 << 30)) + return 5; + if (PAGE_SIZE == (1llu << 32)) + return 6; + if (PAGE_SIZE > (256 << 10)) + return 7; /* reserved */ + /* fall through */ + case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: + return (PAGE_SHIFT - 10) / 2; + default: + panic("Invalid FTLB configuration with Conf4_mmuextdef=%d value\n", + mmuextdef >> 14); + } +} #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT #define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3) @@ -46,7 +71,6 @@ #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ #include <linux/pfn.h> -#include <asm/io.h> extern void build_clear_page(void); extern void build_copy_page(void); @@ -95,11 +119,11 @@ extern void copy_user_highpage(struct page *to, struct page *from, #ifdef CONFIG_64BIT_PHYS_ADDR #ifdef CONFIG_CPU_MIPS32 typedef struct { unsigned long pte_low, pte_high; } pte_t; - #define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32)) - #define __pte(x) ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; }) + #define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32)) + #define __pte(x) ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; }) #else typedef struct { unsigned long long pte; } pte_t; - #define pte_val(x) ((x).pte) + #define pte_val(x) ((x).pte) #define __pte(x) ((pte_t) { (x) } ) #endif #else @@ -151,6 +175,7 @@ typedef struct { unsigned long pgprot; } pgprot_t; ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) #endif #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) +#include <asm/io.h> /* * RELOC_HIDE was originally added by 6007b903dfe5f1d13e0c711ac2894bdd4a61b1ad @@ -165,20 +190,21 @@ typedef struct { unsigned long pgprot; } pgprot_t; * https://patchwork.linux-mips.org/patch/1541/ */ +#ifndef __pa_symbol #define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x), 0)) +#endif #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) #ifdef CONFIG_FLATMEM -#define pfn_valid(pfn) \ -({ \ - unsigned long __pfn = (pfn); \ - /* avoid <linux/bootmem.h> include hell */ \ - extern unsigned long min_low_pfn; \ - \ - __pfn >= min_low_pfn && __pfn < max_mapnr; \ -}) +static inline int pfn_valid(unsigned long pfn) +{ + /* avoid <linux/mm.h> include hell */ + extern unsigned long max_mapnr; + + return pfn >= ARCH_PFN_OFFSET && pfn < max_mapnr; +} #elif defined(CONFIG_SPARSEMEM) @@ -191,8 +217,8 @@ typedef struct { unsigned long pgprot; } pgprot_t; unsigned long __pfn = (pfn); \ int __n = pfn_to_nid(__pfn); \ ((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn + \ - NODE_DATA(__n)->node_spanned_pages) \ - : 0); \ + NODE_DATA(__n)->node_spanned_pages) \ + : 0); \ }) #endif @@ -206,10 +232,8 @@ extern int __virt_addr_valid(const volatile void *kaddr); #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) -#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE + \ - PHYS_OFFSET) -#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET - \ - PHYS_OFFSET) +#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE) +#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET) #include <asm-generic/memory_model.h> #include <asm-generic/getorder.h> diff --git a/arch/mips/include/asm/parport.h b/arch/mips/include/asm/parport.h deleted file mode 100644 index cf252af6459..00000000000 --- a/arch/mips/include/asm/parport.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/parport.h> diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index d69ea743272..974b0e30896 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -12,7 +12,7 @@ /* * This file essentially defines the interface between board - * specific PCI code and MIPS common PCI code. Should potentially put + * specific PCI code and MIPS common PCI code. Should potentially put * into include/asm/pci.h file. */ @@ -20,7 +20,7 @@ #include <linux/of.h> /* - * Each pci channel is a top-level PCI bus seem by CPU. A machine with + * Each pci channel is a top-level PCI bus seem by CPU. A machine with * multiple PCI channels may have multiple PCI host controllers or a * single controller supporting multiple channels. */ @@ -52,7 +52,6 @@ struct pci_controller { /* * Used by boards to register their PCI busses before the actual scanning. */ -extern struct pci_controller * alloc_pci_controller(void); extern void register_pci_controller(struct pci_controller *hose); /* @@ -74,16 +73,23 @@ extern unsigned long PCIBIOS_MIN_MEM; extern void pcibios_set_master(struct pci_dev *dev); -static inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - #define HAVE_PCI_MMAP extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); +#define HAVE_ARCH_PCI_RESOURCE_TO_USER + +static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, + const struct resource *rsrc, resource_size_t *start, + resource_size_t *end) +{ + phys_t size = resource_size(rsrc); + + *start = fixup_bigphys_addr(rsrc->start, size); + *end = rsrc->start + size; +} + /* * Dynamic DMA mapping stuff. * MIPS has everything mapped statically. @@ -99,7 +105,7 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, struct pci_dev; /* - * The PCI address space does equal the physical memory address space. The + * The PCI address space does equal the physical memory address space. The * networking and block device layers use this boolean for bounce buffer * decisions. This is set if any hose does not have an IOMMU. */ @@ -137,15 +143,15 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) return channel ? 15 : 14; } -#ifdef CONFIG_CPU_CAVIUM_OCTEON -/* MSI arch hook for OCTEON */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#endif - extern char * (*pcibios_plat_setup)(char *str); +#ifdef CONFIG_OF /* this function parses memory ranges from a device node */ extern void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node); +#else +static inline void pci_load_of_ranges(struct pci_controller *hose, + struct device_node *node) {} +#endif #endif /* _ASM_PCI_H */ diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h index be44fb0266d..af2c8a351ca 100644 --- a/arch/mips/include/asm/pci/bridge.h +++ b/arch/mips/include/asm/pci/bridge.h @@ -85,7 +85,7 @@ typedef volatile struct bridge_s { #define b_wid_llp b_widget.w_llp_cfg #define b_wid_tflush b_widget.w_tflush - /* bridge-specific widget configuration 0x000058-0x00007F */ + /* bridge-specific widget configuration 0x000058-0x00007F */ bridgereg_t _pad_000058; bridgereg_t b_wid_aux_err; /* 0x00005C */ bridgereg_t _pad_000060; @@ -167,8 +167,8 @@ typedef volatile struct bridge_s { bridgereg_t __pad; /* 0x0002{80,,,88} */ bridgereg_t reg; /* 0x0002{84,,,8C} */ } b_rrb_map[2]; /* 0x000280 */ -#define b_even_resp b_rrb_map[0].reg /* 0x000284 */ -#define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ +#define b_even_resp b_rrb_map[0].reg /* 0x000284 */ +#define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ bridgereg_t _pad_000290; bridgereg_t b_resp_status; /* 0x000294 */ @@ -233,7 +233,7 @@ typedef volatile struct bridge_s { u8 _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */ /* External Address Translation Entry RAM 0x080000-0x0FFFFF */ - bridge_ate_t b_ext_ate_ram[0x10000]; + bridge_ate_t b_ext_ate_ram[0x10000]; /* Reserved 0x100000-0x1FFFFF */ char _pad_100000[0x200000-0x100000]; @@ -400,7 +400,7 @@ typedef struct bridge_err_cmdword_s { #define BRIDGE_REV_A 0x1 #define BRIDGE_REV_B 0x2 #define BRIDGE_REV_C 0x3 -#define BRIDGE_REV_D 0x4 +#define BRIDGE_REV_D 0x4 /* Bridge widget status register bits definition */ @@ -691,21 +691,21 @@ typedef struct bridge_err_cmdword_s { #define BRIDGE_CREDIT 3 /* RRB assignment register */ -#define BRIDGE_RRB_EN 0x8 /* after shifting down */ -#define BRIDGE_RRB_DEV 0x7 /* after shifting down */ -#define BRIDGE_RRB_VDEV 0x4 /* after shifting down */ -#define BRIDGE_RRB_PDEV 0x3 /* after shifting down */ +#define BRIDGE_RRB_EN 0x8 /* after shifting down */ +#define BRIDGE_RRB_DEV 0x7 /* after shifting down */ +#define BRIDGE_RRB_VDEV 0x4 /* after shifting down */ +#define BRIDGE_RRB_PDEV 0x3 /* after shifting down */ /* RRB status register */ -#define BRIDGE_RRB_VALID(r) (0x00010000<<(r)) -#define BRIDGE_RRB_INUSE(r) (0x00000001<<(r)) +#define BRIDGE_RRB_VALID(r) (0x00010000<<(r)) +#define BRIDGE_RRB_INUSE(r) (0x00000001<<(r)) /* RRB clear register */ -#define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r)) +#define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r)) /* xbox system controller declarations */ -#define XBOX_BRIDGE_WID 8 -#define FLASH_PROM1_BASE 0xE00000 /* To read the xbox sysctlr status */ +#define XBOX_BRIDGE_WID 8 +#define FLASH_PROM1_BASE 0xE00000 /* To read the xbox sysctlr status */ #define XBOX_RPS_EXISTS 1 << 6 /* RPS bit in status register */ #define XBOX_RPS_FAIL 1 << 4 /* RPS status bit in register */ @@ -838,7 +838,7 @@ struct bridge_controller { bridge_t *base; nasid_t nasid; unsigned int widget_id; - unsigned int irq_cpu; + unsigned int irq_cpu; u64 baddr; unsigned int pci_int[8]; }; diff --git a/arch/mips/include/asm/percpu.h b/arch/mips/include/asm/percpu.h deleted file mode 100644 index 844e763e933..00000000000 --- a/arch/mips/include/asm/percpu.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_PERCPU_H -#define __ASM_PERCPU_H - -#include <asm-generic/percpu.h> - -#endif /* __ASM_PERCPU_H */ diff --git a/arch/mips/include/asm/pgalloc.h b/arch/mips/include/asm/pgalloc.h index 881d18b4e29..b336037e876 100644 --- a/arch/mips/include/asm/pgalloc.h +++ b/arch/mips/include/asm/pgalloc.h @@ -80,9 +80,12 @@ static inline struct page *pte_alloc_one(struct mm_struct *mm, struct page *pte; pte = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER); - if (pte) { - clear_highpage(pte); - pgtable_page_ctor(pte); + if (!pte) + return NULL; + clear_highpage(pte); + if (!pgtable_page_ctor(pte)) { + __free_page(pte); + return NULL; } return pte; } diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h index 5d56bb23034..b4204c179b9 100644 --- a/arch/mips/include/asm/pgtable-32.h +++ b/arch/mips/include/asm/pgtable-32.h @@ -47,7 +47,7 @@ #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) #define FIRST_USER_ADDRESS 0 -#define VMALLOC_START MAP_BASE +#define VMALLOC_START MAP_BASE #define PKMAP_BASE (0xfe000000UL) @@ -136,7 +136,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) #define pte_offset_kernel(dir, address) \ ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) -#define pte_offset_map(dir, address) \ +#define pte_offset_map(dir, address) \ ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) #define pte_unmap(pte) ((void)(pte)) @@ -155,7 +155,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) #define pte_to_pgoff(_pte) ((((_pte).pte >> 1 ) & 0x07) | \ (((_pte).pte >> 2 ) & 0x38) | \ - (((_pte).pte >> 10) << 6 )) + (((_pte).pte >> 10) << 6 )) #define pgoff_to_pte(off) ((pte_t) { (((off) & 0x07) << 1 ) | \ (((off) & 0x38) << 2 ) | \ @@ -167,14 +167,14 @@ pfn_pte(unsigned long pfn, pgprot_t prot) /* Swap entries must have VALID and GLOBAL bits cleared. */ #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) #define __swp_type(x) (((x).val >> 2) & 0x1f) -#define __swp_offset(x) ((x).val >> 7) +#define __swp_offset(x) ((x).val >> 7) #define __swp_entry(type,offset) \ - ((swp_entry_t) { ((type) << 2) | ((offset) << 7) }) + ((swp_entry_t) { ((type) << 2) | ((offset) << 7) }) #else #define __swp_type(x) (((x).val >> 8) & 0x1f) -#define __swp_offset(x) ((x).val >> 13) +#define __swp_offset(x) ((x).val >> 13) #define __swp_entry(type,offset) \ - ((swp_entry_t) { ((type) << 8) | ((offset) << 13) }) + ((swp_entry_t) { ((type) << 8) | ((offset) << 13) }) #endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) @@ -184,7 +184,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) #define PTE_FILE_MAX_BITS 30 #define pte_to_pgoff(_pte) ((_pte).pte_high >> 2) -#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) << 2 }) +#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) << 2 }) #else /* @@ -194,7 +194,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) #define pte_to_pgoff(_pte) ((((_pte).pte >> 1) & 0x7) | \ (((_pte).pte >> 2) & 0x8) | \ - (((_pte).pte >> 8) << 4)) + (((_pte).pte >> 8) << 4)) #define pgoff_to_pte(off) ((pte_t) { (((off) & 0x7) << 1) | \ (((off) & 0x8) << 2) | \ @@ -208,7 +208,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high }) #define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val }) #else -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) +#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) #endif diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index c63191055e6..e1c49a96807 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -115,7 +115,7 @@ #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) #if PGDIR_SIZE >= TASK_SIZE64 -#define USER_PTRS_PER_PGD (1) +#define USER_PTRS_PER_PGD (1) #else #define USER_PTRS_PER_PGD (TASK_SIZE64 / PGDIR_SIZE) #endif @@ -230,6 +230,7 @@ static inline void pud_clear(pud_t *pudp) #else #define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT)) #define pfn_pte(pfn, prot) __pte(((pfn) << _PFN_SHIFT) | pgprot_val(prot)) +#define pfn_pmd(pfn, prot) __pmd(((pfn) << _PFN_SHIFT) | pgprot_val(prot)) #endif #define __pgd_offset(address) pgd_index(address) @@ -287,7 +288,7 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) #define __swp_type(x) (((x).val >> 32) & 0xff) #define __swp_offset(x) ((x).val >> 40) #define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) }) -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) +#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) /* diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index f6a0439a408..e592f3687d6 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -21,7 +21,7 @@ * Similar to the Alpha port, we need to keep track of the ref * and mod bits in software. We have a software "yeah you can read * from this page" bit, and a hardware one which actually lets the - * process read from the page. On the same token we have a software + * process read from the page. On the same token we have a software * writable bit and the real hardware one which actually lets the * process write to the page, this keeps a mod bit via the hardware * dirty bit. @@ -41,9 +41,9 @@ #define _PAGE_GLOBAL (1 << 0) #define _PAGE_VALID_SHIFT 1 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) -#define _PAGE_SILENT_READ (1 << 1) /* synonym */ +#define _PAGE_SILENT_READ (1 << 1) /* synonym */ #define _PAGE_DIRTY_SHIFT 2 -#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) /* The MIPS dirty bit */ +#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) /* The MIPS dirty bit */ #define _PAGE_SILENT_WRITE (1 << 2) #define _CACHE_SHIFT 3 #define _CACHE_MASK (7 << 3) @@ -52,7 +52,7 @@ * The following bits are implemented in software * * _PAGE_FILE semantics: set:pagecache unset:swap - */ + */ #define _PAGE_PRESENT_SHIFT 6 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) #define _PAGE_READ_SHIFT 7 @@ -134,7 +134,7 @@ #define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) #else #define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT) -#define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */ +#define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */ #endif #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT @@ -143,7 +143,7 @@ #define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT) #else #define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT) -#define _PAGE_SPLITTING ({BUG(); 1; }) /* Dummy value */ +#define _PAGE_SPLITTING ({BUG(); 1; }) /* Dummy value */ #endif /* Page cannot be executed */ @@ -159,10 +159,10 @@ #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) -/* synonym */ +/* synonym */ #define _PAGE_SILENT_READ (_PAGE_VALID) -/* The MIPS dirty bit */ +/* The MIPS dirty bit */ #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) #define _PAGE_SILENT_WRITE (_PAGE_DIRTY) @@ -175,7 +175,7 @@ #endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ #ifndef _PFN_SHIFT -#define _PFN_SHIFT PAGE_SHIFT +#define _PFN_SHIFT PAGE_SHIFT #endif #define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) @@ -230,28 +230,37 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) /* No penalty for being coherent on the SB1, so just use it for "noncoherent" spaces, too. Shouldn't hurt. */ -#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) -#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) +#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) +#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) +#elif defined(CONFIG_CPU_LOONGSON3) + +/* Using COHERENT flag for NONCOHERENT doesn't hurt. */ + +#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* LOONGSON */ +#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ +#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ +#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* LOONGSON */ + #else -#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */ -#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */ -#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */ -#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */ -#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */ -#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */ -#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */ -#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */ -#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */ +#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */ +#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */ +#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */ +#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */ +#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */ +#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */ +#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */ +#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */ +#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */ #endif #define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ)) #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) -#define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) +#define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) #endif /* _ASM_PGTABLE_BITS_H */ diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index ec50d52cfb7..539ddd148bb 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -8,6 +8,7 @@ #ifndef _ASM_PGTABLE_H #define _ASM_PGTABLE_H +#include <linux/mm_types.h> #include <linux/mmzone.h> #ifdef CONFIG_32BIT #include <asm/pgtable-32.h> @@ -31,6 +32,8 @@ struct vm_area_struct; _page_cachable_default) #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ _PAGE_GLOBAL | _page_cachable_default) +#define PAGE_KERNEL_NC __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ + _PAGE_GLOBAL | _CACHE_CACHABLE_NONCOHERENT) #define PAGE_USERIO __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \ _page_cachable_default) #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ @@ -112,7 +115,7 @@ static inline void set_pte(pte_t *ptep, pte_t pte) * it better already be global) */ if (pte_none(*buddy)) { - buddy->pte_low |= _PAGE_GLOBAL; + buddy->pte_low |= _PAGE_GLOBAL; buddy->pte_high |= _PAGE_GLOBAL; } } @@ -319,7 +322,7 @@ static inline int pte_special(pte_t pte) { return 0; } static inline pte_t pte_mkspecial(pte_t pte) { return pte; } /* - * Macro to make mark a page protection value as "uncacheable". Note + * Macro to make mark a page protection value as "uncacheable". Note * that "protection" is really a misnomer here as the protection value * contains the memory attribute bits, dirty bits, and various other * bits as well. @@ -393,9 +396,7 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma, phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size); return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot); } -#else -#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ - remap_pfn_range(vma, vaddr, pfn, size, prot) +#define io_remap_pfn_range io_remap_pfn_range #endif #ifdef CONFIG_TRANSPARENT_HUGEPAGE diff --git a/arch/mips/include/asm/pm-cps.h b/arch/mips/include/asm/pm-cps.h new file mode 100644 index 00000000000..625eda53d57 --- /dev/null +++ b/arch/mips/include/asm/pm-cps.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2014 Imagination Technologies + * Author: Paul Burton <paul.burton@imgtec.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MIPS_ASM_PM_CPS_H__ +#define __MIPS_ASM_PM_CPS_H__ + +/* + * The CM & CPC can only handle coherence & power control on a per-core basis, + * thus in an MT system the VPEs within each core are coupled and can only + * enter or exit states requiring CM or CPC assistance in unison. + */ +#ifdef CONFIG_MIPS_MT +# define coupled_coherence cpu_has_mipsmt +#else +# define coupled_coherence 0 +#endif + +/* Enumeration of possible PM states */ +enum cps_pm_state { + CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */ + CPS_PM_CLOCK_GATED, /* Core clock gated */ + CPS_PM_POWER_GATED, /* Core power gated */ + CPS_PM_STATE_COUNT, +}; + +/** + * cps_pm_support_state - determine whether the system supports a PM state + * @state: the state to test for support + * + * Returns true if the system supports the given state, otherwise false. + */ +extern bool cps_pm_support_state(enum cps_pm_state state); + +/** + * cps_pm_enter_state - enter a PM state + * @state: the state to enter + * + * Enter the given PM state. If coupled_coherence is non-zero then it is + * expected that this function be called at approximately the same time on + * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno. + */ +extern int cps_pm_enter_state(enum cps_pm_state state); + +#endif /* __MIPS_ASM_PM_CPS_H__ */ diff --git a/arch/mips/include/asm/pm.h b/arch/mips/include/asm/pm.h new file mode 100644 index 00000000000..7c03469e043 --- /dev/null +++ b/arch/mips/include/asm/pm.h @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2014 Imagination Technologies Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * PM helper macros for CPU power off (e.g. Suspend-to-RAM). + */ + +#ifndef __ASM_PM_H +#define __ASM_PM_H + +#ifdef __ASSEMBLY__ + +#include <asm/asm-offsets.h> +#include <asm/asm.h> +#include <asm/mipsregs.h> +#include <asm/regdef.h> + +/* Save CPU state to stack for suspend to RAM */ +.macro SUSPEND_SAVE_REGS + subu sp, PT_SIZE + /* Call preserved GPRs */ + LONG_S $16, PT_R16(sp) + LONG_S $17, PT_R17(sp) + LONG_S $18, PT_R18(sp) + LONG_S $19, PT_R19(sp) + LONG_S $20, PT_R20(sp) + LONG_S $21, PT_R21(sp) + LONG_S $22, PT_R22(sp) + LONG_S $23, PT_R23(sp) + LONG_S $28, PT_R28(sp) + LONG_S $30, PT_R30(sp) + LONG_S $31, PT_R31(sp) + /* A couple of CP0 registers with space in pt_regs */ + mfc0 k0, CP0_STATUS + LONG_S k0, PT_STATUS(sp) +.endm + +/* Restore CPU state from stack after resume from RAM */ +.macro RESUME_RESTORE_REGS_RETURN + .set push + .set noreorder + /* A couple of CP0 registers with space in pt_regs */ + LONG_L k0, PT_STATUS(sp) + mtc0 k0, CP0_STATUS + /* Call preserved GPRs */ + LONG_L $16, PT_R16(sp) + LONG_L $17, PT_R17(sp) + LONG_L $18, PT_R18(sp) + LONG_L $19, PT_R19(sp) + LONG_L $20, PT_R20(sp) + LONG_L $21, PT_R21(sp) + LONG_L $22, PT_R22(sp) + LONG_L $23, PT_R23(sp) + LONG_L $28, PT_R28(sp) + LONG_L $30, PT_R30(sp) + LONG_L $31, PT_R31(sp) + /* Pop and return */ + jr ra + addiu sp, PT_SIZE + .set pop +.endm + +/* Get address of static suspend state into t1 */ +.macro LA_STATIC_SUSPEND + la t1, mips_static_suspend_state +.endm + +/* Save important CPU state for early restoration to global data */ +.macro SUSPEND_SAVE_STATIC +#ifdef CONFIG_EVA + /* + * Segment configuration is saved in global data where it can be easily + * reloaded without depending on the segment configuration. + */ + mfc0 k0, CP0_PAGEMASK, 2 /* SegCtl0 */ + LONG_S k0, SSS_SEGCTL0(t1) + mfc0 k0, CP0_PAGEMASK, 3 /* SegCtl1 */ + LONG_S k0, SSS_SEGCTL1(t1) + mfc0 k0, CP0_PAGEMASK, 4 /* SegCtl2 */ + LONG_S k0, SSS_SEGCTL2(t1) +#endif + /* save stack pointer (pointing to GPRs) */ + LONG_S sp, SSS_SP(t1) +.endm + +/* Restore important CPU state early from global data */ +.macro RESUME_RESTORE_STATIC +#ifdef CONFIG_EVA + /* + * Segment configuration must be restored prior to any access to + * allocated memory, as it may reside outside of the legacy kernel + * segments. + */ + LONG_L k0, SSS_SEGCTL0(t1) + mtc0 k0, CP0_PAGEMASK, 2 /* SegCtl0 */ + LONG_L k0, SSS_SEGCTL1(t1) + mtc0 k0, CP0_PAGEMASK, 3 /* SegCtl1 */ + LONG_L k0, SSS_SEGCTL2(t1) + mtc0 k0, CP0_PAGEMASK, 4 /* SegCtl2 */ + tlbw_use_hazard +#endif + /* restore stack pointer (pointing to GPRs) */ + LONG_L sp, SSS_SP(t1) +.endm + +/* flush caches to make sure context has reached memory */ +.macro SUSPEND_CACHE_FLUSH + .extern __wback_cache_all + .set push + .set noreorder + la t1, __wback_cache_all + LONG_L t0, 0(t1) + jalr t0 + nop + .set pop + .endm + +/* Save suspend state and flush data caches to RAM */ +.macro SUSPEND_SAVE + SUSPEND_SAVE_REGS + LA_STATIC_SUSPEND + SUSPEND_SAVE_STATIC + SUSPEND_CACHE_FLUSH +.endm + +/* Restore saved state after resume from RAM and return */ +.macro RESUME_RESTORE_RETURN + LA_STATIC_SUSPEND + RESUME_RESTORE_STATIC + RESUME_RESTORE_REGS_RETURN +.endm + +#else /* __ASSEMBLY__ */ + +/** + * struct mips_static_suspend_state - Core saved CPU state across S2R. + * @segctl: CP0 Segment control registers. + * @sp: Stack frame where GP register context is saved. + * + * This structure contains minimal CPU state that must be saved in static kernel + * data in order to be able to restore the rest of the state. This includes + * segmentation configuration in the case of EVA being enabled, as they must be + * restored prior to any kmalloc'd memory being referenced (even the stack + * pointer). + */ +struct mips_static_suspend_state { +#ifdef CONFIG_EVA + unsigned long segctl[3]; +#endif + unsigned long sp; +}; + +#endif /* !__ASSEMBLY__ */ + +#endif /* __ASM_PM_HELPERS_H */ diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/gpio.h b/arch/mips/include/asm/pmc-sierra/msp71xx/gpio.h deleted file mode 100644 index ebdbab973e4..00000000000 --- a/arch/mips/include/asm/pmc-sierra/msp71xx/gpio.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * include/asm-mips/pmc-sierra/msp71xx/gpio.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * @author Patrick Glass <patrickglass@gmail.com> - */ - -#ifndef __PMC_MSP71XX_GPIO_H -#define __PMC_MSP71XX_GPIO_H - -/* Max number of gpio's is 28 on chip plus 3 banks of I2C IO Expanders */ -#define ARCH_NR_GPIOS (28 + (3 * 8)) - -/* new generic GPIO API - see Documentation/gpio.txt */ -#include <asm-generic/gpio.h> - -#define gpio_get_value __gpio_get_value -#define gpio_set_value __gpio_set_value -#define gpio_cansleep __gpio_cansleep - -/* Setup calls for the gpio and gpio extended */ -extern void msp71xx_init_gpio(void); -extern void msp71xx_init_gpio_extended(void); -extern int msp71xx_set_output_drive(unsigned gpio, int value); - -/* Custom output drive functionss */ -static inline int gpio_set_output_drive(unsigned gpio, int value) -{ - return msp71xx_set_output_drive(gpio, value); -} - -/* IRQ's are not supported for gpio lines */ -static inline int gpio_to_irq(unsigned gpio) -{ - return -EINVAL; -} - -static inline int irq_to_gpio(unsigned irq) -{ - return -EINVAL; -} - -#endif /* __PMC_MSP71XX_GPIO_H */ diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index bd98b503f04..ad70cba8daf 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -28,7 +28,6 @@ /* * System setup and hardware flags.. */ -extern void (*cpu_wait)(void); extern unsigned int vced_count, vcei_count; @@ -44,11 +43,16 @@ extern unsigned int vced_count, vcei_count; #define SPECIAL_PAGES_SIZE PAGE_SIZE #ifdef CONFIG_32BIT +#ifdef CONFIG_KVM_GUEST +/* User space process size is limited to 1GB in KVM Guest Mode */ +#define TASK_SIZE 0x3fff8000UL +#else /* * User space process size: 2GB. This is hardcoded into a few places, * so don't change it unless you know what you are doing. */ #define TASK_SIZE 0x7fff8000UL +#endif #ifdef __KERNEL__ #define STACK_TOP_MAX TASK_SIZE @@ -93,18 +97,48 @@ extern unsigned int vced_count, vcei_count; #define NUM_FPU_REGS 32 -typedef __u64 fpureg_t; +#ifdef CONFIG_CPU_HAS_MSA +# define FPU_REG_WIDTH 128 +#else +# define FPU_REG_WIDTH 64 +#endif + +union fpureg { + __u32 val32[FPU_REG_WIDTH / 32]; + __u64 val64[FPU_REG_WIDTH / 64]; +}; + +#ifdef CONFIG_CPU_LITTLE_ENDIAN +# define FPR_IDX(width, idx) (idx) +#else +# define FPR_IDX(width, idx) ((FPU_REG_WIDTH / (width)) - 1 - (idx)) +#endif + +#define BUILD_FPR_ACCESS(width) \ +static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx) \ +{ \ + return fpr->val##width[FPR_IDX(width, idx)]; \ +} \ + \ +static inline void set_fpr##width(union fpureg *fpr, unsigned idx, \ + u##width val) \ +{ \ + fpr->val##width[FPR_IDX(width, idx)] = val; \ +} + +BUILD_FPR_ACCESS(32) +BUILD_FPR_ACCESS(64) /* - * It would be nice to add some more fields for emulator statistics, but there - * are a number of fixed offsets in offset.h and elsewhere that would have to - * be recalculated by hand. So the additional information will be private to - * the FPU emulator for now. See asm-mips/fpu_emulator.h. + * It would be nice to add some more fields for emulator statistics, + * the additional information is private to the FPU emulator for now. + * See arch/mips/include/asm/fpu_emulator.h. */ struct mips_fpu_struct { - fpureg_t fpr[NUM_FPU_REGS]; + union fpureg fpr[NUM_FPU_REGS]; unsigned int fcr31; + unsigned int msacsr; }; #define NUM_DSP_REGS 6 @@ -112,8 +146,8 @@ struct mips_fpu_struct { typedef __u32 dspreg_t; struct mips_dsp_state { - dspreg_t dspr[NUM_DSP_REGS]; - unsigned int dspcontrol; + dspreg_t dspr[NUM_DSP_REGS]; + unsigned int dspcontrol; }; #define INIT_CPUMASK { \ @@ -133,58 +167,71 @@ union mips_watch_reg_state { struct mips3264_watch_reg_state mips3264; }; -#ifdef CONFIG_CPU_CAVIUM_OCTEON +#if defined(CONFIG_CPU_CAVIUM_OCTEON) struct octeon_cop2_state { /* DMFC2 rt, 0x0201 */ - unsigned long cop2_crc_iv; + unsigned long cop2_crc_iv; /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */ - unsigned long cop2_crc_length; + unsigned long cop2_crc_length; /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */ - unsigned long cop2_crc_poly; + unsigned long cop2_crc_poly; /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */ - unsigned long cop2_llm_dat[2]; + unsigned long cop2_llm_dat[2]; /* DMFC2 rt, 0x0084 */ - unsigned long cop2_3des_iv; + unsigned long cop2_3des_iv; /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */ - unsigned long cop2_3des_key[3]; + unsigned long cop2_3des_key[3]; /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */ - unsigned long cop2_3des_result; + unsigned long cop2_3des_result; /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */ - unsigned long cop2_aes_inp0; + unsigned long cop2_aes_inp0; /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */ - unsigned long cop2_aes_iv[2]; + unsigned long cop2_aes_iv[2]; /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2 * rt, 0x0107 */ - unsigned long cop2_aes_key[4]; + unsigned long cop2_aes_key[4]; /* DMFC2 rt, 0x0110 */ - unsigned long cop2_aes_keylen; + unsigned long cop2_aes_keylen; /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */ - unsigned long cop2_aes_result[2]; + unsigned long cop2_aes_result[2]; /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt, * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt, * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt, * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */ - unsigned long cop2_hsh_datw[15]; + unsigned long cop2_hsh_datw[15]; /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt, * 0x0256; DMFC2 rt, 0x0257 - Pass2 */ - unsigned long cop2_hsh_ivw[8]; + unsigned long cop2_hsh_ivw[8]; /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */ - unsigned long cop2_gfm_mult[2]; + unsigned long cop2_gfm_mult[2]; /* DMFC2 rt, 0x025E - Pass2 */ - unsigned long cop2_gfm_poly; + unsigned long cop2_gfm_poly; /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */ - unsigned long cop2_gfm_result[2]; + unsigned long cop2_gfm_result[2]; }; -#define INIT_OCTEON_COP2 {0,} +#define COP2_INIT \ + .cp2 = {0,}, struct octeon_cvmseg_state { unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE] [cpu_dcache_line_size() / sizeof(unsigned long)]; }; +#elif defined(CONFIG_CPU_XLP) +struct nlm_cop2_state { + u64 rx[4]; + u64 tx[4]; + u32 tx_msg_status; + u32 rx_msg_status; +}; + +#define COP2_INIT \ + .cp2 = {{0}, {0}, 0, 0}, +#else +#define COP2_INIT #endif typedef struct { @@ -227,8 +274,11 @@ struct thread_struct { unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ unsigned long error_code; #ifdef CONFIG_CPU_CAVIUM_OCTEON - struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); - struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); + struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); + struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); +#endif +#ifdef CONFIG_CPU_XLP + struct nlm_cop2_state cp2; #endif struct mips_abi *abi; }; @@ -241,17 +291,10 @@ struct thread_struct { #define FPAFF_INIT #endif /* CONFIG_MIPS_MT_FPAFF */ -#ifdef CONFIG_CPU_CAVIUM_OCTEON -#define OCTEON_INIT \ - .cp2 = INIT_OCTEON_COP2, -#else -#define OCTEON_INIT -#endif /* CONFIG_CPU_CAVIUM_OCTEON */ - #define INIT_THREAD { \ - /* \ - * Saved main processor registers \ - */ \ + /* \ + * Saved main processor registers \ + */ \ .reg16 = 0, \ .reg17 = 0, \ .reg18 = 0, \ @@ -271,8 +314,9 @@ struct thread_struct { * Saved FPU/FPU emulator stuff \ */ \ .fpu = { \ - .fpr = {0,}, \ + .fpr = {{{0,},},}, \ .fcr31 = 0, \ + .msacsr = 0, \ }, \ /* \ * FPU affinity state (null if not FPAFF) \ @@ -296,9 +340,9 @@ struct thread_struct { .cp0_baduaddr = 0, \ .error_code = 0, \ /* \ - * Cavium Octeon specifics (null if not Octeon) \ + * Platform specific cop2 registers(null if no COP2) \ */ \ - OCTEON_INIT \ + COP2_INIT \ } struct task_struct; @@ -332,7 +376,7 @@ unsigned long get_wchan(struct task_struct *p); * aborts compilation on some CPUs. It's simply not possible to unwind * some CPU's stackframes. * - * __builtin_return_address works only for non-leaf functions. We avoid the + * __builtin_return_address works only for non-leaf functions. We avoid the * overhead of a function call by forcing the compiler to save the return * address register on the stack. */ diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h index 8808bf548b9..a9494c0141f 100644 --- a/arch/mips/include/asm/prom.h +++ b/arch/mips/include/asm/prom.h @@ -17,35 +17,24 @@ #include <linux/types.h> #include <asm/bootinfo.h> -extern int early_init_dt_scan_memory_arch(unsigned long node, - const char *uname, int depth, void *data); - extern void device_tree_init(void); -static inline unsigned long pci_address_to_pio(phys_addr_t address) -{ - /* - * The ioport address can be directly used by inX() / outX() - */ - BUG_ON(address > IO_SPACE_LIMIT); - - return (unsigned long) address; -} -#define pci_address_to_pio pci_address_to_pio - struct boot_param_header; -extern void __dt_setup_arch(struct boot_param_header *bph); +extern void __dt_setup_arch(void *bph); #define dt_setup_arch(sym) \ ({ \ - extern struct boot_param_header __dtb_##sym##_begin; \ + extern char __dtb_##sym##_begin[]; \ \ - __dt_setup_arch(&__dtb_##sym##_begin); \ + __dt_setup_arch(__dtb_##sym##_begin); \ }) #else /* CONFIG_OF */ static inline void device_tree_init(void) { } #endif /* CONFIG_OF */ +extern char *mips_get_machine_name(void); +extern void mips_set_machine_name(const char *name); + #endif /* __ASM_PROM_H */ diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h index a3186f2bb8a..7e6e682aece 100644 --- a/arch/mips/include/asm/ptrace.h +++ b/arch/mips/include/asm/ptrace.h @@ -16,6 +16,35 @@ #include <asm/isadep.h> #include <uapi/asm/ptrace.h> +/* + * This struct defines the way the registers are stored on the stack during a + * system call/exception. As usual the registers k0/k1 aren't being saved. + */ +struct pt_regs { +#ifdef CONFIG_32BIT + /* Pad bytes for argument save space on the stack. */ + unsigned long pad0[6]; +#endif + + /* Saved main processor registers. */ + unsigned long regs[32]; + + /* Saved special registers. */ + unsigned long cp0_status; + unsigned long hi; + unsigned long lo; +#ifdef CONFIG_CPU_HAS_SMARTMIPS + unsigned long acx; +#endif + unsigned long cp0_badvaddr; + unsigned long cp0_cause; + unsigned long cp0_epc; +#ifdef CONFIG_CPU_CAVIUM_OCTEON + unsigned long long mpl[3]; /* MTM{0,1,2} */ + unsigned long long mtp[3]; /* MTP{0,1,2} */ +#endif +} __aligned(8); + struct task_struct; extern int ptrace_getregs(struct task_struct *child, __s64 __user *data); @@ -49,9 +78,8 @@ static inline long regs_return_value(struct pt_regs *regs) #define instruction_pointer(regs) ((regs)->cp0_epc) #define profile_pc(regs) instruction_pointer(regs) -#define user_stack_pointer(r) ((r)->regs[29]) -extern asmlinkage void syscall_trace_enter(struct pt_regs *regs); +extern asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall); extern asmlinkage void syscall_trace_leave(struct pt_regs *regs); extern void die(const char *, struct pt_regs *) __noreturn; @@ -68,4 +96,17 @@ static inline void die_if_kernel(const char *str, struct pt_regs *regs) (struct pt_regs *)((sp | (THREAD_SIZE - 1)) + 1 - 32) - 1; \ }) +/* Helpers for working with the user stack pointer */ + +static inline unsigned long user_stack_pointer(struct pt_regs *regs) +{ + return regs->regs[29]; +} + +static inline void user_stack_pointer_set(struct pt_regs *regs, + unsigned long val) +{ + regs->regs[29] = val; +} + #endif /* _ASM_PTRACE_H */ diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h index 54ea47da59a..0b8bd28a0df 100644 --- a/arch/mips/include/asm/r4kcache.h +++ b/arch/mips/include/asm/r4kcache.h @@ -15,17 +15,19 @@ #include <asm/asm.h> #include <asm/cacheops.h> #include <asm/cpu-features.h> +#include <asm/cpu-type.h> #include <asm/mipsmtregs.h> +#include <asm/uaccess.h> /* for segment_eq() */ /* * This macro return a properly sign-extended address suitable as base address * for indexed cache operations. Two issues here: * * - The MIPS32 and MIPS64 specs permit an implementation to directly derive - * the index bits from the virtual address. This breaks with tradition - * set by the R4000. To keep unpleasant surprises from happening we pick + * the index bits from the virtual address. This breaks with tradition + * set by the R4000. To keep unpleasant surprises from happening we pick * an address in KSEG0 / CKSEG0. - * - We need a properly sign extended address for 64-bit code. To get away + * - We need a properly sign extended address for 64-bit code. To get away * without ifdefs we let the compiler do it by a type cast. */ #define INDEX_BASE CKSEG0 @@ -34,18 +36,17 @@ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ - " .set mips3\n\t \n" \ + " .set arch=r4000 \n" \ " cache %0, %1 \n" \ " .set pop \n" \ : \ : "i" (op), "R" (*(unsigned char *)(addr))) #ifdef CONFIG_MIPS_MT + /* - * Temporary hacks for SMTC debug. Optionally force single-threaded - * execution during I-cache flushes. + * Optionally force single-threaded execution during I-cache flushes. */ - #define PROTECT_CACHE_FLUSHES 1 #ifdef PROTECT_CACHE_FLUSHES @@ -162,7 +163,15 @@ static inline void flush_scache_line_indexed(unsigned long addr) static inline void flush_icache_line(unsigned long addr) { __iflush_prologue - cache_op(Hit_Invalidate_I, addr); + switch (boot_cpu_type()) { + case CPU_LOONGSON2: + cache_op(Hit_Invalidate_I_Loongson2, addr); + break; + + default: + cache_op(Hit_Invalidate_I, addr); + break; + } __iflush_epilogue } @@ -194,7 +203,7 @@ static inline void flush_scache_line(unsigned long addr) __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ - " .set mips3 \n" \ + " .set arch=r4000 \n" \ "1: cache %0, (%1) \n" \ "2: .set pop \n" \ " .section __ex_table,\"a\" \n" \ @@ -203,12 +212,38 @@ static inline void flush_scache_line(unsigned long addr) : \ : "i" (op), "r" (addr)) +#define protected_cachee_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips0 \n" \ + " .set eva \n" \ + "1: cachee %0, (%1) \n" \ + "2: .set pop \n" \ + " .section __ex_table,\"a\" \n" \ + " "STR(PTR)" 1b, 2b \n" \ + " .previous" \ + : \ + : "i" (op), "r" (addr)) + /* * The next two are for badland addresses like signal trampolines. */ static inline void protected_flush_icache_line(unsigned long addr) { - protected_cache_op(Hit_Invalidate_I, addr); + switch (boot_cpu_type()) { + case CPU_LOONGSON2: + protected_cache_op(Hit_Invalidate_I_Loongson2, addr); + break; + + default: +#ifdef CONFIG_EVA + protected_cachee_op(Hit_Invalidate_I, addr); +#else + protected_cache_op(Hit_Invalidate_I, addr); +#endif + break; + } } /* @@ -339,15 +374,100 @@ static inline void invalidate_tcache_page(unsigned long addr) : "r" (base), \ "i" (op)); +/* + * Perform the cache operation specified by op using a user mode virtual + * address while in kernel mode. + */ +#define cache16_unroll32_user(base,op) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips0 \n" \ + " .set eva \n" \ + " cachee %1, 0x000(%0); cachee %1, 0x010(%0) \n" \ + " cachee %1, 0x020(%0); cachee %1, 0x030(%0) \n" \ + " cachee %1, 0x040(%0); cachee %1, 0x050(%0) \n" \ + " cachee %1, 0x060(%0); cachee %1, 0x070(%0) \n" \ + " cachee %1, 0x080(%0); cachee %1, 0x090(%0) \n" \ + " cachee %1, 0x0a0(%0); cachee %1, 0x0b0(%0) \n" \ + " cachee %1, 0x0c0(%0); cachee %1, 0x0d0(%0) \n" \ + " cachee %1, 0x0e0(%0); cachee %1, 0x0f0(%0) \n" \ + " cachee %1, 0x100(%0); cachee %1, 0x110(%0) \n" \ + " cachee %1, 0x120(%0); cachee %1, 0x130(%0) \n" \ + " cachee %1, 0x140(%0); cachee %1, 0x150(%0) \n" \ + " cachee %1, 0x160(%0); cachee %1, 0x170(%0) \n" \ + " cachee %1, 0x180(%0); cachee %1, 0x190(%0) \n" \ + " cachee %1, 0x1a0(%0); cachee %1, 0x1b0(%0) \n" \ + " cachee %1, 0x1c0(%0); cachee %1, 0x1d0(%0) \n" \ + " cachee %1, 0x1e0(%0); cachee %1, 0x1f0(%0) \n" \ + " .set pop \n" \ + : \ + : "r" (base), \ + "i" (op)); + +#define cache32_unroll32_user(base, op) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips0 \n" \ + " .set eva \n" \ + " cachee %1, 0x000(%0); cachee %1, 0x020(%0) \n" \ + " cachee %1, 0x040(%0); cachee %1, 0x060(%0) \n" \ + " cachee %1, 0x080(%0); cachee %1, 0x0a0(%0) \n" \ + " cachee %1, 0x0c0(%0); cachee %1, 0x0e0(%0) \n" \ + " cachee %1, 0x100(%0); cachee %1, 0x120(%0) \n" \ + " cachee %1, 0x140(%0); cachee %1, 0x160(%0) \n" \ + " cachee %1, 0x180(%0); cachee %1, 0x1a0(%0) \n" \ + " cachee %1, 0x1c0(%0); cachee %1, 0x1e0(%0) \n" \ + " cachee %1, 0x200(%0); cachee %1, 0x220(%0) \n" \ + " cachee %1, 0x240(%0); cachee %1, 0x260(%0) \n" \ + " cachee %1, 0x280(%0); cachee %1, 0x2a0(%0) \n" \ + " cachee %1, 0x2c0(%0); cachee %1, 0x2e0(%0) \n" \ + " cachee %1, 0x300(%0); cachee %1, 0x320(%0) \n" \ + " cachee %1, 0x340(%0); cachee %1, 0x360(%0) \n" \ + " cachee %1, 0x380(%0); cachee %1, 0x3a0(%0) \n" \ + " cachee %1, 0x3c0(%0); cachee %1, 0x3e0(%0) \n" \ + " .set pop \n" \ + : \ + : "r" (base), \ + "i" (op)); + +#define cache64_unroll32_user(base, op) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips0 \n" \ + " .set eva \n" \ + " cachee %1, 0x000(%0); cachee %1, 0x040(%0) \n" \ + " cachee %1, 0x080(%0); cachee %1, 0x0c0(%0) \n" \ + " cachee %1, 0x100(%0); cachee %1, 0x140(%0) \n" \ + " cachee %1, 0x180(%0); cachee %1, 0x1c0(%0) \n" \ + " cachee %1, 0x200(%0); cachee %1, 0x240(%0) \n" \ + " cachee %1, 0x280(%0); cachee %1, 0x2c0(%0) \n" \ + " cachee %1, 0x300(%0); cachee %1, 0x340(%0) \n" \ + " cachee %1, 0x380(%0); cachee %1, 0x3c0(%0) \n" \ + " cachee %1, 0x400(%0); cachee %1, 0x440(%0) \n" \ + " cachee %1, 0x480(%0); cachee %1, 0x4c0(%0) \n" \ + " cachee %1, 0x500(%0); cachee %1, 0x540(%0) \n" \ + " cachee %1, 0x580(%0); cachee %1, 0x5c0(%0) \n" \ + " cachee %1, 0x600(%0); cachee %1, 0x640(%0) \n" \ + " cachee %1, 0x680(%0); cachee %1, 0x6c0(%0) \n" \ + " cachee %1, 0x700(%0); cachee %1, 0x740(%0) \n" \ + " cachee %1, 0x780(%0); cachee %1, 0x7c0(%0) \n" \ + " .set pop \n" \ + : \ + : "r" (base), \ + "i" (op)); + /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */ -#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \ -static inline void blast_##pfx##cache##lsize(void) \ +#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \ +static inline void extra##blast_##pfx##cache##lsize(void) \ { \ unsigned long start = INDEX_BASE; \ unsigned long end = start + current_cpu_data.desc.waysize; \ unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ unsigned long ws_end = current_cpu_data.desc.ways << \ - current_cpu_data.desc.waybit; \ + current_cpu_data.desc.waybit; \ unsigned long ws, addr; \ \ __##pfx##flush_prologue \ @@ -359,7 +479,7 @@ static inline void blast_##pfx##cache##lsize(void) \ __##pfx##flush_epilogue \ } \ \ -static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \ +static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \ { \ unsigned long start = page; \ unsigned long end = page + PAGE_SIZE; \ @@ -374,14 +494,14 @@ static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \ __##pfx##flush_epilogue \ } \ \ -static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ +static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ { \ unsigned long indexmask = current_cpu_data.desc.waysize - 1; \ unsigned long start = INDEX_BASE + (page & indexmask); \ unsigned long end = start + PAGE_SIZE; \ unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ unsigned long ws_end = current_cpu_data.desc.ways << \ - current_cpu_data.desc.waybit; \ + current_cpu_data.desc.waybit; \ unsigned long ws, addr; \ \ __##pfx##flush_prologue \ @@ -393,27 +513,56 @@ static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) __##pfx##flush_epilogue \ } -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16) -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16) -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16) -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32) -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32) -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64) -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64) -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) - -__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16) -__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32) -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16) -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32) -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64) -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128) +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, ) +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, ) +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, ) +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, ) +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, ) +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_) +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, ) +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, ) +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, ) +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, ) +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, ) +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, ) +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, ) + +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, ) +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, ) +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, ) +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, ) +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, ) +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, ) + +#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \ +static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \ +{ \ + unsigned long start = page; \ + unsigned long end = page + PAGE_SIZE; \ + \ + __##pfx##flush_prologue \ + \ + do { \ + cache##lsize##_unroll32_user(start, hitop); \ + start += lsize * 32; \ + } while (start < end); \ + \ + __##pfx##flush_epilogue \ +} + +__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, + 16) +__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16) +__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, + 32) +__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) +__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, + 64) +__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) /* build blast_xxx_range, protected_blast_xxx_range */ -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \ -static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ +#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \ +static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \ unsigned long end) \ { \ unsigned long lsize = cpu_##desc##_line_size(); \ @@ -432,13 +581,54 @@ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ __##pfx##flush_epilogue \ } -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_) -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_) -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_) -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, ) -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, ) +#ifndef CONFIG_EVA + +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, ) +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) + +#else + +#define __BUILD_PROT_BLAST_CACHE_RANGE(pfx, desc, hitop) \ +static inline void protected_blast_##pfx##cache##_range(unsigned long start,\ + unsigned long end) \ +{ \ + unsigned long lsize = cpu_##desc##_line_size(); \ + unsigned long addr = start & ~(lsize - 1); \ + unsigned long aend = (end - 1) & ~(lsize - 1); \ + \ + __##pfx##flush_prologue \ + \ + if (segment_eq(get_fs(), USER_DS)) { \ + while (1) { \ + protected_cachee_op(hitop, addr); \ + if (addr == aend) \ + break; \ + addr += lsize; \ + } \ + } else { \ + while (1) { \ + protected_cache_op(hitop, addr); \ + if (addr == aend) \ + break; \ + addr += lsize; \ + } \ + \ + } \ + __##pfx##flush_epilogue \ +} + +__BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D) +__BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I) + +#endif +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, ) +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \ + protected_, loongson2_) +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , ) +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , ) +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , ) /* blast_inv_dcache_range */ -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, ) -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, ) +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , ) +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , ) #endif /* _ASM_R4KCACHE_H */ diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h index 785a5189b37..3c687df1d51 100644 --- a/arch/mips/include/asm/regdef.h +++ b/arch/mips/include/asm/regdef.h @@ -19,44 +19,44 @@ /* * Symbolic register names for 32 bit ABI */ -#define zero $0 /* wired zero */ -#define AT $1 /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 +#define zero $0 /* wired zero */ +#define AT $1 /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* caller saved */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 #define ta0 $12 -#define t5 $13 +#define t5 $13 #define ta1 $13 -#define t6 $14 +#define t6 $14 #define ta2 $14 -#define t7 $15 +#define t7 $15 #define ta3 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel scratch */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel scratch */ +#define k1 $27 +#define gp $28 /* global pointer */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ #define s8 $30 /* same like fp! */ -#define ra $31 /* return address */ +#define ra $31 /* return address */ #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ diff --git a/arch/mips/include/asm/rm9k-ocd.h b/arch/mips/include/asm/rm9k-ocd.h deleted file mode 100644 index b0b80d9ecf9..00000000000 --- a/arch/mips/include/asm/rm9k-ocd.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2004 by Basler Vision Technologies AG - * Author: Thomas Koeller <thomas.koeller@baslerweb.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#if !defined(_ASM_RM9K_OCD_H) -#define _ASM_RM9K_OCD_H - -#include <linux/types.h> -#include <linux/spinlock.h> -#include <asm/io.h> - -extern volatile void __iomem * const ocd_base; -extern volatile void __iomem * const titan_base; - -#define ocd_addr(__x__) (ocd_base + (__x__)) -#define titan_addr(__x__) (titan_base + (__x__)) -#define scram_addr(__x__) (scram_base + (__x__)) - -/* OCD register access */ -#define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__)) -#define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__)) -#define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__)) -#define ocd_writel(__val__, __offs__) \ - __raw_writel((__val__), ocd_addr(__offs__)) -#define ocd_writew(__val__, __offs__) \ - __raw_writew((__val__), ocd_addr(__offs__)) -#define ocd_writeb(__val__, __offs__) \ - __raw_writeb((__val__), ocd_addr(__offs__)) - -/* TITAN register access - 32 bit-wide only */ -#define titan_readl(__offs__) __raw_readl(titan_addr(__offs__)) -#define titan_writel(__val__, __offs__) \ - __raw_writel((__val__), titan_addr(__offs__)) - -/* Protect access to shared TITAN registers */ -extern spinlock_t titan_lock; -extern int titan_irqflags; -#define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags) -#define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags) - -#endif /* !defined(_ASM_RM9K_OCD_H) */ diff --git a/arch/mips/include/asm/rtlx.h b/arch/mips/include/asm/rtlx.h index 4ca3063ed2c..c1020654876 100644 --- a/arch/mips/include/asm/rtlx.h +++ b/arch/mips/include/asm/rtlx.h @@ -1,13 +1,18 @@ /* - * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * + * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2013 Imagination Technologies Ltd. */ - #ifndef __ASM_RTLX_H_ #define __ASM_RTLX_H_ #include <irq.h> +#define RTLX_MODULE_NAME "rtlx" + #define LX_NODE_BASE 10 #define MIPS_CPU_RTLX_IRQ 0 @@ -15,18 +20,31 @@ #define RTLX_VERSION 2 #define RTLX_xID 0x12345600 #define RTLX_ID (RTLX_xID | RTLX_VERSION) +#define RTLX_BUFFER_SIZE 2048 #define RTLX_CHANNELS 8 #define RTLX_CHANNEL_STDIO 0 #define RTLX_CHANNEL_DBG 1 #define RTLX_CHANNEL_SYSIO 2 -extern int rtlx_open(int index, int can_sleep); -extern int rtlx_release(int index); -extern ssize_t rtlx_read(int index, void __user *buff, size_t count); -extern ssize_t rtlx_write(int index, const void __user *buffer, size_t count); -extern unsigned int rtlx_read_poll(int index, int can_sleep); -extern unsigned int rtlx_write_poll(int index); +void rtlx_starting(int vpe); +void rtlx_stopping(int vpe); + +int rtlx_open(int index, int can_sleep); +int rtlx_release(int index); +ssize_t rtlx_read(int index, void __user *buff, size_t count); +ssize_t rtlx_write(int index, const void __user *buffer, size_t count); +unsigned int rtlx_read_poll(int index, int can_sleep); +unsigned int rtlx_write_poll(int index); + +int __init rtlx_module_init(void); +void __exit rtlx_module_exit(void); + +void _interrupt_sp(void); + +extern struct vpe_notifications rtlx_notify; +extern const struct file_operations rtlx_fops; +extern void (*aprp_hook)(void); enum rtlx_state { RTLX_STATE_UNUSED = 0, @@ -35,10 +53,15 @@ enum rtlx_state { RTLX_STATE_OPENED }; -#define RTLX_BUFFER_SIZE 2048 +extern struct chan_waitqueues { + wait_queue_head_t rt_queue; + wait_queue_head_t lx_queue; + atomic_t in_open; + struct mutex mutex; +} channel_wqs[RTLX_CHANNELS]; /* each channel supports read and write. - linux (vpe0) reads lx_buffer and writes rt_buffer + linux (vpe0) reads lx_buffer and writes rt_buffer SP (vpe1) reads rt_buffer and writes lx_buffer */ struct rtlx_channel { @@ -55,11 +78,11 @@ struct rtlx_channel { char *lx_buffer; }; -struct rtlx_info { +extern struct rtlx_info { unsigned long id; enum rtlx_state state; + int ap_int_pending; /* Status of 0 or 1 for CONFIG_MIPS_CMP only */ struct rtlx_channel channel[RTLX_CHANNELS]; -}; - +} *rtlx; #endif /* __ASM_RTLX_H_ */ diff --git a/arch/mips/include/asm/scatterlist.h b/arch/mips/include/asm/scatterlist.h deleted file mode 100644 index 7ee0e646d82..00000000000 --- a/arch/mips/include/asm/scatterlist.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_SCATTERLIST_H -#define __ASM_SCATTERLIST_H - -#include <asm-generic/scatterlist.h> - -#endif /* __ASM_SCATTERLIST_H */ diff --git a/arch/mips/include/asm/seccomp.h b/arch/mips/include/asm/seccomp.h index ae6306ebdca..f29c75cf83c 100644 --- a/arch/mips/include/asm/seccomp.h +++ b/arch/mips/include/asm/seccomp.h @@ -10,7 +10,7 @@ /* * Kludge alert: * - * The generic seccomp code currently allows only a single compat ABI. Until + * The generic seccomp code currently allows only a single compat ABI. Until * this is fixed we priorize O32 as the compat ABI over N32. */ #ifdef CONFIG_MIPS32_O32 diff --git a/arch/mips/include/asm/sections.h b/arch/mips/include/asm/sections.h deleted file mode 100644 index b7e37262c24..00000000000 --- a/arch/mips/include/asm/sections.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_SECTIONS_H -#define _ASM_SECTIONS_H - -#include <asm-generic/sections.h> - -#endif /* _ASM_SECTIONS_H */ diff --git a/arch/mips/include/asm/segment.h b/arch/mips/include/asm/segment.h deleted file mode 100644 index 92ac001fc48..00000000000 --- a/arch/mips/include/asm/segment.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_SEGMENT_H -#define _ASM_SEGMENT_H - -/* Only here because we have some old header files that expect it.. */ - -#endif /* _ASM_SEGMENT_H */ diff --git a/arch/mips/include/asm/serial.h b/arch/mips/include/asm/serial.h deleted file mode 100644 index a0cb0caff15..00000000000 --- a/arch/mips/include/asm/serial.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/serial.h> diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h index e26589ef36e..d7bfdeba9e8 100644 --- a/arch/mips/include/asm/setup.h +++ b/arch/mips/include/asm/setup.h @@ -5,6 +5,14 @@ extern void setup_early_printk(void); +#ifdef CONFIG_EARLY_PRINTK_8250 +extern void setup_8250_early_printk_port(unsigned long base, + unsigned int reg_shift, unsigned int timeout); +#else +static inline void setup_8250_early_printk_port(unsigned long base, + unsigned int reg_shift, unsigned int timeout) {} +#endif + extern void set_handler(unsigned long offset, void *addr, unsigned long len); extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len); diff --git a/arch/mips/include/asm/sgi/gio.h b/arch/mips/include/asm/sgi/gio.h index 889cf028c95..24be2b425be 100644 --- a/arch/mips/include/asm/sgi/gio.h +++ b/arch/mips/include/asm/sgi/gio.h @@ -18,18 +18,18 @@ * three physical connectors, but only two slots, GFX and EXP0. * * There is 10MB of GIO address space for GIO64 slot devices - * slot# slot type address range size + * slot# slot type address range size * ----- --------- ----------------------- ----- - * 0 GFX 0x1f000000 - 0x1f3fffff 4MB - * 1 EXP0 0x1f400000 - 0x1f5fffff 2MB - * 2 EXP1 0x1f600000 - 0x1f9fffff 4MB + * 0 GFX 0x1f000000 - 0x1f3fffff 4MB + * 1 EXP0 0x1f400000 - 0x1f5fffff 2MB + * 2 EXP1 0x1f600000 - 0x1f9fffff 4MB * * There are un-slotted devices, HPC, I/O and misc devices, which are grouped * into the HPC address space. - * - MISC 0x1fb00000 - 0x1fbfffff 1MB + * - MISC 0x1fb00000 - 0x1fbfffff 1MB * * Following space is reserved and unused - * - RESERVED 0x18000000 - 0x1effffff 112MB + * - RESERVED 0x18000000 - 0x1effffff 112MB * * GIO bus IDs * @@ -39,10 +39,10 @@ * the slot undefined. * * 32-bit IDs are divided into - * bits 0:6 the product ID; ranges from 0x00 to 0x7F. + * bits 0:6 the product ID; ranges from 0x00 to 0x7F. * bit 7 0=GIO Product ID is 8 bits wide * 1=GIO Product ID is 32 bits wide. - * bits 8:15 manufacturer version for the product. + * bits 8:15 manufacturer version for the product. * bit 16 0=GIO32 and GIO32-bis, 1=GIO64. * bit 17 0=no ROM present * 1=ROM present on this board AND next three words diff --git a/arch/mips/include/asm/sgi/hpc3.h b/arch/mips/include/asm/sgi/hpc3.h index c4729f53191..59920b34594 100644 --- a/arch/mips/include/asm/sgi/hpc3.h +++ b/arch/mips/include/asm/sgi/hpc3.h @@ -65,39 +65,39 @@ struct hpc3_scsiregs { u32 _unused0[0x1000/4 - 2]; /* padding */ volatile u32 bcd; /* byte count info */ #define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */ -#define HPC3_SBCD_XIE 0x00004000 /* Send IRQ when done with cur buf */ -#define HPC3_SBCD_EOX 0x00008000 /* Indicates this is last buf in chain */ +#define HPC3_SBCD_XIE 0x00004000 /* Send IRQ when done with cur buf */ +#define HPC3_SBCD_EOX 0x00008000 /* Indicates this is last buf in chain */ volatile u32 ctrl; /* control register */ -#define HPC3_SCTRL_IRQ 0x01 /* IRQ asserted, either dma done or parity */ +#define HPC3_SCTRL_IRQ 0x01 /* IRQ asserted, either dma done or parity */ #define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */ -#define HPC3_SCTRL_DIR 0x04 /* DMA direction, 1=dev2mem 0=mem2dev */ +#define HPC3_SCTRL_DIR 0x04 /* DMA direction, 1=dev2mem 0=mem2dev */ #define HPC3_SCTRL_FLUSH 0x08 /* Tells HPC3 to flush scsi fifos */ #define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */ #define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */ #define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */ -#define HPC3_SCTRL_PERR 0x80 /* Bad parity on HPC3 iface to scsi controller */ +#define HPC3_SCTRL_PERR 0x80 /* Bad parity on HPC3 iface to scsi controller */ volatile u32 gfptr; /* current GIO fifo ptr */ volatile u32 dfptr; /* current device fifo ptr */ volatile u32 dconfig; /* DMA configuration register */ #define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */ -#define HPC3_SDCFG_D1 0x00006 /* Cycles to spend in D1 state */ -#define HPC3_SDCFG_D2 0x00038 /* Cycles to spend in D2 state */ -#define HPC3_SDCFG_D3 0x001c0 /* Cycles to spend in D3 state */ +#define HPC3_SDCFG_D1 0x00006 /* Cycles to spend in D1 state */ +#define HPC3_SDCFG_D2 0x00038 /* Cycles to spend in D2 state */ +#define HPC3_SDCFG_D3 0x001c0 /* Cycles to spend in D3 state */ #define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */ -#define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */ +#define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */ #define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */ #define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */ #define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */ #define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */ volatile u32 pconfig; /* PIO configuration register */ -#define HPC3_SPCFG_P3 0x0003 /* Cycles to spend in P3 state */ -#define HPC3_SPCFG_P2W 0x001c /* Cycles to spend in P2 state for writes */ -#define HPC3_SPCFG_P2R 0x01e0 /* Cycles to spend in P2 state for reads */ -#define HPC3_SPCFG_P1 0x0e00 /* Cycles to spend in P1 state */ -#define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */ +#define HPC3_SPCFG_P3 0x0003 /* Cycles to spend in P3 state */ +#define HPC3_SPCFG_P2W 0x001c /* Cycles to spend in P2 state for writes */ +#define HPC3_SPCFG_P2R 0x01e0 /* Cycles to spend in P2 state for reads */ +#define HPC3_SPCFG_P1 0x0e00 /* Cycles to spend in P1 state */ +#define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */ #define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */ #define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */ #define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */ @@ -108,13 +108,13 @@ struct hpc3_scsiregs { /* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */ struct hpc3_ethregs { /* Receiver registers. */ - volatile u32 rx_cbptr; /* current dma buffer ptr, diagnostic use only */ - volatile u32 rx_ndptr; /* next dma descriptor ptr */ + volatile u32 rx_cbptr; /* current dma buffer ptr, diagnostic use only */ + volatile u32 rx_ndptr; /* next dma descriptor ptr */ u32 _unused0[0x1000/4 - 2]; /* padding */ volatile u32 rx_bcd; /* byte count info */ #define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */ -#define HPC3_ERXBCD_XIE 0x20000000 /* HPC3 interrupts cpu at end of this buf */ -#define HPC3_ERXBCD_EOX 0x80000000 /* flags this as end of descriptor chain */ +#define HPC3_ERXBCD_XIE 0x20000000 /* HPC3 interrupts cpu at end of this buf */ +#define HPC3_ERXBCD_EOX 0x80000000 /* flags this as end of descriptor chain */ volatile u32 rx_ctrl; /* control register */ #define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */ @@ -131,23 +131,23 @@ struct hpc3_ethregs { volatile u32 reset; /* reset register */ #define HPC3_ERST_CRESET 0x1 /* Reset dma channel and external controller */ #define HPC3_ERST_CLRIRQ 0x2 /* Clear channel interrupt */ -#define HPC3_ERST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */ +#define HPC3_ERST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */ - volatile u32 dconfig; /* DMA configuration register */ -#define HPC3_EDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */ -#define HPC3_EDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */ -#define HPC3_EDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */ + volatile u32 dconfig; /* DMA configuration register */ +#define HPC3_EDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */ +#define HPC3_EDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */ +#define HPC3_EDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */ #define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */ #define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */ -#define HPC3_EDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */ -#define HPC3_EDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */ -#define HPC3_EDCFG_PTO 0x30000 /* Programmed timeout value for above two */ +#define HPC3_EDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */ +#define HPC3_EDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */ +#define HPC3_EDCFG_PTO 0x30000 /* Programmed timeout value for above two */ - volatile u32 pconfig; /* PIO configuration register */ -#define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */ -#define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */ -#define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */ -#define HPC3_EPCFG_TST 0x1000 /* Diagnistic ram test feature bit */ + volatile u32 pconfig; /* PIO configuration register */ +#define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */ +#define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */ +#define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */ +#define HPC3_EPCFG_TST 0x1000 /* Diagnistic ram test feature bit */ u32 _unused2[0x1000/4 - 8]; /* padding */ @@ -158,9 +158,9 @@ struct hpc3_ethregs { volatile u32 tx_bcd; /* byte count info */ #define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */ #define HPC3_ETXBCD_ESAMP 0x10000000 /* if set, too late to add descriptor */ -#define HPC3_ETXBCD_XIE 0x20000000 /* Interrupt cpu at end of cur desc */ -#define HPC3_ETXBCD_EOP 0x40000000 /* Last byte of cur buf is end of packet */ -#define HPC3_ETXBCD_EOX 0x80000000 /* This buf is the end of desc chain */ +#define HPC3_ETXBCD_XIE 0x20000000 /* Interrupt cpu at end of cur desc */ +#define HPC3_ETXBCD_EOP 0x40000000 /* Last byte of cur buf is end of packet */ +#define HPC3_ETXBCD_EOX 0x80000000 /* This buf is the end of desc chain */ volatile u32 tx_ctrl; /* control register */ #define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */ @@ -215,10 +215,10 @@ struct hpc3_regs { volatile u32 istat1; /* Irq status, only bits <9:5> reliable. */ volatile u32 bestat; /* Bus error interrupt status reg. */ -#define HPC3_BESTAT_BLMASK 0x000ff /* Bus lane where bad parity occurred */ -#define HPC3_BESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */ +#define HPC3_BESTAT_BLMASK 0x000ff /* Bus lane where bad parity occurred */ +#define HPC3_BESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */ #define HPC3_BESTAT_PIDSHIFT 9 -#define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */ +#define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */ u32 _unused1[0x14000/4 - 5]; /* padding */ @@ -259,7 +259,7 @@ struct hpc3_regs { #define HPC3_DMACFG_RTIME 0x00200000 /* 5 bit burst count for DMA device */ #define HPC3_DMACFG_BURST_MASK 0x07c00000 -#define HPC3_DMACFG_BURST_SHIFT 22 +#define HPC3_DMACFG_BURST_SHIFT 22 /* Use live pbus_dreq unsynchronized signal */ #define HPC3_DMACFG_DRQLIVE 0x08000000 volatile u32 pbus_piocfg[16][64]; @@ -288,20 +288,20 @@ struct hpc3_regs { /* PBUS PROM control regs. */ volatile u32 pbus_promwe; /* PROM write enable register */ -#define HPC3_PROM_WENAB 0x1 /* Enable writes to the PROM */ +#define HPC3_PROM_WENAB 0x1 /* Enable writes to the PROM */ u32 _unused5[0x0800/4 - 1]; volatile u32 pbus_promswap; /* Chip select swap reg */ #define HPC3_PROM_SWAP 0x1 /* invert GIO addr bit to select prom0 or prom1 */ u32 _unused6[0x0800/4 - 1]; - volatile u32 pbus_gout; /* PROM general purpose output reg */ + volatile u32 pbus_gout; /* PROM general purpose output reg */ #define HPC3_PROM_STAT 0x1 /* General purpose status bit in gout */ u32 _unused7[0x1000/4 - 1]; volatile u32 rtcregs[14]; /* Dallas clock registers */ u32 _unused8[50]; - volatile u32 bbram[8192-50-14]; /* Battery backed ram */ + volatile u32 bbram[8192-50-14]; /* Battery backed ram */ }; /* diff --git a/arch/mips/include/asm/sgi/ioc.h b/arch/mips/include/asm/sgi/ioc.h index 380347b648e..53c6b1ca686 100644 --- a/arch/mips/include/asm/sgi/ioc.h +++ b/arch/mips/include/asm/sgi/ioc.h @@ -138,7 +138,7 @@ struct sgioc_regs { u8 _sysid[3]; volatile u8 sysid; #define SGIOC_SYSID_FULLHOUSE 0x01 -#define SGIOC_SYSID_BOARDREV(x) (((x) & 0x1e) >> 1) +#define SGIOC_SYSID_BOARDREV(x) (((x) & 0x1e) >> 1) #define SGIOC_SYSID_CHIPREV(x) (((x) & 0xe0) >> 5) u32 _unused2; u8 _read[3]; @@ -150,7 +150,7 @@ struct sgioc_regs { #define SGIOC_DMASEL_ISDNB 0x01 /* enable isdn B */ #define SGIOC_DMASEL_ISDNA 0x02 /* enable isdn A */ #define SGIOC_DMASEL_PPORT 0x04 /* use parallel DMA */ -#define SGIOC_DMASEL_SCLK667MHZ 0x10 /* use 6.67MHZ serial clock */ +#define SGIOC_DMASEL_SCLK667MHZ 0x10 /* use 6.67MHZ serial clock */ #define SGIOC_DMASEL_SCLKEXT 0x20 /* use external serial clock */ u32 _unused4; u8 _reset[3]; diff --git a/arch/mips/include/asm/sgi/ip22.h b/arch/mips/include/asm/sgi/ip22.h index c0501f91719..87ec9eaa04e 100644 --- a/arch/mips/include/asm/sgi/ip22.h +++ b/arch/mips/include/asm/sgi/ip22.h @@ -38,8 +38,8 @@ #define SGI_SOFT_0_IRQ SGINT_CPU + 0 #define SGI_SOFT_1_IRQ SGINT_CPU + 1 -#define SGI_LOCAL_0_IRQ SGINT_CPU + 2 -#define SGI_LOCAL_1_IRQ SGINT_CPU + 3 +#define SGI_LOCAL_0_IRQ SGINT_CPU + 2 +#define SGI_LOCAL_1_IRQ SGINT_CPU + 3 #define SGI_8254_0_IRQ SGINT_CPU + 4 #define SGI_8254_1_IRQ SGINT_CPU + 5 #define SGI_BUSERR_IRQ SGINT_CPU + 6 @@ -51,7 +51,7 @@ #define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */ #define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */ #define SGI_MCDMA_IRQ SGINT_LOCAL0 + 4 /* MC DMA done */ -#define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5 /* Parallel port */ +#define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5 /* Parallel port */ #define SGI_GIO_1_IRQ SGINT_LOCAL0 + 6 /* GE / GIO-1 / 2nd-HPC */ #define SGI_MAP_0_IRQ SGINT_LOCAL0 + 7 /* Mappable interrupt 0 */ @@ -69,6 +69,8 @@ #define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */ #define SGI_KEYBD_IRQ SGINT_LOCAL2 + 4 /* keyboard */ #define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */ +#define SGI_GIOEXP0_IRQ (SGINT_LOCAL2 + 6) /* Indy GIO EXP0 */ +#define SGI_GIOEXP1_IRQ (SGINT_LOCAL2 + 7) /* Indy GIO EXP1 */ #define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE) diff --git a/arch/mips/include/asm/sgi/mc.h b/arch/mips/include/asm/sgi/mc.h index 1576c2394de..3a070cec97e 100644 --- a/arch/mips/include/asm/sgi/mc.h +++ b/arch/mips/include/asm/sgi/mc.h @@ -29,10 +29,10 @@ struct sgimc_regs { #define SGIMC_CCTRL0_IENAB 0x00002000 /* Allow interrupts from MC */ #define SGIMC_CCTRL0_ESNOOP 0x00004000 /* Snooping I/O enable */ #define SGIMC_CCTRL0_EPROMWR 0x00008000 /* Prom writes from cpu enable */ -#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */ +#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */ #define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */ -#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */ -#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */ +#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */ +#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */ #define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */ #define SGIMC_CCTRL0_GIOBTOB 0x08000000 /* Allow GIO back to back writes */ u32 _unused1; @@ -40,13 +40,13 @@ struct sgimc_regs { #define SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */ #define SGIMC_CCTRL1_FIXEDEHPC 0x00001000 /* Fixed HPC endianness */ #define SGIMC_CCTRL1_LITTLEHPC 0x00002000 /* Little endian HPC */ -#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */ -#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */ -#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */ -#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */ +#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */ +#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */ +#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */ +#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */ u32 _unused2; - volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */ + volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */ u32 _unused3; volatile u32 systemid; /* MC system ID register, readonly */ @@ -81,11 +81,11 @@ struct sgimc_regs { #define SGIMC_GIOPAR_RTIMEGFX 0x00000040 /* GFX device has realtime attr */ #define SGIMC_GIOPAR_RTIMEEXP0 0x00000080 /* EXP(slot0) has realtime attr */ #define SGIMC_GIOPAR_RTIMEEXP1 0x00000100 /* EXP(slot1) has realtime attr */ -#define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */ +#define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */ #define SGIMC_GIOPAR_ONEBUS 0x00000400 /* Exists one GIO64 pipelined bus */ #define SGIMC_GIOPAR_MASTERGFX 0x00000800 /* GFX can act as a bus master */ -#define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */ -#define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */ +#define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */ +#define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */ #define SGIMC_GIOPAR_PLINEEXP0 0x00004000 /* EXP(slot0) has pipeline attr */ #define SGIMC_GIOPAR_PLINEEXP1 0x00008000 /* EXP(slot1) has pipeline attr */ @@ -107,9 +107,9 @@ struct sgimc_regs { #define SGIMC_MCONFIG_SBANKS 0x00004000 /* Number of subbanks */ u32 _unused13; - volatile u32 cmacc; /* Mem access config for CPU */ + volatile u32 cmacc; /* Mem access config for CPU */ u32 _unused14; - volatile u32 gmacc; /* Mem access config for GIO */ + volatile u32 gmacc; /* Mem access config for GIO */ /* This define applies to both cmacc and gmacc registers above. */ #define SGIMC_MACC_ALIASBIG 0x20000000 /* 512MB home for alias */ diff --git a/arch/mips/include/asm/sgi/pi1.h b/arch/mips/include/asm/sgi/pi1.h index c9506915dc5..96b1a0771ec 100644 --- a/arch/mips/include/asm/sgi/pi1.h +++ b/arch/mips/include/asm/sgi/pi1.h @@ -28,16 +28,16 @@ struct pi1_regs { #define PI1_STAT_BUSY 0x80 u8 _dmactrl[3]; volatile u8 dmactrl; -#define PI1_DMACTRL_FIFO_EMPTY 0x01 /* fifo empty R/O */ -#define PI1_DMACTRL_ABORT 0x02 /* reset DMA and internal fifo W/O */ -#define PI1_DMACTRL_STDMODE 0x00 /* bits 2-3 */ -#define PI1_DMACTRL_SGIMODE 0x04 /* bits 2-3 */ -#define PI1_DMACTRL_RICOHMODE 0x08 /* bits 2-3 */ -#define PI1_DMACTRL_HPMODE 0x0c /* bits 2-3 */ -#define PI1_DMACTRL_BLKMODE 0x10 /* block mode */ -#define PI1_DMACTRL_FIFO_CLEAR 0x20 /* clear fifo W/O */ -#define PI1_DMACTRL_READ 0x40 /* read */ -#define PI1_DMACTRL_RUN 0x80 /* pedal to the metal */ +#define PI1_DMACTRL_FIFO_EMPTY 0x01 /* fifo empty R/O */ +#define PI1_DMACTRL_ABORT 0x02 /* reset DMA and internal fifo W/O */ +#define PI1_DMACTRL_STDMODE 0x00 /* bits 2-3 */ +#define PI1_DMACTRL_SGIMODE 0x04 /* bits 2-3 */ +#define PI1_DMACTRL_RICOHMODE 0x08 /* bits 2-3 */ +#define PI1_DMACTRL_HPMODE 0x0c /* bits 2-3 */ +#define PI1_DMACTRL_BLKMODE 0x10 /* block mode */ +#define PI1_DMACTRL_FIFO_CLEAR 0x20 /* clear fifo W/O */ +#define PI1_DMACTRL_READ 0x40 /* read */ +#define PI1_DMACTRL_RUN 0x80 /* pedal to the metal */ u8 _intstat[3]; volatile u8 intstat; #define PI1_INTSTAT_ACK 0x04 diff --git a/arch/mips/include/asm/sgialib.h b/arch/mips/include/asm/sgialib.h index f5811576945..753275accd1 100644 --- a/arch/mips/include/asm/sgialib.h +++ b/arch/mips/include/asm/sgialib.h @@ -37,7 +37,7 @@ extern char prom_getchar(void); * in chain is CURR is NULL. */ extern struct linux_mdesc *prom_getmdesc(struct linux_mdesc *curr); -#define PROM_NULL_MDESC ((struct linux_mdesc *) 0) +#define PROM_NULL_MDESC ((struct linux_mdesc *) 0) /* Called by prom_init to setup the physical memory pmemblock * array. diff --git a/arch/mips/include/asm/sgiarcs.h b/arch/mips/include/asm/sgiarcs.h index 3dce7c788b3..26ddfff28c8 100644 --- a/arch/mips/include/asm/sgiarcs.h +++ b/arch/mips/include/asm/sgiarcs.h @@ -16,33 +16,33 @@ #include <asm/fw/arc/types.h> /* Various ARCS error codes. */ -#define PROM_ESUCCESS 0x00 -#define PROM_E2BIG 0x01 -#define PROM_EACCESS 0x02 -#define PROM_EAGAIN 0x03 -#define PROM_EBADF 0x04 -#define PROM_EBUSY 0x05 -#define PROM_EFAULT 0x06 -#define PROM_EINVAL 0x07 -#define PROM_EIO 0x08 -#define PROM_EISDIR 0x09 -#define PROM_EMFILE 0x0a -#define PROM_EMLINK 0x0b -#define PROM_ENAMETOOLONG 0x0c -#define PROM_ENODEV 0x0d -#define PROM_ENOENT 0x0e -#define PROM_ENOEXEC 0x0f -#define PROM_ENOMEM 0x10 -#define PROM_ENOSPC 0x11 -#define PROM_ENOTDIR 0x12 -#define PROM_ENOTTY 0x13 -#define PROM_ENXIO 0x14 -#define PROM_EROFS 0x15 +#define PROM_ESUCCESS 0x00 +#define PROM_E2BIG 0x01 +#define PROM_EACCESS 0x02 +#define PROM_EAGAIN 0x03 +#define PROM_EBADF 0x04 +#define PROM_EBUSY 0x05 +#define PROM_EFAULT 0x06 +#define PROM_EINVAL 0x07 +#define PROM_EIO 0x08 +#define PROM_EISDIR 0x09 +#define PROM_EMFILE 0x0a +#define PROM_EMLINK 0x0b +#define PROM_ENAMETOOLONG 0x0c +#define PROM_ENODEV 0x0d +#define PROM_ENOENT 0x0e +#define PROM_ENOEXEC 0x0f +#define PROM_ENOMEM 0x10 +#define PROM_ENOSPC 0x11 +#define PROM_ENOTDIR 0x12 +#define PROM_ENOTTY 0x13 +#define PROM_ENXIO 0x14 +#define PROM_EROFS 0x15 /* SGI ARCS specific errno's. */ -#define PROM_EADDRNOTAVAIL 0x1f -#define PROM_ETIMEDOUT 0x20 -#define PROM_ECONNABORTED 0x21 -#define PROM_ENOCONNECT 0x22 +#define PROM_EADDRNOTAVAIL 0x1f +#define PROM_ETIMEDOUT 0x20 +#define PROM_ECONNABORTED 0x21 +#define PROM_ENOCONNECT 0x22 /* Device classes, types, and identifiers for prom * device inventory queries. @@ -77,14 +77,14 @@ enum linux_identifier { /* A prom device tree component. */ struct linux_component { - enum linux_devclass class; /* node class */ - enum linux_devtypes type; /* node type */ - enum linux_identifier iflags; /* node flags */ - USHORT vers; /* node version */ - USHORT rev; /* node revision */ - ULONG key; /* completely magic */ - ULONG amask; /* XXX affinity mask??? */ - ULONG cdsize; /* size of configuration data */ + enum linux_devclass class; /* node class */ + enum linux_devtypes type; /* node type */ + enum linux_identifier iflags; /* node flags */ + USHORT vers; /* node version */ + USHORT rev; /* node revision */ + ULONG key; /* completely magic */ + ULONG amask; /* XXX affinity mask??? */ + ULONG cdsize; /* size of configuration data */ ULONG ilen; /* length of string identifier */ _PULONG iname; /* string identifier */ }; @@ -177,13 +177,13 @@ struct linux_finfo { struct linux_bigint end; struct linux_bigint cur; enum linux_devtypes dtype; - unsigned long namelen; - unsigned char attr; - char name[32]; /* XXX imperical, should be define */ + unsigned long namelen; + unsigned char attr; + char name[32]; /* XXX imperical, should be define */ }; /* This describes the vector containing function pointers to the ARC - firmware functions. */ + firmware functions. */ struct linux_romvec { LONG load; /* Load an executable image. */ LONG invoke; /* Invoke a standalong image. */ @@ -244,7 +244,7 @@ struct linux_romvec { */ typedef struct _SYSTEM_PARAMETER_BLOCK { ULONG magic; /* magic cookie */ -#define PROMBLOCK_MAGIC 0x53435241 +#define PROMBLOCK_MAGIC 0x53435241 ULONG len; /* length of parm block */ USHORT ver; /* ARCS firmware version */ @@ -294,16 +294,16 @@ struct linux_cdata { }; /* Common SGI ARCS firmware file descriptors. */ -#define SGIPROM_STDIN 0 -#define SGIPROM_STDOUT 1 +#define SGIPROM_STDIN 0 +#define SGIPROM_STDOUT 1 /* Common SGI ARCS firmware file types. */ -#define SGIPROM_ROFILE 0x01 /* read-only file */ -#define SGIPROM_HFILE 0x02 /* hidden file */ -#define SGIPROM_SFILE 0x04 /* System file */ -#define SGIPROM_AFILE 0x08 /* Archive file */ -#define SGIPROM_DFILE 0x10 /* Directory file */ -#define SGIPROM_DELFILE 0x20 /* Deleted file */ +#define SGIPROM_ROFILE 0x01 /* read-only file */ +#define SGIPROM_HFILE 0x02 /* hidden file */ +#define SGIPROM_SFILE 0x04 /* System file */ +#define SGIPROM_AFILE 0x08 /* Archive file */ +#define SGIPROM_DFILE 0x10 /* Directory file */ +#define SGIPROM_DELFILE 0x20 /* Deleted file */ /* SGI ARCS boot record information. */ struct sgi_partition { @@ -318,7 +318,7 @@ struct sgi_partition { unsigned char tsect0, tsect1, tsect2, tsect3; }; -#define SGIBBLOCK_MAGIC 0xaa55 +#define SGIBBLOCK_MAGIC 0xaa55 #define SGIBBLOCK_MAXPART 0x0004 struct sgi_bootblock { @@ -332,34 +332,34 @@ struct sgi_bparm_block { unsigned short bytes_sect; /* bytes per sector */ unsigned char sect_clust; /* sectors per cluster */ unsigned short sect_resv; /* reserved sectors */ - unsigned char nfats; /* # of allocation tables */ + unsigned char nfats; /* # of allocation tables */ unsigned short nroot_dirents; /* # of root directory entries */ unsigned short sect_volume; /* sectors in volume */ unsigned char media_type; /* media descriptor */ unsigned short sect_fat; /* sectors per allocation table */ unsigned short sect_track; /* sectors per track */ - unsigned short nheads; /* # of heads */ - unsigned short nhsects; /* # of hidden sectors */ + unsigned short nheads; /* # of heads */ + unsigned short nhsects; /* # of hidden sectors */ }; struct sgi_bsector { - unsigned char jmpinfo[3]; - unsigned char manuf_name[8]; + unsigned char jmpinfo[3]; + unsigned char manuf_name[8]; struct sgi_bparm_block info; }; /* Debugging block used with SGI symmon symbolic debugger. */ -#define SMB_DEBUG_MAGIC 0xfeeddead +#define SMB_DEBUG_MAGIC 0xfeeddead struct linux_smonblock { - unsigned long magic; - void (*handler)(void); /* Breakpoint routine. */ - unsigned long dtable_base; /* Base addr of dbg table. */ - int (*printf)(const char *fmt, ...); - unsigned long btable_base; /* Breakpoint table. */ - unsigned long mpflushreqs; /* SMP cache flush request list. */ - unsigned long ntab; /* Name table. */ - unsigned long stab; /* Symbol table. */ - int smax; /* Max # of symbols. */ + unsigned long magic; + void (*handler)(void); /* Breakpoint routine. */ + unsigned long dtable_base; /* Base addr of dbg table. */ + int (*printf)(const char *fmt, ...); + unsigned long btable_base; /* Breakpoint table. */ + unsigned long mpflushreqs; /* SMP cache flush request list. */ + unsigned long ntab; /* Name table. */ + unsigned long stab; /* Symbol table. */ + int smax; /* Max # of symbols. */ }; /* @@ -369,7 +369,7 @@ struct linux_smonblock { #if defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC32) #define __arc_clobbers \ - "$2", "$3" /* ... */, "$8", "$9", "$10", "$11", \ + "$2", "$3" /* ... */, "$8", "$9", "$10", "$11", \ "$12", "$13", "$14", "$15", "$16", "$24", "$25", "$31" #define ARC_CALL0(dest) \ @@ -447,7 +447,7 @@ struct linux_smonblock { "daddu\t$29, 32\n\t" \ "move\t%0, $2" \ : "=r" (__res), "=r" (__vec) \ - : "1" (__vec), "r" (__a1), "r" (__a2), "r" (__a3), \ + : "1" (__vec), "r" (__a1), "r" (__a2), "r" (__a3), \ "r" (__a4) \ : __arc_clobbers); \ __res; \ @@ -468,8 +468,8 @@ struct linux_smonblock { "daddu\t$29, 32\n\t" \ "move\t%0, $2" \ : "=r" (__res), "=r" (__vec) \ - : "1" (__vec), \ - "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4), \ + : "1" (__vec), \ + "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4), \ "r" (__a5) \ : __arc_clobbers); \ __res; \ @@ -512,7 +512,7 @@ struct linux_smonblock { long __a1 = (long) (a1); \ long __a2 = (long) (a2); \ long __a3 = (long) (a3); \ - long (*__vec)(long, long, long) = (void *) romvec->dest; \ + long (*__vec)(long, long, long) = (void *) romvec->dest; \ \ __res = __vec(__a1, __a2, __a3); \ __res; \ diff --git a/arch/mips/include/asm/shmparam.h b/arch/mips/include/asm/shmparam.h index 09290720751..324d04042bd 100644 --- a/arch/mips/include/asm/shmparam.h +++ b/arch/mips/include/asm/shmparam.h @@ -8,6 +8,6 @@ #define __ARCH_FORCE_SHMLBA 1 -#define SHMLBA 0x40000 /* attach addr a multiple of this */ +#define SHMLBA 0x40000 /* attach addr a multiple of this */ #endif /* _ASM_SHMPARAM_H */ diff --git a/arch/mips/include/asm/sibyte/bcm1480_int.h b/arch/mips/include/asm/sibyte/bcm1480_int.h index fffb224d229..6b82ed3c235 100644 --- a/arch/mips/include/asm/sibyte/bcm1480_int.h +++ b/arch/mips/include/asm/sibyte/bcm1480_int.h @@ -60,253 +60,253 @@ * Interrupt sources (Table 22) */ -#define K_BCM1480_INT_SOURCES 128 +#define K_BCM1480_INT_SOURCES 128 #define _BCM1480_INT_HIGH(k) (k) #define _BCM1480_INT_LOW(k) ((k)+64) -#define K_BCM1480_INT_ADDR_TRAP _BCM1480_INT_HIGH(1) -#define K_BCM1480_INT_GPIO_0 _BCM1480_INT_HIGH(4) -#define K_BCM1480_INT_GPIO_1 _BCM1480_INT_HIGH(5) -#define K_BCM1480_INT_GPIO_2 _BCM1480_INT_HIGH(6) -#define K_BCM1480_INT_GPIO_3 _BCM1480_INT_HIGH(7) -#define K_BCM1480_INT_PCI_INTA _BCM1480_INT_HIGH(8) -#define K_BCM1480_INT_PCI_INTB _BCM1480_INT_HIGH(9) -#define K_BCM1480_INT_PCI_INTC _BCM1480_INT_HIGH(10) -#define K_BCM1480_INT_PCI_INTD _BCM1480_INT_HIGH(11) -#define K_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_HIGH(12) -#define K_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_HIGH(13) -#define K_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_HIGH(14) -#define K_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_HIGH(15) -#define K_BCM1480_INT_TIMER_0 _BCM1480_INT_HIGH(20) -#define K_BCM1480_INT_TIMER_1 _BCM1480_INT_HIGH(21) -#define K_BCM1480_INT_TIMER_2 _BCM1480_INT_HIGH(22) -#define K_BCM1480_INT_TIMER_3 _BCM1480_INT_HIGH(23) -#define K_BCM1480_INT_DM_CH_0 _BCM1480_INT_HIGH(28) -#define K_BCM1480_INT_DM_CH_1 _BCM1480_INT_HIGH(29) -#define K_BCM1480_INT_DM_CH_2 _BCM1480_INT_HIGH(30) -#define K_BCM1480_INT_DM_CH_3 _BCM1480_INT_HIGH(31) -#define K_BCM1480_INT_MAC_0 _BCM1480_INT_HIGH(36) -#define K_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_HIGH(37) -#define K_BCM1480_INT_MAC_1 _BCM1480_INT_HIGH(38) -#define K_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_HIGH(39) -#define K_BCM1480_INT_MAC_2 _BCM1480_INT_HIGH(40) -#define K_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_HIGH(41) -#define K_BCM1480_INT_MAC_3 _BCM1480_INT_HIGH(42) -#define K_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_HIGH(43) -#define K_BCM1480_INT_PMI_LOW _BCM1480_INT_HIGH(52) -#define K_BCM1480_INT_PMI_HIGH _BCM1480_INT_HIGH(53) -#define K_BCM1480_INT_PMO_LOW _BCM1480_INT_HIGH(54) -#define K_BCM1480_INT_PMO_HIGH _BCM1480_INT_HIGH(55) -#define K_BCM1480_INT_MBOX_0_0 _BCM1480_INT_HIGH(56) -#define K_BCM1480_INT_MBOX_0_1 _BCM1480_INT_HIGH(57) -#define K_BCM1480_INT_MBOX_0_2 _BCM1480_INT_HIGH(58) -#define K_BCM1480_INT_MBOX_0_3 _BCM1480_INT_HIGH(59) -#define K_BCM1480_INT_MBOX_1_0 _BCM1480_INT_HIGH(60) -#define K_BCM1480_INT_MBOX_1_1 _BCM1480_INT_HIGH(61) -#define K_BCM1480_INT_MBOX_1_2 _BCM1480_INT_HIGH(62) -#define K_BCM1480_INT_MBOX_1_3 _BCM1480_INT_HIGH(63) +#define K_BCM1480_INT_ADDR_TRAP _BCM1480_INT_HIGH(1) +#define K_BCM1480_INT_GPIO_0 _BCM1480_INT_HIGH(4) +#define K_BCM1480_INT_GPIO_1 _BCM1480_INT_HIGH(5) +#define K_BCM1480_INT_GPIO_2 _BCM1480_INT_HIGH(6) +#define K_BCM1480_INT_GPIO_3 _BCM1480_INT_HIGH(7) +#define K_BCM1480_INT_PCI_INTA _BCM1480_INT_HIGH(8) +#define K_BCM1480_INT_PCI_INTB _BCM1480_INT_HIGH(9) +#define K_BCM1480_INT_PCI_INTC _BCM1480_INT_HIGH(10) +#define K_BCM1480_INT_PCI_INTD _BCM1480_INT_HIGH(11) +#define K_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_HIGH(12) +#define K_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_HIGH(13) +#define K_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_HIGH(14) +#define K_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_HIGH(15) +#define K_BCM1480_INT_TIMER_0 _BCM1480_INT_HIGH(20) +#define K_BCM1480_INT_TIMER_1 _BCM1480_INT_HIGH(21) +#define K_BCM1480_INT_TIMER_2 _BCM1480_INT_HIGH(22) +#define K_BCM1480_INT_TIMER_3 _BCM1480_INT_HIGH(23) +#define K_BCM1480_INT_DM_CH_0 _BCM1480_INT_HIGH(28) +#define K_BCM1480_INT_DM_CH_1 _BCM1480_INT_HIGH(29) +#define K_BCM1480_INT_DM_CH_2 _BCM1480_INT_HIGH(30) +#define K_BCM1480_INT_DM_CH_3 _BCM1480_INT_HIGH(31) +#define K_BCM1480_INT_MAC_0 _BCM1480_INT_HIGH(36) +#define K_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_HIGH(37) +#define K_BCM1480_INT_MAC_1 _BCM1480_INT_HIGH(38) +#define K_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_HIGH(39) +#define K_BCM1480_INT_MAC_2 _BCM1480_INT_HIGH(40) +#define K_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_HIGH(41) +#define K_BCM1480_INT_MAC_3 _BCM1480_INT_HIGH(42) +#define K_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_HIGH(43) +#define K_BCM1480_INT_PMI_LOW _BCM1480_INT_HIGH(52) +#define K_BCM1480_INT_PMI_HIGH _BCM1480_INT_HIGH(53) +#define K_BCM1480_INT_PMO_LOW _BCM1480_INT_HIGH(54) +#define K_BCM1480_INT_PMO_HIGH _BCM1480_INT_HIGH(55) +#define K_BCM1480_INT_MBOX_0_0 _BCM1480_INT_HIGH(56) +#define K_BCM1480_INT_MBOX_0_1 _BCM1480_INT_HIGH(57) +#define K_BCM1480_INT_MBOX_0_2 _BCM1480_INT_HIGH(58) +#define K_BCM1480_INT_MBOX_0_3 _BCM1480_INT_HIGH(59) +#define K_BCM1480_INT_MBOX_1_0 _BCM1480_INT_HIGH(60) +#define K_BCM1480_INT_MBOX_1_1 _BCM1480_INT_HIGH(61) +#define K_BCM1480_INT_MBOX_1_2 _BCM1480_INT_HIGH(62) +#define K_BCM1480_INT_MBOX_1_3 _BCM1480_INT_HIGH(63) -#define K_BCM1480_INT_BAD_ECC _BCM1480_INT_LOW(1) -#define K_BCM1480_INT_COR_ECC _BCM1480_INT_LOW(2) -#define K_BCM1480_INT_IO_BUS _BCM1480_INT_LOW(3) -#define K_BCM1480_INT_PERF_CNT _BCM1480_INT_LOW(4) -#define K_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_LOW(5) -#define K_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_LOW(6) -#define K_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_LOW(7) -#define K_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_LOW(8) -#define K_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_LOW(9) -#define K_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_LOW(10) -#define K_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_LOW(11) -#define K_BCM1480_INT_PCI_ERROR _BCM1480_INT_LOW(16) -#define K_BCM1480_INT_PCI_RESET _BCM1480_INT_LOW(17) -#define K_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_LOW(18) -#define K_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_LOW(19) -#define K_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_LOW(20) -#define K_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_LOW(21) -#define K_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_LOW(22) -#define K_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_LOW(23) -#define K_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_LOW(24) -#define K_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_LOW(25) -#define K_BCM1480_INT_LDT_SMI _BCM1480_INT_LOW(32) -#define K_BCM1480_INT_LDT_NMI _BCM1480_INT_LOW(33) -#define K_BCM1480_INT_LDT_INIT _BCM1480_INT_LOW(34) -#define K_BCM1480_INT_LDT_STARTUP _BCM1480_INT_LOW(35) -#define K_BCM1480_INT_LDT_EXT _BCM1480_INT_LOW(36) -#define K_BCM1480_INT_SMB_0 _BCM1480_INT_LOW(40) -#define K_BCM1480_INT_SMB_1 _BCM1480_INT_LOW(41) -#define K_BCM1480_INT_PCMCIA _BCM1480_INT_LOW(42) -#define K_BCM1480_INT_UART_0 _BCM1480_INT_LOW(44) -#define K_BCM1480_INT_UART_1 _BCM1480_INT_LOW(45) -#define K_BCM1480_INT_UART_2 _BCM1480_INT_LOW(46) -#define K_BCM1480_INT_UART_3 _BCM1480_INT_LOW(47) -#define K_BCM1480_INT_GPIO_4 _BCM1480_INT_LOW(52) -#define K_BCM1480_INT_GPIO_5 _BCM1480_INT_LOW(53) -#define K_BCM1480_INT_GPIO_6 _BCM1480_INT_LOW(54) -#define K_BCM1480_INT_GPIO_7 _BCM1480_INT_LOW(55) -#define K_BCM1480_INT_GPIO_8 _BCM1480_INT_LOW(56) -#define K_BCM1480_INT_GPIO_9 _BCM1480_INT_LOW(57) -#define K_BCM1480_INT_GPIO_10 _BCM1480_INT_LOW(58) -#define K_BCM1480_INT_GPIO_11 _BCM1480_INT_LOW(59) -#define K_BCM1480_INT_GPIO_12 _BCM1480_INT_LOW(60) -#define K_BCM1480_INT_GPIO_13 _BCM1480_INT_LOW(61) -#define K_BCM1480_INT_GPIO_14 _BCM1480_INT_LOW(62) -#define K_BCM1480_INT_GPIO_15 _BCM1480_INT_LOW(63) +#define K_BCM1480_INT_BAD_ECC _BCM1480_INT_LOW(1) +#define K_BCM1480_INT_COR_ECC _BCM1480_INT_LOW(2) +#define K_BCM1480_INT_IO_BUS _BCM1480_INT_LOW(3) +#define K_BCM1480_INT_PERF_CNT _BCM1480_INT_LOW(4) +#define K_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_LOW(5) +#define K_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_LOW(6) +#define K_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_LOW(7) +#define K_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_LOW(8) +#define K_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_LOW(9) +#define K_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_LOW(10) +#define K_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_LOW(11) +#define K_BCM1480_INT_PCI_ERROR _BCM1480_INT_LOW(16) +#define K_BCM1480_INT_PCI_RESET _BCM1480_INT_LOW(17) +#define K_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_LOW(18) +#define K_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_LOW(19) +#define K_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_LOW(20) +#define K_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_LOW(21) +#define K_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_LOW(22) +#define K_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_LOW(23) +#define K_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_LOW(24) +#define K_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_LOW(25) +#define K_BCM1480_INT_LDT_SMI _BCM1480_INT_LOW(32) +#define K_BCM1480_INT_LDT_NMI _BCM1480_INT_LOW(33) +#define K_BCM1480_INT_LDT_INIT _BCM1480_INT_LOW(34) +#define K_BCM1480_INT_LDT_STARTUP _BCM1480_INT_LOW(35) +#define K_BCM1480_INT_LDT_EXT _BCM1480_INT_LOW(36) +#define K_BCM1480_INT_SMB_0 _BCM1480_INT_LOW(40) +#define K_BCM1480_INT_SMB_1 _BCM1480_INT_LOW(41) +#define K_BCM1480_INT_PCMCIA _BCM1480_INT_LOW(42) +#define K_BCM1480_INT_UART_0 _BCM1480_INT_LOW(44) +#define K_BCM1480_INT_UART_1 _BCM1480_INT_LOW(45) +#define K_BCM1480_INT_UART_2 _BCM1480_INT_LOW(46) +#define K_BCM1480_INT_UART_3 _BCM1480_INT_LOW(47) +#define K_BCM1480_INT_GPIO_4 _BCM1480_INT_LOW(52) +#define K_BCM1480_INT_GPIO_5 _BCM1480_INT_LOW(53) +#define K_BCM1480_INT_GPIO_6 _BCM1480_INT_LOW(54) +#define K_BCM1480_INT_GPIO_7 _BCM1480_INT_LOW(55) +#define K_BCM1480_INT_GPIO_8 _BCM1480_INT_LOW(56) +#define K_BCM1480_INT_GPIO_9 _BCM1480_INT_LOW(57) +#define K_BCM1480_INT_GPIO_10 _BCM1480_INT_LOW(58) +#define K_BCM1480_INT_GPIO_11 _BCM1480_INT_LOW(59) +#define K_BCM1480_INT_GPIO_12 _BCM1480_INT_LOW(60) +#define K_BCM1480_INT_GPIO_13 _BCM1480_INT_LOW(61) +#define K_BCM1480_INT_GPIO_14 _BCM1480_INT_LOW(62) +#define K_BCM1480_INT_GPIO_15 _BCM1480_INT_LOW(63) /* * Mask values for each interrupt */ -#define _BCM1480_INT_MASK(w, n) _SB_MAKEMASK(w, ((n) & 0x3F)) -#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F)) -#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6) +#define _BCM1480_INT_MASK(w, n) _SB_MAKEMASK(w, ((n) & 0x3F)) +#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F)) +#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6) -#define M_BCM1480_INT_CASCADE _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0)) +#define M_BCM1480_INT_CASCADE _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0)) -#define M_BCM1480_INT_ADDR_TRAP _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP) -#define M_BCM1480_INT_GPIO_0 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0) -#define M_BCM1480_INT_GPIO_1 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1) -#define M_BCM1480_INT_GPIO_2 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2) -#define M_BCM1480_INT_GPIO_3 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3) -#define M_BCM1480_INT_PCI_INTA _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA) -#define M_BCM1480_INT_PCI_INTB _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB) -#define M_BCM1480_INT_PCI_INTC _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC) -#define M_BCM1480_INT_PCI_INTD _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD) -#define M_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0) -#define M_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1) -#define M_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2) -#define M_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3) -#define M_BCM1480_INT_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0) -#define M_BCM1480_INT_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1) -#define M_BCM1480_INT_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2) -#define M_BCM1480_INT_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3) -#define M_BCM1480_INT_DM_CH_0 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0) -#define M_BCM1480_INT_DM_CH_1 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1) -#define M_BCM1480_INT_DM_CH_2 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2) -#define M_BCM1480_INT_DM_CH_3 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3) -#define M_BCM1480_INT_MAC_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0) -#define M_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1) -#define M_BCM1480_INT_MAC_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1) -#define M_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1) -#define M_BCM1480_INT_MAC_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2) -#define M_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1) -#define M_BCM1480_INT_MAC_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3) -#define M_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1) -#define M_BCM1480_INT_PMI_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW) -#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH) -#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW) -#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH) -#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0) -#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0) -#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1) -#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2) -#define M_BCM1480_INT_MBOX_0_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3) -#define M_BCM1480_INT_MBOX_1_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0) -#define M_BCM1480_INT_MBOX_1_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1) -#define M_BCM1480_INT_MBOX_1_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2) -#define M_BCM1480_INT_MBOX_1_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3) -#define M_BCM1480_INT_BAD_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC) -#define M_BCM1480_INT_COR_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC) -#define M_BCM1480_INT_IO_BUS _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS) -#define M_BCM1480_INT_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT) -#define M_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT) -#define M_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE) -#define M_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE) -#define M_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0) -#define M_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1) -#define M_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2) -#define M_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3) -#define M_BCM1480_INT_PCI_ERROR _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR) -#define M_BCM1480_INT_PCI_RESET _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET) -#define M_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER) -#define M_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE) -#define M_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL) -#define M_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL) -#define M_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL) -#define M_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL) -#define M_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL) -#define M_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL) -#define M_BCM1480_INT_LDT_SMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI) -#define M_BCM1480_INT_LDT_NMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI) -#define M_BCM1480_INT_LDT_INIT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT) -#define M_BCM1480_INT_LDT_STARTUP _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP) -#define M_BCM1480_INT_LDT_EXT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT) -#define M_BCM1480_INT_SMB_0 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0) -#define M_BCM1480_INT_SMB_1 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1) -#define M_BCM1480_INT_PCMCIA _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA) -#define M_BCM1480_INT_UART_0 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0) -#define M_BCM1480_INT_UART_1 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1) -#define M_BCM1480_INT_UART_2 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2) -#define M_BCM1480_INT_UART_3 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3) -#define M_BCM1480_INT_GPIO_4 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4) -#define M_BCM1480_INT_GPIO_5 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5) -#define M_BCM1480_INT_GPIO_6 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6) -#define M_BCM1480_INT_GPIO_7 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7) -#define M_BCM1480_INT_GPIO_8 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8) -#define M_BCM1480_INT_GPIO_9 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9) -#define M_BCM1480_INT_GPIO_10 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10) -#define M_BCM1480_INT_GPIO_11 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11) -#define M_BCM1480_INT_GPIO_12 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12) -#define M_BCM1480_INT_GPIO_13 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13) -#define M_BCM1480_INT_GPIO_14 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14) -#define M_BCM1480_INT_GPIO_15 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15) +#define M_BCM1480_INT_ADDR_TRAP _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP) +#define M_BCM1480_INT_GPIO_0 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0) +#define M_BCM1480_INT_GPIO_1 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1) +#define M_BCM1480_INT_GPIO_2 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2) +#define M_BCM1480_INT_GPIO_3 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3) +#define M_BCM1480_INT_PCI_INTA _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA) +#define M_BCM1480_INT_PCI_INTB _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB) +#define M_BCM1480_INT_PCI_INTC _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC) +#define M_BCM1480_INT_PCI_INTD _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD) +#define M_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0) +#define M_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1) +#define M_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2) +#define M_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3) +#define M_BCM1480_INT_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0) +#define M_BCM1480_INT_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1) +#define M_BCM1480_INT_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2) +#define M_BCM1480_INT_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3) +#define M_BCM1480_INT_DM_CH_0 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0) +#define M_BCM1480_INT_DM_CH_1 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1) +#define M_BCM1480_INT_DM_CH_2 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2) +#define M_BCM1480_INT_DM_CH_3 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3) +#define M_BCM1480_INT_MAC_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0) +#define M_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1) +#define M_BCM1480_INT_MAC_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1) +#define M_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1) +#define M_BCM1480_INT_MAC_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2) +#define M_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1) +#define M_BCM1480_INT_MAC_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3) +#define M_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1) +#define M_BCM1480_INT_PMI_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW) +#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH) +#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW) +#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH) +#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0) +#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0) +#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1) +#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2) +#define M_BCM1480_INT_MBOX_0_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3) +#define M_BCM1480_INT_MBOX_1_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0) +#define M_BCM1480_INT_MBOX_1_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1) +#define M_BCM1480_INT_MBOX_1_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2) +#define M_BCM1480_INT_MBOX_1_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3) +#define M_BCM1480_INT_BAD_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC) +#define M_BCM1480_INT_COR_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC) +#define M_BCM1480_INT_IO_BUS _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS) +#define M_BCM1480_INT_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT) +#define M_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT) +#define M_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE) +#define M_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE) +#define M_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0) +#define M_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1) +#define M_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2) +#define M_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3) +#define M_BCM1480_INT_PCI_ERROR _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR) +#define M_BCM1480_INT_PCI_RESET _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET) +#define M_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER) +#define M_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE) +#define M_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL) +#define M_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL) +#define M_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL) +#define M_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL) +#define M_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL) +#define M_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL) +#define M_BCM1480_INT_LDT_SMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI) +#define M_BCM1480_INT_LDT_NMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI) +#define M_BCM1480_INT_LDT_INIT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT) +#define M_BCM1480_INT_LDT_STARTUP _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP) +#define M_BCM1480_INT_LDT_EXT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT) +#define M_BCM1480_INT_SMB_0 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0) +#define M_BCM1480_INT_SMB_1 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1) +#define M_BCM1480_INT_PCMCIA _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA) +#define M_BCM1480_INT_UART_0 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0) +#define M_BCM1480_INT_UART_1 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1) +#define M_BCM1480_INT_UART_2 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2) +#define M_BCM1480_INT_UART_3 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3) +#define M_BCM1480_INT_GPIO_4 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4) +#define M_BCM1480_INT_GPIO_5 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5) +#define M_BCM1480_INT_GPIO_6 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6) +#define M_BCM1480_INT_GPIO_7 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7) +#define M_BCM1480_INT_GPIO_8 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8) +#define M_BCM1480_INT_GPIO_9 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9) +#define M_BCM1480_INT_GPIO_10 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10) +#define M_BCM1480_INT_GPIO_11 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11) +#define M_BCM1480_INT_GPIO_12 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12) +#define M_BCM1480_INT_GPIO_13 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13) +#define M_BCM1480_INT_GPIO_14 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14) +#define M_BCM1480_INT_GPIO_15 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15) /* * Interrupt mappings (Table 18) */ -#define K_BCM1480_INT_MAP_I0 0 /* interrupt pins on processor */ -#define K_BCM1480_INT_MAP_I1 1 -#define K_BCM1480_INT_MAP_I2 2 -#define K_BCM1480_INT_MAP_I3 3 -#define K_BCM1480_INT_MAP_I4 4 -#define K_BCM1480_INT_MAP_I5 5 -#define K_BCM1480_INT_MAP_NMI 6 /* nonmaskable */ -#define K_BCM1480_INT_MAP_DINT 7 /* debug interrupt */ +#define K_BCM1480_INT_MAP_I0 0 /* interrupt pins on processor */ +#define K_BCM1480_INT_MAP_I1 1 +#define K_BCM1480_INT_MAP_I2 2 +#define K_BCM1480_INT_MAP_I3 3 +#define K_BCM1480_INT_MAP_I4 4 +#define K_BCM1480_INT_MAP_I5 5 +#define K_BCM1480_INT_MAP_NMI 6 /* nonmaskable */ +#define K_BCM1480_INT_MAP_DINT 7 /* debug interrupt */ /* * Interrupt LDT Set Register (Table 19) */ -#define S_BCM1480_INT_HT_INTMSG 0 -#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG) -#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG) -#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG) +#define S_BCM1480_INT_HT_INTMSG 0 +#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG) +#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG) +#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG) -#define K_BCM1480_INT_HT_INTMSG_FIXED 0 +#define K_BCM1480_INT_HT_INTMSG_FIXED 0 #define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1 -#define K_BCM1480_INT_HT_INTMSG_SMI 2 -#define K_BCM1480_INT_HT_INTMSG_NMI 3 -#define K_BCM1480_INT_HT_INTMSG_INIT 4 -#define K_BCM1480_INT_HT_INTMSG_STARTUP 5 -#define K_BCM1480_INT_HT_INTMSG_EXTINT 6 +#define K_BCM1480_INT_HT_INTMSG_SMI 2 +#define K_BCM1480_INT_HT_INTMSG_NMI 3 +#define K_BCM1480_INT_HT_INTMSG_INIT 4 +#define K_BCM1480_INT_HT_INTMSG_STARTUP 5 +#define K_BCM1480_INT_HT_INTMSG_EXTINT 6 #define K_BCM1480_INT_HT_INTMSG_RESERVED 7 -#define M_BCM1480_INT_HT_TRIGGERMODE _SB_MAKEMASK1(3) -#define V_BCM1480_INT_HT_EDGETRIGGER 0 -#define V_BCM1480_INT_HT_LEVELTRIGGER M_BCM1480_INT_HT_TRIGGERMODE +#define M_BCM1480_INT_HT_TRIGGERMODE _SB_MAKEMASK1(3) +#define V_BCM1480_INT_HT_EDGETRIGGER 0 +#define V_BCM1480_INT_HT_LEVELTRIGGER M_BCM1480_INT_HT_TRIGGERMODE -#define M_BCM1480_INT_HT_DESTMODE _SB_MAKEMASK1(4) -#define V_BCM1480_INT_HT_PHYSICALDEST 0 -#define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE +#define M_BCM1480_INT_HT_DESTMODE _SB_MAKEMASK1(4) +#define V_BCM1480_INT_HT_PHYSICALDEST 0 +#define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE -#define S_BCM1480_INT_HT_INTDEST 5 -#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST) -#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST) -#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST) +#define S_BCM1480_INT_HT_INTDEST 5 +#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST) +#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST) +#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST) -#define S_BCM1480_INT_HT_VECTOR 13 -#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR) -#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR) -#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR) +#define S_BCM1480_INT_HT_VECTOR 13 +#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR) +#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR) +#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR) /* * Vector prefix (Table 4-7) */ #define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH 0x00 -#define M_BCM1480_HTVECT_RAISE_MBOX_0 0x40 +#define M_BCM1480_HTVECT_RAISE_MBOX_0 0x40 #define M_BCM1480_HTVECT_RAISE_INTLDT_LO 0x80 -#define M_BCM1480_HTVECT_RAISE_MBOX_1 0xC0 +#define M_BCM1480_HTVECT_RAISE_MBOX_1 0xC0 #endif /* _BCM1480_INT_H */ diff --git a/arch/mips/include/asm/sibyte/bcm1480_l2c.h b/arch/mips/include/asm/sibyte/bcm1480_l2c.h index 725d38cb9d1..910e5c7e1b0 100644 --- a/arch/mips/include/asm/sibyte/bcm1480_l2c.h +++ b/arch/mips/include/asm/sibyte/bcm1480_l2c.h @@ -39,120 +39,120 @@ * Format of level 2 cache management address (Table 55) */ -#define S_BCM1480_L2C_MGMT_INDEX 5 -#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX) -#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX) -#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX) +#define S_BCM1480_L2C_MGMT_INDEX 5 +#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX) +#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX) +#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX) -#define S_BCM1480_L2C_MGMT_WAY 17 -#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY) -#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY) -#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY) +#define S_BCM1480_L2C_MGMT_WAY 17 +#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY) +#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY) +#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY) -#define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20) -#define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21) +#define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20) +#define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21) -#define S_BCM1480_L2C_MGMT_ECC_DIAG 22 -#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG) -#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG) -#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG) +#define S_BCM1480_L2C_MGMT_ECC_DIAG 22 +#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG) +#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG) +#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG) -#define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000 +#define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000 -#define BCM1480_L2C_ENTRIES_PER_WAY 4096 -#define BCM1480_L2C_NUM_WAYS 8 +#define BCM1480_L2C_ENTRIES_PER_WAY 4096 +#define BCM1480_L2C_NUM_WAYS 8 /* * Level 2 Cache Tag register (Table 59) */ -#define S_BCM1480_L2C_TAG_MBZ 0 -#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ) +#define S_BCM1480_L2C_TAG_MBZ 0 +#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ) -#define S_BCM1480_L2C_TAG_INDEX 5 -#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX) -#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX) -#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX) +#define S_BCM1480_L2C_TAG_INDEX 5 +#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX) +#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX) +#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX) /* Note that index bit 16 is also tag bit 40 */ -#define S_BCM1480_L2C_TAG_TAG 17 -#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG) -#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG) -#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG) +#define S_BCM1480_L2C_TAG_TAG 17 +#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG) +#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG) +#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG) -#define S_BCM1480_L2C_TAG_ECC 40 -#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC) -#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC) -#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC) +#define S_BCM1480_L2C_TAG_ECC 40 +#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC) +#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC) +#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC) -#define S_BCM1480_L2C_TAG_WAY 46 -#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY) -#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY) -#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY) +#define S_BCM1480_L2C_TAG_WAY 46 +#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY) +#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY) +#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY) -#define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49) -#define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50) +#define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49) +#define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50) -#define S_BCM1480_L2C_DATA_ECC 51 -#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC) -#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC) -#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC) +#define S_BCM1480_L2C_DATA_ECC 51 +#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC) +#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC) +#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC) /* * L2 Misc0 Value Register (Table 60) */ -#define S_BCM1480_L2C_MISC0_WAY_REMOTE 0 -#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE) +#define S_BCM1480_L2C_MISC0_WAY_REMOTE 0 +#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE) #define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_REMOTE, M_BCM1480_L2C_MISC0_WAY_REMOTE) -#define S_BCM1480_L2C_MISC0_WAY_LOCAL 8 -#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL) +#define S_BCM1480_L2C_MISC0_WAY_LOCAL 8 +#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL) #define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_LOCAL, M_BCM1480_L2C_MISC0_WAY_LOCAL) -#define S_BCM1480_L2C_MISC0_WAY_ENABLE 16 -#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE) +#define S_BCM1480_L2C_MISC0_WAY_ENABLE 16 +#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE) #define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_ENABLE, M_BCM1480_L2C_MISC0_WAY_ENABLE) #define S_BCM1480_L2C_MISC0_CACHE_DISABLE 24 #define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_DISABLE) #define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_DISABLE, M_BCM1480_L2C_MISC0_CACHE_DISABLE) -#define S_BCM1480_L2C_MISC0_CACHE_QUAD 26 -#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD) +#define S_BCM1480_L2C_MISC0_CACHE_QUAD 26 +#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD) #define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_QUAD, M_BCM1480_L2C_MISC0_CACHE_QUAD) -#define S_BCM1480_L2C_MISC0_MC_PRIORITY 30 -#define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY) +#define S_BCM1480_L2C_MISC0_MC_PRIORITY 30 +#define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY) -#define S_BCM1480_L2C_MISC0_ECC_CLEANUP 31 -#define M_BCM1480_L2C_MISC0_ECC_CLEANUP _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP) +#define S_BCM1480_L2C_MISC0_ECC_CLEANUP 31 +#define M_BCM1480_L2C_MISC0_ECC_CLEANUP _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP) /* * L2 Misc1 Value Register (Table 60) */ -#define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0) +#define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0 +#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0) #define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_0, M_BCM1480_L2C_MISC1_WAY_AGENT_0) -#define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1) +#define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8 +#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1) #define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_1, M_BCM1480_L2C_MISC1_WAY_AGENT_1) -#define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2) +#define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16 +#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2) #define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_2, M_BCM1480_L2C_MISC1_WAY_AGENT_2) -#define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3) +#define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24 +#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3) #define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_3, M_BCM1480_L2C_MISC1_WAY_AGENT_3) -#define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32 -#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4) +#define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32 +#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4) #define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_4, M_BCM1480_L2C_MISC1_WAY_AGENT_4) @@ -160,16 +160,16 @@ * L2 Misc2 Value Register (Table 60) */ -#define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8) +#define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0 +#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8) #define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_8, M_BCM1480_L2C_MISC2_WAY_AGENT_8) -#define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9) +#define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8 +#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9) #define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_9, M_BCM1480_L2C_MISC2_WAY_AGENT_9) -#define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16 -#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A) +#define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16 +#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A) #define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_A, M_BCM1480_L2C_MISC2_WAY_AGENT_A) diff --git a/arch/mips/include/asm/sibyte/bcm1480_mc.h b/arch/mips/include/asm/sibyte/bcm1480_mc.h index 4307a758e3b..86908fdb403 100644 --- a/arch/mips/include/asm/sibyte/bcm1480_mc.h +++ b/arch/mips/include/asm/sibyte/bcm1480_mc.h @@ -1,7 +1,7 @@ /* ********************************************************************* * BCM1280/BCM1480 Board Support Package * - * Memory Controller constants File: bcm1480_mc.h + * Memory Controller constants File: bcm1480_mc.h * * This module contains constants and macros useful for * programming the memory controller. @@ -39,33 +39,33 @@ * Memory Channel Configuration Register (Table 81) */ -#define S_BCM1480_MC_INTLV0 0 -#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) -#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) -#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) -#define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0) - -#define S_BCM1480_MC_INTLV1 8 -#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) -#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) -#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) -#define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0) - -#define S_BCM1480_MC_INTLV2 16 -#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2) -#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2) -#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2) -#define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0) - -#define S_BCM1480_MC_CS_MODE 32 -#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE) -#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE) -#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE) -#define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0) - -#define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \ - V_BCM1480_MC_INTLV1_DEFAULT | \ - V_BCM1480_MC_INTLV2_DEFAULT | \ +#define S_BCM1480_MC_INTLV0 0 +#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) +#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) +#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) +#define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0) + +#define S_BCM1480_MC_INTLV1 8 +#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) +#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) +#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) +#define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0) + +#define S_BCM1480_MC_INTLV2 16 +#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2) +#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2) +#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2) +#define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0) + +#define S_BCM1480_MC_CS_MODE 32 +#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE) +#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE) +#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE) +#define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0) + +#define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \ + V_BCM1480_MC_INTLV1_DEFAULT | \ + V_BCM1480_MC_INTLV2_DEFAULT | \ V_BCM1480_MC_CS_MODE_DEFAULT) #define K_BCM1480_MC_CS01_MODE 0x03 @@ -80,254 +80,254 @@ * Chip Select Start Address Register (Table 82) */ -#define S_BCM1480_MC_CS0_START 0 -#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START) -#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START) -#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START) +#define S_BCM1480_MC_CS0_START 0 +#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START) +#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START) +#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START) -#define S_BCM1480_MC_CS1_START 16 -#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START) -#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START) -#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START) +#define S_BCM1480_MC_CS1_START 16 +#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START) +#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START) +#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START) -#define S_BCM1480_MC_CS2_START 32 -#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START) -#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START) -#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START) +#define S_BCM1480_MC_CS2_START 32 +#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START) +#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START) +#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START) -#define S_BCM1480_MC_CS3_START 48 -#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START) -#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START) -#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START) +#define S_BCM1480_MC_CS3_START 48 +#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START) +#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START) +#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START) /* * Chip Select End Address Register (Table 83) */ -#define S_BCM1480_MC_CS0_END 0 -#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END) -#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END) -#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END) +#define S_BCM1480_MC_CS0_END 0 +#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END) +#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END) +#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END) -#define S_BCM1480_MC_CS1_END 16 -#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END) -#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END) -#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END) +#define S_BCM1480_MC_CS1_END 16 +#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END) +#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END) +#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END) -#define S_BCM1480_MC_CS2_END 32 -#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END) -#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END) -#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END) +#define S_BCM1480_MC_CS2_END 32 +#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END) +#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END) +#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END) -#define S_BCM1480_MC_CS3_END 48 -#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END) -#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END) -#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END) +#define S_BCM1480_MC_CS3_END 48 +#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END) +#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END) +#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END) /* * Row Address Bit Select Register 0 (Table 84) */ -#define S_BCM1480_MC_ROW00 0 -#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6, S_BCM1480_MC_ROW00) -#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00) -#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00) - -#define S_BCM1480_MC_ROW01 8 -#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6, S_BCM1480_MC_ROW01) -#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01) -#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01) - -#define S_BCM1480_MC_ROW02 16 -#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6, S_BCM1480_MC_ROW02) -#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02) -#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02) - -#define S_BCM1480_MC_ROW03 24 -#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6, S_BCM1480_MC_ROW03) -#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03) -#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03) - -#define S_BCM1480_MC_ROW04 32 -#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6, S_BCM1480_MC_ROW04) -#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04) -#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04) - -#define S_BCM1480_MC_ROW05 40 -#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6, S_BCM1480_MC_ROW05) -#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05) -#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05) - -#define S_BCM1480_MC_ROW06 48 -#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6, S_BCM1480_MC_ROW06) -#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06) -#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06) - -#define S_BCM1480_MC_ROW07 56 -#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6, S_BCM1480_MC_ROW07) -#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07) -#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07) +#define S_BCM1480_MC_ROW00 0 +#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6, S_BCM1480_MC_ROW00) +#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00) +#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00) + +#define S_BCM1480_MC_ROW01 8 +#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6, S_BCM1480_MC_ROW01) +#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01) +#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01) + +#define S_BCM1480_MC_ROW02 16 +#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6, S_BCM1480_MC_ROW02) +#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02) +#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02) + +#define S_BCM1480_MC_ROW03 24 +#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6, S_BCM1480_MC_ROW03) +#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03) +#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03) + +#define S_BCM1480_MC_ROW04 32 +#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6, S_BCM1480_MC_ROW04) +#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04) +#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04) + +#define S_BCM1480_MC_ROW05 40 +#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6, S_BCM1480_MC_ROW05) +#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05) +#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05) + +#define S_BCM1480_MC_ROW06 48 +#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6, S_BCM1480_MC_ROW06) +#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06) +#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06) + +#define S_BCM1480_MC_ROW07 56 +#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6, S_BCM1480_MC_ROW07) +#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07) +#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07) /* * Row Address Bit Select Register 1 (Table 85) */ -#define S_BCM1480_MC_ROW08 0 -#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6, S_BCM1480_MC_ROW08) -#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08) -#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08) +#define S_BCM1480_MC_ROW08 0 +#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6, S_BCM1480_MC_ROW08) +#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08) +#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08) -#define S_BCM1480_MC_ROW09 8 -#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6, S_BCM1480_MC_ROW09) -#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09) -#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09) +#define S_BCM1480_MC_ROW09 8 +#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6, S_BCM1480_MC_ROW09) +#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09) +#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09) -#define S_BCM1480_MC_ROW10 16 -#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6, S_BCM1480_MC_ROW10) -#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10) -#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10) +#define S_BCM1480_MC_ROW10 16 +#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6, S_BCM1480_MC_ROW10) +#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10) +#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10) -#define S_BCM1480_MC_ROW11 24 -#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6, S_BCM1480_MC_ROW11) -#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11) -#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11) +#define S_BCM1480_MC_ROW11 24 +#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6, S_BCM1480_MC_ROW11) +#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11) +#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11) -#define S_BCM1480_MC_ROW12 32 -#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6, S_BCM1480_MC_ROW12) -#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12) -#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12) +#define S_BCM1480_MC_ROW12 32 +#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6, S_BCM1480_MC_ROW12) +#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12) +#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12) -#define S_BCM1480_MC_ROW13 40 -#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6, S_BCM1480_MC_ROW13) -#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13) -#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13) +#define S_BCM1480_MC_ROW13 40 +#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6, S_BCM1480_MC_ROW13) +#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13) +#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13) -#define S_BCM1480_MC_ROW14 48 -#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6, S_BCM1480_MC_ROW14) -#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14) -#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14) +#define S_BCM1480_MC_ROW14 48 +#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6, S_BCM1480_MC_ROW14) +#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14) +#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14) -#define K_BCM1480_MC_ROWX_BIT_SPACING 8 +#define K_BCM1480_MC_ROWX_BIT_SPACING 8 /* * Column Address Bit Select Register 0 (Table 86) */ -#define S_BCM1480_MC_COL00 0 -#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6, S_BCM1480_MC_COL00) -#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL00) -#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00) - -#define S_BCM1480_MC_COL01 8 -#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6, S_BCM1480_MC_COL01) -#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL01) -#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01) - -#define S_BCM1480_MC_COL02 16 -#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6, S_BCM1480_MC_COL02) -#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL02) -#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02) - -#define S_BCM1480_MC_COL03 24 -#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6, S_BCM1480_MC_COL03) -#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL03) -#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03) - -#define S_BCM1480_MC_COL04 32 -#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6, S_BCM1480_MC_COL04) -#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL04) -#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04) - -#define S_BCM1480_MC_COL05 40 -#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6, S_BCM1480_MC_COL05) -#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL05) -#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05) - -#define S_BCM1480_MC_COL06 48 -#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6, S_BCM1480_MC_COL06) -#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL06) -#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06) - -#define S_BCM1480_MC_COL07 56 -#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6, S_BCM1480_MC_COL07) -#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL07) -#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07) +#define S_BCM1480_MC_COL00 0 +#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6, S_BCM1480_MC_COL00) +#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL00) +#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00) + +#define S_BCM1480_MC_COL01 8 +#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6, S_BCM1480_MC_COL01) +#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL01) +#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01) + +#define S_BCM1480_MC_COL02 16 +#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6, S_BCM1480_MC_COL02) +#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL02) +#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02) + +#define S_BCM1480_MC_COL03 24 +#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6, S_BCM1480_MC_COL03) +#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL03) +#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03) + +#define S_BCM1480_MC_COL04 32 +#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6, S_BCM1480_MC_COL04) +#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL04) +#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04) + +#define S_BCM1480_MC_COL05 40 +#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6, S_BCM1480_MC_COL05) +#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL05) +#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05) + +#define S_BCM1480_MC_COL06 48 +#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6, S_BCM1480_MC_COL06) +#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL06) +#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06) + +#define S_BCM1480_MC_COL07 56 +#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6, S_BCM1480_MC_COL07) +#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL07) +#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07) /* * Column Address Bit Select Register 1 (Table 87) */ -#define S_BCM1480_MC_COL08 0 -#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6, S_BCM1480_MC_COL08) -#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL08) -#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08) +#define S_BCM1480_MC_COL08 0 +#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6, S_BCM1480_MC_COL08) +#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL08) +#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08) -#define S_BCM1480_MC_COL09 8 -#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6, S_BCM1480_MC_COL09) -#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL09) -#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09) +#define S_BCM1480_MC_COL09 8 +#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6, S_BCM1480_MC_COL09) +#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL09) +#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09) -#define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */ +#define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */ -#define S_BCM1480_MC_COL11 24 -#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6, S_BCM1480_MC_COL11) -#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL11) -#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11) +#define S_BCM1480_MC_COL11 24 +#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6, S_BCM1480_MC_COL11) +#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL11) +#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11) -#define S_BCM1480_MC_COL12 32 -#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6, S_BCM1480_MC_COL12) -#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL12) -#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12) +#define S_BCM1480_MC_COL12 32 +#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6, S_BCM1480_MC_COL12) +#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL12) +#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12) -#define S_BCM1480_MC_COL13 40 -#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6, S_BCM1480_MC_COL13) -#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL13) -#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13) +#define S_BCM1480_MC_COL13 40 +#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6, S_BCM1480_MC_COL13) +#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL13) +#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13) -#define S_BCM1480_MC_COL14 48 -#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6, S_BCM1480_MC_COL14) -#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL14) -#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14) +#define S_BCM1480_MC_COL14 48 +#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6, S_BCM1480_MC_COL14) +#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL14) +#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14) -#define K_BCM1480_MC_COLX_BIT_SPACING 8 +#define K_BCM1480_MC_COLX_BIT_SPACING 8 /* * CS0 and CS1 Bank Address Bit Select Register (Table 88) */ -#define S_BCM1480_MC_CS01_BANK0 0 -#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0) -#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0) -#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0) +#define S_BCM1480_MC_CS01_BANK0 0 +#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0) +#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0) +#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0) -#define S_BCM1480_MC_CS01_BANK1 8 -#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1) -#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1) -#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1) +#define S_BCM1480_MC_CS01_BANK1 8 +#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1) +#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1) +#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1) -#define S_BCM1480_MC_CS01_BANK2 16 -#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2) -#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2) -#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2) +#define S_BCM1480_MC_CS01_BANK2 16 +#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2) +#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2) +#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2) /* * CS2 and CS3 Bank Address Bit Select Register (Table 89) */ -#define S_BCM1480_MC_CS23_BANK0 0 -#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0) -#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0) -#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0) +#define S_BCM1480_MC_CS23_BANK0 0 +#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0) +#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0) +#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0) -#define S_BCM1480_MC_CS23_BANK1 8 -#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1) -#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1) -#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1) +#define S_BCM1480_MC_CS23_BANK1 8 +#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1) +#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1) +#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1) -#define S_BCM1480_MC_CS23_BANK2 16 -#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2) -#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2) -#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2) +#define S_BCM1480_MC_CS23_BANK2 16 +#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2) +#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2) +#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2) #define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8 @@ -335,19 +335,19 @@ * DRAM Command Register (Table 90) */ -#define S_BCM1480_MC_COMMAND 0 -#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND) -#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND) -#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND) +#define S_BCM1480_MC_COMMAND 0 +#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND) +#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND) +#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND) -#define K_BCM1480_MC_COMMAND_EMRS 0 -#define K_BCM1480_MC_COMMAND_MRS 1 -#define K_BCM1480_MC_COMMAND_PRE 2 -#define K_BCM1480_MC_COMMAND_AR 3 -#define K_BCM1480_MC_COMMAND_SETRFSH 4 -#define K_BCM1480_MC_COMMAND_CLRRFSH 5 -#define K_BCM1480_MC_COMMAND_SETPWRDN 6 -#define K_BCM1480_MC_COMMAND_CLRPWRDN 7 +#define K_BCM1480_MC_COMMAND_EMRS 0 +#define K_BCM1480_MC_COMMAND_MRS 1 +#define K_BCM1480_MC_COMMAND_PRE 2 +#define K_BCM1480_MC_COMMAND_AR 3 +#define K_BCM1480_MC_COMMAND_SETRFSH 4 +#define K_BCM1480_MC_COMMAND_CLRRFSH 5 +#define K_BCM1480_MC_COMMAND_SETPWRDN 6 +#define K_BCM1480_MC_COMMAND_CLRPWRDN 7 #if SIBYTE_HDR_FEATURE(1480, PASS2) #define K_BCM1480_MC_COMMAND_EMRS2 8 @@ -356,61 +356,61 @@ #define K_BCM1480_MC_COMMAND_DISABLE_MCLK 11 #endif -#define V_BCM1480_MC_COMMAND_EMRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS) -#define V_BCM1480_MC_COMMAND_MRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS) -#define V_BCM1480_MC_COMMAND_PRE V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE) -#define V_BCM1480_MC_COMMAND_AR V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR) -#define V_BCM1480_MC_COMMAND_SETRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH) -#define V_BCM1480_MC_COMMAND_CLRRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH) -#define V_BCM1480_MC_COMMAND_SETPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN) -#define V_BCM1480_MC_COMMAND_CLRPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN) +#define V_BCM1480_MC_COMMAND_EMRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS) +#define V_BCM1480_MC_COMMAND_MRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS) +#define V_BCM1480_MC_COMMAND_PRE V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE) +#define V_BCM1480_MC_COMMAND_AR V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR) +#define V_BCM1480_MC_COMMAND_SETRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH) +#define V_BCM1480_MC_COMMAND_CLRRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH) +#define V_BCM1480_MC_COMMAND_SETPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN) +#define V_BCM1480_MC_COMMAND_CLRPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN) #if SIBYTE_HDR_FEATURE(1480, PASS2) -#define V_BCM1480_MC_COMMAND_EMRS2 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2) -#define V_BCM1480_MC_COMMAND_EMRS3 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3) +#define V_BCM1480_MC_COMMAND_EMRS2 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2) +#define V_BCM1480_MC_COMMAND_EMRS3 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3) #define V_BCM1480_MC_COMMAND_ENABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK) #define V_BCM1480_MC_COMMAND_DISABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK) #endif #define S_BCM1480_MC_CS0 4 -#define M_BCM1480_MC_CS0 _SB_MAKEMASK1(4) -#define M_BCM1480_MC_CS1 _SB_MAKEMASK1(5) -#define M_BCM1480_MC_CS2 _SB_MAKEMASK1(6) -#define M_BCM1480_MC_CS3 _SB_MAKEMASK1(7) -#define M_BCM1480_MC_CS4 _SB_MAKEMASK1(8) -#define M_BCM1480_MC_CS5 _SB_MAKEMASK1(9) -#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) -#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) +#define M_BCM1480_MC_CS0 _SB_MAKEMASK1(4) +#define M_BCM1480_MC_CS1 _SB_MAKEMASK1(5) +#define M_BCM1480_MC_CS2 _SB_MAKEMASK1(6) +#define M_BCM1480_MC_CS3 _SB_MAKEMASK1(7) +#define M_BCM1480_MC_CS4 _SB_MAKEMASK1(8) +#define M_BCM1480_MC_CS5 _SB_MAKEMASK1(9) +#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) +#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) -#define M_BCM1480_MC_CS _SB_MAKEMASK(8, S_BCM1480_MC_CS0) -#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0) -#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0) +#define M_BCM1480_MC_CS _SB_MAKEMASK(8, S_BCM1480_MC_CS0) +#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0) +#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0) -#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) +#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) /* * DRAM Mode Register (Table 91) */ -#define S_BCM1480_MC_EMODE 0 -#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15, S_BCM1480_MC_EMODE) -#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE) -#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE) -#define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0) +#define S_BCM1480_MC_EMODE 0 +#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15, S_BCM1480_MC_EMODE) +#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE) +#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE) +#define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0) -#define S_BCM1480_MC_MODE 16 -#define M_BCM1480_MC_MODE _SB_MAKEMASK(15, S_BCM1480_MC_MODE) -#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MODE) -#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE) -#define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0) +#define S_BCM1480_MC_MODE 16 +#define M_BCM1480_MC_MODE _SB_MAKEMASK(15, S_BCM1480_MC_MODE) +#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MODE) +#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE) +#define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0) -#define S_BCM1480_MC_DRAM_TYPE 32 -#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE) -#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE) -#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE) +#define S_BCM1480_MC_DRAM_TYPE 32 +#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE) +#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE) +#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE) -#define K_BCM1480_MC_DRAM_TYPE_JEDEC 0 -#define K_BCM1480_MC_DRAM_TYPE_FCRAM 1 +#define K_BCM1480_MC_DRAM_TYPE_JEDEC 0 +#define K_BCM1480_MC_DRAM_TYPE_FCRAM 1 #if SIBYTE_HDR_FEATURE(1480, PASS2) #define K_BCM1480_MC_DRAM_TYPE_DDR2 2 @@ -418,27 +418,27 @@ #define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1 0 -#define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC) -#define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM) +#define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC) +#define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define V_BCM1480_MC_DRAM_TYPE_DDR2 V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2) #endif -#define M_BCM1480_MC_GANGED _SB_MAKEMASK1(36) -#define M_BCM1480_MC_BY9_INTF _SB_MAKEMASK1(37) -#define M_BCM1480_MC_FORCE_ECC64 _SB_MAKEMASK1(38) -#define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39) +#define M_BCM1480_MC_GANGED _SB_MAKEMASK1(36) +#define M_BCM1480_MC_BY9_INTF _SB_MAKEMASK1(37) +#define M_BCM1480_MC_FORCE_ECC64 _SB_MAKEMASK1(38) +#define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39) -#define S_BCM1480_MC_PG_POLICY 40 -#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY) -#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY) -#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY) +#define S_BCM1480_MC_PG_POLICY 40 +#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY) +#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY) +#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY) -#define K_BCM1480_MC_PG_POLICY_CLOSED 0 +#define K_BCM1480_MC_PG_POLICY_CLOSED 0 #define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1 -#define V_BCM1480_MC_PG_POLICY_CLOSED V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED) +#define V_BCM1480_MC_PG_POLICY_CLOSED V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED) #define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) #if SIBYTE_HDR_FEATURE(1480, PASS2) @@ -447,32 +447,32 @@ #endif #define V_BCM1480_MC_DRAMMODE_DEFAULT V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \ - V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) + V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) /* * Memory Clock Configuration Register (Table 92) */ -#define S_BCM1480_MC_CLK_RATIO 0 -#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6, S_BCM1480_MC_CLK_RATIO) -#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CLK_RATIO) -#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_BCM1480_MC_CLK_RATIO, M_BCM1480_MC_CLK_RATIO) +#define S_BCM1480_MC_CLK_RATIO 0 +#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6, S_BCM1480_MC_CLK_RATIO) +#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CLK_RATIO) +#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_BCM1480_MC_CLK_RATIO, M_BCM1480_MC_CLK_RATIO) -#define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10) +#define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10) -#define S_BCM1480_MC_REF_RATE 8 -#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8, S_BCM1480_MC_REF_RATE) -#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_REF_RATE) -#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x, S_BCM1480_MC_REF_RATE, M_BCM1480_MC_REF_RATE) +#define S_BCM1480_MC_REF_RATE 8 +#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8, S_BCM1480_MC_REF_RATE) +#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_REF_RATE) +#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x, S_BCM1480_MC_REF_RATE, M_BCM1480_MC_REF_RATE) -#define K_BCM1480_MC_REF_RATE_100MHz 0x31 -#define K_BCM1480_MC_REF_RATE_200MHz 0x62 -#define K_BCM1480_MC_REF_RATE_400MHz 0xC4 +#define K_BCM1480_MC_REF_RATE_100MHz 0x31 +#define K_BCM1480_MC_REF_RATE_200MHz 0x62 +#define K_BCM1480_MC_REF_RATE_400MHz 0xC4 -#define V_BCM1480_MC_REF_RATE_100MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz) -#define V_BCM1480_MC_REF_RATE_200MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz) -#define V_BCM1480_MC_REF_RATE_400MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz) -#define V_BCM1480_MC_REF_RATE_DEFAULT V_BCM1480_MC_REF_RATE_400MHz +#define V_BCM1480_MC_REF_RATE_100MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz) +#define V_BCM1480_MC_REF_RATE_200MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz) +#define V_BCM1480_MC_REF_RATE_400MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz) +#define V_BCM1480_MC_REF_RATE_DEFAULT V_BCM1480_MC_REF_RATE_400MHz #if SIBYTE_HDR_FEATURE(1480, PASS2) #define M_BCM1480_MC_AUTO_REF_DIS _SB_MAKEMASK1(16) @@ -518,19 +518,19 @@ #define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32) -#define S_BCM1480_MC_ODT0 0 +#define S_BCM1480_MC_ODT0 0 #define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8, S_BCM1480_MC_ODT0) #define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT0) -#define S_BCM1480_MC_ODT2 8 +#define S_BCM1480_MC_ODT2 8 #define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8, S_BCM1480_MC_ODT2) #define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT2) -#define S_BCM1480_MC_ODT4 16 +#define S_BCM1480_MC_ODT4 16 #define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8, S_BCM1480_MC_ODT4) #define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT4) -#define S_BCM1480_MC_ODT6 24 +#define S_BCM1480_MC_ODT6 24 #define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8, S_BCM1480_MC_ODT6) #define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT6) #endif @@ -539,139 +539,139 @@ * Memory DLL Configuration Register (Table 93) */ -#define S_BCM1480_MC_ADDR_COARSE_ADJ 0 -#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_ADDR_COARSE_ADJ) -#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ) -#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ, M_BCM1480_MC_ADDR_COARSE_ADJ) +#define S_BCM1480_MC_ADDR_COARSE_ADJ 0 +#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_ADDR_COARSE_ADJ) +#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ) +#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ, M_BCM1480_MC_ADDR_COARSE_ADJ) #define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0) #if SIBYTE_HDR_FEATURE(1480, PASS2) -#define S_BCM1480_MC_ADDR_FREQ_RANGE 8 -#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FREQ_RANGE) -#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE) -#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE, M_BCM1480_MC_ADDR_FREQ_RANGE) -#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4) +#define S_BCM1480_MC_ADDR_FREQ_RANGE 8 +#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FREQ_RANGE) +#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE) +#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE, M_BCM1480_MC_ADDR_FREQ_RANGE) +#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4) #endif -#define S_BCM1480_MC_ADDR_FINE_ADJ 8 -#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FINE_ADJ) -#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ) -#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ, M_BCM1480_MC_ADDR_FINE_ADJ) +#define S_BCM1480_MC_ADDR_FINE_ADJ 8 +#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FINE_ADJ) +#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ) +#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ, M_BCM1480_MC_ADDR_FINE_ADJ) #define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8) -#define S_BCM1480_MC_DQI_COARSE_ADJ 16 -#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQI_COARSE_ADJ) -#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ) -#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ, M_BCM1480_MC_DQI_COARSE_ADJ) +#define S_BCM1480_MC_DQI_COARSE_ADJ 16 +#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQI_COARSE_ADJ) +#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ) +#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ, M_BCM1480_MC_DQI_COARSE_ADJ) #define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0) #if SIBYTE_HDR_FEATURE(1480, PASS2) -#define S_BCM1480_MC_DQI_FREQ_RANGE 24 -#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FREQ_RANGE) -#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE) -#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE, M_BCM1480_MC_DQI_FREQ_RANGE) -#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4) +#define S_BCM1480_MC_DQI_FREQ_RANGE 24 +#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FREQ_RANGE) +#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE) +#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE, M_BCM1480_MC_DQI_FREQ_RANGE) +#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4) #endif -#define S_BCM1480_MC_DQI_FINE_ADJ 24 -#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FINE_ADJ) -#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ) -#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ, M_BCM1480_MC_DQI_FINE_ADJ) +#define S_BCM1480_MC_DQI_FINE_ADJ 24 +#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FINE_ADJ) +#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ) +#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ, M_BCM1480_MC_DQI_FINE_ADJ) #define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8) -#define S_BCM1480_MC_DQO_COARSE_ADJ 32 -#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQO_COARSE_ADJ) -#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ) -#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ, M_BCM1480_MC_DQO_COARSE_ADJ) +#define S_BCM1480_MC_DQO_COARSE_ADJ 32 +#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQO_COARSE_ADJ) +#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ) +#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ, M_BCM1480_MC_DQO_COARSE_ADJ) #define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0) #if SIBYTE_HDR_FEATURE(1480, PASS2) -#define S_BCM1480_MC_DQO_FREQ_RANGE 40 -#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FREQ_RANGE) -#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE) -#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE, M_BCM1480_MC_DQO_FREQ_RANGE) -#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4) +#define S_BCM1480_MC_DQO_FREQ_RANGE 40 +#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FREQ_RANGE) +#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE) +#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE, M_BCM1480_MC_DQO_FREQ_RANGE) +#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4) #endif -#define S_BCM1480_MC_DQO_FINE_ADJ 40 -#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FINE_ADJ) -#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ) -#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ, M_BCM1480_MC_DQO_FINE_ADJ) +#define S_BCM1480_MC_DQO_FINE_ADJ 40 +#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FINE_ADJ) +#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ) +#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ, M_BCM1480_MC_DQO_FINE_ADJ) #define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8) #if SIBYTE_HDR_FEATURE(1480, PASS2) -#define S_BCM1480_MC_DLL_PDSEL 44 -#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_PDSEL) -#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_PDSEL) -#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_PDSEL, M_BCM1480_MC_DLL_PDSEL) -#define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0) - -#define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46) -#define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47) +#define S_BCM1480_MC_DLL_PDSEL 44 +#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_PDSEL) +#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_PDSEL) +#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_PDSEL, M_BCM1480_MC_DLL_PDSEL) +#define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0) + +#define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46) +#define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47) #endif -#define S_BCM1480_MC_DLL_DEFAULT 48 -#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6, S_BCM1480_MC_DLL_DEFAULT) -#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_DEFAULT) -#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_DEFAULT, M_BCM1480_MC_DLL_DEFAULT) +#define S_BCM1480_MC_DLL_DEFAULT 48 +#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6, S_BCM1480_MC_DLL_DEFAULT) +#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_DEFAULT) +#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_DEFAULT, M_BCM1480_MC_DLL_DEFAULT) #define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DLL_REGCTRL 54 -#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_REGCTRL) -#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_REGCTRL) -#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_REGCTRL, M_BCM1480_MC_DLL_REGCTRL) +#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_REGCTRL) +#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_REGCTRL) +#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_REGCTRL, M_BCM1480_MC_DLL_REGCTRL) #define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0) #endif #if SIBYTE_HDR_FEATURE(1480, PASS2) -#define S_BCM1480_MC_DLL_FREQ_RANGE 56 -#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_FREQ_RANGE) -#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE) -#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE, M_BCM1480_MC_DLL_FREQ_RANGE) -#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4) +#define S_BCM1480_MC_DLL_FREQ_RANGE 56 +#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_FREQ_RANGE) +#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE) +#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE, M_BCM1480_MC_DLL_FREQ_RANGE) +#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4) #endif -#define S_BCM1480_MC_DLL_STEP_SIZE 56 -#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_STEP_SIZE) -#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE) -#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE, M_BCM1480_MC_DLL_STEP_SIZE) +#define S_BCM1480_MC_DLL_STEP_SIZE 56 +#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_STEP_SIZE) +#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE) +#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE, M_BCM1480_MC_DLL_STEP_SIZE) #define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8) #if SIBYTE_HDR_FEATURE(1480, PASS2) #define S_BCM1480_MC_DLL_BGCTRL 60 -#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_BGCTRL) -#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_BGCTRL) -#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_BGCTRL, M_BCM1480_MC_DLL_BGCTRL) -#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0) +#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_BGCTRL) +#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_BGCTRL) +#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_BGCTRL, M_BCM1480_MC_DLL_BGCTRL) +#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0) #endif -#define M_BCM1480_MC_DLL_BYPASS _SB_MAKEMASK1(63) +#define M_BCM1480_MC_DLL_BYPASS _SB_MAKEMASK1(63) /* * Memory Drive Configuration Register (Table 94) */ -#define S_BCM1480_MC_RTT_BYP_PULLDOWN 0 -#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLDOWN) +#define S_BCM1480_MC_RTT_BYP_PULLDOWN 0 +#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLDOWN) #define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN) #define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN, M_BCM1480_MC_RTT_BYP_PULLDOWN) -#define S_BCM1480_MC_RTT_BYP_PULLUP 6 -#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLUP) -#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP) -#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP, M_BCM1480_MC_RTT_BYP_PULLUP) +#define S_BCM1480_MC_RTT_BYP_PULLUP 6 +#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLUP) +#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP) +#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP, M_BCM1480_MC_RTT_BYP_PULLUP) -#define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8) -#define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9) +#define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8) +#define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9) #define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10 #define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) #define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) #define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN, M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) -#define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15 -#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLUP) +#define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15 +#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLUP) #define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP) #define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP, M_BCM1480_MC_PVT_BYP_C1_PULLUP) @@ -680,153 +680,153 @@ #define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) #define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN, M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) -#define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25 -#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLUP) +#define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25 +#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLUP) #define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP) #define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP, M_BCM1480_MC_PVT_BYP_C2_PULLUP) -#define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30) -#define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31) +#define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30) +#define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31) -#define M_BCM1480_MC_CLK_CLASS _SB_MAKEMASK1(34) -#define M_BCM1480_MC_DATA_CLASS _SB_MAKEMASK1(35) -#define M_BCM1480_MC_ADDR_CLASS _SB_MAKEMASK1(36) +#define M_BCM1480_MC_CLK_CLASS _SB_MAKEMASK1(34) +#define M_BCM1480_MC_DATA_CLASS _SB_MAKEMASK1(35) +#define M_BCM1480_MC_ADDR_CLASS _SB_MAKEMASK1(36) -#define M_BCM1480_MC_DQ_ODT_75 _SB_MAKEMASK1(37) -#define M_BCM1480_MC_DQ_ODT_150 _SB_MAKEMASK1(38) -#define M_BCM1480_MC_DQS_ODT_75 _SB_MAKEMASK1(39) -#define M_BCM1480_MC_DQS_ODT_150 _SB_MAKEMASK1(40) -#define M_BCM1480_MC_DQS_DIFF _SB_MAKEMASK1(41) +#define M_BCM1480_MC_DQ_ODT_75 _SB_MAKEMASK1(37) +#define M_BCM1480_MC_DQ_ODT_150 _SB_MAKEMASK1(38) +#define M_BCM1480_MC_DQS_ODT_75 _SB_MAKEMASK1(39) +#define M_BCM1480_MC_DQS_ODT_150 _SB_MAKEMASK1(40) +#define M_BCM1480_MC_DQS_DIFF _SB_MAKEMASK1(41) /* * ECC Test Data Register (Table 95) */ -#define S_BCM1480_MC_DATA_INVERT 0 -#define M_DATA_ECC_INVERT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_INVERT) +#define S_BCM1480_MC_DATA_INVERT 0 +#define M_DATA_ECC_INVERT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_INVERT) /* * ECC Test ECC Register (Table 96) */ -#define S_BCM1480_MC_ECC_INVERT 0 -#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8, S_BCM1480_MC_ECC_INVERT) +#define S_BCM1480_MC_ECC_INVERT 0 +#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8, S_BCM1480_MC_ECC_INVERT) /* * SDRAM Timing Register (Table 97) */ -#define S_BCM1480_MC_tRCD 0 -#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4, S_BCM1480_MC_tRCD) -#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCD) -#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCD, M_BCM1480_MC_tRCD) -#define K_BCM1480_MC_tRCD_DEFAULT 3 -#define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT) - -#define S_BCM1480_MC_tCL 4 -#define M_BCM1480_MC_tCL _SB_MAKEMASK(4, S_BCM1480_MC_tCL) -#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCL) -#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x, S_BCM1480_MC_tCL, M_BCM1480_MC_tCL) -#define K_BCM1480_MC_tCL_DEFAULT 2 -#define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT) - -#define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8) - -#define S_BCM1480_MC_tWR 9 -#define M_BCM1480_MC_tWR _SB_MAKEMASK(3, S_BCM1480_MC_tWR) -#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tWR) -#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x, S_BCM1480_MC_tWR, M_BCM1480_MC_tWR) -#define K_BCM1480_MC_tWR_DEFAULT 2 -#define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT) - -#define S_BCM1480_MC_tCwD 12 -#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4, S_BCM1480_MC_tCwD) -#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCwD) -#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x, S_BCM1480_MC_tCwD, M_BCM1480_MC_tCwD) -#define K_BCM1480_MC_tCwD_DEFAULT 1 -#define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT) - -#define S_BCM1480_MC_tRP 16 -#define M_BCM1480_MC_tRP _SB_MAKEMASK(4, S_BCM1480_MC_tRP) -#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRP) -#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRP, M_BCM1480_MC_tRP) -#define K_BCM1480_MC_tRP_DEFAULT 4 -#define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT) - -#define S_BCM1480_MC_tRRD 20 -#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4, S_BCM1480_MC_tRRD) -#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRRD) -#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRRD, M_BCM1480_MC_tRRD) -#define K_BCM1480_MC_tRRD_DEFAULT 2 -#define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT) - -#define S_BCM1480_MC_tRCw 24 -#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5, S_BCM1480_MC_tRCw) -#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCw) -#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCw, M_BCM1480_MC_tRCw) -#define K_BCM1480_MC_tRCw_DEFAULT 10 -#define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT) - -#define S_BCM1480_MC_tRCr 32 -#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5, S_BCM1480_MC_tRCr) -#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCr) -#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCr, M_BCM1480_MC_tRCr) -#define K_BCM1480_MC_tRCr_DEFAULT 9 -#define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT) +#define S_BCM1480_MC_tRCD 0 +#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4, S_BCM1480_MC_tRCD) +#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCD) +#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCD, M_BCM1480_MC_tRCD) +#define K_BCM1480_MC_tRCD_DEFAULT 3 +#define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT) + +#define S_BCM1480_MC_tCL 4 +#define M_BCM1480_MC_tCL _SB_MAKEMASK(4, S_BCM1480_MC_tCL) +#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCL) +#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x, S_BCM1480_MC_tCL, M_BCM1480_MC_tCL) +#define K_BCM1480_MC_tCL_DEFAULT 2 +#define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT) + +#define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8) + +#define S_BCM1480_MC_tWR 9 +#define M_BCM1480_MC_tWR _SB_MAKEMASK(3, S_BCM1480_MC_tWR) +#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tWR) +#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x, S_BCM1480_MC_tWR, M_BCM1480_MC_tWR) +#define K_BCM1480_MC_tWR_DEFAULT 2 +#define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT) + +#define S_BCM1480_MC_tCwD 12 +#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4, S_BCM1480_MC_tCwD) +#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCwD) +#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x, S_BCM1480_MC_tCwD, M_BCM1480_MC_tCwD) +#define K_BCM1480_MC_tCwD_DEFAULT 1 +#define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT) + +#define S_BCM1480_MC_tRP 16 +#define M_BCM1480_MC_tRP _SB_MAKEMASK(4, S_BCM1480_MC_tRP) +#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRP) +#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRP, M_BCM1480_MC_tRP) +#define K_BCM1480_MC_tRP_DEFAULT 4 +#define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT) + +#define S_BCM1480_MC_tRRD 20 +#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4, S_BCM1480_MC_tRRD) +#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRRD) +#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRRD, M_BCM1480_MC_tRRD) +#define K_BCM1480_MC_tRRD_DEFAULT 2 +#define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT) + +#define S_BCM1480_MC_tRCw 24 +#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5, S_BCM1480_MC_tRCw) +#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCw) +#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCw, M_BCM1480_MC_tRCw) +#define K_BCM1480_MC_tRCw_DEFAULT 10 +#define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT) + +#define S_BCM1480_MC_tRCr 32 +#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5, S_BCM1480_MC_tRCr) +#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCr) +#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCr, M_BCM1480_MC_tRCr) +#define K_BCM1480_MC_tRCr_DEFAULT 9 +#define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT) #if SIBYTE_HDR_FEATURE(1480, PASS2) -#define S_BCM1480_MC_tFAW 40 -#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6, S_BCM1480_MC_tFAW) -#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFAW) -#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x, S_BCM1480_MC_tFAW, M_BCM1480_MC_tFAW) -#define K_BCM1480_MC_tFAW_DEFAULT 0 -#define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT) +#define S_BCM1480_MC_tFAW 40 +#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6, S_BCM1480_MC_tFAW) +#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFAW) +#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x, S_BCM1480_MC_tFAW, M_BCM1480_MC_tFAW) +#define K_BCM1480_MC_tFAW_DEFAULT 0 +#define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT) #endif -#define S_BCM1480_MC_tRFC 48 -#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7, S_BCM1480_MC_tRFC) -#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRFC) -#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x, S_BCM1480_MC_tRFC, M_BCM1480_MC_tRFC) -#define K_BCM1480_MC_tRFC_DEFAULT 12 -#define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT) - -#define S_BCM1480_MC_tFIFO 56 -#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2, S_BCM1480_MC_tFIFO) -#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFIFO) -#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x, S_BCM1480_MC_tFIFO, M_BCM1480_MC_tFIFO) -#define K_BCM1480_MC_tFIFO_DEFAULT 0 -#define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT) - -#define S_BCM1480_MC_tW2R 58 -#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2, S_BCM1480_MC_tW2R) -#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2R) -#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2R, M_BCM1480_MC_tW2R) -#define K_BCM1480_MC_tW2R_DEFAULT 1 -#define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT) - -#define S_BCM1480_MC_tR2W 60 -#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2, S_BCM1480_MC_tR2W) -#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tR2W) -#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tR2W, M_BCM1480_MC_tR2W) -#define K_BCM1480_MC_tR2W_DEFAULT 0 -#define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT) +#define S_BCM1480_MC_tRFC 48 +#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7, S_BCM1480_MC_tRFC) +#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRFC) +#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x, S_BCM1480_MC_tRFC, M_BCM1480_MC_tRFC) +#define K_BCM1480_MC_tRFC_DEFAULT 12 +#define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT) + +#define S_BCM1480_MC_tFIFO 56 +#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2, S_BCM1480_MC_tFIFO) +#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFIFO) +#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x, S_BCM1480_MC_tFIFO, M_BCM1480_MC_tFIFO) +#define K_BCM1480_MC_tFIFO_DEFAULT 0 +#define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT) + +#define S_BCM1480_MC_tW2R 58 +#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2, S_BCM1480_MC_tW2R) +#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2R) +#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2R, M_BCM1480_MC_tW2R) +#define K_BCM1480_MC_tW2R_DEFAULT 1 +#define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT) + +#define S_BCM1480_MC_tR2W 60 +#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2, S_BCM1480_MC_tR2W) +#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tR2W) +#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tR2W, M_BCM1480_MC_tR2W) +#define K_BCM1480_MC_tR2W_DEFAULT 0 +#define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT) #define M_BCM1480_MC_tR2R _SB_MAKEMASK1(62) -#define V_BCM1480_MC_TIMING_DEFAULT (M_BCM1480_MC_tR2R | \ - V_BCM1480_MC_tFIFO_DEFAULT | \ - V_BCM1480_MC_tR2W_DEFAULT | \ - V_BCM1480_MC_tW2R_DEFAULT | \ - V_BCM1480_MC_tRFC_DEFAULT | \ - V_BCM1480_MC_tRCr_DEFAULT | \ - V_BCM1480_MC_tRCw_DEFAULT | \ - V_BCM1480_MC_tRRD_DEFAULT | \ - V_BCM1480_MC_tRP_DEFAULT | \ - V_BCM1480_MC_tCwD_DEFAULT | \ - V_BCM1480_MC_tWR_DEFAULT | \ - M_BCM1480_MC_tCrDh | \ - V_BCM1480_MC_tCL_DEFAULT | \ - V_BCM1480_MC_tRCD_DEFAULT) +#define V_BCM1480_MC_TIMING_DEFAULT (M_BCM1480_MC_tR2R | \ + V_BCM1480_MC_tFIFO_DEFAULT | \ + V_BCM1480_MC_tR2W_DEFAULT | \ + V_BCM1480_MC_tW2R_DEFAULT | \ + V_BCM1480_MC_tRFC_DEFAULT | \ + V_BCM1480_MC_tRCr_DEFAULT | \ + V_BCM1480_MC_tRCw_DEFAULT | \ + V_BCM1480_MC_tRRD_DEFAULT | \ + V_BCM1480_MC_tRP_DEFAULT | \ + V_BCM1480_MC_tCwD_DEFAULT | \ + V_BCM1480_MC_tWR_DEFAULT | \ + M_BCM1480_MC_tCrDh | \ + V_BCM1480_MC_tCL_DEFAULT | \ + V_BCM1480_MC_tRCD_DEFAULT) /* * SDRAM Timing Register 2 @@ -834,33 +834,33 @@ #if SIBYTE_HDR_FEATURE(1480, PASS2) -#define S_BCM1480_MC_tAL 0 -#define M_BCM1480_MC_tAL _SB_MAKEMASK(4, S_BCM1480_MC_tAL) -#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tAL) -#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x, S_BCM1480_MC_tAL, M_BCM1480_MC_tAL) -#define K_BCM1480_MC_tAL_DEFAULT 0 -#define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT) - -#define S_BCM1480_MC_tRTP 4 -#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3, S_BCM1480_MC_tRTP) -#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRTP) -#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRTP, M_BCM1480_MC_tRTP) -#define K_BCM1480_MC_tRTP_DEFAULT 2 -#define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT) - -#define S_BCM1480_MC_tW2W 8 -#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2, S_BCM1480_MC_tW2W) -#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2W) -#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2W, M_BCM1480_MC_tW2W) -#define K_BCM1480_MC_tW2W_DEFAULT 0 -#define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT) - -#define S_BCM1480_MC_tRAP 12 -#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4, S_BCM1480_MC_tRAP) -#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRAP) -#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRAP, M_BCM1480_MC_tRAP) -#define K_BCM1480_MC_tRAP_DEFAULT 0 -#define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT) +#define S_BCM1480_MC_tAL 0 +#define M_BCM1480_MC_tAL _SB_MAKEMASK(4, S_BCM1480_MC_tAL) +#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tAL) +#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x, S_BCM1480_MC_tAL, M_BCM1480_MC_tAL) +#define K_BCM1480_MC_tAL_DEFAULT 0 +#define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT) + +#define S_BCM1480_MC_tRTP 4 +#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3, S_BCM1480_MC_tRTP) +#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRTP) +#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRTP, M_BCM1480_MC_tRTP) +#define K_BCM1480_MC_tRTP_DEFAULT 2 +#define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT) + +#define S_BCM1480_MC_tW2W 8 +#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2, S_BCM1480_MC_tW2W) +#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2W) +#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2W, M_BCM1480_MC_tW2W) +#define K_BCM1480_MC_tW2W_DEFAULT 0 +#define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT) + +#define S_BCM1480_MC_tRAP 12 +#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4, S_BCM1480_MC_tRAP) +#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRAP) +#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRAP, M_BCM1480_MC_tRAP) +#define K_BCM1480_MC_tRAP_DEFAULT 0 +#define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT) #endif @@ -874,111 +874,111 @@ * Global Configuration Register (Table 99) */ -#define S_BCM1480_MC_BLK_SET_MARK 8 -#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_SET_MARK) -#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_SET_MARK) -#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_SET_MARK, M_BCM1480_MC_BLK_SET_MARK) +#define S_BCM1480_MC_BLK_SET_MARK 8 +#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_SET_MARK) +#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_SET_MARK) +#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_SET_MARK, M_BCM1480_MC_BLK_SET_MARK) -#define S_BCM1480_MC_BLK_CLR_MARK 12 -#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_CLR_MARK) -#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_CLR_MARK) -#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_CLR_MARK, M_BCM1480_MC_BLK_CLR_MARK) +#define S_BCM1480_MC_BLK_CLR_MARK 12 +#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_CLR_MARK) +#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_CLR_MARK) +#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_CLR_MARK, M_BCM1480_MC_BLK_CLR_MARK) -#define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16) +#define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16) -#define S_BCM1480_MC_MAX_AGE 20 -#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4, S_BCM1480_MC_MAX_AGE) -#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MAX_AGE) -#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x, S_BCM1480_MC_MAX_AGE, M_BCM1480_MC_MAX_AGE) +#define S_BCM1480_MC_MAX_AGE 20 +#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4, S_BCM1480_MC_MAX_AGE) +#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MAX_AGE) +#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x, S_BCM1480_MC_MAX_AGE, M_BCM1480_MC_MAX_AGE) -#define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29) -#define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30) -#define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32) +#define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29) +#define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30) +#define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32) -#define S_BCM1480_MC_SLEW 33 -#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2, S_BCM1480_MC_SLEW) -#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_SLEW) -#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x, S_BCM1480_MC_SLEW, M_BCM1480_MC_SLEW) +#define S_BCM1480_MC_SLEW 33 +#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2, S_BCM1480_MC_SLEW) +#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_SLEW) +#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x, S_BCM1480_MC_SLEW, M_BCM1480_MC_SLEW) -#define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35) +#define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35) /* * Global Channel Interleave Register (Table 100) */ -#define S_BCM1480_MC_INTLV0 0 -#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) -#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) -#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) - -#define S_BCM1480_MC_INTLV1 8 -#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) -#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) -#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) - -#define S_BCM1480_MC_INTLV_MODE 16 -#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3, S_BCM1480_MC_INTLV_MODE) -#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV_MODE) -#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV_MODE, M_BCM1480_MC_INTLV_MODE) - -#define K_BCM1480_MC_INTLV_MODE_NONE 0x0 -#define K_BCM1480_MC_INTLV_MODE_01 0x1 -#define K_BCM1480_MC_INTLV_MODE_23 0x2 -#define K_BCM1480_MC_INTLV_MODE_01_23 0x3 -#define K_BCM1480_MC_INTLV_MODE_0123 0x4 - -#define V_BCM1480_MC_INTLV_MODE_NONE V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE) -#define V_BCM1480_MC_INTLV_MODE_01 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01) -#define V_BCM1480_MC_INTLV_MODE_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23) -#define V_BCM1480_MC_INTLV_MODE_01_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23) -#define V_BCM1480_MC_INTLV_MODE_0123 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123) +#define S_BCM1480_MC_INTLV0 0 +#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) +#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) +#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) + +#define S_BCM1480_MC_INTLV1 8 +#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) +#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) +#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) + +#define S_BCM1480_MC_INTLV_MODE 16 +#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3, S_BCM1480_MC_INTLV_MODE) +#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV_MODE) +#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV_MODE, M_BCM1480_MC_INTLV_MODE) + +#define K_BCM1480_MC_INTLV_MODE_NONE 0x0 +#define K_BCM1480_MC_INTLV_MODE_01 0x1 +#define K_BCM1480_MC_INTLV_MODE_23 0x2 +#define K_BCM1480_MC_INTLV_MODE_01_23 0x3 +#define K_BCM1480_MC_INTLV_MODE_0123 0x4 + +#define V_BCM1480_MC_INTLV_MODE_NONE V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE) +#define V_BCM1480_MC_INTLV_MODE_01 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01) +#define V_BCM1480_MC_INTLV_MODE_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23) +#define V_BCM1480_MC_INTLV_MODE_01_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23) +#define V_BCM1480_MC_INTLV_MODE_0123 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123) /* * ECC Status Register */ -#define S_BCM1480_MC_ECC_ERR_ADDR 0 -#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_ERR_ADDR) -#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR) -#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR, M_BCM1480_MC_ECC_ERR_ADDR) +#define S_BCM1480_MC_ECC_ERR_ADDR 0 +#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_ERR_ADDR) +#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR) +#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR, M_BCM1480_MC_ECC_ERR_ADDR) #if SIBYTE_HDR_FEATURE(1480, PASS2) -#define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60) +#define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60) #endif -#define M_BCM1480_MC_ECC_MULT_ERR_DET _SB_MAKEMASK1(61) -#define M_BCM1480_MC_ECC_UERR_DET _SB_MAKEMASK1(62) -#define M_BCM1480_MC_ECC_CERR_DET _SB_MAKEMASK1(63) +#define M_BCM1480_MC_ECC_MULT_ERR_DET _SB_MAKEMASK1(61) +#define M_BCM1480_MC_ECC_UERR_DET _SB_MAKEMASK1(62) +#define M_BCM1480_MC_ECC_CERR_DET _SB_MAKEMASK1(63) /* * Global ECC Address Register (Table 102) */ -#define S_BCM1480_MC_ECC_CORR_ADDR 0 -#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_CORR_ADDR) -#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR) -#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR, M_BCM1480_MC_ECC_CORR_ADDR) +#define S_BCM1480_MC_ECC_CORR_ADDR 0 +#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_CORR_ADDR) +#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR) +#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR, M_BCM1480_MC_ECC_CORR_ADDR) /* * Global ECC Correction Register (Table 103) */ -#define S_BCM1480_MC_ECC_CORRECT 0 -#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_CORRECT) -#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORRECT) -#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORRECT, M_BCM1480_MC_ECC_CORRECT) +#define S_BCM1480_MC_ECC_CORRECT 0 +#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_CORRECT) +#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORRECT) +#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORRECT, M_BCM1480_MC_ECC_CORRECT) /* * Global ECC Performance Counters Control Register (Table 104) */ -#define S_BCM1480_MC_CHANNEL_SELECT 0 -#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4, S_BCM1480_MC_CHANNEL_SELECT) -#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CHANNEL_SELECT) -#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x, S_BCM1480_MC_CHANNEL_SELECT, M_BCM1480_MC_CHANNEL_SELECT) -#define K_BCM1480_MC_CHANNEL_SELECT_0 0x1 -#define K_BCM1480_MC_CHANNEL_SELECT_1 0x2 -#define K_BCM1480_MC_CHANNEL_SELECT_2 0x4 -#define K_BCM1480_MC_CHANNEL_SELECT_3 0x8 +#define S_BCM1480_MC_CHANNEL_SELECT 0 +#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4, S_BCM1480_MC_CHANNEL_SELECT) +#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CHANNEL_SELECT) +#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x, S_BCM1480_MC_CHANNEL_SELECT, M_BCM1480_MC_CHANNEL_SELECT) +#define K_BCM1480_MC_CHANNEL_SELECT_0 0x1 +#define K_BCM1480_MC_CHANNEL_SELECT_1 0x2 +#define K_BCM1480_MC_CHANNEL_SELECT_2 0x4 +#define K_BCM1480_MC_CHANNEL_SELECT_3 0x8 #endif /* _BCM1480_MC_H */ diff --git a/arch/mips/include/asm/sibyte/bcm1480_regs.h b/arch/mips/include/asm/sibyte/bcm1480_regs.h index 84d168ddfeb..ec0dacf6f0c 100644 --- a/arch/mips/include/asm/sibyte/bcm1480_regs.h +++ b/arch/mips/include/asm/sibyte/bcm1480_regs.h @@ -1,7 +1,7 @@ /* ********************************************************************* * BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package * - * Register Definitions File: bcm1480_regs.h + * Register Definitions File: bcm1480_regs.h * * This module contains the addresses of the on-chip peripherals * on the BCM1280 and BCM1480. @@ -80,48 +80,48 @@ * Memory Controller Registers (Section 6) ********************************************************************* */ -#define A_BCM1480_MC_BASE_0 0x0010050000 -#define A_BCM1480_MC_BASE_1 0x0010051000 -#define A_BCM1480_MC_BASE_2 0x0010052000 -#define A_BCM1480_MC_BASE_3 0x0010053000 -#define BCM1480_MC_REGISTER_SPACING 0x1000 +#define A_BCM1480_MC_BASE_0 0x0010050000 +#define A_BCM1480_MC_BASE_1 0x0010051000 +#define A_BCM1480_MC_BASE_2 0x0010052000 +#define A_BCM1480_MC_BASE_3 0x0010053000 +#define BCM1480_MC_REGISTER_SPACING 0x1000 -#define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING) +#define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING) #define A_BCM1480_MC_REGISTER(ctlid, reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) -#define R_BCM1480_MC_CONFIG 0x0000000100 -#define R_BCM1480_MC_CS_START 0x0000000120 -#define R_BCM1480_MC_CS_END 0x0000000140 -#define S_BCM1480_MC_CS_STARTEND 24 - -#define R_BCM1480_MC_CS01_ROW0 0x0000000180 -#define R_BCM1480_MC_CS01_ROW1 0x00000001A0 -#define R_BCM1480_MC_CS23_ROW0 0x0000000200 -#define R_BCM1480_MC_CS23_ROW1 0x0000000220 -#define R_BCM1480_MC_CS01_COL0 0x0000000280 -#define R_BCM1480_MC_CS01_COL1 0x00000002A0 -#define R_BCM1480_MC_CS23_COL0 0x0000000300 -#define R_BCM1480_MC_CS23_COL1 0x0000000320 - -#define R_BCM1480_MC_CSX_BASE 0x0000000180 -#define R_BCM1480_MC_CSX_ROW0 0x0000000000 /* relative to CSX_BASE */ -#define R_BCM1480_MC_CSX_ROW1 0x0000000020 /* relative to CSX_BASE */ -#define R_BCM1480_MC_CSX_COL0 0x0000000100 /* relative to CSX_BASE */ -#define R_BCM1480_MC_CSX_COL1 0x0000000120 /* relative to CSX_BASE */ -#define BCM1480_MC_CSX_SPACING 0x0000000080 /* CS23 relative to CS01 */ - -#define R_BCM1480_MC_CS01_BA 0x0000000380 -#define R_BCM1480_MC_CS23_BA 0x00000003A0 -#define R_BCM1480_MC_DRAMCMD 0x0000000400 -#define R_BCM1480_MC_DRAMMODE 0x0000000420 -#define R_BCM1480_MC_CLOCK_CFG 0x0000000440 -#define R_BCM1480_MC_MCLK_CFG R_BCM1480_MC_CLOCK_CFG -#define R_BCM1480_MC_TEST_DATA 0x0000000480 -#define R_BCM1480_MC_TEST_ECC 0x00000004A0 -#define R_BCM1480_MC_TIMING1 0x00000004C0 -#define R_BCM1480_MC_TIMING2 0x00000004E0 -#define R_BCM1480_MC_DLL_CFG 0x0000000500 -#define R_BCM1480_MC_DRIVE_CFG 0x0000000520 +#define R_BCM1480_MC_CONFIG 0x0000000100 +#define R_BCM1480_MC_CS_START 0x0000000120 +#define R_BCM1480_MC_CS_END 0x0000000140 +#define S_BCM1480_MC_CS_STARTEND 24 + +#define R_BCM1480_MC_CS01_ROW0 0x0000000180 +#define R_BCM1480_MC_CS01_ROW1 0x00000001A0 +#define R_BCM1480_MC_CS23_ROW0 0x0000000200 +#define R_BCM1480_MC_CS23_ROW1 0x0000000220 +#define R_BCM1480_MC_CS01_COL0 0x0000000280 +#define R_BCM1480_MC_CS01_COL1 0x00000002A0 +#define R_BCM1480_MC_CS23_COL0 0x0000000300 +#define R_BCM1480_MC_CS23_COL1 0x0000000320 + +#define R_BCM1480_MC_CSX_BASE 0x0000000180 +#define R_BCM1480_MC_CSX_ROW0 0x0000000000 /* relative to CSX_BASE */ +#define R_BCM1480_MC_CSX_ROW1 0x0000000020 /* relative to CSX_BASE */ +#define R_BCM1480_MC_CSX_COL0 0x0000000100 /* relative to CSX_BASE */ +#define R_BCM1480_MC_CSX_COL1 0x0000000120 /* relative to CSX_BASE */ +#define BCM1480_MC_CSX_SPACING 0x0000000080 /* CS23 relative to CS01 */ + +#define R_BCM1480_MC_CS01_BA 0x0000000380 +#define R_BCM1480_MC_CS23_BA 0x00000003A0 +#define R_BCM1480_MC_DRAMCMD 0x0000000400 +#define R_BCM1480_MC_DRAMMODE 0x0000000420 +#define R_BCM1480_MC_CLOCK_CFG 0x0000000440 +#define R_BCM1480_MC_MCLK_CFG R_BCM1480_MC_CLOCK_CFG +#define R_BCM1480_MC_TEST_DATA 0x0000000480 +#define R_BCM1480_MC_TEST_ECC 0x00000004A0 +#define R_BCM1480_MC_TIMING1 0x00000004C0 +#define R_BCM1480_MC_TIMING2 0x00000004E0 +#define R_BCM1480_MC_DLL_CFG 0x0000000500 +#define R_BCM1480_MC_DRIVE_CFG 0x0000000520 #if SIBYTE_HDR_FEATURE(1480, PASS2) #define R_BCM1480_MC_ODT 0x0000000460 @@ -129,55 +129,55 @@ #endif /* Global registers (single instance) */ -#define A_BCM1480_MC_GLB_CONFIG 0x0010054100 -#define A_BCM1480_MC_GLB_INTLV 0x0010054120 -#define A_BCM1480_MC_GLB_ECC_STATUS 0x0010054140 -#define A_BCM1480_MC_GLB_ECC_ADDR 0x0010054160 -#define A_BCM1480_MC_GLB_ECC_CORRECT 0x0010054180 +#define A_BCM1480_MC_GLB_CONFIG 0x0010054100 +#define A_BCM1480_MC_GLB_INTLV 0x0010054120 +#define A_BCM1480_MC_GLB_ECC_STATUS 0x0010054140 +#define A_BCM1480_MC_GLB_ECC_ADDR 0x0010054160 +#define A_BCM1480_MC_GLB_ECC_CORRECT 0x0010054180 #define A_BCM1480_MC_GLB_PERF_CNT_CONTROL 0x00100541A0 /* ********************************************************************* * L2 Cache Control Registers (Section 5) ********************************************************************* */ -#define A_BCM1480_L2_BASE 0x0010040000 +#define A_BCM1480_L2_BASE 0x0010040000 -#define A_BCM1480_L2_READ_TAG 0x0010040018 -#define A_BCM1480_L2_ECC_TAG 0x0010040038 -#define A_BCM1480_L2_MISC0_VALUE 0x0010040058 -#define A_BCM1480_L2_MISC1_VALUE 0x0010040078 -#define A_BCM1480_L2_MISC2_VALUE 0x0010040098 -#define A_BCM1480_L2_MISC_CONFIG 0x0010040040 /* x040 */ -#define A_BCM1480_L2_CACHE_DISABLE 0x0010040060 /* x060 */ +#define A_BCM1480_L2_READ_TAG 0x0010040018 +#define A_BCM1480_L2_ECC_TAG 0x0010040038 +#define A_BCM1480_L2_MISC0_VALUE 0x0010040058 +#define A_BCM1480_L2_MISC1_VALUE 0x0010040078 +#define A_BCM1480_L2_MISC2_VALUE 0x0010040098 +#define A_BCM1480_L2_MISC_CONFIG 0x0010040040 /* x040 */ +#define A_BCM1480_L2_CACHE_DISABLE 0x0010040060 /* x060 */ #define A_BCM1480_L2_MAKECACHEDISABLE(x) (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12)) -#define A_BCM1480_L2_WAY_ENABLE_3_0 0x0010040080 /* x080 */ -#define A_BCM1480_L2_WAY_ENABLE_7_4 0x00100400A0 /* x0A0 */ +#define A_BCM1480_L2_WAY_ENABLE_3_0 0x0010040080 /* x080 */ +#define A_BCM1480_L2_WAY_ENABLE_7_4 0x00100400A0 /* x0A0 */ #define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12)) #define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12)) #define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12)) #define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12)) -#define A_BCM1480_L2_WAY_LOCAL_3_0 0x0010040100 /* x100 */ -#define A_BCM1480_L2_WAY_LOCAL_7_4 0x0010040120 /* x120 */ -#define A_BCM1480_L2_WAY_REMOTE_3_0 0x0010040140 /* x140 */ -#define A_BCM1480_L2_WAY_REMOTE_7_4 0x0010040160 /* x160 */ -#define A_BCM1480_L2_WAY_AGENT_3_0 0x00100400C0 /* xxC0 */ -#define A_BCM1480_L2_WAY_AGENT_7_4 0x00100400E0 /* xxE0 */ +#define A_BCM1480_L2_WAY_LOCAL_3_0 0x0010040100 /* x100 */ +#define A_BCM1480_L2_WAY_LOCAL_7_4 0x0010040120 /* x120 */ +#define A_BCM1480_L2_WAY_REMOTE_3_0 0x0010040140 /* x140 */ +#define A_BCM1480_L2_WAY_REMOTE_7_4 0x0010040160 /* x160 */ +#define A_BCM1480_L2_WAY_AGENT_3_0 0x00100400C0 /* xxC0 */ +#define A_BCM1480_L2_WAY_AGENT_7_4 0x00100400E0 /* xxE0 */ #define A_BCM1480_L2_WAY_ENABLE(A, banks) (A | (((~(banks))&0x0F) << 8)) -#define A_BCM1480_L2_BANK_BASE 0x00D0300000 -#define A_BCM1480_L2_BANK_ADDRESS(b) (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17)) -#define A_BCM1480_L2_MGMT_TAG_BASE 0x00D0000000 +#define A_BCM1480_L2_BANK_BASE 0x00D0300000 +#define A_BCM1480_L2_BANK_ADDRESS(b) (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17)) +#define A_BCM1480_L2_MGMT_TAG_BASE 0x00D0000000 /* ********************************************************************* * PCI-X Interface Registers (Section 7) ********************************************************************* */ -#define A_BCM1480_PCI_BASE 0x0010061400 +#define A_BCM1480_PCI_BASE 0x0010061400 -#define A_BCM1480_PCI_RESET 0x0010061400 -#define A_BCM1480_PCI_DLL 0x0010061500 +#define A_BCM1480_PCI_RESET 0x0010061400 +#define A_BCM1480_PCI_DLL 0x0010061500 -#define A_BCM1480_PCI_TYPE00_HEADER 0x002E000000 +#define A_BCM1480_PCI_TYPE00_HEADER 0x002E000000 /* ********************************************************************* * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6) @@ -185,19 +185,19 @@ /* No register changes with Rev.C BCM1250, but one additional MAC */ -#define A_BCM1480_MAC_BASE_2 0x0010066000 +#define A_BCM1480_MAC_BASE_2 0x0010066000 #ifndef A_MAC_BASE_2 -#define A_MAC_BASE_2 A_BCM1480_MAC_BASE_2 +#define A_MAC_BASE_2 A_BCM1480_MAC_BASE_2 #endif -#define A_BCM1480_MAC_BASE_3 0x0010067000 -#define A_MAC_BASE_3 A_BCM1480_MAC_BASE_3 +#define A_BCM1480_MAC_BASE_3 0x0010067000 +#define A_MAC_BASE_3 A_BCM1480_MAC_BASE_3 -#define R_BCM1480_MAC_DMA_OODPKTLOST 0x00000038 +#define R_BCM1480_MAC_DMA_OODPKTLOST 0x00000038 #ifndef R_MAC_DMA_OODPKTLOST -#define R_MAC_DMA_OODPKTLOST R_BCM1480_MAC_DMA_OODPKTLOST +#define R_MAC_DMA_OODPKTLOST R_BCM1480_MAC_DMA_OODPKTLOST #endif @@ -208,18 +208,18 @@ /* No significant differences from BCM1250, two DUARTs */ /* Conventions, per user manual: - * DUART generic, channels A,B,C,D - * DUART0 implementing channels A,B - * DUART1 inplementing channels C,D + * DUART generic, channels A,B,C,D + * DUART0 implementing channels A,B + * DUART1 inplementing channels C,D */ -#define BCM1480_DUART_NUM_PORTS 4 +#define BCM1480_DUART_NUM_PORTS 4 -#define A_BCM1480_DUART0 0x0010060000 -#define A_BCM1480_DUART1 0x0010060400 -#define A_BCM1480_DUART(chan) ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1) +#define A_BCM1480_DUART0 0x0010060000 +#define A_BCM1480_DUART1 0x0010060400 +#define A_BCM1480_DUART(chan) ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1) -#define BCM1480_DUART_CHANREG_SPACING 0x100 +#define BCM1480_DUART_CHANREG_SPACING 0x100 #define A_BCM1480_DUART_CHANREG(chan, reg) \ (A_BCM1480_DUART(chan) + \ BCM1480_DUART_CHANREG_SPACING * (((chan) & 1) + 1) + (reg)) @@ -249,43 +249,43 @@ * These constants are the absolute addresses. */ -#define A_BCM1480_DUART_MODE_REG_1_C 0x0010060400 -#define A_BCM1480_DUART_MODE_REG_2_C 0x0010060410 -#define A_BCM1480_DUART_STATUS_C 0x0010060420 -#define A_BCM1480_DUART_CLK_SEL_C 0x0010060430 -#define A_BCM1480_DUART_FULL_CTL_C 0x0010060440 -#define A_BCM1480_DUART_CMD_C 0x0010060450 -#define A_BCM1480_DUART_RX_HOLD_C 0x0010060460 -#define A_BCM1480_DUART_TX_HOLD_C 0x0010060470 -#define A_BCM1480_DUART_OPCR_C 0x0010060480 -#define A_BCM1480_DUART_AUX_CTRL_C 0x0010060490 - -#define A_BCM1480_DUART_MODE_REG_1_D 0x0010060500 -#define A_BCM1480_DUART_MODE_REG_2_D 0x0010060510 -#define A_BCM1480_DUART_STATUS_D 0x0010060520 -#define A_BCM1480_DUART_CLK_SEL_D 0x0010060530 -#define A_BCM1480_DUART_FULL_CTL_D 0x0010060540 -#define A_BCM1480_DUART_CMD_D 0x0010060550 -#define A_BCM1480_DUART_RX_HOLD_D 0x0010060560 -#define A_BCM1480_DUART_TX_HOLD_D 0x0010060570 -#define A_BCM1480_DUART_OPCR_D 0x0010060580 -#define A_BCM1480_DUART_AUX_CTRL_D 0x0010060590 - -#define A_BCM1480_DUART_INPORT_CHNG_CD 0x0010060600 -#define A_BCM1480_DUART_AUX_CTRL_CD 0x0010060610 -#define A_BCM1480_DUART_ISR_C 0x0010060620 -#define A_BCM1480_DUART_IMR_C 0x0010060630 -#define A_BCM1480_DUART_ISR_D 0x0010060640 -#define A_BCM1480_DUART_IMR_D 0x0010060650 -#define A_BCM1480_DUART_OUT_PORT_CD 0x0010060660 -#define A_BCM1480_DUART_OPCR_CD 0x0010060670 -#define A_BCM1480_DUART_IN_PORT_CD 0x0010060680 -#define A_BCM1480_DUART_ISR_CD 0x0010060690 -#define A_BCM1480_DUART_IMR_CD 0x00100606A0 -#define A_BCM1480_DUART_SET_OPR_CD 0x00100606B0 -#define A_BCM1480_DUART_CLEAR_OPR_CD 0x00100606C0 -#define A_BCM1480_DUART_INPORT_CHNG_C 0x00100606D0 -#define A_BCM1480_DUART_INPORT_CHNG_D 0x00100606E0 +#define A_BCM1480_DUART_MODE_REG_1_C 0x0010060400 +#define A_BCM1480_DUART_MODE_REG_2_C 0x0010060410 +#define A_BCM1480_DUART_STATUS_C 0x0010060420 +#define A_BCM1480_DUART_CLK_SEL_C 0x0010060430 +#define A_BCM1480_DUART_FULL_CTL_C 0x0010060440 +#define A_BCM1480_DUART_CMD_C 0x0010060450 +#define A_BCM1480_DUART_RX_HOLD_C 0x0010060460 +#define A_BCM1480_DUART_TX_HOLD_C 0x0010060470 +#define A_BCM1480_DUART_OPCR_C 0x0010060480 +#define A_BCM1480_DUART_AUX_CTRL_C 0x0010060490 + +#define A_BCM1480_DUART_MODE_REG_1_D 0x0010060500 +#define A_BCM1480_DUART_MODE_REG_2_D 0x0010060510 +#define A_BCM1480_DUART_STATUS_D 0x0010060520 +#define A_BCM1480_DUART_CLK_SEL_D 0x0010060530 +#define A_BCM1480_DUART_FULL_CTL_D 0x0010060540 +#define A_BCM1480_DUART_CMD_D 0x0010060550 +#define A_BCM1480_DUART_RX_HOLD_D 0x0010060560 +#define A_BCM1480_DUART_TX_HOLD_D 0x0010060570 +#define A_BCM1480_DUART_OPCR_D 0x0010060580 +#define A_BCM1480_DUART_AUX_CTRL_D 0x0010060590 + +#define A_BCM1480_DUART_INPORT_CHNG_CD 0x0010060600 +#define A_BCM1480_DUART_AUX_CTRL_CD 0x0010060610 +#define A_BCM1480_DUART_ISR_C 0x0010060620 +#define A_BCM1480_DUART_IMR_C 0x0010060630 +#define A_BCM1480_DUART_ISR_D 0x0010060640 +#define A_BCM1480_DUART_IMR_D 0x0010060650 +#define A_BCM1480_DUART_OUT_PORT_CD 0x0010060660 +#define A_BCM1480_DUART_OPCR_CD 0x0010060670 +#define A_BCM1480_DUART_IN_PORT_CD 0x0010060680 +#define A_BCM1480_DUART_ISR_CD 0x0010060690 +#define A_BCM1480_DUART_IMR_CD 0x00100606A0 +#define A_BCM1480_DUART_SET_OPR_CD 0x00100606B0 +#define A_BCM1480_DUART_CLEAR_OPR_CD 0x00100606C0 +#define A_BCM1480_DUART_INPORT_CHNG_C 0x00100606D0 +#define A_BCM1480_DUART_INPORT_CHNG_D 0x00100606E0 /* ********************************************************************* @@ -301,8 +301,8 @@ /* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */ -#define A_BCM1480_GPIO_INT_ADD_TYPE 0x0010061A78 -#define R_BCM1480_GPIO_INT_ADD_TYPE (-8) +#define A_BCM1480_GPIO_INT_ADD_TYPE 0x0010061A78 +#define R_BCM1480_GPIO_INT_ADD_TYPE (-8) #define A_GPIO_INT_ADD_TYPE A_BCM1480_GPIO_INT_ADD_TYPE #define R_GPIO_INT_ADD_TYPE R_BCM1480_GPIO_INT_ADD_TYPE @@ -321,30 +321,30 @@ /* Watchdog timers */ -#define A_BCM1480_SCD_WDOG_2 0x0010022050 -#define A_BCM1480_SCD_WDOG_3 0x0010022150 +#define A_BCM1480_SCD_WDOG_2 0x0010022050 +#define A_BCM1480_SCD_WDOG_3 0x0010022150 -#define BCM1480_SCD_NUM_WDOGS 4 +#define BCM1480_SCD_NUM_WDOGS 4 -#define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100) +#define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100) #define A_BCM1480_SCD_WDOG_REGISTER(w, r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) -#define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050 -#define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058 -#define A_BCM1480_SCD_WDOG_CFG_2 0x0010022060 +#define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050 +#define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058 +#define A_BCM1480_SCD_WDOG_CFG_2 0x0010022060 -#define A_BCM1480_SCD_WDOG_INIT_3 0x0010022150 -#define A_BCM1480_SCD_WDOG_CNT_3 0x0010022158 -#define A_BCM1480_SCD_WDOG_CFG_3 0x0010022160 +#define A_BCM1480_SCD_WDOG_INIT_3 0x0010022150 +#define A_BCM1480_SCD_WDOG_CNT_3 0x0010022158 +#define A_BCM1480_SCD_WDOG_CFG_3 0x0010022160 /* BCM1480 has two additional compare registers */ #define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT A_SCD_ZBBUS_CYCLE_COUNT -#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE 0x0010020C00 -#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0 A_SCD_ZBBUS_CYCLE_CP0 -#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1 A_SCD_ZBBUS_CYCLE_CP1 -#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2 0x0010020C10 -#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3 0x0010020C18 +#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE 0x0010020C00 +#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0 A_SCD_ZBBUS_CYCLE_CP0 +#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1 A_SCD_ZBBUS_CYCLE_CP1 +#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2 0x0010020C10 +#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3 0x0010020C18 /* ********************************************************************* * System Control Registers (Section 4.2) @@ -352,7 +352,7 @@ /* Scratch register in different place */ -#define A_BCM1480_SCD_SCRATCH 0x100200A0 +#define A_BCM1480_SCD_SCRATCH 0x100200A0 /* ********************************************************************* * System Address Trap Registers (Section 4.9) @@ -364,68 +364,68 @@ * System Interrupt Mapper Registers (Sections 4.3-4.5) ********************************************************************* */ -#define A_BCM1480_IMR_CPU0_BASE 0x0010020000 -#define A_BCM1480_IMR_CPU1_BASE 0x0010022000 -#define A_BCM1480_IMR_CPU2_BASE 0x0010024000 -#define A_BCM1480_IMR_CPU3_BASE 0x0010026000 -#define BCM1480_IMR_REGISTER_SPACING 0x2000 +#define A_BCM1480_IMR_CPU0_BASE 0x0010020000 +#define A_BCM1480_IMR_CPU1_BASE 0x0010022000 +#define A_BCM1480_IMR_CPU2_BASE 0x0010024000 +#define A_BCM1480_IMR_CPU3_BASE 0x0010026000 +#define BCM1480_IMR_REGISTER_SPACING 0x2000 #define BCM1480_IMR_REGISTER_SPACING_SHIFT 13 -#define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING) +#define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING) #define A_BCM1480_IMR_REGISTER(cpu, reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) /* Most IMR registers are 128 bits, implemented as non-contiguous 64-bit registers high (_H) and low (_L) */ -#define BCM1480_IMR_HL_SPACING 0x1000 +#define BCM1480_IMR_HL_SPACING 0x1000 -#define R_BCM1480_IMR_INTERRUPT_DIAG_H 0x0010 -#define R_BCM1480_IMR_LDT_INTERRUPT_H 0x0018 -#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H 0x0020 -#define R_BCM1480_IMR_INTERRUPT_MASK_H 0x0028 -#define R_BCM1480_IMR_INTERRUPT_TRACE_H 0x0038 +#define R_BCM1480_IMR_INTERRUPT_DIAG_H 0x0010 +#define R_BCM1480_IMR_LDT_INTERRUPT_H 0x0018 +#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H 0x0020 +#define R_BCM1480_IMR_INTERRUPT_MASK_H 0x0028 +#define R_BCM1480_IMR_INTERRUPT_TRACE_H 0x0038 #define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040 -#define R_BCM1480_IMR_LDT_INTERRUPT_SET 0x0048 -#define R_BCM1480_IMR_MAILBOX_0_CPU 0x00C0 -#define R_BCM1480_IMR_MAILBOX_0_SET_CPU 0x00C8 -#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU 0x00D0 -#define R_BCM1480_IMR_MAILBOX_1_CPU 0x00E0 -#define R_BCM1480_IMR_MAILBOX_1_SET_CPU 0x00E8 -#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU 0x00F0 -#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H 0x0100 -#define BCM1480_IMR_INTERRUPT_STATUS_COUNT 8 -#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H 0x0200 -#define BCM1480_IMR_INTERRUPT_MAP_COUNT 64 - -#define R_BCM1480_IMR_INTERRUPT_DIAG_L 0x1010 -#define R_BCM1480_IMR_LDT_INTERRUPT_L 0x1018 -#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L 0x1020 -#define R_BCM1480_IMR_INTERRUPT_MASK_L 0x1028 -#define R_BCM1480_IMR_INTERRUPT_TRACE_L 0x1038 +#define R_BCM1480_IMR_LDT_INTERRUPT_SET 0x0048 +#define R_BCM1480_IMR_MAILBOX_0_CPU 0x00C0 +#define R_BCM1480_IMR_MAILBOX_0_SET_CPU 0x00C8 +#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU 0x00D0 +#define R_BCM1480_IMR_MAILBOX_1_CPU 0x00E0 +#define R_BCM1480_IMR_MAILBOX_1_SET_CPU 0x00E8 +#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU 0x00F0 +#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H 0x0100 +#define BCM1480_IMR_INTERRUPT_STATUS_COUNT 8 +#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H 0x0200 +#define BCM1480_IMR_INTERRUPT_MAP_COUNT 64 + +#define R_BCM1480_IMR_INTERRUPT_DIAG_L 0x1010 +#define R_BCM1480_IMR_LDT_INTERRUPT_L 0x1018 +#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L 0x1020 +#define R_BCM1480_IMR_INTERRUPT_MASK_L 0x1028 +#define R_BCM1480_IMR_INTERRUPT_TRACE_L 0x1038 #define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040 -#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L 0x1100 -#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L 0x1200 +#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L 0x1100 +#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L 0x1200 -#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE 0x0010028000 -#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE 0x0010028100 -#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE 0x0010028200 -#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE 0x0010028300 -#define BCM1480_IMR_ALIAS_MAILBOX_SPACING 0100 +#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE 0x0010028000 +#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE 0x0010028100 +#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE 0x0010028200 +#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE 0x0010028300 +#define BCM1480_IMR_ALIAS_MAILBOX_SPACING 0100 #define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \ - (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING) + (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING) #define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu, reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) -#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ -#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ +#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ +#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ /* * these macros work together to build the address of a mailbox * register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2) * for mbox_0_set_cpu2 returns 0x00100240C8 */ -#define R_BCM1480_IMR_MAILBOX_CPU 0x00 -#define R_BCM1480_IMR_MAILBOX_SET 0x08 -#define R_BCM1480_IMR_MAILBOX_CLR 0x10 +#define R_BCM1480_IMR_MAILBOX_CPU 0x00 +#define R_BCM1480_IMR_MAILBOX_SET 0x08 +#define R_BCM1480_IMR_MAILBOX_CLR 0x10 #define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20 #define A_BCM1480_MAILBOX_REGISTER(num, reg, cpu) \ (A_BCM1480_IMR_CPU0_BASE + \ @@ -440,22 +440,22 @@ /* BCM1480 has four more performance counter registers, and two control registers. */ -#define A_BCM1480_SCD_PERF_CNT_BASE 0x00100204C0 +#define A_BCM1480_SCD_PERF_CNT_BASE 0x00100204C0 -#define A_BCM1480_SCD_PERF_CNT_CFG0 0x00100204C0 -#define A_BCM1480_SCD_PERF_CNT_CFG_0 A_BCM1480_SCD_PERF_CNT_CFG0 -#define A_BCM1480_SCD_PERF_CNT_CFG1 0x00100204C8 -#define A_BCM1480_SCD_PERF_CNT_CFG_1 A_BCM1480_SCD_PERF_CNT_CFG1 +#define A_BCM1480_SCD_PERF_CNT_CFG0 0x00100204C0 +#define A_BCM1480_SCD_PERF_CNT_CFG_0 A_BCM1480_SCD_PERF_CNT_CFG0 +#define A_BCM1480_SCD_PERF_CNT_CFG1 0x00100204C8 +#define A_BCM1480_SCD_PERF_CNT_CFG_1 A_BCM1480_SCD_PERF_CNT_CFG1 -#define A_BCM1480_SCD_PERF_CNT_0 A_SCD_PERF_CNT_0 -#define A_BCM1480_SCD_PERF_CNT_1 A_SCD_PERF_CNT_1 -#define A_BCM1480_SCD_PERF_CNT_2 A_SCD_PERF_CNT_2 -#define A_BCM1480_SCD_PERF_CNT_3 A_SCD_PERF_CNT_3 +#define A_BCM1480_SCD_PERF_CNT_0 A_SCD_PERF_CNT_0 +#define A_BCM1480_SCD_PERF_CNT_1 A_SCD_PERF_CNT_1 +#define A_BCM1480_SCD_PERF_CNT_2 A_SCD_PERF_CNT_2 +#define A_BCM1480_SCD_PERF_CNT_3 A_SCD_PERF_CNT_3 -#define A_BCM1480_SCD_PERF_CNT_4 0x00100204F0 -#define A_BCM1480_SCD_PERF_CNT_5 0x00100204F8 -#define A_BCM1480_SCD_PERF_CNT_6 0x0010020500 -#define A_BCM1480_SCD_PERF_CNT_7 0x0010020508 +#define A_BCM1480_SCD_PERF_CNT_4 0x00100204F0 +#define A_BCM1480_SCD_PERF_CNT_5 0x00100204F8 +#define A_BCM1480_SCD_PERF_CNT_6 0x0010020500 +#define A_BCM1480_SCD_PERF_CNT_7 0x0010020508 #define BCM1480_SCD_NUM_PERF_CNT 8 #define BCM1480_SCD_PERF_CNT_SPACING 8 @@ -468,7 +468,7 @@ /* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */ -#define A_BCM1480_BUS_ERR_STATUS_DEBUG 0x00100208D8 +#define A_BCM1480_BUS_ERR_STATUS_DEBUG 0x00100208D8 /* ********************************************************************* * System Debug Controller Registers (Section 19) @@ -497,46 +497,46 @@ #define BCM1480_HT_PORT_SPACING 0x800 #define A_BCM1480_HT_PORT_HEADER(x) (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING)) -#define A_BCM1480_HT_PORT0_HEADER 0x00FE000000 -#define A_BCM1480_HT_PORT1_HEADER 0x00FE000800 -#define A_BCM1480_HT_PORT2_HEADER 0x00FE001000 -#define A_BCM1480_HT_TYPE00_HEADER 0x00FE002000 +#define A_BCM1480_HT_PORT0_HEADER 0x00FE000000 +#define A_BCM1480_HT_PORT1_HEADER 0x00FE000800 +#define A_BCM1480_HT_PORT2_HEADER 0x00FE001000 +#define A_BCM1480_HT_TYPE00_HEADER 0x00FE002000 /* ********************************************************************* * Node Controller Registers (Section 9) ********************************************************************* */ -#define A_BCM1480_NC_BASE 0x00DFBD0000 +#define A_BCM1480_NC_BASE 0x00DFBD0000 -#define A_BCM1480_NC_RLD_FIELD 0x00DFBD0000 -#define A_BCM1480_NC_RLD_TRIGGER 0x00DFBD0020 -#define A_BCM1480_NC_RLD_BAD_ERROR 0x00DFBD0040 -#define A_BCM1480_NC_RLD_COR_ERROR 0x00DFBD0060 -#define A_BCM1480_NC_RLD_ECC_STATUS 0x00DFBD0080 -#define A_BCM1480_NC_RLD_WAY_ENABLE 0x00DFBD00A0 -#define A_BCM1480_NC_RLD_RANDOM_LFSR 0x00DFBD00C0 +#define A_BCM1480_NC_RLD_FIELD 0x00DFBD0000 +#define A_BCM1480_NC_RLD_TRIGGER 0x00DFBD0020 +#define A_BCM1480_NC_RLD_BAD_ERROR 0x00DFBD0040 +#define A_BCM1480_NC_RLD_COR_ERROR 0x00DFBD0060 +#define A_BCM1480_NC_RLD_ECC_STATUS 0x00DFBD0080 +#define A_BCM1480_NC_RLD_WAY_ENABLE 0x00DFBD00A0 +#define A_BCM1480_NC_RLD_RANDOM_LFSR 0x00DFBD00C0 -#define A_BCM1480_NC_INTERRUPT_STATUS 0x00DFBD00E0 -#define A_BCM1480_NC_INTERRUPT_ENABLE 0x00DFBD0100 -#define A_BCM1480_NC_TIMEOUT_COUNTER 0x00DFBD0120 +#define A_BCM1480_NC_INTERRUPT_STATUS 0x00DFBD00E0 +#define A_BCM1480_NC_INTERRUPT_ENABLE 0x00DFBD0100 +#define A_BCM1480_NC_TIMEOUT_COUNTER 0x00DFBD0120 #define A_BCM1480_NC_TIMEOUT_COUNTER_SEL 0x00DFBD0140 -#define A_BCM1480_NC_CREDIT_STATUS_REG0 0x00DFBD0200 -#define A_BCM1480_NC_CREDIT_STATUS_REG1 0x00DFBD0220 -#define A_BCM1480_NC_CREDIT_STATUS_REG2 0x00DFBD0240 -#define A_BCM1480_NC_CREDIT_STATUS_REG3 0x00DFBD0260 -#define A_BCM1480_NC_CREDIT_STATUS_REG4 0x00DFBD0280 -#define A_BCM1480_NC_CREDIT_STATUS_REG5 0x00DFBD02A0 -#define A_BCM1480_NC_CREDIT_STATUS_REG6 0x00DFBD02C0 -#define A_BCM1480_NC_CREDIT_STATUS_REG7 0x00DFBD02E0 -#define A_BCM1480_NC_CREDIT_STATUS_REG8 0x00DFBD0300 -#define A_BCM1480_NC_CREDIT_STATUS_REG9 0x00DFBD0320 +#define A_BCM1480_NC_CREDIT_STATUS_REG0 0x00DFBD0200 +#define A_BCM1480_NC_CREDIT_STATUS_REG1 0x00DFBD0220 +#define A_BCM1480_NC_CREDIT_STATUS_REG2 0x00DFBD0240 +#define A_BCM1480_NC_CREDIT_STATUS_REG3 0x00DFBD0260 +#define A_BCM1480_NC_CREDIT_STATUS_REG4 0x00DFBD0280 +#define A_BCM1480_NC_CREDIT_STATUS_REG5 0x00DFBD02A0 +#define A_BCM1480_NC_CREDIT_STATUS_REG6 0x00DFBD02C0 +#define A_BCM1480_NC_CREDIT_STATUS_REG7 0x00DFBD02E0 +#define A_BCM1480_NC_CREDIT_STATUS_REG8 0x00DFBD0300 +#define A_BCM1480_NC_CREDIT_STATUS_REG9 0x00DFBD0320 #define A_BCM1480_NC_CREDIT_STATUS_REG10 0x00DFBE0000 #define A_BCM1480_NC_CREDIT_STATUS_REG11 0x00DFBE0020 #define A_BCM1480_NC_CREDIT_STATUS_REG12 0x00DFBE0040 -#define A_BCM1480_NC_SR_TIMEOUT_COUNTER 0x00DFBE0060 +#define A_BCM1480_NC_SR_TIMEOUT_COUNTER 0x00DFBE0060 #define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080 @@ -544,43 +544,43 @@ * H&R Block Configuration Registers (Section 12.4) ********************************************************************* */ -#define A_BCM1480_HR_BASE_0 0x00DF820000 -#define A_BCM1480_HR_BASE_1 0x00DF8A0000 -#define A_BCM1480_HR_BASE_2 0x00DF920000 -#define BCM1480_HR_REGISTER_SPACING 0x80000 +#define A_BCM1480_HR_BASE_0 0x00DF820000 +#define A_BCM1480_HR_BASE_1 0x00DF8A0000 +#define A_BCM1480_HR_BASE_2 0x00DF920000 +#define BCM1480_HR_REGISTER_SPACING 0x80000 -#define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING)) -#define A_BCM1480_HR_REGISTER(idx, reg) (A_BCM1480_HR_BASE(idx) + (reg)) +#define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING)) +#define A_BCM1480_HR_REGISTER(idx, reg) (A_BCM1480_HR_BASE(idx) + (reg)) -#define R_BCM1480_HR_CFG 0x0000000000 +#define R_BCM1480_HR_CFG 0x0000000000 #define R_BCM1480_HR_MAPPING 0x0000010010 -#define BCM1480_HR_RULE_SPACING 0x0000000010 -#define BCM1480_HR_NUM_RULES 16 -#define BCM1480_HR_OP_OFFSET 0x0000000100 -#define BCM1480_HR_TYPE_OFFSET 0x0000000108 -#define R_BCM1480_HR_RULE_OP(idx) (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) -#define R_BCM1480_HR_RULE_TYPE(idx) (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) +#define BCM1480_HR_RULE_SPACING 0x0000000010 +#define BCM1480_HR_NUM_RULES 16 +#define BCM1480_HR_OP_OFFSET 0x0000000100 +#define BCM1480_HR_TYPE_OFFSET 0x0000000108 +#define R_BCM1480_HR_RULE_OP(idx) (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) +#define R_BCM1480_HR_RULE_TYPE(idx) (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) -#define BCM1480_HR_LEAF_SPACING 0x0000000010 -#define BCM1480_HR_NUM_LEAVES 10 -#define BCM1480_HR_LEAF_OFFSET 0x0000000300 -#define R_BCM1480_HR_HA_LEAF0(idx) (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING)) +#define BCM1480_HR_LEAF_SPACING 0x0000000010 +#define BCM1480_HR_NUM_LEAVES 10 +#define BCM1480_HR_LEAF_OFFSET 0x0000000300 +#define R_BCM1480_HR_HA_LEAF0(idx) (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING)) -#define R_BCM1480_HR_EX_LEAF0 0x00000003A0 +#define R_BCM1480_HR_EX_LEAF0 0x00000003A0 -#define BCM1480_HR_PATH_SPACING 0x0000000010 -#define BCM1480_HR_NUM_PATHS 16 -#define BCM1480_HR_PATH_OFFSET 0x0000000600 -#define R_BCM1480_HR_PATH(idx) (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING)) +#define BCM1480_HR_PATH_SPACING 0x0000000010 +#define BCM1480_HR_NUM_PATHS 16 +#define BCM1480_HR_PATH_OFFSET 0x0000000600 +#define R_BCM1480_HR_PATH(idx) (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING)) -#define R_BCM1480_HR_PATH_DEFAULT 0x0000000700 +#define R_BCM1480_HR_PATH_DEFAULT 0x0000000700 -#define BCM1480_HR_ROUTE_SPACING 8 -#define BCM1480_HR_NUM_ROUTES 512 -#define BCM1480_HR_ROUTE_OFFSET 0x0000001000 -#define R_BCM1480_HR_RT_WORD(idx) (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING)) +#define BCM1480_HR_ROUTE_SPACING 8 +#define BCM1480_HR_NUM_ROUTES 512 +#define BCM1480_HR_ROUTE_OFFSET 0x0000001000 +#define R_BCM1480_HR_RT_WORD(idx) (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING)) /* checked to here - ehs */ @@ -588,55 +588,55 @@ * Packet Manager DMA Registers (Section 12.5) ********************************************************************* */ -#define A_BCM1480_PM_BASE 0x0010056000 +#define A_BCM1480_PM_BASE 0x0010056000 -#define A_BCM1480_PMI_LCL_0 0x0010058000 -#define A_BCM1480_PMO_LCL_0 0x001005C000 -#define A_BCM1480_PMI_OFFSET_0 (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE) -#define A_BCM1480_PMO_OFFSET_0 (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE) +#define A_BCM1480_PMI_LCL_0 0x0010058000 +#define A_BCM1480_PMO_LCL_0 0x001005C000 +#define A_BCM1480_PMI_OFFSET_0 (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE) +#define A_BCM1480_PMO_OFFSET_0 (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE) -#define BCM1480_PM_LCL_REGISTER_SPACING 0x100 -#define BCM1480_PM_NUM_CHANNELS 32 +#define BCM1480_PM_LCL_REGISTER_SPACING 0x100 +#define BCM1480_PM_NUM_CHANNELS 32 -#define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) -#define A_BCM1480_PMI_LCL_REGISTER(idx, reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) -#define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) -#define A_BCM1480_PMO_LCL_REGISTER(idx, reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) +#define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) +#define A_BCM1480_PMI_LCL_REGISTER(idx, reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) +#define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) +#define A_BCM1480_PMO_LCL_REGISTER(idx, reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) -#define BCM1480_PM_INT_PACKING 8 -#define BCM1480_PM_INT_FUNCTION_SPACING 0x40 -#define BCM1480_PM_INT_NUM_FUNCTIONS 3 +#define BCM1480_PM_INT_PACKING 8 +#define BCM1480_PM_INT_FUNCTION_SPACING 0x40 +#define BCM1480_PM_INT_NUM_FUNCTIONS 3 /* * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n) */ -#define R_BCM1480_PM_BASE_SIZE 0x0000000000 -#define R_BCM1480_PM_CNT 0x0000000008 -#define R_BCM1480_PM_PFCNT 0x0000000010 -#define R_BCM1480_PM_LAST 0x0000000018 -#define R_BCM1480_PM_PFINDX 0x0000000020 -#define R_BCM1480_PM_INT_WMK 0x0000000028 -#define R_BCM1480_PM_CONFIG0 0x0000000030 -#define R_BCM1480_PM_LOCALDEBUG 0x0000000078 -#define R_BCM1480_PM_CACHEABILITY 0x0000000080 /* PMI only */ -#define R_BCM1480_PM_INT_CNFG 0x0000000088 -#define R_BCM1480_PM_DESC_MERGE_TIMER 0x0000000090 -#define R_BCM1480_PM_LOCALDEBUG_PIB 0x00000000F8 /* PMI only */ -#define R_BCM1480_PM_LOCALDEBUG_POB 0x00000000F8 /* PMO only */ +#define R_BCM1480_PM_BASE_SIZE 0x0000000000 +#define R_BCM1480_PM_CNT 0x0000000008 +#define R_BCM1480_PM_PFCNT 0x0000000010 +#define R_BCM1480_PM_LAST 0x0000000018 +#define R_BCM1480_PM_PFINDX 0x0000000020 +#define R_BCM1480_PM_INT_WMK 0x0000000028 +#define R_BCM1480_PM_CONFIG0 0x0000000030 +#define R_BCM1480_PM_LOCALDEBUG 0x0000000078 +#define R_BCM1480_PM_CACHEABILITY 0x0000000080 /* PMI only */ +#define R_BCM1480_PM_INT_CNFG 0x0000000088 +#define R_BCM1480_PM_DESC_MERGE_TIMER 0x0000000090 +#define R_BCM1480_PM_LOCALDEBUG_PIB 0x00000000F8 /* PMI only */ +#define R_BCM1480_PM_LOCALDEBUG_POB 0x00000000F8 /* PMO only */ /* * Global Registers (Not Channelized) */ -#define A_BCM1480_PMI_GLB_0 0x0010056000 -#define A_BCM1480_PMO_GLB_0 0x0010057000 +#define A_BCM1480_PMI_GLB_0 0x0010056000 +#define A_BCM1480_PMO_GLB_0 0x0010057000 /* * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0 */ -#define R_BCM1480_PM_PMO_MAPPING 0x00000008C8 /* PMO only */ +#define R_BCM1480_PM_PMO_MAPPING 0x00000008C8 /* PMO only */ #define A_BCM1480_PM_PMO_MAPPING (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING) @@ -645,32 +645,32 @@ */ -#define A_BCM1480_PMI_INT_0 0x0010056800 -#define A_BCM1480_PMI_INT(q) (A_BCM1480_PMI_INT_0 + ((q>>8)<<8)) -#define A_BCM1480_PMI_INT_OFFSET_0 (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE) -#define A_BCM1480_PMO_INT_0 0x0010057800 -#define A_BCM1480_PMO_INT(q) (A_BCM1480_PMO_INT_0 + ((q>>8)<<8)) -#define A_BCM1480_PMO_INT_OFFSET_0 (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE) +#define A_BCM1480_PMI_INT_0 0x0010056800 +#define A_BCM1480_PMI_INT(q) (A_BCM1480_PMI_INT_0 + ((q>>8)<<8)) +#define A_BCM1480_PMI_INT_OFFSET_0 (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE) +#define A_BCM1480_PMO_INT_0 0x0010057800 +#define A_BCM1480_PMO_INT(q) (A_BCM1480_PMO_INT_0 + ((q>>8)<<8)) +#define A_BCM1480_PMO_INT_OFFSET_0 (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE) /* * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0 */ -#define R_BCM1480_PM_INT_ST 0x0000000000 -#define R_BCM1480_PM_INT_MSK 0x0000000040 -#define R_BCM1480_PM_INT_CLR 0x0000000080 -#define R_BCM1480_PM_MRGD_INT 0x00000000C0 +#define R_BCM1480_PM_INT_ST 0x0000000000 +#define R_BCM1480_PM_INT_MSK 0x0000000040 +#define R_BCM1480_PM_INT_CLR 0x0000000080 +#define R_BCM1480_PM_MRGD_INT 0x00000000C0 /* * Debug registers (global) */ #define A_BCM1480_PM_GLOBALDEBUGMODE_PMI 0x0010056000 -#define A_BCM1480_PM_GLOBALDEBUG_PID 0x00100567F8 -#define A_BCM1480_PM_GLOBALDEBUG_PIB 0x0010056FF8 +#define A_BCM1480_PM_GLOBALDEBUG_PID 0x00100567F8 +#define A_BCM1480_PM_GLOBALDEBUG_PIB 0x0010056FF8 #define A_BCM1480_PM_GLOBALDEBUGMODE_PMO 0x0010057000 -#define A_BCM1480_PM_GLOBALDEBUG_POD 0x00100577F8 -#define A_BCM1480_PM_GLOBALDEBUG_POB 0x0010057FF8 +#define A_BCM1480_PM_GLOBALDEBUG_POD 0x00100577F8 +#define A_BCM1480_PM_GLOBALDEBUG_POB 0x0010057FF8 /* ********************************************************************* * Switch performance counters @@ -715,16 +715,16 @@ * High-Speed Port Registers (Section 13) ********************************************************************* */ -#define A_BCM1480_HSP_BASE_0 0x00DF810000 -#define A_BCM1480_HSP_BASE_1 0x00DF890000 -#define A_BCM1480_HSP_BASE_2 0x00DF910000 -#define BCM1480_HSP_REGISTER_SPACING 0x80000 +#define A_BCM1480_HSP_BASE_0 0x00DF810000 +#define A_BCM1480_HSP_BASE_1 0x00DF890000 +#define A_BCM1480_HSP_BASE_2 0x00DF910000 +#define BCM1480_HSP_REGISTER_SPACING 0x80000 -#define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING)) +#define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING)) #define A_BCM1480_HSP_REGISTER(idx, reg) (A_BCM1480_HSP_BASE(idx) + (reg)) -#define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000 -#define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008 +#define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000 +#define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008 #define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010 #define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018 #define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN 0x0000000020 @@ -733,34 +733,34 @@ #define R_BCM1480_HSP_RX_SPI4_CALENDAR_0 0x0000000200 #define R_BCM1480_HSP_RX_SPI4_CALENDAR_1 0x0000000208 -#define R_BCM1480_HSP_RX_PLL_CNFG 0x0000000800 -#define R_BCM1480_HSP_RX_CALIBRATION 0x0000000808 -#define R_BCM1480_HSP_RX_TEST 0x0000000810 -#define R_BCM1480_HSP_RX_DIAG_DETAILS 0x0000000818 -#define R_BCM1480_HSP_RX_DIAG_CRC_0 0x0000000820 -#define R_BCM1480_HSP_RX_DIAG_CRC_1 0x0000000828 -#define R_BCM1480_HSP_RX_DIAG_HTCMD 0x0000000830 -#define R_BCM1480_HSP_RX_DIAG_PKTCTL 0x0000000838 +#define R_BCM1480_HSP_RX_PLL_CNFG 0x0000000800 +#define R_BCM1480_HSP_RX_CALIBRATION 0x0000000808 +#define R_BCM1480_HSP_RX_TEST 0x0000000810 +#define R_BCM1480_HSP_RX_DIAG_DETAILS 0x0000000818 +#define R_BCM1480_HSP_RX_DIAG_CRC_0 0x0000000820 +#define R_BCM1480_HSP_RX_DIAG_CRC_1 0x0000000828 +#define R_BCM1480_HSP_RX_DIAG_HTCMD 0x0000000830 +#define R_BCM1480_HSP_RX_DIAG_PKTCTL 0x0000000838 #define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER 0x0000000870 -#define R_BCM1480_HSP_RX_PKT_RAMALLOC_0 0x0000020020 -#define R_BCM1480_HSP_RX_PKT_RAMALLOC_1 0x0000020028 -#define R_BCM1480_HSP_RX_PKT_RAMALLOC_2 0x0000020030 -#define R_BCM1480_HSP_RX_PKT_RAMALLOC_3 0x0000020038 -#define R_BCM1480_HSP_RX_PKT_RAMALLOC_4 0x0000020040 -#define R_BCM1480_HSP_RX_PKT_RAMALLOC_5 0x0000020048 -#define R_BCM1480_HSP_RX_PKT_RAMALLOC_6 0x0000020050 -#define R_BCM1480_HSP_RX_PKT_RAMALLOC_7 0x0000020058 +#define R_BCM1480_HSP_RX_PKT_RAMALLOC_0 0x0000020020 +#define R_BCM1480_HSP_RX_PKT_RAMALLOC_1 0x0000020028 +#define R_BCM1480_HSP_RX_PKT_RAMALLOC_2 0x0000020030 +#define R_BCM1480_HSP_RX_PKT_RAMALLOC_3 0x0000020038 +#define R_BCM1480_HSP_RX_PKT_RAMALLOC_4 0x0000020040 +#define R_BCM1480_HSP_RX_PKT_RAMALLOC_5 0x0000020048 +#define R_BCM1480_HSP_RX_PKT_RAMALLOC_6 0x0000020050 +#define R_BCM1480_HSP_RX_PKT_RAMALLOC_7 0x0000020058 #define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx)) /* XXX Following registers were shuffled. Renamed/renumbered per errata. */ -#define R_BCM1480_HSP_RX_HT_RAMALLOC_0 0x0000020078 -#define R_BCM1480_HSP_RX_HT_RAMALLOC_1 0x0000020080 -#define R_BCM1480_HSP_RX_HT_RAMALLOC_2 0x0000020088 -#define R_BCM1480_HSP_RX_HT_RAMALLOC_3 0x0000020090 -#define R_BCM1480_HSP_RX_HT_RAMALLOC_4 0x0000020098 -#define R_BCM1480_HSP_RX_HT_RAMALLOC_5 0x00000200A0 +#define R_BCM1480_HSP_RX_HT_RAMALLOC_0 0x0000020078 +#define R_BCM1480_HSP_RX_HT_RAMALLOC_1 0x0000020080 +#define R_BCM1480_HSP_RX_HT_RAMALLOC_2 0x0000020088 +#define R_BCM1480_HSP_RX_HT_RAMALLOC_3 0x0000020090 +#define R_BCM1480_HSP_RX_HT_RAMALLOC_4 0x0000020098 +#define R_BCM1480_HSP_RX_HT_RAMALLOC_5 0x00000200A0 #define R_BCM1480_HSP_RX_SPI_WATERMARK_0 0x00000200B0 #define R_BCM1480_HSP_RX_SPI_WATERMARK_1 0x00000200B8 @@ -772,30 +772,30 @@ #define R_BCM1480_HSP_RX_SPI_WATERMARK_7 0x00000200E8 #define R_BCM1480_HSP_RX_SPI_WATERMARK(idx) (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx)) -#define R_BCM1480_HSP_RX_VIS_CMDQ_0 0x00000200F0 -#define R_BCM1480_HSP_RX_VIS_CMDQ_1 0x00000200F8 -#define R_BCM1480_HSP_RX_VIS_CMDQ_2 0x0000020100 -#define R_BCM1480_HSP_RX_RAM_READCTL 0x0000020108 -#define R_BCM1480_HSP_RX_RAM_READWINDOW 0x0000020110 -#define R_BCM1480_HSP_RX_RF_READCTL 0x0000020118 -#define R_BCM1480_HSP_RX_RF_READWINDOW 0x0000020120 +#define R_BCM1480_HSP_RX_VIS_CMDQ_0 0x00000200F0 +#define R_BCM1480_HSP_RX_VIS_CMDQ_1 0x00000200F8 +#define R_BCM1480_HSP_RX_VIS_CMDQ_2 0x0000020100 +#define R_BCM1480_HSP_RX_RAM_READCTL 0x0000020108 +#define R_BCM1480_HSP_RX_RAM_READWINDOW 0x0000020110 +#define R_BCM1480_HSP_RX_RF_READCTL 0x0000020118 +#define R_BCM1480_HSP_RX_RF_READWINDOW 0x0000020120 -#define R_BCM1480_HSP_TX_SPI4_CFG_0 0x0000040000 -#define R_BCM1480_HSP_TX_SPI4_CFG_1 0x0000040008 +#define R_BCM1480_HSP_TX_SPI4_CFG_0 0x0000040000 +#define R_BCM1480_HSP_TX_SPI4_CFG_1 0x0000040008 #define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT 0x0000040010 -#define R_BCM1480_HSP_TX_PKT_RAMALLOC_0 0x0000040020 -#define R_BCM1480_HSP_TX_PKT_RAMALLOC_1 0x0000040028 -#define R_BCM1480_HSP_TX_PKT_RAMALLOC_2 0x0000040030 -#define R_BCM1480_HSP_TX_PKT_RAMALLOC_3 0x0000040038 -#define R_BCM1480_HSP_TX_PKT_RAMALLOC_4 0x0000040040 -#define R_BCM1480_HSP_TX_PKT_RAMALLOC_5 0x0000040048 -#define R_BCM1480_HSP_TX_PKT_RAMALLOC_6 0x0000040050 -#define R_BCM1480_HSP_TX_PKT_RAMALLOC_7 0x0000040058 +#define R_BCM1480_HSP_TX_PKT_RAMALLOC_0 0x0000040020 +#define R_BCM1480_HSP_TX_PKT_RAMALLOC_1 0x0000040028 +#define R_BCM1480_HSP_TX_PKT_RAMALLOC_2 0x0000040030 +#define R_BCM1480_HSP_TX_PKT_RAMALLOC_3 0x0000040038 +#define R_BCM1480_HSP_TX_PKT_RAMALLOC_4 0x0000040040 +#define R_BCM1480_HSP_TX_PKT_RAMALLOC_5 0x0000040048 +#define R_BCM1480_HSP_TX_PKT_RAMALLOC_6 0x0000040050 +#define R_BCM1480_HSP_TX_PKT_RAMALLOC_7 0x0000040058 #define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx)) -#define R_BCM1480_HSP_TX_NPC_RAMALLOC 0x0000040078 -#define R_BCM1480_HSP_TX_RSP_RAMALLOC 0x0000040080 -#define R_BCM1480_HSP_TX_PC_RAMALLOC 0x0000040088 +#define R_BCM1480_HSP_TX_NPC_RAMALLOC 0x0000040078 +#define R_BCM1480_HSP_TX_RSP_RAMALLOC 0x0000040080 +#define R_BCM1480_HSP_TX_PC_RAMALLOC 0x0000040088 #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0 0x0000040090 #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1 0x0000040098 #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2 0x00000400A0 @@ -805,37 +805,37 @@ #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2 0x00000400C0 #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3 0x00000400C8 #define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx)) -#define R_BCM1480_HSP_TX_HTIO_RXPHITCNT 0x00000400D0 -#define R_BCM1480_HSP_TX_HTCC_RXPHITCNT 0x00000400D8 +#define R_BCM1480_HSP_TX_HTIO_RXPHITCNT 0x00000400D0 +#define R_BCM1480_HSP_TX_HTCC_RXPHITCNT 0x00000400D8 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 0x00000400E0 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1 0x00000400E8 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2 0x00000400F0 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3 0x00000400F8 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx)) -#define R_BCM1480_HSP_TX_HTIO_TXPHITCNT 0x0000040100 -#define R_BCM1480_HSP_TX_HTCC_TXPHITCNT 0x0000040108 +#define R_BCM1480_HSP_TX_HTIO_TXPHITCNT 0x0000040100 +#define R_BCM1480_HSP_TX_HTCC_TXPHITCNT 0x0000040108 #define R_BCM1480_HSP_TX_SPI4_CALENDAR_0 0x0000040200 #define R_BCM1480_HSP_TX_SPI4_CALENDAR_1 0x0000040208 -#define R_BCM1480_HSP_TX_PLL_CNFG 0x0000040800 -#define R_BCM1480_HSP_TX_CALIBRATION 0x0000040808 -#define R_BCM1480_HSP_TX_TEST 0x0000040810 +#define R_BCM1480_HSP_TX_PLL_CNFG 0x0000040800 +#define R_BCM1480_HSP_TX_CALIBRATION 0x0000040808 +#define R_BCM1480_HSP_TX_TEST 0x0000040810 -#define R_BCM1480_HSP_TX_VIS_CMDQ_0 0x0000040840 -#define R_BCM1480_HSP_TX_VIS_CMDQ_1 0x0000040848 -#define R_BCM1480_HSP_TX_VIS_CMDQ_2 0x0000040850 -#define R_BCM1480_HSP_TX_RAM_READCTL 0x0000040860 -#define R_BCM1480_HSP_TX_RAM_READWINDOW 0x0000040868 -#define R_BCM1480_HSP_TX_RF_READCTL 0x0000040870 -#define R_BCM1480_HSP_TX_RF_READWINDOW 0x0000040878 +#define R_BCM1480_HSP_TX_VIS_CMDQ_0 0x0000040840 +#define R_BCM1480_HSP_TX_VIS_CMDQ_1 0x0000040848 +#define R_BCM1480_HSP_TX_VIS_CMDQ_2 0x0000040850 +#define R_BCM1480_HSP_TX_RAM_READCTL 0x0000040860 +#define R_BCM1480_HSP_TX_RAM_READWINDOW 0x0000040868 +#define R_BCM1480_HSP_TX_RF_READCTL 0x0000040870 +#define R_BCM1480_HSP_TX_RF_READWINDOW 0x0000040878 #define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880 #define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN 0x0000040888 #define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400 -#define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x) (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x)) +#define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x) (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x)) @@ -843,60 +843,60 @@ * Physical Address Map (Table 10 and Figure 7) ********************************************************************* */ -#define A_BCM1480_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) -#define A_BCM1480_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) -#define A_BCM1480_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) -#define A_BCM1480_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) -#define A_BCM1480_PHYS_GENBUS _SB_MAKE64(0x0010090000) -#define A_BCM1480_PHYS_GENBUS_END _SB_MAKE64(0x0028000000) -#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES _SB_MAKE64(0x0028000000) -#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES _SB_MAKE64(0x0029000000) -#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES _SB_MAKE64(0x002C000000) -#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES _SB_MAKE64(0x002E000000) -#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES _SB_MAKE64(0x002F000000) -#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES _SB_MAKE64(0x0030000000) -#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES _SB_MAKE64(0x0040000000) -#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS _SB_MAKE64(0x0060000000) -#define A_BCM1480_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) -#define A_BCM1480_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) -#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS _SB_MAKE64(0x00A8000000) -#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS _SB_MAKE64(0x00A9000000) -#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS _SB_MAKE64(0x00AC000000) -#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS _SB_MAKE64(0x00AE000000) -#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS _SB_MAKE64(0x00AF000000) -#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS _SB_MAKE64(0x00B0000000) -#define A_BCM1480_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) -#define A_BCM1480_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) -#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) -#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) -#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) -#define A_BCM1480_PHYS_HS_SUBSYS _SB_MAKE64(0x00DF000000) -#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) -#define A_BCM1480_PHYS_HT_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) -#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) -#define A_BCM1480_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) -#define A_BCM1480_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) -#define A_BCM1480_PHYS_PCI_UPPER _SB_MAKE64(0x1000000000) -#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES _SB_MAKE64(0x2000000000) -#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS _SB_MAKE64(0x3000000000) -#define A_BCM1480_PHYS_HT_NODE_ALIAS _SB_MAKE64(0x4000000000) -#define A_BCM1480_PHYS_HT_FULLACCESS _SB_MAKE64(0xF000000000) +#define A_BCM1480_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) +#define A_BCM1480_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) +#define A_BCM1480_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) +#define A_BCM1480_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) +#define A_BCM1480_PHYS_GENBUS _SB_MAKE64(0x0010090000) +#define A_BCM1480_PHYS_GENBUS_END _SB_MAKE64(0x0028000000) +#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES _SB_MAKE64(0x0028000000) +#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES _SB_MAKE64(0x0029000000) +#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES _SB_MAKE64(0x002C000000) +#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES _SB_MAKE64(0x002E000000) +#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES _SB_MAKE64(0x002F000000) +#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES _SB_MAKE64(0x0030000000) +#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES _SB_MAKE64(0x0040000000) +#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS _SB_MAKE64(0x0060000000) +#define A_BCM1480_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) +#define A_BCM1480_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) +#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS _SB_MAKE64(0x00A8000000) +#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS _SB_MAKE64(0x00A9000000) +#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS _SB_MAKE64(0x00AC000000) +#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS _SB_MAKE64(0x00AE000000) +#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS _SB_MAKE64(0x00AF000000) +#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS _SB_MAKE64(0x00B0000000) +#define A_BCM1480_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) +#define A_BCM1480_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) +#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) +#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) +#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) +#define A_BCM1480_PHYS_HS_SUBSYS _SB_MAKE64(0x00DF000000) +#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) +#define A_BCM1480_PHYS_HT_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) +#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) +#define A_BCM1480_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) +#define A_BCM1480_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) +#define A_BCM1480_PHYS_PCI_UPPER _SB_MAKE64(0x1000000000) +#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES _SB_MAKE64(0x2000000000) +#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS _SB_MAKE64(0x3000000000) +#define A_BCM1480_PHYS_HT_NODE_ALIAS _SB_MAKE64(0x4000000000) +#define A_BCM1480_PHYS_HT_FULLACCESS _SB_MAKE64(0xF000000000) /* ********************************************************************* * L2 Cache as RAM (Table 54) ********************************************************************* */ -#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) -#define BCM1480_PHYS_L2CACHE_NUM_WAYS 8 -#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000100000) -#define A_BCM1480_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0300000) -#define A_BCM1480_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D0320000) -#define A_BCM1480_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D0340000) -#define A_BCM1480_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D0360000) -#define A_BCM1480_PHYS_L2CACHE_WAY4 _SB_MAKE64(0x00D0380000) -#define A_BCM1480_PHYS_L2CACHE_WAY5 _SB_MAKE64(0x00D03A0000) -#define A_BCM1480_PHYS_L2CACHE_WAY6 _SB_MAKE64(0x00D03C0000) -#define A_BCM1480_PHYS_L2CACHE_WAY7 _SB_MAKE64(0x00D03E0000) +#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) +#define BCM1480_PHYS_L2CACHE_NUM_WAYS 8 +#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000100000) +#define A_BCM1480_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0300000) +#define A_BCM1480_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D0320000) +#define A_BCM1480_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D0340000) +#define A_BCM1480_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D0360000) +#define A_BCM1480_PHYS_L2CACHE_WAY4 _SB_MAKE64(0x00D0380000) +#define A_BCM1480_PHYS_L2CACHE_WAY5 _SB_MAKE64(0x00D03A0000) +#define A_BCM1480_PHYS_L2CACHE_WAY6 _SB_MAKE64(0x00D03C0000) +#define A_BCM1480_PHYS_L2CACHE_WAY7 _SB_MAKE64(0x00D03E0000) #endif /* _BCM1480_REGS_H */ diff --git a/arch/mips/include/asm/sibyte/bcm1480_scd.h b/arch/mips/include/asm/sibyte/bcm1480_scd.h index 2af3706b964..8a1e2b05a62 100644 --- a/arch/mips/include/asm/sibyte/bcm1480_scd.h +++ b/arch/mips/include/asm/sibyte/bcm1480_scd.h @@ -1,7 +1,7 @@ /* ********************************************************************* * BCM1280/BCM1400 Board Support Package * - * SCD Constants and Macros File: bcm1480_scd.h + * SCD Constants and Macros File: bcm1480_scd.h * * This module contains constants and macros useful for * manipulating the System Control and Debug module. @@ -74,11 +74,11 @@ * New part definitions */ -#define K_SYS_PART_BCM1480 0x1406 -#define K_SYS_PART_BCM1280 0x1206 -#define K_SYS_PART_BCM1455 0x1407 -#define K_SYS_PART_BCM1255 0x1257 -#define K_SYS_PART_BCM1158 0x1156 +#define K_SYS_PART_BCM1480 0x1406 +#define K_SYS_PART_BCM1280 0x1206 +#define K_SYS_PART_BCM1455 0x1407 +#define K_SYS_PART_BCM1255 0x1257 +#define K_SYS_PART_BCM1158 0x1156 /* * Manufacturing Information Register (Table 14) @@ -91,73 +91,73 @@ * Entire register is different from 1250, all new constants below */ -#define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0) -#define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1) -#define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2) -#define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3) -#define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4) -#define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) - -#define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) -#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV) -#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV) -#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV) - -#define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) -#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV) -#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV) -#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV) - -#define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) -#define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) - -#define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) -#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE) -#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE) -#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE) -#define K_BCM1480_SYS_BOOT_MODE_ROM32 0 -#define K_BCM1480_SYS_BOOT_MODE_ROM8 1 +#define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0) +#define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1) +#define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2) +#define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3) +#define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4) +#define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) + +#define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) +#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV) +#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV) +#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV) + +#define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) +#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV) +#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV) +#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV) + +#define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) +#define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) + +#define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) +#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE) +#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE) +#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE) +#define K_BCM1480_SYS_BOOT_MODE_ROM32 0 +#define K_BCM1480_SYS_BOOT_MODE_ROM8 1 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG 3 -#define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19) - -#define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20) -#define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21) -#define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) -#define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23) -#define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24) -#define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) - -#define S_BCM1480_SYS_CONFIG 26 -#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG) -#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG) -#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG) - -#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15) - -#define S_BCM1480_SYS_NODEID 47 -#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID) -#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID) -#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID) - -#define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) -#define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) -#define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53) -#define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54) -#define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55) -#define S_BCM1480_SYS_DISABLECPU0 56 -#define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0) -#define S_BCM1480_SYS_DISABLECPU1 57 -#define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1) -#define S_BCM1480_SYS_DISABLECPU2 58 -#define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2) -#define S_BCM1480_SYS_DISABLECPU3 59 -#define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3) - -#define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60) -#define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61) -#define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62) -#define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63) +#define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19) + +#define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20) +#define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21) +#define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) +#define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23) +#define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24) +#define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) + +#define S_BCM1480_SYS_CONFIG 26 +#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG) +#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG) +#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG) + +#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15) + +#define S_BCM1480_SYS_NODEID 47 +#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID) +#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID) +#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID) + +#define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) +#define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) +#define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53) +#define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54) +#define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55) +#define S_BCM1480_SYS_DISABLECPU0 56 +#define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0) +#define S_BCM1480_SYS_DISABLECPU1 57 +#define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1) +#define S_BCM1480_SYS_DISABLECPU2 58 +#define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2) +#define S_BCM1480_SYS_DISABLECPU3 59 +#define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3) + +#define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60) +#define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61) +#define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62) +#define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63) /* * Scratch Register (Table 16) @@ -193,23 +193,23 @@ * Registers: SCD_WDOG_CFG_x */ -#define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) +#define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) -#define S_BCM1480_SCD_WDOG_RESET_TYPE 2 -#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE) +#define S_BCM1480_SCD_WDOG_RESET_TYPE 2 +#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE) #define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE) #define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE) -#define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ -#define K_BCM1480_SCD_WDOG_RESET_SOFT 1 -#define K_BCM1480_SCD_WDOG_RESET_CPU0 3 -#define K_BCM1480_SCD_WDOG_RESET_CPU1 5 -#define K_BCM1480_SCD_WDOG_RESET_CPU2 9 -#define K_BCM1480_SCD_WDOG_RESET_CPU3 17 +#define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ +#define K_BCM1480_SCD_WDOG_RESET_SOFT 1 +#define K_BCM1480_SCD_WDOG_RESET_CPU0 3 +#define K_BCM1480_SCD_WDOG_RESET_CPU1 5 +#define K_BCM1480_SCD_WDOG_RESET_CPU2 9 +#define K_BCM1480_SCD_WDOG_RESET_CPU3 17 #define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS 31 -#define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8) +#define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8) /* * General Timer Initial Count Registers (Table 26) @@ -243,32 +243,32 @@ * The clear/enable bits are in different locations on the 1250 and 1480. */ -#define S_SPC_CFG_SRC4 32 -#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4) -#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4) -#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4) +#define S_SPC_CFG_SRC4 32 +#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4) +#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4) +#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4) -#define S_SPC_CFG_SRC5 40 -#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5) -#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5) -#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5) +#define S_SPC_CFG_SRC5 40 +#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5) +#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5) +#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5) -#define S_SPC_CFG_SRC6 48 -#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6) -#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6) -#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6) +#define S_SPC_CFG_SRC6 48 +#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6) +#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6) +#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6) -#define S_SPC_CFG_SRC7 56 -#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7) -#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7) -#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7) +#define S_SPC_CFG_SRC7 56 +#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7) +#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7) +#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7) /* * System Performance Counter Control Register (Table 32) * Register: PERF_CNT_CFG_1 * BCM1480 specific */ -#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) +#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) #define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1) #if SIBYTE_HDR_FEATURE_CHIP(1480) #define M_SPC_CFG_CLEAR M_BCM1480_SPC_CFG_CLEAR @@ -280,12 +280,12 @@ * Registers: PERF_CNT_x */ -#define S_BCM1480_SPC_CNT_COUNT 0 -#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT) -#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT) -#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT) +#define S_BCM1480_SPC_CNT_COUNT 0 +#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT) +#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT) +#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT) -#define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) +#define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) /* @@ -325,45 +325,45 @@ #define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4, 0) #define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) -#define S_BCM1480_ATRAP_CFG_CNT 0 -#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT) -#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT) -#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT) +#define S_BCM1480_ATRAP_CFG_CNT 0 +#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT) +#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT) +#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT) #define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) -#define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) -#define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5) +#define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) +#define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5) #define M_BCM1480_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) #define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) -#define S_BCM1480_ATRAP_CFG_AGENTID 8 -#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID) -#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID) -#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID) +#define S_BCM1480_ATRAP_CFG_AGENTID 8 +#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID) +#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID) +#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID) -#define K_BCM1480_BUS_AGENT_CPU0 0 -#define K_BCM1480_BUS_AGENT_CPU1 1 -#define K_BCM1480_BUS_AGENT_NC 2 -#define K_BCM1480_BUS_AGENT_IOB 3 -#define K_BCM1480_BUS_AGENT_SCD 4 -#define K_BCM1480_BUS_AGENT_L2C 6 -#define K_BCM1480_BUS_AGENT_MC 7 -#define K_BCM1480_BUS_AGENT_CPU2 8 -#define K_BCM1480_BUS_AGENT_CPU3 9 -#define K_BCM1480_BUS_AGENT_PM 10 +#define K_BCM1480_BUS_AGENT_CPU0 0 +#define K_BCM1480_BUS_AGENT_CPU1 1 +#define K_BCM1480_BUS_AGENT_NC 2 +#define K_BCM1480_BUS_AGENT_IOB 3 +#define K_BCM1480_BUS_AGENT_SCD 4 +#define K_BCM1480_BUS_AGENT_L2C 6 +#define K_BCM1480_BUS_AGENT_MC 7 +#define K_BCM1480_BUS_AGENT_CPU2 8 +#define K_BCM1480_BUS_AGENT_CPU3 9 +#define K_BCM1480_BUS_AGENT_PM 10 -#define S_BCM1480_ATRAP_CFG_CATTR 12 -#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR) -#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR) -#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR) +#define S_BCM1480_ATRAP_CFG_CATTR 12 +#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR) +#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR) +#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR) #define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 -#define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 +#define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 #define K_BCM1480_ATRAP_CFG_CATTR_NONCOH 2 #define K_BCM1480_ATRAP_CFG_CATTR_COHERENT 3 -#define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14) +#define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14) /* @@ -381,10 +381,10 @@ #define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) -#define S_BCM1480_SCD_TRSEQ_SWFUNC 26 -#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC) -#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC) -#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC) +#define S_BCM1480_SCD_TRSEQ_SWFUNC 26 +#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC) +#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC) +#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC) /* * Trace Control Register (Table 49) @@ -394,13 +394,13 @@ * are defined below. */ -#define S_BCM1480_SCD_TRACE_CFG_MODE 16 -#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE) -#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE) -#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE) +#define S_BCM1480_SCD_TRACE_CFG_MODE 16 +#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE) +#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE) +#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE) #define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 -#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 +#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 #define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2 #endif /* _BCM1480_SCD_H */ diff --git a/arch/mips/include/asm/sibyte/bigsur.h b/arch/mips/include/asm/sibyte/bigsur.h index 2d1a26d3436..ae29dae4155 100644 --- a/arch/mips/include/asm/sibyte/bigsur.h +++ b/arch/mips/include/asm/sibyte/bigsur.h @@ -24,25 +24,25 @@ #ifdef CONFIG_SIBYTE_BIGSUR #define SIBYTE_BOARD_NAME "BCM91x80A/B (BigSur)" #define SIBYTE_HAVE_PCMCIA 1 -#define SIBYTE_HAVE_IDE 1 +#define SIBYTE_HAVE_IDE 1 #endif /* Generic bus chip selects */ -#define LEDS_CS 3 -#define LEDS_PHYS 0x100a0000 +#define LEDS_CS 3 +#define LEDS_PHYS 0x100a0000 #ifdef SIBYTE_HAVE_IDE -#define IDE_CS 4 -#define IDE_PHYS 0x100b0000 -#define K_GPIO_GB_IDE 4 -#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) +#define IDE_CS 4 +#define IDE_PHYS 0x100b0000 +#define K_GPIO_GB_IDE 4 +#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) #endif #ifdef SIBYTE_HAVE_PCMCIA -#define PCMCIA_CS 6 -#define PCMCIA_PHYS 0x11000000 +#define PCMCIA_CS 6 +#define PCMCIA_PHYS 0x11000000 #define K_GPIO_PC_READY 9 -#define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY) +#define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY) #endif #endif /* __ASM_SIBYTE_BIGSUR_H */ diff --git a/arch/mips/include/asm/sibyte/carmel.h b/arch/mips/include/asm/sibyte/carmel.h index 11cad71323e..793edba73aa 100644 --- a/arch/mips/include/asm/sibyte/carmel.h +++ b/arch/mips/include/asm/sibyte/carmel.h @@ -23,35 +23,35 @@ #define SIBYTE_BOARD_NAME "Carmel" -#define GPIO_PHY_INTERRUPT 2 -#define GPIO_NONMASKABLE_INT 3 -#define GPIO_CF_INSERTED 6 -#define GPIO_MONTEREY_RESET 7 -#define GPIO_QUADUART_INT 8 -#define GPIO_CF_INT 9 -#define GPIO_FPGA_CCLK 10 -#define GPIO_FPGA_DOUT 11 -#define GPIO_FPGA_DIN 12 -#define GPIO_FPGA_PGM 13 -#define GPIO_FPGA_DONE 14 -#define GPIO_FPGA_INIT 15 +#define GPIO_PHY_INTERRUPT 2 +#define GPIO_NONMASKABLE_INT 3 +#define GPIO_CF_INSERTED 6 +#define GPIO_MONTEREY_RESET 7 +#define GPIO_QUADUART_INT 8 +#define GPIO_CF_INT 9 +#define GPIO_FPGA_CCLK 10 +#define GPIO_FPGA_DOUT 11 +#define GPIO_FPGA_DIN 12 +#define GPIO_FPGA_PGM 13 +#define GPIO_FPGA_DONE 14 +#define GPIO_FPGA_INIT 15 -#define LEDS_CS 2 -#define LEDS_PHYS 0x100C0000 -#define MLEDS_CS 3 -#define MLEDS_PHYS 0x100A0000 -#define UART_CS 4 -#define UART_PHYS 0x100D0000 -#define ARAVALI_CS 5 -#define ARAVALI_PHYS 0x11000000 -#define IDE_CS 6 -#define IDE_PHYS 0x100B0000 -#define ARAVALI2_CS 7 -#define ARAVALI2_PHYS 0x100E0000 +#define LEDS_CS 2 +#define LEDS_PHYS 0x100C0000 +#define MLEDS_CS 3 +#define MLEDS_PHYS 0x100A0000 +#define UART_CS 4 +#define UART_PHYS 0x100D0000 +#define ARAVALI_CS 5 +#define ARAVALI_PHYS 0x11000000 +#define IDE_CS 6 +#define IDE_PHYS 0x100B0000 +#define ARAVALI2_CS 7 +#define ARAVALI2_PHYS 0x100E0000 #if defined(CONFIG_SIBYTE_CARMEL) -#define K_GPIO_GB_IDE 9 -#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) +#define K_GPIO_GB_IDE 9 +#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) #endif diff --git a/arch/mips/include/asm/sibyte/sb1250.h b/arch/mips/include/asm/sibyte/sb1250.h index 80c1a052662..d45dff9753d 100644 --- a/arch/mips/include/asm/sibyte/sb1250.h +++ b/arch/mips/include/asm/sibyte/sb1250.h @@ -27,8 +27,8 @@ #define SB1250_NR_IRQS 64 -#define BCM1480_NR_IRQS 128 -#define BCM1480_NR_IRQS_HALF 64 +#define BCM1480_NR_IRQS 128 +#define BCM1480_NR_IRQS_HALF 64 #define SB1250_DUART_MINOR_BASE 64 diff --git a/arch/mips/include/asm/sibyte/sb1250_defs.h b/arch/mips/include/asm/sibyte/sb1250_defs.h index 09365f9111f..4364eb8d22a 100644 --- a/arch/mips/include/asm/sibyte/sb1250_defs.h +++ b/arch/mips/include/asm/sibyte/sb1250_defs.h @@ -51,15 +51,15 @@ * * Use like: * - * #define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_112x_PASS1 + * #define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_112x_PASS1 * * Generate defines only for that revision of chip. * - * #if SIBYTE_HDR_FEATURE(chip,pass) + * #if SIBYTE_HDR_FEATURE(chip,pass) * * True if header features for that revision or later of - * that particular chip type are enabled in SIBYTE_HDR_FEATURES. - * (Use this to bracket #defines for features present in a given + * that particular chip type are enabled in SIBYTE_HDR_FEATURES. + * (Use this to bracket #defines for features present in a given * revision and later.) * * Note that there is no implied ordering between chip types. @@ -69,12 +69,12 @@ * SIBYTE_HDR_FEATURE(112x, PASS1) is OK, but * SIBYTE_HDR_FEATURE(1120, pass1) is not (for two reasons). * - * #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass) + * #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass) * * Same as SIBYTE_HDR_FEATURE, but true for the named revision * and earlier revisions of the named chip type. * - * #if SIBYTE_HDR_FEATURE_EXACT(chip,pass) + * #if SIBYTE_HDR_FEATURE_EXACT(chip,pass) * * Same as SIBYTE_HDR_FEATURE, but only true for the named * revision of the named chip type. (Note that this CANNOT @@ -82,7 +82,7 @@ * particular chip/revision. It will be true any time this * chip/revision is included in SIBYTE_HDR_FEATURES.) * - * #if SIBYTE_HDR_FEATURE_CHIP(chip) + * #if SIBYTE_HDR_FEATURE_CHIP(chip) * * True if header features for (any revision of) that chip type * are enabled in SIBYTE_HDR_FEATURES. (Use this to bracket @@ -95,47 +95,47 @@ * ordering, so be careful when adding support for new minor revs. ********************************************************************* */ -#define SIBYTE_HDR_FMASK_1250_ALL 0x000000ff -#define SIBYTE_HDR_FMASK_1250_PASS1 0x00000001 -#define SIBYTE_HDR_FMASK_1250_PASS2 0x00000002 -#define SIBYTE_HDR_FMASK_1250_PASS3 0x00000004 +#define SIBYTE_HDR_FMASK_1250_ALL 0x000000ff +#define SIBYTE_HDR_FMASK_1250_PASS1 0x00000001 +#define SIBYTE_HDR_FMASK_1250_PASS2 0x00000002 +#define SIBYTE_HDR_FMASK_1250_PASS3 0x00000004 -#define SIBYTE_HDR_FMASK_112x_ALL 0x00000f00 -#define SIBYTE_HDR_FMASK_112x_PASS1 0x00000100 +#define SIBYTE_HDR_FMASK_112x_ALL 0x00000f00 +#define SIBYTE_HDR_FMASK_112x_PASS1 0x00000100 #define SIBYTE_HDR_FMASK_1480_ALL 0x0000f000 #define SIBYTE_HDR_FMASK_1480_PASS1 0x00001000 #define SIBYTE_HDR_FMASK_1480_PASS2 0x00002000 -/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ -#define SIBYTE_HDR_FMASK(chip, pass) \ +/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ +#define SIBYTE_HDR_FMASK(chip, pass) \ (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass) -#define SIBYTE_HDR_FMASK_ALLREVS(chip) \ +#define SIBYTE_HDR_FMASK_ALLREVS(chip) \ (SIBYTE_HDR_FMASK_ ## chip ## _ALL) /* Default constant value for all chips, all revisions */ -#define SIBYTE_HDR_FMASK_ALL \ +#define SIBYTE_HDR_FMASK_ALL \ (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL \ | SIBYTE_HDR_FMASK_1480_ALL) /* This one is used for the "original" BCM1250/BCM112x chips. We use this to weed out constants and macros that do not exist on later chips like - the BCM1480 */ + the BCM1480 */ #define SIBYTE_HDR_FMASK_1250_112x_ALL \ (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL) #define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL #ifndef SIBYTE_HDR_FEATURES -#define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_ALL +#define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_ALL #endif /* Bit mask for revisions of chip exclusively before the named revision. */ -#define SIBYTE_HDR_FMASK_BEFORE(chip, pass) \ +#define SIBYTE_HDR_FMASK_BEFORE(chip, pass) \ ((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip)) -/* Bit mask for revisions of chip exclusively after the named revision. */ -#define SIBYTE_HDR_FMASK_AFTER(chip, pass) \ +/* Bit mask for revisions of chip exclusively after the named revision. */ +#define SIBYTE_HDR_FMASK_AFTER(chip, pass) \ (~(SIBYTE_HDR_FMASK(chip, pass) \ | (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip)) @@ -168,38 +168,38 @@ /* ********************************************************************* * Naming schemes for constants in these files: * - * M_xxx MASK constant (identifies bits in a register). - * For multi-bit fields, all bits in the field will - * be set. + * M_xxx MASK constant (identifies bits in a register). + * For multi-bit fields, all bits in the field will + * be set. * - * K_xxx "Code" constant (value for data in a multi-bit - * field). The value is right justified. + * K_xxx "Code" constant (value for data in a multi-bit + * field). The value is right justified. * - * V_xxx "Value" constant. This is the same as the - * corresponding "K_xxx" constant, except it is - * shifted to the correct position in the register. + * V_xxx "Value" constant. This is the same as the + * corresponding "K_xxx" constant, except it is + * shifted to the correct position in the register. * - * S_xxx SHIFT constant. This is the number of bits that - * a field value (code) needs to be shifted - * (towards the left) to put the value in the right - * position for the register. + * S_xxx SHIFT constant. This is the number of bits that + * a field value (code) needs to be shifted + * (towards the left) to put the value in the right + * position for the register. * - * A_xxx ADDRESS constant. This will be a physical - * address. Use the PHYS_TO_K1 macro to generate - * a K1SEG address. + * A_xxx ADDRESS constant. This will be a physical + * address. Use the PHYS_TO_K1 macro to generate + * a K1SEG address. * - * R_xxx RELATIVE offset constant. This is an offset from - * an A_xxx constant (usually the first register in - * a group). + * R_xxx RELATIVE offset constant. This is an offset from + * an A_xxx constant (usually the first register in + * a group). * - * G_xxx(X) GET value. This macro obtains a multi-bit field - * from a register, masks it, and shifts it to - * the bottom of the register (retrieving a K_xxx - * value, for example). + * G_xxx(X) GET value. This macro obtains a multi-bit field + * from a register, masks it, and shifts it to + * the bottom of the register (retrieving a K_xxx + * value, for example). * - * V_xxx(X) VALUE. This macro computes the value of a - * K_xxx constant shifted to the correct position - * in the register. + * V_xxx(X) VALUE. This macro computes the value of a + * K_xxx constant shifted to the correct position + * in the register. ********************************************************************* */ diff --git a/arch/mips/include/asm/sibyte/sb1250_dma.h b/arch/mips/include/asm/sibyte/sb1250_dma.h index 6c44dfb5287..ea81713b78d 100644 --- a/arch/mips/include/asm/sibyte/sb1250_dma.h +++ b/arch/mips/include/asm/sibyte/sb1250_dma.h @@ -51,15 +51,15 @@ */ -#define M_DMA_DROP _SB_MAKEMASK1(0) +#define M_DMA_DROP _SB_MAKEMASK1(0) -#define M_DMA_CHAIN_SEL _SB_MAKEMASK1(1) -#define M_DMA_RESERVED1 _SB_MAKEMASK1(2) +#define M_DMA_CHAIN_SEL _SB_MAKEMASK1(1) +#define M_DMA_RESERVED1 _SB_MAKEMASK1(2) #define S_DMA_DESC_TYPE _SB_MAKE64(1) #define M_DMA_DESC_TYPE _SB_MAKEMASK(2, S_DMA_DESC_TYPE) -#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x, S_DMA_DESC_TYPE) -#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE) +#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x, S_DMA_DESC_TYPE) +#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE) #define K_DMA_DESC_TYPE_RING_AL 0 #define K_DMA_DESC_TYPE_CHAIN_AL 1 @@ -69,31 +69,31 @@ #define K_DMA_DESC_TYPE_RING_UAL_RMW 3 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3) -#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4) -#define M_DMA_LWM_INT_EN _SB_MAKEMASK1(5) -#define M_DMA_TBX_EN _SB_MAKEMASK1(6) -#define M_DMA_TDX_EN _SB_MAKEMASK1(7) +#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3) +#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4) +#define M_DMA_LWM_INT_EN _SB_MAKEMASK1(5) +#define M_DMA_TBX_EN _SB_MAKEMASK1(6) +#define M_DMA_TDX_EN _SB_MAKEMASK1(7) -#define S_DMA_INT_PKTCNT _SB_MAKE64(8) -#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8, S_DMA_INT_PKTCNT) -#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT) -#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT) +#define S_DMA_INT_PKTCNT _SB_MAKE64(8) +#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8, S_DMA_INT_PKTCNT) +#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT) +#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT) -#define S_DMA_RINGSZ _SB_MAKE64(16) -#define M_DMA_RINGSZ _SB_MAKEMASK(16, S_DMA_RINGSZ) -#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x, S_DMA_RINGSZ) -#define G_DMA_RINGSZ(x) _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ) +#define S_DMA_RINGSZ _SB_MAKE64(16) +#define M_DMA_RINGSZ _SB_MAKEMASK(16, S_DMA_RINGSZ) +#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x, S_DMA_RINGSZ) +#define G_DMA_RINGSZ(x) _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ) -#define S_DMA_HIGH_WATERMARK _SB_MAKE64(32) -#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK) -#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK) -#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK) +#define S_DMA_HIGH_WATERMARK _SB_MAKE64(32) +#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK) +#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK) +#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK) -#define S_DMA_LOW_WATERMARK _SB_MAKE64(48) -#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK) -#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK) -#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK) +#define S_DMA_LOW_WATERMARK _SB_MAKE64(48) +#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK) +#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK) +#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK) /* * Ethernet and Serial DMA Configuration Register 1 (Table 7-5) @@ -103,11 +103,11 @@ * Registers: DMA_CONFIG1_SER_x_TX */ -#define M_DMA_HDR_CF_EN _SB_MAKEMASK1(0) -#define M_DMA_ASIC_XFR_EN _SB_MAKEMASK1(1) -#define M_DMA_PRE_ADDR_EN _SB_MAKEMASK1(2) -#define M_DMA_FLOW_CTL_EN _SB_MAKEMASK1(3) -#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4) +#define M_DMA_HDR_CF_EN _SB_MAKEMASK1(0) +#define M_DMA_ASIC_XFR_EN _SB_MAKEMASK1(1) +#define M_DMA_PRE_ADDR_EN _SB_MAKEMASK1(2) +#define M_DMA_FLOW_CTL_EN _SB_MAKEMASK1(3) +#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4) #define M_DMA_L2CA _SB_MAKEMASK1(5) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) @@ -116,37 +116,37 @@ #define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define M_DMA_MBZ1 _SB_MAKEMASK(6, 15) +#define M_DMA_MBZ1 _SB_MAKEMASK(6, 15) -#define S_DMA_HDR_SIZE _SB_MAKE64(21) -#define M_DMA_HDR_SIZE _SB_MAKEMASK(9, S_DMA_HDR_SIZE) -#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_HDR_SIZE) -#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE) +#define S_DMA_HDR_SIZE _SB_MAKE64(21) +#define M_DMA_HDR_SIZE _SB_MAKEMASK(9, S_DMA_HDR_SIZE) +#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_HDR_SIZE) +#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE) -#define M_DMA_MBZ2 _SB_MAKEMASK(5, 32) +#define M_DMA_MBZ2 _SB_MAKEMASK(5, 32) -#define S_DMA_ASICXFR_SIZE _SB_MAKE64(37) -#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE) -#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE) -#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE) +#define S_DMA_ASICXFR_SIZE _SB_MAKE64(37) +#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE) +#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE) +#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE) -#define S_DMA_INT_TIMEOUT _SB_MAKE64(48) -#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT) -#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT) -#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT) +#define S_DMA_INT_TIMEOUT _SB_MAKE64(48) +#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT) +#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT) +#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT) /* * Ethernet and Serial DMA Descriptor base address (Table 7-6) */ -#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4, 0) +#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4, 0) /* * ASIC Mode Base Address (Table 7-7) */ -#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20, 0) +#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20, 0) /* * DMA Descriptor Count Registers (Table 7-8) @@ -159,10 +159,10 @@ * Current Descriptor Address Register (Table 7-11) */ -#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0) -#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR) -#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) -#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT) +#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0) +#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR) +#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) +#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) @@ -172,13 +172,13 @@ * Receive Packet Drop Registers */ #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_DMA_OODLOST_RX _SB_MAKE64(0) -#define M_DMA_OODLOST_RX _SB_MAKEMASK(16, S_DMA_OODLOST_RX) -#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX) +#define S_DMA_OODLOST_RX _SB_MAKE64(0) +#define M_DMA_OODLOST_RX _SB_MAKEMASK(16, S_DMA_OODLOST_RX) +#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX) -#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) -#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX) -#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX) +#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) +#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX) +#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ /* ********************************************************************* @@ -189,26 +189,26 @@ * Descriptor doubleword "A" (Table 7-12) */ -#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0) -#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET) -#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET) -#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET) +#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0) +#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET) +#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET) +#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET) /* Note: Don't shift the address over, just mask it with the mask below */ -#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5) -#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR) +#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5) +#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR) #define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) -#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA) +#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) +#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) -#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE) -#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE) -#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE) +#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) +#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE) +#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE) +#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) @@ -216,43 +216,43 @@ #define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x, S_DMA_DSCRA_DSCR_CNT, M_DMA_DSCRA_DSCR_CNT) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) +#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) #define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) -#define S_DMA_DSCRA_STATUS _SB_MAKE64(51) -#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS) -#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS) -#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS) +#define S_DMA_DSCRA_STATUS _SB_MAKE64(51) +#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS) +#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS) +#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS) /* * Descriptor doubleword "B" (Table 7-13) */ -#define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0) -#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS) -#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS) -#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS) +#define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0) +#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS) +#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS) +#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) -#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE) -#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE) -#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE) +#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) +#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE) +#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE) +#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) +#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) /* Note: Don't shift the address over, just mask it with the mask below */ -#define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5) -#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR) +#define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5) +#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR) -#define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40) -#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE) -#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE) -#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE) +#define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40) +#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE) +#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE) +#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE) -#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) +#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) @@ -261,24 +261,24 @@ #define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB, M_DMA_DSCRB_PKT_SIZE_MSB) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) -#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE) -#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE) -#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE) +#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) +#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE) +#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE) +#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE) /* * from pass2 some bits in dscr_b are also used for rx status */ -#define S_DMA_DSCRB_STATUS _SB_MAKE64(0) -#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS) -#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS) -#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS) +#define S_DMA_DSCRB_STATUS _SB_MAKE64(0) +#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS) +#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS) +#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS) /* * Ethernet Descriptor Status Bits (Table 7-15) */ -#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) +#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) #define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) @@ -292,70 +292,70 @@ #define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define S_DMA_ETHRX_RXCH 53 -#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH) -#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH) -#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH) +#define S_DMA_ETHRX_RXCH 53 +#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH) +#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH) +#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH) -#define S_DMA_ETHRX_PKTTYPE 55 -#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE) -#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE) -#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE) +#define S_DMA_ETHRX_PKTTYPE 55 +#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE) +#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE) +#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE) #define K_DMA_ETHRX_PKTTYPE_IPV4 0 #define K_DMA_ETHRX_PKTTYPE_ARPV4 1 -#define K_DMA_ETHRX_PKTTYPE_802 2 +#define K_DMA_ETHRX_PKTTYPE_802 2 #define K_DMA_ETHRX_PKTTYPE_OTHER 3 #define K_DMA_ETHRX_PKTTYPE_USER0 4 #define K_DMA_ETHRX_PKTTYPE_USER1 5 #define K_DMA_ETHRX_PKTTYPE_USER2 6 #define K_DMA_ETHRX_PKTTYPE_USER3 7 -#define M_DMA_ETHRX_MATCH_HASH _SB_MAKEMASK1(58) -#define M_DMA_ETHRX_MATCH_EXACT _SB_MAKEMASK1(59) -#define M_DMA_ETHRX_BCAST _SB_MAKEMASK1(60) -#define M_DMA_ETHRX_MCAST _SB_MAKEMASK1(61) -#define M_DMA_ETHRX_BAD _SB_MAKEMASK1(62) -#define M_DMA_ETHRX_SOP _SB_MAKEMASK1(63) +#define M_DMA_ETHRX_MATCH_HASH _SB_MAKEMASK1(58) +#define M_DMA_ETHRX_MATCH_EXACT _SB_MAKEMASK1(59) +#define M_DMA_ETHRX_BCAST _SB_MAKEMASK1(60) +#define M_DMA_ETHRX_MCAST _SB_MAKEMASK1(61) +#define M_DMA_ETHRX_BAD _SB_MAKEMASK1(62) +#define M_DMA_ETHRX_SOP _SB_MAKEMASK1(63) /* * Ethernet Transmit Status Bits (Table 7-16) */ -#define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63) +#define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63) /* * Ethernet Transmit Options (Table 7-17) */ -#define K_DMA_ETHTX_NOTSOP _SB_MAKE64(0x00) -#define K_DMA_ETHTX_APPENDCRC _SB_MAKE64(0x01) -#define K_DMA_ETHTX_REPLACECRC _SB_MAKE64(0x02) +#define K_DMA_ETHTX_NOTSOP _SB_MAKE64(0x00) +#define K_DMA_ETHTX_APPENDCRC _SB_MAKE64(0x01) +#define K_DMA_ETHTX_REPLACECRC _SB_MAKE64(0x02) #define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03) #define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04) #define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05) #define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6) -#define K_DMA_ETHTX_NOMODS _SB_MAKE64(0x07) -#define K_DMA_ETHTX_RESERVED1 _SB_MAKE64(0x08) +#define K_DMA_ETHTX_NOMODS _SB_MAKE64(0x07) +#define K_DMA_ETHTX_RESERVED1 _SB_MAKE64(0x08) #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09) #define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A) #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B) #define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C) #define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D) #define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E) -#define K_DMA_ETHTX_RESERVED2 _SB_MAKE64(0x0F) +#define K_DMA_ETHTX_RESERVED2 _SB_MAKE64(0x0F) /* * Serial Receive Options (Table 7-18) */ -#define M_DMA_SERRX_CRC_ERROR _SB_MAKEMASK1(56) -#define M_DMA_SERRX_ABORT _SB_MAKEMASK1(57) -#define M_DMA_SERRX_OCTET_ERROR _SB_MAKEMASK1(58) +#define M_DMA_SERRX_CRC_ERROR _SB_MAKEMASK1(56) +#define M_DMA_SERRX_ABORT _SB_MAKEMASK1(57) +#define M_DMA_SERRX_OCTET_ERROR _SB_MAKEMASK1(58) #define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59) #define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60) #define M_DMA_SERRX_OVERRUN_ERROR _SB_MAKEMASK1(61) -#define M_DMA_SERRX_GOOD _SB_MAKEMASK1(62) -#define M_DMA_SERRX_SOP _SB_MAKEMASK1(63) +#define M_DMA_SERRX_GOOD _SB_MAKEMASK1(62) +#define M_DMA_SERRX_SOP _SB_MAKEMASK1(63) /* * Serial Transmit Status Bits (Table 7-20) @@ -367,10 +367,10 @@ * Serial Transmit Options (Table 7-21) */ -#define K_DMA_SERTX_RESERVED _SB_MAKEMASK1(0) -#define K_DMA_SERTX_APPENDCRC _SB_MAKEMASK1(1) -#define K_DMA_SERTX_APPENDPAD _SB_MAKEMASK1(2) -#define K_DMA_SERTX_ABORT _SB_MAKEMASK1(3) +#define K_DMA_SERTX_RESERVED _SB_MAKEMASK1(0) +#define K_DMA_SERTX_APPENDCRC _SB_MAKEMASK1(1) +#define K_DMA_SERTX_APPENDPAD _SB_MAKEMASK1(2) +#define K_DMA_SERTX_ABORT _SB_MAKEMASK1(3) /* ********************************************************************* @@ -385,19 +385,19 @@ * Register: DM_DSCR_BASE_3 */ -#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4, 0) +#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4, 0) /* Note: Just mask the base address and then OR it in. */ -#define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4) -#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR) +#define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4) +#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR) -#define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40) -#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ) +#define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40) +#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ) #define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_RINGSZ) #define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_RINGSZ, M_DM_DSCR_BASE_RINGSZ) -#define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56) -#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY) +#define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56) +#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY) #define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_PRIORITY) #define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_PRIORITY, M_DM_DSCR_BASE_PRIORITY) @@ -407,12 +407,12 @@ #define K_DM_DSCR_BASE_PRIORITY_8 3 #define K_DM_DSCR_BASE_PRIORITY_16 4 -#define M_DM_DSCR_BASE_ACTIVE _SB_MAKEMASK1(59) +#define M_DM_DSCR_BASE_ACTIVE _SB_MAKEMASK1(59) #define M_DM_DSCR_BASE_INTERRUPT _SB_MAKEMASK1(60) -#define M_DM_DSCR_BASE_RESET _SB_MAKEMASK1(61) /* write register */ -#define M_DM_DSCR_BASE_ERROR _SB_MAKEMASK1(61) /* read register */ -#define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62) -#define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63) +#define M_DM_DSCR_BASE_RESET _SB_MAKEMASK1(61) /* write register */ +#define M_DM_DSCR_BASE_ERROR _SB_MAKEMASK1(61) /* read register */ +#define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62) +#define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63) /* * Data Mover Descriptor Count Register (Table 7-25) @@ -428,14 +428,14 @@ * Register: DM_CUR_DSCR_ADDR_3 */ -#define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0) -#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR) +#define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0) +#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR) #define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48) #define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16, S_DM_CUR_DSCR_DSCR_COUNT) #define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT) #define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT,\ - M_DM_CUR_DSCR_DSCR_COUNT) + M_DM_CUR_DSCR_DSCR_COUNT) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) @@ -450,15 +450,15 @@ #define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32, S_DM_PARTIAL_CRC_PARTIAL) #define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_CRC_PARTIAL) #define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_CRC_PARTIAL,\ - M_DM_PARTIAL_CRC_PARTIAL) + M_DM_PARTIAL_CRC_PARTIAL) #define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32) #define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16, S_DM_PARTIAL_TCPCS_PARTIAL) #define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL) #define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL,\ - M_DM_PARTIAL_TCPCS_PARTIAL) + M_DM_PARTIAL_TCPCS_PARTIAL) -#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) +#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ @@ -468,17 +468,17 @@ * Register: CRC_DEF_0 * Register: CRC_DEF_1 */ -#define S_CRC_DEF_CRC_INIT _SB_MAKE64(0) -#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT) -#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT) -#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\ - M_CRC_DEF_CRC_INIT) - -#define S_CRC_DEF_CRC_POLY _SB_MAKE64(32) -#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY) -#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY) -#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\ - M_CRC_DEF_CRC_POLY) +#define S_CRC_DEF_CRC_INIT _SB_MAKE64(0) +#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT) +#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT) +#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\ + M_CRC_DEF_CRC_INIT) + +#define S_CRC_DEF_CRC_POLY _SB_MAKE64(32) +#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY) +#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY) +#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\ + M_CRC_DEF_CRC_POLY) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ @@ -488,50 +488,50 @@ * Register: CTCP_DEF_0 * Register: CTCP_DEF_1 */ -#define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0) -#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR) -#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR) -#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\ - M_CTCP_DEF_CRC_TXOR) - -#define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32) -#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT) +#define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0) +#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR) +#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR) +#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\ + M_CTCP_DEF_CRC_TXOR) + +#define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32) +#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT) #define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r, S_CTCP_DEF_TCPCS_INIT) #define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r, S_CTCP_DEF_TCPCS_INIT,\ - M_CTCP_DEF_TCPCS_INIT) + M_CTCP_DEF_TCPCS_INIT) -#define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48) -#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH) -#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH) -#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\ - M_CTCP_DEF_CRC_WIDTH) +#define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48) +#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH) +#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH) +#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\ + M_CTCP_DEF_CRC_WIDTH) -#define K_CTCP_DEF_CRC_WIDTH_4 0 -#define K_CTCP_DEF_CRC_WIDTH_2 1 -#define K_CTCP_DEF_CRC_WIDTH_1 2 +#define K_CTCP_DEF_CRC_WIDTH_4 0 +#define K_CTCP_DEF_CRC_WIDTH_2 1 +#define K_CTCP_DEF_CRC_WIDTH_1 2 #define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ /* - * Data Mover Descriptor Doubleword "A" (Table 7-26) + * Data Mover Descriptor Doubleword "A" (Table 7-26) */ -#define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0) -#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR) +#define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0) +#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR) -#define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40) -#define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41) -#define M_DM_DSCRA_INTERRUPT _SB_MAKEMASK1(42) +#define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40) +#define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41) +#define M_DM_DSCRA_INTERRUPT _SB_MAKEMASK1(42) #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) -#define M_DM_DSCRA_THROTTLE _SB_MAKEMASK1(43) +#define M_DM_DSCRA_THROTTLE _SB_MAKEMASK1(43) #endif /* up to 1250 PASS1 */ -#define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44) -#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST) -#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST) -#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST) +#define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44) +#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST) +#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST) +#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST) #define K_DM_DSCRA_DIR_DEST_INCR 0 #define K_DM_DSCRA_DIR_DEST_DECR 1 @@ -541,24 +541,24 @@ #define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR, S_DM_DSCRA_DIR_DEST) #define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST, S_DM_DSCRA_DIR_DEST) -#define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46) -#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC) -#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC) +#define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46) +#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC) +#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC) +#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC) -#define K_DM_DSCRA_DIR_SRC_INCR 0 -#define K_DM_DSCRA_DIR_SRC_DECR 1 +#define K_DM_DSCRA_DIR_SRC_INCR 0 +#define K_DM_DSCRA_DIR_SRC_DECR 1 #define K_DM_DSCRA_DIR_SRC_CONST 2 -#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC) +#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC) +#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC) #define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST, S_DM_DSCRA_DIR_SRC) -#define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48) -#define M_DM_DSCRA_PREFETCH _SB_MAKEMASK1(49) -#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50) -#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51) +#define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48) +#define M_DM_DSCRA_PREFETCH _SB_MAKEMASK1(49) +#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50) +#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52) @@ -566,27 +566,27 @@ #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54) -#define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55) -#define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56) -#define M_DM_DSCRA_CRC_EN _SB_MAKEMASK1(57) -#define M_DM_DSCRA_CRC_RES _SB_MAKEMASK1(58) -#define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59) -#define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60) -#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) +#define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54) +#define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55) +#define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56) +#define M_DM_DSCRA_CRC_EN _SB_MAKEMASK1(57) +#define M_DM_DSCRA_CRC_RES _SB_MAKEMASK1(58) +#define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59) +#define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60) +#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3, 61) +#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3, 61) /* - * Data Mover Descriptor Doubleword "B" (Table 7-25) + * Data Mover Descriptor Doubleword "B" (Table 7-25) */ -#define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0) -#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR) +#define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0) +#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR) -#define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40) -#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH) +#define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40) +#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH) #define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x, S_DM_DSCRB_SRC_LENGTH) #define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x, S_DM_DSCRB_SRC_LENGTH, M_DM_DSCRB_SRC_LENGTH) diff --git a/arch/mips/include/asm/sibyte/sb1250_genbus.h b/arch/mips/include/asm/sibyte/sb1250_genbus.h index a96ded17bdc..04c009c3693 100644 --- a/arch/mips/include/asm/sibyte/sb1250_genbus.h +++ b/arch/mips/include/asm/sibyte/sb1250_genbus.h @@ -1,7 +1,7 @@ /* ********************************************************************* * SB1250 Board Support Package * - * Generic Bus Constants File: sb1250_genbus.h + * Generic Bus Constants File: sb1250_genbus.h * * This module contains constants and macros useful for * manipulating the SB1250's Generic Bus interface @@ -40,10 +40,10 @@ * Generic Bus Region Configuration Registers (Table 11-4) */ -#define S_IO_RDY_ACTIVE 0 +#define S_IO_RDY_ACTIVE 0 #define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE) -#define S_IO_ENA_RDY 1 +#define S_IO_ENA_RDY 1 #define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) #define S_IO_WIDTH_SEL 2 @@ -52,7 +52,7 @@ #define K_IO_WIDTH_SEL_2 1 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ || SIBYTE_HDR_FEATURE_CHIP(1480) -#define K_IO_WIDTH_SEL_1L 2 +#define K_IO_WIDTH_SEL_1L 2 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define K_IO_WIDTH_SEL_4 3 #define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x, S_IO_WIDTH_SEL) @@ -111,7 +111,7 @@ #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_IO_EARLY_CS _SB_MAKEMASK1(3) +#define M_IO_EARLY_CS _SB_MAKEMASK1(3) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_IO_ALE_TO_CS 4 @@ -121,10 +121,10 @@ #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_IO_BURST_WIDTH _SB_MAKE64(6) -#define M_IO_BURST_WIDTH _SB_MAKEMASK(2, S_IO_BURST_WIDTH) -#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x, S_IO_BURST_WIDTH) -#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH) +#define S_IO_BURST_WIDTH _SB_MAKE64(6) +#define M_IO_BURST_WIDTH _SB_MAKEMASK(2, S_IO_BURST_WIDTH) +#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x, S_IO_BURST_WIDTH) +#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_IO_CS_WIDTH 8 @@ -149,7 +149,7 @@ #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_IO_RDY_SYNC _SB_MAKEMASK1(3) +#define M_IO_RDY_SYNC _SB_MAKEMASK1(3) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ #define S_IO_WRITE_WIDTH 4 @@ -191,7 +191,7 @@ #define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11) #define M_IO_MULT_CS_INT _SB_MAKEMASK1(12) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_IO_COH_ERR _SB_MAKEMASK1(14) +#define M_IO_COH_ERR _SB_MAKEMASK1(14) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ @@ -370,8 +370,8 @@ #define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) #define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n)) -#define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n)) -#define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n)) +#define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n)) +#define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n)) #define S_GPIO_INTR_TYPE0 0 #define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0) diff --git a/arch/mips/include/asm/sibyte/sb1250_int.h b/arch/mips/include/asm/sibyte/sb1250_int.h index dbea73ddd2f..36afcb2766c 100644 --- a/arch/mips/include/asm/sibyte/sb1250_int.h +++ b/arch/mips/include/asm/sibyte/sb1250_int.h @@ -45,71 +45,71 @@ * First, the interrupt numbers. */ -#define K_INT_SOURCES 64 - -#define K_INT_WATCHDOG_TIMER_0 0 -#define K_INT_WATCHDOG_TIMER_1 1 -#define K_INT_TIMER_0 2 -#define K_INT_TIMER_1 3 -#define K_INT_TIMER_2 4 -#define K_INT_TIMER_3 5 -#define K_INT_SMB_0 6 -#define K_INT_SMB_1 7 -#define K_INT_UART_0 8 -#define K_INT_UART_1 9 -#define K_INT_SER_0 10 -#define K_INT_SER_1 11 -#define K_INT_PCMCIA 12 -#define K_INT_ADDR_TRAP 13 -#define K_INT_PERF_CNT 14 -#define K_INT_TRACE_FREEZE 15 -#define K_INT_BAD_ECC 16 -#define K_INT_COR_ECC 17 -#define K_INT_IO_BUS 18 -#define K_INT_MAC_0 19 -#define K_INT_MAC_1 20 -#define K_INT_MAC_2 21 -#define K_INT_DM_CH_0 22 -#define K_INT_DM_CH_1 23 -#define K_INT_DM_CH_2 24 -#define K_INT_DM_CH_3 25 -#define K_INT_MBOX_0 26 -#define K_INT_MBOX_1 27 -#define K_INT_MBOX_2 28 -#define K_INT_MBOX_3 29 +#define K_INT_SOURCES 64 + +#define K_INT_WATCHDOG_TIMER_0 0 +#define K_INT_WATCHDOG_TIMER_1 1 +#define K_INT_TIMER_0 2 +#define K_INT_TIMER_1 3 +#define K_INT_TIMER_2 4 +#define K_INT_TIMER_3 5 +#define K_INT_SMB_0 6 +#define K_INT_SMB_1 7 +#define K_INT_UART_0 8 +#define K_INT_UART_1 9 +#define K_INT_SER_0 10 +#define K_INT_SER_1 11 +#define K_INT_PCMCIA 12 +#define K_INT_ADDR_TRAP 13 +#define K_INT_PERF_CNT 14 +#define K_INT_TRACE_FREEZE 15 +#define K_INT_BAD_ECC 16 +#define K_INT_COR_ECC 17 +#define K_INT_IO_BUS 18 +#define K_INT_MAC_0 19 +#define K_INT_MAC_1 20 +#define K_INT_MAC_2 21 +#define K_INT_DM_CH_0 22 +#define K_INT_DM_CH_1 23 +#define K_INT_DM_CH_2 24 +#define K_INT_DM_CH_3 25 +#define K_INT_MBOX_0 26 +#define K_INT_MBOX_1 27 +#define K_INT_MBOX_2 28 +#define K_INT_MBOX_3 29 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) #define K_INT_CYCLE_CP0_INT 30 #define K_INT_CYCLE_CP1_INT 31 #endif /* 1250 PASS2 || 112x PASS1 */ -#define K_INT_GPIO_0 32 -#define K_INT_GPIO_1 33 -#define K_INT_GPIO_2 34 -#define K_INT_GPIO_3 35 -#define K_INT_GPIO_4 36 -#define K_INT_GPIO_5 37 -#define K_INT_GPIO_6 38 -#define K_INT_GPIO_7 39 -#define K_INT_GPIO_8 40 -#define K_INT_GPIO_9 41 -#define K_INT_GPIO_10 42 -#define K_INT_GPIO_11 43 -#define K_INT_GPIO_12 44 -#define K_INT_GPIO_13 45 -#define K_INT_GPIO_14 46 -#define K_INT_GPIO_15 47 -#define K_INT_LDT_FATAL 48 -#define K_INT_LDT_NONFATAL 49 -#define K_INT_LDT_SMI 50 -#define K_INT_LDT_NMI 51 -#define K_INT_LDT_INIT 52 -#define K_INT_LDT_STARTUP 53 -#define K_INT_LDT_EXT 54 -#define K_INT_PCI_ERROR 55 -#define K_INT_PCI_INTA 56 -#define K_INT_PCI_INTB 57 -#define K_INT_PCI_INTC 58 -#define K_INT_PCI_INTD 59 -#define K_INT_SPARE_2 60 +#define K_INT_GPIO_0 32 +#define K_INT_GPIO_1 33 +#define K_INT_GPIO_2 34 +#define K_INT_GPIO_3 35 +#define K_INT_GPIO_4 36 +#define K_INT_GPIO_5 37 +#define K_INT_GPIO_6 38 +#define K_INT_GPIO_7 39 +#define K_INT_GPIO_8 40 +#define K_INT_GPIO_9 41 +#define K_INT_GPIO_10 42 +#define K_INT_GPIO_11 43 +#define K_INT_GPIO_12 44 +#define K_INT_GPIO_13 45 +#define K_INT_GPIO_14 46 +#define K_INT_GPIO_15 47 +#define K_INT_LDT_FATAL 48 +#define K_INT_LDT_NONFATAL 49 +#define K_INT_LDT_SMI 50 +#define K_INT_LDT_NMI 51 +#define K_INT_LDT_INIT 52 +#define K_INT_LDT_STARTUP 53 +#define K_INT_LDT_EXT 54 +#define K_INT_PCI_ERROR 55 +#define K_INT_PCI_INTA 56 +#define K_INT_PCI_INTB 57 +#define K_INT_PCI_INTC 58 +#define K_INT_PCI_INTD 59 +#define K_INT_SPARE_2 60 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) #define K_INT_MAC_0_CH1 61 #define K_INT_MAC_1_CH1 62 @@ -120,70 +120,70 @@ * Mask values for each interrupt */ -#define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0) -#define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1) -#define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0) -#define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1) -#define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2) -#define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3) -#define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0) -#define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1) -#define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0) -#define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1) -#define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0) -#define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1) -#define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA) -#define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP) -#define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT) -#define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE) -#define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC) -#define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC) -#define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS) -#define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0) -#define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1) -#define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2) -#define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0) -#define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1) -#define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2) -#define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3) -#define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0) -#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1) -#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2) -#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3) -#define M_INT_MBOX_ALL _SB_MAKEMASK(4, K_INT_MBOX_0) +#define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0) +#define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1) +#define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0) +#define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1) +#define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2) +#define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3) +#define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0) +#define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1) +#define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0) +#define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1) +#define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0) +#define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1) +#define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA) +#define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP) +#define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT) +#define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE) +#define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC) +#define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC) +#define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS) +#define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0) +#define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1) +#define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2) +#define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0) +#define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1) +#define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2) +#define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3) +#define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0) +#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1) +#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2) +#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3) +#define M_INT_MBOX_ALL _SB_MAKEMASK(4, K_INT_MBOX_0) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) #define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT) #define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT) #endif /* 1250 PASS2 || 112x PASS1 */ -#define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0) -#define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1) -#define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2) -#define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3) -#define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4) -#define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5) -#define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6) -#define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7) -#define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8) -#define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9) -#define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10) -#define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11) -#define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12) -#define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13) -#define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14) -#define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15) -#define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL) -#define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL) -#define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI) -#define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI) -#define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT) -#define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP) -#define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT) -#define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR) -#define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA) -#define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB) -#define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC) -#define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD) -#define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2) +#define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0) +#define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1) +#define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2) +#define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3) +#define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4) +#define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5) +#define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6) +#define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7) +#define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8) +#define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9) +#define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10) +#define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11) +#define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12) +#define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13) +#define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14) +#define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15) +#define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL) +#define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL) +#define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI) +#define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI) +#define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT) +#define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP) +#define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT) +#define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR) +#define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA) +#define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB) +#define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC) +#define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD) +#define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) #define M_INT_MAC_0_CH1 _SB_MAKEMASK1(K_INT_MAC_0_CH1) #define M_INT_MAC_1_CH1 _SB_MAKEMASK1(K_INT_MAC_1_CH1) @@ -208,9 +208,9 @@ */ #define S_INT_LDT_INTMSG 0 -#define M_INT_LDT_INTMSG _SB_MAKEMASK(3, S_INT_LDT_INTMSG) -#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x, S_INT_LDT_INTMSG) -#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG) +#define M_INT_LDT_INTMSG _SB_MAKEMASK(3, S_INT_LDT_INTMSG) +#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x, S_INT_LDT_INTMSG) +#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG) #define K_INT_LDT_INTMSG_FIXED 0 #define K_INT_LDT_INTMSG_ARBITRATED 1 @@ -221,28 +221,28 @@ #define K_INT_LDT_INTMSG_EXTINT 6 #define K_INT_LDT_INTMSG_RESERVED 7 -#define M_INT_LDT_EDGETRIGGER 0 -#define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3) +#define M_INT_LDT_EDGETRIGGER 0 +#define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3) -#define M_INT_LDT_PHYSICALDEST 0 -#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4) +#define M_INT_LDT_PHYSICALDEST 0 +#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4) -#define S_INT_LDT_INTDEST 5 -#define M_INT_LDT_INTDEST _SB_MAKEMASK(10, S_INT_LDT_INTDEST) -#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x, S_INT_LDT_INTDEST) -#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST) +#define S_INT_LDT_INTDEST 5 +#define M_INT_LDT_INTDEST _SB_MAKEMASK(10, S_INT_LDT_INTDEST) +#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x, S_INT_LDT_INTDEST) +#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST) -#define S_INT_LDT_VECTOR 13 -#define M_INT_LDT_VECTOR _SB_MAKEMASK(8, S_INT_LDT_VECTOR) -#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x, S_INT_LDT_VECTOR) -#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR) +#define S_INT_LDT_VECTOR 13 +#define M_INT_LDT_VECTOR _SB_MAKEMASK(8, S_INT_LDT_VECTOR) +#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x, S_INT_LDT_VECTOR) +#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR) /* * Vector format (Table 4-6) */ #define M_LDTVECT_RAISEINT 0x00 -#define M_LDTVECT_RAISEMBOX 0x40 +#define M_LDTVECT_RAISEMBOX 0x40 #endif /* 1250/112x */ diff --git a/arch/mips/include/asm/sibyte/sb1250_l2c.h b/arch/mips/include/asm/sibyte/sb1250_l2c.h index b61a7491607..30092d7cfdc 100644 --- a/arch/mips/include/asm/sibyte/sb1250_l2c.h +++ b/arch/mips/include/asm/sibyte/sb1250_l2c.h @@ -39,71 +39,71 @@ * Level 2 Cache Tag register (Table 5-3) */ -#define S_L2C_TAG_MBZ 0 -#define M_L2C_TAG_MBZ _SB_MAKEMASK(5, S_L2C_TAG_MBZ) +#define S_L2C_TAG_MBZ 0 +#define M_L2C_TAG_MBZ _SB_MAKEMASK(5, S_L2C_TAG_MBZ) -#define S_L2C_TAG_INDEX 5 -#define M_L2C_TAG_INDEX _SB_MAKEMASK(12, S_L2C_TAG_INDEX) -#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_L2C_TAG_INDEX) -#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX) +#define S_L2C_TAG_INDEX 5 +#define M_L2C_TAG_INDEX _SB_MAKEMASK(12, S_L2C_TAG_INDEX) +#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_L2C_TAG_INDEX) +#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX) -#define S_L2C_TAG_TAG 17 -#define M_L2C_TAG_TAG _SB_MAKEMASK(23, S_L2C_TAG_TAG) -#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_L2C_TAG_TAG) -#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG) +#define S_L2C_TAG_TAG 17 +#define M_L2C_TAG_TAG _SB_MAKEMASK(23, S_L2C_TAG_TAG) +#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_L2C_TAG_TAG) +#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG) -#define S_L2C_TAG_ECC 40 -#define M_L2C_TAG_ECC _SB_MAKEMASK(6, S_L2C_TAG_ECC) -#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_L2C_TAG_ECC) -#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC) +#define S_L2C_TAG_ECC 40 +#define M_L2C_TAG_ECC _SB_MAKEMASK(6, S_L2C_TAG_ECC) +#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_L2C_TAG_ECC) +#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC) -#define S_L2C_TAG_WAY 46 -#define M_L2C_TAG_WAY _SB_MAKEMASK(2, S_L2C_TAG_WAY) -#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_L2C_TAG_WAY) -#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY) +#define S_L2C_TAG_WAY 46 +#define M_L2C_TAG_WAY _SB_MAKEMASK(2, S_L2C_TAG_WAY) +#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_L2C_TAG_WAY) +#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY) -#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48) -#define M_L2C_TAG_VALID _SB_MAKEMASK1(49) +#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48) +#define M_L2C_TAG_VALID _SB_MAKEMASK1(49) /* * Format of level 2 cache management address (table 5-2) */ -#define S_L2C_MGMT_INDEX 5 -#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_L2C_MGMT_INDEX) -#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX) -#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX) +#define S_L2C_MGMT_INDEX 5 +#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_L2C_MGMT_INDEX) +#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX) +#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX) -#define S_L2C_MGMT_QUADRANT 15 -#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT) -#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT) -#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT) +#define S_L2C_MGMT_QUADRANT 15 +#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT) +#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT) +#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT) #define S_L2C_MGMT_HALF 16 -#define M_L2C_MGMT_HALF _SB_MAKEMASK(1, S_L2C_MGMT_HALF) +#define M_L2C_MGMT_HALF _SB_MAKEMASK(1, S_L2C_MGMT_HALF) -#define S_L2C_MGMT_WAY 17 -#define M_L2C_MGMT_WAY _SB_MAKEMASK(2, S_L2C_MGMT_WAY) -#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_L2C_MGMT_WAY) -#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY) +#define S_L2C_MGMT_WAY 17 +#define M_L2C_MGMT_WAY _SB_MAKEMASK(2, S_L2C_MGMT_WAY) +#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_L2C_MGMT_WAY) +#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY) -#define S_L2C_MGMT_ECC_DIAG 21 -#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG) -#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG) -#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG) +#define S_L2C_MGMT_ECC_DIAG 21 +#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG) +#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG) +#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG) -#define S_L2C_MGMT_TAG 23 -#define M_L2C_MGMT_TAG _SB_MAKEMASK(4, S_L2C_MGMT_TAG) -#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_TAG) -#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG) +#define S_L2C_MGMT_TAG 23 +#define M_L2C_MGMT_TAG _SB_MAKEMASK(4, S_L2C_MGMT_TAG) +#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_TAG) +#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG) -#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19) -#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20) +#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19) +#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20) -#define A_L2C_MGMT_TAG_BASE 0x00D0000000 +#define A_L2C_MGMT_TAG_BASE 0x00D0000000 -#define L2C_ENTRIES_PER_WAY 4096 -#define L2C_NUM_WAYS 4 +#define L2C_ENTRIES_PER_WAY 4096 +#define L2C_NUM_WAYS 4 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) diff --git a/arch/mips/include/asm/sibyte/sb1250_ldt.h b/arch/mips/include/asm/sibyte/sb1250_ldt.h index bf7f320d1a8..2340c29dc0c 100644 --- a/arch/mips/include/asm/sibyte/sb1250_ldt.h +++ b/arch/mips/include/asm/sibyte/sb1250_ldt.h @@ -66,7 +66,7 @@ #define R_LDT_TYPE1_SRICMD 0x0050 #define R_LDT_TYPE1_SRITXNUM 0x0054 #define R_LDT_TYPE1_SRIRXNUM 0x0058 -#define R_LDT_TYPE1_ERRSTATUS 0x0068 +#define R_LDT_TYPE1_ERRSTATUS 0x0068 #define R_LDT_TYPE1_SRICTRL 0x006C #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) #define R_LDT_TYPE1_ADDSTATUS 0x0070 @@ -258,7 +258,7 @@ #define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31) /* - * LDT Link frequency register (Table 8-20) offset 0x48 + * LDT Link frequency register (Table 8-20) offset 0x48 */ #define S_LDT_LINKFREQ_FREQ 8 @@ -301,8 +301,8 @@ #define S_LDT_SRICMD_TXINITIALOFFSET 28 #define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET) -#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET) -#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET) +#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET) +#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET) #define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31) @@ -318,16 +318,16 @@ #define M_LDT_ERRCTL_OVFSYNCFLOOD_EN _SB_MAKEMASK1_32(5) #define M_LDT_ERRCTL_EOCNXAFATAL_EN _SB_MAKEMASK1_32(6) #define M_LDT_ERRCTL_EOCNXANONFATAL_EN _SB_MAKEMASK1_32(7) -#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8) +#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8) #define M_LDT_ERRCTL_CRCFATAL_EN _SB_MAKEMASK1_32(9) #define M_LDT_ERRCTL_CRCNONFATAL_EN _SB_MAKEMASK1_32(10) #define M_LDT_ERRCTL_SERRFATAL_EN _SB_MAKEMASK1_32(11) #define M_LDT_ERRCTL_SRCTAGFATAL_EN _SB_MAKEMASK1_32(12) #define M_LDT_ERRCTL_SRCTAGNONFATAL_EN _SB_MAKEMASK1_32(13) -#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14) +#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14) #define M_LDT_ERRCTL_MAPNXAFATAL_EN _SB_MAKEMASK1_32(15) #define M_LDT_ERRCTL_MAPNXANONFATAL_EN _SB_MAKEMASK1_32(16) -#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17) +#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17) #define M_LDT_ERRCTL_PROTOERR _SB_MAKEMASK1_32(24) #define M_LDT_ERRCTL_OVFERR _SB_MAKEMASK1_32(25) diff --git a/arch/mips/include/asm/sibyte/sb1250_mac.h b/arch/mips/include/asm/sibyte/sb1250_mac.h index cfc4d787088..3fa94fc7404 100644 --- a/arch/mips/include/asm/sibyte/sb1250_mac.h +++ b/arch/mips/include/asm/sibyte/sb1250_mac.h @@ -47,86 +47,86 @@ */ -#define M_MAC_RESERVED0 _SB_MAKEMASK1(0) -#define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1) -#define M_MAC_RETRY_EN _SB_MAKEMASK1(2) -#define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3) -#define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4) -#define M_MAC_BURST_EN _SB_MAKEMASK1(5) - -#define S_MAC_TX_PAUSE _SB_MAKE64(6) -#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3, S_MAC_TX_PAUSE) -#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x, S_MAC_TX_PAUSE) - -#define K_MAC_TX_PAUSE_CNT_512 0 -#define K_MAC_TX_PAUSE_CNT_1K 1 -#define K_MAC_TX_PAUSE_CNT_2K 2 -#define K_MAC_TX_PAUSE_CNT_4K 3 -#define K_MAC_TX_PAUSE_CNT_8K 4 -#define K_MAC_TX_PAUSE_CNT_16K 5 -#define K_MAC_TX_PAUSE_CNT_32K 6 -#define K_MAC_TX_PAUSE_CNT_64K 7 - -#define V_MAC_TX_PAUSE_CNT_512 V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512) -#define V_MAC_TX_PAUSE_CNT_1K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K) -#define V_MAC_TX_PAUSE_CNT_2K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K) -#define V_MAC_TX_PAUSE_CNT_4K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K) -#define V_MAC_TX_PAUSE_CNT_8K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K) -#define V_MAC_TX_PAUSE_CNT_16K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K) -#define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) -#define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) - -#define M_MAC_RESERVED1 _SB_MAKEMASK(8, 9) - -#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) +#define M_MAC_RESERVED0 _SB_MAKEMASK1(0) +#define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1) +#define M_MAC_RETRY_EN _SB_MAKEMASK1(2) +#define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3) +#define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4) +#define M_MAC_BURST_EN _SB_MAKEMASK1(5) + +#define S_MAC_TX_PAUSE _SB_MAKE64(6) +#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3, S_MAC_TX_PAUSE) +#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x, S_MAC_TX_PAUSE) + +#define K_MAC_TX_PAUSE_CNT_512 0 +#define K_MAC_TX_PAUSE_CNT_1K 1 +#define K_MAC_TX_PAUSE_CNT_2K 2 +#define K_MAC_TX_PAUSE_CNT_4K 3 +#define K_MAC_TX_PAUSE_CNT_8K 4 +#define K_MAC_TX_PAUSE_CNT_16K 5 +#define K_MAC_TX_PAUSE_CNT_32K 6 +#define K_MAC_TX_PAUSE_CNT_64K 7 + +#define V_MAC_TX_PAUSE_CNT_512 V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512) +#define V_MAC_TX_PAUSE_CNT_1K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K) +#define V_MAC_TX_PAUSE_CNT_2K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K) +#define V_MAC_TX_PAUSE_CNT_4K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K) +#define V_MAC_TX_PAUSE_CNT_8K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K) +#define V_MAC_TX_PAUSE_CNT_16K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K) +#define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) +#define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) + +#define M_MAC_RESERVED1 _SB_MAKEMASK(8, 9) + +#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) #if SIBYTE_HDR_FEATURE_CHIP(1480) #define M_MAC_TIMESTAMP _SB_MAKEMASK1(18) #endif -#define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) -#define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) -#define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) -#define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22) -#define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23) -#define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) -#define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) +#define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) +#define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) +#define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) +#define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22) +#define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23) +#define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) +#define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) -#define M_MAC_RESERVED3 _SB_MAKEMASK(6, 26) +#define M_MAC_RESERVED3 _SB_MAKEMASK(6, 26) -#define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) -#define M_MAC_HDX_EN _SB_MAKEMASK1(33) +#define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) +#define M_MAC_HDX_EN _SB_MAKEMASK1(33) -#define S_MAC_SPEED_SEL _SB_MAKE64(34) -#define M_MAC_SPEED_SEL _SB_MAKEMASK(2, S_MAC_SPEED_SEL) +#define S_MAC_SPEED_SEL _SB_MAKE64(34) +#define M_MAC_SPEED_SEL _SB_MAKEMASK(2, S_MAC_SPEED_SEL) #define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x, S_MAC_SPEED_SEL) #define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x, S_MAC_SPEED_SEL, M_MAC_SPEED_SEL) -#define K_MAC_SPEED_SEL_10MBPS 0 -#define K_MAC_SPEED_SEL_100MBPS 1 +#define K_MAC_SPEED_SEL_10MBPS 0 +#define K_MAC_SPEED_SEL_100MBPS 1 #define K_MAC_SPEED_SEL_1000MBPS 2 #define K_MAC_SPEED_SEL_RESERVED 3 -#define V_MAC_SPEED_SEL_10MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS) -#define V_MAC_SPEED_SEL_100MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS) +#define V_MAC_SPEED_SEL_10MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS) +#define V_MAC_SPEED_SEL_100MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS) #define V_MAC_SPEED_SEL_1000MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS) #define V_MAC_SPEED_SEL_RESERVED V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED) -#define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36) -#define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37) -#define M_MAC_FAST_SYNC _SB_MAKEMASK1(38) -#define M_MAC_SS_EN _SB_MAKEMASK1(39) +#define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36) +#define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37) +#define M_MAC_FAST_SYNC _SB_MAKEMASK1(38) +#define M_MAC_SS_EN _SB_MAKEMASK1(39) #define S_MAC_BYPASS_CFG _SB_MAKE64(40) -#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2, S_MAC_BYPASS_CFG) -#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG) -#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG) +#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2, S_MAC_BYPASS_CFG) +#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG) +#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG) #define K_MAC_BYPASS_GMII 0 -#define K_MAC_BYPASS_ENCODED 1 -#define K_MAC_BYPASS_SOP 2 -#define K_MAC_BYPASS_EOP 3 +#define K_MAC_BYPASS_ENCODED 1 +#define K_MAC_BYPASS_SOP 2 +#define K_MAC_BYPASS_EOP 3 -#define M_MAC_BYPASS_16 _SB_MAKEMASK1(42) +#define M_MAC_BYPASS_16 _SB_MAKEMASK1(42) #define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) @@ -137,30 +137,30 @@ #define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define S_MAC_BYPASS_IFG _SB_MAKE64(46) -#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8, S_MAC_BYPASS_IFG) +#define S_MAC_BYPASS_IFG _SB_MAKE64(46) +#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8, S_MAC_BYPASS_IFG) #define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_IFG) #define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_IFG, M_MAC_BYPASS_IFG) -#define K_MAC_FC_CMD_DISABLED 0 -#define K_MAC_FC_CMD_ENABLED 1 +#define K_MAC_FC_CMD_DISABLED 0 +#define K_MAC_FC_CMD_ENABLED 1 #define K_MAC_FC_CMD_ENAB_FALSECARR 2 -#define V_MAC_FC_CMD_DISABLED V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED) -#define V_MAC_FC_CMD_ENABLED V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED) +#define V_MAC_FC_CMD_DISABLED V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED) +#define V_MAC_FC_CMD_ENABLED V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED) #define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR) -#define M_MAC_FC_SEL _SB_MAKEMASK1(54) +#define M_MAC_FC_SEL _SB_MAKEMASK1(54) -#define S_MAC_FC_CMD _SB_MAKE64(55) -#define M_MAC_FC_CMD _SB_MAKEMASK(2, S_MAC_FC_CMD) -#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x, S_MAC_FC_CMD) -#define G_MAC_FC_CMD(x) _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD) +#define S_MAC_FC_CMD _SB_MAKE64(55) +#define M_MAC_FC_CMD _SB_MAKEMASK(2, S_MAC_FC_CMD) +#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x, S_MAC_FC_CMD) +#define G_MAC_FC_CMD(x) _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD) -#define S_MAC_RX_CH_SEL _SB_MAKE64(57) -#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7, S_MAC_RX_CH_SEL) -#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL) -#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL) +#define S_MAC_RX_CH_SEL _SB_MAKE64(57) +#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7, S_MAC_RX_CH_SEL) +#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL) +#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL) /* @@ -170,18 +170,18 @@ * Register: MAC_ENABLE_2 */ -#define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0) -#define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1) -#define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4) -#define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5) +#define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0) +#define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1) +#define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4) +#define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5) -#define M_MAC_PORT_RESET _SB_MAKEMASK1(8) +#define M_MAC_PORT_RESET _SB_MAKEMASK1(8) #if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x)) -#define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) -#define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) -#define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) -#define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) +#define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) +#define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) +#define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) +#define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) #endif /* @@ -203,13 +203,13 @@ #define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) #define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT0) -#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0) -#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0) +#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0) +#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0) #define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) #define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT1) -#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1) -#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1) +#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1) +#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1) /* * MAC Fifo Threshold registers (Table 9-14) @@ -218,53 +218,53 @@ * Register: MAC_THRSH_CFG_2 */ -#define S_MAC_TX_WR_THRSH _SB_MAKE64(0) +#define S_MAC_TX_WR_THRSH _SB_MAKE64(0) #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) -/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ -/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */ +/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ +/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */ #endif /* up to 1250 PASS1 */ #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH) +#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH) -#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH) +#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH) +#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH) -#define S_MAC_TX_RD_THRSH _SB_MAKE64(8) +#define S_MAC_TX_RD_THRSH _SB_MAKE64(8) #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) -/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ -/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */ +/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ +/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */ #endif /* up to 1250 PASS1 */ #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH) +#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH) -#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH) +#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH) +#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH) -#define S_MAC_TX_RL_THRSH _SB_MAKE64(16) -#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH) -#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH) -#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH) +#define S_MAC_TX_RL_THRSH _SB_MAKE64(16) +#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH) +#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH) +#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH) -#define S_MAC_RX_PL_THRSH _SB_MAKE64(24) -#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH) -#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH) -#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH) +#define S_MAC_RX_PL_THRSH _SB_MAKE64(24) +#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH) +#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH) +#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH) -#define S_MAC_RX_RD_THRSH _SB_MAKE64(32) -#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH) -#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH) -#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH) +#define S_MAC_RX_RD_THRSH _SB_MAKE64(32) +#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH) +#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH) +#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH) -#define S_MAC_RX_RL_THRSH _SB_MAKE64(40) -#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH) -#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH) -#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH) +#define S_MAC_RX_RL_THRSH _SB_MAKE64(40) +#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH) +#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH) +#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) -#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH) -#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH) -#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH) +#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) +#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH) +#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH) +#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ /* @@ -275,79 +275,79 @@ */ /* XXXCGD: ??? Unused in pass2? */ -#define S_MAC_IFG_RX _SB_MAKE64(0) -#define M_MAC_IFG_RX _SB_MAKEMASK(6, S_MAC_IFG_RX) -#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x, S_MAC_IFG_RX) -#define G_MAC_IFG_RX(x) _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX) +#define S_MAC_IFG_RX _SB_MAKE64(0) +#define M_MAC_IFG_RX _SB_MAKEMASK(6, S_MAC_IFG_RX) +#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x, S_MAC_IFG_RX) +#define G_MAC_IFG_RX(x) _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_MAC_PRE_LEN _SB_MAKE64(0) -#define M_MAC_PRE_LEN _SB_MAKEMASK(6, S_MAC_PRE_LEN) -#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x, S_MAC_PRE_LEN) -#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN) +#define S_MAC_PRE_LEN _SB_MAKE64(0) +#define M_MAC_PRE_LEN _SB_MAKEMASK(6, S_MAC_PRE_LEN) +#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x, S_MAC_PRE_LEN) +#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define S_MAC_IFG_TX _SB_MAKE64(6) -#define M_MAC_IFG_TX _SB_MAKEMASK(6, S_MAC_IFG_TX) -#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x, S_MAC_IFG_TX) -#define G_MAC_IFG_TX(x) _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX) - -#define S_MAC_IFG_THRSH _SB_MAKE64(12) -#define M_MAC_IFG_THRSH _SB_MAKEMASK(6, S_MAC_IFG_THRSH) -#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x, S_MAC_IFG_THRSH) -#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH) - -#define S_MAC_BACKOFF_SEL _SB_MAKE64(18) -#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL) -#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL) -#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL) - -#define S_MAC_LFSR_SEED _SB_MAKE64(22) -#define M_MAC_LFSR_SEED _SB_MAKEMASK(8, S_MAC_LFSR_SEED) -#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x, S_MAC_LFSR_SEED) -#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED) - -#define S_MAC_SLOT_SIZE _SB_MAKE64(30) -#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10, S_MAC_SLOT_SIZE) -#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE) -#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE) - -#define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) -#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ) -#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ) -#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ) - -#define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) -#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ) -#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ) -#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ) +#define S_MAC_IFG_TX _SB_MAKE64(6) +#define M_MAC_IFG_TX _SB_MAKEMASK(6, S_MAC_IFG_TX) +#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x, S_MAC_IFG_TX) +#define G_MAC_IFG_TX(x) _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX) + +#define S_MAC_IFG_THRSH _SB_MAKE64(12) +#define M_MAC_IFG_THRSH _SB_MAKEMASK(6, S_MAC_IFG_THRSH) +#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x, S_MAC_IFG_THRSH) +#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH) + +#define S_MAC_BACKOFF_SEL _SB_MAKE64(18) +#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL) +#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL) +#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL) + +#define S_MAC_LFSR_SEED _SB_MAKE64(22) +#define M_MAC_LFSR_SEED _SB_MAKEMASK(8, S_MAC_LFSR_SEED) +#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x, S_MAC_LFSR_SEED) +#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED) + +#define S_MAC_SLOT_SIZE _SB_MAKE64(30) +#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10, S_MAC_SLOT_SIZE) +#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE) +#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE) + +#define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) +#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ) +#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ) +#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ) + +#define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) +#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ) +#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ) +#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ) /* * These constants are used to configure the fields within the Frame * Configuration Register. */ -#define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ -#define K_MAC_IFG_RX_100 _SB_MAKE64(0) -#define K_MAC_IFG_RX_1000 _SB_MAKE64(0) +#define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ +#define K_MAC_IFG_RX_100 _SB_MAKE64(0) +#define K_MAC_IFG_RX_1000 _SB_MAKE64(0) -#define K_MAC_IFG_TX_10 _SB_MAKE64(20) -#define K_MAC_IFG_TX_100 _SB_MAKE64(20) -#define K_MAC_IFG_TX_1000 _SB_MAKE64(8) +#define K_MAC_IFG_TX_10 _SB_MAKE64(20) +#define K_MAC_IFG_TX_100 _SB_MAKE64(20) +#define K_MAC_IFG_TX_1000 _SB_MAKE64(8) -#define K_MAC_IFG_THRSH_10 _SB_MAKE64(4) -#define K_MAC_IFG_THRSH_100 _SB_MAKE64(4) -#define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0) +#define K_MAC_IFG_THRSH_10 _SB_MAKE64(4) +#define K_MAC_IFG_THRSH_100 _SB_MAKE64(4) +#define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0) -#define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0) -#define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0) -#define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0) +#define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0) +#define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0) +#define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0) -#define V_MAC_IFG_RX_10 V_MAC_IFG_RX(K_MAC_IFG_RX_10) +#define V_MAC_IFG_RX_10 V_MAC_IFG_RX(K_MAC_IFG_RX_10) #define V_MAC_IFG_RX_100 V_MAC_IFG_RX(K_MAC_IFG_RX_100) #define V_MAC_IFG_RX_1000 V_MAC_IFG_RX(K_MAC_IFG_RX_1000) -#define V_MAC_IFG_TX_10 V_MAC_IFG_TX(K_MAC_IFG_TX_10) +#define V_MAC_IFG_TX_10 V_MAC_IFG_TX(K_MAC_IFG_TX_10) #define V_MAC_IFG_TX_100 V_MAC_IFG_TX(K_MAC_IFG_TX_100) #define V_MAC_IFG_TX_1000 V_MAC_IFG_TX(K_MAC_IFG_TX_1000) @@ -359,15 +359,15 @@ #define V_MAC_SLOT_SIZE_100 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100) #define V_MAC_SLOT_SIZE_1000 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000) -#define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9) +#define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9) #define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64) #define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518) -#define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216) +#define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216) -#define V_MAC_MIN_FRAMESZ_FIFO V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO) +#define V_MAC_MIN_FRAMESZ_FIFO V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO) #define V_MAC_MIN_FRAMESZ_DEFAULT V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT) #define V_MAC_MAX_FRAMESZ_DEFAULT V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT) -#define V_MAC_MAX_FRAMESZ_JUMBO V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO) +#define V_MAC_MAX_FRAMESZ_JUMBO V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO) /* * MAC VLAN Tag Registers (Table 9-16) @@ -376,23 +376,23 @@ * Register: MAC_VLANTAG_2 */ -#define S_MAC_VLAN_TAG _SB_MAKE64(0) -#define M_MAC_VLAN_TAG _SB_MAKEMASK(32, S_MAC_VLAN_TAG) -#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x, S_MAC_VLAN_TAG) -#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG) +#define S_MAC_VLAN_TAG _SB_MAKE64(0) +#define M_MAC_VLAN_TAG _SB_MAKEMASK(32, S_MAC_VLAN_TAG) +#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x, S_MAC_VLAN_TAG) +#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) -#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET) -#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET) -#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET) +#define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) +#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET) +#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET) +#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET) -#define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) -#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET) -#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET) -#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET) +#define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) +#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET) +#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET) +#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET) -#define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) +#define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) #endif /* 1250 PASS3 || 112x PASS1 */ /* @@ -412,29 +412,29 @@ * on each channel. */ -#define S_MAC_RX_CH0 _SB_MAKE64(0) -#define S_MAC_RX_CH1 _SB_MAKE64(8) -#define S_MAC_TX_CH0 _SB_MAKE64(16) -#define S_MAC_TX_CH1 _SB_MAKE64(24) +#define S_MAC_RX_CH0 _SB_MAKE64(0) +#define S_MAC_RX_CH1 _SB_MAKE64(8) +#define S_MAC_TX_CH0 _SB_MAKE64(16) +#define S_MAC_TX_CH1 _SB_MAKE64(24) #define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */ -#define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */ +#define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */ /* - * These are the same as RX channel 0. The idea here + * These are the same as RX channel 0. The idea here * is that you'll use one of the "S_" things above * and pass just the six bits to a DMA-channel-specific ISR */ -#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8, 0) -#define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) -#define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) -#define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) -#define M_MAC_INT_HWM _SB_MAKEMASK1(3) -#define M_MAC_INT_LWM _SB_MAKEMASK1(4) -#define M_MAC_INT_DSCR _SB_MAKEMASK1(5) -#define M_MAC_INT_ERR _SB_MAKEMASK1(6) -#define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */ -#define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */ +#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8, 0) +#define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) +#define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) +#define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) +#define M_MAC_INT_HWM _SB_MAKEMASK1(3) +#define M_MAC_INT_LWM _SB_MAKEMASK1(4) +#define M_MAC_INT_DSCR _SB_MAKEMASK1(5) +#define M_MAC_INT_ERR _SB_MAKEMASK1(6) +#define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */ +#define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */ /* * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see @@ -442,34 +442,34 @@ */ #define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) -#define M_MAC_STATUS_CHANNEL(ch, txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_CHANNEL(ch, txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx)) #define M_MAC_STATUS_EOP_COUNT(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT, S_MAC_STATUS_CH_OFFSET(ch, txrx)) #define M_MAC_STATUS_EOP_TIMER(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_EOP_SEEN(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_HWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_LWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_DSCR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_ERR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_DZERO(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_DROP(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx)) -#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40) - - -#define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) -#define M_MAC_RX_OVRFL _SB_MAKEMASK1(41) -#define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42) -#define M_MAC_TX_OVRFL _SB_MAKEMASK1(43) -#define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44) -#define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45) -#define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46) +#define M_MAC_STATUS_EOP_SEEN(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_HWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_LWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_DSCR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_ERR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_DZERO(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_DROP(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx)) +#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40) + + +#define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) +#define M_MAC_RX_OVRFL _SB_MAKEMASK1(41) +#define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42) +#define M_MAC_TX_OVRFL _SB_MAKEMASK1(43) +#define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44) +#define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45) +#define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */ +#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */ #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#define S_MAC_COUNTER_ADDR _SB_MAKE64(47) -#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR) -#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR) -#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR) +#define S_MAC_COUNTER_ADDR _SB_MAKE64(47) +#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR) +#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR) +#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) @@ -482,42 +482,42 @@ * Register: MAC_FIFO_PTRS_2 */ -#define S_MAC_TX_WRPTR _SB_MAKE64(0) -#define M_MAC_TX_WRPTR _SB_MAKEMASK(6, S_MAC_TX_WRPTR) -#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_WRPTR) -#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR) +#define S_MAC_TX_WRPTR _SB_MAKE64(0) +#define M_MAC_TX_WRPTR _SB_MAKEMASK(6, S_MAC_TX_WRPTR) +#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_WRPTR) +#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR) -#define S_MAC_TX_RDPTR _SB_MAKE64(8) -#define M_MAC_TX_RDPTR _SB_MAKEMASK(6, S_MAC_TX_RDPTR) -#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_RDPTR) -#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR) +#define S_MAC_TX_RDPTR _SB_MAKE64(8) +#define M_MAC_TX_RDPTR _SB_MAKEMASK(6, S_MAC_TX_RDPTR) +#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_RDPTR) +#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR) -#define S_MAC_RX_WRPTR _SB_MAKE64(16) -#define M_MAC_RX_WRPTR _SB_MAKEMASK(6, S_MAC_RX_WRPTR) -#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_WRPTR) -#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR) +#define S_MAC_RX_WRPTR _SB_MAKE64(16) +#define M_MAC_RX_WRPTR _SB_MAKEMASK(6, S_MAC_RX_WRPTR) +#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_WRPTR) +#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR) -#define S_MAC_RX_RDPTR _SB_MAKE64(24) -#define M_MAC_RX_RDPTR _SB_MAKEMASK(6, S_MAC_RX_RDPTR) -#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_RDPTR) -#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR) +#define S_MAC_RX_RDPTR _SB_MAKE64(24) +#define M_MAC_RX_RDPTR _SB_MAKEMASK(6, S_MAC_RX_RDPTR) +#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_RDPTR) +#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR) /* - * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] + * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] * Register: MAC_EOPCNT_0 * Register: MAC_EOPCNT_1 * Register: MAC_EOPCNT_2 */ -#define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) -#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER) -#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER) -#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER) +#define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) +#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER) +#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER) +#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER) -#define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) -#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER) -#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER) -#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER) +#define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) +#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER) +#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER) +#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER) /* * MAC Receive Address Filter Exact Match Registers (Table 9-21) @@ -562,27 +562,27 @@ * Register: MAC_TYPE_CFG_2 */ -#define S_TYPECFG_TYPESIZE _SB_MAKE64(16) +#define S_TYPECFG_TYPESIZE _SB_MAKE64(16) #define S_TYPECFG_TYPE0 _SB_MAKE64(0) -#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16, S_TYPECFG_TYPE0) -#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE0) -#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0) +#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16, S_TYPECFG_TYPE0) +#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE0) +#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0) #define S_TYPECFG_TYPE1 _SB_MAKE64(0) -#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16, S_TYPECFG_TYPE1) -#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE1) -#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1) +#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16, S_TYPECFG_TYPE1) +#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE1) +#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1) #define S_TYPECFG_TYPE2 _SB_MAKE64(0) -#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16, S_TYPECFG_TYPE2) -#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE2) -#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2) +#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16, S_TYPECFG_TYPE2) +#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE2) +#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2) #define S_TYPECFG_TYPE3 _SB_MAKE64(0) -#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16, S_TYPECFG_TYPE3) -#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE3) -#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3) +#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16, S_TYPECFG_TYPE3) +#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE3) +#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3) /* * MAC Receive Address Filter Control Registers (Table 9-24) @@ -591,38 +591,38 @@ * Register: MAC_ADFILTER_CFG_2 */ -#define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0) -#define M_MAC_UCAST_EN _SB_MAKEMASK1(1) -#define M_MAC_UCAST_INV _SB_MAKEMASK1(2) -#define M_MAC_MCAST_EN _SB_MAKEMASK1(3) -#define M_MAC_MCAST_INV _SB_MAKEMASK1(4) -#define M_MAC_BCAST_EN _SB_MAKEMASK1(5) -#define M_MAC_DIRECT_INV _SB_MAKEMASK1(6) +#define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0) +#define M_MAC_UCAST_EN _SB_MAKEMASK1(1) +#define M_MAC_UCAST_INV _SB_MAKEMASK1(2) +#define M_MAC_MCAST_EN _SB_MAKEMASK1(3) +#define M_MAC_MCAST_INV _SB_MAKEMASK1(4) +#define M_MAC_BCAST_EN _SB_MAKEMASK1(5) +#define M_MAC_DIRECT_INV _SB_MAKEMASK1(6) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) -#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET) +#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) +#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET) #define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_IPHDR_OFFSET) #define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x, S_MAC_IPHDR_OFFSET, M_MAC_IPHDR_OFFSET) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) -#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET) +#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) +#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET) #define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_CRC_OFFSET) #define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_CRC_OFFSET, M_MAC_RX_CRC_OFFSET) -#define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) -#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET) +#define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) +#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET) #define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_PKT_OFFSET) #define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_PKT_OFFSET, M_MAC_RX_PKT_OFFSET) #define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32) #define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33) -#define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) -#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL) +#define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) +#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL) #define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_MSN_SEL) #define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_MSN_SEL, M_MAC_RX_CH_MSN_SEL) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ diff --git a/arch/mips/include/asm/sibyte/sb1250_mc.h b/arch/mips/include/asm/sibyte/sb1250_mc.h index 15048dcaf22..8368e411131 100644 --- a/arch/mips/include/asm/sibyte/sb1250_mc.h +++ b/arch/mips/include/asm/sibyte/sb1250_mc.h @@ -1,7 +1,7 @@ /* ********************************************************************* * SB1250 Board Support Package * - * Memory Controller constants File: sb1250_mc.h + * Memory Controller constants File: sb1250_mc.h * * This module contains constants and macros useful for * programming the memory controller. @@ -39,96 +39,96 @@ * Memory Channel Config Register (table 6-14) */ -#define S_MC_RESERVED0 0 -#define M_MC_RESERVED0 _SB_MAKEMASK(8, S_MC_RESERVED0) +#define S_MC_RESERVED0 0 +#define M_MC_RESERVED0 _SB_MAKEMASK(8, S_MC_RESERVED0) -#define S_MC_CHANNEL_SEL 8 -#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8, S_MC_CHANNEL_SEL) -#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL) -#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL) +#define S_MC_CHANNEL_SEL 8 +#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8, S_MC_CHANNEL_SEL) +#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL) +#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL) -#define S_MC_BANK0_MAP 16 -#define M_MC_BANK0_MAP _SB_MAKEMASK(4, S_MC_BANK0_MAP) -#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK0_MAP) -#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP) +#define S_MC_BANK0_MAP 16 +#define M_MC_BANK0_MAP _SB_MAKEMASK(4, S_MC_BANK0_MAP) +#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK0_MAP) +#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP) -#define K_MC_BANK0_MAP_DEFAULT 0x00 -#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT) +#define K_MC_BANK0_MAP_DEFAULT 0x00 +#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT) -#define S_MC_BANK1_MAP 20 -#define M_MC_BANK1_MAP _SB_MAKEMASK(4, S_MC_BANK1_MAP) -#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK1_MAP) -#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP) +#define S_MC_BANK1_MAP 20 +#define M_MC_BANK1_MAP _SB_MAKEMASK(4, S_MC_BANK1_MAP) +#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK1_MAP) +#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP) -#define K_MC_BANK1_MAP_DEFAULT 0x08 -#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT) +#define K_MC_BANK1_MAP_DEFAULT 0x08 +#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT) -#define S_MC_BANK2_MAP 24 -#define M_MC_BANK2_MAP _SB_MAKEMASK(4, S_MC_BANK2_MAP) -#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK2_MAP) -#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP) +#define S_MC_BANK2_MAP 24 +#define M_MC_BANK2_MAP _SB_MAKEMASK(4, S_MC_BANK2_MAP) +#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK2_MAP) +#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP) -#define K_MC_BANK2_MAP_DEFAULT 0x09 -#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT) +#define K_MC_BANK2_MAP_DEFAULT 0x09 +#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT) -#define S_MC_BANK3_MAP 28 -#define M_MC_BANK3_MAP _SB_MAKEMASK(4, S_MC_BANK3_MAP) -#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK3_MAP) -#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP) +#define S_MC_BANK3_MAP 28 +#define M_MC_BANK3_MAP _SB_MAKEMASK(4, S_MC_BANK3_MAP) +#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK3_MAP) +#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP) -#define K_MC_BANK3_MAP_DEFAULT 0x0C -#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT) +#define K_MC_BANK3_MAP_DEFAULT 0x0C +#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT) -#define M_MC_RESERVED1 _SB_MAKEMASK(8, 32) +#define M_MC_RESERVED1 _SB_MAKEMASK(8, 32) #define S_MC_QUEUE_SIZE 40 -#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4, S_MC_QUEUE_SIZE) -#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE) -#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE) -#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A) - -#define S_MC_AGE_LIMIT 44 -#define M_MC_AGE_LIMIT _SB_MAKEMASK(4, S_MC_AGE_LIMIT) -#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x, S_MC_AGE_LIMIT) -#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT) -#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8) - -#define S_MC_WR_LIMIT 48 -#define M_MC_WR_LIMIT _SB_MAKEMASK(4, S_MC_WR_LIMIT) -#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x, S_MC_WR_LIMIT) -#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT) -#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) +#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4, S_MC_QUEUE_SIZE) +#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE) +#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE) +#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A) + +#define S_MC_AGE_LIMIT 44 +#define M_MC_AGE_LIMIT _SB_MAKEMASK(4, S_MC_AGE_LIMIT) +#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x, S_MC_AGE_LIMIT) +#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT) +#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8) + +#define S_MC_WR_LIMIT 48 +#define M_MC_WR_LIMIT _SB_MAKEMASK(4, S_MC_WR_LIMIT) +#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x, S_MC_WR_LIMIT) +#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT) +#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) #define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52) -#define M_MC_RESERVED2 _SB_MAKEMASK(3, 53) +#define M_MC_RESERVED2 _SB_MAKEMASK(3, 53) -#define S_MC_CS_MODE 56 -#define M_MC_CS_MODE _SB_MAKEMASK(4, S_MC_CS_MODE) -#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_MC_CS_MODE) -#define G_MC_CS_MODE(x) _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE) +#define S_MC_CS_MODE 56 +#define M_MC_CS_MODE _SB_MAKEMASK(4, S_MC_CS_MODE) +#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_MC_CS_MODE) +#define G_MC_CS_MODE(x) _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE) -#define K_MC_CS_MODE_MSB_CS 0 -#define K_MC_CS_MODE_INTLV_CS 15 +#define K_MC_CS_MODE_MSB_CS 0 +#define K_MC_CS_MODE_INTLV_CS 15 #define K_MC_CS_MODE_MIXED_CS_10 12 #define K_MC_CS_MODE_MIXED_CS_30 6 #define K_MC_CS_MODE_MIXED_CS_32 3 -#define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS) -#define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS) +#define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS) +#define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS) #define V_MC_CS_MODE_MIXED_CS_10 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10) #define V_MC_CS_MODE_MIXED_CS_30 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30) #define V_MC_CS_MODE_MIXED_CS_32 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32) -#define M_MC_ECC_DISABLE _SB_MAKEMASK1(60) -#define M_MC_BERR_DISABLE _SB_MAKEMASK1(61) -#define M_MC_FORCE_SEQ _SB_MAKEMASK1(62) -#define M_MC_DEBUG _SB_MAKEMASK1(63) +#define M_MC_ECC_DISABLE _SB_MAKEMASK1(60) +#define M_MC_BERR_DISABLE _SB_MAKEMASK1(61) +#define M_MC_FORCE_SEQ _SB_MAKEMASK1(62) +#define M_MC_DEBUG _SB_MAKEMASK1(63) -#define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \ +#define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \ V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \ V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \ - M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT + M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT /* @@ -137,96 +137,96 @@ * Note: this field has been updated to be consistent with the errata to 0.2 */ -#define S_MC_CLK_RATIO 0 -#define M_MC_CLK_RATIO _SB_MAKEMASK(4, S_MC_CLK_RATIO) -#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_MC_CLK_RATIO) -#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO) +#define S_MC_CLK_RATIO 0 +#define M_MC_CLK_RATIO _SB_MAKEMASK(4, S_MC_CLK_RATIO) +#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_MC_CLK_RATIO) +#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO) -#define K_MC_CLK_RATIO_2X 4 -#define K_MC_CLK_RATIO_25X 5 -#define K_MC_CLK_RATIO_3X 6 -#define K_MC_CLK_RATIO_35X 7 -#define K_MC_CLK_RATIO_4X 8 +#define K_MC_CLK_RATIO_2X 4 +#define K_MC_CLK_RATIO_25X 5 +#define K_MC_CLK_RATIO_3X 6 +#define K_MC_CLK_RATIO_35X 7 +#define K_MC_CLK_RATIO_4X 8 #define K_MC_CLK_RATIO_45X 9 #define V_MC_CLK_RATIO_2X V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X) -#define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X) -#define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X) -#define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X) -#define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X) -#define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X) -#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X - -#define S_MC_REF_RATE 8 -#define M_MC_REF_RATE _SB_MAKEMASK(8, S_MC_REF_RATE) -#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_MC_REF_RATE) -#define G_MC_REF_RATE(x) _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE) - -#define K_MC_REF_RATE_100MHz 0x62 -#define K_MC_REF_RATE_133MHz 0x81 -#define K_MC_REF_RATE_200MHz 0xC4 - -#define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz) -#define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz) -#define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz) -#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz - -#define S_MC_CLOCK_DRIVE 16 -#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE) -#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE) -#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE) +#define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X) +#define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X) +#define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X) +#define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X) +#define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X) +#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X + +#define S_MC_REF_RATE 8 +#define M_MC_REF_RATE _SB_MAKEMASK(8, S_MC_REF_RATE) +#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_MC_REF_RATE) +#define G_MC_REF_RATE(x) _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE) + +#define K_MC_REF_RATE_100MHz 0x62 +#define K_MC_REF_RATE_133MHz 0x81 +#define K_MC_REF_RATE_200MHz 0xC4 + +#define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz) +#define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz) +#define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz) +#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz + +#define S_MC_CLOCK_DRIVE 16 +#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE) +#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE) +#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE) #define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF) -#define S_MC_DATA_DRIVE 20 -#define M_MC_DATA_DRIVE _SB_MAKEMASK(4, S_MC_DATA_DRIVE) -#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x, S_MC_DATA_DRIVE) -#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE) -#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0) +#define S_MC_DATA_DRIVE 20 +#define M_MC_DATA_DRIVE _SB_MAKEMASK(4, S_MC_DATA_DRIVE) +#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x, S_MC_DATA_DRIVE) +#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE) +#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0) -#define S_MC_ADDR_DRIVE 24 -#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4, S_MC_ADDR_DRIVE) -#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE) -#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE) -#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0) +#define S_MC_ADDR_DRIVE 24 +#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4, S_MC_ADDR_DRIVE) +#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE) +#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE) +#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_MC_REF_DISABLE _SB_MAKEMASK1(30) +#define M_MC_REF_DISABLE _SB_MAKEMASK1(30) #endif /* 1250 PASS3 || 112x PASS1 */ -#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31) - -#define S_MC_DQI_SKEW 32 -#define M_MC_DQI_SKEW _SB_MAKEMASK(8, S_MC_DQI_SKEW) -#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQI_SKEW) -#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW) -#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0) - -#define S_MC_DQO_SKEW 40 -#define M_MC_DQO_SKEW _SB_MAKEMASK(8, S_MC_DQO_SKEW) -#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQO_SKEW) -#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW) -#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0) - -#define S_MC_ADDR_SKEW 48 -#define M_MC_ADDR_SKEW _SB_MAKEMASK(8, S_MC_ADDR_SKEW) -#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x, S_MC_ADDR_SKEW) -#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW) -#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F) - -#define S_MC_DLL_DEFAULT 56 -#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8, S_MC_DLL_DEFAULT) -#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT) -#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT) +#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31) + +#define S_MC_DQI_SKEW 32 +#define M_MC_DQI_SKEW _SB_MAKEMASK(8, S_MC_DQI_SKEW) +#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQI_SKEW) +#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW) +#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0) + +#define S_MC_DQO_SKEW 40 +#define M_MC_DQO_SKEW _SB_MAKEMASK(8, S_MC_DQO_SKEW) +#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQO_SKEW) +#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW) +#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0) + +#define S_MC_ADDR_SKEW 48 +#define M_MC_ADDR_SKEW _SB_MAKEMASK(8, S_MC_ADDR_SKEW) +#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x, S_MC_ADDR_SKEW) +#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW) +#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F) + +#define S_MC_DLL_DEFAULT 56 +#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8, S_MC_DLL_DEFAULT) +#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT) +#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT) #define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10) -#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \ - V_MC_ADDR_SKEW_DEFAULT | \ - V_MC_DQO_SKEW_DEFAULT | \ - V_MC_DQI_SKEW_DEFAULT | \ - V_MC_ADDR_DRIVE_DEFAULT | \ - V_MC_DATA_DRIVE_DEFAULT | \ - V_MC_CLOCK_DRIVE_DEFAULT | \ - V_MC_REF_RATE_DEFAULT +#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \ + V_MC_ADDR_SKEW_DEFAULT | \ + V_MC_DQO_SKEW_DEFAULT | \ + V_MC_DQI_SKEW_DEFAULT | \ + V_MC_ADDR_DRIVE_DEFAULT | \ + V_MC_DATA_DRIVE_DEFAULT | \ + V_MC_CLOCK_DRIVE_DEFAULT | \ + V_MC_REF_RATE_DEFAULT @@ -234,68 +234,68 @@ * DRAM Command Register (Table 6-13) */ -#define S_MC_COMMAND 0 -#define M_MC_COMMAND _SB_MAKEMASK(4, S_MC_COMMAND) -#define V_MC_COMMAND(x) _SB_MAKEVALUE(x, S_MC_COMMAND) -#define G_MC_COMMAND(x) _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND) - -#define K_MC_COMMAND_EMRS 0 -#define K_MC_COMMAND_MRS 1 -#define K_MC_COMMAND_PRE 2 -#define K_MC_COMMAND_AR 3 -#define K_MC_COMMAND_SETRFSH 4 -#define K_MC_COMMAND_CLRRFSH 5 -#define K_MC_COMMAND_SETPWRDN 6 -#define K_MC_COMMAND_CLRPWRDN 7 - -#define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS) -#define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS) -#define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE) -#define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR) -#define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH) -#define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH) -#define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN) -#define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN) - -#define M_MC_CS0 _SB_MAKEMASK1(4) -#define M_MC_CS1 _SB_MAKEMASK1(5) -#define M_MC_CS2 _SB_MAKEMASK1(6) -#define M_MC_CS3 _SB_MAKEMASK1(7) +#define S_MC_COMMAND 0 +#define M_MC_COMMAND _SB_MAKEMASK(4, S_MC_COMMAND) +#define V_MC_COMMAND(x) _SB_MAKEVALUE(x, S_MC_COMMAND) +#define G_MC_COMMAND(x) _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND) + +#define K_MC_COMMAND_EMRS 0 +#define K_MC_COMMAND_MRS 1 +#define K_MC_COMMAND_PRE 2 +#define K_MC_COMMAND_AR 3 +#define K_MC_COMMAND_SETRFSH 4 +#define K_MC_COMMAND_CLRRFSH 5 +#define K_MC_COMMAND_SETPWRDN 6 +#define K_MC_COMMAND_CLRPWRDN 7 + +#define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS) +#define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS) +#define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE) +#define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR) +#define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH) +#define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH) +#define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN) +#define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN) + +#define M_MC_CS0 _SB_MAKEMASK1(4) +#define M_MC_CS1 _SB_MAKEMASK1(5) +#define M_MC_CS2 _SB_MAKEMASK1(6) +#define M_MC_CS3 _SB_MAKEMASK1(7) /* * DRAM Mode Register (Table 6-14) */ -#define S_MC_EMODE 0 -#define M_MC_EMODE _SB_MAKEMASK(15, S_MC_EMODE) -#define V_MC_EMODE(x) _SB_MAKEVALUE(x, S_MC_EMODE) -#define G_MC_EMODE(x) _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE) -#define V_MC_EMODE_DEFAULT V_MC_EMODE(0) - -#define S_MC_MODE 16 -#define M_MC_MODE _SB_MAKEMASK(15, S_MC_MODE) -#define V_MC_MODE(x) _SB_MAKEVALUE(x, S_MC_MODE) -#define G_MC_MODE(x) _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE) -#define V_MC_MODE_DEFAULT V_MC_MODE(0x22) - -#define S_MC_DRAM_TYPE 32 -#define M_MC_DRAM_TYPE _SB_MAKEMASK(3, S_MC_DRAM_TYPE) -#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_MC_DRAM_TYPE) -#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE) - -#define K_MC_DRAM_TYPE_JEDEC 0 -#define K_MC_DRAM_TYPE_FCRAM 1 +#define S_MC_EMODE 0 +#define M_MC_EMODE _SB_MAKEMASK(15, S_MC_EMODE) +#define V_MC_EMODE(x) _SB_MAKEVALUE(x, S_MC_EMODE) +#define G_MC_EMODE(x) _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE) +#define V_MC_EMODE_DEFAULT V_MC_EMODE(0) + +#define S_MC_MODE 16 +#define M_MC_MODE _SB_MAKEMASK(15, S_MC_MODE) +#define V_MC_MODE(x) _SB_MAKEVALUE(x, S_MC_MODE) +#define G_MC_MODE(x) _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE) +#define V_MC_MODE_DEFAULT V_MC_MODE(0x22) + +#define S_MC_DRAM_TYPE 32 +#define M_MC_DRAM_TYPE _SB_MAKEMASK(3, S_MC_DRAM_TYPE) +#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_MC_DRAM_TYPE) +#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE) + +#define K_MC_DRAM_TYPE_JEDEC 0 +#define K_MC_DRAM_TYPE_FCRAM 1 #define K_MC_DRAM_TYPE_SGRAM 2 -#define V_MC_DRAM_TYPE_JEDEC V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC) -#define V_MC_DRAM_TYPE_FCRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM) -#define V_MC_DRAM_TYPE_SGRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM) +#define V_MC_DRAM_TYPE_JEDEC V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC) +#define V_MC_DRAM_TYPE_FCRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM) +#define V_MC_DRAM_TYPE_SGRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM) #define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36) -#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(37) +#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36) +#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(37) #endif /* 1250 PASS3 || 112x PASS1 */ @@ -308,99 +308,99 @@ #define M_MC_r2wIDLE_TWOCYCLES _SB_MAKEMASK1(61) #define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62) -#define S_MC_tFIFO 56 -#define M_MC_tFIFO _SB_MAKEMASK(4, S_MC_tFIFO) -#define V_MC_tFIFO(x) _SB_MAKEVALUE(x, S_MC_tFIFO) -#define G_MC_tFIFO(x) _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO) -#define K_MC_tFIFO_DEFAULT 1 -#define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) +#define S_MC_tFIFO 56 +#define M_MC_tFIFO _SB_MAKEMASK(4, S_MC_tFIFO) +#define V_MC_tFIFO(x) _SB_MAKEVALUE(x, S_MC_tFIFO) +#define G_MC_tFIFO(x) _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO) +#define K_MC_tFIFO_DEFAULT 1 +#define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) -#define S_MC_tRFC 52 -#define M_MC_tRFC _SB_MAKEMASK(4, S_MC_tRFC) -#define V_MC_tRFC(x) _SB_MAKEVALUE(x, S_MC_tRFC) -#define G_MC_tRFC(x) _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC) -#define K_MC_tRFC_DEFAULT 12 -#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) +#define S_MC_tRFC 52 +#define M_MC_tRFC _SB_MAKEMASK(4, S_MC_tRFC) +#define V_MC_tRFC(x) _SB_MAKEVALUE(x, S_MC_tRFC) +#define G_MC_tRFC(x) _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC) +#define K_MC_tRFC_DEFAULT 12 +#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) #if SIBYTE_HDR_FEATURE(1250, PASS3) -#define M_MC_tRFC_PLUS16 _SB_MAKEMASK1(51) /* 1250C3 and later. */ +#define M_MC_tRFC_PLUS16 _SB_MAKEMASK1(51) /* 1250C3 and later. */ #endif -#define S_MC_tCwCr 40 -#define M_MC_tCwCr _SB_MAKEMASK(4, S_MC_tCwCr) -#define V_MC_tCwCr(x) _SB_MAKEVALUE(x, S_MC_tCwCr) -#define G_MC_tCwCr(x) _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr) -#define K_MC_tCwCr_DEFAULT 4 -#define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT) - -#define S_MC_tRCr 28 -#define M_MC_tRCr _SB_MAKEMASK(4, S_MC_tRCr) -#define V_MC_tRCr(x) _SB_MAKEVALUE(x, S_MC_tRCr) -#define G_MC_tRCr(x) _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr) -#define K_MC_tRCr_DEFAULT 9 -#define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT) - -#define S_MC_tRCw 24 -#define M_MC_tRCw _SB_MAKEMASK(4, S_MC_tRCw) -#define V_MC_tRCw(x) _SB_MAKEVALUE(x, S_MC_tRCw) -#define G_MC_tRCw(x) _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw) -#define K_MC_tRCw_DEFAULT 10 -#define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT) - -#define S_MC_tRRD 20 -#define M_MC_tRRD _SB_MAKEMASK(4, S_MC_tRRD) -#define V_MC_tRRD(x) _SB_MAKEVALUE(x, S_MC_tRRD) -#define G_MC_tRRD(x) _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD) -#define K_MC_tRRD_DEFAULT 2 -#define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT) - -#define S_MC_tRP 16 -#define M_MC_tRP _SB_MAKEMASK(4, S_MC_tRP) -#define V_MC_tRP(x) _SB_MAKEVALUE(x, S_MC_tRP) -#define G_MC_tRP(x) _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP) -#define K_MC_tRP_DEFAULT 4 -#define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT) - -#define S_MC_tCwD 8 -#define M_MC_tCwD _SB_MAKEMASK(4, S_MC_tCwD) -#define V_MC_tCwD(x) _SB_MAKEVALUE(x, S_MC_tCwD) -#define G_MC_tCwD(x) _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD) -#define K_MC_tCwD_DEFAULT 1 -#define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT) - -#define M_tCrDh _SB_MAKEMASK1(7) +#define S_MC_tCwCr 40 +#define M_MC_tCwCr _SB_MAKEMASK(4, S_MC_tCwCr) +#define V_MC_tCwCr(x) _SB_MAKEVALUE(x, S_MC_tCwCr) +#define G_MC_tCwCr(x) _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr) +#define K_MC_tCwCr_DEFAULT 4 +#define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT) + +#define S_MC_tRCr 28 +#define M_MC_tRCr _SB_MAKEMASK(4, S_MC_tRCr) +#define V_MC_tRCr(x) _SB_MAKEVALUE(x, S_MC_tRCr) +#define G_MC_tRCr(x) _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr) +#define K_MC_tRCr_DEFAULT 9 +#define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT) + +#define S_MC_tRCw 24 +#define M_MC_tRCw _SB_MAKEMASK(4, S_MC_tRCw) +#define V_MC_tRCw(x) _SB_MAKEVALUE(x, S_MC_tRCw) +#define G_MC_tRCw(x) _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw) +#define K_MC_tRCw_DEFAULT 10 +#define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT) + +#define S_MC_tRRD 20 +#define M_MC_tRRD _SB_MAKEMASK(4, S_MC_tRRD) +#define V_MC_tRRD(x) _SB_MAKEVALUE(x, S_MC_tRRD) +#define G_MC_tRRD(x) _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD) +#define K_MC_tRRD_DEFAULT 2 +#define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT) + +#define S_MC_tRP 16 +#define M_MC_tRP _SB_MAKEMASK(4, S_MC_tRP) +#define V_MC_tRP(x) _SB_MAKEVALUE(x, S_MC_tRP) +#define G_MC_tRP(x) _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP) +#define K_MC_tRP_DEFAULT 4 +#define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT) + +#define S_MC_tCwD 8 +#define M_MC_tCwD _SB_MAKEMASK(4, S_MC_tCwD) +#define V_MC_tCwD(x) _SB_MAKEVALUE(x, S_MC_tCwD) +#define G_MC_tCwD(x) _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD) +#define K_MC_tCwD_DEFAULT 1 +#define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT) + +#define M_tCrDh _SB_MAKEMASK1(7) #define M_MC_tCrDh M_tCrDh -#define S_MC_tCrD 4 -#define M_MC_tCrD _SB_MAKEMASK(3, S_MC_tCrD) -#define V_MC_tCrD(x) _SB_MAKEVALUE(x, S_MC_tCrD) -#define G_MC_tCrD(x) _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD) -#define K_MC_tCrD_DEFAULT 2 -#define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT) - -#define S_MC_tRCD 0 -#define M_MC_tRCD _SB_MAKEMASK(4, S_MC_tRCD) -#define V_MC_tRCD(x) _SB_MAKEVALUE(x, S_MC_tRCD) -#define G_MC_tRCD(x) _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD) -#define K_MC_tRCD_DEFAULT 3 -#define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT) - -#define V_MC_TIMING_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \ - V_MC_tRFC(K_MC_tRFC_DEFAULT) | \ - V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \ - V_MC_tRCr(K_MC_tRCr_DEFAULT) | \ - V_MC_tRCw(K_MC_tRCw_DEFAULT) | \ - V_MC_tRRD(K_MC_tRRD_DEFAULT) | \ - V_MC_tRP(K_MC_tRP_DEFAULT) | \ - V_MC_tCwD(K_MC_tCwD_DEFAULT) | \ - V_MC_tCrD(K_MC_tCrD_DEFAULT) | \ - V_MC_tRCD(K_MC_tRCD_DEFAULT) | \ - M_MC_r2rIDLE_TWOCYCLES +#define S_MC_tCrD 4 +#define M_MC_tCrD _SB_MAKEMASK(3, S_MC_tCrD) +#define V_MC_tCrD(x) _SB_MAKEVALUE(x, S_MC_tCrD) +#define G_MC_tCrD(x) _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD) +#define K_MC_tCrD_DEFAULT 2 +#define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT) + +#define S_MC_tRCD 0 +#define M_MC_tRCD _SB_MAKEMASK(4, S_MC_tRCD) +#define V_MC_tRCD(x) _SB_MAKEVALUE(x, S_MC_tRCD) +#define G_MC_tRCD(x) _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD) +#define K_MC_tRCD_DEFAULT 3 +#define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT) + +#define V_MC_TIMING_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \ + V_MC_tRFC(K_MC_tRFC_DEFAULT) | \ + V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \ + V_MC_tRCr(K_MC_tRCr_DEFAULT) | \ + V_MC_tRCw(K_MC_tRCw_DEFAULT) | \ + V_MC_tRRD(K_MC_tRRD_DEFAULT) | \ + V_MC_tRP(K_MC_tRP_DEFAULT) | \ + V_MC_tCwD(K_MC_tCwD_DEFAULT) | \ + V_MC_tCrD(K_MC_tCrD_DEFAULT) | \ + V_MC_tRCD(K_MC_tRCD_DEFAULT) | \ + M_MC_r2rIDLE_TWOCYCLES /* * Errata says these are not the default - * M_MC_w2rIDLE_TWOCYCLES | \ - * M_MC_r2wIDLE_TWOCYCLES | \ + * M_MC_w2rIDLE_TWOCYCLES | \ + * M_MC_r2wIDLE_TWOCYCLES | \ */ @@ -408,143 +408,143 @@ * Chip Select Start Address Register (Table 6-17) */ -#define S_MC_CS0_START 0 -#define M_MC_CS0_START _SB_MAKEMASK(16, S_MC_CS0_START) -#define V_MC_CS0_START(x) _SB_MAKEVALUE(x, S_MC_CS0_START) -#define G_MC_CS0_START(x) _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START) +#define S_MC_CS0_START 0 +#define M_MC_CS0_START _SB_MAKEMASK(16, S_MC_CS0_START) +#define V_MC_CS0_START(x) _SB_MAKEVALUE(x, S_MC_CS0_START) +#define G_MC_CS0_START(x) _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START) -#define S_MC_CS1_START 16 -#define M_MC_CS1_START _SB_MAKEMASK(16, S_MC_CS1_START) -#define V_MC_CS1_START(x) _SB_MAKEVALUE(x, S_MC_CS1_START) -#define G_MC_CS1_START(x) _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START) +#define S_MC_CS1_START 16 +#define M_MC_CS1_START _SB_MAKEMASK(16, S_MC_CS1_START) +#define V_MC_CS1_START(x) _SB_MAKEVALUE(x, S_MC_CS1_START) +#define G_MC_CS1_START(x) _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START) -#define S_MC_CS2_START 32 -#define M_MC_CS2_START _SB_MAKEMASK(16, S_MC_CS2_START) -#define V_MC_CS2_START(x) _SB_MAKEVALUE(x, S_MC_CS2_START) -#define G_MC_CS2_START(x) _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START) +#define S_MC_CS2_START 32 +#define M_MC_CS2_START _SB_MAKEMASK(16, S_MC_CS2_START) +#define V_MC_CS2_START(x) _SB_MAKEVALUE(x, S_MC_CS2_START) +#define G_MC_CS2_START(x) _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START) -#define S_MC_CS3_START 48 -#define M_MC_CS3_START _SB_MAKEMASK(16, S_MC_CS3_START) -#define V_MC_CS3_START(x) _SB_MAKEVALUE(x, S_MC_CS3_START) -#define G_MC_CS3_START(x) _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START) +#define S_MC_CS3_START 48 +#define M_MC_CS3_START _SB_MAKEMASK(16, S_MC_CS3_START) +#define V_MC_CS3_START(x) _SB_MAKEVALUE(x, S_MC_CS3_START) +#define G_MC_CS3_START(x) _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START) /* * Chip Select End Address Register (Table 6-18) */ -#define S_MC_CS0_END 0 -#define M_MC_CS0_END _SB_MAKEMASK(16, S_MC_CS0_END) -#define V_MC_CS0_END(x) _SB_MAKEVALUE(x, S_MC_CS0_END) -#define G_MC_CS0_END(x) _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END) +#define S_MC_CS0_END 0 +#define M_MC_CS0_END _SB_MAKEMASK(16, S_MC_CS0_END) +#define V_MC_CS0_END(x) _SB_MAKEVALUE(x, S_MC_CS0_END) +#define G_MC_CS0_END(x) _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END) -#define S_MC_CS1_END 16 -#define M_MC_CS1_END _SB_MAKEMASK(16, S_MC_CS1_END) -#define V_MC_CS1_END(x) _SB_MAKEVALUE(x, S_MC_CS1_END) -#define G_MC_CS1_END(x) _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END) +#define S_MC_CS1_END 16 +#define M_MC_CS1_END _SB_MAKEMASK(16, S_MC_CS1_END) +#define V_MC_CS1_END(x) _SB_MAKEVALUE(x, S_MC_CS1_END) +#define G_MC_CS1_END(x) _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END) -#define S_MC_CS2_END 32 -#define M_MC_CS2_END _SB_MAKEMASK(16, S_MC_CS2_END) -#define V_MC_CS2_END(x) _SB_MAKEVALUE(x, S_MC_CS2_END) -#define G_MC_CS2_END(x) _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END) +#define S_MC_CS2_END 32 +#define M_MC_CS2_END _SB_MAKEMASK(16, S_MC_CS2_END) +#define V_MC_CS2_END(x) _SB_MAKEVALUE(x, S_MC_CS2_END) +#define G_MC_CS2_END(x) _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END) -#define S_MC_CS3_END 48 -#define M_MC_CS3_END _SB_MAKEMASK(16, S_MC_CS3_END) -#define V_MC_CS3_END(x) _SB_MAKEVALUE(x, S_MC_CS3_END) -#define G_MC_CS3_END(x) _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END) +#define S_MC_CS3_END 48 +#define M_MC_CS3_END _SB_MAKEMASK(16, S_MC_CS3_END) +#define V_MC_CS3_END(x) _SB_MAKEVALUE(x, S_MC_CS3_END) +#define G_MC_CS3_END(x) _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END) /* * Chip Select Interleave Register (Table 6-19) */ -#define S_MC_INTLV_RESERVED 0 -#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5, S_MC_INTLV_RESERVED) +#define S_MC_INTLV_RESERVED 0 +#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5, S_MC_INTLV_RESERVED) -#define S_MC_INTERLEAVE 7 -#define M_MC_INTERLEAVE _SB_MAKEMASK(18, S_MC_INTERLEAVE) -#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x, S_MC_INTERLEAVE) +#define S_MC_INTERLEAVE 7 +#define M_MC_INTERLEAVE _SB_MAKEMASK(18, S_MC_INTERLEAVE) +#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x, S_MC_INTERLEAVE) -#define S_MC_INTLV_MBZ 25 -#define M_MC_INTLV_MBZ _SB_MAKEMASK(39, S_MC_INTLV_MBZ) +#define S_MC_INTLV_MBZ 25 +#define M_MC_INTLV_MBZ _SB_MAKEMASK(39, S_MC_INTLV_MBZ) /* * Row Address Bits Register (Table 6-20) */ -#define S_MC_RAS_RESERVED 0 -#define M_MC_RAS_RESERVED _SB_MAKEMASK(5, S_MC_RAS_RESERVED) +#define S_MC_RAS_RESERVED 0 +#define M_MC_RAS_RESERVED _SB_MAKEMASK(5, S_MC_RAS_RESERVED) -#define S_MC_RAS_SELECT 12 -#define M_MC_RAS_SELECT _SB_MAKEMASK(25, S_MC_RAS_SELECT) -#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_RAS_SELECT) +#define S_MC_RAS_SELECT 12 +#define M_MC_RAS_SELECT _SB_MAKEMASK(25, S_MC_RAS_SELECT) +#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_RAS_SELECT) -#define S_MC_RAS_MBZ 37 -#define M_MC_RAS_MBZ _SB_MAKEMASK(27, S_MC_RAS_MBZ) +#define S_MC_RAS_MBZ 37 +#define M_MC_RAS_MBZ _SB_MAKEMASK(27, S_MC_RAS_MBZ) /* * Column Address Bits Register (Table 6-21) */ -#define S_MC_CAS_RESERVED 0 -#define M_MC_CAS_RESERVED _SB_MAKEMASK(5, S_MC_CAS_RESERVED) +#define S_MC_CAS_RESERVED 0 +#define M_MC_CAS_RESERVED _SB_MAKEMASK(5, S_MC_CAS_RESERVED) -#define S_MC_CAS_SELECT 5 -#define M_MC_CAS_SELECT _SB_MAKEMASK(18, S_MC_CAS_SELECT) -#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_CAS_SELECT) +#define S_MC_CAS_SELECT 5 +#define M_MC_CAS_SELECT _SB_MAKEMASK(18, S_MC_CAS_SELECT) +#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_CAS_SELECT) -#define S_MC_CAS_MBZ 23 -#define M_MC_CAS_MBZ _SB_MAKEMASK(41, S_MC_CAS_MBZ) +#define S_MC_CAS_MBZ 23 +#define M_MC_CAS_MBZ _SB_MAKEMASK(41, S_MC_CAS_MBZ) /* * Bank Address Address Bits Register (Table 6-22) */ -#define S_MC_BA_RESERVED 0 -#define M_MC_BA_RESERVED _SB_MAKEMASK(5, S_MC_BA_RESERVED) +#define S_MC_BA_RESERVED 0 +#define M_MC_BA_RESERVED _SB_MAKEMASK(5, S_MC_BA_RESERVED) -#define S_MC_BA_SELECT 5 -#define M_MC_BA_SELECT _SB_MAKEMASK(20, S_MC_BA_SELECT) -#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x, S_MC_BA_SELECT) +#define S_MC_BA_SELECT 5 +#define M_MC_BA_SELECT _SB_MAKEMASK(20, S_MC_BA_SELECT) +#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x, S_MC_BA_SELECT) -#define S_MC_BA_MBZ 25 -#define M_MC_BA_MBZ _SB_MAKEMASK(39, S_MC_BA_MBZ) +#define S_MC_BA_MBZ 25 +#define M_MC_BA_MBZ _SB_MAKEMASK(39, S_MC_BA_MBZ) /* * Chip Select Attribute Register (Table 6-23) */ -#define K_MC_CS_ATTR_CLOSED 0 -#define K_MC_CS_ATTR_CASCHECK 1 -#define K_MC_CS_ATTR_HINT 2 -#define K_MC_CS_ATTR_OPEN 3 +#define K_MC_CS_ATTR_CLOSED 0 +#define K_MC_CS_ATTR_CASCHECK 1 +#define K_MC_CS_ATTR_HINT 2 +#define K_MC_CS_ATTR_OPEN 3 -#define S_MC_CS0_PAGE 0 -#define M_MC_CS0_PAGE _SB_MAKEMASK(2, S_MC_CS0_PAGE) -#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS0_PAGE) -#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE) +#define S_MC_CS0_PAGE 0 +#define M_MC_CS0_PAGE _SB_MAKEMASK(2, S_MC_CS0_PAGE) +#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS0_PAGE) +#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE) -#define S_MC_CS1_PAGE 16 -#define M_MC_CS1_PAGE _SB_MAKEMASK(2, S_MC_CS1_PAGE) -#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS1_PAGE) -#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE) +#define S_MC_CS1_PAGE 16 +#define M_MC_CS1_PAGE _SB_MAKEMASK(2, S_MC_CS1_PAGE) +#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS1_PAGE) +#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE) -#define S_MC_CS2_PAGE 32 -#define M_MC_CS2_PAGE _SB_MAKEMASK(2, S_MC_CS2_PAGE) -#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS2_PAGE) -#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE) +#define S_MC_CS2_PAGE 32 +#define M_MC_CS2_PAGE _SB_MAKEMASK(2, S_MC_CS2_PAGE) +#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS2_PAGE) +#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE) -#define S_MC_CS3_PAGE 48 -#define M_MC_CS3_PAGE _SB_MAKEMASK(2, S_MC_CS3_PAGE) -#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS3_PAGE) -#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE) +#define S_MC_CS3_PAGE 48 +#define M_MC_CS3_PAGE _SB_MAKEMASK(2, S_MC_CS3_PAGE) +#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS3_PAGE) +#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE) /* * ECC Test ECC Register (Table 6-25) */ -#define S_MC_ECC_INVERT 0 -#define M_MC_ECC_INVERT _SB_MAKEMASK(8, S_MC_ECC_INVERT) +#define S_MC_ECC_INVERT 0 +#define M_MC_ECC_INVERT _SB_MAKEMASK(8, S_MC_ECC_INVERT) #endif diff --git a/arch/mips/include/asm/sibyte/sb1250_regs.h b/arch/mips/include/asm/sibyte/sb1250_regs.h index 29b9f0b26b3..ee86ca0fad3 100644 --- a/arch/mips/include/asm/sibyte/sb1250_regs.h +++ b/arch/mips/include/asm/sibyte/sb1250_regs.h @@ -1,7 +1,7 @@ /* ********************************************************************* * SB1250 Board Support Package * - * Register Definitions File: sb1250_regs.h + * Register Definitions File: sb1250_regs.h * * This module contains the addresses of the on-chip peripherals * on the SB1250. @@ -61,45 +61,45 @@ */ #if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ -#define A_MC_BASE_0 0x0010051000 -#define A_MC_BASE_1 0x0010052000 -#define MC_REGISTER_SPACING 0x1000 +#define A_MC_BASE_0 0x0010051000 +#define A_MC_BASE_1 0x0010052000 +#define MC_REGISTER_SPACING 0x1000 -#define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) +#define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) #define A_MC_REGISTER(ctlid, reg) (A_MC_BASE(ctlid)+(reg)) -#define R_MC_CONFIG 0x0000000100 -#define R_MC_DRAMCMD 0x0000000120 -#define R_MC_DRAMMODE 0x0000000140 -#define R_MC_TIMING1 0x0000000160 -#define R_MC_TIMING2 0x0000000180 -#define R_MC_CS_START 0x00000001A0 -#define R_MC_CS_END 0x00000001C0 -#define R_MC_CS_INTERLEAVE 0x00000001E0 -#define S_MC_CS_STARTEND 16 - -#define R_MC_CSX_BASE 0x0000000200 -#define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */ -#define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */ -#define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */ -#define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */ - -#define R_MC_CS0_ROW 0x0000000200 -#define R_MC_CS0_COL 0x0000000220 -#define R_MC_CS0_BA 0x0000000240 -#define R_MC_CS1_ROW 0x0000000260 -#define R_MC_CS1_COL 0x0000000280 -#define R_MC_CS1_BA 0x00000002A0 -#define R_MC_CS2_ROW 0x00000002C0 -#define R_MC_CS2_COL 0x00000002E0 -#define R_MC_CS2_BA 0x0000000300 -#define R_MC_CS3_ROW 0x0000000320 -#define R_MC_CS3_COL 0x0000000340 -#define R_MC_CS3_BA 0x0000000360 -#define R_MC_CS_ATTR 0x0000000380 -#define R_MC_TEST_DATA 0x0000000400 -#define R_MC_TEST_ECC 0x0000000420 -#define R_MC_MCLK_CFG 0x0000000500 +#define R_MC_CONFIG 0x0000000100 +#define R_MC_DRAMCMD 0x0000000120 +#define R_MC_DRAMMODE 0x0000000140 +#define R_MC_TIMING1 0x0000000160 +#define R_MC_TIMING2 0x0000000180 +#define R_MC_CS_START 0x00000001A0 +#define R_MC_CS_END 0x00000001C0 +#define R_MC_CS_INTERLEAVE 0x00000001E0 +#define S_MC_CS_STARTEND 16 + +#define R_MC_CSX_BASE 0x0000000200 +#define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */ +#define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */ +#define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */ +#define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */ + +#define R_MC_CS0_ROW 0x0000000200 +#define R_MC_CS0_COL 0x0000000220 +#define R_MC_CS0_BA 0x0000000240 +#define R_MC_CS1_ROW 0x0000000260 +#define R_MC_CS1_COL 0x0000000280 +#define R_MC_CS1_BA 0x00000002A0 +#define R_MC_CS2_ROW 0x00000002C0 +#define R_MC_CS2_COL 0x00000002E0 +#define R_MC_CS2_BA 0x0000000300 +#define R_MC_CS3_ROW 0x0000000320 +#define R_MC_CS3_COL 0x0000000340 +#define R_MC_CS3_BA 0x0000000360 +#define R_MC_CS_ATTR 0x0000000380 +#define R_MC_TEST_DATA 0x0000000400 +#define R_MC_TEST_ECC 0x0000000420 +#define R_MC_MCLK_CFG 0x0000000500 #endif /* 1250 & 112x */ @@ -109,14 +109,14 @@ #if SIBYTE_HDR_FEATURE_1250_112x /* This L2C only on 1250/112x */ -#define A_L2_READ_TAG 0x0010040018 -#define A_L2_ECC_TAG 0x0010040038 +#define A_L2_READ_TAG 0x0010040018 +#define A_L2_ECC_TAG 0x0010040038 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define A_L2_READ_MISC 0x0010040058 +#define A_L2_READ_MISC 0x0010040058 #endif /* 1250 PASS3 || 112x PASS1 */ -#define A_L2_WAY_DISABLE 0x0010041000 -#define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8)) -#define A_L2_MGMT_TAG_BASE 0x00D0000000 +#define A_L2_WAY_DISABLE 0x0010041000 +#define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8)) +#define A_L2_MGMT_TAG_BASE 0x00D0000000 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) #define A_L2_CACHE_DISABLE 0x0010042000 @@ -124,10 +124,10 @@ #define A_L2_MISC_CONFIG 0x0010043000 #endif /* 1250 PASS2 || 112x PASS1 */ -/* Backward-compatibility definitions. */ +/* Backward-compatibility definitions. */ /* XXX: discourage people from using these constants. */ -#define A_L2_READ_ADDRESS A_L2_READ_TAG -#define A_L2_EEC_ADDRESS A_L2_ECC_TAG +#define A_L2_READ_ADDRESS A_L2_READ_TAG +#define A_L2_EEC_ADDRESS A_L2_ECC_TAG #endif @@ -137,8 +137,8 @@ ********************************************************************* */ #if SIBYTE_HDR_FEATURE_1250_112x /* This PCI/HT only on 1250/112x */ -#define A_PCI_TYPE00_HEADER 0x00DE000000 -#define A_PCI_TYPE01_HEADER 0x00DE000800 +#define A_PCI_TYPE00_HEADER 0x00DE000000 +#define A_PCI_TYPE01_HEADER 0x00DE000800 #endif @@ -146,121 +146,121 @@ * Ethernet DMA and MACs ********************************************************************* */ -#define A_MAC_BASE_0 0x0010064000 -#define A_MAC_BASE_1 0x0010065000 +#define A_MAC_BASE_0 0x0010064000 +#define A_MAC_BASE_1 0x0010065000 #if SIBYTE_HDR_FEATURE_CHIP(1250) -#define A_MAC_BASE_2 0x0010066000 +#define A_MAC_BASE_2 0x0010066000 #endif /* 1250 */ -#define MAC_SPACING 0x1000 -#define MAC_DMA_TXRX_SPACING 0x0400 -#define MAC_DMA_CHANNEL_SPACING 0x0100 -#define DMA_RX 0 -#define DMA_TX 1 +#define MAC_SPACING 0x1000 +#define MAC_DMA_TXRX_SPACING 0x0400 +#define MAC_DMA_CHANNEL_SPACING 0x0100 +#define DMA_RX 0 +#define DMA_TX 1 #define MAC_NUM_DMACHAN 2 /* channels per direction */ /* XXX: not correct; depends on SOC type. */ -#define MAC_NUM_PORTS 3 +#define MAC_NUM_PORTS 3 -#define A_MAC_CHANNEL_BASE(macnum) \ - (A_MAC_BASE_0 + \ - MAC_SPACING*(macnum)) +#define A_MAC_CHANNEL_BASE(macnum) \ + (A_MAC_BASE_0 + \ + MAC_SPACING*(macnum)) -#define A_MAC_REGISTER(macnum,reg) \ - (A_MAC_BASE_0 + \ - MAC_SPACING*(macnum) + (reg)) +#define A_MAC_REGISTER(macnum,reg) \ + (A_MAC_BASE_0 + \ + MAC_SPACING*(macnum) + (reg)) #define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ #define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) \ - ((A_MAC_CHANNEL_BASE(macnum)) + \ - R_MAC_DMA_CHANNELS + \ - (MAC_DMA_TXRX_SPACING*(txrx)) + \ - (MAC_DMA_CHANNEL_SPACING*(chan))) + ((A_MAC_CHANNEL_BASE(macnum)) + \ + R_MAC_DMA_CHANNELS + \ + (MAC_DMA_TXRX_SPACING*(txrx)) + \ + (MAC_DMA_CHANNEL_SPACING*(chan))) #define R_MAC_DMA_CHANNEL_BASE(txrx, chan) \ - (R_MAC_DMA_CHANNELS + \ - (MAC_DMA_TXRX_SPACING*(txrx)) + \ - (MAC_DMA_CHANNEL_SPACING*(chan))) + (R_MAC_DMA_CHANNELS + \ + (MAC_DMA_TXRX_SPACING*(txrx)) + \ + (MAC_DMA_CHANNEL_SPACING*(chan))) -#define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg) \ - (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) + \ - (reg)) +#define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg) \ + (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) + \ + (reg)) -#define R_MAC_DMA_REGISTER(txrx, chan, reg) \ - (R_MAC_DMA_CHANNEL_BASE(txrx, chan) + \ - (reg)) +#define R_MAC_DMA_REGISTER(txrx, chan, reg) \ + (R_MAC_DMA_CHANNEL_BASE(txrx, chan) + \ + (reg)) /* * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE */ -#define R_MAC_DMA_CONFIG0 0x00000000 -#define R_MAC_DMA_CONFIG1 0x00000008 -#define R_MAC_DMA_DSCR_BASE 0x00000010 -#define R_MAC_DMA_DSCR_CNT 0x00000018 -#define R_MAC_DMA_CUR_DSCRA 0x00000020 -#define R_MAC_DMA_CUR_DSCRB 0x00000028 -#define R_MAC_DMA_CUR_DSCRADDR 0x00000030 +#define R_MAC_DMA_CONFIG0 0x00000000 +#define R_MAC_DMA_CONFIG1 0x00000008 +#define R_MAC_DMA_DSCR_BASE 0x00000010 +#define R_MAC_DMA_DSCR_CNT 0x00000018 +#define R_MAC_DMA_CUR_DSCRA 0x00000020 +#define R_MAC_DMA_CUR_DSCRB 0x00000028 +#define R_MAC_DMA_CUR_DSCRADDR 0x00000030 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */ +#define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */ #endif /* 1250 PASS3 || 112x PASS1 */ /* * RMON Counters */ -#define R_MAC_RMON_TX_BYTES 0x00000000 -#define R_MAC_RMON_COLLISIONS 0x00000008 -#define R_MAC_RMON_LATE_COL 0x00000010 -#define R_MAC_RMON_EX_COL 0x00000018 -#define R_MAC_RMON_FCS_ERROR 0x00000020 -#define R_MAC_RMON_TX_ABORT 0x00000028 +#define R_MAC_RMON_TX_BYTES 0x00000000 +#define R_MAC_RMON_COLLISIONS 0x00000008 +#define R_MAC_RMON_LATE_COL 0x00000010 +#define R_MAC_RMON_EX_COL 0x00000018 +#define R_MAC_RMON_FCS_ERROR 0x00000020 +#define R_MAC_RMON_TX_ABORT 0x00000028 /* Counter #6 (0x30) now reserved */ -#define R_MAC_RMON_TX_BAD 0x00000038 -#define R_MAC_RMON_TX_GOOD 0x00000040 -#define R_MAC_RMON_TX_RUNT 0x00000048 -#define R_MAC_RMON_TX_OVERSIZE 0x00000050 -#define R_MAC_RMON_RX_BYTES 0x00000080 -#define R_MAC_RMON_RX_MCAST 0x00000088 -#define R_MAC_RMON_RX_BCAST 0x00000090 -#define R_MAC_RMON_RX_BAD 0x00000098 -#define R_MAC_RMON_RX_GOOD 0x000000A0 -#define R_MAC_RMON_RX_RUNT 0x000000A8 -#define R_MAC_RMON_RX_OVERSIZE 0x000000B0 -#define R_MAC_RMON_RX_FCS_ERROR 0x000000B8 -#define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0 -#define R_MAC_RMON_RX_CODE_ERROR 0x000000C8 -#define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0 +#define R_MAC_RMON_TX_BAD 0x00000038 +#define R_MAC_RMON_TX_GOOD 0x00000040 +#define R_MAC_RMON_TX_RUNT 0x00000048 +#define R_MAC_RMON_TX_OVERSIZE 0x00000050 +#define R_MAC_RMON_RX_BYTES 0x00000080 +#define R_MAC_RMON_RX_MCAST 0x00000088 +#define R_MAC_RMON_RX_BCAST 0x00000090 +#define R_MAC_RMON_RX_BAD 0x00000098 +#define R_MAC_RMON_RX_GOOD 0x000000A0 +#define R_MAC_RMON_RX_RUNT 0x000000A8 +#define R_MAC_RMON_RX_OVERSIZE 0x000000B0 +#define R_MAC_RMON_RX_FCS_ERROR 0x000000B8 +#define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0 +#define R_MAC_RMON_RX_CODE_ERROR 0x000000C8 +#define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0 /* Updated to spec 0.2 */ -#define R_MAC_CFG 0x00000100 -#define R_MAC_THRSH_CFG 0x00000108 -#define R_MAC_VLANTAG 0x00000110 -#define R_MAC_FRAMECFG 0x00000118 -#define R_MAC_EOPCNT 0x00000120 -#define R_MAC_FIFO_PTRS 0x00000128 -#define R_MAC_ADFILTER_CFG 0x00000200 -#define R_MAC_ETHERNET_ADDR 0x00000208 -#define R_MAC_PKT_TYPE 0x00000210 +#define R_MAC_CFG 0x00000100 +#define R_MAC_THRSH_CFG 0x00000108 +#define R_MAC_VLANTAG 0x00000110 +#define R_MAC_FRAMECFG 0x00000118 +#define R_MAC_EOPCNT 0x00000120 +#define R_MAC_FIFO_PTRS 0x00000128 +#define R_MAC_ADFILTER_CFG 0x00000200 +#define R_MAC_ETHERNET_ADDR 0x00000208 +#define R_MAC_PKT_TYPE 0x00000210 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define R_MAC_ADMASK0 0x00000218 #define R_MAC_ADMASK1 0x00000220 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define R_MAC_HASH_BASE 0x00000240 -#define R_MAC_ADDR_BASE 0x00000280 -#define R_MAC_CHLO0_BASE 0x00000300 -#define R_MAC_CHUP0_BASE 0x00000320 -#define R_MAC_ENABLE 0x00000400 -#define R_MAC_STATUS 0x00000408 -#define R_MAC_INT_MASK 0x00000410 -#define R_MAC_TXD_CTL 0x00000420 -#define R_MAC_MDIO 0x00000428 +#define R_MAC_HASH_BASE 0x00000240 +#define R_MAC_ADDR_BASE 0x00000280 +#define R_MAC_CHLO0_BASE 0x00000300 +#define R_MAC_CHUP0_BASE 0x00000320 +#define R_MAC_ENABLE 0x00000400 +#define R_MAC_STATUS 0x00000408 +#define R_MAC_INT_MASK 0x00000410 +#define R_MAC_TXD_CTL 0x00000420 +#define R_MAC_MDIO 0x00000428 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define R_MAC_STATUS1 0x00000430 +#define R_MAC_STATUS1 0x00000430 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ -#define R_MAC_DEBUG_STATUS 0x00000448 +#define R_MAC_DEBUG_STATUS 0x00000448 #define MAC_HASH_COUNT 8 #define MAC_ADDR_COUNT 8 @@ -273,11 +273,11 @@ #if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ -#define R_DUART_NUM_PORTS 2 +#define R_DUART_NUM_PORTS 2 -#define A_DUART 0x0010060000 +#define A_DUART 0x0010060000 -#define DUART_CHANREG_SPACING 0x100 +#define DUART_CHANREG_SPACING 0x100 #define A_DUART_CHANREG(chan, reg) \ (A_DUART + DUART_CHANREG_SPACING * ((chan) + 1) + (reg)) @@ -341,44 +341,44 @@ * These constants are the absolute addresses. */ -#define A_DUART_MODE_REG_1_A 0x0010060100 -#define A_DUART_MODE_REG_2_A 0x0010060110 -#define A_DUART_STATUS_A 0x0010060120 -#define A_DUART_CLK_SEL_A 0x0010060130 -#define A_DUART_CMD_A 0x0010060150 -#define A_DUART_RX_HOLD_A 0x0010060160 -#define A_DUART_TX_HOLD_A 0x0010060170 - -#define A_DUART_MODE_REG_1_B 0x0010060200 -#define A_DUART_MODE_REG_2_B 0x0010060210 -#define A_DUART_STATUS_B 0x0010060220 -#define A_DUART_CLK_SEL_B 0x0010060230 -#define A_DUART_CMD_B 0x0010060250 -#define A_DUART_RX_HOLD_B 0x0010060260 -#define A_DUART_TX_HOLD_B 0x0010060270 - -#define A_DUART_INPORT_CHNG 0x0010060300 -#define A_DUART_AUX_CTRL 0x0010060310 -#define A_DUART_ISR_A 0x0010060320 -#define A_DUART_IMR_A 0x0010060330 -#define A_DUART_ISR_B 0x0010060340 -#define A_DUART_IMR_B 0x0010060350 -#define A_DUART_OUT_PORT 0x0010060360 -#define A_DUART_OPCR 0x0010060370 -#define A_DUART_IN_PORT 0x0010060380 -#define A_DUART_ISR 0x0010060390 -#define A_DUART_IMR 0x00100603A0 -#define A_DUART_SET_OPR 0x00100603B0 -#define A_DUART_CLEAR_OPR 0x00100603C0 -#define A_DUART_INPORT_CHNG_A 0x00100603D0 -#define A_DUART_INPORT_CHNG_B 0x00100603E0 +#define A_DUART_MODE_REG_1_A 0x0010060100 +#define A_DUART_MODE_REG_2_A 0x0010060110 +#define A_DUART_STATUS_A 0x0010060120 +#define A_DUART_CLK_SEL_A 0x0010060130 +#define A_DUART_CMD_A 0x0010060150 +#define A_DUART_RX_HOLD_A 0x0010060160 +#define A_DUART_TX_HOLD_A 0x0010060170 + +#define A_DUART_MODE_REG_1_B 0x0010060200 +#define A_DUART_MODE_REG_2_B 0x0010060210 +#define A_DUART_STATUS_B 0x0010060220 +#define A_DUART_CLK_SEL_B 0x0010060230 +#define A_DUART_CMD_B 0x0010060250 +#define A_DUART_RX_HOLD_B 0x0010060260 +#define A_DUART_TX_HOLD_B 0x0010060270 + +#define A_DUART_INPORT_CHNG 0x0010060300 +#define A_DUART_AUX_CTRL 0x0010060310 +#define A_DUART_ISR_A 0x0010060320 +#define A_DUART_IMR_A 0x0010060330 +#define A_DUART_ISR_B 0x0010060340 +#define A_DUART_IMR_B 0x0010060350 +#define A_DUART_OUT_PORT 0x0010060360 +#define A_DUART_OPCR 0x0010060370 +#define A_DUART_IN_PORT 0x0010060380 +#define A_DUART_ISR 0x0010060390 +#define A_DUART_IMR 0x00100603A0 +#define A_DUART_SET_OPR 0x00100603B0 +#define A_DUART_CLEAR_OPR 0x00100603C0 +#define A_DUART_INPORT_CHNG_A 0x00100603D0 +#define A_DUART_INPORT_CHNG_B 0x00100603E0 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) #define A_DUART_FULL_CTL_A 0x0010060140 #define A_DUART_FULL_CTL_B 0x0010060240 -#define A_DUART_OPCR_A 0x0010060180 -#define A_DUART_OPCR_B 0x0010060280 +#define A_DUART_OPCR_A 0x0010060180 +#define A_DUART_OPCR_B 0x0010060280 #define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0 #endif /* 1250 PASS2 || 112x PASS1 */ @@ -391,94 +391,94 @@ #if SIBYTE_HDR_FEATURE_1250_112x /* sync serial only on 1250/112x */ -#define A_SER_BASE_0 0x0010060400 -#define A_SER_BASE_1 0x0010060800 -#define SER_SPACING 0x400 +#define A_SER_BASE_0 0x0010060400 +#define A_SER_BASE_1 0x0010060800 +#define SER_SPACING 0x400 -#define SER_DMA_TXRX_SPACING 0x80 +#define SER_DMA_TXRX_SPACING 0x80 -#define SER_NUM_PORTS 2 +#define SER_NUM_PORTS 2 -#define A_SER_CHANNEL_BASE(sernum) \ - (A_SER_BASE_0 + \ - SER_SPACING*(sernum)) +#define A_SER_CHANNEL_BASE(sernum) \ + (A_SER_BASE_0 + \ + SER_SPACING*(sernum)) -#define A_SER_REGISTER(sernum,reg) \ - (A_SER_BASE_0 + \ - SER_SPACING*(sernum) + (reg)) +#define A_SER_REGISTER(sernum,reg) \ + (A_SER_BASE_0 + \ + SER_SPACING*(sernum) + (reg)) #define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */ #define A_SER_DMA_CHANNEL_BASE(sernum,txrx) \ - ((A_SER_CHANNEL_BASE(sernum)) + \ - R_SER_DMA_CHANNELS + \ - (SER_DMA_TXRX_SPACING*(txrx))) + ((A_SER_CHANNEL_BASE(sernum)) + \ + R_SER_DMA_CHANNELS + \ + (SER_DMA_TXRX_SPACING*(txrx))) -#define A_SER_DMA_REGISTER(sernum, txrx, reg) \ - (A_SER_DMA_CHANNEL_BASE(sernum, txrx) + \ - (reg)) +#define A_SER_DMA_REGISTER(sernum, txrx, reg) \ + (A_SER_DMA_CHANNEL_BASE(sernum, txrx) + \ + (reg)) /* * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE */ -#define R_SER_DMA_CONFIG0 0x00000000 -#define R_SER_DMA_CONFIG1 0x00000008 -#define R_SER_DMA_DSCR_BASE 0x00000010 -#define R_SER_DMA_DSCR_CNT 0x00000018 -#define R_SER_DMA_CUR_DSCRA 0x00000020 -#define R_SER_DMA_CUR_DSCRB 0x00000028 -#define R_SER_DMA_CUR_DSCRADDR 0x00000030 - -#define R_SER_DMA_CONFIG0_RX 0x00000000 -#define R_SER_DMA_CONFIG1_RX 0x00000008 -#define R_SER_DMA_DSCR_BASE_RX 0x00000010 -#define R_SER_DMA_DSCR_COUNT_RX 0x00000018 -#define R_SER_DMA_CUR_DSCR_A_RX 0x00000020 -#define R_SER_DMA_CUR_DSCR_B_RX 0x00000028 +#define R_SER_DMA_CONFIG0 0x00000000 +#define R_SER_DMA_CONFIG1 0x00000008 +#define R_SER_DMA_DSCR_BASE 0x00000010 +#define R_SER_DMA_DSCR_CNT 0x00000018 +#define R_SER_DMA_CUR_DSCRA 0x00000020 +#define R_SER_DMA_CUR_DSCRB 0x00000028 +#define R_SER_DMA_CUR_DSCRADDR 0x00000030 + +#define R_SER_DMA_CONFIG0_RX 0x00000000 +#define R_SER_DMA_CONFIG1_RX 0x00000008 +#define R_SER_DMA_DSCR_BASE_RX 0x00000010 +#define R_SER_DMA_DSCR_COUNT_RX 0x00000018 +#define R_SER_DMA_CUR_DSCR_A_RX 0x00000020 +#define R_SER_DMA_CUR_DSCR_B_RX 0x00000028 #define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030 -#define R_SER_DMA_CONFIG0_TX 0x00000080 -#define R_SER_DMA_CONFIG1_TX 0x00000088 -#define R_SER_DMA_DSCR_BASE_TX 0x00000090 -#define R_SER_DMA_DSCR_COUNT_TX 0x00000098 -#define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0 -#define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8 +#define R_SER_DMA_CONFIG0_TX 0x00000080 +#define R_SER_DMA_CONFIG1_TX 0x00000088 +#define R_SER_DMA_DSCR_BASE_TX 0x00000090 +#define R_SER_DMA_DSCR_COUNT_TX 0x00000098 +#define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0 +#define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8 #define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0 -#define R_SER_MODE 0x00000100 -#define R_SER_MINFRM_SZ 0x00000108 -#define R_SER_MAXFRM_SZ 0x00000110 -#define R_SER_ADDR 0x00000118 -#define R_SER_USR0_ADDR 0x00000120 -#define R_SER_USR1_ADDR 0x00000128 -#define R_SER_USR2_ADDR 0x00000130 -#define R_SER_USR3_ADDR 0x00000138 -#define R_SER_CMD 0x00000140 -#define R_SER_TX_RD_THRSH 0x00000160 -#define R_SER_TX_WR_THRSH 0x00000168 -#define R_SER_RX_RD_THRSH 0x00000170 +#define R_SER_MODE 0x00000100 +#define R_SER_MINFRM_SZ 0x00000108 +#define R_SER_MAXFRM_SZ 0x00000110 +#define R_SER_ADDR 0x00000118 +#define R_SER_USR0_ADDR 0x00000120 +#define R_SER_USR1_ADDR 0x00000128 +#define R_SER_USR2_ADDR 0x00000130 +#define R_SER_USR3_ADDR 0x00000138 +#define R_SER_CMD 0x00000140 +#define R_SER_TX_RD_THRSH 0x00000160 +#define R_SER_TX_WR_THRSH 0x00000168 +#define R_SER_RX_RD_THRSH 0x00000170 #define R_SER_LINE_MODE 0x00000178 -#define R_SER_DMA_ENABLE 0x00000180 -#define R_SER_INT_MASK 0x00000190 -#define R_SER_STATUS 0x00000188 -#define R_SER_STATUS_DEBUG 0x000001A8 -#define R_SER_RX_TABLE_BASE 0x00000200 -#define SER_RX_TABLE_COUNT 16 -#define R_SER_TX_TABLE_BASE 0x00000300 -#define SER_TX_TABLE_COUNT 16 +#define R_SER_DMA_ENABLE 0x00000180 +#define R_SER_INT_MASK 0x00000190 +#define R_SER_STATUS 0x00000188 +#define R_SER_STATUS_DEBUG 0x000001A8 +#define R_SER_RX_TABLE_BASE 0x00000200 +#define SER_RX_TABLE_COUNT 16 +#define R_SER_TX_TABLE_BASE 0x00000300 +#define SER_TX_TABLE_COUNT 16 /* RMON Counters */ -#define R_SER_RMON_TX_BYTE_LO 0x000001C0 -#define R_SER_RMON_TX_BYTE_HI 0x000001C8 -#define R_SER_RMON_RX_BYTE_LO 0x000001D0 -#define R_SER_RMON_RX_BYTE_HI 0x000001D8 -#define R_SER_RMON_TX_UNDERRUN 0x000001E0 -#define R_SER_RMON_RX_OVERFLOW 0x000001E8 -#define R_SER_RMON_RX_ERRORS 0x000001F0 -#define R_SER_RMON_RX_BADADDR 0x000001F8 +#define R_SER_RMON_TX_BYTE_LO 0x000001C0 +#define R_SER_RMON_TX_BYTE_HI 0x000001C8 +#define R_SER_RMON_RX_BYTE_LO 0x000001D0 +#define R_SER_RMON_RX_BYTE_HI 0x000001D8 +#define R_SER_RMON_TX_UNDERRUN 0x000001E0 +#define R_SER_RMON_RX_OVERFLOW 0x000001E8 +#define R_SER_RMON_RX_ERRORS 0x000001F0 +#define R_SER_RMON_RX_BADADDR 0x000001F8 #endif /* 1250/112x */ @@ -486,38 +486,38 @@ * Generic Bus Registers ********************************************************************* */ -#define IO_EXT_CFG_COUNT 8 +#define IO_EXT_CFG_COUNT 8 #define A_IO_EXT_BASE 0x0010061000 #define A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r)) -#define A_IO_EXT_CFG_BASE 0x0010061000 -#define A_IO_EXT_MULT_SIZE_BASE 0x0010061100 +#define A_IO_EXT_CFG_BASE 0x0010061000 +#define A_IO_EXT_MULT_SIZE_BASE 0x0010061100 #define A_IO_EXT_START_ADDR_BASE 0x0010061200 -#define A_IO_EXT_TIME_CFG0_BASE 0x0010061600 -#define A_IO_EXT_TIME_CFG1_BASE 0x0010061700 +#define A_IO_EXT_TIME_CFG0_BASE 0x0010061600 +#define A_IO_EXT_TIME_CFG1_BASE 0x0010061700 #define IO_EXT_REGISTER_SPACING 8 #define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) #define R_IO_EXT_REG(reg, cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) #define R_IO_EXT_CFG 0x0000 -#define R_IO_EXT_MULT_SIZE 0x0100 +#define R_IO_EXT_MULT_SIZE 0x0100 #define R_IO_EXT_START_ADDR 0x0200 -#define R_IO_EXT_TIME_CFG0 0x0600 -#define R_IO_EXT_TIME_CFG1 0x0700 - - -#define A_IO_INTERRUPT_STATUS 0x0010061A00 -#define A_IO_INTERRUPT_DATA0 0x0010061A10 -#define A_IO_INTERRUPT_DATA1 0x0010061A18 -#define A_IO_INTERRUPT_DATA2 0x0010061A20 -#define A_IO_INTERRUPT_DATA3 0x0010061A28 -#define A_IO_INTERRUPT_ADDR0 0x0010061A30 -#define A_IO_INTERRUPT_ADDR1 0x0010061A40 -#define A_IO_INTERRUPT_PARITY 0x0010061A50 -#define A_IO_PCMCIA_CFG 0x0010061A60 -#define A_IO_PCMCIA_STATUS 0x0010061A70 +#define R_IO_EXT_TIME_CFG0 0x0600 +#define R_IO_EXT_TIME_CFG1 0x0700 + + +#define A_IO_INTERRUPT_STATUS 0x0010061A00 +#define A_IO_INTERRUPT_DATA0 0x0010061A10 +#define A_IO_INTERRUPT_DATA1 0x0010061A18 +#define A_IO_INTERRUPT_DATA2 0x0010061A20 +#define A_IO_INTERRUPT_DATA3 0x0010061A28 +#define A_IO_INTERRUPT_ADDR0 0x0010061A30 +#define A_IO_INTERRUPT_ADDR1 0x0010061A40 +#define A_IO_INTERRUPT_PARITY 0x0010061A50 +#define A_IO_PCMCIA_CFG 0x0010061A60 +#define A_IO_PCMCIA_STATUS 0x0010061A70 #define A_IO_DRIVE_0 0x0010061300 #define A_IO_DRIVE_1 0x0010061308 #define A_IO_DRIVE_2 0x0010061310 @@ -527,76 +527,76 @@ #define R_IO_DRIVE(x) ((x)*IO_DRIVE_REGISTER_SPACING) #define A_IO_DRIVE(x) (A_IO_DRIVE_BASE + R_IO_DRIVE(x)) -#define R_IO_INTERRUPT_STATUS 0x0A00 -#define R_IO_INTERRUPT_DATA0 0x0A10 -#define R_IO_INTERRUPT_DATA1 0x0A18 -#define R_IO_INTERRUPT_DATA2 0x0A20 -#define R_IO_INTERRUPT_DATA3 0x0A28 -#define R_IO_INTERRUPT_ADDR0 0x0A30 -#define R_IO_INTERRUPT_ADDR1 0x0A40 -#define R_IO_INTERRUPT_PARITY 0x0A50 -#define R_IO_PCMCIA_CFG 0x0A60 -#define R_IO_PCMCIA_STATUS 0x0A70 +#define R_IO_INTERRUPT_STATUS 0x0A00 +#define R_IO_INTERRUPT_DATA0 0x0A10 +#define R_IO_INTERRUPT_DATA1 0x0A18 +#define R_IO_INTERRUPT_DATA2 0x0A20 +#define R_IO_INTERRUPT_DATA3 0x0A28 +#define R_IO_INTERRUPT_ADDR0 0x0A30 +#define R_IO_INTERRUPT_ADDR1 0x0A40 +#define R_IO_INTERRUPT_PARITY 0x0A50 +#define R_IO_PCMCIA_CFG 0x0A60 +#define R_IO_PCMCIA_STATUS 0x0A70 /* ********************************************************************* * GPIO Registers ********************************************************************* */ -#define A_GPIO_CLR_EDGE 0x0010061A80 -#define A_GPIO_INT_TYPE 0x0010061A88 -#define A_GPIO_INPUT_INVERT 0x0010061A90 -#define A_GPIO_GLITCH 0x0010061A98 -#define A_GPIO_READ 0x0010061AA0 -#define A_GPIO_DIRECTION 0x0010061AA8 -#define A_GPIO_PIN_CLR 0x0010061AB0 -#define A_GPIO_PIN_SET 0x0010061AB8 +#define A_GPIO_CLR_EDGE 0x0010061A80 +#define A_GPIO_INT_TYPE 0x0010061A88 +#define A_GPIO_INPUT_INVERT 0x0010061A90 +#define A_GPIO_GLITCH 0x0010061A98 +#define A_GPIO_READ 0x0010061AA0 +#define A_GPIO_DIRECTION 0x0010061AA8 +#define A_GPIO_PIN_CLR 0x0010061AB0 +#define A_GPIO_PIN_SET 0x0010061AB8 #define A_GPIO_BASE 0x0010061A80 -#define R_GPIO_CLR_EDGE 0x00 -#define R_GPIO_INT_TYPE 0x08 -#define R_GPIO_INPUT_INVERT 0x10 -#define R_GPIO_GLITCH 0x18 -#define R_GPIO_READ 0x20 -#define R_GPIO_DIRECTION 0x28 -#define R_GPIO_PIN_CLR 0x30 -#define R_GPIO_PIN_SET 0x38 +#define R_GPIO_CLR_EDGE 0x00 +#define R_GPIO_INT_TYPE 0x08 +#define R_GPIO_INPUT_INVERT 0x10 +#define R_GPIO_GLITCH 0x18 +#define R_GPIO_READ 0x20 +#define R_GPIO_DIRECTION 0x28 +#define R_GPIO_PIN_CLR 0x30 +#define R_GPIO_PIN_SET 0x38 /* ********************************************************************* * SMBus Registers ********************************************************************* */ -#define A_SMB_XTRA_0 0x0010060000 -#define A_SMB_XTRA_1 0x0010060008 -#define A_SMB_FREQ_0 0x0010060010 -#define A_SMB_FREQ_1 0x0010060018 -#define A_SMB_STATUS_0 0x0010060020 -#define A_SMB_STATUS_1 0x0010060028 -#define A_SMB_CMD_0 0x0010060030 -#define A_SMB_CMD_1 0x0010060038 -#define A_SMB_START_0 0x0010060040 -#define A_SMB_START_1 0x0010060048 -#define A_SMB_DATA_0 0x0010060050 -#define A_SMB_DATA_1 0x0010060058 -#define A_SMB_CONTROL_0 0x0010060060 -#define A_SMB_CONTROL_1 0x0010060068 -#define A_SMB_PEC_0 0x0010060070 -#define A_SMB_PEC_1 0x0010060078 - -#define A_SMB_0 0x0010060000 -#define A_SMB_1 0x0010060008 -#define SMB_REGISTER_SPACING 0x8 -#define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) +#define A_SMB_XTRA_0 0x0010060000 +#define A_SMB_XTRA_1 0x0010060008 +#define A_SMB_FREQ_0 0x0010060010 +#define A_SMB_FREQ_1 0x0010060018 +#define A_SMB_STATUS_0 0x0010060020 +#define A_SMB_STATUS_1 0x0010060028 +#define A_SMB_CMD_0 0x0010060030 +#define A_SMB_CMD_1 0x0010060038 +#define A_SMB_START_0 0x0010060040 +#define A_SMB_START_1 0x0010060048 +#define A_SMB_DATA_0 0x0010060050 +#define A_SMB_DATA_1 0x0010060058 +#define A_SMB_CONTROL_0 0x0010060060 +#define A_SMB_CONTROL_1 0x0010060068 +#define A_SMB_PEC_0 0x0010060070 +#define A_SMB_PEC_1 0x0010060078 + +#define A_SMB_0 0x0010060000 +#define A_SMB_1 0x0010060008 +#define SMB_REGISTER_SPACING 0x8 +#define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) #define A_SMB_REGISTER(idx, reg) (A_SMB_BASE(idx)+(reg)) -#define R_SMB_XTRA 0x0000000000 -#define R_SMB_FREQ 0x0000000010 -#define R_SMB_STATUS 0x0000000020 -#define R_SMB_CMD 0x0000000030 -#define R_SMB_START 0x0000000040 -#define R_SMB_DATA 0x0000000050 -#define R_SMB_CONTROL 0x0000000060 -#define R_SMB_PEC 0x0000000070 +#define R_SMB_XTRA 0x0000000000 +#define R_SMB_FREQ 0x0000000010 +#define R_SMB_STATUS 0x0000000020 +#define R_SMB_CMD 0x0000000030 +#define R_SMB_START 0x0000000040 +#define R_SMB_DATA 0x0000000050 +#define R_SMB_CONTROL 0x0000000060 +#define R_SMB_PEC 0x0000000070 /* ********************************************************************* * Timer Registers @@ -607,55 +607,55 @@ */ #define A_SCD_WDOG_0 0x0010020050 -#define A_SCD_WDOG_1 0x0010020150 -#define SCD_WDOG_SPACING 0x100 +#define A_SCD_WDOG_1 0x0010020150 +#define SCD_WDOG_SPACING 0x100 #define SCD_NUM_WDOGS 2 -#define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) +#define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) #define A_SCD_WDOG_REGISTER(w, r) (A_SCD_WDOG_BASE(w) + (r)) #define R_SCD_WDOG_INIT 0x0000000000 #define R_SCD_WDOG_CNT 0x0000000008 #define R_SCD_WDOG_CFG 0x0000000010 -#define A_SCD_WDOG_INIT_0 0x0010020050 -#define A_SCD_WDOG_CNT_0 0x0010020058 -#define A_SCD_WDOG_CFG_0 0x0010020060 +#define A_SCD_WDOG_INIT_0 0x0010020050 +#define A_SCD_WDOG_CNT_0 0x0010020058 +#define A_SCD_WDOG_CFG_0 0x0010020060 -#define A_SCD_WDOG_INIT_1 0x0010020150 -#define A_SCD_WDOG_CNT_1 0x0010020158 -#define A_SCD_WDOG_CFG_1 0x0010020160 +#define A_SCD_WDOG_INIT_1 0x0010020150 +#define A_SCD_WDOG_CNT_1 0x0010020158 +#define A_SCD_WDOG_CFG_1 0x0010020160 /* * Generic timers */ #define A_SCD_TIMER_0 0x0010020070 -#define A_SCD_TIMER_1 0x0010020078 +#define A_SCD_TIMER_1 0x0010020078 #define A_SCD_TIMER_2 0x0010020170 -#define A_SCD_TIMER_3 0x0010020178 +#define A_SCD_TIMER_3 0x0010020178 #define SCD_NUM_TIMERS 4 -#define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) +#define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) #define A_SCD_TIMER_REGISTER(w, r) (A_SCD_TIMER_BASE(w) + (r)) #define R_SCD_TIMER_INIT 0x0000000000 #define R_SCD_TIMER_CNT 0x0000000010 #define R_SCD_TIMER_CFG 0x0000000020 -#define A_SCD_TIMER_INIT_0 0x0010020070 -#define A_SCD_TIMER_CNT_0 0x0010020080 -#define A_SCD_TIMER_CFG_0 0x0010020090 +#define A_SCD_TIMER_INIT_0 0x0010020070 +#define A_SCD_TIMER_CNT_0 0x0010020080 +#define A_SCD_TIMER_CFG_0 0x0010020090 -#define A_SCD_TIMER_INIT_1 0x0010020078 -#define A_SCD_TIMER_CNT_1 0x0010020088 -#define A_SCD_TIMER_CFG_1 0x0010020098 +#define A_SCD_TIMER_INIT_1 0x0010020078 +#define A_SCD_TIMER_CNT_1 0x0010020088 +#define A_SCD_TIMER_CFG_1 0x0010020098 -#define A_SCD_TIMER_INIT_2 0x0010020170 -#define A_SCD_TIMER_CNT_2 0x0010020180 -#define A_SCD_TIMER_CFG_2 0x0010020190 +#define A_SCD_TIMER_INIT_2 0x0010020170 +#define A_SCD_TIMER_CNT_2 0x0010020180 +#define A_SCD_TIMER_CFG_2 0x0010020190 -#define A_SCD_TIMER_INIT_3 0x0010020178 -#define A_SCD_TIMER_CNT_3 0x0010020188 -#define A_SCD_TIMER_CFG_3 0x0010020198 +#define A_SCD_TIMER_INIT_3 0x0010020178 +#define A_SCD_TIMER_CNT_3 0x0010020188 +#define A_SCD_TIMER_CFG_3 0x0010020198 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) #define A_SCD_SCRATCH 0x0010020C10 @@ -671,28 +671,28 @@ * System Control Registers ********************************************************************* */ -#define A_SCD_SYSTEM_REVISION 0x0010020000 -#define A_SCD_SYSTEM_CFG 0x0010020008 -#define A_SCD_SYSTEM_MANUF 0x0010038000 +#define A_SCD_SYSTEM_REVISION 0x0010020000 +#define A_SCD_SYSTEM_CFG 0x0010020008 +#define A_SCD_SYSTEM_MANUF 0x0010038000 /* ********************************************************************* * System Address Trap Registers ********************************************************************* */ -#define A_ADDR_TRAP_INDEX 0x00100200B0 -#define A_ADDR_TRAP_REG 0x00100200B8 -#define A_ADDR_TRAP_UP_0 0x0010020400 -#define A_ADDR_TRAP_UP_1 0x0010020408 -#define A_ADDR_TRAP_UP_2 0x0010020410 -#define A_ADDR_TRAP_UP_3 0x0010020418 -#define A_ADDR_TRAP_DOWN_0 0x0010020420 -#define A_ADDR_TRAP_DOWN_1 0x0010020428 -#define A_ADDR_TRAP_DOWN_2 0x0010020430 -#define A_ADDR_TRAP_DOWN_3 0x0010020438 -#define A_ADDR_TRAP_CFG_0 0x0010020440 -#define A_ADDR_TRAP_CFG_1 0x0010020448 -#define A_ADDR_TRAP_CFG_2 0x0010020450 -#define A_ADDR_TRAP_CFG_3 0x0010020458 +#define A_ADDR_TRAP_INDEX 0x00100200B0 +#define A_ADDR_TRAP_REG 0x00100200B8 +#define A_ADDR_TRAP_UP_0 0x0010020400 +#define A_ADDR_TRAP_UP_1 0x0010020408 +#define A_ADDR_TRAP_UP_2 0x0010020410 +#define A_ADDR_TRAP_UP_3 0x0010020418 +#define A_ADDR_TRAP_DOWN_0 0x0010020420 +#define A_ADDR_TRAP_DOWN_1 0x0010020428 +#define A_ADDR_TRAP_DOWN_2 0x0010020430 +#define A_ADDR_TRAP_DOWN_3 0x0010020438 +#define A_ADDR_TRAP_CFG_0 0x0010020440 +#define A_ADDR_TRAP_CFG_1 0x0010020448 +#define A_ADDR_TRAP_CFG_2 0x0010020450 +#define A_ADDR_TRAP_CFG_3 0x0010020458 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) #define A_ADDR_TRAP_REG_DEBUG 0x0010020460 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ @@ -708,31 +708,31 @@ * System Interrupt Mapper Registers ********************************************************************* */ -#define A_IMR_CPU0_BASE 0x0010020000 -#define A_IMR_CPU1_BASE 0x0010022000 -#define IMR_REGISTER_SPACING 0x2000 -#define IMR_REGISTER_SPACING_SHIFT 13 +#define A_IMR_CPU0_BASE 0x0010020000 +#define A_IMR_CPU1_BASE 0x0010022000 +#define IMR_REGISTER_SPACING 0x2000 +#define IMR_REGISTER_SPACING_SHIFT 13 #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) #define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg)) -#define R_IMR_INTERRUPT_DIAG 0x0010 -#define R_IMR_INTERRUPT_LDT 0x0018 -#define R_IMR_INTERRUPT_MASK 0x0028 -#define R_IMR_INTERRUPT_TRACE 0x0038 -#define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 -#define R_IMR_LDT_INTERRUPT_SET 0x0048 -#define R_IMR_LDT_INTERRUPT 0x0018 -#define R_IMR_LDT_INTERRUPT_CLR 0x0020 -#define R_IMR_MAILBOX_CPU 0x00c0 -#define R_IMR_ALIAS_MAILBOX_CPU 0x1000 -#define R_IMR_MAILBOX_SET_CPU 0x00C8 -#define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 -#define R_IMR_MAILBOX_CLR_CPU 0x00D0 -#define R_IMR_INTERRUPT_STATUS_BASE 0x0100 -#define R_IMR_INTERRUPT_STATUS_COUNT 7 -#define R_IMR_INTERRUPT_MAP_BASE 0x0200 -#define R_IMR_INTERRUPT_MAP_COUNT 64 +#define R_IMR_INTERRUPT_DIAG 0x0010 +#define R_IMR_INTERRUPT_LDT 0x0018 +#define R_IMR_INTERRUPT_MASK 0x0028 +#define R_IMR_INTERRUPT_TRACE 0x0038 +#define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 +#define R_IMR_LDT_INTERRUPT_SET 0x0048 +#define R_IMR_LDT_INTERRUPT 0x0018 +#define R_IMR_LDT_INTERRUPT_CLR 0x0020 +#define R_IMR_MAILBOX_CPU 0x00c0 +#define R_IMR_ALIAS_MAILBOX_CPU 0x1000 +#define R_IMR_MAILBOX_SET_CPU 0x00C8 +#define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 +#define R_IMR_MAILBOX_CLR_CPU 0x00D0 +#define R_IMR_INTERRUPT_STATUS_BASE 0x0100 +#define R_IMR_INTERRUPT_STATUS_COUNT 7 +#define R_IMR_INTERRUPT_MAP_BASE 0x0200 +#define R_IMR_INTERRUPT_MAP_COUNT 64 /* * these macros work together to build the address of a mailbox @@ -746,11 +746,11 @@ * System Performance Counter Registers ********************************************************************* */ -#define A_SCD_PERF_CNT_CFG 0x00100204C0 -#define A_SCD_PERF_CNT_0 0x00100204D0 -#define A_SCD_PERF_CNT_1 0x00100204D8 -#define A_SCD_PERF_CNT_2 0x00100204E0 -#define A_SCD_PERF_CNT_3 0x00100204E8 +#define A_SCD_PERF_CNT_CFG 0x00100204C0 +#define A_SCD_PERF_CNT_0 0x00100204D0 +#define A_SCD_PERF_CNT_1 0x00100204D8 +#define A_SCD_PERF_CNT_2 0x00100204E0 +#define A_SCD_PERF_CNT_3 0x00100204E8 #define SCD_NUM_PERF_CNT 4 #define SCD_PERF_CNT_SPACING 8 @@ -760,46 +760,46 @@ * System Bus Watcher Registers ********************************************************************* */ -#define A_SCD_BUS_ERR_STATUS 0x0010020880 +#define A_SCD_BUS_ERR_STATUS 0x0010020880 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) #define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 -#define A_BUS_ERR_STATUS_DEBUG 0x00100208D0 +#define A_BUS_ERR_STATUS_DEBUG 0x00100208D0 #endif /* 1250 PASS2 || 112x PASS1 */ -#define A_BUS_ERR_DATA_0 0x00100208A0 -#define A_BUS_ERR_DATA_1 0x00100208A8 -#define A_BUS_ERR_DATA_2 0x00100208B0 -#define A_BUS_ERR_DATA_3 0x00100208B8 -#define A_BUS_L2_ERRORS 0x00100208C0 -#define A_BUS_MEM_IO_ERRORS 0x00100208C8 +#define A_BUS_ERR_DATA_0 0x00100208A0 +#define A_BUS_ERR_DATA_1 0x00100208A8 +#define A_BUS_ERR_DATA_2 0x00100208B0 +#define A_BUS_ERR_DATA_3 0x00100208B8 +#define A_BUS_L2_ERRORS 0x00100208C0 +#define A_BUS_MEM_IO_ERRORS 0x00100208C8 /* ********************************************************************* * System Debug Controller Registers ********************************************************************* */ -#define A_SCD_JTAG_BASE 0x0010000000 +#define A_SCD_JTAG_BASE 0x0010000000 /* ********************************************************************* * System Trace Buffer Registers ********************************************************************* */ -#define A_SCD_TRACE_CFG 0x0010020A00 -#define A_SCD_TRACE_READ 0x0010020A08 -#define A_SCD_TRACE_EVENT_0 0x0010020A20 -#define A_SCD_TRACE_EVENT_1 0x0010020A28 -#define A_SCD_TRACE_EVENT_2 0x0010020A30 -#define A_SCD_TRACE_EVENT_3 0x0010020A38 -#define A_SCD_TRACE_SEQUENCE_0 0x0010020A40 -#define A_SCD_TRACE_SEQUENCE_1 0x0010020A48 -#define A_SCD_TRACE_SEQUENCE_2 0x0010020A50 -#define A_SCD_TRACE_SEQUENCE_3 0x0010020A58 -#define A_SCD_TRACE_EVENT_4 0x0010020A60 -#define A_SCD_TRACE_EVENT_5 0x0010020A68 -#define A_SCD_TRACE_EVENT_6 0x0010020A70 -#define A_SCD_TRACE_EVENT_7 0x0010020A78 -#define A_SCD_TRACE_SEQUENCE_4 0x0010020A80 -#define A_SCD_TRACE_SEQUENCE_5 0x0010020A88 -#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 -#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 +#define A_SCD_TRACE_CFG 0x0010020A00 +#define A_SCD_TRACE_READ 0x0010020A08 +#define A_SCD_TRACE_EVENT_0 0x0010020A20 +#define A_SCD_TRACE_EVENT_1 0x0010020A28 +#define A_SCD_TRACE_EVENT_2 0x0010020A30 +#define A_SCD_TRACE_EVENT_3 0x0010020A38 +#define A_SCD_TRACE_SEQUENCE_0 0x0010020A40 +#define A_SCD_TRACE_SEQUENCE_1 0x0010020A48 +#define A_SCD_TRACE_SEQUENCE_2 0x0010020A50 +#define A_SCD_TRACE_SEQUENCE_3 0x0010020A58 +#define A_SCD_TRACE_EVENT_4 0x0010020A60 +#define A_SCD_TRACE_EVENT_5 0x0010020A68 +#define A_SCD_TRACE_EVENT_6 0x0010020A70 +#define A_SCD_TRACE_EVENT_7 0x0010020A78 +#define A_SCD_TRACE_SEQUENCE_4 0x0010020A80 +#define A_SCD_TRACE_SEQUENCE_5 0x0010020A88 +#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 +#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 #define TRACE_REGISTER_SPACING 8 #define TRACE_NUM_REGISTERS 8 @@ -814,8 +814,8 @@ * System Generic DMA Registers ********************************************************************* */ -#define A_DM_0 0x0010020B00 -#define A_DM_1 0x0010020B20 +#define A_DM_0 0x0010020B00 +#define A_DM_1 0x0010020B20 #define A_DM_2 0x0010020B40 #define A_DM_3 0x0010020B60 #define DM_REGISTER_SPACING 0x20 @@ -854,39 +854,39 @@ ********************************************************************* */ #if SIBYTE_HDR_FEATURE_1250_112x -#define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) -#define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) -#define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) -#define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) +#define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) +#define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) +#define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) +#define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) #define A_PHYS_GENBUS _SB_MAKE64(0x0010090000) #define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000) #define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000) -#define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000) -#define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) -#define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) -#define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) -#define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) -#define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) -#define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) -#define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) -#define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) -#define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) -#define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) -#define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) -#define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) -#define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000) -#define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000) -#define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000) -#define A_PHYS_RESERVED _SB_MAKE64(0xF200000000) -#define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000) - -#define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) -#define PHYS_L2CACHE_NUM_WAYS 4 -#define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000) -#define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000) -#define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) -#define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) -#define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) +#define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000) +#define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) +#define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) +#define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) +#define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) +#define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) +#define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) +#define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) +#define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) +#define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) +#define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) +#define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) +#define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) +#define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000) +#define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000) +#define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000) +#define A_PHYS_RESERVED _SB_MAKE64(0xF200000000) +#define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000) + +#define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) +#define PHYS_L2CACHE_NUM_WAYS 4 +#define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000) +#define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000) +#define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) +#define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) +#define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) #endif diff --git a/arch/mips/include/asm/sibyte/sb1250_scd.h b/arch/mips/include/asm/sibyte/sb1250_scd.h index 615e165dbd2..d725f2f41af 100644 --- a/arch/mips/include/asm/sibyte/sb1250_scd.h +++ b/arch/mips/include/asm/sibyte/sb1250_scd.h @@ -44,10 +44,10 @@ #define M_SYS_RESERVED _SB_MAKEMASK(8, 0) -#define S_SYS_REVISION _SB_MAKE64(8) -#define M_SYS_REVISION _SB_MAKEMASK(8, S_SYS_REVISION) -#define V_SYS_REVISION(x) _SB_MAKEVALUE(x, S_SYS_REVISION) -#define G_SYS_REVISION(x) _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION) +#define S_SYS_REVISION _SB_MAKE64(8) +#define M_SYS_REVISION _SB_MAKEMASK(8, S_SYS_REVISION) +#define V_SYS_REVISION(x) _SB_MAKEVALUE(x, S_SYS_REVISION) +#define G_SYS_REVISION(x) _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION) #define K_SYS_REVISION_BCM1250_PASS1 0x01 @@ -93,10 +93,10 @@ #define K_SYS_REVISION_BCM1480_B0 0x11 /*Cache size - 23:20 of revision register*/ -#define S_SYS_L2C_SIZE _SB_MAKE64(20) -#define M_SYS_L2C_SIZE _SB_MAKEMASK(4, S_SYS_L2C_SIZE) -#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x, S_SYS_L2C_SIZE) -#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE) +#define S_SYS_L2C_SIZE _SB_MAKE64(20) +#define M_SYS_L2C_SIZE _SB_MAKEMASK(4, S_SYS_L2C_SIZE) +#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x, S_SYS_L2C_SIZE) +#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE) #define K_SYS_L2C_SIZE_1MB 0 #define K_SYS_L2C_SIZE_512KB 5 @@ -109,40 +109,40 @@ /* Number of CPU cores, bits 27:24 of revision register*/ -#define S_SYS_NUM_CPUS _SB_MAKE64(24) -#define M_SYS_NUM_CPUS _SB_MAKEMASK(4, S_SYS_NUM_CPUS) -#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x, S_SYS_NUM_CPUS) -#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS) +#define S_SYS_NUM_CPUS _SB_MAKE64(24) +#define M_SYS_NUM_CPUS _SB_MAKEMASK(4, S_SYS_NUM_CPUS) +#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x, S_SYS_NUM_CPUS) +#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS) /* XXX: discourage people from using these constants. */ -#define S_SYS_PART _SB_MAKE64(16) -#define M_SYS_PART _SB_MAKEMASK(16, S_SYS_PART) -#define V_SYS_PART(x) _SB_MAKEVALUE(x, S_SYS_PART) -#define G_SYS_PART(x) _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART) +#define S_SYS_PART _SB_MAKE64(16) +#define M_SYS_PART _SB_MAKEMASK(16, S_SYS_PART) +#define V_SYS_PART(x) _SB_MAKEVALUE(x, S_SYS_PART) +#define G_SYS_PART(x) _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART) /* XXX: discourage people from using these constants. */ -#define K_SYS_PART_SB1250 0x1250 -#define K_SYS_PART_BCM1120 0x1121 -#define K_SYS_PART_BCM1125 0x1123 -#define K_SYS_PART_BCM1125H 0x1124 -#define K_SYS_PART_BCM1122 0x1113 +#define K_SYS_PART_SB1250 0x1250 +#define K_SYS_PART_BCM1120 0x1121 +#define K_SYS_PART_BCM1125 0x1123 +#define K_SYS_PART_BCM1125H 0x1124 +#define K_SYS_PART_BCM1122 0x1113 /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ -#define S_SYS_SOC_TYPE _SB_MAKE64(16) -#define M_SYS_SOC_TYPE _SB_MAKEMASK(4, S_SYS_SOC_TYPE) -#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x, S_SYS_SOC_TYPE) -#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE) - -#define K_SYS_SOC_TYPE_BCM1250 0x0 -#define K_SYS_SOC_TYPE_BCM1120 0x1 -#define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */ -#define K_SYS_SOC_TYPE_BCM1125 0x3 -#define K_SYS_SOC_TYPE_BCM1125H 0x4 -#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ -#define K_SYS_SOC_TYPE_BCM1x80 0x6 -#define K_SYS_SOC_TYPE_BCM1x55 0x7 +#define S_SYS_SOC_TYPE _SB_MAKE64(16) +#define M_SYS_SOC_TYPE _SB_MAKEMASK(4, S_SYS_SOC_TYPE) +#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x, S_SYS_SOC_TYPE) +#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE) + +#define K_SYS_SOC_TYPE_BCM1250 0x0 +#define K_SYS_SOC_TYPE_BCM1120 0x1 +#define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */ +#define K_SYS_SOC_TYPE_BCM1125 0x3 +#define K_SYS_SOC_TYPE_BCM1125H 0x4 +#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ +#define K_SYS_SOC_TYPE_BCM1x80 0x6 +#define K_SYS_SOC_TYPE_BCM1x55 0x7 /* * Calculate correct SOC type given a copy of system revision register. @@ -169,10 +169,10 @@ ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev)) #endif -#define S_SYS_WID _SB_MAKE64(32) -#define M_SYS_WID _SB_MAKEMASK(32, S_SYS_WID) -#define V_SYS_WID(x) _SB_MAKEVALUE(x, S_SYS_WID) -#define G_SYS_WID(x) _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID) +#define S_SYS_WID _SB_MAKE64(32) +#define M_SYS_WID _SB_MAKEMASK(32, S_SYS_WID) +#define V_SYS_WID(x) _SB_MAKEVALUE(x, S_SYS_WID) +#define G_SYS_WID(x) _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID) /* * System Manufacturing Register @@ -181,37 +181,37 @@ #if SIBYTE_HDR_FEATURE_1250_112x /* Wafer ID: bits 31:0 */ -#define S_SYS_WAFERID1_200 _SB_MAKE64(0) -#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32, S_SYS_WAFERID1_200) -#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID1_200) -#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200) +#define S_SYS_WAFERID1_200 _SB_MAKE64(0) +#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32, S_SYS_WAFERID1_200) +#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID1_200) +#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200) -#define S_SYS_BIN _SB_MAKE64(32) -#define M_SYS_BIN _SB_MAKEMASK(4, S_SYS_BIN) -#define V_SYS_BIN(x) _SB_MAKEVALUE(x, S_SYS_BIN) -#define G_SYS_BIN(x) _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN) +#define S_SYS_BIN _SB_MAKE64(32) +#define M_SYS_BIN _SB_MAKEMASK(4, S_SYS_BIN) +#define V_SYS_BIN(x) _SB_MAKEVALUE(x, S_SYS_BIN) +#define G_SYS_BIN(x) _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN) /* Wafer ID: bits 39:36 */ -#define S_SYS_WAFERID2_200 _SB_MAKE64(36) -#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4, S_SYS_WAFERID2_200) -#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID2_200) -#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200) +#define S_SYS_WAFERID2_200 _SB_MAKE64(36) +#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4, S_SYS_WAFERID2_200) +#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID2_200) +#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200) /* Wafer ID: bits 39:0 */ -#define S_SYS_WAFERID_300 _SB_MAKE64(0) -#define M_SYS_WAFERID_300 _SB_MAKEMASK(40, S_SYS_WAFERID_300) -#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x, S_SYS_WAFERID_300) -#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300) - -#define S_SYS_XPOS _SB_MAKE64(40) -#define M_SYS_XPOS _SB_MAKEMASK(6, S_SYS_XPOS) -#define V_SYS_XPOS(x) _SB_MAKEVALUE(x, S_SYS_XPOS) -#define G_SYS_XPOS(x) _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS) - -#define S_SYS_YPOS _SB_MAKE64(46) -#define M_SYS_YPOS _SB_MAKEMASK(6, S_SYS_YPOS) -#define V_SYS_YPOS(x) _SB_MAKEVALUE(x, S_SYS_YPOS) -#define G_SYS_YPOS(x) _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS) +#define S_SYS_WAFERID_300 _SB_MAKE64(0) +#define M_SYS_WAFERID_300 _SB_MAKEMASK(40, S_SYS_WAFERID_300) +#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x, S_SYS_WAFERID_300) +#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300) + +#define S_SYS_XPOS _SB_MAKE64(40) +#define M_SYS_XPOS _SB_MAKEMASK(6, S_SYS_XPOS) +#define V_SYS_XPOS(x) _SB_MAKEVALUE(x, S_SYS_XPOS) +#define G_SYS_XPOS(x) _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS) + +#define S_SYS_YPOS _SB_MAKE64(46) +#define M_SYS_YPOS _SB_MAKEMASK(6, S_SYS_YPOS) +#define V_SYS_YPOS(x) _SB_MAKEVALUE(x, S_SYS_YPOS) +#define G_SYS_YPOS(x) _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS) #endif @@ -221,55 +221,55 @@ */ #if SIBYTE_HDR_FEATURE_1250_112x -#define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) +#define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) -#define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) -#define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) - -#define S_SYS_PLL_DIV _SB_MAKE64(7) -#define M_SYS_PLL_DIV _SB_MAKEMASK(5, S_SYS_PLL_DIV) -#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_SYS_PLL_DIV) -#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV) - -#define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) -#define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) -#define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) -#define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) -#define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) - -#define S_SYS_BOOT_MODE _SB_MAKE64(17) -#define M_SYS_BOOT_MODE _SB_MAKEMASK(2, S_SYS_BOOT_MODE) -#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_SYS_BOOT_MODE) -#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE) -#define K_SYS_BOOT_MODE_ROM32 0 -#define K_SYS_BOOT_MODE_ROM8 1 +#define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) +#define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) + +#define S_SYS_PLL_DIV _SB_MAKE64(7) +#define M_SYS_PLL_DIV _SB_MAKEMASK(5, S_SYS_PLL_DIV) +#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_SYS_PLL_DIV) +#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV) + +#define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) +#define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) +#define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) +#define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) +#define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) + +#define S_SYS_BOOT_MODE _SB_MAKE64(17) +#define M_SYS_BOOT_MODE _SB_MAKEMASK(2, S_SYS_BOOT_MODE) +#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_SYS_BOOT_MODE) +#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE) +#define K_SYS_BOOT_MODE_ROM32 0 +#define K_SYS_BOOT_MODE_ROM8 1 #define K_SYS_BOOT_MODE_SMBUS_SMALL 2 #define K_SYS_BOOT_MODE_SMBUS_BIG 3 -#define M_SYS_PCI_HOST _SB_MAKEMASK1(19) -#define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) -#define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) -#define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) -#define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) -#define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) -#define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) +#define M_SYS_PCI_HOST _SB_MAKEMASK1(19) +#define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) +#define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) +#define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) +#define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) +#define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) +#define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) -#define S_SYS_CONFIG 26 -#define M_SYS_CONFIG _SB_MAKEMASK(6, S_SYS_CONFIG) -#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_SYS_CONFIG) -#define G_SYS_CONFIG(x) _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG) +#define S_SYS_CONFIG 26 +#define M_SYS_CONFIG _SB_MAKEMASK(6, S_SYS_CONFIG) +#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_SYS_CONFIG) +#define G_SYS_CONFIG(x) _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG) /* The following bits are writeable by JTAG only. */ -#define M_SYS_CLKSTOP _SB_MAKEMASK1(32) -#define M_SYS_CLKSTEP _SB_MAKEMASK1(33) +#define M_SYS_CLKSTOP _SB_MAKEMASK1(32) +#define M_SYS_CLKSTEP _SB_MAKEMASK1(33) -#define S_SYS_CLKCOUNT 34 -#define M_SYS_CLKCOUNT _SB_MAKEMASK(8, S_SYS_CLKCOUNT) -#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x, S_SYS_CLKCOUNT) -#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT) +#define S_SYS_CLKCOUNT 34 +#define M_SYS_CLKCOUNT _SB_MAKEMASK(8, S_SYS_CLKCOUNT) +#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x, S_SYS_CLKCOUNT) +#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT) -#define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) +#define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) #define S_SYS_PLL_IREF 43 #define M_SYS_PLL_IREF _SB_MAKEMASK(2, S_SYS_PLL_IREF) @@ -280,26 +280,26 @@ #define S_SYS_PLL_VREG 47 #define M_SYS_PLL_VREG _SB_MAKEMASK(2, S_SYS_PLL_VREG) -#define M_SYS_MEM_RESET _SB_MAKEMASK1(49) -#define M_SYS_L2C_RESET _SB_MAKEMASK1(50) -#define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) -#define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) -#define M_SYS_SCD_RESET _SB_MAKEMASK1(53) +#define M_SYS_MEM_RESET _SB_MAKEMASK1(49) +#define M_SYS_L2C_RESET _SB_MAKEMASK1(50) +#define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) +#define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) +#define M_SYS_SCD_RESET _SB_MAKEMASK1(53) /* End of bits writable by JTAG only. */ -#define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) -#define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) +#define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) +#define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) -#define M_SYS_UNICPU0 _SB_MAKEMASK1(56) -#define M_SYS_UNICPU1 _SB_MAKEMASK1(57) +#define M_SYS_UNICPU0 _SB_MAKEMASK1(56) +#define M_SYS_UNICPU1 _SB_MAKEMASK1(57) -#define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) -#define M_SYS_EXT_RESET _SB_MAKEMASK1(59) -#define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) +#define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) +#define M_SYS_EXT_RESET _SB_MAKEMASK1(59) +#define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) -#define M_SYS_MISR_MODE _SB_MAKEMASK1(61) -#define M_SYS_MISR_RESET _SB_MAKEMASK1(62) +#define M_SYS_MISR_MODE _SB_MAKEMASK1(61) +#define M_SYS_MISR_RESET _SB_MAKEMASK1(62) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) #define M_SYS_SW_FLAG _SB_MAKEMASK1(63) @@ -313,46 +313,46 @@ * Registers: SCD_MBOX_CPU_x */ -#define S_MBOX_INT_3 0 -#define M_MBOX_INT_3 _SB_MAKEMASK(16, S_MBOX_INT_3) -#define S_MBOX_INT_2 16 -#define M_MBOX_INT_2 _SB_MAKEMASK(16, S_MBOX_INT_2) -#define S_MBOX_INT_1 32 -#define M_MBOX_INT_1 _SB_MAKEMASK(16, S_MBOX_INT_1) -#define S_MBOX_INT_0 48 -#define M_MBOX_INT_0 _SB_MAKEMASK(16, S_MBOX_INT_0) +#define S_MBOX_INT_3 0 +#define M_MBOX_INT_3 _SB_MAKEMASK(16, S_MBOX_INT_3) +#define S_MBOX_INT_2 16 +#define M_MBOX_INT_2 _SB_MAKEMASK(16, S_MBOX_INT_2) +#define S_MBOX_INT_1 32 +#define M_MBOX_INT_1 _SB_MAKEMASK(16, S_MBOX_INT_1) +#define S_MBOX_INT_0 48 +#define M_MBOX_INT_0 _SB_MAKEMASK(16, S_MBOX_INT_0) /* * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) * Registers: SCD_WDOG_INIT_CNT_x */ -#define V_SCD_WDOG_FREQ 1000000 +#define V_SCD_WDOG_FREQ 1000000 -#define S_SCD_WDOG_INIT 0 -#define M_SCD_WDOG_INIT _SB_MAKEMASK(23, S_SCD_WDOG_INIT) +#define S_SCD_WDOG_INIT 0 +#define M_SCD_WDOG_INIT _SB_MAKEMASK(23, S_SCD_WDOG_INIT) -#define S_SCD_WDOG_CNT 0 -#define M_SCD_WDOG_CNT _SB_MAKEMASK(23, S_SCD_WDOG_CNT) +#define S_SCD_WDOG_CNT 0 +#define M_SCD_WDOG_CNT _SB_MAKEMASK(23, S_SCD_WDOG_CNT) -#define S_SCD_WDOG_ENABLE 0 -#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) +#define S_SCD_WDOG_ENABLE 0 +#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) -#define S_SCD_WDOG_RESET_TYPE 2 -#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE) +#define S_SCD_WDOG_RESET_TYPE 2 +#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE) #define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE) #define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE) -#define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ -#define K_SCD_WDOG_RESET_SOFT 1 -#define K_SCD_WDOG_RESET_CPU0 3 -#define K_SCD_WDOG_RESET_CPU1 5 +#define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ +#define K_SCD_WDOG_RESET_SOFT 1 +#define K_SCD_WDOG_RESET_CPU0 3 +#define K_SCD_WDOG_RESET_CPU1 5 #define K_SCD_WDOG_RESET_BOTH_CPUS 7 /* This feature is present in 1250 C0 and later, but *not* in 112x A revs. */ #if SIBYTE_HDR_FEATURE(1250, PASS3) -#define S_SCD_WDOG_HAS_RESET 8 -#define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET) +#define S_SCD_WDOG_HAS_RESET 8 +#define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET) #endif @@ -360,46 +360,46 @@ * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13) */ -#define V_SCD_TIMER_FREQ 1000000 +#define V_SCD_TIMER_FREQ 1000000 -#define S_SCD_TIMER_INIT 0 -#define M_SCD_TIMER_INIT _SB_MAKEMASK(23, S_SCD_TIMER_INIT) -#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_INIT) -#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT) +#define S_SCD_TIMER_INIT 0 +#define M_SCD_TIMER_INIT _SB_MAKEMASK(23, S_SCD_TIMER_INIT) +#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_INIT) +#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT) #define V_SCD_TIMER_WIDTH 23 -#define S_SCD_TIMER_CNT 0 -#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT) -#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_CNT) -#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT) +#define S_SCD_TIMER_CNT 0 +#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT) +#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_CNT) +#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT) -#define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) -#define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) +#define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) +#define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE /* * System Performance Counters */ -#define S_SPC_CFG_SRC0 0 -#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8, S_SPC_CFG_SRC0) -#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC0) -#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0) +#define S_SPC_CFG_SRC0 0 +#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8, S_SPC_CFG_SRC0) +#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC0) +#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0) -#define S_SPC_CFG_SRC1 8 -#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8, S_SPC_CFG_SRC1) -#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC1) -#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1) +#define S_SPC_CFG_SRC1 8 +#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8, S_SPC_CFG_SRC1) +#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC1) +#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1) -#define S_SPC_CFG_SRC2 16 -#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8, S_SPC_CFG_SRC2) -#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC2) -#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2) +#define S_SPC_CFG_SRC2 16 +#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8, S_SPC_CFG_SRC2) +#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC2) +#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2) -#define S_SPC_CFG_SRC3 24 -#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8, S_SPC_CFG_SRC3) -#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC3) -#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3) +#define S_SPC_CFG_SRC3 24 +#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8, S_SPC_CFG_SRC3) +#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC3) +#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3) #if SIBYTE_HDR_FEATURE_1250_112x #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) @@ -411,58 +411,58 @@ * Bus Watcher */ -#define S_SCD_BERR_TID 8 -#define M_SCD_BERR_TID _SB_MAKEMASK(10, S_SCD_BERR_TID) -#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x, S_SCD_BERR_TID) -#define G_SCD_BERR_TID(x) _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID) +#define S_SCD_BERR_TID 8 +#define M_SCD_BERR_TID _SB_MAKEMASK(10, S_SCD_BERR_TID) +#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x, S_SCD_BERR_TID) +#define G_SCD_BERR_TID(x) _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID) -#define S_SCD_BERR_RID 18 -#define M_SCD_BERR_RID _SB_MAKEMASK(4, S_SCD_BERR_RID) -#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x, S_SCD_BERR_RID) -#define G_SCD_BERR_RID(x) _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID) +#define S_SCD_BERR_RID 18 +#define M_SCD_BERR_RID _SB_MAKEMASK(4, S_SCD_BERR_RID) +#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x, S_SCD_BERR_RID) +#define G_SCD_BERR_RID(x) _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID) -#define S_SCD_BERR_DCODE 22 -#define M_SCD_BERR_DCODE _SB_MAKEMASK(3, S_SCD_BERR_DCODE) -#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x, S_SCD_BERR_DCODE) -#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE) +#define S_SCD_BERR_DCODE 22 +#define M_SCD_BERR_DCODE _SB_MAKEMASK(3, S_SCD_BERR_DCODE) +#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x, S_SCD_BERR_DCODE) +#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE) -#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) +#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) -#define S_SCD_L2ECC_CORR_D 0 -#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D) -#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D) -#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D) +#define S_SCD_L2ECC_CORR_D 0 +#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D) +#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D) +#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D) -#define S_SCD_L2ECC_BAD_D 8 -#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D) -#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D) -#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D) +#define S_SCD_L2ECC_BAD_D 8 +#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D) +#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D) +#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D) -#define S_SCD_L2ECC_CORR_T 16 -#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T) -#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T) -#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T) +#define S_SCD_L2ECC_CORR_T 16 +#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T) +#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T) +#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T) -#define S_SCD_L2ECC_BAD_T 24 -#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T) -#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T) -#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T) +#define S_SCD_L2ECC_BAD_T 24 +#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T) +#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T) +#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T) -#define S_SCD_MEM_ECC_CORR 0 -#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR) -#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR) -#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR) +#define S_SCD_MEM_ECC_CORR 0 +#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR) +#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR) +#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR) -#define S_SCD_MEM_ECC_BAD 8 -#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD) -#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD) -#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD) +#define S_SCD_MEM_ECC_BAD 8 +#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD) +#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD) +#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD) -#define S_SCD_MEM_BUSERR 16 -#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8, S_SCD_MEM_BUSERR) -#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR) -#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR) +#define S_SCD_MEM_BUSERR 16 +#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8, S_SCD_MEM_BUSERR) +#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR) +#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR) /* @@ -473,28 +473,28 @@ #define M_ATRAP_INDEX _SB_MAKEMASK(4, 0) #define M_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) -#define S_ATRAP_CFG_CNT 0 -#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_ATRAP_CFG_CNT) -#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT) -#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT) +#define S_ATRAP_CFG_CNT 0 +#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_ATRAP_CFG_CNT) +#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT) +#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT) #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) -#define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) -#define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) +#define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) +#define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) -#define S_ATRAP_CFG_AGENTID 8 -#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID) -#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID) -#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID) +#define S_ATRAP_CFG_AGENTID 8 +#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID) +#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID) +#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID) #define K_BUS_AGENT_CPU0 0 #define K_BUS_AGENT_CPU1 1 #define K_BUS_AGENT_IOB0 2 #define K_BUS_AGENT_IOB1 3 -#define K_BUS_AGENT_SCD 4 -#define K_BUS_AGENT_L2C 6 +#define K_BUS_AGENT_SCD 4 +#define K_BUS_AGENT_L2C 6 #define K_BUS_AGENT_MC 7 #define S_ATRAP_CFG_CATTR 12 @@ -503,13 +503,13 @@ #define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR) #define K_ATRAP_CFG_CATTR_IGNORE 0 -#define K_ATRAP_CFG_CATTR_UNC 1 +#define K_ATRAP_CFG_CATTR_UNC 1 #define K_ATRAP_CFG_CATTR_CACHEABLE 2 -#define K_ATRAP_CFG_CATTR_NONCOH 3 +#define K_ATRAP_CFG_CATTR_NONCOH 3 #define K_ATRAP_CFG_CATTR_COHERENT 4 #define K_ATRAP_CFG_CATTR_NOTUNC 5 #define K_ATRAP_CFG_CATTR_NOTNONCOH 6 -#define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 +#define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 #endif /* 1250/112x */ @@ -517,16 +517,16 @@ * Trace Buffer Config register */ -#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) -#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) -#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) -#define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) -#define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) -#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) -#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) -#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) +#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) +#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) +#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) +#define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) +#define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) +#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) +#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) +#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) +#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ /* @@ -534,121 +534,121 @@ * a slightly different place in the register. */ #if SIBYTE_HDR_FEATURE_1250_112x -#define S_SCD_TRACE_CFG_CUR_ADDR 10 +#define S_SCD_TRACE_CFG_CUR_ADDR 10 #else #if SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_SCD_TRACE_CFG_CUR_ADDR 24 +#define S_SCD_TRACE_CFG_CUR_ADDR 24 #endif /* 1480 */ -#endif /* 1250/112x */ +#endif /* 1250/112x */ -#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR) -#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR) -#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR) +#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR) +#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR) +#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR) /* * Trace Event registers */ -#define S_SCD_TREVT_ADDR_MATCH 0 -#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH) -#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH) -#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH) - -#define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) -#define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) -#define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) -#define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) -#define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) -#define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) -#define M_SCD_TREVT_READ _SB_MAKEMASK1(11) - -#define S_SCD_TREVT_REQID 12 -#define M_SCD_TREVT_REQID _SB_MAKEMASK(4, S_SCD_TREVT_REQID) -#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_REQID) -#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID) - -#define S_SCD_TREVT_RESPID 16 -#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4, S_SCD_TREVT_RESPID) -#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID) -#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID) - -#define S_SCD_TREVT_DATAID 20 -#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4, S_SCD_TREVT_DATAID) -#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID) -#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID) - -#define S_SCD_TREVT_COUNT 24 -#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8, S_SCD_TREVT_COUNT) -#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT) -#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT) +#define S_SCD_TREVT_ADDR_MATCH 0 +#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH) +#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH) +#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH) + +#define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) +#define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) +#define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) +#define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) +#define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) +#define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) +#define M_SCD_TREVT_READ _SB_MAKEMASK1(11) + +#define S_SCD_TREVT_REQID 12 +#define M_SCD_TREVT_REQID _SB_MAKEMASK(4, S_SCD_TREVT_REQID) +#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_REQID) +#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID) + +#define S_SCD_TREVT_RESPID 16 +#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4, S_SCD_TREVT_RESPID) +#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID) +#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID) + +#define S_SCD_TREVT_DATAID 20 +#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4, S_SCD_TREVT_DATAID) +#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID) +#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID) + +#define S_SCD_TREVT_COUNT 24 +#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8, S_SCD_TREVT_COUNT) +#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT) +#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT) /* * Trace Sequence registers */ -#define S_SCD_TRSEQ_EVENT4 0 -#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4) -#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4) -#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4) - -#define S_SCD_TRSEQ_EVENT3 4 -#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3) -#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3) -#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3) - -#define S_SCD_TRSEQ_EVENT2 8 -#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2) -#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2) -#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2) - -#define S_SCD_TRSEQ_EVENT1 12 -#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1) -#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1) -#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1) - -#define K_SCD_TRSEQ_E0 0 -#define K_SCD_TRSEQ_E1 1 -#define K_SCD_TRSEQ_E2 2 -#define K_SCD_TRSEQ_E3 3 -#define K_SCD_TRSEQ_E0_E1 4 -#define K_SCD_TRSEQ_E1_E2 5 -#define K_SCD_TRSEQ_E2_E3 6 -#define K_SCD_TRSEQ_E0_E1_E2 7 -#define K_SCD_TRSEQ_E0_E1_E2_E3 8 -#define K_SCD_TRSEQ_E0E1 9 -#define K_SCD_TRSEQ_E0E1E2 10 -#define K_SCD_TRSEQ_E0E1E2E3 11 -#define K_SCD_TRSEQ_E0E1_E2 12 -#define K_SCD_TRSEQ_E0E1_E2E3 13 -#define K_SCD_TRSEQ_E0E1_E2_E3 14 -#define K_SCD_TRSEQ_IGNORED 15 - -#define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ - V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ - V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ - V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) - -#define S_SCD_TRSEQ_FUNCTION 16 -#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION) -#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION) -#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION) - -#define K_SCD_TRSEQ_FUNC_NOP 0 -#define K_SCD_TRSEQ_FUNC_START 1 -#define K_SCD_TRSEQ_FUNC_STOP 2 -#define K_SCD_TRSEQ_FUNC_FREEZE 3 - -#define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) -#define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) -#define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) -#define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) - -#define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) -#define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) -#define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) -#define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) -#define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) -#define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23) -#define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24) +#define S_SCD_TRSEQ_EVENT4 0 +#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4) +#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4) +#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4) + +#define S_SCD_TRSEQ_EVENT3 4 +#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3) +#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3) +#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3) + +#define S_SCD_TRSEQ_EVENT2 8 +#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2) +#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2) +#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2) + +#define S_SCD_TRSEQ_EVENT1 12 +#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1) +#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1) +#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1) + +#define K_SCD_TRSEQ_E0 0 +#define K_SCD_TRSEQ_E1 1 +#define K_SCD_TRSEQ_E2 2 +#define K_SCD_TRSEQ_E3 3 +#define K_SCD_TRSEQ_E0_E1 4 +#define K_SCD_TRSEQ_E1_E2 5 +#define K_SCD_TRSEQ_E2_E3 6 +#define K_SCD_TRSEQ_E0_E1_E2 7 +#define K_SCD_TRSEQ_E0_E1_E2_E3 8 +#define K_SCD_TRSEQ_E0E1 9 +#define K_SCD_TRSEQ_E0E1E2 10 +#define K_SCD_TRSEQ_E0E1E2E3 11 +#define K_SCD_TRSEQ_E0E1_E2 12 +#define K_SCD_TRSEQ_E0E1_E2E3 13 +#define K_SCD_TRSEQ_E0E1_E2_E3 14 +#define K_SCD_TRSEQ_IGNORED 15 + +#define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ + V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ + V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ + V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) + +#define S_SCD_TRSEQ_FUNCTION 16 +#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION) +#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION) +#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION) + +#define K_SCD_TRSEQ_FUNC_NOP 0 +#define K_SCD_TRSEQ_FUNC_START 1 +#define K_SCD_TRSEQ_FUNC_STOP 2 +#define K_SCD_TRSEQ_FUNC_FREEZE 3 + +#define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) +#define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) +#define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) +#define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) + +#define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) +#define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) +#define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) +#define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) +#define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) +#define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23) +#define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24) #endif diff --git a/arch/mips/include/asm/sibyte/sb1250_smbus.h b/arch/mips/include/asm/sibyte/sb1250_smbus.h index 128d6b75b81..3cb73e89bbb 100644 --- a/arch/mips/include/asm/sibyte/sb1250_smbus.h +++ b/arch/mips/include/asm/sibyte/sb1250_smbus.h @@ -1,7 +1,7 @@ /* ********************************************************************* * SB1250 Board Support Package * - * SMBUS Constants File: sb1250_smbus.h + * SMBUS Constants File: sb1250_smbus.h * * This module contains constants and macros useful for * manipulating the SB1250's SMbus devices. @@ -40,83 +40,83 @@ * SMBus Clock Frequency Register (Table 14-2) */ -#define S_SMB_FREQ_DIV 0 -#define M_SMB_FREQ_DIV _SB_MAKEMASK(13, S_SMB_FREQ_DIV) -#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x, S_SMB_FREQ_DIV) +#define S_SMB_FREQ_DIV 0 +#define M_SMB_FREQ_DIV _SB_MAKEMASK(13, S_SMB_FREQ_DIV) +#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x, S_SMB_FREQ_DIV) #define K_SMB_FREQ_400KHZ 0x1F #define K_SMB_FREQ_100KHZ 0x7D #define K_SMB_FREQ_10KHZ 1250 -#define S_SMB_CMD 0 -#define M_SMB_CMD _SB_MAKEMASK(8, S_SMB_CMD) -#define V_SMB_CMD(x) _SB_MAKEVALUE(x, S_SMB_CMD) +#define S_SMB_CMD 0 +#define M_SMB_CMD _SB_MAKEMASK(8, S_SMB_CMD) +#define V_SMB_CMD(x) _SB_MAKEVALUE(x, S_SMB_CMD) /* * SMBus control register (Table 14-4) */ -#define M_SMB_ERR_INTR _SB_MAKEMASK1(0) -#define M_SMB_FINISH_INTR _SB_MAKEMASK1(1) +#define M_SMB_ERR_INTR _SB_MAKEMASK1(0) +#define M_SMB_FINISH_INTR _SB_MAKEMASK1(1) -#define S_SMB_DATA_OUT 4 -#define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT) -#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x, S_SMB_DATA_OUT) +#define S_SMB_DATA_OUT 4 +#define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT) +#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x, S_SMB_DATA_OUT) -#define M_SMB_DATA_DIR _SB_MAKEMASK1(5) -#define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR -#define M_SMB_CLK_OUT _SB_MAKEMASK1(6) -#define M_SMB_DIRECT_ENABLE _SB_MAKEMASK1(7) +#define M_SMB_DATA_DIR _SB_MAKEMASK1(5) +#define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR +#define M_SMB_CLK_OUT _SB_MAKEMASK1(6) +#define M_SMB_DIRECT_ENABLE _SB_MAKEMASK1(7) /* * SMBus status registers (Table 14-5) */ -#define M_SMB_BUSY _SB_MAKEMASK1(0) -#define M_SMB_ERROR _SB_MAKEMASK1(1) -#define M_SMB_ERROR_TYPE _SB_MAKEMASK1(2) +#define M_SMB_BUSY _SB_MAKEMASK1(0) +#define M_SMB_ERROR _SB_MAKEMASK1(1) +#define M_SMB_ERROR_TYPE _SB_MAKEMASK1(2) #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_SMB_SCL_IN 5 -#define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN) -#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x, S_SMB_SCL_IN) -#define G_SMB_SCL_IN(x) _SB_GETVALUE(x, S_SMB_SCL_IN, M_SMB_SCL_IN) +#define S_SMB_SCL_IN 5 +#define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN) +#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x, S_SMB_SCL_IN) +#define G_SMB_SCL_IN(x) _SB_GETVALUE(x, S_SMB_SCL_IN, M_SMB_SCL_IN) #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ -#define S_SMB_REF 6 -#define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF) -#define V_SMB_REF(x) _SB_MAKEVALUE(x, S_SMB_REF) -#define G_SMB_REF(x) _SB_GETVALUE(x, S_SMB_REF, M_SMB_REF) +#define S_SMB_REF 6 +#define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF) +#define V_SMB_REF(x) _SB_MAKEVALUE(x, S_SMB_REF) +#define G_SMB_REF(x) _SB_GETVALUE(x, S_SMB_REF, M_SMB_REF) -#define S_SMB_DATA_IN 7 -#define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN) -#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x, S_SMB_DATA_IN) -#define G_SMB_DATA_IN(x) _SB_GETVALUE(x, S_SMB_DATA_IN, M_SMB_DATA_IN) +#define S_SMB_DATA_IN 7 +#define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN) +#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x, S_SMB_DATA_IN) +#define G_SMB_DATA_IN(x) _SB_GETVALUE(x, S_SMB_DATA_IN, M_SMB_DATA_IN) /* * SMBus Start/Command registers (Table 14-9) */ -#define S_SMB_ADDR 0 -#define M_SMB_ADDR _SB_MAKEMASK(7, S_SMB_ADDR) -#define V_SMB_ADDR(x) _SB_MAKEVALUE(x, S_SMB_ADDR) -#define G_SMB_ADDR(x) _SB_GETVALUE(x, S_SMB_ADDR, M_SMB_ADDR) +#define S_SMB_ADDR 0 +#define M_SMB_ADDR _SB_MAKEMASK(7, S_SMB_ADDR) +#define V_SMB_ADDR(x) _SB_MAKEVALUE(x, S_SMB_ADDR) +#define G_SMB_ADDR(x) _SB_GETVALUE(x, S_SMB_ADDR, M_SMB_ADDR) -#define M_SMB_QDATA _SB_MAKEMASK1(7) +#define M_SMB_QDATA _SB_MAKEMASK1(7) -#define S_SMB_TT 8 -#define M_SMB_TT _SB_MAKEMASK(3, S_SMB_TT) -#define V_SMB_TT(x) _SB_MAKEVALUE(x, S_SMB_TT) -#define G_SMB_TT(x) _SB_GETVALUE(x, S_SMB_TT, M_SMB_TT) +#define S_SMB_TT 8 +#define M_SMB_TT _SB_MAKEMASK(3, S_SMB_TT) +#define V_SMB_TT(x) _SB_MAKEVALUE(x, S_SMB_TT) +#define G_SMB_TT(x) _SB_GETVALUE(x, S_SMB_TT, M_SMB_TT) -#define K_SMB_TT_WR1BYTE 0 -#define K_SMB_TT_WR2BYTE 1 -#define K_SMB_TT_WR3BYTE 2 -#define K_SMB_TT_CMD_RD1BYTE 3 -#define K_SMB_TT_CMD_RD2BYTE 4 -#define K_SMB_TT_RD1BYTE 5 -#define K_SMB_TT_QUICKCMD 6 -#define K_SMB_TT_EEPROMREAD 7 +#define K_SMB_TT_WR1BYTE 0 +#define K_SMB_TT_WR2BYTE 1 +#define K_SMB_TT_WR3BYTE 2 +#define K_SMB_TT_CMD_RD1BYTE 3 +#define K_SMB_TT_CMD_RD2BYTE 4 +#define K_SMB_TT_RD1BYTE 5 +#define K_SMB_TT_QUICKCMD 6 +#define K_SMB_TT_EEPROMREAD 7 #define V_SMB_TT_WR1BYTE V_SMB_TT(K_SMB_TT_WR1BYTE) #define V_SMB_TT_WR2BYTE V_SMB_TT(K_SMB_TT_WR2BYTE) @@ -127,51 +127,51 @@ #define V_SMB_TT_QUICKCMD V_SMB_TT(K_SMB_TT_QUICKCMD) #define V_SMB_TT_EEPROMREAD V_SMB_TT(K_SMB_TT_EEPROMREAD) -#define M_SMB_PEC _SB_MAKEMASK1(15) +#define M_SMB_PEC _SB_MAKEMASK1(15) /* * SMBus Data Register (Table 14-6) and SMBus Extra Register (Table 14-7) */ -#define S_SMB_LB 0 -#define M_SMB_LB _SB_MAKEMASK(8, S_SMB_LB) -#define V_SMB_LB(x) _SB_MAKEVALUE(x, S_SMB_LB) +#define S_SMB_LB 0 +#define M_SMB_LB _SB_MAKEMASK(8, S_SMB_LB) +#define V_SMB_LB(x) _SB_MAKEVALUE(x, S_SMB_LB) -#define S_SMB_MB 8 -#define M_SMB_MB _SB_MAKEMASK(8, S_SMB_MB) -#define V_SMB_MB(x) _SB_MAKEVALUE(x, S_SMB_MB) +#define S_SMB_MB 8 +#define M_SMB_MB _SB_MAKEMASK(8, S_SMB_MB) +#define V_SMB_MB(x) _SB_MAKEVALUE(x, S_SMB_MB) /* * SMBus Packet Error Check register (Table 14-8) */ -#define S_SPEC_PEC 0 -#define M_SPEC_PEC _SB_MAKEMASK(8, S_SPEC_PEC) -#define V_SPEC_MB(x) _SB_MAKEVALUE(x, S_SPEC_PEC) +#define S_SPEC_PEC 0 +#define M_SPEC_PEC _SB_MAKEMASK(8, S_SPEC_PEC) +#define V_SPEC_MB(x) _SB_MAKEVALUE(x, S_SPEC_PEC) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define S_SMB_CMDH 8 -#define M_SMB_CMDH _SB_MAKEMASK(8, S_SMB_CMDH) -#define V_SMB_CMDH(x) _SB_MAKEVALUE(x, S_SMB_CMDH) +#define S_SMB_CMDH 8 +#define M_SMB_CMDH _SB_MAKEMASK(8, S_SMB_CMDH) +#define V_SMB_CMDH(x) _SB_MAKEVALUE(x, S_SMB_CMDH) #define M_SMB_EXTEND _SB_MAKEMASK1(14) -#define S_SMB_DFMT 8 -#define M_SMB_DFMT _SB_MAKEMASK(3, S_SMB_DFMT) -#define V_SMB_DFMT(x) _SB_MAKEVALUE(x, S_SMB_DFMT) -#define G_SMB_DFMT(x) _SB_GETVALUE(x, S_SMB_DFMT, M_SMB_DFMT) +#define S_SMB_DFMT 8 +#define M_SMB_DFMT _SB_MAKEMASK(3, S_SMB_DFMT) +#define V_SMB_DFMT(x) _SB_MAKEVALUE(x, S_SMB_DFMT) +#define G_SMB_DFMT(x) _SB_GETVALUE(x, S_SMB_DFMT, M_SMB_DFMT) -#define K_SMB_DFMT_1BYTE 0 -#define K_SMB_DFMT_2BYTE 1 -#define K_SMB_DFMT_3BYTE 2 -#define K_SMB_DFMT_4BYTE 3 -#define K_SMB_DFMT_NODATA 4 -#define K_SMB_DFMT_CMD4BYTE 5 -#define K_SMB_DFMT_CMD5BYTE 6 -#define K_SMB_DFMT_RESERVED 7 +#define K_SMB_DFMT_1BYTE 0 +#define K_SMB_DFMT_2BYTE 1 +#define K_SMB_DFMT_3BYTE 2 +#define K_SMB_DFMT_4BYTE 3 +#define K_SMB_DFMT_NODATA 4 +#define K_SMB_DFMT_CMD4BYTE 5 +#define K_SMB_DFMT_CMD5BYTE 6 +#define K_SMB_DFMT_RESERVED 7 #define V_SMB_DFMT_1BYTE V_SMB_DFMT(K_SMB_DFMT_1BYTE) #define V_SMB_DFMT_2BYTE V_SMB_DFMT(K_SMB_DFMT_2BYTE) @@ -182,13 +182,13 @@ #define V_SMB_DFMT_CMD5BYTE V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE) #define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED) -#define S_SMB_AFMT 11 -#define M_SMB_AFMT _SB_MAKEMASK(2, S_SMB_AFMT) -#define V_SMB_AFMT(x) _SB_MAKEVALUE(x, S_SMB_AFMT) -#define G_SMB_AFMT(x) _SB_GETVALUE(x, S_SMB_AFMT, M_SMB_AFMT) +#define S_SMB_AFMT 11 +#define M_SMB_AFMT _SB_MAKEMASK(2, S_SMB_AFMT) +#define V_SMB_AFMT(x) _SB_MAKEVALUE(x, S_SMB_AFMT) +#define G_SMB_AFMT(x) _SB_GETVALUE(x, S_SMB_AFMT, M_SMB_AFMT) -#define K_SMB_AFMT_NONE 0 -#define K_SMB_AFMT_ADDR 1 +#define K_SMB_AFMT_NONE 0 +#define K_SMB_AFMT_ADDR 1 #define K_SMB_AFMT_ADDR_CMD1BYTE 2 #define K_SMB_AFMT_ADDR_CMD2BYTE 3 diff --git a/arch/mips/include/asm/sibyte/sb1250_syncser.h b/arch/mips/include/asm/sibyte/sb1250_syncser.h index 274e9179d32..b3acc75cf0f 100644 --- a/arch/mips/include/asm/sibyte/sb1250_syncser.h +++ b/arch/mips/include/asm/sibyte/sb1250_syncser.h @@ -1,7 +1,7 @@ /* ********************************************************************* * SB1250 Board Support Package * - * Synchronous Serial Constants File: sb1250_syncser.h + * Synchronous Serial Constants File: sb1250_syncser.h * * This module contains constants and macros useful for * manipulating the SB1250's Synchronous Serial @@ -39,108 +39,108 @@ * Serial Mode Configuration Register */ -#define M_SYNCSER_CRC_MODE _SB_MAKEMASK1(0) -#define M_SYNCSER_MSB_FIRST _SB_MAKEMASK1(1) +#define M_SYNCSER_CRC_MODE _SB_MAKEMASK1(0) +#define M_SYNCSER_MSB_FIRST _SB_MAKEMASK1(1) -#define S_SYNCSER_FLAG_NUM 2 -#define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM) -#define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM) +#define S_SYNCSER_FLAG_NUM 2 +#define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM) +#define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM) -#define M_SYNCSER_FLAG_EN _SB_MAKEMASK1(6) -#define M_SYNCSER_HDLC_EN _SB_MAKEMASK1(7) -#define M_SYNCSER_LOOP_MODE _SB_MAKEMASK1(8) -#define M_SYNCSER_LOOPBACK _SB_MAKEMASK1(9) +#define M_SYNCSER_FLAG_EN _SB_MAKEMASK1(6) +#define M_SYNCSER_HDLC_EN _SB_MAKEMASK1(7) +#define M_SYNCSER_LOOP_MODE _SB_MAKEMASK1(8) +#define M_SYNCSER_LOOPBACK _SB_MAKEMASK1(9) /* * Serial Clock Source and Line Interface Mode Register */ -#define M_SYNCSER_RXCLK_INV _SB_MAKEMASK1(0) -#define M_SYNCSER_RXCLK_EXT _SB_MAKEMASK1(1) +#define M_SYNCSER_RXCLK_INV _SB_MAKEMASK1(0) +#define M_SYNCSER_RXCLK_EXT _SB_MAKEMASK1(1) -#define S_SYNCSER_RXSYNC_DLY 2 -#define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY) -#define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY) +#define S_SYNCSER_RXSYNC_DLY 2 +#define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY) +#define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY) -#define M_SYNCSER_RXSYNC_LOW _SB_MAKEMASK1(4) -#define M_SYNCSER_RXSTRB_LOW _SB_MAKEMASK1(5) +#define M_SYNCSER_RXSYNC_LOW _SB_MAKEMASK1(4) +#define M_SYNCSER_RXSTRB_LOW _SB_MAKEMASK1(5) -#define M_SYNCSER_RXSYNC_EDGE _SB_MAKEMASK1(6) -#define M_SYNCSER_RXSYNC_INT _SB_MAKEMASK1(7) +#define M_SYNCSER_RXSYNC_EDGE _SB_MAKEMASK1(6) +#define M_SYNCSER_RXSYNC_INT _SB_MAKEMASK1(7) -#define M_SYNCSER_TXCLK_INV _SB_MAKEMASK1(8) -#define M_SYNCSER_TXCLK_EXT _SB_MAKEMASK1(9) +#define M_SYNCSER_TXCLK_INV _SB_MAKEMASK1(8) +#define M_SYNCSER_TXCLK_EXT _SB_MAKEMASK1(9) -#define S_SYNCSER_TXSYNC_DLY 10 -#define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY) -#define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY) +#define S_SYNCSER_TXSYNC_DLY 10 +#define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY) +#define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY) -#define M_SYNCSER_TXSYNC_LOW _SB_MAKEMASK1(12) -#define M_SYNCSER_TXSTRB_LOW _SB_MAKEMASK1(13) +#define M_SYNCSER_TXSYNC_LOW _SB_MAKEMASK1(12) +#define M_SYNCSER_TXSTRB_LOW _SB_MAKEMASK1(13) -#define M_SYNCSER_TXSYNC_EDGE _SB_MAKEMASK1(14) -#define M_SYNCSER_TXSYNC_INT _SB_MAKEMASK1(15) +#define M_SYNCSER_TXSYNC_EDGE _SB_MAKEMASK1(14) +#define M_SYNCSER_TXSYNC_INT _SB_MAKEMASK1(15) /* * Serial Command Register */ -#define M_SYNCSER_CMD_RX_EN _SB_MAKEMASK1(0) -#define M_SYNCSER_CMD_TX_EN _SB_MAKEMASK1(1) -#define M_SYNCSER_CMD_RX_RESET _SB_MAKEMASK1(2) -#define M_SYNCSER_CMD_TX_RESET _SB_MAKEMASK1(3) -#define M_SYNCSER_CMD_TX_PAUSE _SB_MAKEMASK1(5) +#define M_SYNCSER_CMD_RX_EN _SB_MAKEMASK1(0) +#define M_SYNCSER_CMD_TX_EN _SB_MAKEMASK1(1) +#define M_SYNCSER_CMD_RX_RESET _SB_MAKEMASK1(2) +#define M_SYNCSER_CMD_TX_RESET _SB_MAKEMASK1(3) +#define M_SYNCSER_CMD_TX_PAUSE _SB_MAKEMASK1(5) /* * Serial DMA Enable Register */ -#define M_SYNCSER_DMA_RX_EN _SB_MAKEMASK1(0) -#define M_SYNCSER_DMA_TX_EN _SB_MAKEMASK1(4) +#define M_SYNCSER_DMA_RX_EN _SB_MAKEMASK1(0) +#define M_SYNCSER_DMA_TX_EN _SB_MAKEMASK1(4) /* * Serial Status Register */ -#define M_SYNCSER_RX_CRCERR _SB_MAKEMASK1(0) -#define M_SYNCSER_RX_ABORT _SB_MAKEMASK1(1) -#define M_SYNCSER_RX_OCTET _SB_MAKEMASK1(2) -#define M_SYNCSER_RX_LONGFRM _SB_MAKEMASK1(3) -#define M_SYNCSER_RX_SHORTFRM _SB_MAKEMASK1(4) -#define M_SYNCSER_RX_OVERRUN _SB_MAKEMASK1(5) -#define M_SYNCSER_RX_SYNC_ERR _SB_MAKEMASK1(6) -#define M_SYNCSER_TX_CRCERR _SB_MAKEMASK1(8) -#define M_SYNCSER_TX_UNDERRUN _SB_MAKEMASK1(9) -#define M_SYNCSER_TX_SYNC_ERR _SB_MAKEMASK1(10) -#define M_SYNCSER_TX_PAUSE_COMPLETE _SB_MAKEMASK1(11) -#define M_SYNCSER_RX_EOP_COUNT _SB_MAKEMASK1(16) -#define M_SYNCSER_RX_EOP_TIMER _SB_MAKEMASK1(17) -#define M_SYNCSER_RX_EOP_SEEN _SB_MAKEMASK1(18) -#define M_SYNCSER_RX_HWM _SB_MAKEMASK1(19) -#define M_SYNCSER_RX_LWM _SB_MAKEMASK1(20) -#define M_SYNCSER_RX_DSCR _SB_MAKEMASK1(21) -#define M_SYNCSER_RX_DERR _SB_MAKEMASK1(22) -#define M_SYNCSER_TX_EOP_COUNT _SB_MAKEMASK1(24) -#define M_SYNCSER_TX_EOP_TIMER _SB_MAKEMASK1(25) -#define M_SYNCSER_TX_EOP_SEEN _SB_MAKEMASK1(26) -#define M_SYNCSER_TX_HWM _SB_MAKEMASK1(27) -#define M_SYNCSER_TX_LWM _SB_MAKEMASK1(28) -#define M_SYNCSER_TX_DSCR _SB_MAKEMASK1(29) -#define M_SYNCSER_TX_DERR _SB_MAKEMASK1(30) -#define M_SYNCSER_TX_DZERO _SB_MAKEMASK1(31) +#define M_SYNCSER_RX_CRCERR _SB_MAKEMASK1(0) +#define M_SYNCSER_RX_ABORT _SB_MAKEMASK1(1) +#define M_SYNCSER_RX_OCTET _SB_MAKEMASK1(2) +#define M_SYNCSER_RX_LONGFRM _SB_MAKEMASK1(3) +#define M_SYNCSER_RX_SHORTFRM _SB_MAKEMASK1(4) +#define M_SYNCSER_RX_OVERRUN _SB_MAKEMASK1(5) +#define M_SYNCSER_RX_SYNC_ERR _SB_MAKEMASK1(6) +#define M_SYNCSER_TX_CRCERR _SB_MAKEMASK1(8) +#define M_SYNCSER_TX_UNDERRUN _SB_MAKEMASK1(9) +#define M_SYNCSER_TX_SYNC_ERR _SB_MAKEMASK1(10) +#define M_SYNCSER_TX_PAUSE_COMPLETE _SB_MAKEMASK1(11) +#define M_SYNCSER_RX_EOP_COUNT _SB_MAKEMASK1(16) +#define M_SYNCSER_RX_EOP_TIMER _SB_MAKEMASK1(17) +#define M_SYNCSER_RX_EOP_SEEN _SB_MAKEMASK1(18) +#define M_SYNCSER_RX_HWM _SB_MAKEMASK1(19) +#define M_SYNCSER_RX_LWM _SB_MAKEMASK1(20) +#define M_SYNCSER_RX_DSCR _SB_MAKEMASK1(21) +#define M_SYNCSER_RX_DERR _SB_MAKEMASK1(22) +#define M_SYNCSER_TX_EOP_COUNT _SB_MAKEMASK1(24) +#define M_SYNCSER_TX_EOP_TIMER _SB_MAKEMASK1(25) +#define M_SYNCSER_TX_EOP_SEEN _SB_MAKEMASK1(26) +#define M_SYNCSER_TX_HWM _SB_MAKEMASK1(27) +#define M_SYNCSER_TX_LWM _SB_MAKEMASK1(28) +#define M_SYNCSER_TX_DSCR _SB_MAKEMASK1(29) +#define M_SYNCSER_TX_DERR _SB_MAKEMASK1(30) +#define M_SYNCSER_TX_DZERO _SB_MAKEMASK1(31) /* * Sequencer Table Entry format */ -#define M_SYNCSER_SEQ_LAST _SB_MAKEMASK1(0) -#define M_SYNCSER_SEQ_BYTE _SB_MAKEMASK1(1) +#define M_SYNCSER_SEQ_LAST _SB_MAKEMASK1(0) +#define M_SYNCSER_SEQ_BYTE _SB_MAKEMASK1(1) -#define S_SYNCSER_SEQ_COUNT 2 -#define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT) -#define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT) +#define S_SYNCSER_SEQ_COUNT 2 +#define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT) +#define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT) -#define M_SYNCSER_SEQ_ENABLE _SB_MAKEMASK1(6) -#define M_SYNCSER_SEQ_STROBE _SB_MAKEMASK1(7) +#define M_SYNCSER_SEQ_ENABLE _SB_MAKEMASK1(6) +#define M_SYNCSER_SEQ_STROBE _SB_MAKEMASK1(7) #endif diff --git a/arch/mips/include/asm/sibyte/sb1250_uart.h b/arch/mips/include/asm/sibyte/sb1250_uart.h index bb99ecac581..a43dc197628 100644 --- a/arch/mips/include/asm/sibyte/sb1250_uart.h +++ b/arch/mips/include/asm/sibyte/sb1250_uart.h @@ -45,33 +45,33 @@ * Register: DUART_MODE_REG_1_B */ -#define S_DUART_BITS_PER_CHAR 0 -#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR) +#define S_DUART_BITS_PER_CHAR 0 +#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR) #define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR) #define K_DUART_BITS_PER_CHAR_RSV0 0 #define K_DUART_BITS_PER_CHAR_RSV1 1 -#define K_DUART_BITS_PER_CHAR_7 2 -#define K_DUART_BITS_PER_CHAR_8 3 +#define K_DUART_BITS_PER_CHAR_7 2 +#define K_DUART_BITS_PER_CHAR_8 3 #define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0) #define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1) -#define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7) -#define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8) +#define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7) +#define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8) #define M_DUART_PARITY_TYPE_EVEN 0x00 -#define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) +#define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) -#define S_DUART_PARITY_MODE 3 -#define M_DUART_PARITY_MODE _SB_MAKEMASK(2, S_DUART_PARITY_MODE) -#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x, S_DUART_PARITY_MODE) +#define S_DUART_PARITY_MODE 3 +#define M_DUART_PARITY_MODE _SB_MAKEMASK(2, S_DUART_PARITY_MODE) +#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x, S_DUART_PARITY_MODE) -#define K_DUART_PARITY_MODE_ADD 0 +#define K_DUART_PARITY_MODE_ADD 0 #define K_DUART_PARITY_MODE_ADD_FIXED 1 #define K_DUART_PARITY_MODE_NONE 2 -#define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD) +#define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD) #define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED) #define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE) @@ -81,7 +81,7 @@ #define M_DUART_RX_IRQ_SEL_RXRDY 0 #define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6) -#define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7) +#define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7) /* * DUART Mode Register #2 (Table 10-4) @@ -89,18 +89,18 @@ * Register: DUART_MODE_REG_2_B */ -#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3, 0) /* ignored */ +#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3, 0) /* ignored */ -#define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) -#define M_DUART_STOP_BIT_LEN_1 0 +#define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) +#define M_DUART_STOP_BIT_LEN_1 0 -#define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4) +#define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4) -#define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ +#define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ #define S_DUART_CHAN_MODE 6 -#define M_DUART_CHAN_MODE _SB_MAKEMASK(2, S_DUART_CHAN_MODE) +#define M_DUART_CHAN_MODE _SB_MAKEMASK(2, S_DUART_CHAN_MODE) #define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x, S_DUART_CHAN_MODE) #define K_DUART_CHAN_MODE_NORMAL 0 @@ -117,34 +117,34 @@ * Register: DUART_CMD_B */ -#define M_DUART_RX_EN _SB_MAKEMASK1(0) -#define M_DUART_RX_DIS _SB_MAKEMASK1(1) -#define M_DUART_TX_EN _SB_MAKEMASK1(2) -#define M_DUART_TX_DIS _SB_MAKEMASK1(3) +#define M_DUART_RX_EN _SB_MAKEMASK1(0) +#define M_DUART_RX_DIS _SB_MAKEMASK1(1) +#define M_DUART_TX_EN _SB_MAKEMASK1(2) +#define M_DUART_TX_DIS _SB_MAKEMASK1(3) #define S_DUART_MISC_CMD 4 -#define M_DUART_MISC_CMD _SB_MAKEMASK(3, S_DUART_MISC_CMD) -#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x, S_DUART_MISC_CMD) - -#define K_DUART_MISC_CMD_NOACTION0 0 -#define K_DUART_MISC_CMD_NOACTION1 1 -#define K_DUART_MISC_CMD_RESET_RX 2 -#define K_DUART_MISC_CMD_RESET_TX 3 -#define K_DUART_MISC_CMD_NOACTION4 4 +#define M_DUART_MISC_CMD _SB_MAKEMASK(3, S_DUART_MISC_CMD) +#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x, S_DUART_MISC_CMD) + +#define K_DUART_MISC_CMD_NOACTION0 0 +#define K_DUART_MISC_CMD_NOACTION1 1 +#define K_DUART_MISC_CMD_RESET_RX 2 +#define K_DUART_MISC_CMD_RESET_TX 3 +#define K_DUART_MISC_CMD_NOACTION4 4 #define K_DUART_MISC_CMD_RESET_BREAK_INT 5 -#define K_DUART_MISC_CMD_START_BREAK 6 -#define K_DUART_MISC_CMD_STOP_BREAK 7 - -#define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0) -#define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1) -#define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX) -#define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX) -#define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4) +#define K_DUART_MISC_CMD_START_BREAK 6 +#define K_DUART_MISC_CMD_STOP_BREAK 7 + +#define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0) +#define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1) +#define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX) +#define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX) +#define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4) #define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT) -#define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK) -#define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK) +#define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK) +#define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK) -#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) +#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) /* * DUART Status Register (Table 10-6) @@ -153,14 +153,14 @@ * READ-ONLY */ -#define M_DUART_RX_RDY _SB_MAKEMASK1(0) -#define M_DUART_RX_FFUL _SB_MAKEMASK1(1) -#define M_DUART_TX_RDY _SB_MAKEMASK1(2) -#define M_DUART_TX_EMT _SB_MAKEMASK1(3) -#define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4) -#define M_DUART_PARITY_ERR _SB_MAKEMASK1(5) -#define M_DUART_FRM_ERR _SB_MAKEMASK1(6) -#define M_DUART_RCVD_BRK _SB_MAKEMASK1(7) +#define M_DUART_RX_RDY _SB_MAKEMASK1(0) +#define M_DUART_RX_FFUL _SB_MAKEMASK1(1) +#define M_DUART_TX_RDY _SB_MAKEMASK1(2) +#define M_DUART_TX_EMT _SB_MAKEMASK1(3) +#define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4) +#define M_DUART_PARITY_ERR _SB_MAKEMASK1(5) +#define M_DUART_FRM_ERR _SB_MAKEMASK1(6) +#define M_DUART_RCVD_BRK _SB_MAKEMASK1(7) /* * DUART Baud Rate Register (Table 10-7) @@ -168,8 +168,8 @@ * Register: DUART_CLK_SEL_B */ -#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12, 0) -#define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) +#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12, 0) +#define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) /* * DUART Data Registers (Table 10-8 and 10-9) @@ -179,33 +179,33 @@ * Register: DUART_TX_HOLD_B */ -#define M_DUART_RX_DATA _SB_MAKEMASK(8, 0) -#define M_DUART_TX_DATA _SB_MAKEMASK(8, 0) +#define M_DUART_RX_DATA _SB_MAKEMASK(8, 0) +#define M_DUART_TX_DATA _SB_MAKEMASK(8, 0) /* * DUART Input Port Register (Table 10-10) * Register: DUART_IN_PORT */ -#define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0) -#define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1) -#define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2) -#define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3) -#define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4) -#define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5) -#define M_DUART_RIN0_PIN _SB_MAKEMASK1(6) -#define M_DUART_RIN1_PIN _SB_MAKEMASK1(7) +#define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0) +#define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1) +#define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2) +#define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3) +#define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4) +#define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5) +#define M_DUART_RIN0_PIN _SB_MAKEMASK1(6) +#define M_DUART_RIN1_PIN _SB_MAKEMASK1(7) /* * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13) * Register: DUART_INPORT_CHNG */ -#define S_DUART_IN_PIN_VAL 0 -#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL) +#define S_DUART_IN_PIN_VAL 0 +#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL) -#define S_DUART_IN_PIN_CHNG 4 -#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG) +#define S_DUART_IN_PIN_CHNG 4 +#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG) /* @@ -213,46 +213,46 @@ * Register: DUART_OPCR */ -#define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */ -#define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) -#define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ -#define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) -#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4, 4) /* must be zero */ +#define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */ +#define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) +#define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ +#define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) +#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4, 4) /* must be zero */ /* * DUART Aux Control Register (Table 10-15) * Register: DUART_AUX_CTRL */ -#define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0) -#define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) -#define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) -#define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) -#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4, 4) +#define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0) +#define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) +#define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) +#define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) +#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4, 4) -#define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) -#define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) +#define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) +#define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) /* * DUART Interrupt Status Register (Table 10-16) * Register: DUART_ISR */ -#define M_DUART_ISR_TX_A _SB_MAKEMASK1(0) +#define M_DUART_ISR_TX_A _SB_MAKEMASK1(0) -#define S_DUART_ISR_RX_A 1 -#define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A) -#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x, S_DUART_ISR_RX_A) -#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A) +#define S_DUART_ISR_RX_A 1 +#define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A) +#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x, S_DUART_ISR_RX_A) +#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A) -#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) -#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) +#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) +#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) #define M_DUART_ISR_ALL_A _SB_MAKEMASK(4, 0) -#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) -#define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) -#define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) -#define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) +#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) +#define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) +#define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) +#define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) #define M_DUART_ISR_ALL_B _SB_MAKEMASK(4, 4) /* @@ -262,29 +262,29 @@ * Register: DUART_ISR_B */ -#define M_DUART_ISR_TX _SB_MAKEMASK1(0) -#define M_DUART_ISR_RX _SB_MAKEMASK1(1) -#define M_DUART_ISR_BRK _SB_MAKEMASK1(2) -#define M_DUART_ISR_IN _SB_MAKEMASK1(3) +#define M_DUART_ISR_TX _SB_MAKEMASK1(0) +#define M_DUART_ISR_RX _SB_MAKEMASK1(1) +#define M_DUART_ISR_BRK _SB_MAKEMASK1(2) +#define M_DUART_ISR_IN _SB_MAKEMASK1(3) #define M_DUART_ISR_ALL _SB_MAKEMASK(4, 0) -#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4, 4) +#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4, 4) /* * DUART Interrupt Mask Register (Table 10-19) * Register: DUART_IMR */ -#define M_DUART_IMR_TX_A _SB_MAKEMASK1(0) -#define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) -#define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) -#define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) +#define M_DUART_IMR_TX_A _SB_MAKEMASK1(0) +#define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) +#define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) +#define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) #define M_DUART_IMR_ALL_A _SB_MAKEMASK(4, 0) -#define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) -#define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) -#define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) -#define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) -#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4, 4) +#define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) +#define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) +#define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) +#define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) +#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4, 4) /* * DUART Channel A Interrupt Mask Register (Table 10-20) @@ -293,12 +293,12 @@ * Register: DUART_IMR_B */ -#define M_DUART_IMR_TX _SB_MAKEMASK1(0) -#define M_DUART_IMR_RX _SB_MAKEMASK1(1) -#define M_DUART_IMR_BRK _SB_MAKEMASK1(2) -#define M_DUART_IMR_IN _SB_MAKEMASK1(3) +#define M_DUART_IMR_TX _SB_MAKEMASK1(0) +#define M_DUART_IMR_RX _SB_MAKEMASK1(1) +#define M_DUART_IMR_BRK _SB_MAKEMASK1(2) +#define M_DUART_IMR_IN _SB_MAKEMASK1(3) #define M_DUART_IMR_ALL _SB_MAKEMASK(4, 0) -#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4, 4) +#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4, 4) /* @@ -306,33 +306,33 @@ * Register: DUART_SET_OPR */ -#define M_DUART_SET_OPR0 _SB_MAKEMASK1(0) -#define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) -#define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) -#define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) -#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4, 4) +#define M_DUART_SET_OPR0 _SB_MAKEMASK1(0) +#define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) +#define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) +#define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) +#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4, 4) /* * DUART Output Port Clear Register (Table 10-23) * Register: DUART_CLEAR_OPR */ -#define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0) -#define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) -#define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) -#define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) -#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4, 4) +#define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0) +#define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) +#define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) +#define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) +#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4, 4) /* * DUART Output Port RTS Register (Table 10-24) * Register: DUART_OUT_PORT */ -#define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0) -#define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) -#define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) -#define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) -#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4, 4) +#define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0) +#define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) +#define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) +#define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) +#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4, 4) #define M_DUART_OUT_PIN_SET(chan) \ (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) @@ -344,15 +344,15 @@ * Full Interrupt Control Register */ -#define S_DUART_SIG_FULL _SB_MAKE64(0) -#define M_DUART_SIG_FULL _SB_MAKEMASK(4, S_DUART_SIG_FULL) -#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x, S_DUART_SIG_FULL) -#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL) +#define S_DUART_SIG_FULL _SB_MAKE64(0) +#define M_DUART_SIG_FULL _SB_MAKEMASK(4, S_DUART_SIG_FULL) +#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x, S_DUART_SIG_FULL) +#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL) -#define S_DUART_INT_TIME _SB_MAKE64(4) -#define M_DUART_INT_TIME _SB_MAKEMASK(4, S_DUART_INT_TIME) -#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x, S_DUART_INT_TIME) -#define G_DUART_INT_TIME(x) _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME) +#define S_DUART_INT_TIME _SB_MAKE64(4) +#define M_DUART_INT_TIME _SB_MAKEMASK(4, S_DUART_INT_TIME) +#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x, S_DUART_INT_TIME) +#define G_DUART_INT_TIME(x) _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME) #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ diff --git a/arch/mips/include/asm/sibyte/sentosa.h b/arch/mips/include/asm/sibyte/sentosa.h index 64c47874f32..0351a46eebb 100644 --- a/arch/mips/include/asm/sibyte/sentosa.h +++ b/arch/mips/include/asm/sibyte/sentosa.h @@ -30,11 +30,11 @@ /* Generic bus chip selects */ #ifdef CONFIG_SIBYTE_RHONE -#define LEDS_CS 6 -#define LEDS_PHYS 0x1d0a0000 +#define LEDS_CS 6 +#define LEDS_PHYS 0x1d0a0000 #endif /* GPIOs */ -#define K_GPIO_DBG_LED 0 +#define K_GPIO_DBG_LED 0 #endif /* __ASM_SIBYTE_SENTOSA_H */ diff --git a/arch/mips/include/asm/sibyte/swarm.h b/arch/mips/include/asm/sibyte/swarm.h index 114d9d29ca9..187cfb1f67c 100644 --- a/arch/mips/include/asm/sibyte/swarm.h +++ b/arch/mips/include/asm/sibyte/swarm.h @@ -24,41 +24,41 @@ #ifdef CONFIG_SIBYTE_SWARM #define SIBYTE_BOARD_NAME "BCM91250A (SWARM)" #define SIBYTE_HAVE_PCMCIA 1 -#define SIBYTE_HAVE_IDE 1 +#define SIBYTE_HAVE_IDE 1 #endif #ifdef CONFIG_SIBYTE_LITTLESUR #define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)" #define SIBYTE_HAVE_PCMCIA 0 -#define SIBYTE_HAVE_IDE 1 +#define SIBYTE_HAVE_IDE 1 #define SIBYTE_DEFAULT_CONSOLE "cfe0" #endif #ifdef CONFIG_SIBYTE_CRHONE #define SIBYTE_BOARD_NAME "BCM91125C (CRhone)" #define SIBYTE_HAVE_PCMCIA 0 -#define SIBYTE_HAVE_IDE 0 +#define SIBYTE_HAVE_IDE 0 #endif #ifdef CONFIG_SIBYTE_CRHINE #define SIBYTE_BOARD_NAME "BCM91120C (CRhine)" #define SIBYTE_HAVE_PCMCIA 0 -#define SIBYTE_HAVE_IDE 0 +#define SIBYTE_HAVE_IDE 0 #endif /* Generic bus chip selects */ -#define LEDS_CS 3 -#define LEDS_PHYS 0x100a0000 +#define LEDS_CS 3 +#define LEDS_PHYS 0x100a0000 #ifdef SIBYTE_HAVE_IDE -#define IDE_CS 4 -#define IDE_PHYS 0x100b0000 -#define K_GPIO_GB_IDE 4 -#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) +#define IDE_CS 4 +#define IDE_PHYS 0x100b0000 +#define K_GPIO_GB_IDE 4 +#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) #endif #ifdef SIBYTE_HAVE_PCMCIA -#define PCMCIA_CS 6 -#define PCMCIA_PHYS 0x11000000 +#define PCMCIA_CS 6 +#define PCMCIA_PHYS 0x11000000 #define K_GPIO_PC_READY 9 -#define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY) +#define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY) #endif #endif /* __ASM_SIBYTE_SWARM_H */ diff --git a/arch/mips/include/asm/signal.h b/arch/mips/include/asm/signal.h index cf4a08062d1..8efe5a9e2c3 100644 --- a/arch/mips/include/asm/signal.h +++ b/arch/mips/include/asm/signal.h @@ -21,4 +21,6 @@ #include <asm/sigcontext.h> #include <asm/siginfo.h> +#define __ARCH_HAS_IRIX_SIGACTION + #endif /* _ASM_SIGNAL_H */ diff --git a/arch/mips/include/asm/sim.h b/arch/mips/include/asm/sim.h index 0cd719fabb5..91831800c48 100644 --- a/arch/mips/include/asm/sim.h +++ b/arch/mips/include/asm/sim.h @@ -20,10 +20,10 @@ #define save_static_function(symbol) \ __asm__( \ ".text\n\t" \ - ".globl\t" #symbol "\n\t" \ + ".globl\t__" #symbol "\n\t" \ ".align\t2\n\t" \ - ".type\t" #symbol ", @function\n\t" \ - ".ent\t" #symbol ", 0\n" \ + ".type\t__" #symbol ", @function\n\t" \ + ".ent\t__" #symbol ", 0\n__" \ #symbol":\n\t" \ ".frame\t$29, 0, $31\n\t" \ "sw\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t" \ @@ -35,9 +35,9 @@ __asm__( \ "sw\t$22,"__str(PT_R22)"($29)\n\t" \ "sw\t$23,"__str(PT_R23)"($29)\n\t" \ "sw\t$30,"__str(PT_R30)"($29)\n\t" \ - "j\t_" #symbol "\n\t" \ - ".end\t" #symbol "\n\t" \ - ".size\t" #symbol",. - " #symbol) + "j\t" #symbol "\n\t" \ + ".end\t__" #symbol "\n\t" \ + ".size\t__" #symbol",. - __" #symbol) #define nabi_no_regargs @@ -48,10 +48,10 @@ __asm__( \ #define save_static_function(symbol) \ __asm__( \ ".text\n\t" \ - ".globl\t" #symbol "\n\t" \ + ".globl\t__" #symbol "\n\t" \ ".align\t2\n\t" \ - ".type\t" #symbol ", @function\n\t" \ - ".ent\t" #symbol ", 0\n" \ + ".type\t__" #symbol ", @function\n\t" \ + ".ent\t__" #symbol ", 0\n__" \ #symbol":\n\t" \ ".frame\t$29, 0, $31\n\t" \ "sd\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t" \ @@ -63,9 +63,9 @@ __asm__( \ "sd\t$22,"__str(PT_R22)"($29)\n\t" \ "sd\t$23,"__str(PT_R23)"($29)\n\t" \ "sd\t$30,"__str(PT_R30)"($29)\n\t" \ - "j\t_" #symbol "\n\t" \ - ".end\t" #symbol "\n\t" \ - ".size\t" #symbol",. - " #symbol) + "j\t" #symbol "\n\t" \ + ".end\t__" #symbol "\n\t" \ + ".size\t__" #symbol",. - __" #symbol) #define nabi_no_regargs \ unsigned long __dummy0, \ diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cps.h new file mode 100644 index 00000000000..a06a08a9afc --- /dev/null +++ b/arch/mips/include/asm/smp-cps.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton <paul.burton@imgtec.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MIPS_ASM_SMP_CPS_H__ +#define __MIPS_ASM_SMP_CPS_H__ + +#ifndef __ASSEMBLY__ + +struct vpe_boot_config { + unsigned long pc; + unsigned long sp; + unsigned long gp; +}; + +struct core_boot_config { + atomic_t vpe_mask; + struct vpe_boot_config *vpe_config; +}; + +extern struct core_boot_config *mips_cps_core_bootcfg; + +extern void mips_cps_core_entry(void); +extern void mips_cps_core_init(void); + +extern struct vpe_boot_config *mips_cps_boot_vpes(void); + +extern bool mips_cps_smp_in_use(void); + +extern void mips_cps_pm_save(void); +extern void mips_cps_pm_restore(void); + +#else /* __ASSEMBLY__ */ + +.extern mips_cps_bootcfg; + +#endif /* __ASSEMBLY__ */ +#endif /* __MIPS_ASM_SMP_CPS_H__ */ diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h index ef2a8041e78..6ba1fb8b11e 100644 --- a/arch/mips/include/asm/smp-ops.h +++ b/arch/mips/include/asm/smp-ops.h @@ -13,6 +13,8 @@ #include <linux/errno.h> +#include <asm/mips-cm.h> + #ifdef CONFIG_SMP #include <linux/cpumask.h> @@ -24,7 +26,6 @@ struct plat_smp_ops { void (*send_ipi_mask)(const struct cpumask *mask, unsigned int action); void (*init_secondary)(void); void (*smp_finish)(void); - void (*cpus_done)(void); void (*boot_secondary)(int cpu, struct task_struct *idle); void (*smp_setup)(void); void (*prepare_cpus)(unsigned int max_cpus); @@ -43,6 +44,9 @@ static inline void plat_smp_setup(void) mp_ops->smp_setup(); } +extern void gic_send_ipi_single(int cpu, unsigned int action); +extern void gic_send_ipi_mask(const struct cpumask *mask, unsigned int action); + #else /* !CONFIG_SMP */ struct plat_smp_ops; @@ -76,6 +80,9 @@ static inline int register_cmp_smp_ops(void) #ifdef CONFIG_MIPS_CMP extern struct plat_smp_ops cmp_smp_ops; + if (!mips_cm_present()) + return -ENODEV; + register_smp_ops(&cmp_smp_ops); return 0; @@ -97,4 +104,13 @@ static inline int register_vsmp_smp_ops(void) #endif } +#ifdef CONFIG_MIPS_CPS +extern int register_cps_smp_ops(void); +#else +static inline int register_cps_smp_ops(void) +{ + return -ENODEV; +} +#endif + #endif /* __ASM_SMP_OPS_H */ diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h index f33b5fd6972..b037334fca2 100644 --- a/arch/mips/include/asm/smp.h +++ b/arch/mips/include/asm/smp.h @@ -26,7 +26,7 @@ extern cpumask_t cpu_sibling_map[]; #define raw_smp_processor_id() (current_thread_info()->cpu) /* Map from cpu id to sequential logical cpu number. This will only - not be idempotent when cpus failed to come on-line. */ + not be idempotent when cpus failed to come on-line. */ extern int __cpu_number_map[NR_CPUS]; #define cpu_number_map(cpu) __cpu_number_map[cpu] @@ -36,15 +36,19 @@ extern int __cpu_logical_map[NR_CPUS]; #define NO_PROC_ID (-1) -#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */ +#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */ #define SMP_CALL_FUNCTION 0x2 /* Octeon - Tell another core to flush its icache */ #define SMP_ICACHE_FLUSH 0x4 /* Used by kexec crashdump to save all cpu's state */ #define SMP_DUMP 0x8 +#define SMP_ASK_C0COUNT 0x10 extern volatile cpumask_t cpu_callin_map; +/* Mask of CPUs which are currently definitely operating coherently */ +extern cpumask_t cpu_coherent_mask; + extern void asmlinkage smp_bootstrap(void); /* @@ -62,14 +66,14 @@ static inline void smp_send_reschedule(int cpu) #ifdef CONFIG_HOTPLUG_CPU static inline int __cpu_disable(void) { - extern struct plat_smp_ops *mp_ops; /* private */ + extern struct plat_smp_ops *mp_ops; /* private */ return mp_ops->cpu_disable(); } static inline void __cpu_die(unsigned int cpu) { - extern struct plat_smp_ops *mp_ops; /* private */ + extern struct plat_smp_ops *mp_ops; /* private */ mp_ops->cpu_die(cpu); } @@ -81,14 +85,14 @@ extern asmlinkage void smp_call_function_interrupt(void); static inline void arch_send_call_function_single_ipi(int cpu) { - extern struct plat_smp_ops *mp_ops; /* private */ + extern struct plat_smp_ops *mp_ops; /* private */ mp_ops->send_ipi_mask(&cpumask_of_cpu(cpu), SMP_CALL_FUNCTION); } static inline void arch_send_call_function_ipi_mask(const struct cpumask *mask) { - extern struct plat_smp_ops *mp_ops; /* private */ + extern struct plat_smp_ops *mp_ops; /* private */ mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION); } diff --git a/arch/mips/include/asm/smtc.h b/arch/mips/include/asm/smtc.h deleted file mode 100644 index 8935426a56a..00000000000 --- a/arch/mips/include/asm/smtc.h +++ /dev/null @@ -1,78 +0,0 @@ -#ifndef _ASM_SMTC_MT_H -#define _ASM_SMTC_MT_H - -/* - * Definitions for SMTC multitasking on MIPS MT cores - */ - -#include <asm/mips_mt.h> -#include <asm/smtc_ipi.h> - -/* - * System-wide SMTC status information - */ - -extern unsigned int smtc_status; - -#define SMTC_TLB_SHARED 0x00000001 -#define SMTC_MTC_ACTIVE 0x00000002 - -/* - * TLB/ASID Management information - */ - -#define MAX_SMTC_TLBS 2 -#define MAX_SMTC_ASIDS 256 -#if NR_CPUS <= 8 -typedef char asiduse; -#else -#if NR_CPUS <= 16 -typedef short asiduse; -#else -typedef long asiduse; -#endif -#endif - -/* - * VPE Management information - */ - -#define MAX_SMTC_VPES MAX_SMTC_TLBS /* FIXME: May not always be true. */ - -extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; - -struct mm_struct; -struct task_struct; - -void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu); -void self_ipi(struct smtc_ipi *); -void smtc_flush_tlb_asid(unsigned long asid); -extern int smtc_build_cpu_map(int startslot); -extern void smtc_prepare_cpus(int cpus); -extern void smtc_smp_finish(void); -extern void smtc_boot_secondary(int cpu, struct task_struct *t); -extern void smtc_cpus_done(void); -extern void smtc_init_secondary(void); - - -/* - * Sharing the TLB between multiple VPEs means that the - * "random" index selection function is not allowed to - * select the current value of the Index register. To - * avoid additional TLB pressure, the Index registers - * are "parked" with an non-Valid value. - */ - -#define PARKED_INDEX ((unsigned int)0x80000000) - -/* - * Define low-level interrupt mask for IPIs, if necessary. - * By default, use SW interrupt 1, which requires no external - * hardware support, but which works only for single-core - * MIPS MT systems. - */ -#ifndef MIPS_CPU_IPI_IRQ -#define MIPS_CPU_IPI_IRQ 1 -#endif - -#endif /* _ASM_SMTC_MT_H */ diff --git a/arch/mips/include/asm/smtc_ipi.h b/arch/mips/include/asm/smtc_ipi.h deleted file mode 100644 index 15278dbd7e7..00000000000 --- a/arch/mips/include/asm/smtc_ipi.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Definitions used in MIPS MT SMTC "Interprocessor Interrupt" code. - */ -#ifndef __ASM_SMTC_IPI_H -#define __ASM_SMTC_IPI_H - -#include <linux/spinlock.h> - -//#define SMTC_IPI_DEBUG - -#ifdef SMTC_IPI_DEBUG -#include <asm/mipsregs.h> -#include <asm/mipsmtregs.h> -#endif /* SMTC_IPI_DEBUG */ - -/* - * An IPI "message" - */ - -struct smtc_ipi { - struct smtc_ipi *flink; - int type; - void *arg; - int dest; -#ifdef SMTC_IPI_DEBUG - int sender; - long stamp; -#endif /* SMTC_IPI_DEBUG */ -}; - -/* - * Defined IPI Types - */ - -#define LINUX_SMP_IPI 1 -#define SMTC_CLOCK_TICK 2 -#define IRQ_AFFINITY_IPI 3 - -/* - * A queue of IPI messages - */ - -struct smtc_ipi_q { - struct smtc_ipi *head; - spinlock_t lock; - struct smtc_ipi *tail; - int depth; - int resched_flag; /* reschedule already queued */ -}; - -static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p) -{ - unsigned long flags; - - spin_lock_irqsave(&q->lock, flags); - if (q->head == NULL) - q->head = q->tail = p; - else - q->tail->flink = p; - p->flink = NULL; - q->tail = p; - q->depth++; -#ifdef SMTC_IPI_DEBUG - p->sender = read_c0_tcbind(); - p->stamp = read_c0_count(); -#endif /* SMTC_IPI_DEBUG */ - spin_unlock_irqrestore(&q->lock, flags); -} - -static inline struct smtc_ipi *__smtc_ipi_dq(struct smtc_ipi_q *q) -{ - struct smtc_ipi *p; - - if (q->head == NULL) - p = NULL; - else { - p = q->head; - q->head = q->head->flink; - q->depth--; - /* Arguably unnecessary, but leaves queue cleaner */ - if (q->head == NULL) - q->tail = NULL; - } - - return p; -} - -static inline struct smtc_ipi *smtc_ipi_dq(struct smtc_ipi_q *q) -{ - unsigned long flags; - struct smtc_ipi *p; - - spin_lock_irqsave(&q->lock, flags); - p = __smtc_ipi_dq(q); - spin_unlock_irqrestore(&q->lock, flags); - - return p; -} - -static inline void smtc_ipi_req(struct smtc_ipi_q *q, struct smtc_ipi *p) -{ - unsigned long flags; - - spin_lock_irqsave(&q->lock, flags); - if (q->head == NULL) { - q->head = q->tail = p; - p->flink = NULL; - } else { - p->flink = q->head; - q->head = p; - } - q->depth++; - spin_unlock_irqrestore(&q->lock, flags); -} - -static inline int smtc_ipi_qdepth(struct smtc_ipi_q *q) -{ - unsigned long flags; - int retval; - - spin_lock_irqsave(&q->lock, flags); - retval = q->depth; - spin_unlock_irqrestore(&q->lock, flags); - return retval; -} - -extern void smtc_send_ipi(int cpu, int type, unsigned int action); - -#endif /* __ASM_SMTC_IPI_H */ diff --git a/arch/mips/include/asm/smtc_proc.h b/arch/mips/include/asm/smtc_proc.h deleted file mode 100644 index 25da651f1f5..00000000000 --- a/arch/mips/include/asm/smtc_proc.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Definitions for SMTC /proc entries - * Copyright(C) 2005 MIPS Technologies Inc. - */ -#ifndef __ASM_SMTC_PROC_H -#define __ASM_SMTC_PROC_H - -/* - * per-"CPU" statistics - */ - -struct smtc_cpu_proc { - unsigned long timerints; - unsigned long selfipis; -}; - -extern struct smtc_cpu_proc smtc_cpu_stats[NR_CPUS]; - -/* Count of number of recoveries of "stolen" FPU access rights on 34K */ - -extern atomic_t smtc_fpu_recoveries; - -#endif /* __ASM_SMTC_PROC_H */ diff --git a/arch/mips/include/asm/sn/addrs.h b/arch/mips/include/asm/sn/addrs.h index 2367b56dcde..66814f8ba8e 100644 --- a/arch/mips/include/asm/sn/addrs.h +++ b/arch/mips/include/asm/sn/addrs.h @@ -88,8 +88,8 @@ #define SWIN_SIZE_BITS 24 #define SWIN_SIZE (UINT64_CAST 1 << 24) -#define SWIN_SIZEMASK (SWIN_SIZE - 1) -#define SWIN_WIDGET_MASK 0xF +#define SWIN_SIZEMASK (SWIN_SIZE - 1) +#define SWIN_WIDGET_MASK 0xF /* * Convert smallwindow address to xtalk address. @@ -97,8 +97,8 @@ * 'addr' can be physical or virtual address, but will be converted * to Xtalk address in the range 0 -> SWINZ_SIZEMASK */ -#define SWIN_WIDGETADDR(addr) ((addr) & SWIN_SIZEMASK) -#define SWIN_WIDGETNUM(addr) (((addr) >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK) +#define SWIN_WIDGETADDR(addr) ((addr) & SWIN_SIZEMASK) +#define SWIN_WIDGETNUM(addr) (((addr) >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK) /* * Verify if addr belongs to small window address on node with "nasid" * @@ -108,7 +108,7 @@ * * */ -#define NODE_SWIN_ADDR(nasid, addr) \ +#define NODE_SWIN_ADDR(nasid, addr) \ (((addr) >= NODE_SWIN_BASE(nasid, 0)) && \ ((addr) < (NODE_SWIN_BASE(nasid, HUB_NUM_WIDGET) + SWIN_SIZE)\ )) @@ -150,7 +150,7 @@ #endif -#define HUB_REGISTER_WIDGET 1 +#define HUB_REGISTER_WIDGET 1 #define IALIAS_BASE NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET) #define IALIAS_SIZE 0x800000 /* 8 Megabytes */ #define IS_IALIAS(_a) (((_a) >= IALIAS_BASE) && \ @@ -174,16 +174,16 @@ * WARNING: They won't work in assembler. * * BDDIR_ENTRY_LO returns the address of the low double-word of the dir - * entry corresponding to a physical (Cac or Uncac) address. + * entry corresponding to a physical (Cac or Uncac) address. * BDDIR_ENTRY_HI returns the address of the high double-word of the entry. * BDPRT_ENTRY returns the address of the double-word protection entry - * corresponding to the page containing the physical address. + * corresponding to the page containing the physical address. * BDPRT_ENTRY_S Stores the value into the protection entry. * BDPRT_ENTRY_L Load the value from the protection entry. * BDECC_ENTRY returns the address of the ECC byte corresponding to a - * double-word at a specified physical address. + * double-word at a specified physical address. * BDECC_ENTRY_H returns the address of the two ECC bytes corresponding to a - * quad-word at a specified physical address. + * quad-word at a specified physical address. */ #define NODE_BDOOR_BASE(_n) (NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2)) @@ -226,11 +226,11 @@ #define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x200) != 0) #define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x200) == 0) -#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ +#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2 | \ (UINT64_CAST(_ba) & 0x1f << 4) << 3) -#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ +#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2) #define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ @@ -251,23 +251,23 @@ /* * WARNING: * When certain Hub chip workaround are defined, it's not sufficient - * to dereference the *_HUB_ADDR() macros. You should instead use + * to dereference the *_HUB_ADDR() macros. You should instead use * HUB_L() and HUB_S() if you must deal with pointers to hub registers. * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S(). * They're always safe. */ #define LOCAL_HUB_ADDR(_x) (HUBREG_CAST (IALIAS_BASE + (_x))) -#define REMOTE_HUB_ADDR(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \ +#define REMOTE_HUB_ADDR(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \ 0x800000 + (_x))) #ifdef CONFIG_SGI_IP27 -#define REMOTE_HUB_PI_ADDR(_n, _sn, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \ +#define REMOTE_HUB_PI_ADDR(_n, _sn, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \ 0x800000 + (_x))) #endif /* CONFIG_SGI_IP27 */ #ifndef __ASSEMBLY__ #define HUB_L(_a) *(_a) -#define HUB_S(_a, _d) *(_a) = (_d) +#define HUB_S(_a, _d) *(_a) = (_d) #define LOCAL_HUB_L(_r) HUB_L(LOCAL_HUB_ADDR(_r)) #define LOCAL_HUB_S(_r, _d) HUB_S(LOCAL_HUB_ADDR(_r), (_d)) @@ -330,14 +330,14 @@ #define KLI_LAUNCH 0 /* Dir. entries */ #define KLI_KLCONFIG 1 -#define KLI_NMI 2 +#define KLI_NMI 2 #define KLI_GDA 3 #define KLI_FREEMEM 4 -#define KLI_SYMMON_STK 5 +#define KLI_SYMMON_STK 5 #define KLI_PI_ERROR 6 #define KLI_KERN_VARS 7 -#define KLI_KERN_XP 8 -#define KLI_KERN_PARTID 9 +#define KLI_KERN_XP 8 +#define KLI_KERN_PARTID 9 #ifndef __ASSEMBLY__ @@ -350,8 +350,8 @@ #define KLD_SYMMON_STK(nasid) (KLD_BASE(nasid) + KLI_SYMMON_STK) #define KLD_FREEMEM(nasid) (KLD_BASE(nasid) + KLI_FREEMEM) #define KLD_KERN_VARS(nasid) (KLD_BASE(nasid) + KLI_KERN_VARS) -#define KLD_KERN_XP(nasid) (KLD_BASE(nasid) + KLI_KERN_XP) -#define KLD_KERN_PARTID(nasid) (KLD_BASE(nasid) + KLI_KERN_PARTID) +#define KLD_KERN_XP(nasid) (KLD_BASE(nasid) + KLI_KERN_XP) +#define KLD_KERN_PARTID(nasid) (KLD_BASE(nasid) + KLI_KERN_PARTID) #define LAUNCH_OFFSET(nasid, slice) \ (KLD_LAUNCH(nasid)->offset + \ @@ -365,7 +365,7 @@ KLD_NMI(nasid)->stride * (slice)) #define NMI_ADDR(nasid, slice) \ TO_NODE_UNCAC((nasid), SN_NMI_OFFSET(nasid, slice)) -#define NMI_SIZE(nasid) KLD_NMI(nasid)->size +#define NMI_SIZE(nasid) KLD_NMI(nasid)->size #define KLCONFIG_OFFSET(nasid) KLD_KLCONFIG(nasid)->offset #define KLCONFIG_ADDR(nasid) \ @@ -390,8 +390,8 @@ /* loading symmon 4k below UNIX. the arcs loader needs the topaddr for a * relocatable program */ -#define UNIX_DEBUG_LOADADDR 0x300000 -#define SYMMON_LOADADDR(nasid) \ +#define UNIX_DEBUG_LOADADDR 0x300000 +#define SYMMON_LOADADDR(nasid) \ TO_NODE(nasid, PHYS_TO_K0(UNIX_DEBUG_LOADADDR - 0x1000)) #define FREEMEM_OFFSET(nasid) KLD_FREEMEM(nasid)->offset @@ -420,8 +420,8 @@ #define KERN_VARS_ADDR(nasid) KLD_KERN_VARS(nasid)->pointer #define KERN_VARS_SIZE(nasid) KLD_KERN_VARS(nasid)->size -#define KERN_XP_ADDR(nasid) KLD_KERN_XP(nasid)->pointer -#define KERN_XP_SIZE(nasid) KLD_KERN_XP(nasid)->size +#define KERN_XP_ADDR(nasid) KLD_KERN_XP(nasid)->pointer +#define KERN_XP_SIZE(nasid) KLD_KERN_XP(nasid)->size #define GPDA_ADDR(nasid) TO_NODE_CAC(nasid, GPDA_OFFSET) diff --git a/arch/mips/include/asm/sn/agent.h b/arch/mips/include/asm/sn/agent.h index dc81114d474..e33d0929301 100644 --- a/arch/mips/include/asm/sn/agent.h +++ b/arch/mips/include/asm/sn/agent.h @@ -25,21 +25,21 @@ */ #if defined(CONFIG_SGI_IP27) -#define HUB_NIC_ADDR(_cpuid) \ - REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cpu_to_node(_cpuid)), \ +#define HUB_NIC_ADDR(_cpuid) \ + REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cpu_to_node(_cpuid)), \ MD_MLAN_CTL) #endif -#define SET_HUB_NIC(_my_cpuid, _val) \ +#define SET_HUB_NIC(_my_cpuid, _val) \ (HUB_S(HUB_NIC_ADDR(_my_cpuid), (_val))) -#define SET_MY_HUB_NIC(_v) \ +#define SET_MY_HUB_NIC(_v) \ SET_HUB_NIC(cpuid(), (_v)) -#define GET_HUB_NIC(_my_cpuid) \ +#define GET_HUB_NIC(_my_cpuid) \ (HUB_L(HUB_NIC_ADDR(_my_cpuid))) -#define GET_MY_HUB_NIC() \ +#define GET_MY_HUB_NIC() \ GET_HUB_NIC(cpuid()) #endif /* _ASM_SGI_SN_AGENT_H */ diff --git a/arch/mips/include/asm/sn/arch.h b/arch/mips/include/asm/sn/arch.h index bd75945e10f..471e6870d87 100644 --- a/arch/mips/include/asm/sn/arch.h +++ b/arch/mips/include/asm/sn/arch.h @@ -28,14 +28,14 @@ typedef u64 hubreg_t; #define INVALID_CNODEID (cnodeid_t)-1 #define INVALID_PNODEID (pnodeid_t)-1 #define INVALID_MODULE (moduleid_t)-1 -#define INVALID_PARTID (partid_t)-1 +#define INVALID_PARTID (partid_t)-1 extern nasid_t get_nasid(void); extern cnodeid_t get_cpu_cnode(cpuid_t); extern int get_cpu_slice(cpuid_t); /* - * NO ONE should access these arrays directly. The only reason we refer to + * NO ONE should access these arrays directly. The only reason we refer to * them here is to avoid the procedure call that would be required in the * macros below. (Really want private data members here :-) */ @@ -44,12 +44,12 @@ extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES]; /* * These macros are used by various parts of the kernel to convert - * between the three different kinds of node numbering. At least some + * between the three different kinds of node numbering. At least some * of them may change to procedure calls in the future, but the macros * will continue to work. Don't use the arrays above directly. */ -#define NASID_TO_REGION(nnode) \ +#define NASID_TO_REGION(nnode) \ ((nnode) >> \ (is_fine_dirmode() ? NASID_TO_FINEREG_SHFT : NASID_TO_COARSEREG_SHFT)) diff --git a/arch/mips/include/asm/sn/fru.h b/arch/mips/include/asm/sn/fru.h index b3e3606723b..bbb83257c8e 100644 --- a/arch/mips/include/asm/sn/fru.h +++ b/arch/mips/include/asm/sn/fru.h @@ -21,24 +21,24 @@ typedef struct kf_mem_s { * is this necessary ? */ confidence_t km_dimm[MAX_DIMMS]; - /* confidence level that dimm[i] is bad + /* confidence level that dimm[i] is bad *I think this is the right number */ } kf_mem_t; typedef struct kf_cpu_s { - confidence_t kc_confidence; /* confidence level that cpu is bad */ - confidence_t kc_icache; /* confidence level that instr. cache is bad */ - confidence_t kc_dcache; /* confidence level that data cache is bad */ - confidence_t kc_scache; /* confidence level that sec. cache is bad */ + confidence_t kc_confidence; /* confidence level that cpu is bad */ + confidence_t kc_icache; /* confidence level that instr. cache is bad */ + confidence_t kc_dcache; /* confidence level that data cache is bad */ + confidence_t kc_scache; /* confidence level that sec. cache is bad */ confidence_t kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */ } kf_cpu_t; typedef struct kf_pci_bus_s { confidence_t kpb_belief; /* confidence level that the pci bus is bad */ confidence_t kpb_pcidev_belief[MAX_PCIDEV]; - /* confidence level that the pci dev is bad */ + /* confidence level that the pci dev is bad */ } kf_pci_bus_t; #endif /* __ASM_SN_FRU_H */ diff --git a/arch/mips/include/asm/sn/gda.h b/arch/mips/include/asm/sn/gda.h index 9cb6ff77091..85fa1b5f639 100644 --- a/arch/mips/include/asm/sn/gda.h +++ b/arch/mips/include/asm/sn/gda.h @@ -8,7 +8,7 @@ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. * * gda.h -- Contains the data structure for the global data area, - * The GDA contains information communicated between the + * The GDA contains information communicated between the * PROM, SYMMON, and the kernel. */ #ifndef _ASM_SN_GDA_H @@ -23,8 +23,8 @@ * * Version # | Change * -------------+------------------------------------------------------- - * 1 | Initial SN0 version - * 2 | Prom sets g_partid field to the partition number. 0 IS + * 1 | Initial SN0 version + * 2 | Prom sets g_partid field to the partition number. 0 IS * | a valid partition #. */ @@ -60,7 +60,7 @@ typedef struct gda { /* Pointer to a mask of nodes with copies * of the kernel. */ char g_padding[56]; /* pad out to 128 bytes */ - nasid_t g_nasidtable[MAX_COMPACT_NODES]; /* NASID of each node, + nasid_t g_nasidtable[MAX_COMPACT_NODES]; /* NASID of each node, * indexed by cnodeid. */ } gda_t; @@ -74,7 +74,7 @@ typedef struct gda { * revisions assume GDA is NOT set up, and read partition * information from the board info. */ -#define PART_GDA_VERSION 2 +#define PART_GDA_VERSION 2 /* * The following requests can be sent to the PROM during startup. @@ -83,17 +83,17 @@ typedef struct gda { #define PROMOP_MAGIC 0x0ead0000 #define PROMOP_MAGIC_MASK 0x0fff0000 -#define PROMOP_BIST_SHIFT 11 -#define PROMOP_BIST_MASK (0x3 << 11) +#define PROMOP_BIST_SHIFT 11 +#define PROMOP_BIST_MASK (0x3 << 11) #define PROMOP_REG PI_ERR_STACK_ADDR_A #define PROMOP_INVALID (PROMOP_MAGIC | 0x00) -#define PROMOP_HALT (PROMOP_MAGIC | 0x10) -#define PROMOP_POWERDOWN (PROMOP_MAGIC | 0x20) -#define PROMOP_RESTART (PROMOP_MAGIC | 0x30) -#define PROMOP_REBOOT (PROMOP_MAGIC | 0x40) -#define PROMOP_IMODE (PROMOP_MAGIC | 0x50) +#define PROMOP_HALT (PROMOP_MAGIC | 0x10) +#define PROMOP_POWERDOWN (PROMOP_MAGIC | 0x20) +#define PROMOP_RESTART (PROMOP_MAGIC | 0x30) +#define PROMOP_REBOOT (PROMOP_MAGIC | 0x40) +#define PROMOP_IMODE (PROMOP_MAGIC | 0x50) #define PROMOP_CMD_MASK 0x00f0 #define PROMOP_OPTIONS_MASK 0xfff0 diff --git a/arch/mips/include/asm/sn/intr.h b/arch/mips/include/asm/sn/intr.h index 6718b644b97..fc134819395 100644 --- a/arch/mips/include/asm/sn/intr.h +++ b/arch/mips/include/asm/sn/intr.h @@ -14,8 +14,8 @@ #define INT_PEND0_BASELVL 0 #define INT_PEND1_BASELVL 64 -#define N_INTPENDJUNK_BITS 8 -#define INTPENDJUNK_CLRBIT 0x80 +#define N_INTPENDJUNK_BITS 8 +#define INTPENDJUNK_CLRBIT 0x80 /* * Macros to manipulate the interrupt register on the calling hub chip. @@ -32,7 +32,7 @@ * We do an uncached load of the int_pend0 register to ensure this. */ -#define LOCAL_HUB_CLR_INTR(level) \ +#define LOCAL_HUB_CLR_INTR(level) \ do { \ LOCAL_HUB_S(PI_INT_PEND_MOD, (level)); \ LOCAL_HUB_L(PI_INT_PEND0); \ @@ -40,7 +40,7 @@ do { \ #define REMOTE_HUB_CLR_INTR(hub, level) \ do { \ - nasid_t __hub = (hub); \ + nasid_t __hub = (hub); \ \ REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level)); \ REMOTE_HUB_L(__hub, PI_INT_PEND0); \ @@ -102,8 +102,8 @@ do { \ #define LLP_PFAIL_INTR_A 41 /* see ml/SN/SN0/sysctlr.c */ #define LLP_PFAIL_INTR_B 42 -#define TLB_INTR_A 43 /* used for tlb flush random */ -#define TLB_INTR_B 44 +#define TLB_INTR_A 43 /* used for tlb flush random */ +#define TLB_INTR_B 44 #define IP27_INTR_0 45 /* Reserved for PROM use */ #define IP27_INTR_1 46 /* do not use in Kernel */ @@ -116,8 +116,8 @@ do { \ #define BRIDGE_ERROR_INTR 53 /* Setup by PROM to catch */ /* Bridge Errors */ -#define DEBUG_INTR_A 54 -#define DEBUG_INTR_B 55 /* Used by symmon to stop all cpus */ +#define DEBUG_INTR_A 54 +#define DEBUG_INTR_B 55 /* Used by symmon to stop all cpus */ #define IO_ERROR_INTR 57 /* Setup by PROM */ #define CLK_ERR_INTR 58 #define COR_ERR_INTR_A 59 diff --git a/arch/mips/include/asm/sn/io.h b/arch/mips/include/asm/sn/io.h index 24c6775fbb0..d5174d04538 100644 --- a/arch/mips/include/asm/sn/io.h +++ b/arch/mips/include/asm/sn/io.h @@ -31,7 +31,7 @@ #define HUB_PIO_MAP_TO_MEM 0 #define HUB_PIO_MAP_TO_IO 1 -#define IIO_ITTE_INVALID_WIDGET 3 /* an invalid widget */ +#define IIO_ITTE_INVALID_WIDGET 3 /* an invalid widget */ #define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) \ REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), \ @@ -52,7 +52,7 @@ * value _x is expected to be a widget number in the range * 0, 8 - 0xF */ -#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \ +#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \ (_x) : \ (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) diff --git a/arch/mips/include/asm/sn/ioc3.h b/arch/mips/include/asm/sn/ioc3.h index 099677774d7..e33f0363235 100644 --- a/arch/mips/include/asm/sn/ioc3.h +++ b/arch/mips/include/asm/sn/ioc3.h @@ -62,8 +62,8 @@ struct ioc3_sioregs { volatile u8 fill3[0x170 - 0x169 - 1]; - struct ioc3_uartregs uartb; /* 0x20170 */ - struct ioc3_uartregs uarta; /* 0x20178 */ + struct ioc3_uartregs uartb; /* 0x20170 */ + struct ioc3_uartregs uarta; /* 0x20178 */ }; /* Register layout of IOC3 in configuration space. */ @@ -106,7 +106,7 @@ struct ioc3 { volatile u32 ppbr_l_b; /* 0x00094 */ volatile u32 ppcr_b; /* 0x00098 */ - /* Keyboard and Mouse Registers */ + /* Keyboard and Mouse Registers */ volatile u32 km_csr; /* 0x0009c */ volatile u32 k_rd; /* 0x000a0 */ volatile u32 m_rd; /* 0x000a4 */ @@ -208,7 +208,7 @@ struct ioc3_erxbuf { /* * Ethernet TX Descriptor */ -#define ETXD_DATALEN 104 +#define ETXD_DATALEN 104 struct ioc3_etxd { u32 cmd; /* command field */ u32 bufcnt; /* buffer counts field */ diff --git a/arch/mips/include/asm/sn/klconfig.h b/arch/mips/include/asm/sn/klconfig.h index fe02900b930..467c313d576 100644 --- a/arch/mips/include/asm/sn/klconfig.h +++ b/arch/mips/include/asm/sn/klconfig.h @@ -8,8 +8,8 @@ * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 1999, 2000 by Ralf Baechle */ -#ifndef _ASM_SN_KLCONFIG_H -#define _ASM_SN_KLCONFIG_H +#ifndef _ASM_SN_KLCONFIG_H +#define _ASM_SN_KLCONFIG_H /* * The KLCONFIG structures store info about the various BOARDs found @@ -20,11 +20,11 @@ /* * WARNING: * Certain assembly language routines (notably xxxxx.s) in the IP27PROM - * will depend on the format of the data structures in this file. In - * most cases, rearranging the fields can seriously break things. - * Adding fields in the beginning or middle can also break things. - * Add fields if necessary, to the end of a struct in such a way - * that offsets of existing fields do not change. + * will depend on the format of the data structures in this file. In + * most cases, rearranging the fields can seriously break things. + * Adding fields in the beginning or middle can also break things. + * Add fields if necessary, to the end of a struct in such a way + * that offsets of existing fields do not change. */ #include <linux/types.h> @@ -35,7 +35,7 @@ #include <asm/sn/sn0/addrs.h> //#include <sys/SN/router.h> // XXX Stolen from <sys/SN/router.h>: -#define MAX_ROUTER_PORTS (6) /* Max. number of ports on a router */ +#define MAX_ROUTER_PORTS (6) /* Max. number of ports on a router */ #include <asm/sn/fru.h> //#include <sys/graph.h> //#include <sys/xtalk/xbow.h> @@ -63,14 +63,14 @@ typedef u64 nic_t; -#define KLCFGINFO_MAGIC 0xbeedbabe +#define KLCFGINFO_MAGIC 0xbeedbabe typedef s32 klconf_off_t; /* * Some IMPORTANT OFFSETS. These are the offsets on all NODES. */ -#define MAX_MODULE_ID 255 +#define MAX_MODULE_ID 255 #define SIZE_PAD 4096 /* 4k padding for structures */ /* * 1 NODE brd, 2 Router brd (1 8p, 1 meta), 6 Widgets, @@ -86,25 +86,25 @@ typedef s32 klconf_off_t; /* All bits in this field are currently used. Try the pad fields if you need more flag bits */ -#define ENABLE_BOARD 0x01 -#define FAILED_BOARD 0x02 -#define DUPLICATE_BOARD 0x04 /* Boards like midplanes/routers which +#define ENABLE_BOARD 0x01 +#define FAILED_BOARD 0x02 +#define DUPLICATE_BOARD 0x04 /* Boards like midplanes/routers which are discovered twice. Use one of them */ #define VISITED_BOARD 0x08 /* Used for compact hub numbering. */ -#define LOCAL_MASTER_IO6 0x10 /* master io6 for that node */ +#define LOCAL_MASTER_IO6 0x10 /* master io6 for that node */ #define GLOBAL_MASTER_IO6 0x20 -#define THIRD_NIC_PRESENT 0x40 /* for future use */ -#define SECOND_NIC_PRESENT 0x80 /* addons like MIO are present */ +#define THIRD_NIC_PRESENT 0x40 /* for future use */ +#define SECOND_NIC_PRESENT 0x80 /* addons like MIO are present */ /* klinfo->flags fields */ -#define KLINFO_ENABLE 0x01 /* This component is enabled */ -#define KLINFO_FAILED 0x02 /* This component failed */ -#define KLINFO_DEVICE 0x04 /* This component is a device */ -#define KLINFO_VISITED 0x08 /* This component has been visited */ -#define KLINFO_CONTROLLER 0x10 /* This component is a device controller */ -#define KLINFO_INSTALL 0x20 /* Install a driver */ -#define KLINFO_HEADLESS 0x40 /* Headless (or hubless) component */ +#define KLINFO_ENABLE 0x01 /* This component is enabled */ +#define KLINFO_FAILED 0x02 /* This component failed */ +#define KLINFO_DEVICE 0x04 /* This component is a device */ +#define KLINFO_VISITED 0x08 /* This component has been visited */ +#define KLINFO_CONTROLLER 0x10 /* This component is a device controller */ +#define KLINFO_INSTALL 0x20 /* Install a driver */ +#define KLINFO_HEADLESS 0x40 /* Headless (or hubless) component */ #define IS_CONSOLE_IOC3(i) ((((klinfo_t *)i)->flags) & KLINFO_INSTALL) #define GB2 0x80000000 @@ -116,30 +116,30 @@ typedef s32 klconf_off_t; is used in the code to allocate various areas. */ -#define BOARD_STRUCT 0 -#define COMPONENT_STRUCT 1 -#define ERRINFO_STRUCT 2 -#define KLMALLOC_TYPE_MAX (ERRINFO_STRUCT + 1) -#define DEVICE_STRUCT 3 +#define BOARD_STRUCT 0 +#define COMPONENT_STRUCT 1 +#define ERRINFO_STRUCT 2 +#define KLMALLOC_TYPE_MAX (ERRINFO_STRUCT + 1) +#define DEVICE_STRUCT 3 typedef struct console_s { - unsigned long uart_base; - unsigned long config_base; - unsigned long memory_base; + unsigned long uart_base; + unsigned long config_base; + unsigned long memory_base; short baud; short flag; int type; nasid_t nasid; char wid; - char npci; + char npci; nic_t baseio_nic; } console_t; typedef struct klc_malloc_hdr { - klconf_off_t km_base; - klconf_off_t km_limit; - klconf_off_t km_current; + klconf_off_t km_base; + klconf_off_t km_limit; + klconf_off_t km_current; } klc_malloc_hdr_t; /* Functions/macros needed to use this structure */ @@ -148,7 +148,7 @@ typedef struct kl_config_hdr { u64 ch_magic; /* set this to KLCFGINFO_MAGIC */ u32 ch_version; /* structure version number */ klconf_off_t ch_malloc_hdr_off; /* offset of ch_malloc_hdr */ - klconf_off_t ch_cons_off; /* offset of ch_cons */ + klconf_off_t ch_cons_off; /* offset of ch_cons */ klconf_off_t ch_board_info; /* the link list of boards */ console_t ch_cons_info; /* address info of the console */ klc_malloc_hdr_t ch_malloc_hdr[KLMALLOC_TYPE_MAX]; @@ -157,27 +157,27 @@ typedef struct kl_config_hdr { } kl_config_hdr_t; -#define KL_CONFIG_HDR(_nasid) ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid))) +#define KL_CONFIG_HDR(_nasid) ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid))) #define KL_CONFIG_INFO_OFFSET(_nasid) \ - (KL_CONFIG_HDR(_nasid)->ch_board_info) + (KL_CONFIG_HDR(_nasid)->ch_board_info) #define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off) \ - (KL_CONFIG_HDR(_nasid)->ch_board_info = (_off)) + (KL_CONFIG_HDR(_nasid)->ch_board_info = (_off)) -#define KL_CONFIG_INFO(_nasid) \ - (lboard_t *)((KL_CONFIG_HDR(_nasid)->ch_board_info) ? \ +#define KL_CONFIG_INFO(_nasid) \ + (lboard_t *)((KL_CONFIG_HDR(_nasid)->ch_board_info) ? \ NODE_OFFSET_TO_K1((_nasid), KL_CONFIG_HDR(_nasid)->ch_board_info) : \ 0) #define KL_CONFIG_MAGIC(_nasid) (KL_CONFIG_HDR(_nasid)->ch_magic) #define KL_CONFIG_CHECK_MAGIC(_nasid) \ - (KL_CONFIG_HDR(_nasid)->ch_magic == KLCFGINFO_MAGIC) + (KL_CONFIG_HDR(_nasid)->ch_magic == KLCFGINFO_MAGIC) #define KL_CONFIG_HDR_INIT_MAGIC(_nasid) \ - (KL_CONFIG_HDR(_nasid)->ch_magic = KLCFGINFO_MAGIC) + (KL_CONFIG_HDR(_nasid)->ch_magic = KLCFGINFO_MAGIC) /* --- New Macros for the changed kl_config_hdr_t structure --- */ -#define PTR_CH_MALLOC_HDR(_k) ((klc_malloc_hdr_t *)\ +#define PTR_CH_MALLOC_HDR(_k) ((klc_malloc_hdr_t *)\ ((unsigned long)_k + (_k->ch_malloc_hdr_off))) #define KL_CONFIG_CH_MALLOC_HDR(_n) PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n)) @@ -190,29 +190,29 @@ typedef struct kl_config_hdr { /* ------------------------------------------------------------- */ #define KL_CONFIG_INFO_START(_nasid) \ - (klconf_off_t)(KLCONFIG_OFFSET(_nasid) + sizeof(kl_config_hdr_t)) + (klconf_off_t)(KLCONFIG_OFFSET(_nasid) + sizeof(kl_config_hdr_t)) #define KL_CONFIG_BOARD_NASID(_brd) ((_brd)->brd_nasid) #define KL_CONFIG_BOARD_SET_NEXT(_brd, _off) ((_brd)->brd_next = (_off)) -#define KL_CONFIG_DUPLICATE_BOARD(_brd) ((_brd)->brd_flags & DUPLICATE_BOARD) +#define KL_CONFIG_DUPLICATE_BOARD(_brd) ((_brd)->brd_flags & DUPLICATE_BOARD) -#define XBOW_PORT_TYPE_HUB(_xbowp, _link) \ - ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_HUB) -#define XBOW_PORT_TYPE_IO(_xbowp, _link) \ - ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_IO) +#define XBOW_PORT_TYPE_HUB(_xbowp, _link) \ + ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_HUB) +#define XBOW_PORT_TYPE_IO(_xbowp, _link) \ + ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_IO) -#define XBOW_PORT_IS_ENABLED(_xbowp, _link) \ - ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_ENABLE) -#define XBOW_PORT_NASID(_xbowp, _link) \ - ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_nasid) +#define XBOW_PORT_IS_ENABLED(_xbowp, _link) \ + ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_ENABLE) +#define XBOW_PORT_NASID(_xbowp, _link) \ + ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_nasid) -#define XBOW_PORT_IO 0x1 -#define XBOW_PORT_HUB 0x2 +#define XBOW_PORT_IO 0x1 +#define XBOW_PORT_HUB 0x2 #define XBOW_PORT_ENABLE 0x4 -#define SN0_PORT_FENCE_SHFT 0 -#define SN0_PORT_FENCE_MASK (1 << SN0_PORT_FENCE_SHFT) +#define SN0_PORT_FENCE_SHFT 0 +#define SN0_PORT_FENCE_MASK (1 << SN0_PORT_FENCE_SHFT) /* * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD @@ -242,28 +242,28 @@ typedef struct kl_config_hdr { * KLCONFIG - +------------+ +------------+ +------------+ +------------+ - | lboard | +-->| lboard | +-->| rboard | +-->| lboard | - +------------+ | +------------+ | +------------+ | +------------+ - | board info | | | board info | | |errinfo,bptr| | | board info | - +------------+ | +------------+ | +------------+ | +------------+ - | offset |--+ | offset |--+ | offset |--+ |offset=NULL | - +------------+ +------------+ +------------+ +------------+ + +------------+ +------------+ +------------+ +------------+ + | lboard | +-->| lboard | +-->| rboard | +-->| lboard | + +------------+ | +------------+ | +------------+ | +------------+ + | board info | | | board info | | |errinfo,bptr| | | board info | + +------------+ | +------------+ | +------------+ | +------------+ + | offset |--+ | offset |--+ | offset |--+ |offset=NULL | + +------------+ +------------+ +------------+ +------------+ +------------+ | board info | - +------------+ +--------------------------------+ + +------------+ +--------------------------------+ | compt 1 |------>| type, rev, diaginfo, size ... | (CPU) - +------------+ +--------------------------------+ + +------------+ +--------------------------------+ | compt 2 |--+ - +------------+ | +--------------------------------+ - | ... | +--->| type, rev, diaginfo, size ... | (MEM_BANK) - +------------+ +--------------------------------+ + +------------+ | +--------------------------------+ + | ... | +--->| type, rev, diaginfo, size ... | (MEM_BANK) + +------------+ +--------------------------------+ | errinfo |--+ - +------------+ | +--------------------------------+ - +--->|r/l brd errinfo,compt err flags | - +--------------------------------+ + +------------+ | +--------------------------------+ + +--->|r/l brd errinfo,compt err flags | + +--------------------------------+ * * Each BOARD consists of COMPONENTs and the BOARD structure has @@ -311,7 +311,7 @@ typedef struct kl_config_hdr { */ #define KL_CPU_R4000 0x1 /* Standard R4000 */ #define KL_CPU_TFP 0x2 /* TFP processor */ -#define KL_CPU_R10000 0x3 /* R10000 (T5) */ +#define KL_CPU_R10000 0x3 /* R10000 (T5) */ #define KL_CPU_NONE (-1) /* no cpu present in slot */ /* @@ -320,13 +320,13 @@ typedef struct kl_config_hdr { #define KLCLASS_MASK 0xf0 #define KLCLASS_NONE 0x00 -#define KLCLASS_NODE 0x10 /* CPU, Memory and HUB board */ +#define KLCLASS_NODE 0x10 /* CPU, Memory and HUB board */ #define KLCLASS_CPU KLCLASS_NODE -#define KLCLASS_IO 0x20 /* BaseIO, 4 ch SCSI, ethernet, FDDI +#define KLCLASS_IO 0x20 /* BaseIO, 4 ch SCSI, ethernet, FDDI and the non-graphics widget boards */ -#define KLCLASS_ROUTER 0x30 /* Router board */ -#define KLCLASS_MIDPLANE 0x40 /* We need to treat this as a board - so that we can record error info */ +#define KLCLASS_ROUTER 0x30 /* Router board */ +#define KLCLASS_MIDPLANE 0x40 /* We need to treat this as a board + so that we can record error info */ #define KLCLASS_GFX 0x50 /* graphics boards */ #define KLCLASS_PSEUDO_GFX 0x60 /* HDTV type cards that use a gfx @@ -336,7 +336,7 @@ typedef struct kl_config_hdr { #define KLCLASS_MAX 7 /* Bump this if a new CLASS is added */ #define KLTYPE_MAX 10 /* Bump this if a new CLASS is added */ -#define KLCLASS_UNKNOWN 0xf0 +#define KLCLASS_UNKNOWN 0xf0 #define KLCLASS(_x) ((_x) & KLCLASS_MASK) @@ -353,36 +353,36 @@ typedef struct kl_config_hdr { #define KLTYPE_WEIRDIO (KLCLASS_IO | 0x0) #define KLTYPE_BASEIO (KLCLASS_IO | 0x1) /* IOC3, SuperIO, Bridge, SCSI */ -#define KLTYPE_IO6 KLTYPE_BASEIO /* Additional name */ +#define KLTYPE_IO6 KLTYPE_BASEIO /* Additional name */ #define KLTYPE_4CHSCSI (KLCLASS_IO | 0x2) -#define KLTYPE_MSCSI KLTYPE_4CHSCSI /* Additional name */ -#define KLTYPE_ETHERNET (KLCLASS_IO | 0x3) -#define KLTYPE_MENET KLTYPE_ETHERNET /* Additional name */ -#define KLTYPE_FDDI (KLCLASS_IO | 0x4) +#define KLTYPE_MSCSI KLTYPE_4CHSCSI /* Additional name */ +#define KLTYPE_ETHERNET (KLCLASS_IO | 0x3) +#define KLTYPE_MENET KLTYPE_ETHERNET /* Additional name */ +#define KLTYPE_FDDI (KLCLASS_IO | 0x4) #define KLTYPE_UNUSED (KLCLASS_IO | 0x5) /* XXX UNUSED */ -#define KLTYPE_HAROLD (KLCLASS_IO | 0x6) /* PCI SHOE BOX */ +#define KLTYPE_HAROLD (KLCLASS_IO | 0x6) /* PCI SHOE BOX */ #define KLTYPE_PCI KLTYPE_HAROLD -#define KLTYPE_VME (KLCLASS_IO | 0x7) /* Any 3rd party VME card */ -#define KLTYPE_MIO (KLCLASS_IO | 0x8) -#define KLTYPE_FC (KLCLASS_IO | 0x9) -#define KLTYPE_LINC (KLCLASS_IO | 0xA) -#define KLTYPE_TPU (KLCLASS_IO | 0xB) /* Tensor Processing Unit */ -#define KLTYPE_GSN_A (KLCLASS_IO | 0xC) /* Main GSN board */ -#define KLTYPE_GSN_B (KLCLASS_IO | 0xD) /* Auxiliary GSN board */ +#define KLTYPE_VME (KLCLASS_IO | 0x7) /* Any 3rd party VME card */ +#define KLTYPE_MIO (KLCLASS_IO | 0x8) +#define KLTYPE_FC (KLCLASS_IO | 0x9) +#define KLTYPE_LINC (KLCLASS_IO | 0xA) +#define KLTYPE_TPU (KLCLASS_IO | 0xB) /* Tensor Processing Unit */ +#define KLTYPE_GSN_A (KLCLASS_IO | 0xC) /* Main GSN board */ +#define KLTYPE_GSN_B (KLCLASS_IO | 0xD) /* Auxiliary GSN board */ #define KLTYPE_GFX (KLCLASS_GFX | 0x0) /* unknown graphics type */ #define KLTYPE_GFX_KONA (KLCLASS_GFX | 0x1) /* KONA graphics on IP27 */ #define KLTYPE_GFX_MGRA (KLCLASS_GFX | 0x3) /* MGRAS graphics on IP27 */ #define KLTYPE_WEIRDROUTER (KLCLASS_ROUTER | 0x0) -#define KLTYPE_ROUTER (KLCLASS_ROUTER | 0x1) -#define KLTYPE_ROUTER2 KLTYPE_ROUTER /* Obsolete! */ +#define KLTYPE_ROUTER (KLCLASS_ROUTER | 0x1) +#define KLTYPE_ROUTER2 KLTYPE_ROUTER /* Obsolete! */ #define KLTYPE_NULL_ROUTER (KLCLASS_ROUTER | 0x2) #define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3) #define KLTYPE_WEIRDMIDPLANE (KLCLASS_MIDPLANE | 0x0) #define KLTYPE_MIDPLANE8 (KLCLASS_MIDPLANE | 0x1) /* 8 slot backplane */ -#define KLTYPE_MIDPLANE KLTYPE_MIDPLANE8 +#define KLTYPE_MIDPLANE KLTYPE_MIDPLANE8 #define KLTYPE_PBRICK_XBOW (KLCLASS_MIDPLANE | 0x2) #define KLTYPE_IOBRICK (KLCLASS_IOBRICK | 0x0) @@ -398,11 +398,11 @@ typedef struct kl_config_hdr { * When bringup started nic names had not standardized and so we * had to hard code. (For people interested in history.) */ -#define KLTYPE_XTHD (KLCLASS_PSEUDO_GFX | 0x9) +#define KLTYPE_XTHD (KLCLASS_PSEUDO_GFX | 0x9) #define KLTYPE_UNKNOWN (KLCLASS_UNKNOWN | 0xf) -#define KLTYPE(_x) ((_x) & KLTYPE_MASK) +#define KLTYPE(_x) ((_x) & KLTYPE_MASK) #define IS_MIO_PRESENT(l) ((l->brd_type == KLTYPE_BASEIO) && \ (l->brd_flags & SECOND_NIC_PRESENT)) #define IS_MIO_IOC3(l, n) (IS_MIO_PRESENT(l) && (n > 2)) @@ -416,33 +416,33 @@ typedef struct kl_config_hdr { #define LOCAL_BOARD 1 #define REMOTE_BOARD 2 -#define LBOARD_STRUCT_VERSION 2 +#define LBOARD_STRUCT_VERSION 2 typedef struct lboard_s { - klconf_off_t brd_next; /* Next BOARD */ - unsigned char struct_type; /* type of structure, local or remote */ - unsigned char brd_type; /* type+class */ - unsigned char brd_sversion; /* version of this structure */ - unsigned char brd_brevision; /* board revision */ - unsigned char brd_promver; /* board prom version, if any */ - unsigned char brd_flags; /* Enabled, Disabled etc */ - unsigned char brd_slot; /* slot number */ - unsigned short brd_debugsw; /* Debug switches */ - moduleid_t brd_module; /* module to which it belongs */ - partid_t brd_partition; /* Partition number */ - unsigned short brd_diagval; /* diagnostic value */ - unsigned short brd_diagparm; /* diagnostic parameter */ - unsigned char brd_inventory; /* inventory history */ - unsigned char brd_numcompts; /* Number of components */ - nic_t brd_nic; /* Number in CAN */ - nasid_t brd_nasid; /* passed parameter */ - klconf_off_t brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */ - klconf_off_t brd_errinfo; /* Board's error information */ + klconf_off_t brd_next; /* Next BOARD */ + unsigned char struct_type; /* type of structure, local or remote */ + unsigned char brd_type; /* type+class */ + unsigned char brd_sversion; /* version of this structure */ + unsigned char brd_brevision; /* board revision */ + unsigned char brd_promver; /* board prom version, if any */ + unsigned char brd_flags; /* Enabled, Disabled etc */ + unsigned char brd_slot; /* slot number */ + unsigned short brd_debugsw; /* Debug switches */ + moduleid_t brd_module; /* module to which it belongs */ + partid_t brd_partition; /* Partition number */ + unsigned short brd_diagval; /* diagnostic value */ + unsigned short brd_diagparm; /* diagnostic parameter */ + unsigned char brd_inventory; /* inventory history */ + unsigned char brd_numcompts; /* Number of components */ + nic_t brd_nic; /* Number in CAN */ + nasid_t brd_nasid; /* passed parameter */ + klconf_off_t brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */ + klconf_off_t brd_errinfo; /* Board's error information */ struct lboard_s *brd_parent; /* Logical parent for this brd */ - vertex_hdl_t brd_graph_link; /* vertex hdl to connect extern compts */ + vertex_hdl_t brd_graph_link; /* vertex hdl to connect extern compts */ confidence_t brd_confidence; /* confidence that the board is bad */ - nasid_t brd_owner; /* who owns this board */ - unsigned char brd_nic_flags; /* To handle 8 more NICs */ + nasid_t brd_owner; /* who owns this board */ + unsigned char brd_nic_flags; /* To handle 8 more NICs */ char brd_name[32]; } lboard_t; @@ -456,23 +456,23 @@ typedef struct lboard_s { #define KLCF_CLASS(_brd) KLCLASS((_brd)->brd_type) #define KLCF_TYPE(_brd) KLTYPE((_brd)->brd_type) -#define KLCF_REMOTE(_brd) (((_brd)->struct_type & LOCAL_BOARD) ? 0 : 1) +#define KLCF_REMOTE(_brd) (((_brd)->struct_type & LOCAL_BOARD) ? 0 : 1) #define KLCF_NUM_COMPS(_brd) ((_brd)->brd_numcompts) #define KLCF_MODULE_ID(_brd) ((_brd)->brd_module) -#define KLCF_NEXT(_brd) \ - ((_brd)->brd_next ? \ +#define KLCF_NEXT(_brd) \ + ((_brd)->brd_next ? \ (lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\ NULL) -#define KLCF_COMP(_brd, _ndx) \ - (klinfo_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), \ +#define KLCF_COMP(_brd, _ndx) \ + (klinfo_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), \ (_brd)->brd_compts[(_ndx)])) #define KLCF_COMP_ERROR(_brd, _comp) \ - (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo)) + (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo)) #define KLCF_COMP_TYPE(_comp) ((_comp)->struct_type) -#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid) /* Widget ID */ +#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid) /* Widget ID */ @@ -481,73 +481,73 @@ typedef struct lboard_s { * component. */ -typedef struct klinfo_s { /* Generic info */ - unsigned char struct_type; /* type of this structure */ - unsigned char struct_version; /* version of this structure */ - unsigned char flags; /* Enabled, disabled etc */ - unsigned char revision; /* component revision */ - unsigned short diagval; /* result of diagnostics */ - unsigned short diagparm; /* diagnostic parameter */ - unsigned char inventory; /* previous inventory status */ - nic_t nic; /* MUst be aligned properly */ - unsigned char physid; /* physical id of component */ - unsigned int virtid; /* virtual id as seen by system */ - unsigned char widid; /* Widget id - if applicable */ - nasid_t nasid; /* node number - from parent */ +typedef struct klinfo_s { /* Generic info */ + unsigned char struct_type; /* type of this structure */ + unsigned char struct_version; /* version of this structure */ + unsigned char flags; /* Enabled, disabled etc */ + unsigned char revision; /* component revision */ + unsigned short diagval; /* result of diagnostics */ + unsigned short diagparm; /* diagnostic parameter */ + unsigned char inventory; /* previous inventory status */ + nic_t nic; /* MUst be aligned properly */ + unsigned char physid; /* physical id of component */ + unsigned int virtid; /* virtual id as seen by system */ + unsigned char widid; /* Widget id - if applicable */ + nasid_t nasid; /* node number - from parent */ char pad1; /* pad out structure. */ char pad2; /* pad out structure. */ - COMPONENT *arcs_compt; /* ptr to the arcs struct for ease*/ - klconf_off_t errinfo; /* component specific errors */ - unsigned short pad3; /* pci fields have moved over to */ - unsigned short pad4; /* klbri_t */ + COMPONENT *arcs_compt; /* ptr to the arcs struct for ease*/ + klconf_off_t errinfo; /* component specific errors */ + unsigned short pad3; /* pci fields have moved over to */ + unsigned short pad4; /* klbri_t */ } klinfo_t ; #define KLCONFIG_INFO_ENABLED(_i) ((_i)->flags & KLINFO_ENABLE) /* * Component structures. * Following are the currently identified components: - * CPU, HUB, MEM_BANK, - * XBOW(consists of 16 WIDGETs, each of which can be HUB or GRAPHICS or BRIDGE) - * BRIDGE, IOC3, SuperIO, SCSI, FDDI - * ROUTER - * GRAPHICS + * CPU, HUB, MEM_BANK, + * XBOW(consists of 16 WIDGETs, each of which can be HUB or GRAPHICS or BRIDGE) + * BRIDGE, IOC3, SuperIO, SCSI, FDDI + * ROUTER + * GRAPHICS */ #define KLSTRUCT_UNKNOWN 0 -#define KLSTRUCT_CPU 1 -#define KLSTRUCT_HUB 2 -#define KLSTRUCT_MEMBNK 3 -#define KLSTRUCT_XBOW 4 -#define KLSTRUCT_BRI 5 -#define KLSTRUCT_IOC3 6 -#define KLSTRUCT_PCI 7 -#define KLSTRUCT_VME 8 +#define KLSTRUCT_CPU 1 +#define KLSTRUCT_HUB 2 +#define KLSTRUCT_MEMBNK 3 +#define KLSTRUCT_XBOW 4 +#define KLSTRUCT_BRI 5 +#define KLSTRUCT_IOC3 6 +#define KLSTRUCT_PCI 7 +#define KLSTRUCT_VME 8 #define KLSTRUCT_ROU 9 -#define KLSTRUCT_GFX 10 -#define KLSTRUCT_SCSI 11 -#define KLSTRUCT_FDDI 12 -#define KLSTRUCT_MIO 13 -#define KLSTRUCT_DISK 14 -#define KLSTRUCT_TAPE 15 -#define KLSTRUCT_CDROM 16 -#define KLSTRUCT_HUB_UART 17 -#define KLSTRUCT_IOC3ENET 18 -#define KLSTRUCT_IOC3UART 19 +#define KLSTRUCT_GFX 10 +#define KLSTRUCT_SCSI 11 +#define KLSTRUCT_FDDI 12 +#define KLSTRUCT_MIO 13 +#define KLSTRUCT_DISK 14 +#define KLSTRUCT_TAPE 15 +#define KLSTRUCT_CDROM 16 +#define KLSTRUCT_HUB_UART 17 +#define KLSTRUCT_IOC3ENET 18 +#define KLSTRUCT_IOC3UART 19 #define KLSTRUCT_UNUSED 20 /* XXX UNUSED */ -#define KLSTRUCT_IOC3PCKM 21 -#define KLSTRUCT_RAD 22 -#define KLSTRUCT_HUB_TTY 23 -#define KLSTRUCT_IOC3_TTY 24 +#define KLSTRUCT_IOC3PCKM 21 +#define KLSTRUCT_RAD 22 +#define KLSTRUCT_HUB_TTY 23 +#define KLSTRUCT_IOC3_TTY 24 /* Early Access IO proms are compatible only with KLSTRUCT values up to 24. */ -#define KLSTRUCT_FIBERCHANNEL 25 +#define KLSTRUCT_FIBERCHANNEL 25 #define KLSTRUCT_MOD_SERIAL_NUM 26 -#define KLSTRUCT_IOC3MS 27 -#define KLSTRUCT_TPU 28 -#define KLSTRUCT_GSN_A 29 -#define KLSTRUCT_GSN_B 30 -#define KLSTRUCT_XTHD 31 +#define KLSTRUCT_IOC3MS 27 +#define KLSTRUCT_TPU 28 +#define KLSTRUCT_GSN_A 29 +#define KLSTRUCT_GSN_B 30 +#define KLSTRUCT_XTHD 31 /* * These are the indices of various components within a lboard structure. @@ -583,7 +583,7 @@ typedef u64 *router_t; * The port info in ip27_cfg area translates to a lboart_t in the * KLCONFIG area. But since KLCONFIG does not use pointers, lboart_t * is stored in terms of a nasid and a offset from start of KLCONFIG - * area on that nasid. + * area on that nasid. */ typedef struct klport_s { nasid_t port_nasid; @@ -591,20 +591,20 @@ typedef struct klport_s { klconf_off_t port_offset; } klport_t; -typedef struct klcpu_s { /* CPU */ - klinfo_t cpu_info; - unsigned short cpu_prid; /* Processor PRID value */ - unsigned short cpu_fpirr; /* FPU IRR value */ - unsigned short cpu_speed; /* Speed in MHZ */ - unsigned short cpu_scachesz; /* secondary cache size in MB */ - unsigned short cpu_scachespeed;/* secondary cache speed in MHz */ +typedef struct klcpu_s { /* CPU */ + klinfo_t cpu_info; + unsigned short cpu_prid; /* Processor PRID value */ + unsigned short cpu_fpirr; /* FPU IRR value */ + unsigned short cpu_speed; /* Speed in MHZ */ + unsigned short cpu_scachesz; /* secondary cache size in MB */ + unsigned short cpu_scachespeed;/* secondary cache speed in MHz */ } klcpu_t ; #define CPU_STRUCT_VERSION 2 typedef struct klhub_s { /* HUB */ - klinfo_t hub_info; - unsigned int hub_flags; /* PCFG_HUB_xxx flags */ + klinfo_t hub_info; + unsigned int hub_flags; /* PCFG_HUB_xxx flags */ klport_t hub_port; /* hub is connected to this */ nic_t hub_box_nic; /* nic of containing box */ klconf_off_t hub_mfg_nic; /* MFG NIC string */ @@ -612,36 +612,36 @@ typedef struct klhub_s { /* HUB */ } klhub_t ; typedef struct klhub_uart_s { /* HUB */ - klinfo_t hubuart_info; - unsigned int hubuart_flags; /* PCFG_HUB_xxx flags */ + klinfo_t hubuart_info; + unsigned int hubuart_flags; /* PCFG_HUB_xxx flags */ nic_t hubuart_box_nic; /* nic of containing box */ } klhub_uart_t ; -#define MEMORY_STRUCT_VERSION 2 +#define MEMORY_STRUCT_VERSION 2 typedef struct klmembnk_s { /* MEMORY BANK */ - klinfo_t membnk_info; - short membnk_memsz; /* Total memory in megabytes */ + klinfo_t membnk_info; + short membnk_memsz; /* Total memory in megabytes */ short membnk_dimm_select; /* bank to physical addr mapping*/ short membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */ short membnk_attr; } klmembnk_t ; #define KLCONFIG_MEMBNK_SIZE(_info, _bank) \ - ((_info)->membnk_bnksz[(_bank)]) + ((_info)->membnk_bnksz[(_bank)]) #define MEMBNK_PREMIUM 1 #define KLCONFIG_MEMBNK_PREMIUM(_info, _bank) \ - ((_info)->membnk_attr & (MEMBNK_PREMIUM << (_bank))) + ((_info)->membnk_attr & (MEMBNK_PREMIUM << (_bank))) #define MAX_SERIAL_NUM_SIZE 10 typedef struct klmod_serial_num_s { - klinfo_t snum_info; + klinfo_t snum_info; union { - char snum_str[MAX_SERIAL_NUM_SIZE]; - unsigned long long snum_int; + char snum_str[MAX_SERIAL_NUM_SIZE]; + unsigned long long snum_int; } snum; } klmod_serial_num_t; @@ -650,43 +650,43 @@ typedef struct klmod_serial_num_s { serial number struct as a component without losing compatibility between prom versions. */ -#define GET_SNUM_COMP(_l) ((klmod_serial_num_t *)\ +#define GET_SNUM_COMP(_l) ((klmod_serial_num_t *)\ KLCF_COMP(_l, _l->brd_numcompts)) #define MAX_XBOW_LINKS 16 -typedef struct klxbow_s { /* XBOW */ - klinfo_t xbow_info ; +typedef struct klxbow_s { /* XBOW */ + klinfo_t xbow_info ; klport_t xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */ - int xbow_master_hub_link; - /* type of brd connected+component struct ptr+flags */ + int xbow_master_hub_link; + /* type of brd connected+component struct ptr+flags */ } klxbow_t ; #define MAX_PCI_SLOTS 8 typedef struct klpci_device_s { s32 pci_device_id; /* 32 bits of vendor/device ID. */ - s32 pci_device_pad; /* 32 bits of padding. */ + s32 pci_device_pad; /* 32 bits of padding. */ } klpci_device_t; #define BRIDGE_STRUCT_VERSION 2 -typedef struct klbri_s { /* BRIDGE */ - klinfo_t bri_info ; - unsigned char bri_eprominfo ; /* IO6prom connected to bridge */ - unsigned char bri_bustype ; /* PCI/VME BUS bridge/GIO */ - pci_t pci_specific ; /* PCI Board config info */ +typedef struct klbri_s { /* BRIDGE */ + klinfo_t bri_info ; + unsigned char bri_eprominfo ; /* IO6prom connected to bridge */ + unsigned char bri_bustype ; /* PCI/VME BUS bridge/GIO */ + pci_t pci_specific ; /* PCI Board config info */ klpci_device_t bri_devices[MAX_PCI_DEVS] ; /* PCI IDs */ klconf_off_t bri_mfg_nic ; } klbri_t ; #define MAX_IOC3_TTY 2 -typedef struct klioc3_s { /* IOC3 */ - klinfo_t ioc3_info ; - unsigned char ioc3_ssram ; /* Info about ssram */ - unsigned char ioc3_nvram ; /* Info about nvram */ - klinfo_t ioc3_superio ; /* Info about superio */ +typedef struct klioc3_s { /* IOC3 */ + klinfo_t ioc3_info ; + unsigned char ioc3_ssram ; /* Info about ssram */ + unsigned char ioc3_nvram ; /* Info about nvram */ + klinfo_t ioc3_superio ; /* Info about superio */ klconf_off_t ioc3_tty_off ; klinfo_t ioc3_enet ; klconf_off_t ioc3_enet_off ; @@ -695,27 +695,27 @@ typedef struct klioc3_s { /* IOC3 */ #define MAX_VME_SLOTS 8 -typedef struct klvmeb_s { /* VME BRIDGE - PCI CTLR */ - klinfo_t vmeb_info ; +typedef struct klvmeb_s { /* VME BRIDGE - PCI CTLR */ + klinfo_t vmeb_info ; vmeb_t vmeb_specific ; - klconf_off_t vmeb_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */ + klconf_off_t vmeb_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */ } klvmeb_t ; -typedef struct klvmed_s { /* VME DEVICE - VME BOARD */ +typedef struct klvmed_s { /* VME DEVICE - VME BOARD */ klinfo_t vmed_info ; vmed_t vmed_specific ; - klconf_off_t vmed_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */ + klconf_off_t vmed_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */ } klvmed_t ; #define ROUTER_VECTOR_VERS 2 /* XXX - Don't we need the number of ports here?!? */ -typedef struct klrou_s { /* ROUTER */ - klinfo_t rou_info ; - unsigned int rou_flags ; /* PCFG_ROUTER_xxx flags */ - nic_t rou_box_nic ; /* nic of the containing module */ - klport_t rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */ - klconf_off_t rou_mfg_nic ; /* MFG NIC string */ +typedef struct klrou_s { /* ROUTER */ + klinfo_t rou_info ; + unsigned int rou_flags ; /* PCFG_ROUTER_xxx flags */ + nic_t rou_box_nic ; /* nic of the containing module */ + klport_t rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */ + klconf_off_t rou_mfg_nic ; /* MFG NIC string */ u64 rou_vector; /* vector from master node */ } klrou_t ; @@ -732,30 +732,30 @@ typedef struct klrou_s { /* ROUTER */ #define KLGFX_COOKIE 0x0c0de000 typedef struct klgfx_s { /* GRAPHICS Device */ - klinfo_t gfx_info; - klconf_off_t old_gndevs; /* for compatibility with older proms */ - klconf_off_t old_gdoff0; /* for compatibility with older proms */ + klinfo_t gfx_info; + klconf_off_t old_gndevs; /* for compatibility with older proms */ + klconf_off_t old_gdoff0; /* for compatibility with older proms */ unsigned int cookie; /* for compatibility with older proms */ unsigned int moduleslot; struct klgfx_s *gfx_next_pipe; graphics_t gfx_specific; - klconf_off_t pad0; /* for compatibility with older proms */ - klconf_off_t gfx_mfg_nic; + klconf_off_t pad0; /* for compatibility with older proms */ + klconf_off_t gfx_mfg_nic; } klgfx_t; typedef struct klxthd_s { - klinfo_t xthd_info ; - klconf_off_t xthd_mfg_nic ; /* MFG NIC string */ + klinfo_t xthd_info ; + klconf_off_t xthd_mfg_nic ; /* MFG NIC string */ } klxthd_t ; -typedef struct kltpu_s { /* TPU board */ - klinfo_t tpu_info ; - klconf_off_t tpu_mfg_nic ; /* MFG NIC string */ +typedef struct kltpu_s { /* TPU board */ + klinfo_t tpu_info ; + klconf_off_t tpu_mfg_nic ; /* MFG NIC string */ } kltpu_t ; -typedef struct klgsn_s { /* GSN board */ - klinfo_t gsn_info ; - klconf_off_t gsn_mfg_nic ; /* MFG NIC string */ +typedef struct klgsn_s { /* GSN board */ + klinfo_t gsn_info ; + klconf_off_t gsn_mfg_nic ; /* MFG NIC string */ } klgsn_t ; #define MAX_SCSI_DEVS 16 @@ -767,57 +767,57 @@ typedef struct klgsn_s { /* GSN board */ * that as the size to be klmalloced. */ -typedef struct klscsi_s { /* SCSI Controller */ - klinfo_t scsi_info ; - scsi_t scsi_specific ; - unsigned char scsi_numdevs ; +typedef struct klscsi_s { /* SCSI Controller */ + klinfo_t scsi_info ; + scsi_t scsi_specific ; + unsigned char scsi_numdevs ; klconf_off_t scsi_devinfo[MAX_SCSI_DEVS] ; } klscsi_t ; -typedef struct klscdev_s { /* SCSI device */ - klinfo_t scdev_info ; +typedef struct klscdev_s { /* SCSI device */ + klinfo_t scdev_info ; struct scsidisk_data *scdev_cfg ; /* driver fills up this */ } klscdev_t ; -typedef struct klttydev_s { /* TTY device */ - klinfo_t ttydev_info ; +typedef struct klttydev_s { /* TTY device */ + klinfo_t ttydev_info ; struct terminal_data *ttydev_cfg ; /* driver fills up this */ } klttydev_t ; -typedef struct klenetdev_s { /* ENET device */ - klinfo_t enetdev_info ; +typedef struct klenetdev_s { /* ENET device */ + klinfo_t enetdev_info ; struct net_data *enetdev_cfg ; /* driver fills up this */ } klenetdev_t ; -typedef struct klkbddev_s { /* KBD device */ - klinfo_t kbddev_info ; +typedef struct klkbddev_s { /* KBD device */ + klinfo_t kbddev_info ; struct keyboard_data *kbddev_cfg ; /* driver fills up this */ } klkbddev_t ; -typedef struct klmsdev_s { /* mouse device */ - klinfo_t msdev_info ; - void *msdev_cfg ; +typedef struct klmsdev_s { /* mouse device */ + klinfo_t msdev_info ; + void *msdev_cfg ; } klmsdev_t ; #define MAX_FDDI_DEVS 10 /* XXX Is this true */ -typedef struct klfddi_s { /* FDDI */ - klinfo_t fddi_info ; - fddi_t fddi_specific ; +typedef struct klfddi_s { /* FDDI */ + klinfo_t fddi_info ; + fddi_t fddi_specific ; klconf_off_t fddi_devinfo[MAX_FDDI_DEVS] ; } klfddi_t ; -typedef struct klmio_s { /* MIO */ - klinfo_t mio_info ; - mio_t mio_specific ; +typedef struct klmio_s { /* MIO */ + klinfo_t mio_info ; + mio_t mio_specific ; } klmio_t ; typedef union klcomp_s { klcpu_t kc_cpu; klhub_t kc_hub; - klmembnk_t kc_mem; - klxbow_t kc_xbow; + klmembnk_t kc_mem; + klxbow_t kc_xbow; klbri_t kc_bri; klioc3_t kc_ioc3; klvmeb_t kc_vmeb; @@ -831,11 +831,11 @@ typedef union klcomp_s { klmod_serial_num_t kc_snum ; } klcomp_t; -typedef union kldev_s { /* for device structure allocation */ +typedef union kldev_s { /* for device structure allocation */ klscdev_t kc_scsi_dev ; klttydev_t kc_tty_dev ; klenetdev_t kc_enet_dev ; - klkbddev_t kc_kbd_dev ; + klkbddev_t kc_kbd_dev ; } kldev_t ; /* Data structure interface routines. TBD */ diff --git a/arch/mips/include/asm/sn/kldir.h b/arch/mips/include/asm/sn/kldir.h index 1327e12e964..bfb3aec9453 100644 --- a/arch/mips/include/asm/sn/kldir.h +++ b/arch/mips/include/asm/sn/kldir.h @@ -16,8 +16,8 @@ * The kldir memory area resides at a fixed place in each node's memory and * provides pointers to most other IP27 memory areas. This allows us to * resize and/or relocate memory areas at a later time without breaking all - * firmware and kernels that use them. Indices in the array are - * permanently dedicated to areas listed below. Some memory areas (marked + * firmware and kernels that use them. Indices in the array are + * permanently dedicated to areas listed below. Some memory areas (marked * below) reside at a permanently fixed location, but are included in the * directory for completeness. */ @@ -28,98 +28,98 @@ * The upper portion of the memory map applies during boot * only and is overwritten by IRIX/SYMMON. * - * MEMORY MAP PER NODE + * MEMORY MAP PER NODE * - * 0x2000000 (32M) +-----------------------------------------+ - * | IO6 BUFFERS FOR FLASH ENET IOC3 | - * 0x1F80000 (31.5M) +-----------------------------------------+ - * | IO6 TEXT/DATA/BSS/stack | - * 0x1C00000 (30M) +-----------------------------------------+ - * | IO6 PROM DEBUG TEXT/DATA/BSS/stack | - * 0x0800000 (28M) +-----------------------------------------+ - * | IP27 PROM TEXT/DATA/BSS/stack | - * 0x1B00000 (27M) +-----------------------------------------+ - * | IP27 CFG | - * 0x1A00000 (26M) +-----------------------------------------+ - * | Graphics PROM | - * 0x1800000 (24M) +-----------------------------------------+ - * | 3rd Party PROM drivers | - * 0x1600000 (22M) +-----------------------------------------+ - * | | - * | Free | - * | | - * +-----------------------------------------+ - * | UNIX DEBUG Version | - * 0x190000 (2M--) +-----------------------------------------+ - * | SYMMON | - * | (For UNIX Debug only) | - * 0x34000 (208K) +-----------------------------------------+ - * | SYMMON STACK [NUM_CPU_PER_NODE] | - * | (For UNIX Debug only) | - * 0x25000 (148K) +-----------------------------------------+ - * | KLCONFIG - II (temp) | - * | | - * | ---------------------------- | - * | | - * | UNIX NON-DEBUG Version | - * 0x19000 (100K) +-----------------------------------------+ + * 0x2000000 (32M) +-----------------------------------------+ + * | IO6 BUFFERS FOR FLASH ENET IOC3 | + * 0x1F80000 (31.5M) +-----------------------------------------+ + * | IO6 TEXT/DATA/BSS/stack | + * 0x1C00000 (30M) +-----------------------------------------+ + * | IO6 PROM DEBUG TEXT/DATA/BSS/stack | + * 0x0800000 (28M) +-----------------------------------------+ + * | IP27 PROM TEXT/DATA/BSS/stack | + * 0x1B00000 (27M) +-----------------------------------------+ + * | IP27 CFG | + * 0x1A00000 (26M) +-----------------------------------------+ + * | Graphics PROM | + * 0x1800000 (24M) +-----------------------------------------+ + * | 3rd Party PROM drivers | + * 0x1600000 (22M) +-----------------------------------------+ + * | | + * | Free | + * | | + * +-----------------------------------------+ + * | UNIX DEBUG Version | + * 0x190000 (2M--) +-----------------------------------------+ + * | SYMMON | + * | (For UNIX Debug only) | + * 0x34000 (208K) +-----------------------------------------+ + * | SYMMON STACK [NUM_CPU_PER_NODE] | + * | (For UNIX Debug only) | + * 0x25000 (148K) +-----------------------------------------+ + * | KLCONFIG - II (temp) | + * | | + * | ---------------------------- | + * | | + * | UNIX NON-DEBUG Version | + * 0x19000 (100K) +-----------------------------------------+ * * * The lower portion of the memory map contains information that is * permanent and is used by the IP27PROM, IO6PROM and IRIX. * - * 0x19000 (100K) +-----------------------------------------+ - * | | - * | PI Error Spools (32K) | - * | | - * 0x12000 (72K) +-----------------------------------------+ - * | Unused | - * 0x11c00 (71K) +-----------------------------------------+ - * | CPU 1 NMI Eframe area | - * 0x11a00 (70.5K) +-----------------------------------------+ - * | CPU 0 NMI Eframe area | - * 0x11800 (70K) +-----------------------------------------+ - * | CPU 1 NMI Register save area | - * 0x11600 (69.5K) +-----------------------------------------+ - * | CPU 0 NMI Register save area | - * 0x11400 (69K) +-----------------------------------------+ - * | GDA (1k) | - * 0x11000 (68K) +-----------------------------------------+ - * | Early cache Exception stack | - * | and/or | - * | kernel/io6prom nmi registers | + * 0x19000 (100K) +-----------------------------------------+ + * | | + * | PI Error Spools (32K) | + * | | + * 0x12000 (72K) +-----------------------------------------+ + * | Unused | + * 0x11c00 (71K) +-----------------------------------------+ + * | CPU 1 NMI Eframe area | + * 0x11a00 (70.5K) +-----------------------------------------+ + * | CPU 0 NMI Eframe area | + * 0x11800 (70K) +-----------------------------------------+ + * | CPU 1 NMI Register save area | + * 0x11600 (69.5K) +-----------------------------------------+ + * | CPU 0 NMI Register save area | + * 0x11400 (69K) +-----------------------------------------+ + * | GDA (1k) | + * 0x11000 (68K) +-----------------------------------------+ + * | Early cache Exception stack | + * | and/or | + * | kernel/io6prom nmi registers | * 0x10800 (66k) +-----------------------------------------+ - * | cache error eframe | - * 0x10400 (65K) +-----------------------------------------+ - * | Exception Handlers (UALIAS copy) | - * 0x10000 (64K) +-----------------------------------------+ - * | | - * | | - * | KLCONFIG - I (permanent) (48K) | - * | | - * | | - * | | - * 0x4000 (16K) +-----------------------------------------+ - * | NMI Handler (Protected Page) | - * 0x3000 (12K) +-----------------------------------------+ - * | ARCS PVECTORS (master node only) | - * 0x2c00 (11K) +-----------------------------------------+ - * | ARCS TVECTORS (master node only) | - * 0x2800 (10K) +-----------------------------------------+ - * | LAUNCH [NUM_CPU] | - * 0x2400 (9K) +-----------------------------------------+ - * | Low memory directory (KLDIR) | - * 0x2000 (8K) +-----------------------------------------+ - * | ARCS SPB (1K) | - * 0x1000 (4K) +-----------------------------------------+ - * | Early cache Exception stack | - * | and/or | - * | kernel/io6prom nmi registers | - * 0x800 (2k) +-----------------------------------------+ - * | cache error eframe | - * 0x400 (1K) +-----------------------------------------+ - * | Exception Handlers | - * 0x0 (0K) +-----------------------------------------+ + * | cache error eframe | + * 0x10400 (65K) +-----------------------------------------+ + * | Exception Handlers (UALIAS copy) | + * 0x10000 (64K) +-----------------------------------------+ + * | | + * | | + * | KLCONFIG - I (permanent) (48K) | + * | | + * | | + * | | + * 0x4000 (16K) +-----------------------------------------+ + * | NMI Handler (Protected Page) | + * 0x3000 (12K) +-----------------------------------------+ + * | ARCS PVECTORS (master node only) | + * 0x2c00 (11K) +-----------------------------------------+ + * | ARCS TVECTORS (master node only) | + * 0x2800 (10K) +-----------------------------------------+ + * | LAUNCH [NUM_CPU] | + * 0x2400 (9K) +-----------------------------------------+ + * | Low memory directory (KLDIR) | + * 0x2000 (8K) +-----------------------------------------+ + * | ARCS SPB (1K) | + * 0x1000 (4K) +-----------------------------------------+ + * | Early cache Exception stack | + * | and/or | + * | kernel/io6prom nmi registers | + * 0x800 (2k) +-----------------------------------------+ + * | cache error eframe | + * 0x400 (1K) +-----------------------------------------+ + * | Exception Handlers | + * 0x0 (0K) +-----------------------------------------+ */ #ifdef __ASSEMBLY__ @@ -202,13 +202,13 @@ #ifndef __ASSEMBLY__ typedef struct kldir_ent_s { - u64 magic; /* Indicates validity of entry */ + u64 magic; /* Indicates validity of entry */ off_t offset; /* Offset from start of node space */ unsigned long pointer; /* Pointer to area in some cases */ - size_t size; /* Size in bytes */ + size_t size; /* Size in bytes */ u64 count; /* Repeat count if array, 1 if not */ - size_t stride; /* Stride if array, 0 if not */ - char rsvd[16]; /* Pad entry to 0x40 bytes */ + size_t stride; /* Stride if array, 0 if not */ + char rsvd[16]; /* Pad entry to 0x40 bytes */ /* NOTE: These 16 bytes are used in the Partition KLDIR entry to store partition info. Refer to klpart.h for this. */ } kldir_ent_t; diff --git a/arch/mips/include/asm/sn/launch.h b/arch/mips/include/asm/sn/launch.h index b7c2226312c..04226d8d30c 100644 --- a/arch/mips/include/asm/sn/launch.h +++ b/arch/mips/include/asm/sn/launch.h @@ -19,7 +19,7 @@ * * The master stores launch parameters in the launch structure * corresponding to a target processor that is in a slave loop, then sends - * an interrupt to the slave processor. The slave calls the desired + * an interrupt to the slave processor. The slave calls the desired * function, then returns to the slave loop. The master may poll or wait * for the slaves to finish. * @@ -33,7 +33,7 @@ #define LAUNCH_PADSZ 0xa0 #endif -#define LAUNCH_OFF_MAGIC 0x00 /* Struct offsets for assembly */ +#define LAUNCH_OFF_MAGIC 0x00 /* Struct offsets for assembly */ #define LAUNCH_OFF_BUSY 0x08 #define LAUNCH_OFF_CALL 0x10 #define LAUNCH_OFF_CALLC 0x18 @@ -44,7 +44,7 @@ #define LAUNCH_OFF_BEVNORMAL 0x40 #define LAUNCH_OFF_BEVECC 0x48 -#define LAUNCH_STATE_DONE 0 /* Return value of LAUNCH_POLL */ +#define LAUNCH_STATE_DONE 0 /* Return value of LAUNCH_POLL */ #define LAUNCH_STATE_SENT 1 #define LAUNCH_STATE_RECD 2 @@ -65,16 +65,16 @@ typedef int launch_state_t; typedef void (*launch_proc_t)(u64 call_parm); typedef struct launch_s { - volatile u64 magic; /* Magic number */ - volatile u64 busy; /* Slave currently active */ + volatile u64 magic; /* Magic number */ + volatile u64 busy; /* Slave currently active */ volatile launch_proc_t call_addr; /* Func. for slave to call */ volatile u64 call_addr_c; /* 1's complement of call_addr*/ volatile u64 call_parm; /* Single parm passed to call*/ volatile void *stack_addr; /* Stack pointer for slave function */ volatile void *gp_addr; /* Global pointer for slave func. */ - volatile char *bevutlb;/* Address of bev utlb ex handler */ - volatile char *bevnormal;/*Address of bev normal ex handler */ - volatile char *bevecc;/* Address of bev cache err handler */ + volatile char *bevutlb;/* Address of bev utlb ex handler */ + volatile char *bevnormal;/*Address of bev normal ex handler */ + volatile char *bevecc;/* Address of bev cache err handler */ volatile char pad[160]; /* Pad to LAUNCH_SIZEOF */ } launch_t; diff --git a/arch/mips/include/asm/sn/mapped_kernel.h b/arch/mips/include/asm/sn/mapped_kernel.h index 721496a0bb9..401f3b0eee1 100644 --- a/arch/mips/include/asm/sn/mapped_kernel.h +++ b/arch/mips/include/asm/sn/mapped_kernel.h @@ -48,7 +48,7 @@ #endif /* CONFIG_MAPPED_KERNEL */ -#define MAPPED_KERN_RO_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RO_TO_PHYS(x)) -#define MAPPED_KERN_RW_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RW_TO_PHYS(x)) +#define MAPPED_KERN_RO_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RO_TO_PHYS(x)) +#define MAPPED_KERN_RW_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RW_TO_PHYS(x)) #endif /* __ASM_SN_MAPPED_KERNEL_H */ diff --git a/arch/mips/include/asm/sn/nmi.h b/arch/mips/include/asm/sn/nmi.h index 1af49897d4e..12ac210f12a 100644 --- a/arch/mips/include/asm/sn/nmi.h +++ b/arch/mips/include/asm/sn/nmi.h @@ -19,7 +19,7 @@ * * The master stores launch parameters in the launch structure * corresponding to a target processor that is in a slave loop, then sends - * an interrupt to the slave processor. The slave calls the desired + * an interrupt to the slave processor. The slave calls the desired * function, followed by an optional rendezvous function, then returns to * the slave loop. The master does not wait for the slaves before * returning. @@ -31,7 +31,7 @@ #define NMI_MAGIC 0x48414d4d455201 #define NMI_SIZEOF 0x40 -#define NMI_OFF_MAGIC 0x00 /* Struct offsets for assembly */ +#define NMI_OFF_MAGIC 0x00 /* Struct offsets for assembly */ #define NMI_OFF_FLAGS 0x08 #define NMI_OFF_CALL 0x10 #define NMI_OFF_CALLC 0x18 @@ -53,8 +53,8 @@ typedef struct nmi_s { volatile unsigned long magic; /* Magic number */ volatile unsigned long flags; /* Combination of flags above */ - volatile void *call_addr; /* Routine for slave to call */ - volatile void *call_addr_c; /* 1's complement of address */ + volatile void *call_addr; /* Routine for slave to call */ + volatile void *call_addr_c; /* 1's complement of address */ volatile void *call_parm; /* Single parm passed to call */ volatile unsigned long gmaster; /* Flag true only on global master*/ } nmi_t; diff --git a/arch/mips/include/asm/sn/sn0/addrs.h b/arch/mips/include/asm/sn/sn0/addrs.h index b06190093bb..6b53070f400 100644 --- a/arch/mips/include/asm/sn/sn0/addrs.h +++ b/arch/mips/include/asm/sn/sn0/addrs.h @@ -29,7 +29,7 @@ * chapter of the Hub specification. * * NOTE: This header file is included both by C and by assembler source - * files. Please bracket any language-dependent definitions + * files. Please bracket any language-dependent definitions * appropriately. */ @@ -102,14 +102,14 @@ #define BWIN_INDEX_BITS 3 #define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS) -#define BWIN_SIZEMASK (BWIN_SIZE - 1) -#define BWIN_WIDGET_MASK 0x7 +#define BWIN_SIZEMASK (BWIN_SIZE - 1) +#define BWIN_WIDGET_MASK 0x7 #define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) -#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ +#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ (UINT64_CAST(bigwin) << BWIN_SIZE_BITS)) -#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) -#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) +#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) +#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) /* * Verify if addr belongs to large window address of node with "nasid" * @@ -120,7 +120,7 @@ * */ -#define NODE_BWIN_ADDR(nasid, addr) \ +#define NODE_BWIN_ADDR(nasid, addr) \ (((addr) >= NODE_BWIN_BASE0(nasid)) && \ ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \ BWIN_SIZE))) @@ -129,7 +129,7 @@ * The following define the major position-independent aliases used * in SN0. * CALIAS -- Varies in size, points to the first n bytes of memory - * on the reader's node. + * on the reader's node. */ #define CALIAS_BASE CAC_BASE @@ -146,7 +146,7 @@ #ifndef __ASSEMBLY__ #define KERN_NMI_ADDR(nasid, slice) \ - TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + \ + TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + \ (IP27_NMI_KREGS_CPU_SIZE * (slice))) #endif /* !__ASSEMBLY__ */ @@ -203,7 +203,7 @@ #define IO6PROM_BASE PHYS_TO_K0(0x01c00000) #define IO6PROM_SIZE 0x400000 -#define IO6PROM_BASE_MAPPED (UNCAC_BASE | 0x11c00000) +#define IO6PROM_BASE_MAPPED (UNCAC_BASE | 0x11c00000) #define IO6DPROM_BASE PHYS_TO_K0(0x01c00000) #define IO6DPROM_SIZE 0x200000 diff --git a/arch/mips/include/asm/sn/sn0/arch.h b/arch/mips/include/asm/sn/sn0/arch.h index f734f2007f2..425a67e6a94 100644 --- a/arch/mips/include/asm/sn/sn0/arch.h +++ b/arch/mips/include/asm/sn/sn0/arch.h @@ -12,23 +12,23 @@ #define _ASM_SN_SN0_ARCH_H -#ifndef SN0XXL /* 128 cpu SMP max */ +#ifndef SN0XXL /* 128 cpu SMP max */ /* * This is the maximum number of nodes that can be part of a kernel. * Effectively, it's the maximum number of compact node ids (cnodeid_t). */ -#define MAX_COMPACT_NODES 64 +#define MAX_COMPACT_NODES 64 /* * MAXCPUS refers to the maximum number of CPUs in a single kernel. * This is not necessarily the same as MAXNODES * CPUS_PER_NODE */ -#define MAXCPUS 128 +#define MAXCPUS 128 #else /* SN0XXL system */ -#define MAX_COMPACT_NODES 128 -#define MAXCPUS 256 +#define MAX_COMPACT_NODES 128 +#define MAXCPUS 256 #endif /* SN0XXL */ @@ -41,9 +41,9 @@ /* * MAX_REGIONS refers to the maximum number of hardware partitioned regions. */ -#define MAX_REGIONS 64 -#define MAX_NONPREMIUM_REGIONS 16 -#define MAX_PREMIUM_REGIONS MAX_REGIONS +#define MAX_REGIONS 64 +#define MAX_NONPREMIUM_REGIONS 16 +#define MAX_PREMIUM_REGIONS MAX_REGIONS /* * MAX_PARITIONS refers to the maximum number of logically defined @@ -57,12 +57,12 @@ * Slot constants for SN0 */ #ifdef CONFIG_SGI_SN_N_MODE -#define MAX_MEM_SLOTS 16 /* max slots per node */ +#define MAX_MEM_SLOTS 16 /* max slots per node */ #else /* !CONFIG_SGI_SN_N_MODE, assume CONFIG_SGI_SN_M_MODE */ -#define MAX_MEM_SLOTS 32 /* max slots per node */ +#define MAX_MEM_SLOTS 32 /* max slots per node */ #endif /* CONFIG_SGI_SN_M_MODE */ -#define SLOT_SHIFT (27) +#define SLOT_SHIFT (27) #define SLOT_MIN_MEM_SIZE (32*1024*1024) #define CPUS_PER_NODE 2 /* CPUs on a single hub */ diff --git a/arch/mips/include/asm/sn/sn0/hub.h b/arch/mips/include/asm/sn/sn0/hub.h index 3e228f8e796..d78dd76d5dc 100644 --- a/arch/mips/include/asm/sn/sn0/hub.h +++ b/arch/mips/include/asm/sn/sn0/hub.h @@ -19,8 +19,8 @@ #define HUB_REV_2_0 2 #define HUB_REV_2_1 3 #define HUB_REV_2_2 4 -#define HUB_REV_2_3 5 -#define HUB_REV_2_4 6 +#define HUB_REV_2_3 5 +#define HUB_REV_2_4 6 #define MAX_HUB_PATH 80 @@ -32,9 +32,9 @@ //#include <asm/sn/sn0/hubcore.h> /* Translation of uncached attributes */ -#define UATTR_HSPEC 0 -#define UATTR_IO 1 -#define UATTR_MSPEC 2 -#define UATTR_UNCAC 3 +#define UATTR_HSPEC 0 +#define UATTR_IO 1 +#define UATTR_MSPEC 2 +#define UATTR_UNCAC 3 #endif /* _ASM_SN_SN0_HUB_H */ diff --git a/arch/mips/include/asm/sn/sn0/hubio.h b/arch/mips/include/asm/sn/sn0/hubio.h index 46286d8302a..5998b13e976 100644 --- a/arch/mips/include/asm/sn/sn0/hubio.h +++ b/arch/mips/include/asm/sn/sn0/hubio.h @@ -8,8 +8,8 @@ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. * Copyright (C) 1999 by Ralf Baechle */ -#ifndef _ASM_SGI_SN_SN0_HUBIO_H -#define _ASM_SGI_SN_SN0_HUBIO_H +#ifndef _ASM_SGI_SN_SN0_HUBIO_H +#define _ASM_SGI_SN_SN0_HUBIO_H /* * Hub I/O interface registers @@ -22,7 +22,7 @@ * Slightly friendlier names for some common registers. * The hardware definitions follow. */ -#define IIO_WIDGET IIO_WID /* Widget identification */ +#define IIO_WIDGET IIO_WID /* Widget identification */ #define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */ #define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */ #define IIO_WIDGET_TOUT IIO_WRTO /* Widget request timeout */ @@ -37,21 +37,21 @@ #define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/ #define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */ #define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */ -#define IIO_BTE_CRB_CNT IIO_IBCN /* IO BTE CRB count */ +#define IIO_BTE_CRB_CNT IIO_IBCN /* IO BTE CRB count */ #define IIO_LLP_CSR_IS_UP 0x00002000 -#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000 -#define IIO_LLP_CSR_LLP_STAT_SHFT 12 +#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000 +#define IIO_LLP_CSR_LLP_STAT_SHFT 12 /* key to IIO_PROTECT_OVRRD */ #define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */ /* BTE register names */ #define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */ -#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */ +#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */ #define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */ #define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */ -#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */ +#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */ #define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */ #define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */ #define IIO_BTE_OFF_1 IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */ @@ -83,11 +83,11 @@ #define IIO_WSTAT 0x400008 /* Widget status */ #define IIO_WCR 0x400020 /* Widget control */ -#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */ -#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */ -#define IIO_WSTAT_TXRETRY_MASK (0x7F) -#define IIO_WSTAT_TXRETRY_SHFT (16) -#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \ +#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */ +#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */ +#define IIO_WSTAT_TXRETRY_MASK (0x7F) +#define IIO_WSTAT_TXRETRY_SHFT (16) +#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \ IIO_WSTAT_TXRETRY_MASK) #define IIO_ILAPR 0x400100 /* Local Access Protection */ @@ -130,12 +130,12 @@ #define IIO_IGFX_INIT(widget, node, cpu, valid) (\ (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \ (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \ - (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) | \ - (((valid) & IIO_IGFX_VLD_MASK) << IIO_IGFX_VLD_SHIFT) ) + (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) | \ + (((valid) & IIO_IGFX_VLD_MASK) << IIO_IGFX_VLD_SHIFT) ) /* Scratch registers (not all bits available) */ #define IIO_SCRATCH_REG0 0x400150 -#define IIO_SCRATCH_REG1 0x400158 +#define IIO_SCRATCH_REG1 0x400158 #define IIO_SCRATCH_MASK 0x0000000f00f11fff #define IIO_SCRATCH_BIT0_0 0x0000000800000000 @@ -174,43 +174,43 @@ typedef union hubii_wid_u { u64 wid_reg_value; struct { - u64 wid_rsvd: 32, /* unused */ + u64 wid_rsvd: 32, /* unused */ wid_rev_num: 4, /* revision number */ wid_part_num: 16, /* the widget type: hub=c101 */ wid_mfg_num: 11, /* Manufacturer id (IBM) */ wid_rsvd1: 1; /* Reserved */ - } wid_fields_s; + } wid_fields_s; } hubii_wid_t; typedef union hubii_wcr_u { u64 wcr_reg_value; struct { - u64 wcr_rsvd: 41, /* unused */ + u64 wcr_rsvd: 41, /* unused */ wcr_e_thresh: 5, /* elasticity threshold */ wcr_dir_con: 1, /* widget direct connect */ wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */ wcr_xbar_crd: 3, /* LLP crossbar credit */ wcr_rsvd1: 8, /* Reserved */ - wcr_tag_mode: 1, /* Tag mode */ + wcr_tag_mode: 1, /* Tag mode */ wcr_widget_id: 4; /* LLP crossbar credit */ - } wcr_fields_s; + } wcr_fields_s; } hubii_wcr_t; -#define iwcr_dir_con wcr_fields_s.wcr_dir_con +#define iwcr_dir_con wcr_fields_s.wcr_dir_con typedef union hubii_wstat_u { - u64 reg_value; + u64 reg_value; struct { u64 rsvd1: 31, crazy: 1, /* Crazy bit */ rsvd2: 8, - llp_tx_cnt: 8, /* LLP Xmit retry counter */ + llp_tx_cnt: 8, /* LLP Xmit retry counter */ rsvd3: 6, tx_max_rtry: 1, /* LLP Retry Timeout Signal */ rsvd4: 2, xt_tail_to: 1, /* Xtalk Tail Timeout */ - xt_crd_to: 1, /* Xtalk Credit Timeout */ + xt_crd_to: 1, /* Xtalk Credit Timeout */ pending: 4; /* Pending Requests */ } wstat_fields_s; } hubii_wstat_t; @@ -219,50 +219,50 @@ typedef union hubii_wstat_u { typedef union hubii_ilcsr_u { u64 icsr_reg_value; struct { - u64 icsr_rsvd: 22, /* unused */ - icsr_max_burst: 10, /* max burst */ - icsr_rsvd4: 6, /* reserved */ - icsr_max_retry: 10, /* max retry */ - icsr_rsvd3: 2, /* reserved */ - icsr_lnk_stat: 2, /* link status */ - icsr_bm8: 1, /* Bit mode 8 */ - icsr_llp_en: 1, /* LLP enable bit */ - icsr_rsvd2: 1, /* reserver */ - icsr_wrm_reset: 1, /* Warm reset bit */ + u64 icsr_rsvd: 22, /* unused */ + icsr_max_burst: 10, /* max burst */ + icsr_rsvd4: 6, /* reserved */ + icsr_max_retry: 10, /* max retry */ + icsr_rsvd3: 2, /* reserved */ + icsr_lnk_stat: 2, /* link status */ + icsr_bm8: 1, /* Bit mode 8 */ + icsr_llp_en: 1, /* LLP enable bit */ + icsr_rsvd2: 1, /* reserver */ + icsr_wrm_reset: 1, /* Warm reset bit */ icsr_rsvd1: 2, /* Data ready offset */ - icsr_null_to: 6; /* Null timeout */ + icsr_null_to: 6; /* Null timeout */ - } icsr_fields_s; + } icsr_fields_s; } hubii_ilcsr_t; typedef union hubii_iowa_u { u64 iowa_reg_value; struct { - u64 iowa_rsvd: 48, /* unused */ + u64 iowa_rsvd: 48, /* unused */ iowa_wxoac: 8, /* xtalk widget access bits */ iowa_rsvd1: 7, /* xtalk widget access bits */ iowa_w0oac: 1; /* xtalk widget access bits */ - } iowa_fields_s; + } iowa_fields_s; } hubii_iowa_t; typedef union hubii_iiwa_u { u64 iiwa_reg_value; struct { - u64 iiwa_rsvd: 48, /* unused */ + u64 iiwa_rsvd: 48, /* unused */ iiwa_wxiac: 8, /* hub wid access bits */ iiwa_rsvd1: 7, /* reserved */ iiwa_w0iac: 1; /* hub wid0 access */ - } iiwa_fields_s; + } iiwa_fields_s; } hubii_iiwa_t; typedef union hubii_illr_u { u64 illr_reg_value; struct { - u64 illr_rsvd: 32, /* unused */ + u64 illr_rsvd: 32, /* unused */ illr_cb_cnt: 16, /* checkbit error count */ illr_sn_cnt: 16; /* sequence number count */ - } illr_fields_s; + } illr_fields_s; } hubii_illr_t; /* The structures below are defined to extract and modify the ii @@ -273,7 +273,7 @@ performance registers */ typedef union io_perf_sel { u64 perf_sel_reg; struct { - u64 perf_rsvd : 48, + u64 perf_rsvd : 48, perf_icct : 8, perf_ippr1 : 4, perf_ippr0 : 4; @@ -301,7 +301,7 @@ typedef union io_perf_cnt { #define IIO_LLP_SN_MAX 0xffff /* IO PRB Entries */ -#define IIO_NUM_IPRBS (9) +#define IIO_NUM_IPRBS (9) #define IIO_IOPRB_0 0x400198 /* PRB entry 0 */ #define IIO_IOPRB_8 0x4001a0 /* PRB entry 8 */ #define IIO_IOPRB_9 0x4001a8 /* PRB entry 9 */ @@ -318,21 +318,21 @@ typedef union io_perf_cnt { #define IIO_IMEM 0x4001e8 /* Miscellaneous Enable Mask */ #define IIO_IXTT 0x4001f0 /* Crosstalk tail timeout */ #define IIO_IECLR 0x4001f8 /* IO error clear */ -#define IIO_IBCN 0x400200 /* IO BTE CRB count */ +#define IIO_IBCN 0x400200 /* IO BTE CRB count */ /* * IIO_IMEM Register fields. */ -#define IIO_IMEM_W0ESD 0x1 /* Widget 0 shut down due to error */ -#define IIO_IMEM_B0ESD (1 << 4) /* BTE 0 shut down due to error */ -#define IIO_IMEM_B1ESD (1 << 8) /* BTE 1 Shut down due to error */ +#define IIO_IMEM_W0ESD 0x1 /* Widget 0 shut down due to error */ +#define IIO_IMEM_B0ESD (1 << 4) /* BTE 0 shut down due to error */ +#define IIO_IMEM_B1ESD (1 << 8) /* BTE 1 Shut down due to error */ /* PIO Read address Table Entries */ #define IIO_IPCA 0x400300 /* PRB Counter adjust */ #define IIO_NUM_PRTES 8 /* Total number of PRB table entries */ #define IIO_PRTE_0 0x400308 /* PIO Read address table entry 0 */ #define IIO_PRTE(_x) (IIO_PRTE_0 + (8 * (_x))) -#define IIO_WIDPRTE(x) IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */ +#define IIO_WIDPRTE(x) IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */ #define IIO_IPDR 0x400388 /* PIO table entry deallocation */ #define IIO_ICDR 0x400390 /* CRB Entry Deallocation */ #define IIO_IFDR 0x400398 /* IOQ FIFO Depth */ @@ -369,35 +369,35 @@ typedef union io_perf_cnt { /* * IIO PIO Deallocation register field masks : (IIO_IPDR) */ -#define IIO_IPDR_PND (1 << 4) +#define IIO_IPDR_PND (1 << 4) /* * IIO CRB deallocation register field masks: (IIO_ICDR) */ -#define IIO_ICDR_PND (1 << 4) +#define IIO_ICDR_PND (1 << 4) /* * IIO CRB control register Fields: IIO_ICCR */ -#define IIO_ICCR_PENDING (0x10000) -#define IIO_ICCR_CMD_MASK (0xFF) -#define IIO_ICCR_CMD_SHFT (7) -#define IIO_ICCR_CMD_NOP (0x0) /* No Op */ -#define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */ -#define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */ -#define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory +#define IIO_ICCR_PENDING (0x10000) +#define IIO_ICCR_CMD_MASK (0xFF) +#define IIO_ICCR_CMD_SHFT (7) +#define IIO_ICCR_CMD_NOP (0x0) /* No Op */ +#define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */ +#define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */ +#define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory * via a WB */ -#define IIO_ICCR_CMD_FLUSH (0x800) +#define IIO_ICCR_CMD_FLUSH (0x800) /* * CRB manipulation macros * The CRB macros are slightly complicated, since there are up to - * four registers associated with each CRB entry. + * four registers associated with each CRB entry. */ #define IIO_NUM_CRBS 15 /* Number of CRBs */ -#define IIO_NUM_NORMAL_CRBS 12 /* Number of regular CRB entries */ -#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */ +#define IIO_NUM_NORMAL_CRBS 12 /* Number of regular CRB entries */ +#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */ #define IIO_ICRB_OFFSET 8 #define IIO_ICRB_0 0x400400 /* XXX - This is now tuneable: @@ -405,9 +405,9 @@ typedef union io_perf_cnt { */ #define IIO_ICRB_A(_x) (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x))) -#define IIO_ICRB_B(_x) (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET) +#define IIO_ICRB_B(_x) (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET) #define IIO_ICRB_C(_x) (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET) -#define IIO_ICRB_D(_x) (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET) +#define IIO_ICRB_D(_x) (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET) /* XXX - IBUE register coming for Hub 2 */ @@ -444,16 +444,16 @@ typedef union io_perf_cnt { typedef union icrba_u { u64 reg_value; struct { - u64 resvd: 6, + u64 resvd: 6, stall_bte0: 1, /* Stall BTE 0 */ stall_bte1: 1, /* Stall BTE 1 */ error: 1, /* CRB has an error */ - ecode: 3, /* Error Code */ + ecode: 3, /* Error Code */ lnetuce: 1, /* SN0net Uncorrectable error */ - mark: 1, /* CRB Has been marked */ + mark: 1, /* CRB Has been marked */ xerr: 1, /* Error bit set in xtalk header */ sidn: 4, /* SIDN field from xtalk */ - tnum: 5, /* TNUM field in xtalk */ + tnum: 5, /* TNUM field in xtalk */ addr: 38, /* Address of request */ valid: 1, /* Valid status */ iow: 1; /* IO Write operation */ @@ -467,15 +467,15 @@ typedef union h1_icrba_u { u64 reg_value; struct { - u64 resvd: 6, - unused: 1, /* Unused but RW!! */ + u64 resvd: 6, + unused: 1, /* Unused but RW!! */ error: 1, /* CRB has an error */ - ecode: 4, /* Error Code */ + ecode: 4, /* Error Code */ lnetuce: 1, /* SN0net Uncorrectable error */ - mark: 1, /* CRB Has been marked */ + mark: 1, /* CRB Has been marked */ xerr: 1, /* Error bit set in xtalk header */ sidn: 4, /* SIDN field from xtalk */ - tnum: 5, /* TNUM field in xtalk */ + tnum: 5, /* TNUM field in xtalk */ addr: 38, /* Address of request */ valid: 1, /* Valid status */ iow: 1; /* IO Write operation */ @@ -488,21 +488,21 @@ typedef union h1_icrba_u { #endif /* !__ASSEMBLY__ */ -#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */ +#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */ /* * values for "ecode" field */ -#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */ -#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */ -#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access +#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */ +#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */ +#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access * e.g. WINV to a Read only line. */ -#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */ -#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */ -#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */ -#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */ -#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */ +#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */ +#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */ +#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */ +#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */ +#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */ @@ -513,10 +513,10 @@ typedef union h1_icrba_u { typedef union icrbb_u { u64 reg_value; struct { - u64 rsvd1: 5, - btenum: 1, /* BTE to which entry belongs to */ - cohtrans: 1, /* Coherent transaction */ - xtsize: 2, /* Xtalk operation size + u64 rsvd1: 5, + btenum: 1, /* BTE to which entry belongs to */ + cohtrans: 1, /* Coherent transaction */ + xtsize: 2, /* Xtalk operation size * 0: Double Word * 1: 32 Bytes. * 2: 128 Bytes, @@ -526,11 +526,11 @@ typedef union icrbb_u { srcinit: 2, /* Source Initiator: * See below for field values. */ - useold: 1, /* Use OLD command for processing */ + useold: 1, /* Use OLD command for processing */ imsgtype: 2, /* Incoming message type * see below for field values */ - imsg: 8, /* Incoming message */ + imsg: 8, /* Incoming message */ initator: 3, /* Initiator of original request * See below for field values. */ @@ -538,12 +538,12 @@ typedef union icrbb_u { * See below for field values. */ rsvd2: 7, - ackcnt: 11, /* Invalidate ack count */ + ackcnt: 11, /* Invalidate ack count */ resp: 1, /* data response given to processor */ - ack: 1, /* indicates data ack received */ + ack: 1, /* indicates data ack received */ hold: 1, /* entry is gathering inval acks */ wb_pend:1, /* waiting for writeback to complete */ - intvn: 1, /* Intervention */ + intvn: 1, /* Intervention */ stall_ib: 1, /* Stall Ibuf (from crosstalk) */ stall_intr: 1; /* Stall internal interrupts */ } icrbb_field_s; @@ -556,9 +556,9 @@ typedef union h1_icrbb_u { u64 reg_value; struct { u64 rsvd1: 5, - btenum: 1, /* BTE to which entry belongs to */ - cohtrans: 1, /* Coherent transaction */ - xtsize: 2, /* Xtalk operation size + btenum: 1, /* BTE to which entry belongs to */ + cohtrans: 1, /* Coherent transaction */ + xtsize: 2, /* Xtalk operation size * 0: Double Word * 1: 32 Bytes. * 2: 128 Bytes, @@ -568,99 +568,99 @@ typedef union h1_icrbb_u { srcinit: 2, /* Source Initiator: * See below for field values. */ - useold: 1, /* Use OLD command for processing */ + useold: 1, /* Use OLD command for processing */ imsgtype: 2, /* Incoming message type * see below for field values */ - imsg: 8, /* Incoming message */ + imsg: 8, /* Incoming message */ initator: 3, /* Initiator of original request * See below for field values. */ - rsvd2: 1, + rsvd2: 1, pcache: 1, /* entry belongs to partial cache */ reqtype: 5, /* Identifies type of request * See below for field values. */ - stl_ib: 1, /* stall Ibus coming from xtalk */ + stl_ib: 1, /* stall Ibus coming from xtalk */ stl_intr: 1, /* Stall internal interrupts */ - stl_bte0: 1, /* Stall BTE 0 */ + stl_bte0: 1, /* Stall BTE 0 */ stl_bte1: 1, /* Stall BTE 1 */ - intrvn: 1, /* Req was target of intervention */ - ackcnt: 11, /* Invalidate ack count */ + intrvn: 1, /* Req was target of intervention */ + ackcnt: 11, /* Invalidate ack count */ resp: 1, /* data response given to processor */ - ack: 1, /* indicates data ack received */ + ack: 1, /* indicates data ack received */ hold: 1, /* entry is gathering inval acks */ wb_pend:1, /* waiting for writeback to complete */ - sleep: 1, /* xtalk req sleeping till IO-sync */ + sleep: 1, /* xtalk req sleeping till IO-sync */ pnd_reply: 1, /* replies not issed due to IOQ full */ pnd_req: 1; /* reqs not issued due to IOQ full */ } h1_icrbb_field_s; } h1_icrbb_t; -#define b_imsgtype icrbb_field_s.imsgtype -#define b_btenum icrbb_field_s.btenum -#define b_cohtrans icrbb_field_s.cohtrans -#define b_xtsize icrbb_field_s.xtsize -#define b_srcnode icrbb_field_s.srcnode -#define b_srcinit icrbb_field_s.srcinit -#define b_imsgtype icrbb_field_s.imsgtype -#define b_imsg icrbb_field_s.imsg -#define b_initiator icrbb_field_s.initiator +#define b_imsgtype icrbb_field_s.imsgtype +#define b_btenum icrbb_field_s.btenum +#define b_cohtrans icrbb_field_s.cohtrans +#define b_xtsize icrbb_field_s.xtsize +#define b_srcnode icrbb_field_s.srcnode +#define b_srcinit icrbb_field_s.srcinit +#define b_imsgtype icrbb_field_s.imsgtype +#define b_imsg icrbb_field_s.imsg +#define b_initiator icrbb_field_s.initiator #endif /* !__ASSEMBLY__ */ /* * values for field xtsize */ -#define IIO_ICRB_XTSIZE_DW 0 /* Xtalk operation size is 8 bytes */ -#define IIO_ICRB_XTSIZE_32 1 /* Xtalk operation size is 32 bytes */ -#define IIO_ICRB_XTSIZE_128 2 /* Xtalk operation size is 128 bytes */ +#define IIO_ICRB_XTSIZE_DW 0 /* Xtalk operation size is 8 bytes */ +#define IIO_ICRB_XTSIZE_32 1 /* Xtalk operation size is 32 bytes */ +#define IIO_ICRB_XTSIZE_128 2 /* Xtalk operation size is 128 bytes */ /* * values for field srcinit */ -#define IIO_ICRB_PROC0 0 /* Source of request is Proc 0 */ -#define IIO_ICRB_PROC1 1 /* Source of request is Proc 1 */ -#define IIO_ICRB_GB_REQ 2 /* Source is Guaranteed BW request */ -#define IIO_ICRB_IO_REQ 3 /* Source is Normal IO request */ +#define IIO_ICRB_PROC0 0 /* Source of request is Proc 0 */ +#define IIO_ICRB_PROC1 1 /* Source of request is Proc 1 */ +#define IIO_ICRB_GB_REQ 2 /* Source is Guaranteed BW request */ +#define IIO_ICRB_IO_REQ 3 /* Source is Normal IO request */ /* * Values for field imsgtype */ -#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */ -#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */ -#define IIO_ICRB_IMSGT_SN0NET 2 /* Incoming message from SN0 net */ -#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */ +#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */ +#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */ +#define IIO_ICRB_IMSGT_SN0NET 2 /* Incoming message from SN0 net */ +#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */ /* * values for field initiator. */ -#define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */ -#define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */ -#define IIO_ICRB_INIT_SN0NET 0x2 /* Message originated in SN0net */ -#define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */ -#define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */ +#define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */ +#define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */ +#define IIO_ICRB_INIT_SN0NET 0x2 /* Message originated in SN0net */ +#define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */ +#define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */ /* * Values for field reqtype. */ /* XXX - Need to fix this for Hub 2 */ -#define IIO_ICRB_REQ_DWRD 0 /* Request type double word */ -#define IIO_ICRB_REQ_QCLRD 1 /* Request is Qrtr Caceh line Rd */ -#define IIO_ICRB_REQ_BLKRD 2 /* Request is block read */ -#define IIO_ICRB_REQ_RSHU 6 /* Request is BTE block read */ -#define IIO_ICRB_REQ_REXU 7 /* request is BTE Excl Read */ -#define IIO_ICRB_REQ_RDEX 8 /* Request is Read Exclusive */ -#define IIO_ICRB_REQ_WINC 9 /* Request is Write Invalidate */ -#define IIO_ICRB_REQ_BWINV 10 /* Request is BTE Winv */ -#define IIO_ICRB_REQ_PIORD 11 /* Request is PIO read */ -#define IIO_ICRB_REQ_PIOWR 12 /* Request is PIO Write */ -#define IIO_ICRB_REQ_PRDM 13 /* Request is Fetch&Op */ -#define IIO_ICRB_REQ_PWRM 14 /* Request is Store &Op */ -#define IIO_ICRB_REQ_PTPWR 15 /* Request is Peer to peer */ -#define IIO_ICRB_REQ_WB 16 /* Request is Write back */ -#define IIO_ICRB_REQ_DEX 17 /* Retained DEX Cache line */ +#define IIO_ICRB_REQ_DWRD 0 /* Request type double word */ +#define IIO_ICRB_REQ_QCLRD 1 /* Request is Qrtr Caceh line Rd */ +#define IIO_ICRB_REQ_BLKRD 2 /* Request is block read */ +#define IIO_ICRB_REQ_RSHU 6 /* Request is BTE block read */ +#define IIO_ICRB_REQ_REXU 7 /* request is BTE Excl Read */ +#define IIO_ICRB_REQ_RDEX 8 /* Request is Read Exclusive */ +#define IIO_ICRB_REQ_WINC 9 /* Request is Write Invalidate */ +#define IIO_ICRB_REQ_BWINV 10 /* Request is BTE Winv */ +#define IIO_ICRB_REQ_PIORD 11 /* Request is PIO read */ +#define IIO_ICRB_REQ_PIOWR 12 /* Request is PIO Write */ +#define IIO_ICRB_REQ_PRDM 13 /* Request is Fetch&Op */ +#define IIO_ICRB_REQ_PWRM 14 /* Request is Store &Op */ +#define IIO_ICRB_REQ_PTPWR 15 /* Request is Peer to peer */ +#define IIO_ICRB_REQ_WB 16 /* Request is Write back */ +#define IIO_ICRB_REQ_DEX 17 /* Retained DEX Cache line */ /* * Fields in CRB Register C @@ -674,8 +674,8 @@ typedef union icrbc_s { u64 rsvd: 6, sleep: 1, pricnt: 4, /* Priority count sent with Read req */ - pripsc: 4, /* Priority Pre scalar */ - bteop: 1, /* BTE Operation */ + pripsc: 4, /* Priority Pre scalar */ + bteop: 1, /* BTE Operation */ push_be: 34, /* Push address Byte enable * Holds push addr, if CRB is for BTE * If CRB belongs to Partial cache, @@ -684,20 +684,20 @@ typedef union icrbc_s { */ suppl: 11, /* Supplemental field */ barrop: 1, /* Barrier Op bit set in xtalk req */ - doresp: 1, /* Xtalk req needs a response */ - gbr: 1; /* GBR bit set in xtalk packet */ + doresp: 1, /* Xtalk req needs a response */ + gbr: 1; /* GBR bit set in xtalk packet */ } icrbc_field_s; } icrbc_t; -#define c_pricnt icrbc_field_s.pricnt -#define c_pripsc icrbc_field_s.pripsc -#define c_bteop icrbc_field_s.bteop -#define c_bteaddr icrbc_field_s.push_be /* push_be field has 2 names */ -#define c_benable icrbc_field_s.push_be /* push_be field has 2 names */ -#define c_suppl icrbc_field_s.suppl -#define c_barrop icrbc_field_s.barrop -#define c_doresp icrbc_field_s.doresp -#define c_gbr icrbc_field_s.gbr +#define c_pricnt icrbc_field_s.pricnt +#define c_pripsc icrbc_field_s.pripsc +#define c_bteop icrbc_field_s.bteop +#define c_bteaddr icrbc_field_s.push_be /* push_be field has 2 names */ +#define c_benable icrbc_field_s.push_be /* push_be field has 2 names */ +#define c_suppl icrbc_field_s.suppl +#define c_barrop icrbc_field_s.barrop +#define c_doresp icrbc_field_s.doresp +#define c_gbr icrbc_field_s.gbr #endif /* !__ASSEMBLY__ */ /* @@ -708,31 +708,31 @@ typedef union icrbc_s { typedef union icrbd_s { u64 reg_value; struct { - u64 rsvd: 38, + u64 rsvd: 38, toutvld: 1, /* Timeout in progress for this CRB */ - ctxtvld: 1, /* Context field below is valid */ + ctxtvld: 1, /* Context field below is valid */ rsvd2: 1, - context: 15, /* Bit vector: + context: 15, /* Bit vector: * Has a bit set for each CRB entry * which needs to be deallocated * before this CRB entry is processed. * Set only for barrier operations. */ - timeout: 8; /* Timeout Upper 8 bits */ + timeout: 8; /* Timeout Upper 8 bits */ } icrbd_field_s; } icrbd_t; -#define icrbd_toutvld icrbd_field_s.toutvld -#define icrbd_ctxtvld icrbd_field_s.ctxtvld -#define icrbd_context icrbd_field_s.context +#define icrbd_toutvld icrbd_field_s.toutvld +#define icrbd_ctxtvld icrbd_field_s.ctxtvld +#define icrbd_context icrbd_field_s.context typedef union hubii_ifdr_u { u64 hi_ifdr_value; struct { u64 ifdr_rsvd: 49, - ifdr_maxrp: 7, - ifdr_rsvd1: 1, + ifdr_maxrp: 7, + ifdr_rsvd1: 1, ifdr_maxrq: 7; } hi_ifdr_fields; } hubii_ifdr_t; @@ -789,26 +789,26 @@ typedef union hubii_ifdr_u { typedef union iprte_a { u64 entry; struct { - u64 rsvd1 : 7, /* Reserved field */ - valid : 1, /* Maps to a timeout entry */ - rsvd2 : 1, - srcnode : 9, /* Node which did this PIO */ - initiator : 2, /* If T5A or T5B or IO */ - rsvd3 : 3, - addr : 38, /* Physical address of PIO */ - rsvd4 : 3; + u64 rsvd1 : 7, /* Reserved field */ + valid : 1, /* Maps to a timeout entry */ + rsvd2 : 1, + srcnode : 9, /* Node which did this PIO */ + initiator : 2, /* If T5A or T5B or IO */ + rsvd3 : 3, + addr : 38, /* Physical address of PIO */ + rsvd4 : 3; } iprte_fields; } iprte_a_t; -#define iprte_valid iprte_fields.valid -#define iprte_timeout iprte_fields.timeout -#define iprte_srcnode iprte_fields.srcnode -#define iprte_init iprte_fields.initiator -#define iprte_addr iprte_fields.addr +#define iprte_valid iprte_fields.valid +#define iprte_timeout iprte_fields.timeout +#define iprte_srcnode iprte_fields.srcnode +#define iprte_init iprte_fields.initiator +#define iprte_addr iprte_fields.addr #endif /* !__ASSEMBLY__ */ -#define IPRTE_ADDRSHFT 3 +#define IPRTE_ADDRSHFT 3 /* * Hub IIO PRB Register format. @@ -823,14 +823,14 @@ typedef union iprte_a { typedef union iprb_u { u64 reg_value; struct { - u64 rsvd1: 15, + u64 rsvd1: 15, error: 1, /* Widget rcvd wr resp pkt w/ error */ - ovflow: 5, /* Overflow count. perf measurement */ + ovflow: 5, /* Overflow count. perf measurement */ fire_and_forget: 1, /* Launch Write without response */ mode: 2, /* Widget operation Mode */ rsvd2: 2, bnakctr: 14, - rsvd3: 2, + rsvd3: 2, anakctr: 14, xtalkctr: 8; } iprb_fields_s; @@ -838,13 +838,13 @@ typedef union iprb_u { #define iprb_regval reg_value -#define iprb_error iprb_fields_s.error -#define iprb_ovflow iprb_fields_s.ovflow -#define iprb_ff iprb_fields_s.fire_and_forget -#define iprb_mode iprb_fields_s.mode -#define iprb_bnakctr iprb_fields_s.bnakctr -#define iprb_anakctr iprb_fields_s.anakctr -#define iprb_xtalkctr iprb_fields_s.xtalkctr +#define iprb_error iprb_fields_s.error +#define iprb_ovflow iprb_fields_s.ovflow +#define iprb_ff iprb_fields_s.fire_and_forget +#define iprb_mode iprb_fields_s.mode +#define iprb_bnakctr iprb_fields_s.bnakctr +#define iprb_anakctr iprb_fields_s.anakctr +#define iprb_xtalkctr iprb_fields_s.xtalkctr #endif /* !__ASSEMBLY__ */ @@ -853,10 +853,10 @@ typedef union iprb_u { * For details of the meanings of NAK and Accept, refer the PIO flow * document */ -#define IPRB_MODE_NORMAL (0) -#define IPRB_MODE_COLLECT_A (1) /* PRB in collect A mode */ -#define IPRB_MODE_SERVICE_A (2) /* NAK B and Accept A */ -#define IPRB_MODE_SERVICE_B (3) /* NAK A and Accept B */ +#define IPRB_MODE_NORMAL (0) +#define IPRB_MODE_COLLECT_A (1) /* PRB in collect A mode */ +#define IPRB_MODE_SERVICE_A (2) /* NAK B and Accept A */ +#define IPRB_MODE_SERVICE_B (3) /* NAK A and Accept B */ /* * IO CRB entry C_A to E_A : Partial (cache) CRBS @@ -865,31 +865,31 @@ typedef union iprb_u { typedef union icrbp_a { u64 ip_reg; /* the entire register value */ struct { - u64 error: 1, /* 63, error occurred */ - ln_uce: 1, /* 62: uncorrectable memory */ - ln_ae: 1, /* 61: protection violation */ - ln_werr:1, /* 60: write access error */ - ln_aerr:1, /* 59: sn0net: Address error */ - ln_perr:1, /* 58: sn0net: poison error */ - timeout:1, /* 57: CRB timed out */ - l_bdpkt:1, /* 56: truncated pkt on sn0net */ - c_bdpkt:1, /* 55: truncated pkt on xtalk */ - c_err: 1, /* 54: incoming xtalk req, err set*/ + u64 error: 1, /* 63, error occurred */ + ln_uce: 1, /* 62: uncorrectable memory */ + ln_ae: 1, /* 61: protection violation */ + ln_werr:1, /* 60: write access error */ + ln_aerr:1, /* 59: sn0net: Address error */ + ln_perr:1, /* 58: sn0net: poison error */ + timeout:1, /* 57: CRB timed out */ + l_bdpkt:1, /* 56: truncated pkt on sn0net */ + c_bdpkt:1, /* 55: truncated pkt on xtalk */ + c_err: 1, /* 54: incoming xtalk req, err set*/ rsvd1: 12, /* 53-42: reserved */ - valid: 1, /* 41: Valid status */ + valid: 1, /* 41: Valid status */ sidn: 4, /* 40-37: SIDN field of xtalk rqst */ tnum: 5, /* 36-32: TNUM of xtalk request */ - bo: 1, /* 31: barrier op set in xtalk rqst*/ - resprqd:1, /* 30: xtalk rqst requires response*/ - gbr: 1, /* 29: gbr bit set in xtalk rqst */ + bo: 1, /* 31: barrier op set in xtalk rqst*/ + resprqd:1, /* 30: xtalk rqst requires response*/ + gbr: 1, /* 29: gbr bit set in xtalk rqst */ size: 2, /* 28-27: size of xtalk request */ excl: 4, /* 26-23: exclusive bit(s) */ stall: 3, /* 22-20: stall (xtalk, bte 0/1) */ - intvn: 1, /* 19: rqst target of intervention*/ - resp: 1, /* 18: Data response given to t5 */ - ack: 1, /* 17: Data ack received. */ - hold: 1, /* 16: crb gathering invalidate acks*/ - wb: 1, /* 15: writeback pending. */ + intvn: 1, /* 19: rqst target of intervention*/ + resp: 1, /* 18: Data response given to t5 */ + ack: 1, /* 17: Data ack received. */ + hold: 1, /* 16: crb gathering invalidate acks*/ + wb: 1, /* 15: writeback pending. */ ack_cnt:11, /* 14-04: counter of invalidate acks*/ tscaler:4; /* 03-00: Timeout prescaler */ } ip_fmt; @@ -908,13 +908,13 @@ typedef union hubii_idsr { u64 iin_reg; struct { u64 rsvd1 : 35, - isent : 1, - rsvd2 : 3, - ienable: 1, - rsvd : 7, - node : 9, - rsvd4 : 1, - level : 7; + isent : 1, + rsvd2 : 3, + ienable: 1, + rsvd : 7, + node : 9, + rsvd4 : 1, + level : 7; } iin_fmt; } hubii_idsr_t; #endif /* !__ASSEMBLY__ */ @@ -966,7 +966,7 @@ typedef union hubii_idsr { * Value of 3 is required by Xbow 1.1 * We may be able to increase this to 4 with Xbow 1.2. */ -#define HUBII_XBOW_CREDIT 3 +#define HUBII_XBOW_CREDIT 3 #define HUBII_XBOW_REV2_CREDIT 4 #endif /* _ASM_SGI_SN_SN0_HUBIO_H */ diff --git a/arch/mips/include/asm/sn/sn0/hubmd.h b/arch/mips/include/asm/sn/sn0/hubmd.h index 14c225d8066..305d002be18 100644 --- a/arch/mips/include/asm/sn/sn0/hubmd.h +++ b/arch/mips/include/asm/sn/sn0/hubmd.h @@ -8,16 +8,16 @@ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. * Copyright (C) 1999 by Ralf Baechle */ -#ifndef _ASM_SN_SN0_HUBMD_H -#define _ASM_SN_SN0_HUBMD_H +#ifndef _ASM_SN_SN0_HUBMD_H +#define _ASM_SN_SN0_HUBMD_H /* * Hub Memory/Directory interface registers */ -#define CACHE_SLINE_SIZE 128 /* Secondary cache line size on SN0 */ +#define CACHE_SLINE_SIZE 128 /* Secondary cache line size on SN0 */ -#define MAX_REGIONS 64 +#define MAX_REGIONS 64 /* Hardware page size and shift */ @@ -34,62 +34,62 @@ #define MD_IO_PROT_OVRRD 0x200008 /* Clear my bit in MD_IO_PROTECT */ #define MD_HSPEC_PROTECT 0x200010 /* BDDIR, LBOOT, RBOOT protection */ #define MD_MEMORY_CONFIG 0x200018 /* Memory/Directory DIMM control */ -#define MD_REFRESH_CONTROL 0x200020 /* Memory/Directory refresh ctrl */ -#define MD_FANDOP_CAC_STAT 0x200028 /* Fetch-and-op cache status */ -#define MD_MIG_DIFF_THRESH 0x200030 /* Page migr. count diff thresh. */ -#define MD_MIG_VALUE_THRESH 0x200038 /* Page migr. count abs. thresh. */ -#define MD_MIG_CANDIDATE 0x200040 /* Latest page migration candidate */ -#define MD_MIG_CANDIDATE_CLR 0x200048 /* Clear page migration candidate */ -#define MD_DIR_ERROR 0x200050 /* Directory DIMM error */ -#define MD_DIR_ERROR_CLR 0x200058 /* Directory DIMM error clear */ -#define MD_PROTOCOL_ERROR 0x200060 /* Directory protocol error */ +#define MD_REFRESH_CONTROL 0x200020 /* Memory/Directory refresh ctrl */ +#define MD_FANDOP_CAC_STAT 0x200028 /* Fetch-and-op cache status */ +#define MD_MIG_DIFF_THRESH 0x200030 /* Page migr. count diff thresh. */ +#define MD_MIG_VALUE_THRESH 0x200038 /* Page migr. count abs. thresh. */ +#define MD_MIG_CANDIDATE 0x200040 /* Latest page migration candidate */ +#define MD_MIG_CANDIDATE_CLR 0x200048 /* Clear page migration candidate */ +#define MD_DIR_ERROR 0x200050 /* Directory DIMM error */ +#define MD_DIR_ERROR_CLR 0x200058 /* Directory DIMM error clear */ +#define MD_PROTOCOL_ERROR 0x200060 /* Directory protocol error */ #define MD_PROTOCOL_ERROR_CLR 0x200068 /* Directory protocol error clear */ -#define MD_MEM_ERROR 0x200070 /* Memory DIMM error */ -#define MD_MEM_ERROR_CLR 0x200078 /* Memory DIMM error clear */ -#define MD_MISC_ERROR 0x200080 /* Miscellaneous MD error */ +#define MD_MEM_ERROR 0x200070 /* Memory DIMM error */ +#define MD_MEM_ERROR_CLR 0x200078 /* Memory DIMM error clear */ +#define MD_MISC_ERROR 0x200080 /* Miscellaneous MD error */ #define MD_MISC_ERROR_CLR 0x200088 /* Miscellaneous MD error clear */ #define MD_MEM_DIMM_INIT 0x200090 /* Memory DIMM mode initization. */ -#define MD_DIR_DIMM_INIT 0x200098 /* Directory DIMM mode init. */ -#define MD_MOQ_SIZE 0x2000a0 /* MD outgoing queue size */ +#define MD_DIR_DIMM_INIT 0x200098 /* Directory DIMM mode init. */ +#define MD_MOQ_SIZE 0x2000a0 /* MD outgoing queue size */ #define MD_MLAN_CTL 0x2000a8 /* NIC (Microlan) control register */ -#define MD_PERF_SEL 0x210000 /* Select perf monitor events */ -#define MD_PERF_CNT0 0x210010 /* Performance counter 0 */ -#define MD_PERF_CNT1 0x210018 /* Performance counter 1 */ -#define MD_PERF_CNT2 0x210020 /* Performance counter 2 */ -#define MD_PERF_CNT3 0x210028 /* Performance counter 3 */ -#define MD_PERF_CNT4 0x210030 /* Performance counter 4 */ -#define MD_PERF_CNT5 0x210038 /* Performance counter 5 */ - -#define MD_UREG0_0 0x220000 /* uController/UART 0 register */ -#define MD_UREG0_1 0x220008 /* uController/UART 0 register */ -#define MD_UREG0_2 0x220010 /* uController/UART 0 register */ -#define MD_UREG0_3 0x220018 /* uController/UART 0 register */ -#define MD_UREG0_4 0x220020 /* uController/UART 0 register */ -#define MD_UREG0_5 0x220028 /* uController/UART 0 register */ -#define MD_UREG0_6 0x220030 /* uController/UART 0 register */ -#define MD_UREG0_7 0x220038 /* uController/UART 0 register */ +#define MD_PERF_SEL 0x210000 /* Select perf monitor events */ +#define MD_PERF_CNT0 0x210010 /* Performance counter 0 */ +#define MD_PERF_CNT1 0x210018 /* Performance counter 1 */ +#define MD_PERF_CNT2 0x210020 /* Performance counter 2 */ +#define MD_PERF_CNT3 0x210028 /* Performance counter 3 */ +#define MD_PERF_CNT4 0x210030 /* Performance counter 4 */ +#define MD_PERF_CNT5 0x210038 /* Performance counter 5 */ + +#define MD_UREG0_0 0x220000 /* uController/UART 0 register */ +#define MD_UREG0_1 0x220008 /* uController/UART 0 register */ +#define MD_UREG0_2 0x220010 /* uController/UART 0 register */ +#define MD_UREG0_3 0x220018 /* uController/UART 0 register */ +#define MD_UREG0_4 0x220020 /* uController/UART 0 register */ +#define MD_UREG0_5 0x220028 /* uController/UART 0 register */ +#define MD_UREG0_6 0x220030 /* uController/UART 0 register */ +#define MD_UREG0_7 0x220038 /* uController/UART 0 register */ #define MD_SLOTID_USTAT 0x220048 /* Hub slot ID & UART/uCtlr status */ -#define MD_LED0 0x220050 /* Eight-bit LED for CPU A */ -#define MD_LED1 0x220058 /* Eight-bit LED for CPU B */ - -#define MD_UREG1_0 0x220080 /* uController/UART 1 register */ -#define MD_UREG1_1 0x220088 /* uController/UART 1 register */ -#define MD_UREG1_2 0x220090 /* uController/UART 1 register */ -#define MD_UREG1_3 0x220098 /* uController/UART 1 register */ -#define MD_UREG1_4 0x2200a0 /* uController/UART 1 register */ -#define MD_UREG1_5 0x2200a8 /* uController/UART 1 register */ -#define MD_UREG1_6 0x2200b0 /* uController/UART 1 register */ -#define MD_UREG1_7 0x2200b8 /* uController/UART 1 register */ -#define MD_UREG1_8 0x2200c0 /* uController/UART 1 register */ -#define MD_UREG1_9 0x2200c8 /* uController/UART 1 register */ -#define MD_UREG1_10 0x2200d0 /* uController/UART 1 register */ -#define MD_UREG1_11 0x2200d8 /* uController/UART 1 register */ -#define MD_UREG1_12 0x2200e0 /* uController/UART 1 register */ -#define MD_UREG1_13 0x2200e8 /* uController/UART 1 register */ -#define MD_UREG1_14 0x2200f0 /* uController/UART 1 register */ -#define MD_UREG1_15 0x2200f8 /* uController/UART 1 register */ +#define MD_LED0 0x220050 /* Eight-bit LED for CPU A */ +#define MD_LED1 0x220058 /* Eight-bit LED for CPU B */ + +#define MD_UREG1_0 0x220080 /* uController/UART 1 register */ +#define MD_UREG1_1 0x220088 /* uController/UART 1 register */ +#define MD_UREG1_2 0x220090 /* uController/UART 1 register */ +#define MD_UREG1_3 0x220098 /* uController/UART 1 register */ +#define MD_UREG1_4 0x2200a0 /* uController/UART 1 register */ +#define MD_UREG1_5 0x2200a8 /* uController/UART 1 register */ +#define MD_UREG1_6 0x2200b0 /* uController/UART 1 register */ +#define MD_UREG1_7 0x2200b8 /* uController/UART 1 register */ +#define MD_UREG1_8 0x2200c0 /* uController/UART 1 register */ +#define MD_UREG1_9 0x2200c8 /* uController/UART 1 register */ +#define MD_UREG1_10 0x2200d0 /* uController/UART 1 register */ +#define MD_UREG1_11 0x2200d8 /* uController/UART 1 register */ +#define MD_UREG1_12 0x2200e0 /* uController/UART 1 register */ +#define MD_UREG1_13 0x2200e8 /* uController/UART 1 register */ +#define MD_UREG1_14 0x2200f0 /* uController/UART 1 register */ +#define MD_UREG1_15 0x2200f8 /* uController/UART 1 register */ #ifdef CONFIG_SGI_SN_N_MODE #define MD_MEM_BANKS 4 /* 4 banks of memory max in N mode */ @@ -106,14 +106,14 @@ * Bits not used by the MD are used by software. */ -#define MD_SIZE_EMPTY 0 /* Valid in MEMORY_CONFIG */ +#define MD_SIZE_EMPTY 0 /* Valid in MEMORY_CONFIG */ #define MD_SIZE_8MB 1 #define MD_SIZE_16MB 2 #define MD_SIZE_32MB 3 /* Broken in Hub 1 */ -#define MD_SIZE_64MB 4 /* Valid in MEMORY_CONFIG */ -#define MD_SIZE_128MB 5 /* Valid in MEMORY_CONFIG */ +#define MD_SIZE_64MB 4 /* Valid in MEMORY_CONFIG */ +#define MD_SIZE_128MB 5 /* Valid in MEMORY_CONFIG */ #define MD_SIZE_256MB 6 -#define MD_SIZE_512MB 7 /* Valid in MEMORY_CONFIG */ +#define MD_SIZE_512MB 7 /* Valid in MEMORY_CONFIG */ #define MD_SIZE_1GB 8 #define MD_SIZE_2GB 9 #define MD_SIZE_4GB 10 @@ -207,16 +207,16 @@ /* MD_SLOTID_USTAT bit definitions */ -#define MSU_CORECLK_TST_SHFT 7 /* You don't wanna know */ +#define MSU_CORECLK_TST_SHFT 7 /* You don't wanna know */ #define MSU_CORECLK_TST_MASK (UINT64_CAST 1 << 7) #define MSU_CORECLK_TST (UINT64_CAST 1 << 7) -#define MSU_CORECLK_SHFT 6 /* You don't wanna know */ +#define MSU_CORECLK_SHFT 6 /* You don't wanna know */ #define MSU_CORECLK_MASK (UINT64_CAST 1 << 6) #define MSU_CORECLK (UINT64_CAST 1 << 6) -#define MSU_NETSYNC_SHFT 5 /* You don't wanna know */ +#define MSU_NETSYNC_SHFT 5 /* You don't wanna know */ #define MSU_NETSYNC_MASK (UINT64_CAST 1 << 5) #define MSU_NETSYNC (UINT64_CAST 1 << 5) -#define MSU_FPROMRDY_SHFT 4 /* Flash PROM ready bit */ +#define MSU_FPROMRDY_SHFT 4 /* Flash PROM ready bit */ #define MSU_FPROMRDY_MASK (UINT64_CAST 1 << 4) #define MSU_FPROMRDY (UINT64_CAST 1 << 4) #define MSU_I2CINTR_SHFT 3 /* I2C interrupt bit */ @@ -228,8 +228,8 @@ #define MSU_SN00_SLOTID_SHFT 7 #define MSU_SN00_SLOTID_MASK (UINT64_CAST 0x80) -#define MSU_PIMM_PSC_SHFT 4 -#define MSU_PIMM_PSC_MASK (0xf << MSU_PIMM_PSC_SHFT) +#define MSU_PIMM_PSC_SHFT 4 +#define MSU_PIMM_PSC_MASK (0xf << MSU_PIMM_PSC_SHFT) /* MD_MIG_DIFF_THRESH bit definitions */ @@ -260,7 +260,7 @@ /* Other MD definitions */ -#define MD_BANK_SHFT 29 /* log2(512 MB) */ +#define MD_BANK_SHFT 29 /* log2(512 MB) */ #define MD_BANK_MASK (UINT64_CAST 7 << 29) #define MD_BANK_SIZE (UINT64_CAST 1 << MD_BANK_SHFT) /* 512 MB */ #define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT) @@ -300,32 +300,32 @@ * Format C: STATE != shared (FINE must be 0) */ -#define MD_PDIR_MASK 0xffffffffffff /* Whole entry */ +#define MD_PDIR_MASK 0xffffffffffff /* Whole entry */ #define MD_PDIR_ECC_SHFT 0 /* ABC low or high */ #define MD_PDIR_ECC_MASK 0x7f -#define MD_PDIR_PRIO_SHFT 8 /* ABC low */ +#define MD_PDIR_PRIO_SHFT 8 /* ABC low */ #define MD_PDIR_PRIO_MASK (0xf << 8) -#define MD_PDIR_AX_SHFT 7 /* ABC low */ +#define MD_PDIR_AX_SHFT 7 /* ABC low */ #define MD_PDIR_AX_MASK (1 << 7) #define MD_PDIR_AX (1 << 7) -#define MD_PDIR_FINE_SHFT 12 /* ABC low */ +#define MD_PDIR_FINE_SHFT 12 /* ABC low */ #define MD_PDIR_FINE_MASK (1 << 12) #define MD_PDIR_FINE (1 << 12) -#define MD_PDIR_OCT_SHFT 13 /* A low */ +#define MD_PDIR_OCT_SHFT 13 /* A low */ #define MD_PDIR_OCT_MASK (7 << 13) -#define MD_PDIR_STATE_SHFT 13 /* BC low */ +#define MD_PDIR_STATE_SHFT 13 /* BC low */ #define MD_PDIR_STATE_MASK (7 << 13) -#define MD_PDIR_ONECNT_SHFT 16 /* BC low */ +#define MD_PDIR_ONECNT_SHFT 16 /* BC low */ #define MD_PDIR_ONECNT_MASK (0x3f << 16) -#define MD_PDIR_PTR_SHFT 22 /* C low */ +#define MD_PDIR_PTR_SHFT 22 /* C low */ #define MD_PDIR_PTR_MASK (UINT64_CAST 0x7ff << 22) -#define MD_PDIR_VECMSB_SHFT 22 /* AB low */ +#define MD_PDIR_VECMSB_SHFT 22 /* AB low */ #define MD_PDIR_VECMSB_BITMASK 0x3ffffff #define MD_PDIR_VECMSB_BITSHFT 27 #define MD_PDIR_VECMSB_MASK (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22) -#define MD_PDIR_CWOFF_SHFT 7 /* C high */ +#define MD_PDIR_CWOFF_SHFT 7 /* C high */ #define MD_PDIR_CWOFF_MASK (7 << 7) -#define MD_PDIR_VECLSB_SHFT 10 /* AB high */ +#define MD_PDIR_VECLSB_SHFT 10 /* AB high */ #define MD_PDIR_VECLSB_BITMASK (UINT64_CAST 0x3fffffffff) #define MD_PDIR_VECLSB_BITSHFT 0 #define MD_PDIR_VECLSB_MASK (MD_PDIR_VECLSB_BITMASK << 10) @@ -349,25 +349,25 @@ * Format C: STATE != shared */ -#define MD_SDIR_MASK 0xffff /* Whole entry */ +#define MD_SDIR_MASK 0xffff /* Whole entry */ #define MD_SDIR_ECC_SHFT 0 /* AC low or high */ #define MD_SDIR_ECC_MASK 0x1f -#define MD_SDIR_PRIO_SHFT 6 /* AC low */ +#define MD_SDIR_PRIO_SHFT 6 /* AC low */ #define MD_SDIR_PRIO_MASK (1 << 6) -#define MD_SDIR_AX_SHFT 5 /* AC low */ +#define MD_SDIR_AX_SHFT 5 /* AC low */ #define MD_SDIR_AX_MASK (1 << 5) #define MD_SDIR_AX (1 << 5) -#define MD_SDIR_STATE_SHFT 7 /* AC low */ +#define MD_SDIR_STATE_SHFT 7 /* AC low */ #define MD_SDIR_STATE_MASK (7 << 7) -#define MD_SDIR_PTR_SHFT 10 /* C low */ +#define MD_SDIR_PTR_SHFT 10 /* C low */ #define MD_SDIR_PTR_MASK (0x3f << 10) -#define MD_SDIR_CWOFF_SHFT 5 /* C high */ +#define MD_SDIR_CWOFF_SHFT 5 /* C high */ #define MD_SDIR_CWOFF_MASK (7 << 5) -#define MD_SDIR_VECMSB_SHFT 11 /* A low */ +#define MD_SDIR_VECMSB_SHFT 11 /* A low */ #define MD_SDIR_VECMSB_BITMASK 0x1f #define MD_SDIR_VECMSB_BITSHFT 7 #define MD_SDIR_VECMSB_MASK (MD_SDIR_VECMSB_BITMASK << 11) -#define MD_SDIR_VECLSB_SHFT 5 /* A high */ +#define MD_SDIR_VECLSB_SHFT 5 /* A high */ #define MD_SDIR_VECLSB_BITMASK 0x7ff #define MD_SDIR_VECLSB_BITSHFT 0 #define MD_SDIR_VECLSB_MASK (MD_SDIR_VECLSB_BITMASK << 5) @@ -390,7 +390,7 @@ /* Premium SIMM protection entry shifts and masks. */ -#define MD_PPROT_SHFT 0 /* Prot. field */ +#define MD_PPROT_SHFT 0 /* Prot. field */ #define MD_PPROT_MASK 7 #define MD_PPROT_MIGMD_SHFT 3 /* Migration mode */ #define MD_PPROT_MIGMD_MASK (3 << 3) @@ -403,7 +403,7 @@ /* Standard SIMM protection entry shifts and masks. */ -#define MD_SPROT_SHFT 0 /* Prot. field */ +#define MD_SPROT_SHFT 0 /* Prot. field */ #define MD_SPROT_MASK 7 #define MD_SPROT_MIGMD_SHFT 3 /* Migration mode */ #define MD_SPROT_MIGMD_MASK (3 << 3) @@ -431,13 +431,13 @@ #define CPU_LED_ADDR(_nasid, _slice) \ (private.p_sn00 ? \ - REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) : \ + REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) : \ REMOTE_HUB_ADDR((_nasid), MD_LED0 + ((_slice) << 3))) #define SET_CPU_LEDS(_nasid, _slice, _val) \ (HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val))) -#define SET_MY_LEDS(_v) \ +#define SET_MY_LEDS(_v) \ SET_CPU_LEDS(get_nasid(), get_slice(), (_v)) /* @@ -541,7 +541,7 @@ */ struct dir_error_reg { - u64 uce_vld: 1, /* 63: valid directory uce */ + u64 uce_vld: 1, /* 63: valid directory uce */ ae_vld: 1, /* 62: valid dir prot ecc error */ ce_vld: 1, /* 61: valid correctable ECC err*/ rsvd1: 19, /* 60-42: reserved */ @@ -555,13 +555,13 @@ struct dir_error_reg { }; typedef union md_dir_error { - u64 derr_reg; /* the entire register */ + u64 derr_reg; /* the entire register */ struct dir_error_reg derr_fmt; /* the register format */ } md_dir_error_t; struct mem_error_reg { - u64 uce_vld: 1, /* 63: valid memory uce */ + u64 uce_vld: 1, /* 63: valid memory uce */ ce_vld: 1, /* 62: valid correctable ECC err*/ rsvd1: 22, /* 61-40: reserved */ bad_syn: 8, /* 39-32: bad mem ecc syndrome */ @@ -573,8 +573,8 @@ struct mem_error_reg { typedef union md_mem_error { - u64 merr_reg; /* the entire register */ - struct mem_error_reg merr_fmt; /* format of the mem_error reg */ + u64 merr_reg; /* the entire register */ + struct mem_error_reg merr_fmt; /* format of the mem_error reg */ } md_mem_error_t; @@ -594,7 +594,7 @@ struct proto_error_reg { }; typedef union md_proto_error { - u64 perr_reg; /* the entire register */ + u64 perr_reg; /* the entire register */ struct proto_error_reg perr_fmt; /* format of the register */ } md_proto_error_t; @@ -695,33 +695,33 @@ typedef union md_pdir_loent { * represent directory memory information. */ -typedef union md_dir_high { - md_sdir_high_t md_sdir_high; - md_pdir_high_t md_pdir_high; +typedef union md_dir_high { + md_sdir_high_t md_sdir_high; + md_pdir_high_t md_pdir_high; } md_dir_high_t; -typedef union md_dir_low { - md_sdir_low_t md_sdir_low; - md_pdir_low_t md_pdir_low; +typedef union md_dir_low { + md_sdir_low_t md_sdir_low; + md_pdir_low_t md_pdir_low; } md_dir_low_t; -typedef struct bddir_entry { - md_dir_low_t md_dir_low; - md_dir_high_t md_dir_high; +typedef struct bddir_entry { + md_dir_low_t md_dir_low; + md_dir_high_t md_dir_high; } bddir_entry_t; typedef struct dir_mem_entry { - u64 prcpf[MAX_REGIONS]; - bddir_entry_t directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE]; + u64 prcpf[MAX_REGIONS]; + bddir_entry_t directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE]; } dir_mem_entry_t; typedef union md_perf_sel { - u64 perf_sel_reg; + u64 perf_sel_reg; struct { u64 perf_rsvd : 60, - perf_en : 1, + perf_en : 1, perf_sel : 3; } perf_sel_bits; } md_perf_sel_t; @@ -730,7 +730,7 @@ typedef union md_perf_cnt { u64 perf_cnt; struct { u64 perf_rsvd : 44, - perf_cnt : 20; + perf_cnt : 20; } perf_cnt_bits; } md_perf_cnt_t; diff --git a/arch/mips/include/asm/sn/sn0/hubni.h b/arch/mips/include/asm/sn/sn0/hubni.h index b40d3ef97a1..b73c4bee65f 100644 --- a/arch/mips/include/asm/sn/sn0/hubni.h +++ b/arch/mips/include/asm/sn/sn0/hubni.h @@ -25,38 +25,38 @@ #define NI_BASE_TABLES 0x630000 #define NI_STATUS_REV_ID 0x600000 /* Hub network status, rev, and ID */ -#define NI_PORT_RESET 0x600008 /* Reset the network interface */ +#define NI_PORT_RESET 0x600008 /* Reset the network interface */ #define NI_PROTECTION 0x600010 /* NI register access permissions */ -#define NI_GLOBAL_PARMS 0x600018 /* LLP parameters */ +#define NI_GLOBAL_PARMS 0x600018 /* LLP parameters */ #define NI_SCRATCH_REG0 0x600100 /* Scratch register 0 (64 bits) */ #define NI_SCRATCH_REG1 0x600108 /* Scratch register 1 (64 bits) */ #define NI_DIAG_PARMS 0x600110 /* Parameters for diags */ #define NI_VECTOR_PARMS 0x600200 /* Vector PIO routing parameters */ -#define NI_VECTOR 0x600208 /* Vector PIO route */ -#define NI_VECTOR_DATA 0x600210 /* Vector PIO data */ -#define NI_VECTOR_STATUS 0x600300 /* Vector PIO return status */ -#define NI_RETURN_VECTOR 0x600308 /* Vector PIO return vector */ -#define NI_VECTOR_READ_DATA 0x600310 /* Vector PIO read data */ +#define NI_VECTOR 0x600208 /* Vector PIO route */ +#define NI_VECTOR_DATA 0x600210 /* Vector PIO data */ +#define NI_VECTOR_STATUS 0x600300 /* Vector PIO return status */ +#define NI_RETURN_VECTOR 0x600308 /* Vector PIO return vector */ +#define NI_VECTOR_READ_DATA 0x600310 /* Vector PIO read data */ #define NI_VECTOR_CLEAR 0x600380 /* Vector PIO read & clear status */ -#define NI_IO_PROTECT 0x600400 /* PIO protection bits */ -#define NI_IO_PROT_OVRRD 0x600408 /* PIO protection bit override */ - -#define NI_AGE_CPU0_MEMORY 0x600500 /* CPU 0 memory age control */ -#define NI_AGE_CPU0_PIO 0x600508 /* CPU 0 PIO age control */ -#define NI_AGE_CPU1_MEMORY 0x600510 /* CPU 1 memory age control */ -#define NI_AGE_CPU1_PIO 0x600518 /* CPU 1 PIO age control */ -#define NI_AGE_GBR_MEMORY 0x600520 /* GBR memory age control */ -#define NI_AGE_GBR_PIO 0x600528 /* GBR PIO age control */ -#define NI_AGE_IO_MEMORY 0x600530 /* IO memory age control */ -#define NI_AGE_IO_PIO 0x600538 /* IO PIO age control */ +#define NI_IO_PROTECT 0x600400 /* PIO protection bits */ +#define NI_IO_PROT_OVRRD 0x600408 /* PIO protection bit override */ + +#define NI_AGE_CPU0_MEMORY 0x600500 /* CPU 0 memory age control */ +#define NI_AGE_CPU0_PIO 0x600508 /* CPU 0 PIO age control */ +#define NI_AGE_CPU1_MEMORY 0x600510 /* CPU 1 memory age control */ +#define NI_AGE_CPU1_PIO 0x600518 /* CPU 1 PIO age control */ +#define NI_AGE_GBR_MEMORY 0x600520 /* GBR memory age control */ +#define NI_AGE_GBR_PIO 0x600528 /* GBR PIO age control */ +#define NI_AGE_IO_MEMORY 0x600530 /* IO memory age control */ +#define NI_AGE_IO_PIO 0x600538 /* IO PIO age control */ #define NI_AGE_REG_MIN NI_AGE_CPU0_MEMORY #define NI_AGE_REG_MAX NI_AGE_IO_PIO -#define NI_PORT_PARMS 0x608000 /* LLP Parameters */ -#define NI_PORT_ERROR 0x608008 /* LLP Errors */ -#define NI_PORT_ERROR_CLEAR 0x608088 /* Clear the error bits */ +#define NI_PORT_PARMS 0x608000 /* LLP Parameters */ +#define NI_PORT_ERROR 0x608008 /* LLP Errors */ +#define NI_PORT_ERROR_CLEAR 0x608088 /* Clear the error bits */ #define NI_META_TABLE0 0x638000 /* First meta routing table entry */ #define NI_META_TABLE(_x) (NI_META_TABLE0 + (8 * (_x))) @@ -76,13 +76,13 @@ #define NSRI_LINKUP_SHFT 29 #define NSRI_LINKUP_MASK (UINT64_CAST 0x1 << 29) #define NSRI_DOWNREASON_SHFT 28 /* 0=failed, 1=never came */ -#define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28) /* out of reset. */ +#define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28) /* out of reset. */ #define NSRI_MORENODES_SHFT 18 #define NSRI_MORENODES_MASK (UINT64_CAST 1 << 18) /* Max. # of nodes */ #define MORE_MEMORY 0 #define MORE_NODES 1 #define NSRI_REGIONSIZE_SHFT 17 -#define NSRI_REGIONSIZE_MASK (UINT64_CAST 1 << 17) /* Granularity */ +#define NSRI_REGIONSIZE_MASK (UINT64_CAST 1 << 17) /* Granularity */ #define REGIONSIZE_FINE 1 #define REGIONSIZE_COARSE 0 #define NSRI_NODEID_SHFT 8 @@ -90,14 +90,14 @@ #define NSRI_REV_SHFT 4 #define NSRI_REV_MASK (UINT64_CAST 0xf << 4) /* Chip Revision */ #define NSRI_CHIPID_SHFT 0 -#define NSRI_CHIPID_MASK (UINT64_CAST 0xf) /* Chip type ID */ +#define NSRI_CHIPID_MASK (UINT64_CAST 0xf) /* Chip type ID */ /* - * In fine mode, each node is a region. In coarse mode, there are + * In fine mode, each node is a region. In coarse mode, there are * eight nodes per region. */ #define NASID_TO_FINEREG_SHFT 0 -#define NASID_TO_COARSEREG_SHFT 3 +#define NASID_TO_COARSEREG_SHFT 3 /* NI_PORT_RESET mask definitions */ @@ -111,21 +111,21 @@ /* NI_GLOBAL_PARMS mask and shift definitions */ -#define NGP_MAXRETRY_SHFT 48 /* Maximum retries */ +#define NGP_MAXRETRY_SHFT 48 /* Maximum retries */ #define NGP_MAXRETRY_MASK (UINT64_CAST 0x3ff << 48) -#define NGP_TAILTOWRAP_SHFT 32 /* Tail timeout wrap */ +#define NGP_TAILTOWRAP_SHFT 32 /* Tail timeout wrap */ #define NGP_TAILTOWRAP_MASK (UINT64_CAST 0xffff << 32) -#define NGP_CREDITTOVAL_SHFT 16 /* Tail timeout wrap */ +#define NGP_CREDITTOVAL_SHFT 16 /* Tail timeout wrap */ #define NGP_CREDITTOVAL_MASK (UINT64_CAST 0xf << 16) -#define NGP_TAILTOVAL_SHFT 4 /* Tail timeout value */ +#define NGP_TAILTOVAL_SHFT 4 /* Tail timeout value */ #define NGP_TAILTOVAL_MASK (UINT64_CAST 0xf << 4) /* NI_DIAG_PARMS mask and shift definitions */ #define NDP_PORTTORESET (UINT64_CAST 1 << 18) /* Port tmout reset */ #define NDP_LLP8BITMODE (UINT64_CAST 1 << 12) /* LLP 8-bit mode */ -#define NDP_PORTDISABLE (UINT64_CAST 1 << 6) /* Port disable */ +#define NDP_PORTDISABLE (UINT64_CAST 1 << 6) /* Port disable */ #define NDP_SENDERROR (UINT64_CAST 1) /* Send data error */ /* @@ -137,7 +137,7 @@ #define NVP_PIOID_MASK (UINT64_CAST 0x3ff << 40) #define NVP_WRITEID_SHFT 32 #define NVP_WRITEID_MASK (UINT64_CAST 0xff << 32) -#define NVP_ADDRESS_MASK (UINT64_CAST 0xffff8) /* Bits 19:3 */ +#define NVP_ADDRESS_MASK (UINT64_CAST 0xffff8) /* Bits 19:3 */ #define NVP_TYPE_SHFT 0 #define NVP_TYPE_MASK (UINT64_CAST 0x3) @@ -151,7 +151,7 @@ #define NVS_PIOID_MASK (UINT64_CAST 0x3ff << 40) #define NVS_WRITEID_SHFT 32 #define NVS_WRITEID_MASK (UINT64_CAST 0xff << 32) -#define NVS_ADDRESS_MASK (UINT64_CAST 0xfffffff8) /* Bits 31:3 */ +#define NVS_ADDRESS_MASK (UINT64_CAST 0xfffffff8) /* Bits 31:3 */ #define NVS_TYPE_SHFT 0 #define NVS_TYPE_MASK (UINT64_CAST 0x7) #define NVS_ERROR_MASK (UINT64_CAST 0x4) /* bit set means error */ @@ -161,10 +161,10 @@ #define PIOTYPE_WRITE 1 /* VECTOR_PARMS and VECTOR_STATUS */ #define PIOTYPE_UNDEFINED 2 /* VECTOR_PARMS and VECTOR_STATUS */ #define PIOTYPE_EXCHANGE 3 /* VECTOR_PARMS and VECTOR_STATUS */ -#define PIOTYPE_ADDR_ERR 4 /* VECTOR_STATUS only */ -#define PIOTYPE_CMD_ERR 5 /* VECTOR_STATUS only */ -#define PIOTYPE_PROT_ERR 6 /* VECTOR_STATUS only */ -#define PIOTYPE_UNKNOWN 7 /* VECTOR_STATUS only */ +#define PIOTYPE_ADDR_ERR 4 /* VECTOR_STATUS only */ +#define PIOTYPE_CMD_ERR 5 /* VECTOR_STATUS only */ +#define PIOTYPE_PROT_ERR 6 /* VECTOR_STATUS only */ +#define PIOTYPE_UNKNOWN 7 /* VECTOR_STATUS only */ /* NI_AGE_XXX mask and shift definitions */ @@ -215,7 +215,7 @@ #define NPE_FATAL_ERRORS (NPE_LINKRESET | NPE_INTERNALERROR | \ NPE_BADMESSAGE | NPE_BADDEST | \ - NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \ + NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \ NPE_TAILTO_MASK) /* NI_META_TABLE mask and shift definitions */ @@ -231,7 +231,7 @@ typedef union hubni_port_error_u { u64 nipe_reg_value; struct { - u64 nipe_rsvd: 26, /* unused */ + u64 nipe_rsvd: 26, /* unused */ nipe_lnk_reset: 1, /* link reset */ nipe_intl_err: 1, /* internal error */ nipe_bad_msg: 1, /* bad message */ diff --git a/arch/mips/include/asm/sn/sn0/hubpi.h b/arch/mips/include/asm/sn/sn0/hubpi.h index e39f5f9da04..7b83655913c 100644 --- a/arch/mips/include/asm/sn/sn0/hubpi.h +++ b/arch/mips/include/asm/sn/sn0/hubpi.h @@ -8,8 +8,8 @@ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. * Copyright (C) 1999 by Ralf Baechle */ -#ifndef _ASM_SN_SN0_HUBPI_H -#define _ASM_SN_SN0_HUBPI_H +#ifndef _ASM_SN_SN0_HUBPI_H +#define _ASM_SN_SN0_HUBPI_H #include <linux/types.h> @@ -25,13 +25,13 @@ /* General protection and control registers */ -#define PI_CPU_PROTECT 0x000000 /* CPU Protection */ -#define PI_PROT_OVERRD 0x000008 /* Clear CPU Protection bit */ -#define PI_IO_PROTECT 0x000010 /* Interrupt Pending Protection */ +#define PI_CPU_PROTECT 0x000000 /* CPU Protection */ +#define PI_PROT_OVERRD 0x000008 /* Clear CPU Protection bit */ +#define PI_IO_PROTECT 0x000010 /* Interrupt Pending Protection */ #define PI_REGION_PRESENT 0x000018 /* Indicates whether region exists */ -#define PI_CPU_NUM 0x000020 /* CPU Number ID */ -#define PI_CALIAS_SIZE 0x000028 /* Cached Alias Size */ -#define PI_MAX_CRB_TIMEOUT 0x000030 /* Maximum Timeout for CRB */ +#define PI_CPU_NUM 0x000020 /* CPU Number ID */ +#define PI_CALIAS_SIZE 0x000028 /* Cached Alias Size */ +#define PI_MAX_CRB_TIMEOUT 0x000030 /* Maximum Timeout for CRB */ #define PI_CRB_SFACTOR 0x000038 /* Scale factor for CRB timeout */ /* CALIAS values */ @@ -54,28 +54,28 @@ /* Processor control and status checking */ -#define PI_CPU_PRESENT_A 0x000040 /* CPU Present A */ -#define PI_CPU_PRESENT_B 0x000048 /* CPU Present B */ -#define PI_CPU_ENABLE_A 0x000050 /* CPU Enable A */ -#define PI_CPU_ENABLE_B 0x000058 /* CPU Enable B */ -#define PI_REPLY_LEVEL 0x000060 /* Reply Level */ +#define PI_CPU_PRESENT_A 0x000040 /* CPU Present A */ +#define PI_CPU_PRESENT_B 0x000048 /* CPU Present B */ +#define PI_CPU_ENABLE_A 0x000050 /* CPU Enable A */ +#define PI_CPU_ENABLE_B 0x000058 /* CPU Enable B */ +#define PI_REPLY_LEVEL 0x000060 /* Reply Level */ #define PI_HARDRESET_BIT 0x020068 /* Bit cleared by s/w on SR */ -#define PI_NMI_A 0x000070 /* NMI to CPU A */ -#define PI_NMI_B 0x000078 /* NMI to CPU B */ +#define PI_NMI_A 0x000070 /* NMI to CPU A */ +#define PI_NMI_B 0x000078 /* NMI to CPU B */ #define PI_NMI_OFFSET (PI_NMI_B - PI_NMI_A) -#define PI_SOFTRESET 0x000080 /* Softreset (to both CPUs) */ +#define PI_SOFTRESET 0x000080 /* Softreset (to both CPUs) */ -/* Regular Interrupt register checking. */ +/* Regular Interrupt register checking. */ #define PI_INT_PEND_MOD 0x000090 /* Write to set pending ints */ -#define PI_INT_PEND0 0x000098 /* Read to get pending ints */ -#define PI_INT_PEND1 0x0000a0 /* Read to get pending ints */ -#define PI_INT_MASK0_A 0x0000a8 /* Interrupt Mask 0 for CPU A */ -#define PI_INT_MASK1_A 0x0000b0 /* Interrupt Mask 1 for CPU A */ -#define PI_INT_MASK0_B 0x0000b8 /* Interrupt Mask 0 for CPU B */ -#define PI_INT_MASK1_B 0x0000c0 /* Interrupt Mask 1 for CPU B */ +#define PI_INT_PEND0 0x000098 /* Read to get pending ints */ +#define PI_INT_PEND1 0x0000a0 /* Read to get pending ints */ +#define PI_INT_MASK0_A 0x0000a8 /* Interrupt Mask 0 for CPU A */ +#define PI_INT_MASK1_A 0x0000b0 /* Interrupt Mask 1 for CPU A */ +#define PI_INT_MASK0_B 0x0000b8 /* Interrupt Mask 0 for CPU B */ +#define PI_INT_MASK1_B 0x0000c0 /* Interrupt Mask 1 for CPU B */ -#define PI_INT_MASK_OFFSET 0x10 /* Offset from A to B */ +#define PI_INT_MASK_OFFSET 0x10 /* Offset from A to B */ /* Crosscall interrupts */ @@ -83,49 +83,49 @@ #define PI_CC_PEND_SET_B 0x0000d0 /* CC Interrupt Pending Set, CPU B */ #define PI_CC_PEND_CLR_A 0x0000d8 /* CC Interrupt Pending Clr, CPU A */ #define PI_CC_PEND_CLR_B 0x0000e0 /* CC Interrupt Pending Clr, CPU B */ -#define PI_CC_MASK 0x0000e8 /* CC Interrupt mask */ +#define PI_CC_MASK 0x0000e8 /* CC Interrupt mask */ -#define PI_INT_SET_OFFSET 0x08 /* Offset from A to B */ +#define PI_INT_SET_OFFSET 0x08 /* Offset from A to B */ /* Realtime Counter and Profiler control registers */ -#define PI_RT_COUNT 0x030100 /* Real Time Counter */ -#define PI_RT_COMPARE_A 0x000108 /* Real Time Compare A */ -#define PI_RT_COMPARE_B 0x000110 /* Real Time Compare B */ +#define PI_RT_COUNT 0x030100 /* Real Time Counter */ +#define PI_RT_COMPARE_A 0x000108 /* Real Time Compare A */ +#define PI_RT_COMPARE_B 0x000110 /* Real Time Compare B */ #define PI_PROFILE_COMPARE 0x000118 /* L5 int to both cpus when == RTC */ -#define PI_RT_PEND_A 0x000120 /* Set if RT int for A pending */ -#define PI_RT_PEND_B 0x000128 /* Set if RT int for B pending */ +#define PI_RT_PEND_A 0x000120 /* Set if RT int for A pending */ +#define PI_RT_PEND_B 0x000128 /* Set if RT int for B pending */ #define PI_PROF_PEND_A 0x000130 /* Set if Prof int for A pending */ #define PI_PROF_PEND_B 0x000138 /* Set if Prof int for B pending */ -#define PI_RT_EN_A 0x000140 /* RT int for CPU A enable */ -#define PI_RT_EN_B 0x000148 /* RT int for CPU B enable */ -#define PI_PROF_EN_A 0x000150 /* PROF int for CPU A enable */ -#define PI_PROF_EN_B 0x000158 /* PROF int for CPU B enable */ -#define PI_RT_LOCAL_CTRL 0x000160 /* RT control register */ +#define PI_RT_EN_A 0x000140 /* RT int for CPU A enable */ +#define PI_RT_EN_B 0x000148 /* RT int for CPU B enable */ +#define PI_PROF_EN_A 0x000150 /* PROF int for CPU A enable */ +#define PI_PROF_EN_B 0x000158 /* PROF int for CPU B enable */ +#define PI_RT_LOCAL_CTRL 0x000160 /* RT control register */ #define PI_RT_FILTER_CTRL 0x000168 /* GCLK Filter control register */ #define PI_COUNT_OFFSET 0x08 /* A to B offset for all counts */ /* Built-In Self Test support */ -#define PI_BIST_WRITE_DATA 0x000200 /* BIST write data */ -#define PI_BIST_READ_DATA 0x000208 /* BIST read data */ -#define PI_BIST_COUNT_TARG 0x000210 /* BIST Count and Target */ -#define PI_BIST_READY 0x000218 /* BIST Ready indicator */ -#define PI_BIST_SHIFT_LOAD 0x000220 /* BIST control */ -#define PI_BIST_SHIFT_UNLOAD 0x000228 /* BIST control */ -#define PI_BIST_ENTER_RUN 0x000230 /* BIST control */ +#define PI_BIST_WRITE_DATA 0x000200 /* BIST write data */ +#define PI_BIST_READ_DATA 0x000208 /* BIST read data */ +#define PI_BIST_COUNT_TARG 0x000210 /* BIST Count and Target */ +#define PI_BIST_READY 0x000218 /* BIST Ready indicator */ +#define PI_BIST_SHIFT_LOAD 0x000220 /* BIST control */ +#define PI_BIST_SHIFT_UNLOAD 0x000228 /* BIST control */ +#define PI_BIST_ENTER_RUN 0x000230 /* BIST control */ /* Graphics control registers */ -#define PI_GFX_PAGE_A 0x000300 /* Graphics page A */ -#define PI_GFX_CREDIT_CNTR_A 0x000308 /* Graphics credit counter A */ -#define PI_GFX_BIAS_A 0x000310 /* Graphics bias A */ +#define PI_GFX_PAGE_A 0x000300 /* Graphics page A */ +#define PI_GFX_CREDIT_CNTR_A 0x000308 /* Graphics credit counter A */ +#define PI_GFX_BIAS_A 0x000310 /* Graphics bias A */ #define PI_GFX_INT_CNTR_A 0x000318 /* Graphics interrupt counter A */ #define PI_GFX_INT_CMP_A 0x000320 /* Graphics interrupt comparator A */ -#define PI_GFX_PAGE_B 0x000328 /* Graphics page B */ -#define PI_GFX_CREDIT_CNTR_B 0x000330 /* Graphics credit counter B */ -#define PI_GFX_BIAS_B 0x000338 /* Graphics bias B */ +#define PI_GFX_PAGE_B 0x000328 /* Graphics page B */ +#define PI_GFX_CREDIT_CNTR_B 0x000330 /* Graphics credit counter B */ +#define PI_GFX_BIAS_B 0x000338 /* Graphics bias B */ #define PI_GFX_INT_CNTR_B 0x000340 /* Graphics interrupt counter B */ #define PI_GFX_INT_CMP_B 0x000348 /* Graphics interrupt comparator B */ @@ -138,24 +138,24 @@ #define PI_ERR_INT_MASK_B 0x000410 /* Error Interrupt mask for CPU B */ #define PI_ERR_STACK_ADDR_A 0x000418 /* Error stack address for CPU A */ #define PI_ERR_STACK_ADDR_B 0x000420 /* Error stack address for CPU B */ -#define PI_ERR_STACK_SIZE 0x000428 /* Error Stack Size */ -#define PI_ERR_STATUS0_A 0x000430 /* Error Status 0A */ +#define PI_ERR_STACK_SIZE 0x000428 /* Error Stack Size */ +#define PI_ERR_STATUS0_A 0x000430 /* Error Status 0A */ #define PI_ERR_STATUS0_A_RCLR 0x000438 /* Error Status 0A clear on read */ -#define PI_ERR_STATUS1_A 0x000440 /* Error Status 1A */ +#define PI_ERR_STATUS1_A 0x000440 /* Error Status 1A */ #define PI_ERR_STATUS1_A_RCLR 0x000448 /* Error Status 1A clear on read */ -#define PI_ERR_STATUS0_B 0x000450 /* Error Status 0B */ +#define PI_ERR_STATUS0_B 0x000450 /* Error Status 0B */ #define PI_ERR_STATUS0_B_RCLR 0x000458 /* Error Status 0B clear on read */ -#define PI_ERR_STATUS1_B 0x000460 /* Error Status 1B */ +#define PI_ERR_STATUS1_B 0x000460 /* Error Status 1B */ #define PI_ERR_STATUS1_B_RCLR 0x000468 /* Error Status 1B clear on read */ -#define PI_SPOOL_CMP_A 0x000470 /* Spool compare for CPU A */ -#define PI_SPOOL_CMP_B 0x000478 /* Spool compare for CPU B */ -#define PI_CRB_TIMEOUT_A 0x000480 /* Timed out CRB entries for A */ -#define PI_CRB_TIMEOUT_B 0x000488 /* Timed out CRB entries for B */ +#define PI_SPOOL_CMP_A 0x000470 /* Spool compare for CPU A */ +#define PI_SPOOL_CMP_B 0x000478 /* Spool compare for CPU B */ +#define PI_CRB_TIMEOUT_A 0x000480 /* Timed out CRB entries for A */ +#define PI_CRB_TIMEOUT_B 0x000488 /* Timed out CRB entries for B */ #define PI_SYSAD_ERRCHK_EN 0x000490 /* Enables SYSAD error checking */ -#define PI_BAD_CHECK_BIT_A 0x000498 /* Force SYSAD check bit error */ -#define PI_BAD_CHECK_BIT_B 0x0004a0 /* Force SYSAD check bit error */ -#define PI_NACK_CNT_A 0x0004a8 /* Consecutive NACK counter */ -#define PI_NACK_CNT_B 0x0004b0 /* " " for CPU B */ +#define PI_BAD_CHECK_BIT_A 0x000498 /* Force SYSAD check bit error */ +#define PI_BAD_CHECK_BIT_B 0x0004a0 /* Force SYSAD check bit error */ +#define PI_NACK_CNT_A 0x0004a8 /* Consecutive NACK counter */ +#define PI_NACK_CNT_B 0x0004b0 /* " " for CPU B */ #define PI_NACK_CMP 0x0004b8 /* NACK count compare */ #define PI_STACKADDR_OFFSET (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A) #define PI_ERRSTAT_OFFSET (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A) @@ -168,7 +168,7 @@ #define PI_ERR_SPUR_MSG_A 0x00000008 #define PI_ERR_WRB_TERR_B 0x00000010 /* WRB TERR */ #define PI_ERR_WRB_TERR_A 0x00000020 -#define PI_ERR_WRB_WERR_B 0x00000040 /* WRB WERR */ +#define PI_ERR_WRB_WERR_B 0x00000040 /* WRB WERR */ #define PI_ERR_WRB_WERR_A 0x00000080 #define PI_ERR_SYSSTATE_B 0x00000100 /* SysState parity error */ #define PI_ERR_SYSSTATE_A 0x00000200 @@ -196,32 +196,32 @@ * The following three macros define all possible error int pends. */ -#define PI_FATAL_ERR_CPU_A (PI_ERR_SYSSTATE_TAG_A | \ - PI_ERR_BAD_SPOOL_A | \ - PI_ERR_SYSCMD_ADDR_A | \ - PI_ERR_SYSCMD_DATA_A | \ - PI_ERR_SYSAD_ADDR_A | \ +#define PI_FATAL_ERR_CPU_A (PI_ERR_SYSSTATE_TAG_A | \ + PI_ERR_BAD_SPOOL_A | \ + PI_ERR_SYSCMD_ADDR_A | \ + PI_ERR_SYSCMD_DATA_A | \ + PI_ERR_SYSAD_ADDR_A | \ PI_ERR_SYSAD_DATA_A | \ PI_ERR_SYSSTATE_A) -#define PI_MISC_ERR_CPU_A (PI_ERR_UNCAC_UNCORR_A | \ - PI_ERR_WRB_WERR_A | \ - PI_ERR_WRB_TERR_A | \ - PI_ERR_SPUR_MSG_A | \ +#define PI_MISC_ERR_CPU_A (PI_ERR_UNCAC_UNCORR_A | \ + PI_ERR_WRB_WERR_A | \ + PI_ERR_WRB_TERR_A | \ + PI_ERR_SPUR_MSG_A | \ PI_ERR_SPOOL_CMP_A) -#define PI_FATAL_ERR_CPU_B (PI_ERR_SYSSTATE_TAG_B | \ - PI_ERR_BAD_SPOOL_B | \ - PI_ERR_SYSCMD_ADDR_B | \ - PI_ERR_SYSCMD_DATA_B | \ - PI_ERR_SYSAD_ADDR_B | \ +#define PI_FATAL_ERR_CPU_B (PI_ERR_SYSSTATE_TAG_B | \ + PI_ERR_BAD_SPOOL_B | \ + PI_ERR_SYSCMD_ADDR_B | \ + PI_ERR_SYSCMD_DATA_B | \ + PI_ERR_SYSAD_ADDR_B | \ PI_ERR_SYSAD_DATA_B | \ PI_ERR_SYSSTATE_B) -#define PI_MISC_ERR_CPU_B (PI_ERR_UNCAC_UNCORR_B | \ - PI_ERR_WRB_WERR_B | \ - PI_ERR_WRB_TERR_B | \ - PI_ERR_SPUR_MSG_B | \ +#define PI_MISC_ERR_CPU_B (PI_ERR_UNCAC_UNCORR_B | \ + PI_ERR_WRB_WERR_B | \ + PI_ERR_WRB_TERR_B | \ + PI_ERR_SPUR_MSG_B | \ PI_ERR_SPOOL_CMP_B) #define PI_ERR_GENERIC (PI_ERR_MD_UNCORR) @@ -242,24 +242,24 @@ #define PI_ERR_ST0_CMD_SHFT 17 #define PI_ERR_ST0_ADDR_MASK 0x3ffffffffe000000 #define PI_ERR_ST0_ADDR_SHFT 25 -#define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000 -#define PI_ERR_ST0_OVERRUN_SHFT 62 +#define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000 +#define PI_ERR_ST0_OVERRUN_SHFT 62 #define PI_ERR_ST0_VALID_MASK 0x8000000000000000 #define PI_ERR_ST0_VALID_SHFT 63 /* Fields in PI_ERR_STATUS1_[AB] */ #define PI_ERR_ST1_SPOOL_MASK 0x00000000001fffff #define PI_ERR_ST1_SPOOL_SHFT 0 -#define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000 -#define PI_ERR_ST1_TOUTCNT_SHFT 21 +#define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000 +#define PI_ERR_ST1_TOUTCNT_SHFT 21 #define PI_ERR_ST1_INVCNT_MASK 0x0000007fe0000000 #define PI_ERR_ST1_INVCNT_SHFT 29 #define PI_ERR_ST1_CRBNUM_MASK 0x0000038000000000 #define PI_ERR_ST1_CRBNUM_SHFT 39 #define PI_ERR_ST1_WRBRRB_MASK 0x0000040000000000 #define PI_ERR_ST1_WRBRRB_SHFT 42 -#define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000 -#define PI_ERR_ST1_CRBSTAT_SHFT 43 +#define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000 +#define PI_ERR_ST1_CRBSTAT_SHFT 43 #define PI_ERR_ST1_MSGSRC_MASK 0xffe0000000000000 #define PI_ERR_ST1_MSGSRC_SHFT 53 @@ -274,8 +274,8 @@ #define PI_ERR_STK_CRBNUM_SHFT 9 #define PI_ERR_STK_WRBRRB_MASK 0x0000000000001000 #define PI_ERR_STK_WRBRRB_SHFT 12 -#define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000 -#define PI_ERR_STK_CRBSTAT_SHFT 13 +#define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000 +#define PI_ERR_STK_CRBSTAT_SHFT 13 #define PI_ERR_STK_CMD_MASK 0x000000007f800000 #define PI_ERR_STK_CMD_SHFT 23 #define PI_ERR_STK_ADDR_MASK 0xffffffff80000000 @@ -364,11 +364,11 @@ typedef u64 rtc_time_t; /* Bits in PI_SYSAD_ERRCHK_EN */ #define PI_SYSAD_ERRCHK_ECCGEN 0x01 /* Enable ECC generation */ -#define PI_SYSAD_ERRCHK_QUALGEN 0x02 /* Enable data quality signal gen. */ -#define PI_SYSAD_ERRCHK_SADP 0x04 /* Enable SysAD parity checking */ +#define PI_SYSAD_ERRCHK_QUALGEN 0x02 /* Enable data quality signal gen. */ +#define PI_SYSAD_ERRCHK_SADP 0x04 /* Enable SysAD parity checking */ #define PI_SYSAD_ERRCHK_CMDP 0x08 /* Enable SysCmd parity checking */ #define PI_SYSAD_ERRCHK_STATE 0x10 /* Enable SysState parity checking */ -#define PI_SYSAD_ERRCHK_QUAL 0x20 /* Enable data quality checking */ +#define PI_SYSAD_ERRCHK_QUAL 0x20 /* Enable data quality checking */ #define PI_SYSAD_CHECK_ALL 0x3f /* Generate and check all signals. */ /* Interrupt pending bits on R10000 */ diff --git a/arch/mips/include/asm/sn/sn0/ip27.h b/arch/mips/include/asm/sn/sn0/ip27.h index 3c97e0855c8..3b5efeefcc3 100644 --- a/arch/mips/include/asm/sn/sn0/ip27.h +++ b/arch/mips/include/asm/sn/sn0/ip27.h @@ -21,14 +21,14 @@ #ifndef __ASSEMBLY__ -#define CAUSE_BERRINTR IE_IRQ5 +#define CAUSE_BERRINTR IE_IRQ5 -#define ECCF_CACHE_ERR 0 -#define ECCF_TAGLO 1 -#define ECCF_ECC 2 -#define ECCF_ERROREPC 3 -#define ECCF_PADDR 4 -#define ECCF_SIZE (5 * sizeof(long)) +#define ECCF_CACHE_ERR 0 +#define ECCF_TAGLO 1 +#define ECCF_ECC 2 +#define ECCF_ERROREPC 3 +#define ECCF_PADDR 4 +#define ECCF_SIZE (5 * sizeof(long)) #endif /* !__ASSEMBLY__ */ @@ -39,8 +39,8 @@ * the processor number of the calling processor. The proc parameters * must be a register. */ -#define KL_GET_CPUNUM(proc) \ - dli proc, LOCAL_HUB(0); \ +#define KL_GET_CPUNUM(proc) \ + dli proc, LOCAL_HUB(0); \ ld proc, PI_CPU_NUM(proc) #endif /* __ASSEMBLY__ */ @@ -71,15 +71,15 @@ #define NUM_CAUSE_INTRS 8 -#define SCACHE_LINESIZE 128 -#define SCACHE_LINEMASK (SCACHE_LINESIZE - 1) +#define SCACHE_LINESIZE 128 +#define SCACHE_LINEMASK (SCACHE_LINESIZE - 1) #include <asm/sn/addrs.h> -#define LED_CYCLE_MASK 0x0f -#define LED_CYCLE_SHFT 4 +#define LED_CYCLE_MASK 0x0f +#define LED_CYCLE_SHFT 4 #define SEND_NMI(_nasid, _slice) \ - REMOTE_HUB_S((_nasid), (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1) + REMOTE_HUB_S((_nasid), (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1) #endif /* _ASM_SN_SN0_IP27_H */ diff --git a/arch/mips/include/asm/sn/sn_private.h b/arch/mips/include/asm/sn/sn_private.h index 1a2c3025bf2..fdfae43d8b9 100644 --- a/arch/mips/include/asm/sn/sn_private.h +++ b/arch/mips/include/asm/sn/sn_private.h @@ -14,6 +14,6 @@ extern void install_cpu_nmi_handler(int slice); extern void install_ipi(void); extern void setup_replication_mask(void); extern void replicate_kernel_text(void); -extern pfn_t node_getfirstfree(cnodeid_t); +extern unsigned long node_getfirstfree(cnodeid_t); #endif /* __ASM_SN_SN_PRIVATE_H */ diff --git a/arch/mips/include/asm/sn/types.h b/arch/mips/include/asm/sn/types.h index 74d0bb260b8..6d24d4e8b9e 100644 --- a/arch/mips/include/asm/sn/types.h +++ b/arch/mips/include/asm/sn/types.h @@ -11,7 +11,7 @@ #include <linux/types.h> -typedef unsigned long cpuid_t; +typedef unsigned long cpuid_t; typedef unsigned long cnodemask_t; typedef signed short nasid_t; /* node id in numa-as-id space */ typedef signed short cnodeid_t; /* node id in compact-id space */ @@ -19,7 +19,6 @@ typedef signed char partid_t; /* partition ID type */ typedef signed short moduleid_t; /* user-visible module number type */ typedef signed short cmoduleid_t; /* kernel compact module id type */ typedef unsigned char clusterid_t; /* Clusterid of the cell */ -typedef unsigned long pfn_t; typedef dev_t vertex_hdl_t; /* hardware graph vertex handle */ diff --git a/arch/mips/include/asm/sni.h b/arch/mips/include/asm/sni.h index 8c1eb02c6d1..a107201a2e1 100644 --- a/arch/mips/include/asm/sni.h +++ b/arch/mips/include/asm/sni.h @@ -13,27 +13,27 @@ extern unsigned int sni_brd_type; -#define SNI_BRD_10 2 -#define SNI_BRD_10NEW 3 -#define SNI_BRD_TOWER_OASIC 4 -#define SNI_BRD_MINITOWER 5 -#define SNI_BRD_PCI_TOWER 6 -#define SNI_BRD_RM200 7 -#define SNI_BRD_PCI_MTOWER 8 -#define SNI_BRD_PCI_DESKTOP 9 -#define SNI_BRD_PCI_TOWER_CPLUS 10 +#define SNI_BRD_10 2 +#define SNI_BRD_10NEW 3 +#define SNI_BRD_TOWER_OASIC 4 +#define SNI_BRD_MINITOWER 5 +#define SNI_BRD_PCI_TOWER 6 +#define SNI_BRD_RM200 7 +#define SNI_BRD_PCI_MTOWER 8 +#define SNI_BRD_PCI_DESKTOP 9 +#define SNI_BRD_PCI_TOWER_CPLUS 10 #define SNI_BRD_PCI_MTOWER_CPLUS 11 /* RM400 cpu types */ -#define SNI_CPU_M8021 0x01 -#define SNI_CPU_M8030 0x04 -#define SNI_CPU_M8031 0x06 -#define SNI_CPU_M8034 0x0f -#define SNI_CPU_M8037 0x07 -#define SNI_CPU_M8040 0x05 -#define SNI_CPU_M8043 0x09 -#define SNI_CPU_M8050 0x0b -#define SNI_CPU_M8053 0x0d +#define SNI_CPU_M8021 0x01 +#define SNI_CPU_M8030 0x04 +#define SNI_CPU_M8031 0x06 +#define SNI_CPU_M8034 0x0f +#define SNI_CPU_M8037 0x07 +#define SNI_CPU_M8040 0x05 +#define SNI_CPU_M8043 0x09 +#define SNI_CPU_M8050 0x0b +#define SNI_CPU_M8053 0x0d #define SNI_PORT_BASE CKSEG1ADDR(0xb4000000) @@ -52,14 +52,14 @@ extern unsigned int sni_brd_type; #define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0044) #define PCIMT_SYNDROME CKSEG1ADDR(0xbfff004c) #define PCIMT_ITPEND CKSEG1ADDR(0xbfff0054) -#define IT_INT2 0x01 -#define IT_INTD 0x02 -#define IT_INTC 0x04 -#define IT_INTB 0x08 -#define IT_INTA 0x10 -#define IT_EISA 0x20 -#define IT_SCSI 0x40 -#define IT_ETH 0x80 +#define IT_INT2 0x01 +#define IT_INTD 0x02 +#define IT_INTC 0x04 +#define IT_INTB 0x08 +#define IT_INTA 0x10 +#define IT_EISA 0x20 +#define IT_SCSI 0x40 +#define IT_ETH 0x80 #define PCIMT_IRQSEL CKSEG1ADDR(0xbfff005c) #define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0064) #define PCIMT_ECCREG CKSEG1ADDR(0xbfff006c) @@ -86,14 +86,14 @@ extern unsigned int sni_brd_type; #define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0040) #define PCIMT_SYNDROME CKSEG1ADDR(0xbfff0048) #define PCIMT_ITPEND CKSEG1ADDR(0xbfff0050) -#define IT_INT2 0x01 -#define IT_INTD 0x02 -#define IT_INTC 0x04 -#define IT_INTB 0x08 -#define IT_INTA 0x10 -#define IT_EISA 0x20 -#define IT_SCSI 0x40 -#define IT_ETH 0x80 +#define IT_INT2 0x01 +#define IT_INTD 0x02 +#define IT_INTC 0x04 +#define IT_INTB 0x08 +#define IT_INTA 0x10 +#define IT_EISA 0x20 +#define IT_SCSI 0x40 +#define IT_ETH 0x80 #define PCIMT_IRQSEL CKSEG1ADDR(0xbfff0058) #define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0060) #define PCIMT_ECCREG CKSEG1ADDR(0xbfff0068) @@ -137,29 +137,29 @@ extern unsigned int sni_brd_type; /* * A20R based boards */ -#define A20R_PT_CLOCK_BASE CKSEG1ADDR(0xbc040000) -#define A20R_PT_TIM0_ACK CKSEG1ADDR(0xbc050000) -#define A20R_PT_TIM1_ACK CKSEG1ADDR(0xbc060000) +#define A20R_PT_CLOCK_BASE CKSEG1ADDR(0xbc040000) +#define A20R_PT_TIM0_ACK CKSEG1ADDR(0xbc050000) +#define A20R_PT_TIM1_ACK CKSEG1ADDR(0xbc060000) -#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE -#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5) +#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE +#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5) -#define SNI_PCIT_INT_REG CKSEG1ADDR(0xbfff000c) +#define SNI_PCIT_INT_REG CKSEG1ADDR(0xbfff000c) -#define SNI_PCIT_INT_START 24 -#define SNI_PCIT_INT_END 30 +#define SNI_PCIT_INT_START 24 +#define SNI_PCIT_INT_END 30 -#define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5) -#define PCIT_IRQ_INTA (SNI_PCIT_INT_START + 0) -#define PCIT_IRQ_INTB (SNI_PCIT_INT_START + 1) -#define PCIT_IRQ_INTC (SNI_PCIT_INT_START + 2) -#define PCIT_IRQ_INTD (SNI_PCIT_INT_START + 3) -#define PCIT_IRQ_SCSI0 (SNI_PCIT_INT_START + 4) -#define PCIT_IRQ_SCSI1 (SNI_PCIT_INT_START + 5) +#define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5) +#define PCIT_IRQ_INTA (SNI_PCIT_INT_START + 0) +#define PCIT_IRQ_INTB (SNI_PCIT_INT_START + 1) +#define PCIT_IRQ_INTC (SNI_PCIT_INT_START + 2) +#define PCIT_IRQ_INTD (SNI_PCIT_INT_START + 3) +#define PCIT_IRQ_SCSI0 (SNI_PCIT_INT_START + 4) +#define PCIT_IRQ_SCSI1 (SNI_PCIT_INT_START + 5) /* - * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned + * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned * to the other interrupts generated by ASIC PCI. * * INT2 is a wired-or of the push button interrupt, high temperature interrupt @@ -204,12 +204,12 @@ extern unsigned int sni_brd_type; #ifdef CONFIG_CPU_LITTLE_ENDIAN #define __SNI_END 3 #endif -#define SNI_IDPROM_BASE CKSEG1ADDR(0x1ff00000) +#define SNI_IDPROM_BASE CKSEG1ADDR(0x1ff00000) #define SNI_IDPROM_MEMSIZE (SNI_IDPROM_BASE + (0x28 ^ __SNI_END)) #define SNI_IDPROM_BRDTYPE (SNI_IDPROM_BASE + (0x29 ^ __SNI_END)) #define SNI_IDPROM_CPUTYPE (SNI_IDPROM_BASE + (0x30 ^ __SNI_END)) -#define SNI_IDPROM_SIZE 0x1000 +#define SNI_IDPROM_SIZE 0x1000 /* board specific init functions */ extern void sni_a20r_init(void); diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h index 65900dab3ad..d2da53c2c2f 100644 --- a/arch/mips/include/asm/sparsemem.h +++ b/arch/mips/include/asm/sparsemem.h @@ -11,7 +11,7 @@ #else # define SECTION_SIZE_BITS 28 #endif -#define MAX_PHYSMEM_BITS 35 +#define MAX_PHYSMEM_BITS 35 #endif /* CONFIG_SPARSEMEM */ #endif /* _MIPS_SPARSEMEM_H */ diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h index ca61e846ab0..78d201fb6c8 100644 --- a/arch/mips/include/asm/spinlock.h +++ b/arch/mips/include/asm/spinlock.h @@ -17,7 +17,7 @@ /* * Your basic SMP spinlocks, allowing only a single CPU anywhere * - * Simple spin lock operations. There are two variants, one clears IRQ's + * Simple spin lock operations. There are two variants, one clears IRQ's * on the local processor, one does not. * * These are fair FIFO ticket locks @@ -71,7 +71,6 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) " nop \n" " srl %[my_ticket], %[ticket], 16 \n" " andi %[ticket], %[ticket], 0xffff \n" - " andi %[my_ticket], %[my_ticket], 0xffff \n" " bne %[ticket], %[my_ticket], 4f \n" " subu %[ticket], %[my_ticket], %[ticket] \n" "2: \n" @@ -105,7 +104,6 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) " beqz %[my_ticket], 1b \n" " srl %[my_ticket], %[ticket], 16 \n" " andi %[ticket], %[ticket], 0xffff \n" - " andi %[my_ticket], %[my_ticket], 0xffff \n" " bne %[ticket], %[my_ticket], 4f \n" " subu %[ticket], %[my_ticket], %[ticket] \n" "2: \n" @@ -153,7 +151,6 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock) " \n" "1: ll %[ticket], %[ticket_ptr] \n" " srl %[my_ticket], %[ticket], 16 \n" - " andi %[my_ticket], %[my_ticket], 0xffff \n" " andi %[now_serving], %[ticket], 0xffff \n" " bne %[my_ticket], %[now_serving], 3f \n" " addu %[ticket], %[ticket], %[inc] \n" @@ -178,7 +175,6 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock) " \n" "1: ll %[ticket], %[ticket_ptr] \n" " srl %[my_ticket], %[ticket], 16 \n" - " andi %[my_ticket], %[my_ticket], 0xffff \n" " andi %[now_serving], %[ticket], 0xffff \n" " bne %[my_ticket], %[now_serving], 3f \n" " addu %[ticket], %[ticket], %[inc] \n" @@ -222,7 +218,7 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock) * write_can_lock - would write_trylock() succeed? * @lock: the rwlock in question. */ -#define arch_write_can_lock(rw) (!(rw)->lock) +#define arch_write_can_lock(rw) (!(rw)->lock) static inline void arch_read_lock(arch_rwlock_t *rw) { @@ -242,25 +238,16 @@ static inline void arch_read_lock(arch_rwlock_t *rw) : "m" (rw->lock) : "memory"); } else { - __asm__ __volatile__( - " .set noreorder # arch_read_lock \n" - "1: ll %1, %2 \n" - " bltz %1, 3f \n" - " addu %1, 1 \n" - "2: sc %1, %0 \n" - " beqz %1, 1b \n" - " nop \n" - " .subsection 2 \n" - "3: ll %1, %2 \n" - " bltz %1, 3b \n" - " addu %1, 1 \n" - " b 2b \n" - " nop \n" - " .previous \n" - " .set reorder \n" - : "=m" (rw->lock), "=&r" (tmp) - : "m" (rw->lock) - : "memory"); + do { + __asm__ __volatile__( + "1: ll %1, %2 # arch_read_lock \n" + " bltz %1, 1b \n" + " addu %1, 1 \n" + "2: sc %1, %0 \n" + : "=m" (rw->lock), "=&r" (tmp) + : "m" (rw->lock) + : "memory"); + } while (unlikely(!tmp)); } smp_llsc_mb(); @@ -285,21 +272,15 @@ static inline void arch_read_unlock(arch_rwlock_t *rw) : "m" (rw->lock) : "memory"); } else { - __asm__ __volatile__( - " .set noreorder # arch_read_unlock \n" - "1: ll %1, %2 \n" - " sub %1, 1 \n" - " sc %1, %0 \n" - " beqz %1, 2f \n" - " nop \n" - " .subsection 2 \n" - "2: b 1b \n" - " nop \n" - " .previous \n" - " .set reorder \n" - : "=m" (rw->lock), "=&r" (tmp) - : "m" (rw->lock) - : "memory"); + do { + __asm__ __volatile__( + "1: ll %1, %2 # arch_read_unlock \n" + " sub %1, 1 \n" + " sc %1, %0 \n" + : "=m" (rw->lock), "=&r" (tmp) + : "m" (rw->lock) + : "memory"); + } while (unlikely(!tmp)); } } @@ -321,25 +302,16 @@ static inline void arch_write_lock(arch_rwlock_t *rw) : "m" (rw->lock) : "memory"); } else { - __asm__ __volatile__( - " .set noreorder # arch_write_lock \n" - "1: ll %1, %2 \n" - " bnez %1, 3f \n" - " lui %1, 0x8000 \n" - "2: sc %1, %0 \n" - " beqz %1, 3f \n" - " nop \n" - " .subsection 2 \n" - "3: ll %1, %2 \n" - " bnez %1, 3b \n" - " lui %1, 0x8000 \n" - " b 2b \n" - " nop \n" - " .previous \n" - " .set reorder \n" - : "=m" (rw->lock), "=&r" (tmp) - : "m" (rw->lock) - : "memory"); + do { + __asm__ __volatile__( + "1: ll %1, %2 # arch_write_lock \n" + " bnez %1, 1b \n" + " lui %1, 0x8000 \n" + "2: sc %1, %0 \n" + : "=m" (rw->lock), "=&r" (tmp) + : "m" (rw->lock) + : "memory"); + } while (unlikely(!tmp)); } smp_llsc_mb(); @@ -424,25 +396,21 @@ static inline int arch_write_trylock(arch_rwlock_t *rw) : "m" (rw->lock) : "memory"); } else { - __asm__ __volatile__( - " .set noreorder # arch_write_trylock \n" - " li %2, 0 \n" - "1: ll %1, %3 \n" - " bnez %1, 2f \n" - " lui %1, 0x8000 \n" - " sc %1, %0 \n" - " beqz %1, 3f \n" - " li %2, 1 \n" - "2: \n" - __WEAK_LLSC_MB - " .subsection 2 \n" - "3: b 1b \n" - " li %2, 0 \n" - " .previous \n" - " .set reorder \n" - : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) - : "m" (rw->lock) - : "memory"); + do { + __asm__ __volatile__( + " ll %1, %3 # arch_write_trylock \n" + " li %2, 0 \n" + " bnez %1, 2f \n" + " lui %1, 0x8000 \n" + " sc %1, %0 \n" + " li %2, 1 \n" + "2: \n" + : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) + : "m" (rw->lock) + : "memory"); + } while (unlikely(!tmp)); + + smp_llsc_mb(); } return ret; diff --git a/arch/mips/include/asm/spinlock_types.h b/arch/mips/include/asm/spinlock_types.h index c52f36013a9..9b2528e612c 100644 --- a/arch/mips/include/asm/spinlock_types.h +++ b/arch/mips/include/asm/spinlock_types.h @@ -11,7 +11,7 @@ typedef union { /* - * bits 0..15 : serving_now + * bits 0..15 : serving_now * bits 16..31 : ticket */ u32 lock; diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index cb41af5f340..b188c797565 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -17,23 +17,14 @@ #include <asm/asmmacro.h> #include <asm/mipsregs.h> #include <asm/asm-offsets.h> +#include <asm/thread_info.h> -/* - * For SMTC kernel, global IE should be left set, and interrupts - * controlled exclusively via IXMT. - */ -#ifdef CONFIG_MIPS_MT_SMTC -#define STATMASK 0x1e -#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) +#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) #define STATMASK 0x3f #else #define STATMASK 0x1f #endif -#ifdef CONFIG_MIPS_MT_SMTC -#include <asm/mipsmtregs.h> -#endif /* CONFIG_MIPS_MT_SMTC */ - .macro SAVE_AT .set push .set noat @@ -70,6 +61,14 @@ #ifndef CONFIG_CPU_HAS_SMARTMIPS LONG_S v1, PT_LO(sp) #endif +#ifdef CONFIG_CPU_CAVIUM_OCTEON + /* + * The Octeon multiplier state is affected by general + * multiply instructions. It must be saved before and + * kernel code might corrupt it + */ + jal octeon_mult_save +#endif .endm .macro SAVE_STATIC @@ -85,21 +84,8 @@ .endm #ifdef CONFIG_SMP -#ifdef CONFIG_MIPS_MT_SMTC -#define PTEBASE_SHIFT 19 /* TCBIND */ -#define CPU_ID_REG CP0_TCBIND -#define CPU_ID_MFC0 mfc0 -#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT) -#define PTEBASE_SHIFT 48 /* XCONTEXT */ -#define CPU_ID_REG CP0_XCONTEXT -#define CPU_ID_MFC0 MFC0 -#else -#define PTEBASE_SHIFT 23 /* CONTEXT */ -#define CPU_ID_REG CP0_CONTEXT -#define CPU_ID_MFC0 MFC0 -#endif .macro get_saved_sp /* SMP variation */ - CPU_ID_MFC0 k0, CPU_ID_REG + ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) lui k1, %hi(kernelsp) #else @@ -109,17 +95,17 @@ daddiu k1, %hi(kernelsp) dsll k1, 16 #endif - LONG_SRL k0, PTEBASE_SHIFT + LONG_SRL k0, SMP_CPUID_PTRSHIFT LONG_ADDU k1, k0 LONG_L k1, %lo(kernelsp)(k1) .endm .macro set_saved_sp stackp temp temp2 - CPU_ID_MFC0 \temp, CPU_ID_REG - LONG_SRL \temp, PTEBASE_SHIFT + ASM_CPUID_MFC0 \temp, ASM_SMP_CPUID_REG + LONG_SRL \temp, SMP_CPUID_PTRSHIFT LONG_S \stackp, kernelsp(\temp) .endm -#else +#else /* !CONFIG_SMP */ .macro get_saved_sp /* Uniprocessor variation */ #ifdef CONFIG_CPU_JUMP_WORKAROUNDS /* @@ -139,7 +125,7 @@ 1: move ra, k0 li k0, 3 mtc0 k0, $22 -#endif /* CONFIG_CPU_LOONGSON2F */ +#endif /* CONFIG_CPU_JUMP_WORKAROUNDS */ #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) lui k1, %hi(kernelsp) #else @@ -189,46 +175,27 @@ LONG_S $0, PT_R0(sp) mfc0 v1, CP0_STATUS LONG_S $2, PT_R2(sp) -#ifdef CONFIG_MIPS_MT_SMTC - /* - * Ideally, these instructions would be shuffled in - * to cover the pipeline delay. - */ - .set mips32 - mfc0 k0, CP0_TCSTATUS - .set mips0 - LONG_S k0, PT_TCSTATUS(sp) -#endif /* CONFIG_MIPS_MT_SMTC */ - LONG_S $4, PT_R4(sp) - LONG_S $5, PT_R5(sp) LONG_S v1, PT_STATUS(sp) + LONG_S $4, PT_R4(sp) mfc0 v1, CP0_CAUSE - LONG_S $6, PT_R6(sp) - LONG_S $7, PT_R7(sp) + LONG_S $5, PT_R5(sp) LONG_S v1, PT_CAUSE(sp) + LONG_S $6, PT_R6(sp) MFC0 v1, CP0_EPC + LONG_S $7, PT_R7(sp) #ifdef CONFIG_64BIT LONG_S $8, PT_R8(sp) LONG_S $9, PT_R9(sp) #endif + LONG_S v1, PT_EPC(sp) LONG_S $25, PT_R25(sp) LONG_S $28, PT_R28(sp) LONG_S $31, PT_R31(sp) - LONG_S v1, PT_EPC(sp) ori $28, sp, _THREAD_MASK xori $28, _THREAD_MASK #ifdef CONFIG_CPU_CAVIUM_OCTEON .set mips64 pref 0, 0($28) /* Prefetch the current pointer */ - pref 0, PT_R31(sp) /* Prefetch the $31(ra) */ - /* The Octeon multiplier state is affected by general multiply - instructions. It must be saved before and kernel code might - corrupt it */ - jal octeon_mult_save - LONG_L v1, 0($28) /* Load the current pointer */ - /* Restore $31(ra) that was changed by the jal */ - LONG_L ra, PT_R31(sp) - pref 0, 0(v1) /* Prefetch the current thread */ #endif .set pop .endm @@ -248,6 +215,10 @@ .endm .macro RESTORE_TEMP +#ifdef CONFIG_CPU_CAVIUM_OCTEON + /* Restore the Octeon multiplier state */ + jal octeon_mult_restore +#endif #ifdef CONFIG_CPU_HAS_SMARTMIPS LONG_L $24, PT_ACX(sp) mtlhx $24 @@ -330,40 +301,6 @@ .set push .set reorder .set noat -#ifdef CONFIG_MIPS_MT_SMTC - .set mips32r2 - /* - * We need to make sure the read-modify-write - * of Status below isn't perturbed by an interrupt - * or cross-TC access, so we need to do at least a DMT, - * protected by an interrupt-inhibit. But setting IXMT - * also creates a few-cycle window where an IPI could - * be queued and not be detected before potentially - * returning to a WAIT or user-mode loop. It must be - * replayed. - * - * We're in the middle of a context switch, and - * we can't dispatch it directly without trashing - * some registers, so we'll try to detect this unlikely - * case and program a software interrupt in the VPE, - * as would be done for a cross-VPE IPI. To accommodate - * the handling of that case, we're doing a DVPE instead - * of just a DMT here to protect against other threads. - * This is a lot of cruft to cover a tiny window. - * If you can find a better design, implement it! - * - */ - mfc0 v0, CP0_TCSTATUS - ori v0, TCSTATUS_IXMT - mtc0 v0, CP0_TCSTATUS - _ehb - DVPE 5 # dvpe a1 - jal mips_ihb -#endif /* CONFIG_MIPS_MT_SMTC */ -#ifdef CONFIG_CPU_CAVIUM_OCTEON - /* Restore the Octeon multiplier state */ - jal octeon_mult_restore -#endif mfc0 a0, CP0_STATUS ori a0, STATMASK xori a0, STATMASK @@ -375,59 +312,6 @@ and v0, v1 or v0, a0 mtc0 v0, CP0_STATUS -#ifdef CONFIG_MIPS_MT_SMTC -/* - * Only after EXL/ERL have been restored to status can we - * restore TCStatus.IXMT. - */ - LONG_L v1, PT_TCSTATUS(sp) - _ehb - mfc0 a0, CP0_TCSTATUS - andi v1, TCSTATUS_IXMT - bnez v1, 0f - -/* - * We'd like to detect any IPIs queued in the tiny window - * above and request an software interrupt to service them - * when we ERET. - * - * Computing the offset into the IPIQ array of the executing - * TC's IPI queue in-line would be tedious. We use part of - * the TCContext register to hold 16 bits of offset that we - * can add in-line to find the queue head. - */ - mfc0 v0, CP0_TCCONTEXT - la a2, IPIQ - srl v0, v0, 16 - addu a2, a2, v0 - LONG_L v0, 0(a2) - beqz v0, 0f -/* - * If we have a queue, provoke dispatch within the VPE by setting C_SW1 - */ - mfc0 v0, CP0_CAUSE - ori v0, v0, C_SW1 - mtc0 v0, CP0_CAUSE -0: - /* - * This test should really never branch but - * let's be prudent here. Having atomized - * the shared register modifications, we can - * now EVPE, and must do so before interrupts - * are potentially re-enabled. - */ - andi a1, a1, MVPCONTROL_EVP - beqz a1, 1f - evpe -1: - /* We know that TCStatua.IXMT should be set from above */ - xori a0, a0, TCSTATUS_IXMT - or a0, a0, v1 - mtc0 a0, CP0_TCSTATUS - _ehb - - .set mips0 -#endif /* CONFIG_MIPS_MT_SMTC */ LONG_L v1, PT_EPC(sp) MTC0 v1, CP0_EPC LONG_L $31, PT_R31(sp) @@ -448,7 +332,7 @@ .macro RESTORE_SP_AND_RET LONG_L sp, PT_R29(sp) - .set mips3 + .set arch=r4000 eret .set mips0 .endm @@ -480,33 +364,11 @@ * Set cp0 enable bit as sign that we're running on the kernel stack */ .macro CLI -#if !defined(CONFIG_MIPS_MT_SMTC) mfc0 t0, CP0_STATUS li t1, ST0_CU0 | STATMASK or t0, t1 xori t0, STATMASK mtc0 t0, CP0_STATUS -#else /* CONFIG_MIPS_MT_SMTC */ - /* - * For SMTC, we need to set privilege - * and disable interrupts only for the - * current TC, using the TCStatus register. - */ - mfc0 t0, CP0_TCSTATUS - /* Fortunately CU 0 is in the same place in both registers */ - /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */ - li t1, ST0_CU0 | 0x08001c00 - or t0, t1 - /* Clear TKSU, leave IXMT */ - xori t0, 0x00001800 - mtc0 t0, CP0_TCSTATUS - _ehb - /* We need to leave the global IE bit set, but clear EXL...*/ - mfc0 t0, CP0_STATUS - ori t0, ST0_EXL | ST0_ERL - xori t0, ST0_EXL | ST0_ERL - mtc0 t0, CP0_STATUS -#endif /* CONFIG_MIPS_MT_SMTC */ irq_disable_hazard .endm @@ -515,35 +377,11 @@ * Set cp0 enable bit as sign that we're running on the kernel stack */ .macro STI -#if !defined(CONFIG_MIPS_MT_SMTC) mfc0 t0, CP0_STATUS li t1, ST0_CU0 | STATMASK or t0, t1 xori t0, STATMASK & ~1 mtc0 t0, CP0_STATUS -#else /* CONFIG_MIPS_MT_SMTC */ - /* - * For SMTC, we need to set privilege - * and enable interrupts only for the - * current TC, using the TCStatus register. - */ - _ehb - mfc0 t0, CP0_TCSTATUS - /* Fortunately CU 0 is in the same place in both registers */ - /* Set TCU0, TKSU (for later inversion) and IXMT */ - li t1, ST0_CU0 | 0x08001c00 - or t0, t1 - /* Clear TKSU *and* IXMT */ - xori t0, 0x00001c00 - mtc0 t0, CP0_TCSTATUS - _ehb - /* We need to leave the global IE bit set, but clear EXL...*/ - mfc0 t0, CP0_STATUS - ori t0, ST0_EXL - xori t0, ST0_EXL - mtc0 t0, CP0_STATUS - /* irq_enable_hazard below should expand to EHB for 24K/34K cpus */ -#endif /* CONFIG_MIPS_MT_SMTC */ irq_enable_hazard .endm @@ -553,32 +391,6 @@ * Set cp0 enable bit as sign that we're running on the kernel stack */ .macro KMODE -#ifdef CONFIG_MIPS_MT_SMTC - /* - * This gets baroque in SMTC. We want to - * protect the non-atomic clearing of EXL - * with DMT/EMT, but we don't want to take - * an interrupt while DMT is still in effect. - */ - - /* KMODE gets invoked from both reorder and noreorder code */ - .set push - .set mips32r2 - .set noreorder - mfc0 v0, CP0_TCSTATUS - andi v1, v0, TCSTATUS_IXMT - ori v0, TCSTATUS_IXMT - mtc0 v0, CP0_TCSTATUS - _ehb - DMT 2 # dmt v0 - /* - * We don't know a priori if ra is "live" - */ - move t0, ra - jal mips_ihb - nop /* delay slot */ - move ra, t0 -#endif /* CONFIG_MIPS_MT_SMTC */ mfc0 t0, CP0_STATUS li t1, ST0_CU0 | (STATMASK & ~1) #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) @@ -589,25 +401,6 @@ or t0, t1 xori t0, STATMASK & ~1 mtc0 t0, CP0_STATUS -#ifdef CONFIG_MIPS_MT_SMTC - _ehb - andi v0, v0, VPECONTROL_TE - beqz v0, 2f - nop /* delay slot */ - emt -2: - mfc0 v0, CP0_TCSTATUS - /* Clear IXMT, then OR in previous value */ - ori v0, TCSTATUS_IXMT - xori v0, TCSTATUS_IXMT - or v0, v1, v0 - mtc0 v0, CP0_TCSTATUS - /* - * irq_disable_hazard below should expand to EHB - * on 24K/34K CPUS - */ - .set pop -#endif /* CONFIG_MIPS_MT_SMTC */ irq_disable_hazard .endm diff --git a/arch/mips/include/asm/stackprotector.h b/arch/mips/include/asm/stackprotector.h new file mode 100644 index 00000000000..eb9b1035e92 --- /dev/null +++ b/arch/mips/include/asm/stackprotector.h @@ -0,0 +1,40 @@ +/* + * GCC stack protector support. + * + * (This is directly adopted from the ARM implementation) + * + * Stack protector works by putting predefined pattern at the start of + * the stack frame and verifying that it hasn't been overwritten when + * returning from the function. The pattern is called stack canary + * and gcc expects it to be defined by a global variable called + * "__stack_chk_guard" on MIPS. This unfortunately means that on SMP + * we cannot have a different canary value per task. + */ + +#ifndef _ASM_STACKPROTECTOR_H +#define _ASM_STACKPROTECTOR_H 1 + +#include <linux/random.h> +#include <linux/version.h> + +extern unsigned long __stack_chk_guard; + +/* + * Initialize the stackprotector canary value. + * + * NOTE: this must only be called from functions that never return, + * and it must always be inlined. + */ +static __always_inline void boot_init_stack_canary(void) +{ + unsigned long canary; + + /* Try to get a semi random initial value. */ + get_random_bytes(&canary, sizeof(canary)); + canary ^= LINUX_VERSION_CODE; + + current->stack_canary = canary; + __stack_chk_guard = current->stack_canary; +} + +#endif /* _ASM_STACKPROTECTOR_H */ diff --git a/arch/mips/include/asm/string.h b/arch/mips/include/asm/string.h index 436e3ad352d..29030cb398e 100644 --- a/arch/mips/include/asm/string.h +++ b/arch/mips/include/asm/string.h @@ -35,7 +35,7 @@ static __inline__ char *strcpy(char *__dest, __const__ char *__src) ".set\tat\n\t" ".set\treorder" : "=r" (__dest), "=r" (__src) - : "0" (__dest), "1" (__src) + : "0" (__dest), "1" (__src) : "memory"); return __xdest; @@ -62,9 +62,9 @@ static __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n) "2:\n\t" ".set\tat\n\t" ".set\treorder" - : "=r" (__dest), "=r" (__src), "=r" (__n) - : "0" (__dest), "1" (__src), "2" (__n) - : "memory"); + : "=r" (__dest), "=r" (__src), "=r" (__n) + : "0" (__dest), "1" (__src), "2" (__n) + : "memory"); return __xdest; } diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h index 4f8ddba8c36..495c1041a2c 100644 --- a/arch/mips/include/asm/switch_to.h +++ b/arch/mips/include/asm/switch_to.h @@ -15,14 +15,30 @@ #include <asm/cpu-features.h> #include <asm/watch.h> #include <asm/dsp.h> +#include <asm/cop2.h> +#include <asm/msa.h> struct task_struct; -/* - * switch_to(n) should switch tasks to task nr n, first - * checking that n isn't the current task, in which case it does nothing. +enum { + FP_SAVE_NONE = 0, + FP_SAVE_VECTOR = -1, + FP_SAVE_SCALAR = 1, +}; + +/** + * resume - resume execution of a task + * @prev: The task previously executed. + * @next: The task to begin executing. + * @next_ti: task_thread_info(next). + * @fp_save: Which, if any, FP context to save for prev. + * + * This function is used whilst scheduling to save the context of prev & load + * the context of next. Returns prev. */ -extern asmlinkage void *resume(void *last, void *next, void *next_ti, u32 __usedfpu); +extern asmlinkage struct task_struct *resume(struct task_struct *prev, + struct task_struct *next, struct thread_info *next_ti, + s32 fp_save); extern unsigned int ll_bit; extern struct task_struct *ll_task; @@ -30,7 +46,7 @@ extern struct task_struct *ll_task; #ifdef CONFIG_MIPS_MT_FPAFF /* - * Handle the scheduler resume end of FPU affinity management. We do this + * Handle the scheduler resume end of FPU affinity management. We do this * inline to try to keep the overhead down. If we have been forced to run on * a "CPU" with an FPU because of a previous high level of FP computation, * but did not actually use the FPU during the most recent time-slice (CU1 @@ -66,17 +82,38 @@ do { \ #define switch_to(prev, next, last) \ do { \ - u32 __usedfpu; \ + u32 __c0_stat; \ + s32 __fpsave = FP_SAVE_NONE; \ __mips_mt_fpaff_switch_to(prev); \ if (cpu_has_dsp) \ __save_dsp(prev); \ + if (cop2_present && (KSTK_STATUS(prev) & ST0_CU2)) { \ + if (cop2_lazy_restore) \ + KSTK_STATUS(prev) &= ~ST0_CU2; \ + __c0_stat = read_c0_status(); \ + write_c0_status(__c0_stat | ST0_CU2); \ + cop2_save(&prev->thread.cp2); \ + write_c0_status(__c0_stat & ~ST0_CU2); \ + } \ __clear_software_ll_bit(); \ - __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU); \ - (last) = resume(prev, next, task_thread_info(next), __usedfpu); \ + if (test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU)) \ + __fpsave = FP_SAVE_SCALAR; \ + if (test_and_clear_tsk_thread_flag(prev, TIF_USEDMSA)) \ + __fpsave = FP_SAVE_VECTOR; \ + (last) = resume(prev, next, task_thread_info(next), __fpsave); \ + disable_msa(); \ } while (0) #define finish_arch_switch(prev) \ do { \ + u32 __c0_stat; \ + if (cop2_present && !cop2_lazy_restore && \ + (KSTK_STATUS(current) & ST0_CU2)) { \ + __c0_stat = read_c0_status(); \ + write_c0_status(__c0_stat | ST0_CU2); \ + cop2_restore(¤t->thread.cp2); \ + write_c0_status(__c0_stat & ~ST0_CU2); \ + } \ if (cpu_has_dsp) \ __restore_dsp(current); \ if (cpu_has_userlocal) \ diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h new file mode 100644 index 00000000000..17960fe7a8c --- /dev/null +++ b/arch/mips/include/asm/syscall.h @@ -0,0 +1,145 @@ +/* + * Access to user system call parameters and results + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * See asm-generic/syscall.h for descriptions of what we must do here. + * + * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org> + */ + +#ifndef __ASM_MIPS_SYSCALL_H +#define __ASM_MIPS_SYSCALL_H + +#include <linux/compiler.h> +#include <uapi/linux/audit.h> +#include <linux/elf-em.h> +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/uaccess.h> +#include <asm/ptrace.h> +#include <asm/unistd.h> + +#ifndef __NR_syscall /* Only defined if _MIPS_SIM == _MIPS_SIM_ABI32 */ +#define __NR_syscall 4000 +#endif + +static inline long syscall_get_nr(struct task_struct *task, + struct pt_regs *regs) +{ + /* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */ + if ((config_enabled(CONFIG_32BIT) || + test_tsk_thread_flag(task, TIF_32BIT_REGS)) && + (regs->regs[2] == __NR_syscall)) + return regs->regs[4]; + else + return regs->regs[2]; +} + +static inline unsigned long mips_get_syscall_arg(unsigned long *arg, + struct task_struct *task, struct pt_regs *regs, unsigned int n) +{ + unsigned long usp __maybe_unused = regs->regs[29]; + + switch (n) { + case 0: case 1: case 2: case 3: + *arg = regs->regs[4 + n]; + + return 0; + +#ifdef CONFIG_32BIT + case 4: case 5: case 6: case 7: + return get_user(*arg, (int *)usp + n); +#endif + +#ifdef CONFIG_64BIT + case 4: case 5: case 6: case 7: +#ifdef CONFIG_MIPS32_O32 + if (test_thread_flag(TIF_32BIT_REGS)) + return get_user(*arg, (int *)usp + n); + else +#endif + *arg = regs->regs[4 + n]; + + return 0; +#endif + + default: + BUG(); + } + + unreachable(); +} + +static inline long syscall_get_return_value(struct task_struct *task, + struct pt_regs *regs) +{ + return regs->regs[2]; +} + +static inline void syscall_rollback(struct task_struct *task, + struct pt_regs *regs) +{ + /* Do nothing */ +} + +static inline void syscall_set_return_value(struct task_struct *task, + struct pt_regs *regs, + int error, long val) +{ + if (error) { + regs->regs[2] = -error; + regs->regs[7] = -1; + } else { + regs->regs[2] = val; + regs->regs[7] = 0; + } +} + +static inline void syscall_get_arguments(struct task_struct *task, + struct pt_regs *regs, + unsigned int i, unsigned int n, + unsigned long *args) +{ + int ret; + /* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */ + if ((config_enabled(CONFIG_32BIT) || + test_tsk_thread_flag(task, TIF_32BIT_REGS)) && + (regs->regs[2] == __NR_syscall)) { + i++; + n++; + } + + while (n--) + ret |= mips_get_syscall_arg(args++, task, regs, i++); + + /* + * No way to communicate an error because this is a void function. + */ +#if 0 + return ret; +#endif +} + +extern const unsigned long sys_call_table[]; +extern const unsigned long sys32_call_table[]; +extern const unsigned long sysn32_call_table[]; + +static inline int syscall_get_arch(void) +{ + int arch = EM_MIPS; +#ifdef CONFIG_64BIT + if (!test_thread_flag(TIF_32BIT_REGS)) + arch |= __AUDIT_ARCH_64BIT; + if (test_thread_flag(TIF_32BIT_ADDR)) + arch |= __AUDIT_ARCH_CONVENTION_MIPS64_N32; +#endif +#if defined(__LITTLE_ENDIAN) + arch |= __AUDIT_ARCH_LE; +#endif + return arch; +} + +#endif /* __ASM_MIPS_SYSCALL_H */ diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index b2050b9e64b..7de865805de 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -44,7 +44,7 @@ struct thread_info { #define INIT_THREAD_INFO(tsk) \ { \ .task = &tsk, \ - .exec_domain = &default_exec_domain, \ + .exec_domain = &default_exec_domain, \ .flags = _TIF_FIXADE, \ .cpu = 0, \ .preempt_count = INIT_PREEMPT_COUNT, \ @@ -58,8 +58,12 @@ struct thread_info { #define init_stack (init_thread_union.stack) /* How to get the thread information struct from C. */ -register struct thread_info *__current_thread_info __asm__("$28"); -#define current_thread_info() __current_thread_info +static inline struct thread_info *current_thread_info(void) +{ + register struct thread_info *__current_thread_info __asm__("$28"); + + return __current_thread_info; +} #endif /* !__ASSEMBLY__ */ @@ -88,8 +92,6 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define STACK_WARN (THREAD_SIZE / 8) -#define PREEMPT_ACTIVE 0x10000000 - /* * thread information flags * - these are process state flags that various assembly files may need to @@ -105,12 +107,17 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ #define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ +#define TIF_NOHZ 19 /* in adaptive nohz mode */ #define TIF_FIXADE 20 /* Fix address errors in software */ #define TIF_LOGADE 21 /* Log address errors to syslog */ -#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */ +#define TIF_32BIT_REGS 22 /* 32-bit general purpose registers */ #define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */ #define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */ #define TIF_LOAD_WATCH 25 /* If set, load watch registers */ +#define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */ +#define TIF_32BIT_FPREGS 27 /* 32-bit floating point registers */ +#define TIF_USEDMSA 29 /* MSA has been used this quantum */ +#define TIF_MSA_CTX_LIVE 30 /* MSA context must be preserved */ #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) @@ -120,22 +127,56 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define _TIF_SECCOMP (1<<TIF_SECCOMP) #define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_USEDFPU (1<<TIF_USEDFPU) +#define _TIF_NOHZ (1<<TIF_NOHZ) #define _TIF_FIXADE (1<<TIF_FIXADE) #define _TIF_LOGADE (1<<TIF_LOGADE) #define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS) #define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR) #define _TIF_FPUBOUND (1<<TIF_FPUBOUND) #define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH) +#define _TIF_32BIT_FPREGS (1<<TIF_32BIT_FPREGS) +#define _TIF_USEDMSA (1<<TIF_USEDMSA) +#define _TIF_MSA_CTX_LIVE (1<<TIF_MSA_CTX_LIVE) +#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT) + +#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \ + _TIF_SYSCALL_AUDIT | \ + _TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP) /* work to do in syscall_trace_leave() */ -#define _TIF_WORK_SYSCALL_EXIT (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT) +#define _TIF_WORK_SYSCALL_EXIT (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \ + _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT) /* work to do on interrupt/exception return */ #define _TIF_WORK_MASK \ (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME) /* work to do on any return to u-space */ -#define _TIF_ALLWORK_MASK (_TIF_WORK_MASK | _TIF_WORK_SYSCALL_EXIT) +#define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \ + _TIF_WORK_SYSCALL_EXIT | \ + _TIF_SYSCALL_TRACEPOINT) -#endif /* __KERNEL__ */ +/* + * We stash processor id into a COP0 register to retrieve it fast + * at kernel exception entry. + */ +#if defined(CONFIG_MIPS_PGD_C0_CONTEXT) +#define SMP_CPUID_REG 20, 0 /* XCONTEXT */ +#define ASM_SMP_CPUID_REG $20 +#define SMP_CPUID_PTRSHIFT 48 +#else +#define SMP_CPUID_REG 4, 0 /* CONTEXT */ +#define ASM_SMP_CPUID_REG $4 +#define SMP_CPUID_PTRSHIFT 23 +#endif + +#ifdef CONFIG_64BIT +#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 3) +#else +#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 2) +#endif + +#define ASM_CPUID_MFC0 MFC0 +#define UASM_i_CPUID_MFC0 UASM_i_MFC0 +#endif /* __KERNEL__ */ #endif /* _ASM_THREAD_INFO_H */ diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index 761f2e92119..8f3047d611e 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -6,8 +6,8 @@ * include/asm-mips/time.h * header file for the new style time.c file and time services. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ @@ -52,13 +52,12 @@ extern int (*perf_irq)(void); */ extern unsigned int __weak get_c0_compare_int(void); extern int r4k_clockevent_init(void); +extern int gic_clockevent_init(void); static inline int mips_clockevent_init(void) { -#ifdef CONFIG_MIPS_MT_SMTC - extern int smtc_clockevent_init(void); - - return smtc_clockevent_init(); +#if defined(CONFIG_CEVT_GIC) + return (gic_clockevent_init() | r4k_clockevent_init()); #elif defined(CONFIG_CEVT_R4K) return r4k_clockevent_init(); #else @@ -69,9 +68,7 @@ static inline int mips_clockevent_init(void) /* * Initialize the count register as a clocksource */ -#ifdef CONFIG_CSRC_R4K extern int init_r4k_clocksource(void); -#endif static inline int init_mips_clocksource(void) { diff --git a/arch/mips/include/asm/timex.h b/arch/mips/include/asm/timex.h index 6529704aa73..b05bb70a2e4 100644 --- a/arch/mips/include/asm/timex.h +++ b/arch/mips/include/asm/timex.h @@ -4,13 +4,19 @@ * for more details. * * Copyright (C) 1998, 1999, 2003 by Ralf Baechle + * Copyright (C) 2014 by Maciej W. Rozycki */ #ifndef _ASM_TIMEX_H #define _ASM_TIMEX_H #ifdef __KERNEL__ +#include <linux/compiler.h> + +#include <asm/cpu.h> +#include <asm/cpu-features.h> #include <asm/mipsregs.h> +#include <asm/cpu-type.h> /* * This is the clock rate of the i8253 PIT. A MIPS system may not have @@ -33,10 +39,64 @@ typedef unsigned int cycles_t; +/* + * On R4000/R4400 before version 5.0 an erratum exists such that if the + * cycle counter is read in the exact moment that it is matching the + * compare register, no interrupt will be generated. + * + * There is a suggested workaround and also the erratum can't strike if + * the compare interrupt isn't being used as the clock source device. + * However for now the implementaton of this function doesn't get these + * fine details right. + */ +static inline int can_use_mips_counter(unsigned int prid) +{ + int comp = (prid & PRID_COMP_MASK) != PRID_COMP_LEGACY; + + if (__builtin_constant_p(cpu_has_counter) && !cpu_has_counter) + return 0; + else if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) + return 1; + else if (likely(!__builtin_constant_p(cpu_has_mips_r) && comp)) + return 1; + /* Make sure we don't peek at cpu_data[0].options in the fast path! */ + if (!__builtin_constant_p(cpu_has_counter)) + asm volatile("" : "=m" (cpu_data[0].options)); + if (likely(cpu_has_counter && + prid >= (PRID_IMP_R4000 | PRID_REV_ENCODE_44(5, 0)))) + return 1; + else + return 0; +} + static inline cycles_t get_cycles(void) { - return 0; + if (can_use_mips_counter(read_c0_prid())) + return read_c0_count(); + else + return 0; /* no usable counter */ +} + +/* + * Like get_cycles - but where c0_count is not available we desperately + * use c0_random in an attempt to get at least a little bit of entropy. + * + * R6000 and R6000A neither have a count register nor a random register. + * That leaves no entropy source in the CPU itself. + */ +static inline unsigned long random_get_entropy(void) +{ + unsigned int prid = read_c0_prid(); + unsigned int imp = prid & PRID_IMP_MASK; + + if (can_use_mips_counter(prid)) + return read_c0_count(); + else if (likely(imp != PRID_IMP_R6000 && imp != PRID_IMP_R6000A)) + return read_c0_random(); + else + return 0; /* no usable register */ } +#define random_get_entropy random_get_entropy #endif /* __KERNEL__ */ diff --git a/arch/mips/include/asm/tlb.h b/arch/mips/include/asm/tlb.h index 80d9dfcf1e8..4a2349302b5 100644 --- a/arch/mips/include/asm/tlb.h +++ b/arch/mips/include/asm/tlb.h @@ -5,7 +5,7 @@ * MIPS doesn't need any special per-pte or per-vma handling, except * we need to flush cache for area to be unmapped. */ -#define tlb_start_vma(tlb, vma) \ +#define tlb_start_vma(tlb, vma) \ do { \ if (!tlb->fullmm) \ flush_cache_range(vma, vma->vm_start, vma->vm_end); \ @@ -18,6 +18,10 @@ */ #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) +#define UNIQUE_ENTRYHI(idx) \ + ((CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) | \ + (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0)) + #include <asm-generic/tlb.h> #endif /* __ASM_TLB_H */ diff --git a/arch/mips/include/asm/topology.h b/arch/mips/include/asm/topology.h index 259145e07e9..20ea4859c82 100644 --- a/arch/mips/include/asm/topology.h +++ b/arch/mips/include/asm/topology.h @@ -10,8 +10,4 @@ #include <topology.h> -#ifdef CONFIG_SMP -#define smt_capable() (smp_num_siblings > 1) -#endif - #endif /* __ASM_TOPOLOGY_H */ diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h index 420ca06b2f4..f41cf3ee82a 100644 --- a/arch/mips/include/asm/traps.h +++ b/arch/mips/include/asm/traps.h @@ -14,7 +14,7 @@ /* * Possible status responses for a board_be_handler backend. */ -#define MIPS_BE_DISCARD 0 /* return with no action */ +#define MIPS_BE_DISCARD 0 /* return with no action */ #define MIPS_BE_FIXUP 1 /* return to the fixup code */ #define MIPS_BE_FATAL 2 /* treat as an unrecoverable error */ diff --git a/arch/mips/include/asm/txx9/jmr3927.h b/arch/mips/include/asm/txx9/jmr3927.h index 8808d7f82da..aab959dc30b 100644 --- a/arch/mips/include/asm/txx9/jmr3927.h +++ b/arch/mips/include/asm/txx9/jmr3927.h @@ -40,7 +40,7 @@ #define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO) #define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000) -#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000) +#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000) #define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000) #define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000) #define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000) @@ -115,9 +115,9 @@ #define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ #define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ -#define JMR3927_IRQ_IRC TXX9_IRQ_BASE -#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) -#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) +#define JMR3927_IRQ_IRC TXX9_IRQ_BASE +#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) +#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) #define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0) #define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1) @@ -127,11 +127,11 @@ #define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5) #define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0) #define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1) -#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch)) +#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch)) #define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA) #define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO) #define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI) -#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch)) +#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch)) #define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA) #define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB) #define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC) @@ -147,7 +147,7 @@ #define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 /* Clocks */ -#define JMR3927_CORECLK 132710400 /* 132.7MHz */ +#define JMR3927_CORECLK 132710400 /* 132.7MHz */ /* * TX3927 Pin Configuration: diff --git a/arch/mips/include/asm/txx9/rbtx4927.h b/arch/mips/include/asm/txx9/rbtx4927.h index b2adab3d1ac..4060ad26ca9 100644 --- a/arch/mips/include/asm/txx9/rbtx4927.h +++ b/arch/mips/include/asm/txx9/rbtx4927.h @@ -1,6 +1,6 @@ /* * Author: MontaVista Software, Inc. - * source@mvista.com + * source@mvista.com * * Copyright 2001-2002 MontaVista Software Inc. * @@ -38,7 +38,7 @@ #define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000) #define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006) #define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000) -#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000) +#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000) #define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002) #define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006) #define RBTX4927_BRAMRTC_BASE (IO_BASE + TXX9_CE(2) + 0x00010000) @@ -50,7 +50,7 @@ #define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR) #define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR) #define rbtx4927_softint_addr ((__u8 __iomem *)RBTX4927_SOFTINT_ADDR) -#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR) +#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR) #define rbtx4927_softresetlock_addr \ ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR) #define rbtx4927_pcireset_addr ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR) diff --git a/arch/mips/include/asm/txx9/rbtx4938.h b/arch/mips/include/asm/txx9/rbtx4938.h index 9f0441a2812..9c969dd3c6e 100644 --- a/arch/mips/include/asm/txx9/rbtx4938.h +++ b/arch/mips/include/asm/txx9/rbtx4938.h @@ -36,7 +36,7 @@ #define RBTX4938_SPICS_ADDR (IO_BASE + TXX9_CE(2) + 0x00005002) #define RBTX4938_SFPWR_ADDR (IO_BASE + TXX9_CE(2) + 0x00005008) #define RBTX4938_SFVOL_ADDR (IO_BASE + TXX9_CE(2) + 0x0000500a) -#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000) +#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000) #define RBTX4938_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x00007002) #define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004) #define RBTX4938_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000) @@ -78,7 +78,7 @@ #define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR) #define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR) #define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR) -#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR) +#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR) #define rbtx4938_softresetlock_addr \ ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR) #define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR) @@ -94,7 +94,7 @@ /* These are the virtual IRQ numbers, we divide all IRQ's into * 'spaces', the 'space' determines where and how to enable/disable - * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new + * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new * IRQ hardware is supported. */ #define RBTX4938_NR_IRQ_IOC 8 @@ -103,18 +103,18 @@ #define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR) #define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC) -#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR) -#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) -#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) -#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) +#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR) +#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) +#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) +#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) #define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n)) #define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) #define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) #define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) -#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n)) +#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n)) #define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC) -#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR) -#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME) +#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR) +#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME) #define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC) #define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME) #define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1) diff --git a/arch/mips/include/asm/txx9/rbtx4939.h b/arch/mips/include/asm/txx9/rbtx4939.h index e517899794a..6157bfd9084 100644 --- a/arch/mips/include/asm/txx9/rbtx4939.h +++ b/arch/mips/include/asm/txx9/rbtx4939.h @@ -17,7 +17,7 @@ /* Address map */ #define RBTX4939_IOC_REG_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000) -#define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000) +#define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000) #define RBTX4939_IOC_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000002) #define RBTX4939_CONFIG1_ADDR (IO_BASE + TXX9_CE(1) + 0x00000004) #define RBTX4939_CONFIG2_ADDR (IO_BASE + TXX9_CE(1) + 0x00000006) @@ -46,9 +46,9 @@ #define RBTX4939_VPSIN_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500c) #define RBTX4939_7SEG_ADDR(s, ch) \ (IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2) -#define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000) +#define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000) #define RBTX4939_RESETEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00007002) -#define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004) +#define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004) #define RBTX4939_ETHER_BASE (IO_BASE + TXX9_CE(1) + 0x00020000) /* Ethernet port address */ @@ -77,11 +77,11 @@ #define RBTX4939_PE2_CIR 0x08 #define RBTX4939_PE2_SPI 0x10 #define RBTX4939_PE2_GPIO 0x20 -#define RBTX4939_PE3_VP 0x01 +#define RBTX4939_PE3_VP 0x01 #define RBTX4939_PE3_VP_P 0x02 #define RBTX4939_PE3_VP_S 0x04 -#define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR) +#define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR) #define rbtx4939_ioc_rev_addr ((u8 __iomem *)RBTX4939_IOC_REV_ADDR) #define rbtx4939_config1_addr ((u8 __iomem *)RBTX4939_CONFIG1_ADDR) #define rbtx4939_config2_addr ((u8 __iomem *)RBTX4939_CONFIG2_ADDR) @@ -110,9 +110,9 @@ #define rbtx4939_vpsin_addr ((u8 __iomem *)RBTX4939_VPSIN_ADDR) #define rbtx4939_7seg_addr(s, ch) \ ((u8 __iomem *)RBTX4939_7SEG_ADDR(s, ch)) -#define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR) +#define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR) #define rbtx4939_reseten_addr ((u8 __iomem *)RBTX4939_RESETEN_ADDR) -#define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR) +#define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR) /* * IRQ mappings diff --git a/arch/mips/include/asm/txx9/smsc_fdc37m81x.h b/arch/mips/include/asm/txx9/smsc_fdc37m81x.h index d1d6332b4ca..926d08f1846 100644 --- a/arch/mips/include/asm/txx9/smsc_fdc37m81x.h +++ b/arch/mips/include/asm/txx9/smsc_fdc37m81x.h @@ -18,43 +18,43 @@ /* Common Registers */ #define SMSC_FDC37M81X_CONFIG_INDEX 0x00 #define SMSC_FDC37M81X_CONFIG_DATA 0x01 -#define SMSC_FDC37M81X_CONF 0x02 -#define SMSC_FDC37M81X_INDEX 0x03 -#define SMSC_FDC37M81X_DNUM 0x07 -#define SMSC_FDC37M81X_DID 0x20 -#define SMSC_FDC37M81X_DREV 0x21 -#define SMSC_FDC37M81X_PCNT 0x22 -#define SMSC_FDC37M81X_PMGT 0x23 -#define SMSC_FDC37M81X_OSC 0x24 -#define SMSC_FDC37M81X_CONFPA0 0x26 -#define SMSC_FDC37M81X_CONFPA1 0x27 -#define SMSC_FDC37M81X_TEST4 0x2B -#define SMSC_FDC37M81X_TEST5 0x2C -#define SMSC_FDC37M81X_TEST1 0x2D -#define SMSC_FDC37M81X_TEST2 0x2E -#define SMSC_FDC37M81X_TEST3 0x2F +#define SMSC_FDC37M81X_CONF 0x02 +#define SMSC_FDC37M81X_INDEX 0x03 +#define SMSC_FDC37M81X_DNUM 0x07 +#define SMSC_FDC37M81X_DID 0x20 +#define SMSC_FDC37M81X_DREV 0x21 +#define SMSC_FDC37M81X_PCNT 0x22 +#define SMSC_FDC37M81X_PMGT 0x23 +#define SMSC_FDC37M81X_OSC 0x24 +#define SMSC_FDC37M81X_CONFPA0 0x26 +#define SMSC_FDC37M81X_CONFPA1 0x27 +#define SMSC_FDC37M81X_TEST4 0x2B +#define SMSC_FDC37M81X_TEST5 0x2C +#define SMSC_FDC37M81X_TEST1 0x2D +#define SMSC_FDC37M81X_TEST2 0x2E +#define SMSC_FDC37M81X_TEST3 0x2F /* Logical device numbers */ -#define SMSC_FDC37M81X_FDD 0x00 -#define SMSC_FDC37M81X_PARALLEL 0x03 -#define SMSC_FDC37M81X_SERIAL1 0x04 -#define SMSC_FDC37M81X_SERIAL2 0x05 -#define SMSC_FDC37M81X_KBD 0x07 -#define SMSC_FDC37M81X_AUXIO 0x08 -#define SMSC_FDC37M81X_NONE 0xff +#define SMSC_FDC37M81X_FDD 0x00 +#define SMSC_FDC37M81X_PARALLEL 0x03 +#define SMSC_FDC37M81X_SERIAL1 0x04 +#define SMSC_FDC37M81X_SERIAL2 0x05 +#define SMSC_FDC37M81X_KBD 0x07 +#define SMSC_FDC37M81X_AUXIO 0x08 +#define SMSC_FDC37M81X_NONE 0xff /* Logical device Config Registers */ -#define SMSC_FDC37M81X_ACTIVE 0x30 +#define SMSC_FDC37M81X_ACTIVE 0x30 #define SMSC_FDC37M81X_BASEADDR0 0x60 #define SMSC_FDC37M81X_BASEADDR1 0x61 -#define SMSC_FDC37M81X_INT 0x70 -#define SMSC_FDC37M81X_INT2 0x72 -#define SMSC_FDC37M81X_LDCR_F0 0xF0 +#define SMSC_FDC37M81X_INT 0x70 +#define SMSC_FDC37M81X_INT2 0x72 +#define SMSC_FDC37M81X_LDCR_F0 0xF0 /* Chip Config Values */ #define SMSC_FDC37M81X_CONFIG_ENTER 0x55 #define SMSC_FDC37M81X_CONFIG_EXIT 0xaa -#define SMSC_FDC37M81X_CHIP_ID 0x4d +#define SMSC_FDC37M81X_CHIP_ID 0x4d unsigned long smsc_fdc37m81x_init(unsigned long port); diff --git a/arch/mips/include/asm/txx9/tx3927.h b/arch/mips/include/asm/txx9/tx3927.h index dc30c8d4206..149fab4f832 100644 --- a/arch/mips/include/asm/txx9/tx3927.h +++ b/arch/mips/include/asm/txx9/tx3927.h @@ -8,8 +8,8 @@ #ifndef __ASM_TXX9_TX3927_H #define __ASM_TXX9_TX3927_H -#define TX3927_REG_BASE 0xfffe0000UL -#define TX3927_REG_SIZE 0x00010000 +#define TX3927_REG_BASE 0xfffe0000UL +#define TX3927_REG_SIZE 0x00010000 #define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000) #define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000) #define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000) @@ -191,8 +191,8 @@ struct tx3927_ccfg_reg { #define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2) #define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4) #define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5) -#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6) -#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7) +#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6) +#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7) #define TX3927_DMA_CCR_MEMIO 0x00000002 #define TX3927_DMA_CCR_ONEAD 0x00000001 @@ -250,7 +250,7 @@ struct tx3927_ccfg_reg { /* see PCI_BASE_ADDRESS_XXX in linux/pci.h */ /* bits for PBAPMC */ -#define TX3927_PCIC_PBAPMC_RPBA 0x00000004 +#define TX3927_PCIC_PBAPMC_RPBA 0x00000004 #define TX3927_PCIC_PBAPMC_PBAEN 0x00000002 #define TX3927_PCIC_PBAPMC_BMCEN 0x00000001 @@ -282,7 +282,7 @@ struct tx3927_ccfg_reg { #define TX3927_CCFG_TLBOFF 0x00020000 #define TX3927_CCFG_BEOW 0x00010000 #define TX3927_CCFG_WR 0x00008000 -#define TX3927_CCFG_TOE 0x00004000 +#define TX3927_CCFG_TOE 0x00004000 #define TX3927_CCFG_PCIXARB 0x00002000 #define TX3927_CCFG_PCI3 0x00001000 #define TX3927_CCFG_PSNP 0x00000800 @@ -301,8 +301,8 @@ struct tx3927_ccfg_reg { #define TX3927_PCFG_SELALL 0x0003ffff #define TX3927_PCFG_SELCS 0x00020000 #define TX3927_PCFG_SELDSF 0x00010000 -#define TX3927_PCFG_SELSIOC_ALL 0x0000c000 -#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch)) +#define TX3927_PCFG_SELSIOC_ALL 0x0000c000 +#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch)) #define TX3927_PCFG_SELSIO_ALL 0x00003000 #define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch)) #define TX3927_PCFG_SELTMR_ALL 0x00000e00 diff --git a/arch/mips/include/asm/txx9/tx4927.h b/arch/mips/include/asm/txx9/tx4927.h index 18c98c52afd..284eea752d5 100644 --- a/arch/mips/include/asm/txx9/tx4927.h +++ b/arch/mips/include/asm/txx9/tx4927.h @@ -1,6 +1,6 @@ /* * Author: MontaVista Software, Inc. - * source@mvista.com + * source@mvista.com * * Copyright 2001-2006 MontaVista Software Inc. * @@ -33,11 +33,11 @@ #include <asm/txx9/tx4927pcic.h> #ifdef CONFIG_64BIT -#define TX4927_REG_BASE 0xffffffffff1f0000UL +#define TX4927_REG_BASE 0xffffffffff1f0000UL #else -#define TX4927_REG_BASE 0xff1f0000UL +#define TX4927_REG_BASE 0xff1f0000UL #endif -#define TX4927_REG_SIZE 0x00010000 +#define TX4927_REG_SIZE 0x00010000 #define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000) #define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000) @@ -118,10 +118,10 @@ struct tx4927_ccfg_reg { #define TX4927_CCFG_DIVMODE_2 (0x4 << 17) #define TX4927_CCFG_DIVMODE_3 (0x5 << 17) #define TX4927_CCFG_DIVMODE_4 (0x6 << 17) -#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17) +#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17) #define TX4927_CCFG_BEOW 0x00010000 #define TX4927_CCFG_WR 0x00008000 -#define TX4927_CCFG_TOE 0x00004000 +#define TX4927_CCFG_TOE 0x00004000 #define TX4927_CCFG_PCIARB 0x00002000 #define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 #define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 @@ -136,10 +136,10 @@ struct tx4927_ccfg_reg { /* PCFG : Pin Configuration */ #define TX4927_PCFG_SDCLKDLY_MASK 0x30000000 -#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28) +#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28) #define TX4927_PCFG_SYSCLKEN 0x08000000 -#define TX4927_PCFG_SDCLKEN_ALL 0x07800000 -#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) +#define TX4927_PCFG_SDCLKEN_ALL 0x07800000 +#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) #define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 #define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) #define TX4927_PCFG_SEL2 0x00000200 diff --git a/arch/mips/include/asm/txx9/tx4927pcic.h b/arch/mips/include/asm/txx9/tx4927pcic.h index c470b8a5fe5..9eab2698cae 100644 --- a/arch/mips/include/asm/txx9/tx4927pcic.h +++ b/arch/mips/include/asm/txx9/tx4927pcic.h @@ -93,7 +93,7 @@ struct tx4927_pcic_reg { /* bits for PBACFG */ #define TX4927_PCIC_PBACFG_FIXPA 0x00000008 -#define TX4927_PCIC_PBACFG_RPBA 0x00000004 +#define TX4927_PCIC_PBACFG_RPBA 0x00000004 #define TX4927_PCIC_PBACFG_PBAEN 0x00000002 #define TX4927_PCIC_PBACFG_BMCEN 0x00000001 @@ -165,7 +165,7 @@ struct tx4927_pcic_reg { #define TX4927_PCIC_PDMCFG_CHNEN 0x00000080 #define TX4927_PCIC_PDMCFG_XFRACT 0x00000040 #define TX4927_PCIC_PDMCFG_BSWAP 0x00000020 -#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c +#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c #define TX4927_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000 #define TX4927_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004 #define TX4927_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008 @@ -174,7 +174,7 @@ struct tx4927_pcic_reg { /* bits for PDMSTS */ #define TX4927_PCIC_PDMSTS_REQCNT_MASK 0x3f000000 -#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000 +#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000 #define TX4927_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000 #define TX4927_PCIC_PDMSTS_FIFORP_MASK 0x00030000 #define TX4927_PCIC_PDMSTS_ERRINT 0x00000800 diff --git a/arch/mips/include/asm/txx9/tx4938.h b/arch/mips/include/asm/txx9/tx4938.h index 8a178f186f7..6ca767ee646 100644 --- a/arch/mips/include/asm/txx9/tx4938.h +++ b/arch/mips/include/asm/txx9/tx4938.h @@ -16,11 +16,11 @@ #include <asm/txx9/tx4927.h> #ifdef CONFIG_64BIT -#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */ +#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */ #else -#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */ +#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */ #endif -#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */ +#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */ /* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */ #define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000) @@ -72,16 +72,16 @@ struct tx4938_ccfg_reg { #define TX4938_NUM_IR_DMA 4 #define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */ #define TX4938_IR_PIO 14 -#define TX4938_IR_PDMAC 15 +#define TX4938_IR_PDMAC 15 #define TX4938_IR_PCIC 16 #define TX4938_NUM_IR_TMR 3 #define TX4938_IR_TMR(n) (17 + (n)) -#define TX4938_IR_NDFMC 21 +#define TX4938_IR_NDFMC 21 #define TX4938_IR_PCIERR 22 #define TX4938_IR_PCIPME 23 #define TX4938_IR_ACLC 24 #define TX4938_IR_ACLCPME 25 -#define TX4938_IR_PCIC1 26 +#define TX4938_IR_PCIC1 26 #define TX4938_IR_SPI 31 #define TX4938_NUM_IR 32 /* multiplex */ @@ -105,10 +105,10 @@ struct tx4938_ccfg_reg { #define TX4938_CCFG_PCI1_66 0x00200000 #define TX4938_CCFG_DIVMODE_MASK 0x001e0000 #define TX4938_CCFG_DIVMODE_2 (0x4 << 17) -#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17) +#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17) #define TX4938_CCFG_DIVMODE_3 (0x5 << 17) #define TX4938_CCFG_DIVMODE_4 (0x6 << 17) -#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17) +#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17) #define TX4938_CCFG_DIVMODE_8 (0x0 << 17) #define TX4938_CCFG_DIVMODE_10 (0xb << 17) #define TX4938_CCFG_DIVMODE_12 (0x1 << 17) @@ -116,7 +116,7 @@ struct tx4938_ccfg_reg { #define TX4938_CCFG_DIVMODE_18 (0x9 << 17) #define TX4938_CCFG_BEOW 0x00010000 #define TX4938_CCFG_WR 0x00008000 -#define TX4938_CCFG_TOE 0x00004000 +#define TX4938_CCFG_TOE 0x00004000 #define TX4938_CCFG_PCIARB 0x00002000 #define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00 #define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10) @@ -141,10 +141,10 @@ struct tx4938_ccfg_reg { #define TX4938_PCFG_SPI_SEL 0x0800000000000000ULL #define TX4938_PCFG_NDF_SEL 0x0400000000000000ULL #define TX4938_PCFG_SDCLKDLY_MASK 0x30000000 -#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28) +#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28) #define TX4938_PCFG_SYSCLKEN 0x08000000 -#define TX4938_PCFG_SDCLKEN_ALL 0x07800000 -#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) +#define TX4938_PCFG_SDCLKEN_ALL 0x07800000 +#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) #define TX4938_PCFG_PCICLKEN_ALL 0x003f0000 #define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) #define TX4938_PCFG_SEL2 0x00000200 @@ -230,8 +230,8 @@ struct tx4938_ccfg_reg { #define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3) #define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4) #define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5) -#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6) -#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7) +#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6) +#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7) #define TX4938_DMA_CCR_MEMIO 0x00000002 #define TX4938_DMA_CCR_SNGAD 0x00000001 @@ -263,9 +263,9 @@ struct tx4938_ccfg_reg { #define TX4938_REV_PCODE() \ ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16) -#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits) +#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits) #define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits) -#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new) +#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new) #define TX4938_SDRAMC_CR(ch) TX4927_SDRAMC_CR(ch) #define TX4938_SDRAMC_BA(ch) TX4927_SDRAMC_BA(ch) diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h index d4f342cd593..6d667087f2a 100644 --- a/arch/mips/include/asm/txx9/tx4939.h +++ b/arch/mips/include/asm/txx9/tx4939.h @@ -14,11 +14,11 @@ #include <asm/txx9/tx4938.h> #ifdef CONFIG_64BIT -#define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */ +#define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */ #else -#define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */ +#define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */ #endif -#define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */ +#define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */ #define TX4939_ATA_REG(ch) (TX4939_REG_BASE + 0x3000 + (ch) * 0x1000) #define TX4939_NDFMC_REG (TX4939_REG_BASE + 0x5000) @@ -189,14 +189,14 @@ struct tx4939_vpc_desc { #define TX4939_IR_INT(n) (3 + (n)) #define TX4939_NUM_IR_ETH 2 #define TX4939_IR_ETH(n) ((n) ? 43 : 6) -#define TX4939_IR_VIDEO 7 +#define TX4939_IR_VIDEO 7 #define TX4939_IR_CIR 8 #define TX4939_NUM_IR_SIO 4 #define TX4939_IR_SIO(n) ((n) ? 43 + (n) : 9) /* 9,44-46 */ #define TX4939_NUM_IR_DMA 4 #define TX4939_IR_DMA(ch, n) (((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */ #define TX4939_IR_IRC 14 -#define TX4939_IR_PDMAC 15 +#define TX4939_IR_PDMAC 15 #define TX4939_NUM_IR_TMR 6 #define TX4939_IR_TMR(n) (((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */ #define TX4939_NUM_IR_ATA 2 @@ -210,10 +210,10 @@ struct tx4939_vpc_desc { #define TX4939_IR_I2C 33 #define TX4939_IR_SPI 34 #define TX4939_IR_PCIC 35 -#define TX4939_IR_PCIC1 36 +#define TX4939_IR_PCIC1 36 #define TX4939_IR_PCIERR 37 #define TX4939_IR_PCIPME 38 -#define TX4939_IR_NDFMC 39 +#define TX4939_IR_NDFMC 39 #define TX4939_IR_ACLCPME 40 #define TX4939_IR_RTC 41 #define TX4939_IR_RND 42 @@ -239,7 +239,7 @@ struct tx4939_vpc_desc { #define TX4939_CCFG_PCI66 0x00800000 #define TX4939_CCFG_PCIMODE 0x00400000 #define TX4939_CCFG_SSCG 0x00100000 -#define TX4939_CCFG_MULCLK_MASK 0x000e0000 +#define TX4939_CCFG_MULCLK_MASK 0x000e0000 #define TX4939_CCFG_MULCLK_8 (0x7 << 17) #define TX4939_CCFG_MULCLK_9 (0x0 << 17) #define TX4939_CCFG_MULCLK_10 (0x1 << 17) @@ -250,7 +250,7 @@ struct tx4939_vpc_desc { #define TX4939_CCFG_MULCLK_15 (0x6 << 17) #define TX4939_CCFG_BEOW 0x00010000 #define TX4939_CCFG_WR 0x00008000 -#define TX4939_CCFG_TOE 0x00004000 +#define TX4939_CCFG_TOE 0x00004000 #define TX4939_CCFG_PCIARB 0x00002000 #define TX4939_CCFG_YDIVMODE_MASK 0x00001c00 #define TX4939_CCFG_YDIVMODE_2 (0x0 << 10) @@ -275,7 +275,7 @@ struct tx4939_vpc_desc { #define TX4939_PCFG_I2CMODE 0x1000000000000000ULL #define TX4939_PCFG_I2SMODE_MASK 0x0c00000000000000ULL #define TX4939_PCFG_I2SMODE_GPIO 0x0c00000000000000ULL -#define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL +#define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL #define TX4939_PCFG_I2SMODE_I2S_ALT 0x0400000000000000ULL #define TX4939_PCFG_I2SMODE_ACLC 0x0000000000000000ULL #define TX4939_PCFG_SIO3MODE 0x0200000000000000ULL @@ -392,15 +392,15 @@ struct tx4939_vpc_desc { /* * CRYPTO */ -#define TX4939_CRYPTO_CSR_SAESO 0x08000000 -#define TX4939_CRYPTO_CSR_SAESI 0x04000000 -#define TX4939_CRYPTO_CSR_SDESO 0x02000000 -#define TX4939_CRYPTO_CSR_SDESI 0x01000000 +#define TX4939_CRYPTO_CSR_SAESO 0x08000000 +#define TX4939_CRYPTO_CSR_SAESI 0x04000000 +#define TX4939_CRYPTO_CSR_SDESO 0x02000000 +#define TX4939_CRYPTO_CSR_SDESI 0x01000000 #define TX4939_CRYPTO_CSR_INDXBST_MASK 0x00700000 #define TX4939_CRYPTO_CSR_INDXBST(n) ((n) << 20) -#define TX4939_CRYPTO_CSR_TOINT 0x00080000 -#define TX4939_CRYPTO_CSR_DCINT 0x00040000 -#define TX4939_CRYPTO_CSR_GBINT 0x00010000 +#define TX4939_CRYPTO_CSR_TOINT 0x00080000 +#define TX4939_CRYPTO_CSR_DCINT 0x00040000 +#define TX4939_CRYPTO_CSR_GBINT 0x00010000 #define TX4939_CRYPTO_CSR_INDXAST_MASK 0x0000e000 #define TX4939_CRYPTO_CSR_INDXAST(n) ((n) << 13) #define TX4939_CRYPTO_CSR_CSWAP_MASK 0x00001800 @@ -418,7 +418,7 @@ struct tx4939_vpc_desc { #define TX4939_CRYPTO_CSR_PDINT_END 0x00000040 #define TX4939_CRYPTO_CSR_PDINT_NEXT 0x00000080 #define TX4939_CRYPTO_CSR_PDINT_NONE 0x000000c0 -#define TX4939_CRYPTO_CSR_GINTE 0x00000008 +#define TX4939_CRYPTO_CSR_GINTE 0x00000008 #define TX4939_CRYPTO_CSR_RSTD 0x00000004 #define TX4939_CRYPTO_CSR_RSTC 0x00000002 #define TX4939_CRYPTO_CSR_ENCR 0x00000001 @@ -442,7 +442,7 @@ struct tx4939_vpc_desc { #define TX4939_CRYPTO_DESC_START 0x00000200 #define TX4939_CRYPTO_DESC_END 0x00000100 #define TX4939_CRYPTO_DESC_XOR 0x00000010 -#define TX4939_CRYPTO_DESC_LAST 0x00000008 +#define TX4939_CRYPTO_DESC_LAST 0x00000008 #define TX4939_CRYPTO_DESC_ERR_MASK 0x00000006 #define TX4939_CRYPTO_DESC_ERR_NONE 0x00000000 #define TX4939_CRYPTO_DESC_ERR_TOUT 0x00000002 @@ -457,7 +457,7 @@ struct tx4939_vpc_desc { #define TX4939_CRYPTO_NR_SET 6 -#define TX4939_CRYPTO_RCSR_INTE 0x00000008 +#define TX4939_CRYPTO_RCSR_INTE 0x00000008 #define TX4939_CRYPTO_RCSR_RST 0x00000004 #define TX4939_CRYPTO_RCSR_FIN 0x00000002 #define TX4939_CRYPTO_RCSR_ST 0x00000001 @@ -480,8 +480,8 @@ struct tx4939_vpc_desc { #define TX4939_VPC_CTRLA_PDINT_ALL 0x00000000 #define TX4939_VPC_CTRLA_PDINT_NEXT 0x00000010 #define TX4939_VPC_CTRLA_PDINT_NONE 0x00000030 -#define TX4939_VPC_CTRLA_VDVLDP 0x00000008 -#define TX4939_VPC_CTRLA_VDMODE 0x00000004 +#define TX4939_VPC_CTRLA_VDVLDP 0x00000008 +#define TX4939_VPC_CTRLA_VDMODE 0x00000004 #define TX4939_VPC_CTRLA_VDFOR 0x00000002 #define TX4939_VPC_CTRLA_ENVPC 0x00000001 @@ -512,9 +512,9 @@ struct tx4939_vpc_desc { ((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \ >> 32)) -#define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits) +#define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits) #define tx4939_ccfg_set(bits) tx4938_ccfg_set(bits) -#define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new) +#define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new) #define TX4939_EBUSC_CR(ch) TX4927_EBUSC_CR(ch) #define TX4939_EBUSC_BA(ch) TX4927_EBUSC_BA(ch) @@ -522,7 +522,7 @@ struct tx4939_vpc_desc { #define TX4939_EBUSC_WIDTH(ch) \ (16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1)) -/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2 (14.745MHz for MST 20MHz) */ +/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2 (14.745MHz for MST 20MHz) */ #define TX4939_SCLK0(mst) \ ((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2) diff --git a/arch/mips/include/asm/txx9tmr.h b/arch/mips/include/asm/txx9tmr.h index 67f70a8f09b..466a3def386 100644 --- a/arch/mips/include/asm/txx9tmr.h +++ b/arch/mips/include/asm/txx9tmr.h @@ -59,9 +59,9 @@ void txx9_clockevent_init(unsigned long baseaddr, int irq, void txx9_tmr_init(unsigned long baseaddr); #ifdef CONFIG_CPU_TX39XX -#define TXX9_TIMER_BITS 24 +#define TXX9_TIMER_BITS 24 #else -#define TXX9_TIMER_BITS 32 +#define TXX9_TIMER_BITS 32 #endif #endif /* __ASM_TXX9TMR_H */ diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h index 3b92efef56d..a1095109023 100644 --- a/arch/mips/include/asm/uaccess.h +++ b/arch/mips/include/asm/uaccess.h @@ -6,6 +6,7 @@ * Copyright (C) 1996, 1997, 1998, 1999, 2000, 03, 04 by Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 2007 Maciej W. Rozycki + * Copyright (C) 2014, Imagination Technologies Ltd. */ #ifndef _ASM_UACCESS_H #define _ASM_UACCESS_H @@ -13,6 +14,7 @@ #include <linux/kernel.h> #include <linux/errno.h> #include <linux/thread_info.h> +#include <asm/asm-eva.h> /* * The fs value determines whether argument validity checking should be @@ -23,7 +25,11 @@ */ #ifdef CONFIG_32BIT -#define __UA_LIMIT 0x80000000UL +#ifdef CONFIG_KVM_GUEST +#define __UA_LIMIT 0x40000000UL +#else +#define __UA_LIMIT 0x80000000UL +#endif #define __UA_ADDR ".word" #define __UA_LA "la" @@ -55,8 +61,13 @@ extern u64 __ua_limit; * address in this range it's the process's problem, not ours :-) */ +#ifdef CONFIG_KVM_GUEST +#define KERNEL_DS ((mm_segment_t) { 0x80000000UL }) +#define USER_DS ((mm_segment_t) { 0xC0000000UL }) +#else #define KERNEL_DS ((mm_segment_t) { 0UL }) #define USER_DS ((mm_segment_t) { __UA_LIMIT }) +#endif #define VERIFY_READ 0 #define VERIFY_WRITE 1 @@ -87,12 +98,12 @@ extern u64 __ua_limit; /* * access_ok: - Checks if a user space pointer is valid * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE. Note that - * %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe - * to write to a block, it is always safe to read from it. + * %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe + * to write to a block, it is always safe to read from it. * @addr: User space pointer to start of block to check * @size: Size of block to check * - * Context: User context only. This function may sleep. + * Context: User context only. This function may sleep. * * Checks if a pointer to a block of memory in user space is valid. * @@ -124,10 +135,10 @@ extern u64 __ua_limit; /* * put_user: - Write a simple value into user space. - * @x: Value to copy to user space. + * @x: Value to copy to user space. * @ptr: Destination address, in user space. * - * Context: User context only. This function may sleep. + * Context: User context only. This function may sleep. * * This macro copies a single simple value from kernel space to user * space. It supports simple types like char and int, but not larger @@ -138,15 +149,15 @@ extern u64 __ua_limit; * * Returns zero on success, or -EFAULT on error. */ -#define put_user(x,ptr) \ +#define put_user(x,ptr) \ __put_user_check((x), (ptr), sizeof(*(ptr))) /* * get_user: - Get a simple variable from user space. - * @x: Variable to store result. + * @x: Variable to store result. * @ptr: Source address, in user space. * - * Context: User context only. This function may sleep. + * Context: User context only. This function may sleep. * * This macro copies a single simple variable from user space to kernel * space. It supports simple types like char and int, but not larger @@ -163,10 +174,10 @@ extern u64 __ua_limit; /* * __put_user: - Write a simple value into user space, with less checking. - * @x: Value to copy to user space. + * @x: Value to copy to user space. * @ptr: Destination address, in user space. * - * Context: User context only. This function may sleep. + * Context: User context only. This function may sleep. * * This macro copies a single simple value from kernel space to user * space. It supports simple types like char and int, but not larger @@ -185,10 +196,10 @@ extern u64 __ua_limit; /* * __get_user: - Get a simple variable from user space, with less checking. - * @x: Variable to store result. + * @x: Variable to store result. * @ptr: Source address, in user space. * - * Context: User context only. This function may sleep. + * Context: User context only. This function may sleep. * * This macro copies a single simple variable from user space to kernel * space. It supports simple types like char and int, but not larger @@ -213,11 +224,44 @@ struct __large_struct { unsigned long buf[100]; }; * Yuck. We need two variants, one for 64bit operation and one * for 32 bit mode and old iron. */ +#ifndef CONFIG_EVA +#define __get_kernel_common(val, size, ptr) __get_user_common(val, size, ptr) +#else +/* + * Kernel specific functions for EVA. We need to use normal load instructions + * to read data from kernel when operating in EVA mode. We use these macros to + * avoid redefining __get_user_asm for EVA. + */ +#undef _loadd +#undef _loadw +#undef _loadh +#undef _loadb +#ifdef CONFIG_32BIT +#define _loadd _loadw +#else +#define _loadd(reg, addr) "ld " reg ", " addr +#endif +#define _loadw(reg, addr) "lw " reg ", " addr +#define _loadh(reg, addr) "lh " reg ", " addr +#define _loadb(reg, addr) "lb " reg ", " addr + +#define __get_kernel_common(val, size, ptr) \ +do { \ + switch (size) { \ + case 1: __get_data_asm(val, _loadb, ptr); break; \ + case 2: __get_data_asm(val, _loadh, ptr); break; \ + case 4: __get_data_asm(val, _loadw, ptr); break; \ + case 8: __GET_DW(val, _loadd, ptr); break; \ + default: __get_user_unknown(); break; \ + } \ +} while (0) +#endif + #ifdef CONFIG_32BIT -#define __GET_USER_DW(val, ptr) __get_user_asm_ll32(val, ptr) +#define __GET_DW(val, insn, ptr) __get_data_asm_ll32(val, insn, ptr) #endif #ifdef CONFIG_64BIT -#define __GET_USER_DW(val, ptr) __get_user_asm(val, "ld", ptr) +#define __GET_DW(val, insn, ptr) __get_data_asm(val, insn, ptr) #endif extern void __get_user_unknown(void); @@ -225,10 +269,10 @@ extern void __get_user_unknown(void); #define __get_user_common(val, size, ptr) \ do { \ switch (size) { \ - case 1: __get_user_asm(val, "lb", ptr); break; \ - case 2: __get_user_asm(val, "lh", ptr); break; \ - case 4: __get_user_asm(val, "lw", ptr); break; \ - case 8: __GET_USER_DW(val, ptr); break; \ + case 1: __get_data_asm(val, user_lb, ptr); break; \ + case 2: __get_data_asm(val, user_lh, ptr); break; \ + case 4: __get_data_asm(val, user_lw, ptr); break; \ + case 8: __GET_DW(val, user_ld, ptr); break; \ default: __get_user_unknown(); break; \ } \ } while (0) @@ -237,8 +281,12 @@ do { \ ({ \ int __gu_err; \ \ - __chk_user_ptr(ptr); \ - __get_user_common((x), size, ptr); \ + if (segment_eq(get_fs(), get_ds())) { \ + __get_kernel_common((x), size, ptr); \ + } else { \ + __chk_user_ptr(ptr); \ + __get_user_common((x), size, ptr); \ + } \ __gu_err; \ }) @@ -248,19 +296,24 @@ do { \ const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \ \ might_fault(); \ - if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) \ - __get_user_common((x), size, __gu_ptr); \ + if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) { \ + if (segment_eq(get_fs(), get_ds())) \ + __get_kernel_common((x), size, __gu_ptr); \ + else \ + __get_user_common((x), size, __gu_ptr); \ + } \ \ __gu_err; \ }) -#define __get_user_asm(val, insn, addr) \ +#define __get_data_asm(val, insn, addr) \ { \ long __gu_tmp; \ \ __asm__ __volatile__( \ - "1: " insn " %1, %3 \n" \ + "1: "insn("%1", "%3")" \n" \ "2: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "3: li %0, %4 \n" \ " j 2b \n" \ @@ -277,7 +330,7 @@ do { \ /* * Get a long long 64 using 32 bit registers. */ -#define __get_user_asm_ll32(val, addr) \ +#define __get_data_asm_ll32(val, insn, addr) \ { \ union { \ unsigned long long l; \ @@ -285,9 +338,11 @@ do { \ } __gu_tmp; \ \ __asm__ __volatile__( \ - "1: lw %1, (%3) \n" \ - "2: lw %D1, 4(%3) \n" \ - "3: .section .fixup,\"ax\" \n" \ + "1: " insn("%1", "(%3)")" \n" \ + "2: " insn("%D1", "4(%3)")" \n" \ + "3: \n" \ + " .insn \n" \ + " .section .fixup,\"ax\" \n" \ "4: li %0, %4 \n" \ " move %1, $0 \n" \ " move %D1, $0 \n" \ @@ -303,30 +358,73 @@ do { \ (val) = __gu_tmp.t; \ } +#ifndef CONFIG_EVA +#define __put_kernel_common(ptr, size) __put_user_common(ptr, size) +#else +/* + * Kernel specific functions for EVA. We need to use normal load instructions + * to read data from kernel when operating in EVA mode. We use these macros to + * avoid redefining __get_data_asm for EVA. + */ +#undef _stored +#undef _storew +#undef _storeh +#undef _storeb +#ifdef CONFIG_32BIT +#define _stored _storew +#else +#define _stored(reg, addr) "ld " reg ", " addr +#endif + +#define _storew(reg, addr) "sw " reg ", " addr +#define _storeh(reg, addr) "sh " reg ", " addr +#define _storeb(reg, addr) "sb " reg ", " addr + +#define __put_kernel_common(ptr, size) \ +do { \ + switch (size) { \ + case 1: __put_data_asm(_storeb, ptr); break; \ + case 2: __put_data_asm(_storeh, ptr); break; \ + case 4: __put_data_asm(_storew, ptr); break; \ + case 8: __PUT_DW(_stored, ptr); break; \ + default: __put_user_unknown(); break; \ + } \ +} while(0) +#endif + /* * Yuck. We need two variants, one for 64bit operation and one * for 32 bit mode and old iron. */ #ifdef CONFIG_32BIT -#define __PUT_USER_DW(ptr) __put_user_asm_ll32(ptr) +#define __PUT_DW(insn, ptr) __put_data_asm_ll32(insn, ptr) #endif #ifdef CONFIG_64BIT -#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr) +#define __PUT_DW(insn, ptr) __put_data_asm(insn, ptr) #endif +#define __put_user_common(ptr, size) \ +do { \ + switch (size) { \ + case 1: __put_data_asm(user_sb, ptr); break; \ + case 2: __put_data_asm(user_sh, ptr); break; \ + case 4: __put_data_asm(user_sw, ptr); break; \ + case 8: __PUT_DW(user_sd, ptr); break; \ + default: __put_user_unknown(); break; \ + } \ +} while (0) + #define __put_user_nocheck(x, ptr, size) \ ({ \ __typeof__(*(ptr)) __pu_val; \ int __pu_err = 0; \ \ - __chk_user_ptr(ptr); \ __pu_val = (x); \ - switch (size) { \ - case 1: __put_user_asm("sb", ptr); break; \ - case 2: __put_user_asm("sh", ptr); break; \ - case 4: __put_user_asm("sw", ptr); break; \ - case 8: __PUT_USER_DW(ptr); break; \ - default: __put_user_unknown(); break; \ + if (segment_eq(get_fs(), get_ds())) { \ + __put_kernel_common(ptr, size); \ + } else { \ + __chk_user_ptr(ptr); \ + __put_user_common(ptr, size); \ } \ __pu_err; \ }) @@ -339,22 +437,21 @@ do { \ \ might_fault(); \ if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) { \ - switch (size) { \ - case 1: __put_user_asm("sb", __pu_addr); break; \ - case 2: __put_user_asm("sh", __pu_addr); break; \ - case 4: __put_user_asm("sw", __pu_addr); break; \ - case 8: __PUT_USER_DW(__pu_addr); break; \ - default: __put_user_unknown(); break; \ - } \ + if (segment_eq(get_fs(), get_ds())) \ + __put_kernel_common(__pu_addr, size); \ + else \ + __put_user_common(__pu_addr, size); \ } \ + \ __pu_err; \ }) -#define __put_user_asm(insn, ptr) \ +#define __put_data_asm(insn, ptr) \ { \ __asm__ __volatile__( \ - "1: " insn " %z2, %3 # __put_user_asm\n" \ + "1: "insn("%z2", "%3")" # __put_data_asm \n" \ "2: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "3: li %0, %4 \n" \ " j 2b \n" \ @@ -367,12 +464,13 @@ do { \ "i" (-EFAULT)); \ } -#define __put_user_asm_ll32(ptr) \ +#define __put_data_asm_ll32(insn, ptr) \ { \ __asm__ __volatile__( \ - "1: sw %2, (%3) # __put_user_asm_ll32 \n" \ - "2: sw %D2, 4(%3) \n" \ + "1: "insn("%2", "(%3)")" # __put_data_asm_ll32 \n" \ + "2: "insn("%D2", "4(%3)")" \n" \ "3: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "4: li %0, %4 \n" \ " j 3b \n" \ @@ -389,11 +487,16 @@ do { \ extern void __put_user_unknown(void); /* + * ul{b,h,w} are macros and there are no equivalent macros for EVA. + * EVA unaligned access is handled in the ADE exception handler. + */ +#ifndef CONFIG_EVA +/* * put_user_unaligned: - Write a simple value into user space. - * @x: Value to copy to user space. + * @x: Value to copy to user space. * @ptr: Destination address, in user space. * - * Context: User context only. This function may sleep. + * Context: User context only. This function may sleep. * * This macro copies a single simple value from kernel space to user * space. It supports simple types like char and int, but not larger @@ -409,10 +512,10 @@ extern void __put_user_unknown(void); /* * get_user_unaligned: - Get a simple variable from user space. - * @x: Variable to store result. + * @x: Variable to store result. * @ptr: Source address, in user space. * - * Context: User context only. This function may sleep. + * Context: User context only. This function may sleep. * * This macro copies a single simple variable from user space to kernel * space. It supports simple types like char and int, but not larger @@ -429,10 +532,10 @@ extern void __put_user_unknown(void); /* * __put_user_unaligned: - Write a simple value into user space, with less checking. - * @x: Value to copy to user space. + * @x: Value to copy to user space. * @ptr: Destination address, in user space. * - * Context: User context only. This function may sleep. + * Context: User context only. This function may sleep. * * This macro copies a single simple value from kernel space to user * space. It supports simple types like char and int, but not larger @@ -451,10 +554,10 @@ extern void __put_user_unknown(void); /* * __get_user_unaligned: - Get a simple variable from user space, with less checking. - * @x: Variable to store result. + * @x: Variable to store result. * @ptr: Source address, in user space. * - * Context: User context only. This function may sleep. + * Context: User context only. This function may sleep. * * This macro copies a single simple variable from user space to kernel * space. It supports simple types like char and int, but not larger @@ -490,7 +593,7 @@ extern void __get_user_unaligned_unknown(void); #define __get_user_unaligned_common(val, size, ptr) \ do { \ switch (size) { \ - case 1: __get_user_asm(val, "lb", ptr); break; \ + case 1: __get_data_asm(val, "lb", ptr); break; \ case 2: __get_user_unaligned_asm(val, "ulh", ptr); break; \ case 4: __get_user_unaligned_asm(val, "ulw", ptr); break; \ case 8: __GET_USER_UNALIGNED_DW(val, ptr); break; \ @@ -517,13 +620,14 @@ do { \ __gu_err; \ }) -#define __get_user_unaligned_asm(val, insn, addr) \ +#define __get_data_unaligned_asm(val, insn, addr) \ { \ long __gu_tmp; \ \ __asm__ __volatile__( \ "1: " insn " %1, %3 \n" \ "2: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "3: li %0, %4 \n" \ " j 2b \n" \ @@ -543,13 +647,15 @@ do { \ */ #define __get_user_unaligned_asm_ll32(val, addr) \ { \ - unsigned long long __gu_tmp; \ + unsigned long long __gu_tmp; \ \ __asm__ __volatile__( \ "1: ulw %1, (%3) \n" \ "2: ulw %D1, 4(%3) \n" \ " move %0, $0 \n" \ - "3: .section .fixup,\"ax\" \n" \ + "3: \n" \ + " .insn \n" \ + " .section .fixup,\"ax\" \n" \ "4: li %0, %4 \n" \ " move %1, $0 \n" \ " move %D1, $0 \n" \ @@ -577,19 +683,23 @@ do { \ #define __PUT_USER_UNALIGNED_DW(ptr) __put_user_unaligned_asm("usd", ptr) #endif +#define __put_user_unaligned_common(ptr, size) \ +do { \ + switch (size) { \ + case 1: __put_data_asm("sb", ptr); break; \ + case 2: __put_user_unaligned_asm("ush", ptr); break; \ + case 4: __put_user_unaligned_asm("usw", ptr); break; \ + case 8: __PUT_USER_UNALIGNED_DW(ptr); break; \ + default: __put_user_unaligned_unknown(); break; \ +} while (0) + #define __put_user_unaligned_nocheck(x,ptr,size) \ ({ \ __typeof__(*(ptr)) __pu_val; \ int __pu_err = 0; \ \ __pu_val = (x); \ - switch (size) { \ - case 1: __put_user_asm("sb", ptr); break; \ - case 2: __put_user_unaligned_asm("ush", ptr); break; \ - case 4: __put_user_unaligned_asm("usw", ptr); break; \ - case 8: __PUT_USER_UNALIGNED_DW(ptr); break; \ - default: __put_user_unaligned_unknown(); break; \ - } \ + __put_user_unaligned_common(ptr, size); \ __pu_err; \ }) @@ -599,15 +709,9 @@ do { \ __typeof__(*(ptr)) __pu_val = (x); \ int __pu_err = -EFAULT; \ \ - if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) { \ - switch (size) { \ - case 1: __put_user_asm("sb", __pu_addr); break; \ - case 2: __put_user_unaligned_asm("ush", __pu_addr); break; \ - case 4: __put_user_unaligned_asm("usw", __pu_addr); break; \ - case 8: __PUT_USER_UNALGINED_DW(__pu_addr); break; \ - default: __put_user_unaligned_unknown(); break; \ - } \ - } \ + if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) \ + __put_user_unaligned_common(__pu_addr, size); \ + \ __pu_err; \ }) @@ -616,6 +720,7 @@ do { \ __asm__ __volatile__( \ "1: " insn " %z2, %3 # __put_user_unaligned_asm\n" \ "2: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "3: li %0, %4 \n" \ " j 2b \n" \ @@ -631,9 +736,10 @@ do { \ #define __put_user_unaligned_asm_ll32(ptr) \ { \ __asm__ __volatile__( \ - "1: sw %2, (%3) # __put_user_unaligned_asm_ll32 \n" \ + "1: sw %2, (%3) # __put_user_unaligned_asm_ll32 \n" \ "2: sw %D2, 4(%3) \n" \ "3: \n" \ + " .insn \n" \ " .section .fixup,\"ax\" \n" \ "4: li %0, %4 \n" \ " j 3b \n" \ @@ -650,6 +756,7 @@ do { \ } extern void __put_user_unaligned_unknown(void); +#endif /* * We're generating jump to subroutines which will be outside the range of @@ -658,7 +765,7 @@ extern void __put_user_unaligned_unknown(void); #ifdef MODULE #define __MODULE_JAL(destination) \ ".set\tnoat\n\t" \ - __UA_LA "\t$1, " #destination "\n\t" \ + __UA_LA "\t$1, " #destination "\n\t" \ "jalr\t$1\n\t" \ ".set\tat\n\t" #else @@ -674,6 +781,7 @@ extern void __put_user_unaligned_unknown(void); extern size_t __copy_user(void *__to, const void *__from, size_t __n); +#ifndef CONFIG_EVA #define __invoke_copy_to_user(to, from, n) \ ({ \ register void __user *__cu_to_r __asm__("$4"); \ @@ -692,13 +800,18 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); __cu_len_r; \ }) +#define __invoke_copy_to_kernel(to, from, n) \ + __invoke_copy_to_user(to, from, n) + +#endif + /* * __copy_to_user: - Copy a block of data into user space, with less checking. - * @to: Destination address, in user space. + * @to: Destination address, in user space. * @from: Source address, in kernel space. - * @n: Number of bytes to copy. + * @n: Number of bytes to copy. * - * Context: User context only. This function may sleep. + * Context: User context only. This function may sleep. * * Copy data from kernel space to user space. Caller must check * the specified block with access_ok() before calling this function. @@ -716,7 +829,12 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); __cu_from = (from); \ __cu_len = (n); \ might_fault(); \ - __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \ + if (segment_eq(get_fs(), get_ds())) \ + __cu_len = __invoke_copy_to_kernel(__cu_to, __cu_from, \ + __cu_len); \ + else \ + __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, \ + __cu_len); \ __cu_len; \ }) @@ -731,7 +849,12 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_to = (to); \ __cu_from = (from); \ __cu_len = (n); \ - __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \ + if (segment_eq(get_fs(), get_ds())) \ + __cu_len = __invoke_copy_to_kernel(__cu_to, __cu_from, \ + __cu_len); \ + else \ + __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, \ + __cu_len); \ __cu_len; \ }) @@ -744,18 +867,24 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_to = (to); \ __cu_from = (from); \ __cu_len = (n); \ - __cu_len = __invoke_copy_from_user_inatomic(__cu_to, __cu_from, \ - __cu_len); \ + if (segment_eq(get_fs(), get_ds())) \ + __cu_len = __invoke_copy_from_kernel_inatomic(__cu_to, \ + __cu_from,\ + __cu_len);\ + else \ + __cu_len = __invoke_copy_from_user_inatomic(__cu_to, \ + __cu_from, \ + __cu_len); \ __cu_len; \ }) /* * copy_to_user: - Copy a block of data into user space. - * @to: Destination address, in user space. + * @to: Destination address, in user space. * @from: Source address, in kernel space. - * @n: Number of bytes to copy. + * @n: Number of bytes to copy. * - * Context: User context only. This function may sleep. + * Context: User context only. This function may sleep. * * Copy data from kernel space to user space. * @@ -771,14 +900,23 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_to = (to); \ __cu_from = (from); \ __cu_len = (n); \ - if (access_ok(VERIFY_WRITE, __cu_to, __cu_len)) { \ - might_fault(); \ - __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, \ - __cu_len); \ + if (segment_eq(get_fs(), get_ds())) { \ + __cu_len = __invoke_copy_to_kernel(__cu_to, \ + __cu_from, \ + __cu_len); \ + } else { \ + if (access_ok(VERIFY_WRITE, __cu_to, __cu_len)) { \ + might_fault(); \ + __cu_len = __invoke_copy_to_user(__cu_to, \ + __cu_from, \ + __cu_len); \ + } \ } \ __cu_len; \ }) +#ifndef CONFIG_EVA + #define __invoke_copy_from_user(to, from, n) \ ({ \ register void *__cu_to_r __asm__("$4"); \ @@ -802,6 +940,17 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_len_r; \ }) +#define __invoke_copy_from_kernel(to, from, n) \ + __invoke_copy_from_user(to, from, n) + +/* For userland <-> userland operations */ +#define ___invoke_copy_in_user(to, from, n) \ + __invoke_copy_from_user(to, from, n) + +/* For kernel <-> kernel operations */ +#define ___invoke_copy_in_kernel(to, from, n) \ + __invoke_copy_from_user(to, from, n) + #define __invoke_copy_from_user_inatomic(to, from, n) \ ({ \ register void *__cu_to_r __asm__("$4"); \ @@ -825,13 +974,104 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_len_r; \ }) +#define __invoke_copy_from_kernel_inatomic(to, from, n) \ + __invoke_copy_from_user_inatomic(to, from, n) \ + +#else + +/* EVA specific functions */ + +extern size_t __copy_user_inatomic_eva(void *__to, const void *__from, + size_t __n); +extern size_t __copy_from_user_eva(void *__to, const void *__from, + size_t __n); +extern size_t __copy_to_user_eva(void *__to, const void *__from, + size_t __n); +extern size_t __copy_in_user_eva(void *__to, const void *__from, size_t __n); + +#define __invoke_copy_from_user_eva_generic(to, from, n, func_ptr) \ +({ \ + register void *__cu_to_r __asm__("$4"); \ + register const void __user *__cu_from_r __asm__("$5"); \ + register long __cu_len_r __asm__("$6"); \ + \ + __cu_to_r = (to); \ + __cu_from_r = (from); \ + __cu_len_r = (n); \ + __asm__ __volatile__( \ + ".set\tnoreorder\n\t" \ + __MODULE_JAL(func_ptr) \ + ".set\tnoat\n\t" \ + __UA_ADDU "\t$1, %1, %2\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" \ + : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ + : \ + : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31", \ + DADDI_SCRATCH, "memory"); \ + __cu_len_r; \ +}) + +#define __invoke_copy_to_user_eva_generic(to, from, n, func_ptr) \ +({ \ + register void *__cu_to_r __asm__("$4"); \ + register const void __user *__cu_from_r __asm__("$5"); \ + register long __cu_len_r __asm__("$6"); \ + \ + __cu_to_r = (to); \ + __cu_from_r = (from); \ + __cu_len_r = (n); \ + __asm__ __volatile__( \ + __MODULE_JAL(func_ptr) \ + : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ + : \ + : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31", \ + DADDI_SCRATCH, "memory"); \ + __cu_len_r; \ +}) + +/* + * Source or destination address is in userland. We need to go through + * the TLB + */ +#define __invoke_copy_from_user(to, from, n) \ + __invoke_copy_from_user_eva_generic(to, from, n, __copy_from_user_eva) + +#define __invoke_copy_from_user_inatomic(to, from, n) \ + __invoke_copy_from_user_eva_generic(to, from, n, \ + __copy_user_inatomic_eva) + +#define __invoke_copy_to_user(to, from, n) \ + __invoke_copy_to_user_eva_generic(to, from, n, __copy_to_user_eva) + +#define ___invoke_copy_in_user(to, from, n) \ + __invoke_copy_from_user_eva_generic(to, from, n, __copy_in_user_eva) + +/* + * Source or destination address in the kernel. We are not going through + * the TLB + */ +#define __invoke_copy_from_kernel(to, from, n) \ + __invoke_copy_from_user_eva_generic(to, from, n, __copy_user) + +#define __invoke_copy_from_kernel_inatomic(to, from, n) \ + __invoke_copy_from_user_eva_generic(to, from, n, __copy_user_inatomic) + +#define __invoke_copy_to_kernel(to, from, n) \ + __invoke_copy_to_user_eva_generic(to, from, n, __copy_user) + +#define ___invoke_copy_in_kernel(to, from, n) \ + __invoke_copy_from_user_eva_generic(to, from, n, __copy_user) + +#endif /* CONFIG_EVA */ + /* * __copy_from_user: - Copy a block of data from user space, with less checking. - * @to: Destination address, in kernel space. + * @to: Destination address, in kernel space. * @from: Source address, in user space. - * @n: Number of bytes to copy. + * @n: Number of bytes to copy. * - * Context: User context only. This function may sleep. + * Context: User context only. This function may sleep. * * Copy data from user space to kernel space. Caller must check * the specified block with access_ok() before calling this function. @@ -853,17 +1093,17 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_len = (n); \ might_fault(); \ __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ - __cu_len); \ + __cu_len); \ __cu_len; \ }) /* * copy_from_user: - Copy a block of data from user space. - * @to: Destination address, in kernel space. + * @to: Destination address, in kernel space. * @from: Source address, in user space. - * @n: Number of bytes to copy. + * @n: Number of bytes to copy. * - * Context: User context only. This function may sleep. + * Context: User context only. This function may sleep. * * Copy data from user space to kernel space. * @@ -882,10 +1122,17 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_to = (to); \ __cu_from = (from); \ __cu_len = (n); \ - if (access_ok(VERIFY_READ, __cu_from, __cu_len)) { \ - might_fault(); \ - __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ - __cu_len); \ + if (segment_eq(get_fs(), get_ds())) { \ + __cu_len = __invoke_copy_from_kernel(__cu_to, \ + __cu_from, \ + __cu_len); \ + } else { \ + if (access_ok(VERIFY_READ, __cu_from, __cu_len)) { \ + might_fault(); \ + __cu_len = __invoke_copy_from_user(__cu_to, \ + __cu_from, \ + __cu_len); \ + } \ } \ __cu_len; \ }) @@ -899,9 +1146,14 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_to = (to); \ __cu_from = (from); \ __cu_len = (n); \ - might_fault(); \ - __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ - __cu_len); \ + if (segment_eq(get_fs(), get_ds())) { \ + __cu_len = ___invoke_copy_in_kernel(__cu_to, __cu_from, \ + __cu_len); \ + } else { \ + might_fault(); \ + __cu_len = ___invoke_copy_in_user(__cu_to, __cu_from, \ + __cu_len); \ + } \ __cu_len; \ }) @@ -914,19 +1166,25 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); __cu_to = (to); \ __cu_from = (from); \ __cu_len = (n); \ - if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) && \ - access_ok(VERIFY_WRITE, __cu_to, __cu_len))) { \ - might_fault(); \ - __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ - __cu_len); \ + if (segment_eq(get_fs(), get_ds())) { \ + __cu_len = ___invoke_copy_in_kernel(__cu_to,__cu_from, \ + __cu_len); \ + } else { \ + if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) &&\ + access_ok(VERIFY_WRITE, __cu_to, __cu_len))) {\ + might_fault(); \ + __cu_len = ___invoke_copy_in_user(__cu_to, \ + __cu_from, \ + __cu_len); \ + } \ } \ __cu_len; \ }) /* * __clear_user: - Zero a block of memory in user space, with less checking. - * @to: Destination address, in user space. - * @n: Number of bytes to zero. + * @to: Destination address, in user space. + * @n: Number of bytes to zero. * * Zero a block of memory in user space. Caller must check * the specified block with access_ok() before calling this function. @@ -966,7 +1224,7 @@ __clear_user(void __user *addr, __kernel_size_t size) /* * __strncpy_from_user: - Copy a NUL terminated string from userspace, with less checking. * @dst: Destination address, in kernel space. This buffer must be at - * least @count bytes long. + * least @count bytes long. * @src: Source address, in user space. * @count: Maximum number of bytes to copy, including the trailing NUL. * @@ -988,16 +1246,28 @@ __strncpy_from_user(char *__to, const char __user *__from, long __len) { long res; - might_fault(); - __asm__ __volatile__( - "move\t$4, %1\n\t" - "move\t$5, %2\n\t" - "move\t$6, %3\n\t" - __MODULE_JAL(__strncpy_from_user_nocheck_asm) - "move\t%0, $2" - : "=r" (res) - : "r" (__to), "r" (__from), "r" (__len) - : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory"); + if (segment_eq(get_fs(), get_ds())) { + __asm__ __volatile__( + "move\t$4, %1\n\t" + "move\t$5, %2\n\t" + "move\t$6, %3\n\t" + __MODULE_JAL(__strncpy_from_kernel_nocheck_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (__to), "r" (__from), "r" (__len) + : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory"); + } else { + might_fault(); + __asm__ __volatile__( + "move\t$4, %1\n\t" + "move\t$5, %2\n\t" + "move\t$6, %3\n\t" + __MODULE_JAL(__strncpy_from_user_nocheck_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (__to), "r" (__from), "r" (__len) + : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory"); + } return res; } @@ -1005,7 +1275,7 @@ __strncpy_from_user(char *__to, const char __user *__from, long __len) /* * strncpy_from_user: - Copy a NUL terminated string from userspace. * @dst: Destination address, in kernel space. This buffer must be at - * least @count bytes long. + * least @count bytes long. * @src: Source address, in user space. * @count: Maximum number of bytes to copy, including the trailing NUL. * @@ -1025,16 +1295,28 @@ strncpy_from_user(char *__to, const char __user *__from, long __len) { long res; - might_fault(); - __asm__ __volatile__( - "move\t$4, %1\n\t" - "move\t$5, %2\n\t" - "move\t$6, %3\n\t" - __MODULE_JAL(__strncpy_from_user_asm) - "move\t%0, $2" - : "=r" (res) - : "r" (__to), "r" (__from), "r" (__len) - : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory"); + if (segment_eq(get_fs(), get_ds())) { + __asm__ __volatile__( + "move\t$4, %1\n\t" + "move\t$5, %2\n\t" + "move\t$6, %3\n\t" + __MODULE_JAL(__strncpy_from_kernel_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (__to), "r" (__from), "r" (__len) + : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory"); + } else { + might_fault(); + __asm__ __volatile__( + "move\t$4, %1\n\t" + "move\t$5, %2\n\t" + "move\t$6, %3\n\t" + __MODULE_JAL(__strncpy_from_user_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (__to), "r" (__from), "r" (__len) + : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory"); + } return res; } @@ -1044,14 +1326,24 @@ static inline long __strlen_user(const char __user *s) { long res; - might_fault(); - __asm__ __volatile__( - "move\t$4, %1\n\t" - __MODULE_JAL(__strlen_user_nocheck_asm) - "move\t%0, $2" - : "=r" (res) - : "r" (s) - : "$2", "$4", __UA_t0, "$31"); + if (segment_eq(get_fs(), get_ds())) { + __asm__ __volatile__( + "move\t$4, %1\n\t" + __MODULE_JAL(__strlen_kernel_nocheck_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (s) + : "$2", "$4", __UA_t0, "$31"); + } else { + might_fault(); + __asm__ __volatile__( + "move\t$4, %1\n\t" + __MODULE_JAL(__strlen_user_nocheck_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (s) + : "$2", "$4", __UA_t0, "$31"); + } return res; } @@ -1060,7 +1352,7 @@ static inline long __strlen_user(const char __user *s) * strlen_user: - Get the size of a string in user space. * @str: The string to measure. * - * Context: User context only. This function may sleep. + * Context: User context only. This function may sleep. * * Get the size of a NUL-terminated string in user space. * @@ -1074,14 +1366,24 @@ static inline long strlen_user(const char __user *s) { long res; - might_fault(); - __asm__ __volatile__( - "move\t$4, %1\n\t" - __MODULE_JAL(__strlen_user_asm) - "move\t%0, $2" - : "=r" (res) - : "r" (s) - : "$2", "$4", __UA_t0, "$31"); + if (segment_eq(get_fs(), get_ds())) { + __asm__ __volatile__( + "move\t$4, %1\n\t" + __MODULE_JAL(__strlen_kernel_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (s) + : "$2", "$4", __UA_t0, "$31"); + } else { + might_fault(); + __asm__ __volatile__( + "move\t$4, %1\n\t" + __MODULE_JAL(__strlen_kernel_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (s) + : "$2", "$4", __UA_t0, "$31"); + } return res; } @@ -1091,15 +1393,26 @@ static inline long __strnlen_user(const char __user *s, long n) { long res; - might_fault(); - __asm__ __volatile__( - "move\t$4, %1\n\t" - "move\t$5, %2\n\t" - __MODULE_JAL(__strnlen_user_nocheck_asm) - "move\t%0, $2" - : "=r" (res) - : "r" (s), "r" (n) - : "$2", "$4", "$5", __UA_t0, "$31"); + if (segment_eq(get_fs(), get_ds())) { + __asm__ __volatile__( + "move\t$4, %1\n\t" + "move\t$5, %2\n\t" + __MODULE_JAL(__strnlen_kernel_nocheck_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (s), "r" (n) + : "$2", "$4", "$5", __UA_t0, "$31"); + } else { + might_fault(); + __asm__ __volatile__( + "move\t$4, %1\n\t" + "move\t$5, %2\n\t" + __MODULE_JAL(__strnlen_user_nocheck_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (s), "r" (n) + : "$2", "$4", "$5", __UA_t0, "$31"); + } return res; } @@ -1108,7 +1421,7 @@ static inline long __strnlen_user(const char __user *s, long n) * strlen_user: - Get the size of a string in user space. * @str: The string to measure. * - * Context: User context only. This function may sleep. + * Context: User context only. This function may sleep. * * Get the size of a NUL-terminated string in user space. * @@ -1123,14 +1436,25 @@ static inline long strnlen_user(const char __user *s, long n) long res; might_fault(); - __asm__ __volatile__( - "move\t$4, %1\n\t" - "move\t$5, %2\n\t" - __MODULE_JAL(__strnlen_user_asm) - "move\t%0, $2" - : "=r" (res) - : "r" (s), "r" (n) - : "$2", "$4", "$5", __UA_t0, "$31"); + if (segment_eq(get_fs(), get_ds())) { + __asm__ __volatile__( + "move\t$4, %1\n\t" + "move\t$5, %2\n\t" + __MODULE_JAL(__strnlen_kernel_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (s), "r" (n) + : "$2", "$4", "$5", __UA_t0, "$31"); + } else { + __asm__ __volatile__( + "move\t$4, %1\n\t" + "move\t$5, %2\n\t" + __MODULE_JAL(__strnlen_user_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (s), "r" (n) + : "$2", "$4", "$5", __UA_t0, "$31"); + } return res; } diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 7e0bf17c932..708c5d41490 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -3,63 +3,92 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer + * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer * Copyright (C) 2005 Maciej W. Rozycki * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2012 MIPS Technologies, Inc. + * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. */ #include <linux/types.h> #ifdef CONFIG_EXPORT_UASM #include <linux/export.h> -#define __uasminit -#define __uasminitdata #define UASM_EXPORT_SYMBOL(sym) EXPORT_SYMBOL(sym) #else -#define __uasminit __cpuinit -#define __uasminitdata __cpuinitdata #define UASM_EXPORT_SYMBOL(sym) #endif +#define _UASM_ISA_CLASSIC 0 +#define _UASM_ISA_MICROMIPS 1 + +#ifndef UASM_ISA +#ifdef CONFIG_CPU_MICROMIPS +#define UASM_ISA _UASM_ISA_MICROMIPS +#else +#define UASM_ISA _UASM_ISA_CLASSIC +#endif +#endif + +#if (UASM_ISA == _UASM_ISA_CLASSIC) +#ifdef CONFIG_CPU_MICROMIPS +#define ISAOPC(op) CL_uasm_i##op +#define ISAFUNC(x) CL_##x +#else +#define ISAOPC(op) uasm_i##op +#define ISAFUNC(x) x +#endif +#elif (UASM_ISA == _UASM_ISA_MICROMIPS) +#ifdef CONFIG_CPU_MICROMIPS +#define ISAOPC(op) uasm_i##op +#define ISAFUNC(x) x +#else +#define ISAOPC(op) MM_uasm_i##op +#define ISAFUNC(x) MM_##x +#endif +#else +#error Unsupported micro-assembler ISA!!! +#endif + #define Ip_u1u2u3(op) \ -void __uasminit \ -uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) +void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) #define Ip_u2u1u3(op) \ -void __uasminit \ -uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) +void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) + +#define Ip_u3u2u1(op) \ +void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) #define Ip_u3u1u2(op) \ -void __uasminit \ -uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) +void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) #define Ip_u1u2s3(op) \ -void __uasminit \ -uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) +void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c) #define Ip_u2s3u1(op) \ -void __uasminit \ -uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c) +void ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c) + +#define Ip_s3s1s2(op) \ +void ISAOPC(op)(u32 **buf, int a, int b, int c) #define Ip_u2u1s3(op) \ -void __uasminit \ -uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) +void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c) #define Ip_u2u1msbu3(op) \ -void __uasminit \ -uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \ +void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \ unsigned int d) #define Ip_u1u2(op) \ -void __uasminit uasm_i##op(u32 **buf, unsigned int a, unsigned int b) +void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b) + +#define Ip_u2u1(op) \ +void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b) #define Ip_u1s2(op) \ -void __uasminit uasm_i##op(u32 **buf, unsigned int a, signed int b) +void ISAOPC(op)(u32 **buf, unsigned int a, signed int b) -#define Ip_u1(op) void __uasminit uasm_i##op(u32 **buf, unsigned int a) +#define Ip_u1(op) void ISAOPC(op)(u32 **buf, unsigned int a) -#define Ip_0(op) void __uasminit uasm_i##op(u32 **buf) +#define Ip_0(op) void ISAOPC(op)(u32 **buf) Ip_u2u1s3(_addiu); Ip_u3u1u2(_addu); @@ -79,6 +108,7 @@ Ip_u2u1s3(_daddiu); Ip_u3u1u2(_daddu); Ip_u2u1msbu3(_dins); Ip_u2u1msbu3(_dinsm); +Ip_u1u2(_divu); Ip_u1u2u3(_dmfc0); Ip_u1u2u3(_dmtc0); Ip_u2u1u3(_drotr); @@ -94,16 +124,22 @@ Ip_u2u1msbu3(_ext); Ip_u2u1msbu3(_ins); Ip_u1(_j); Ip_u1(_jal); +Ip_u2u1(_jalr); Ip_u1(_jr); +Ip_u2s3u1(_lb); Ip_u2s3u1(_ld); Ip_u3u1u2(_ldx); +Ip_u2s3u1(_lh); Ip_u2s3u1(_ll); Ip_u2s3u1(_lld); Ip_u1s2(_lui); Ip_u2s3u1(_lw); Ip_u3u1u2(_lwx); Ip_u1u2u3(_mfc0); +Ip_u1(_mfhi); +Ip_u1(_mflo); Ip_u1u2u3(_mtc0); +Ip_u3u1u2(_mul); Ip_u3u1u2(_or); Ip_u2u1u3(_ori); Ip_u2s3u1(_pref); @@ -113,17 +149,26 @@ Ip_u2s3u1(_sc); Ip_u2s3u1(_scd); Ip_u2s3u1(_sd); Ip_u2u1u3(_sll); +Ip_u3u2u1(_sllv); +Ip_s3s1s2(_slt); +Ip_u2u1s3(_sltiu); +Ip_u3u1u2(_sltu); Ip_u2u1u3(_sra); Ip_u2u1u3(_srl); +Ip_u3u2u1(_srlv); Ip_u3u1u2(_subu); Ip_u2s3u1(_sw); +Ip_u1(_sync); Ip_u1(_syscall); Ip_0(_tlbp); Ip_0(_tlbr); Ip_0(_tlbwi); Ip_0(_tlbwr); +Ip_u1(_wait); +Ip_u2u1(_wsbh); Ip_u3u1u2(_xor); Ip_u2u1u3(_xori); +Ip_u2u1(_yield); /* Handle labels. */ @@ -132,19 +177,20 @@ struct uasm_label { int lab; }; -void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid); +void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, + int lid); #ifdef CONFIG_64BIT -int uasm_in_compat_space_p(long addr); +int ISAFUNC(uasm_in_compat_space_p)(long addr); #endif -int uasm_rel_hi(long val); -int uasm_rel_lo(long val); -void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr); -void UASM_i_LA(u32 **buf, unsigned int rs, long addr); +int ISAFUNC(uasm_rel_hi)(long val); +int ISAFUNC(uasm_rel_lo)(long val); +void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr); +void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr); #define UASM_L_LA(lb) \ -static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ +static inline void ISAFUNC(uasm_l##lb)(struct uasm_label **lab, u32 *addr) \ { \ - uasm_build_label(lab, addr, label##lb); \ + ISAFUNC(uasm_build_label)(lab, addr, label##lb); \ } /* convenience macros for instructions */ @@ -196,27 +242,27 @@ static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1, unsigned int a2, unsigned int a3) { if (a3 < 32) - uasm_i_drotr(p, a1, a2, a3); + ISAOPC(_drotr)(p, a1, a2, a3); else - uasm_i_drotr32(p, a1, a2, a3 - 32); + ISAOPC(_drotr32)(p, a1, a2, a3 - 32); } static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1, unsigned int a2, unsigned int a3) { if (a3 < 32) - uasm_i_dsll(p, a1, a2, a3); + ISAOPC(_dsll)(p, a1, a2, a3); else - uasm_i_dsll32(p, a1, a2, a3 - 32); + ISAOPC(_dsll32)(p, a1, a2, a3 - 32); } static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1, unsigned int a2, unsigned int a3) { if (a3 < 32) - uasm_i_dsrl(p, a1, a2, a3); + ISAOPC(_dsrl)(p, a1, a2, a3); else - uasm_i_dsrl32(p, a1, a2, a3 - 32); + ISAOPC(_dsrl32)(p, a1, a2, a3 - 32); } /* Handle relocations. */ @@ -243,6 +289,8 @@ void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg, unsigned int bit, int lid); void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg, unsigned int bit, int lid); +void uasm_il_beq(u32 **p, struct uasm_reloc **r, unsigned int r1, + unsigned int r2, int lid); void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); diff --git a/arch/mips/include/asm/ucontext.h b/arch/mips/include/asm/ucontext.h deleted file mode 100644 index 9bc07b9f30f..00000000000 --- a/arch/mips/include/asm/ucontext.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/ucontext.h> diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h index 9e47cc11aa2..e55813029d5 100644 --- a/arch/mips/include/asm/unistd.h +++ b/arch/mips/include/asm/unistd.h @@ -14,16 +14,21 @@ #include <uapi/asm/unistd.h> +#ifdef CONFIG_MIPS32_N32 +#define NR_syscalls (__NR_N32_Linux + __NR_N32_Linux_syscalls) +#elif defined(CONFIG_64BIT) +#define NR_syscalls (__NR_64_Linux + __NR_64_Linux_syscalls) +#else +#define NR_syscalls (__NR_O32_Linux + __NR_O32_Linux_syscalls) +#endif #ifndef __ASSEMBLY__ -#define __ARCH_OMIT_COMPAT_SYS_GETDENTS64 #define __ARCH_WANT_OLD_READDIR #define __ARCH_WANT_SYS_ALARM #define __ARCH_WANT_SYS_GETHOSTNAME #define __ARCH_WANT_SYS_IPC #define __ARCH_WANT_SYS_PAUSE -#define __ARCH_WANT_SYS_SGETMASK #define __ARCH_WANT_SYS_UTIME #define __ARCH_WANT_SYS_WAITPID #define __ARCH_WANT_SYS_SOCKETCALL @@ -35,7 +40,6 @@ #define __ARCH_WANT_SYS_OLDUMOUNT #define __ARCH_WANT_SYS_SIGPENDING #define __ARCH_WANT_SYS_SIGPROCMASK -#define __ARCH_WANT_SYS_RT_SIGACTION # ifdef CONFIG_32BIT # define __ARCH_WANT_STAT64 # define __ARCH_WANT_SYS_TIME @@ -43,6 +47,8 @@ # ifdef CONFIG_MIPS32_O32 # define __ARCH_WANT_COMPAT_SYS_TIME # endif +#define __ARCH_WANT_SYS_FORK +#define __ARCH_WANT_SYS_CLONE /* whitelists for checksyscalls */ #define __IGNORE_select @@ -62,12 +68,4 @@ #endif /* !__ASSEMBLY__ */ -/* - * "Conditional" syscalls - * - * What we want is __attribute__((weak,alias("sys_ni_syscall"))), - * but it doesn't work on all toolchains, so we just do it by hand - */ -#define cond_syscall(x) asm(".weak\t" #x "\n" #x "\t=\tsys_ni_syscall") - #endif /* _ASM_UNISTD_H */ diff --git a/arch/mips/include/asm/user.h b/arch/mips/include/asm/user.h index afa83a4c188..6bad61b0a53 100644 --- a/arch/mips/include/asm/user.h +++ b/arch/mips/include/asm/user.h @@ -20,7 +20,7 @@ * upage: 1 page consisting of a user struct that tells gdb * what is present in the file. Directly after this is a * copy of the task_struct, which is currently not used by gdb, - * but it may come in handy at some point. All of the registers + * but it may come in handy at some point. All of the registers * are stored as part of the upage. The upage should always be * only one page long. * data: The data segment follows next. We use current->end_text to diff --git a/arch/mips/include/asm/vga.h b/arch/mips/include/asm/vga.h index f4cff7e4fa8..f82c83749a0 100644 --- a/arch/mips/include/asm/vga.h +++ b/arch/mips/include/asm/vga.h @@ -6,6 +6,7 @@ #ifndef _ASM_VGA_H #define _ASM_VGA_H +#include <asm/addrspace.h> #include <asm/byteorder.h> /* @@ -13,7 +14,7 @@ * access the videoram directly without any black magic. */ -#define VGA_MAP_MEM(x, s) (0xb0000000L + (unsigned long)(x)) +#define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x)) #define vga_readb(x) (*(x)) #define vga_writeb(x, y) (*(y) = (x)) diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h index c6e1b961537..7849f3978fe 100644 --- a/arch/mips/include/asm/vpe.h +++ b/arch/mips/include/asm/vpe.h @@ -1,24 +1,95 @@ /* - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2013 Imagination Technologies Ltd. */ - #ifndef _ASM_VPE_H #define _ASM_VPE_H +#include <linux/init.h> +#include <linux/list.h> +#include <linux/smp.h> +#include <linux/spinlock.h> + +#define VPE_MODULE_NAME "vpe" +#define VPE_MODULE_MINOR 1 + +/* grab the likely amount of memory we will need. */ +#ifdef CONFIG_MIPS_VPE_LOADER_TOM +#define P_SIZE (2 * 1024 * 1024) +#else +/* add an overhead to the max kmalloc size for non-striped symbols/etc */ +#define P_SIZE (256 * 1024) +#endif + +#define MAX_VPES 16 +#define VPE_PATH_MAX 256 + +static inline int aprp_cpu_index(void) +{ +#ifdef CONFIG_MIPS_CMP + return setup_max_cpus; +#else + extern int tclimit; + return tclimit; +#endif +} + +enum vpe_state { + VPE_STATE_UNUSED = 0, + VPE_STATE_INUSE, + VPE_STATE_RUNNING +}; + +enum tc_state { + TC_STATE_UNUSED = 0, + TC_STATE_INUSE, + TC_STATE_RUNNING, + TC_STATE_DYNAMIC +}; + +struct vpe { + enum vpe_state state; + + /* (device) minor associated with this vpe */ + int minor; + + /* elfloader stuff */ + void *load_addr; + unsigned long len; + char *pbuffer; + unsigned long plen; + char cwd[VPE_PATH_MAX]; + + unsigned long __start; + + /* tc's associated with this vpe */ + struct list_head tc; + + /* The list of vpe's */ + struct list_head list; + + /* shared symbol address */ + void *shared_ptr; + + /* the list of who wants to know when something major happens */ + struct list_head notify; + + unsigned int ntcs; +}; + +struct tc { + enum tc_state state; + int index; + + struct vpe *pvpe; /* parent VPE */ + struct list_head tc; /* The list of TC's with this VPE */ + struct list_head list; /* The global list of tc's */ +}; + struct vpe_notifications { void (*start)(int vpe); void (*stop)(int vpe); @@ -26,12 +97,34 @@ struct vpe_notifications { struct list_head list; }; +struct vpe_control { + spinlock_t vpe_list_lock; + struct list_head vpe_list; /* Virtual processing elements */ + spinlock_t tc_list_lock; + struct list_head tc_list; /* Thread contexts */ +}; + +extern unsigned long physical_memsize; +extern struct vpe_control vpecontrol; +extern const struct file_operations vpe_fops; + +int vpe_notify(int index, struct vpe_notifications *notify); + +void *vpe_get_shared(int index); +char *vpe_getcwd(int index); + +struct vpe *get_vpe(int minor); +struct tc *get_tc(int index); +struct vpe *alloc_vpe(int minor); +struct tc *alloc_tc(int index); +void release_vpe(struct vpe *v); -extern int vpe_notify(int index, struct vpe_notifications *notify); +void *alloc_progmem(unsigned long len); +void release_progmem(void *ptr); -extern void *vpe_get_shared(int index); -extern int vpe_getuid(int index); -extern int vpe_getgid(int index); -extern char *vpe_getcwd(int index); +int __weak vpe_run(struct vpe *v); +void cleanup_tc(struct tc *tc); +int __init vpe_module_init(void); +void __exit vpe_module_exit(void); #endif /* _ASM_VPE_H */ diff --git a/arch/mips/include/asm/vr41xx/pci.h b/arch/mips/include/asm/vr41xx/pci.h index c231a3d6cfd..a866918cfea 100644 --- a/arch/mips/include/asm/vr41xx/pci.h +++ b/arch/mips/include/asm/vr41xx/pci.h @@ -20,7 +20,7 @@ #ifndef __NEC_VR41XX_PCI_H #define __NEC_VR41XX_PCI_H -#define PCI_MASTER_ADDRESS_MASK 0x7fffffffU +#define PCI_MASTER_ADDRESS_MASK 0x7fffffffU struct pci_master_address_conversion { uint32_t bus_base_address; diff --git a/arch/mips/include/asm/vr41xx/tb0287.h b/arch/mips/include/asm/vr41xx/tb0287.h index 61bead68abf..d58b5678f24 100644 --- a/arch/mips/include/asm/vr41xx/tb0287.h +++ b/arch/mips/include/asm/vr41xx/tb0287.h @@ -1,7 +1,7 @@ /* * tb0287.h, Include file for TANBAC TB0287 mini-ITX board. * - * Copyright (C) 2005 Media Lab Inc. <ito@mlb.co.jp> + * Copyright (C) 2005 Media Lab Inc. <ito@mlb.co.jp> * * This code is largely based on tb0219.h. * diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h index 65e344532de..9344e247a6c 100644 --- a/arch/mips/include/asm/war.h +++ b/arch/mips/include/asm/war.h @@ -83,30 +83,30 @@ #endif /* - * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: + * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: * * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, - * Hit_Invalidate_D and Create_Dirty_Excl_D should only be - * executed if there is no other dcache activity. If the dcache is - * accessed for another instruction immeidately preceding when these - * cache instructions are executing, it is possible that the dcache - * tag match outputs used by these cache instructions will be - * incorrect. These cache instructions should be preceded by at least - * four instructions that are not any kind of load or store - * instruction. - * - * This is not allowed: lw - * nop - * nop - * nop - * cache Hit_Writeback_Invalidate_D - * - * This is allowed: lw - * nop - * nop - * nop - * nop - * cache Hit_Writeback_Invalidate_D + * Hit_Invalidate_D and Create_Dirty_Excl_D should only be + * executed if there is no other dcache activity. If the dcache is + * accessed for another instruction immeidately preceding when these + * cache instructions are executing, it is possible that the dcache + * tag match outputs used by these cache instructions will be + * incorrect. These cache instructions should be preceded by at least + * four instructions that are not any kind of load or store + * instruction. + * + * This is not allowed: lw + * nop + * nop + * nop + * cache Hit_Writeback_Invalidate_D + * + * This is allowed: lw + * nop + * nop + * nop + * nop + * cache Hit_Writeback_Invalidate_D */ #ifndef R4600_V1_HIT_CACHEOP_WAR #error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform @@ -118,7 +118,7 @@ * * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only - * operate correctly if the internal data cache refill buffer is empty. These + * operate correctly if the internal data cache refill buffer is empty. These * CACHE instructions should be separated from any potential data cache miss * by a load instruction to an uncached address to empty the response buffer." * (Revision 2.0 device errata from IDT available on http://www.idt.com/ diff --git a/arch/mips/include/asm/xor.h b/arch/mips/include/asm/xor.h deleted file mode 100644 index c82eb12a5b1..00000000000 --- a/arch/mips/include/asm/xor.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/xor.h> diff --git a/arch/mips/include/asm/xtalk/xtalk.h b/arch/mips/include/asm/xtalk/xtalk.h index 79bac882a73..26d2ed1fa91 100644 --- a/arch/mips/include/asm/xtalk/xtalk.h +++ b/arch/mips/include/asm/xtalk/xtalk.h @@ -16,15 +16,15 @@ /* * User-level device driver visible types */ -typedef char xwidgetnum_t; /* xtalk widget number (0..15) */ +typedef char xwidgetnum_t; /* xtalk widget number (0..15) */ #define XWIDGET_NONE -1 -typedef int xwidget_part_num_t; /* xtalk widget part number */ +typedef int xwidget_part_num_t; /* xtalk widget part number */ #define XWIDGET_PART_NUM_NONE -1 -typedef int xwidget_rev_num_t; /* xtalk widget revision number */ +typedef int xwidget_rev_num_t; /* xtalk widget revision number */ #define XWIDGET_REV_NUM_NONE -1 @@ -37,15 +37,24 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t; /* It is often convenient to fold the XIO target port * number into the XIO address. */ -#define XIO_NOWHERE (0xFFFFFFFFFFFFFFFFull) -#define XIO_ADDR_BITS (0x0000FFFFFFFFFFFFull) -#define XIO_PORT_BITS (0xF000000000000000ull) -#define XIO_PORT_SHIFT (60) - -#define XIO_PACKED(x) (((x)&XIO_PORT_BITS) != 0) -#define XIO_ADDR(x) ((x)&XIO_ADDR_BITS) -#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT)) -#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS)) +#define XIO_NOWHERE (0xFFFFFFFFFFFFFFFFull) +#define XIO_ADDR_BITS (0x0000FFFFFFFFFFFFull) +#define XIO_PORT_BITS (0xF000000000000000ull) +#define XIO_PORT_SHIFT (60) + +#define XIO_PACKED(x) (((x)&XIO_PORT_BITS) != 0) +#define XIO_ADDR(x) ((x)&XIO_ADDR_BITS) +#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT)) +#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS)) + +#ifdef CONFIG_PCI +extern int bridge_probe(nasid_t nasid, int widget, int masterwid); +#else +static inline int bridge_probe(nasid_t nasid, int widget, int masterwid) +{ + return 0; +} +#endif #endif /* !__ASSEMBLY__ */ diff --git a/arch/mips/include/asm/xtalk/xwidget.h b/arch/mips/include/asm/xtalk/xwidget.h index b4a13d7405e..32e4e884f9b 100644 --- a/arch/mips/include/asm/xtalk/xwidget.h +++ b/arch/mips/include/asm/xtalk/xwidget.h @@ -45,12 +45,12 @@ #define WIDGET_PENDING 0x0000001f /* WIDGET_ERR_UPPER_ADDR */ -#define WIDGET_ERR_UPPER_ADDR_ONLY 0x0000ffff +#define WIDGET_ERR_UPPER_ADDR_ONLY 0x0000ffff /* WIDGET_CONTROL */ #define WIDGET_F_BAD_PKT 0x00010000 #define WIDGET_LLP_XBAR_CRD 0x0000f000 -#define WIDGET_LLP_XBAR_CRD_SHFT 12 +#define WIDGET_LLP_XBAR_CRD_SHFT 12 #define WIDGET_CLR_RLLP_CNT 0x00000800 #define WIDGET_CLR_TLLP_CNT 0x00000400 #define WIDGET_SYS_END 0x00000200 @@ -86,8 +86,8 @@ /* * according to the crosstalk spec, only 32-bits access to the widget - * configuration registers is allowed. some widgets may allow 64-bits - * access but software should not depend on it. registers beyond the + * configuration registers is allowed. some widgets may allow 64-bits + * access but software should not depend on it. registers beyond the * widget target flush register are widget dependent thus will not be * defined here */ diff --git a/arch/mips/include/uapi/asm/Kbuild b/arch/mips/include/uapi/asm/Kbuild index a1a0452ac18..96fe7395ed8 100644 --- a/arch/mips/include/uapi/asm/Kbuild +++ b/arch/mips/include/uapi/asm/Kbuild @@ -1,15 +1,19 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm -header-y += auxvec.h +generic-y += auxvec.h +generic-y += ipcbuf.h + +header-y += bitfield.h header-y += bitsperlong.h +header-y += break.h header-y += byteorder.h header-y += cachectl.h header-y += errno.h header-y += fcntl.h +header-y += inst.h header-y += ioctl.h header-y += ioctls.h -header-y += ipcbuf.h header-y += kvm_para.h header-y += mman.h header-y += msgbuf.h diff --git a/arch/mips/include/uapi/asm/auxvec.h b/arch/mips/include/uapi/asm/auxvec.h deleted file mode 100644 index 7cf7f2d2194..00000000000 --- a/arch/mips/include/uapi/asm/auxvec.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef _ASM_AUXVEC_H -#define _ASM_AUXVEC_H - -#endif /* _ASM_AUXVEC_H */ diff --git a/arch/mips/include/uapi/asm/bitfield.h b/arch/mips/include/uapi/asm/bitfield.h new file mode 100644 index 00000000000..ad9861359ce --- /dev/null +++ b/arch/mips/include/uapi/asm/bitfield.h @@ -0,0 +1,29 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2014 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __UAPI_ASM_BITFIELD_H +#define __UAPI_ASM_BITFIELD_H + +/* + * * Damn ... bitfields depend from byteorder :-( + * */ +#ifdef __MIPSEB__ +#define __BITFIELD_FIELD(field, more) \ + field; \ + more + +#elif defined(__MIPSEL__) + +#define __BITFIELD_FIELD(field, more) \ + more \ + field; + +#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */ +#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" +#endif + +#endif /* __UAPI_ASM_BITFIELD_H */ diff --git a/arch/mips/include/uapi/asm/break.h b/arch/mips/include/uapi/asm/break.h new file mode 100644 index 00000000000..002c39ea20c --- /dev/null +++ b/arch/mips/include/uapi/asm/break.h @@ -0,0 +1,29 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 2003 by Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#ifndef __UAPI_ASM_BREAK_H +#define __UAPI_ASM_BREAK_H + +/* + * The following break codes are or were in use for specific purposes in + * other MIPS operating systems. Linux/MIPS doesn't use all of them. The + * unused ones are here as placeholders; we might encounter them in + * non-Linux/MIPS object files or make use of them in the future. + */ +#define BRK_USERBP 0 /* User bp (used by debuggers) */ +#define BRK_SSTEPBP 5 /* User bp (used by debuggers) */ +#define BRK_OVERFLOW 6 /* Overflow check */ +#define BRK_DIVZERO 7 /* Divide by zero check */ +#define BRK_RANGE 8 /* Range error check */ +#define BRK_BUG 12 /* Used by BUG() */ +#define BRK_MEMU 514 /* Used by FPU emulator */ +#define BRK_KPROBE_BP 515 /* Kprobe break */ +#define BRK_KPROBE_SSTEPBP 516 /* Kprobe single step software implementation */ +#define BRK_MULOVF 1023 /* Multiply overflow */ + +#endif /* __UAPI_ASM_BREAK_H */ diff --git a/arch/mips/include/uapi/asm/cachectl.h b/arch/mips/include/uapi/asm/cachectl.h index f3ce721861d..23039090877 100644 --- a/arch/mips/include/uapi/asm/cachectl.h +++ b/arch/mips/include/uapi/asm/cachectl.h @@ -5,15 +5,15 @@ * * Copyright (C) 1994, 1995, 1996 by Ralf Baechle */ -#ifndef _ASM_CACHECTL -#define _ASM_CACHECTL +#ifndef _ASM_CACHECTL +#define _ASM_CACHECTL /* * Options for cacheflush system call */ -#define ICACHE (1<<0) /* flush instruction cache */ -#define DCACHE (1<<1) /* writeback and flush data cache */ -#define BCACHE (ICACHE|DCACHE) /* flush both caches */ +#define ICACHE (1<<0) /* flush instruction cache */ +#define DCACHE (1<<1) /* writeback and flush data cache */ +#define BCACHE (ICACHE|DCACHE) /* flush both caches */ /* * Caching modes for the cachectl(2) call diff --git a/arch/mips/include/uapi/asm/errno.h b/arch/mips/include/uapi/asm/errno.h index bd67b15042e..02d645d7aa9 100644 --- a/arch/mips/include/uapi/asm/errno.h +++ b/arch/mips/include/uapi/asm/errno.h @@ -14,95 +14,95 @@ #include <asm-generic/errno-base.h> -#define ENOMSG 35 /* No message of desired type */ -#define EIDRM 36 /* Identifier removed */ -#define ECHRNG 37 /* Channel number out of range */ -#define EL2NSYNC 38 /* Level 2 not synchronized */ -#define EL3HLT 39 /* Level 3 halted */ -#define EL3RST 40 /* Level 3 reset */ -#define ELNRNG 41 /* Link number out of range */ -#define EUNATCH 42 /* Protocol driver not attached */ -#define ENOCSI 43 /* No CSI structure available */ -#define EL2HLT 44 /* Level 2 halted */ -#define EDEADLK 45 /* Resource deadlock would occur */ -#define ENOLCK 46 /* No record locks available */ -#define EBADE 50 /* Invalid exchange */ -#define EBADR 51 /* Invalid request descriptor */ -#define EXFULL 52 /* Exchange full */ -#define ENOANO 53 /* No anode */ -#define EBADRQC 54 /* Invalid request code */ -#define EBADSLT 55 /* Invalid slot */ -#define EDEADLOCK 56 /* File locking deadlock error */ -#define EBFONT 59 /* Bad font file format */ -#define ENOSTR 60 /* Device not a stream */ -#define ENODATA 61 /* No data available */ -#define ETIME 62 /* Timer expired */ -#define ENOSR 63 /* Out of streams resources */ -#define ENONET 64 /* Machine is not on the network */ -#define ENOPKG 65 /* Package not installed */ -#define EREMOTE 66 /* Object is remote */ -#define ENOLINK 67 /* Link has been severed */ -#define EADV 68 /* Advertise error */ -#define ESRMNT 69 /* Srmount error */ -#define ECOMM 70 /* Communication error on send */ -#define EPROTO 71 /* Protocol error */ -#define EDOTDOT 73 /* RFS specific error */ -#define EMULTIHOP 74 /* Multihop attempted */ -#define EBADMSG 77 /* Not a data message */ -#define ENAMETOOLONG 78 /* File name too long */ -#define EOVERFLOW 79 /* Value too large for defined data type */ -#define ENOTUNIQ 80 /* Name not unique on network */ -#define EBADFD 81 /* File descriptor in bad state */ -#define EREMCHG 82 /* Remote address changed */ -#define ELIBACC 83 /* Can not access a needed shared library */ -#define ELIBBAD 84 /* Accessing a corrupted shared library */ -#define ELIBSCN 85 /* .lib section in a.out corrupted */ -#define ELIBMAX 86 /* Attempting to link in too many shared libraries */ -#define ELIBEXEC 87 /* Cannot exec a shared library directly */ -#define EILSEQ 88 /* Illegal byte sequence */ -#define ENOSYS 89 /* Function not implemented */ -#define ELOOP 90 /* Too many symbolic links encountered */ -#define ERESTART 91 /* Interrupted system call should be restarted */ -#define ESTRPIPE 92 /* Streams pipe error */ -#define ENOTEMPTY 93 /* Directory not empty */ -#define EUSERS 94 /* Too many users */ -#define ENOTSOCK 95 /* Socket operation on non-socket */ -#define EDESTADDRREQ 96 /* Destination address required */ -#define EMSGSIZE 97 /* Message too long */ -#define EPROTOTYPE 98 /* Protocol wrong type for socket */ -#define ENOPROTOOPT 99 /* Protocol not available */ -#define EPROTONOSUPPORT 120 /* Protocol not supported */ -#define ESOCKTNOSUPPORT 121 /* Socket type not supported */ -#define EOPNOTSUPP 122 /* Operation not supported on transport endpoint */ -#define EPFNOSUPPORT 123 /* Protocol family not supported */ -#define EAFNOSUPPORT 124 /* Address family not supported by protocol */ -#define EADDRINUSE 125 /* Address already in use */ -#define EADDRNOTAVAIL 126 /* Cannot assign requested address */ -#define ENETDOWN 127 /* Network is down */ -#define ENETUNREACH 128 /* Network is unreachable */ -#define ENETRESET 129 /* Network dropped connection because of reset */ -#define ECONNABORTED 130 /* Software caused connection abort */ -#define ECONNRESET 131 /* Connection reset by peer */ -#define ENOBUFS 132 /* No buffer space available */ -#define EISCONN 133 /* Transport endpoint is already connected */ -#define ENOTCONN 134 /* Transport endpoint is not connected */ -#define EUCLEAN 135 /* Structure needs cleaning */ -#define ENOTNAM 137 /* Not a XENIX named type file */ -#define ENAVAIL 138 /* No XENIX semaphores available */ -#define EISNAM 139 /* Is a named type file */ -#define EREMOTEIO 140 /* Remote I/O error */ +#define ENOMSG 35 /* No message of desired type */ +#define EIDRM 36 /* Identifier removed */ +#define ECHRNG 37 /* Channel number out of range */ +#define EL2NSYNC 38 /* Level 2 not synchronized */ +#define EL3HLT 39 /* Level 3 halted */ +#define EL3RST 40 /* Level 3 reset */ +#define ELNRNG 41 /* Link number out of range */ +#define EUNATCH 42 /* Protocol driver not attached */ +#define ENOCSI 43 /* No CSI structure available */ +#define EL2HLT 44 /* Level 2 halted */ +#define EDEADLK 45 /* Resource deadlock would occur */ +#define ENOLCK 46 /* No record locks available */ +#define EBADE 50 /* Invalid exchange */ +#define EBADR 51 /* Invalid request descriptor */ +#define EXFULL 52 /* Exchange full */ +#define ENOANO 53 /* No anode */ +#define EBADRQC 54 /* Invalid request code */ +#define EBADSLT 55 /* Invalid slot */ +#define EDEADLOCK 56 /* File locking deadlock error */ +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EDOTDOT 73 /* RFS specific error */ +#define EMULTIHOP 74 /* Multihop attempted */ +#define EBADMSG 77 /* Not a data message */ +#define ENAMETOOLONG 78 /* File name too long */ +#define EOVERFLOW 79 /* Value too large for defined data type */ +#define ENOTUNIQ 80 /* Name not unique on network */ +#define EBADFD 81 /* File descriptor in bad state */ +#define EREMCHG 82 /* Remote address changed */ +#define ELIBACC 83 /* Can not access a needed shared library */ +#define ELIBBAD 84 /* Accessing a corrupted shared library */ +#define ELIBSCN 85 /* .lib section in a.out corrupted */ +#define ELIBMAX 86 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 87 /* Cannot exec a shared library directly */ +#define EILSEQ 88 /* Illegal byte sequence */ +#define ENOSYS 89 /* Function not implemented */ +#define ELOOP 90 /* Too many symbolic links encountered */ +#define ERESTART 91 /* Interrupted system call should be restarted */ +#define ESTRPIPE 92 /* Streams pipe error */ +#define ENOTEMPTY 93 /* Directory not empty */ +#define EUSERS 94 /* Too many users */ +#define ENOTSOCK 95 /* Socket operation on non-socket */ +#define EDESTADDRREQ 96 /* Destination address required */ +#define EMSGSIZE 97 /* Message too long */ +#define EPROTOTYPE 98 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 99 /* Protocol not available */ +#define EPROTONOSUPPORT 120 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 121 /* Socket type not supported */ +#define EOPNOTSUPP 122 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 123 /* Protocol family not supported */ +#define EAFNOSUPPORT 124 /* Address family not supported by protocol */ +#define EADDRINUSE 125 /* Address already in use */ +#define EADDRNOTAVAIL 126 /* Cannot assign requested address */ +#define ENETDOWN 127 /* Network is down */ +#define ENETUNREACH 128 /* Network is unreachable */ +#define ENETRESET 129 /* Network dropped connection because of reset */ +#define ECONNABORTED 130 /* Software caused connection abort */ +#define ECONNRESET 131 /* Connection reset by peer */ +#define ENOBUFS 132 /* No buffer space available */ +#define EISCONN 133 /* Transport endpoint is already connected */ +#define ENOTCONN 134 /* Transport endpoint is not connected */ +#define EUCLEAN 135 /* Structure needs cleaning */ +#define ENOTNAM 137 /* Not a XENIX named type file */ +#define ENAVAIL 138 /* No XENIX semaphores available */ +#define EISNAM 139 /* Is a named type file */ +#define EREMOTEIO 140 /* Remote I/O error */ #define EINIT 141 /* Reserved */ #define EREMDEV 142 /* Error 142 */ -#define ESHUTDOWN 143 /* Cannot send after transport endpoint shutdown */ -#define ETOOMANYREFS 144 /* Too many references: cannot splice */ -#define ETIMEDOUT 145 /* Connection timed out */ -#define ECONNREFUSED 146 /* Connection refused */ -#define EHOSTDOWN 147 /* Host is down */ -#define EHOSTUNREACH 148 /* No route to host */ -#define EWOULDBLOCK EAGAIN /* Operation would block */ -#define EALREADY 149 /* Operation already in progress */ -#define EINPROGRESS 150 /* Operation now in progress */ -#define ESTALE 151 /* Stale NFS file handle */ +#define ESHUTDOWN 143 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 144 /* Too many references: cannot splice */ +#define ETIMEDOUT 145 /* Connection timed out */ +#define ECONNREFUSED 146 /* Connection refused */ +#define EHOSTDOWN 147 /* Host is down */ +#define EHOSTUNREACH 148 /* No route to host */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define EALREADY 149 /* Operation already in progress */ +#define EINPROGRESS 150 /* Operation now in progress */ +#define ESTALE 151 /* Stale file handle */ #define ECANCELED 158 /* AIO operation canceled */ /* @@ -110,16 +110,16 @@ */ #define ENOMEDIUM 159 /* No medium found */ #define EMEDIUMTYPE 160 /* Wrong medium type */ -#define ENOKEY 161 /* Required key not available */ -#define EKEYEXPIRED 162 /* Key has expired */ -#define EKEYREVOKED 163 /* Key has been revoked */ -#define EKEYREJECTED 164 /* Key was rejected by service */ +#define ENOKEY 161 /* Required key not available */ +#define EKEYEXPIRED 162 /* Key has expired */ +#define EKEYREVOKED 163 /* Key has been revoked */ +#define EKEYREJECTED 164 /* Key was rejected by service */ /* for robust mutexes */ -#define EOWNERDEAD 165 /* Owner died */ -#define ENOTRECOVERABLE 166 /* State not recoverable */ +#define EOWNERDEAD 165 /* Owner died */ +#define ENOTRECOVERABLE 166 /* State not recoverable */ -#define ERFKILL 167 /* Operation not possible due to RF-kill */ +#define ERFKILL 167 /* Operation not possible due to RF-kill */ #define EHWPOISON 168 /* Memory page has hardware error */ diff --git a/arch/mips/include/uapi/asm/fcntl.h b/arch/mips/include/uapi/asm/fcntl.h index 75eddedcfc3..6ca432f0086 100644 --- a/arch/mips/include/uapi/asm/fcntl.h +++ b/arch/mips/include/uapi/asm/fcntl.h @@ -5,14 +5,15 @@ * * Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle */ -#ifndef _ASM_FCNTL_H -#define _ASM_FCNTL_H +#ifndef _UAPI_ASM_FCNTL_H +#define _UAPI_ASM_FCNTL_H +#include <asm/sgidefs.h> #define O_APPEND 0x0008 #define O_DSYNC 0x0010 /* used to be O_SYNC, see below */ #define O_NONBLOCK 0x0080 -#define O_CREAT 0x0100 /* not fcntl */ +#define O_CREAT 0x0100 /* not fcntl */ #define O_TRUNC 0x0200 /* not fcntl */ #define O_EXCL 0x0400 /* not fcntl */ #define O_NOCTTY 0x0800 /* not fcntl */ @@ -50,19 +51,20 @@ /* * The flavours of struct flock. "struct flock" is the ABI compliant - * variant. Finally struct flock64 is the LFS variant of struct flock. As + * variant. Finally struct flock64 is the LFS variant of struct flock. As * a historic accident and inconsistence with the ABI definition it doesn't * contain all the same fields as struct flock. */ -#ifdef CONFIG_32BIT +#if _MIPS_SIM != _MIPS_SIM_ABI64 + #include <linux/types.h> struct flock { short l_type; short l_whence; - off_t l_start; - off_t l_len; + __kernel_off_t l_start; + __kernel_off_t l_len; long l_sysid; __kernel_pid_t l_pid; long pad[4]; @@ -70,8 +72,8 @@ struct flock { #define HAVE_ARCH_STRUCT_FLOCK -#endif /* CONFIG_32BIT */ +#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ #include <asm-generic/fcntl.h> -#endif /* _ASM_FCNTL_H */ +#endif /* _UAPI_ASM_FCNTL_H */ diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h new file mode 100644 index 00000000000..4bfdb9d4c18 --- /dev/null +++ b/arch/mips/include/uapi/asm/inst.h @@ -0,0 +1,923 @@ +/* + * Format of an instruction in memory. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 2000 by Ralf Baechle + * Copyright (C) 2006 by Thiemo Seufer + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2014 Imagination Technologies Ltd. + */ +#ifndef _UAPI_ASM_INST_H +#define _UAPI_ASM_INST_H + +#include <asm/bitfield.h> + +/* + * Major opcodes; before MIPS IV cop1x was called cop3. + */ +enum major_op { + spec_op, bcond_op, j_op, jal_op, + beq_op, bne_op, blez_op, bgtz_op, + addi_op, addiu_op, slti_op, sltiu_op, + andi_op, ori_op, xori_op, lui_op, + cop0_op, cop1_op, cop2_op, cop1x_op, + beql_op, bnel_op, blezl_op, bgtzl_op, + daddi_op, daddiu_op, ldl_op, ldr_op, + spec2_op, jalx_op, mdmx_op, spec3_op, + lb_op, lh_op, lwl_op, lw_op, + lbu_op, lhu_op, lwr_op, lwu_op, + sb_op, sh_op, swl_op, sw_op, + sdl_op, sdr_op, swr_op, cache_op, + ll_op, lwc1_op, lwc2_op, pref_op, + lld_op, ldc1_op, ldc2_op, ld_op, + sc_op, swc1_op, swc2_op, major_3b_op, + scd_op, sdc1_op, sdc2_op, sd_op +}; + +/* + * func field of spec opcode. + */ +enum spec_op { + sll_op, movc_op, srl_op, sra_op, + sllv_op, pmon_op, srlv_op, srav_op, + jr_op, jalr_op, movz_op, movn_op, + syscall_op, break_op, spim_op, sync_op, + mfhi_op, mthi_op, mflo_op, mtlo_op, + dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, + mult_op, multu_op, div_op, divu_op, + dmult_op, dmultu_op, ddiv_op, ddivu_op, + add_op, addu_op, sub_op, subu_op, + and_op, or_op, xor_op, nor_op, + spec3_unused_op, spec4_unused_op, slt_op, sltu_op, + dadd_op, daddu_op, dsub_op, dsubu_op, + tge_op, tgeu_op, tlt_op, tltu_op, + teq_op, spec5_unused_op, tne_op, spec6_unused_op, + dsll_op, spec7_unused_op, dsrl_op, dsra_op, + dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op +}; + +/* + * func field of spec2 opcode. + */ +enum spec2_op { + madd_op, maddu_op, mul_op, spec2_3_unused_op, + msub_op, msubu_op, /* more unused ops */ + clz_op = 0x20, clo_op, + dclz_op = 0x24, dclo_op, + sdbpp_op = 0x3f +}; + +/* + * func field of spec3 opcode. + */ +enum spec3_op { + ext_op, dextm_op, dextu_op, dext_op, + ins_op, dinsm_op, dinsu_op, dins_op, + yield_op = 0x09, lx_op = 0x0a, + lwle_op = 0x19, lwre_op = 0x1a, + cachee_op = 0x1b, sbe_op = 0x1c, + she_op = 0x1d, sce_op = 0x1e, + swe_op = 0x1f, bshfl_op = 0x20, + swle_op = 0x21, swre_op = 0x22, + prefe_op = 0x23, dbshfl_op = 0x24, + lbue_op = 0x28, lhue_op = 0x29, + lbe_op = 0x2c, lhe_op = 0x2d, + lle_op = 0x2e, lwe_op = 0x2f, + rdhwr_op = 0x3b +}; + +/* + * rt field of bcond opcodes. + */ +enum rt_op { + bltz_op, bgez_op, bltzl_op, bgezl_op, + spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, + tgei_op, tgeiu_op, tlti_op, tltiu_op, + teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, + bltzal_op, bgezal_op, bltzall_op, bgezall_op, + rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17, + rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b, + bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f +}; + +/* + * rs field of cop opcodes. + */ +enum cop_op { + mfc_op = 0x00, dmfc_op = 0x01, + cfc_op = 0x02, mfhc_op = 0x03, + mtc_op = 0x04, dmtc_op = 0x05, + ctc_op = 0x06, mthc_op = 0x07, + bc_op = 0x08, cop_op = 0x10, + copm_op = 0x18 +}; + +/* + * rt field of cop.bc_op opcodes + */ +enum bcop_op { + bcf_op, bct_op, bcfl_op, bctl_op +}; + +/* + * func field of cop0 coi opcodes. + */ +enum cop0_coi_func { + tlbr_op = 0x01, tlbwi_op = 0x02, + tlbwr_op = 0x06, tlbp_op = 0x08, + rfe_op = 0x10, eret_op = 0x18, + wait_op = 0x20, +}; + +/* + * func field of cop0 com opcodes. + */ +enum cop0_com_func { + tlbr1_op = 0x01, tlbw_op = 0x02, + tlbp1_op = 0x08, dctr_op = 0x09, + dctw_op = 0x0a +}; + +/* + * fmt field of cop1 opcodes. + */ +enum cop1_fmt { + s_fmt, d_fmt, e_fmt, q_fmt, + w_fmt, l_fmt +}; + +/* + * func field of cop1 instructions using d, s or w format. + */ +enum cop1_sdw_func { + fadd_op = 0x00, fsub_op = 0x01, + fmul_op = 0x02, fdiv_op = 0x03, + fsqrt_op = 0x04, fabs_op = 0x05, + fmov_op = 0x06, fneg_op = 0x07, + froundl_op = 0x08, ftruncl_op = 0x09, + fceill_op = 0x0a, ffloorl_op = 0x0b, + fround_op = 0x0c, ftrunc_op = 0x0d, + fceil_op = 0x0e, ffloor_op = 0x0f, + fmovc_op = 0x11, fmovz_op = 0x12, + fmovn_op = 0x13, frecip_op = 0x15, + frsqrt_op = 0x16, fcvts_op = 0x20, + fcvtd_op = 0x21, fcvte_op = 0x22, + fcvtw_op = 0x24, fcvtl_op = 0x25, + fcmp_op = 0x30 +}; + +/* + * func field of cop1x opcodes (MIPS IV). + */ +enum cop1x_func { + lwxc1_op = 0x00, ldxc1_op = 0x01, + swxc1_op = 0x08, sdxc1_op = 0x09, + pfetch_op = 0x0f, madd_s_op = 0x20, + madd_d_op = 0x21, madd_e_op = 0x22, + msub_s_op = 0x28, msub_d_op = 0x29, + msub_e_op = 0x2a, nmadd_s_op = 0x30, + nmadd_d_op = 0x31, nmadd_e_op = 0x32, + nmsub_s_op = 0x38, nmsub_d_op = 0x39, + nmsub_e_op = 0x3a +}; + +/* + * func field for mad opcodes (MIPS IV). + */ +enum mad_func { + madd_fp_op = 0x08, msub_fp_op = 0x0a, + nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e +}; + +/* + * func field for special3 lx opcodes (Cavium Octeon). + */ +enum lx_func { + lwx_op = 0x00, + lhx_op = 0x04, + lbux_op = 0x06, + ldx_op = 0x08, + lwux_op = 0x10, + lhux_op = 0x14, + lbx_op = 0x16, +}; + +/* + * BSHFL opcodes + */ +enum bshfl_func { + wsbh_op = 0x2, + dshd_op = 0x5, + seb_op = 0x10, + seh_op = 0x18, +}; + +/* + * (microMIPS) Major opcodes. + */ +enum mm_major_op { + mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op, + mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op, + mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op, + mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op, + mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op, + mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op, + mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op, + mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op, + mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op, + mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op, + mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op, + mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op, + mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op, + mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op, + mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op, + mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op, +}; + +/* + * (microMIPS) POOL32I minor opcodes. + */ +enum mm_32i_minor_op { + mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op, + mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op, + mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op, + mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op, + mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op, + mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op, + mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op, + mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op, + mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op, +}; + +/* + * (microMIPS) POOL32A minor opcodes. + */ +enum mm_32a_minor_op { + mm_sll32_op = 0x000, + mm_ins_op = 0x00c, + mm_sllv32_op = 0x010, + mm_ext_op = 0x02c, + mm_pool32axf_op = 0x03c, + mm_srl32_op = 0x040, + mm_sra_op = 0x080, + mm_srlv32_op = 0x090, + mm_rotr_op = 0x0c0, + mm_lwxs_op = 0x118, + mm_addu32_op = 0x150, + mm_subu32_op = 0x1d0, + mm_wsbh_op = 0x1ec, + mm_mul_op = 0x210, + mm_and_op = 0x250, + mm_or32_op = 0x290, + mm_xor32_op = 0x310, + mm_slt_op = 0x350, + mm_sltu_op = 0x390, +}; + +/* + * (microMIPS) POOL32B functions. + */ +enum mm_32b_func { + mm_lwc2_func = 0x0, + mm_lwp_func = 0x1, + mm_ldc2_func = 0x2, + mm_ldp_func = 0x4, + mm_lwm32_func = 0x5, + mm_cache_func = 0x6, + mm_ldm_func = 0x7, + mm_swc2_func = 0x8, + mm_swp_func = 0x9, + mm_sdc2_func = 0xa, + mm_sdp_func = 0xc, + mm_swm32_func = 0xd, + mm_sdm_func = 0xf, +}; + +/* + * (microMIPS) POOL32C functions. + */ +enum mm_32c_func { + mm_pref_func = 0x2, + mm_ll_func = 0x3, + mm_swr_func = 0x9, + mm_sc_func = 0xb, + mm_lwu_func = 0xe, +}; + +/* + * (microMIPS) POOL32AXF minor opcodes. + */ +enum mm_32axf_minor_op { + mm_mfc0_op = 0x003, + mm_mtc0_op = 0x00b, + mm_tlbp_op = 0x00d, + mm_mfhi32_op = 0x035, + mm_jalr_op = 0x03c, + mm_tlbr_op = 0x04d, + mm_mflo32_op = 0x075, + mm_jalrhb_op = 0x07c, + mm_tlbwi_op = 0x08d, + mm_tlbwr_op = 0x0cd, + mm_jalrs_op = 0x13c, + mm_jalrshb_op = 0x17c, + mm_sync_op = 0x1ad, + mm_syscall_op = 0x22d, + mm_wait_op = 0x24d, + mm_eret_op = 0x3cd, + mm_divu_op = 0x5dc, +}; + +/* + * (microMIPS) POOL32F minor opcodes. + */ +enum mm_32f_minor_op { + mm_32f_00_op = 0x00, + mm_32f_01_op = 0x01, + mm_32f_02_op = 0x02, + mm_32f_10_op = 0x08, + mm_32f_11_op = 0x09, + mm_32f_12_op = 0x0a, + mm_32f_20_op = 0x10, + mm_32f_30_op = 0x18, + mm_32f_40_op = 0x20, + mm_32f_41_op = 0x21, + mm_32f_42_op = 0x22, + mm_32f_50_op = 0x28, + mm_32f_51_op = 0x29, + mm_32f_52_op = 0x2a, + mm_32f_60_op = 0x30, + mm_32f_70_op = 0x38, + mm_32f_73_op = 0x3b, + mm_32f_74_op = 0x3c, +}; + +/* + * (microMIPS) POOL32F secondary minor opcodes. + */ +enum mm_32f_10_minor_op { + mm_lwxc1_op = 0x1, + mm_swxc1_op, + mm_ldxc1_op, + mm_sdxc1_op, + mm_luxc1_op, + mm_suxc1_op, +}; + +enum mm_32f_func { + mm_lwxc1_func = 0x048, + mm_swxc1_func = 0x088, + mm_ldxc1_func = 0x0c8, + mm_sdxc1_func = 0x108, +}; + +/* + * (microMIPS) POOL32F secondary minor opcodes. + */ +enum mm_32f_40_minor_op { + mm_fmovf_op, + mm_fmovt_op, +}; + +/* + * (microMIPS) POOL32F secondary minor opcodes. + */ +enum mm_32f_60_minor_op { + mm_fadd_op, + mm_fsub_op, + mm_fmul_op, + mm_fdiv_op, +}; + +/* + * (microMIPS) POOL32F secondary minor opcodes. + */ +enum mm_32f_70_minor_op { + mm_fmovn_op, + mm_fmovz_op, +}; + +/* + * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F. + */ +enum mm_32f_73_minor_op { + mm_fmov0_op = 0x01, + mm_fcvtl_op = 0x04, + mm_movf0_op = 0x05, + mm_frsqrt_op = 0x08, + mm_ffloorl_op = 0x0c, + mm_fabs0_op = 0x0d, + mm_fcvtw_op = 0x24, + mm_movt0_op = 0x25, + mm_fsqrt_op = 0x28, + mm_ffloorw_op = 0x2c, + mm_fneg0_op = 0x2d, + mm_cfc1_op = 0x40, + mm_frecip_op = 0x48, + mm_fceill_op = 0x4c, + mm_fcvtd0_op = 0x4d, + mm_ctc1_op = 0x60, + mm_fceilw_op = 0x6c, + mm_fcvts0_op = 0x6d, + mm_mfc1_op = 0x80, + mm_fmov1_op = 0x81, + mm_movf1_op = 0x85, + mm_ftruncl_op = 0x8c, + mm_fabs1_op = 0x8d, + mm_mtc1_op = 0xa0, + mm_movt1_op = 0xa5, + mm_ftruncw_op = 0xac, + mm_fneg1_op = 0xad, + mm_mfhc1_op = 0xc0, + mm_froundl_op = 0xcc, + mm_fcvtd1_op = 0xcd, + mm_mthc1_op = 0xe0, + mm_froundw_op = 0xec, + mm_fcvts1_op = 0xed, +}; + +/* + * (microMIPS) POOL16C minor opcodes. + */ +enum mm_16c_minor_op { + mm_lwm16_op = 0x04, + mm_swm16_op = 0x05, + mm_jr16_op = 0x0c, + mm_jrc_op = 0x0d, + mm_jalr16_op = 0x0e, + mm_jalrs16_op = 0x0f, + mm_jraddiusp_op = 0x18, +}; + +/* + * (microMIPS) POOL16D minor opcodes. + */ +enum mm_16d_minor_op { + mm_addius5_func, + mm_addiusp_func, +}; + +/* + * (MIPS16e) opcodes. + */ +enum MIPS16e_ops { + MIPS16e_jal_op = 003, + MIPS16e_ld_op = 007, + MIPS16e_i8_op = 014, + MIPS16e_sd_op = 017, + MIPS16e_lb_op = 020, + MIPS16e_lh_op = 021, + MIPS16e_lwsp_op = 022, + MIPS16e_lw_op = 023, + MIPS16e_lbu_op = 024, + MIPS16e_lhu_op = 025, + MIPS16e_lwpc_op = 026, + MIPS16e_lwu_op = 027, + MIPS16e_sb_op = 030, + MIPS16e_sh_op = 031, + MIPS16e_swsp_op = 032, + MIPS16e_sw_op = 033, + MIPS16e_rr_op = 035, + MIPS16e_extend_op = 036, + MIPS16e_i64_op = 037, +}; + +enum MIPS16e_i64_func { + MIPS16e_ldsp_func, + MIPS16e_sdsp_func, + MIPS16e_sdrasp_func, + MIPS16e_dadjsp_func, + MIPS16e_ldpc_func, +}; + +enum MIPS16e_rr_func { + MIPS16e_jr_func, +}; + +enum MIPS6e_i8_func { + MIPS16e_swrasp_func = 02, +}; + +/* + * (microMIPS & MIPS16e) NOP instruction. + */ +#define MM_NOP16 0x0c00 + +struct j_format { + __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */ + __BITFIELD_FIELD(unsigned int target : 26, + ;)) +}; + +struct i_format { /* signed immediate format */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rs : 5, + __BITFIELD_FIELD(unsigned int rt : 5, + __BITFIELD_FIELD(signed int simmediate : 16, + ;)))) +}; + +struct u_format { /* unsigned immediate format */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rs : 5, + __BITFIELD_FIELD(unsigned int rt : 5, + __BITFIELD_FIELD(unsigned int uimmediate : 16, + ;)))) +}; + +struct c_format { /* Cache (>= R6000) format */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rs : 5, + __BITFIELD_FIELD(unsigned int c_op : 3, + __BITFIELD_FIELD(unsigned int cache : 2, + __BITFIELD_FIELD(unsigned int simmediate : 16, + ;))))) +}; + +struct r_format { /* Register format */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rs : 5, + __BITFIELD_FIELD(unsigned int rt : 5, + __BITFIELD_FIELD(unsigned int rd : 5, + __BITFIELD_FIELD(unsigned int re : 5, + __BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct p_format { /* Performance counter format (R10000) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rs : 5, + __BITFIELD_FIELD(unsigned int rt : 5, + __BITFIELD_FIELD(unsigned int rd : 5, + __BITFIELD_FIELD(unsigned int re : 5, + __BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct f_format { /* FPU register format */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int : 1, + __BITFIELD_FIELD(unsigned int fmt : 4, + __BITFIELD_FIELD(unsigned int rt : 5, + __BITFIELD_FIELD(unsigned int rd : 5, + __BITFIELD_FIELD(unsigned int re : 5, + __BITFIELD_FIELD(unsigned int func : 6, + ;))))))) +}; + +struct ma_format { /* FPU multiply and add format (MIPS IV) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int fr : 5, + __BITFIELD_FIELD(unsigned int ft : 5, + __BITFIELD_FIELD(unsigned int fs : 5, + __BITFIELD_FIELD(unsigned int fd : 5, + __BITFIELD_FIELD(unsigned int func : 4, + __BITFIELD_FIELD(unsigned int fmt : 2, + ;))))))) +}; + +struct b_format { /* BREAK and SYSCALL */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int code : 20, + __BITFIELD_FIELD(unsigned int func : 6, + ;))) +}; + +struct ps_format { /* MIPS-3D / paired single format */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rs : 5, + __BITFIELD_FIELD(unsigned int ft : 5, + __BITFIELD_FIELD(unsigned int fs : 5, + __BITFIELD_FIELD(unsigned int fd : 5, + __BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct v_format { /* MDMX vector format */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int sel : 4, + __BITFIELD_FIELD(unsigned int fmt : 1, + __BITFIELD_FIELD(unsigned int vt : 5, + __BITFIELD_FIELD(unsigned int vs : 5, + __BITFIELD_FIELD(unsigned int vd : 5, + __BITFIELD_FIELD(unsigned int func : 6, + ;))))))) +}; + +struct spec3_format { /* SPEC3 */ + __BITFIELD_FIELD(unsigned int opcode:6, + __BITFIELD_FIELD(unsigned int rs:5, + __BITFIELD_FIELD(unsigned int rt:5, + __BITFIELD_FIELD(signed int simmediate:9, + __BITFIELD_FIELD(unsigned int func:7, + ;))))) +}; + +/* + * microMIPS instruction formats (32-bit length) + * + * NOTE: + * Parenthesis denote whether the format is a microMIPS instruction or + * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE. + */ +struct fb_format { /* FPU branch format (MIPS32) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int bc : 5, + __BITFIELD_FIELD(unsigned int cc : 3, + __BITFIELD_FIELD(unsigned int flag : 2, + __BITFIELD_FIELD(signed int simmediate : 16, + ;))))) +}; + +struct fp0_format { /* FPU multiply and add format (MIPS32) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int fmt : 5, + __BITFIELD_FIELD(unsigned int ft : 5, + __BITFIELD_FIELD(unsigned int fs : 5, + __BITFIELD_FIELD(unsigned int fd : 5, + __BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int ft : 5, + __BITFIELD_FIELD(unsigned int fs : 5, + __BITFIELD_FIELD(unsigned int fd : 5, + __BITFIELD_FIELD(unsigned int fmt : 3, + __BITFIELD_FIELD(unsigned int op : 2, + __BITFIELD_FIELD(unsigned int func : 6, + ;))))))) +}; + +struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int op : 5, + __BITFIELD_FIELD(unsigned int rt : 5, + __BITFIELD_FIELD(unsigned int fs : 5, + __BITFIELD_FIELD(unsigned int fd : 5, + __BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rt : 5, + __BITFIELD_FIELD(unsigned int fs : 5, + __BITFIELD_FIELD(unsigned int fmt : 2, + __BITFIELD_FIELD(unsigned int op : 8, + __BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int fd : 5, + __BITFIELD_FIELD(unsigned int fs : 5, + __BITFIELD_FIELD(unsigned int cc : 3, + __BITFIELD_FIELD(unsigned int zero : 2, + __BITFIELD_FIELD(unsigned int fmt : 2, + __BITFIELD_FIELD(unsigned int op : 3, + __BITFIELD_FIELD(unsigned int func : 6, + ;)))))))) +}; + +struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rt : 5, + __BITFIELD_FIELD(unsigned int fs : 5, + __BITFIELD_FIELD(unsigned int fmt : 3, + __BITFIELD_FIELD(unsigned int op : 7, + __BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rt : 5, + __BITFIELD_FIELD(unsigned int fs : 5, + __BITFIELD_FIELD(unsigned int cc : 3, + __BITFIELD_FIELD(unsigned int fmt : 3, + __BITFIELD_FIELD(unsigned int cond : 4, + __BITFIELD_FIELD(unsigned int func : 6, + ;))))))) +}; + +struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int index : 5, + __BITFIELD_FIELD(unsigned int base : 5, + __BITFIELD_FIELD(unsigned int fd : 5, + __BITFIELD_FIELD(unsigned int op : 5, + __BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct fp6_format { /* FPU madd and msub format (MIPS IV) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int fr : 5, + __BITFIELD_FIELD(unsigned int ft : 5, + __BITFIELD_FIELD(unsigned int fs : 5, + __BITFIELD_FIELD(unsigned int fd : 5, + __BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int ft : 5, + __BITFIELD_FIELD(unsigned int fs : 5, + __BITFIELD_FIELD(unsigned int fd : 5, + __BITFIELD_FIELD(unsigned int fr : 5, + __BITFIELD_FIELD(unsigned int func : 6, + ;)))))) +}; + +struct mm_i_format { /* Immediate format (microMIPS) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rt : 5, + __BITFIELD_FIELD(unsigned int rs : 5, + __BITFIELD_FIELD(signed int simmediate : 16, + ;)))) +}; + +struct mm_m_format { /* Multi-word load/store format (microMIPS) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rd : 5, + __BITFIELD_FIELD(unsigned int base : 5, + __BITFIELD_FIELD(unsigned int func : 4, + __BITFIELD_FIELD(signed int simmediate : 12, + ;))))) +}; + +struct mm_x_format { /* Scaled indexed load format (microMIPS) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int index : 5, + __BITFIELD_FIELD(unsigned int base : 5, + __BITFIELD_FIELD(unsigned int rd : 5, + __BITFIELD_FIELD(unsigned int func : 11, + ;))))) +}; + +/* + * microMIPS instruction formats (16-bit length) + */ +struct mm_b0_format { /* Unconditional branch format (microMIPS) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(signed int simmediate : 10, + __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ + ;))) +}; + +struct mm_b1_format { /* Conditional branch format (microMIPS) */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rs : 3, + __BITFIELD_FIELD(signed int simmediate : 7, + __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ + ;)))) +}; + +struct mm16_m_format { /* Multi-word load/store format */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int func : 4, + __BITFIELD_FIELD(unsigned int rlist : 2, + __BITFIELD_FIELD(unsigned int imm : 4, + __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ + ;))))) +}; + +struct mm16_rb_format { /* Signed immediate format */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rt : 3, + __BITFIELD_FIELD(unsigned int base : 3, + __BITFIELD_FIELD(signed int simmediate : 4, + __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ + ;))))) +}; + +struct mm16_r3_format { /* Load from global pointer format */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rt : 3, + __BITFIELD_FIELD(signed int simmediate : 7, + __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ + ;)))) +}; + +struct mm16_r5_format { /* Load/store from stack pointer format */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rt : 5, + __BITFIELD_FIELD(signed int simmediate : 5, + __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ + ;)))) +}; + +/* + * MIPS16e instruction formats (16-bit length) + */ +struct m16e_rr { + __BITFIELD_FIELD(unsigned int opcode : 5, + __BITFIELD_FIELD(unsigned int rx : 3, + __BITFIELD_FIELD(unsigned int nd : 1, + __BITFIELD_FIELD(unsigned int l : 1, + __BITFIELD_FIELD(unsigned int ra : 1, + __BITFIELD_FIELD(unsigned int func : 5, + ;)))))) +}; + +struct m16e_jal { + __BITFIELD_FIELD(unsigned int opcode : 5, + __BITFIELD_FIELD(unsigned int x : 1, + __BITFIELD_FIELD(unsigned int imm20_16 : 5, + __BITFIELD_FIELD(signed int imm25_21 : 5, + ;)))) +}; + +struct m16e_i64 { + __BITFIELD_FIELD(unsigned int opcode : 5, + __BITFIELD_FIELD(unsigned int func : 3, + __BITFIELD_FIELD(unsigned int imm : 8, + ;))) +}; + +struct m16e_ri64 { + __BITFIELD_FIELD(unsigned int opcode : 5, + __BITFIELD_FIELD(unsigned int func : 3, + __BITFIELD_FIELD(unsigned int ry : 3, + __BITFIELD_FIELD(unsigned int imm : 5, + ;)))) +}; + +struct m16e_ri { + __BITFIELD_FIELD(unsigned int opcode : 5, + __BITFIELD_FIELD(unsigned int rx : 3, + __BITFIELD_FIELD(unsigned int imm : 8, + ;))) +}; + +struct m16e_rri { + __BITFIELD_FIELD(unsigned int opcode : 5, + __BITFIELD_FIELD(unsigned int rx : 3, + __BITFIELD_FIELD(unsigned int ry : 3, + __BITFIELD_FIELD(unsigned int imm : 5, + ;)))) +}; + +struct m16e_i8 { + __BITFIELD_FIELD(unsigned int opcode : 5, + __BITFIELD_FIELD(unsigned int func : 3, + __BITFIELD_FIELD(unsigned int imm : 8, + ;))) +}; + +union mips_instruction { + unsigned int word; + unsigned short halfword[2]; + unsigned char byte[4]; + struct j_format j_format; + struct i_format i_format; + struct u_format u_format; + struct c_format c_format; + struct r_format r_format; + struct p_format p_format; + struct f_format f_format; + struct ma_format ma_format; + struct b_format b_format; + struct ps_format ps_format; + struct v_format v_format; + struct spec3_format spec3_format; + struct fb_format fb_format; + struct fp0_format fp0_format; + struct mm_fp0_format mm_fp0_format; + struct fp1_format fp1_format; + struct mm_fp1_format mm_fp1_format; + struct mm_fp2_format mm_fp2_format; + struct mm_fp3_format mm_fp3_format; + struct mm_fp4_format mm_fp4_format; + struct mm_fp5_format mm_fp5_format; + struct fp6_format fp6_format; + struct mm_fp6_format mm_fp6_format; + struct mm_i_format mm_i_format; + struct mm_m_format mm_m_format; + struct mm_x_format mm_x_format; + struct mm_b0_format mm_b0_format; + struct mm_b1_format mm_b1_format; + struct mm16_m_format mm16_m_format ; + struct mm16_rb_format mm16_rb_format; + struct mm16_r3_format mm16_r3_format; + struct mm16_r5_format mm16_r5_format; +}; + +union mips16e_instruction { + unsigned int full : 16; + struct m16e_rr rr; + struct m16e_jal jal; + struct m16e_i64 i64; + struct m16e_ri64 ri64; + struct m16e_ri ri; + struct m16e_rri rri; + struct m16e_i8 i8; +}; + +#endif /* _UAPI_ASM_INST_H */ diff --git a/arch/mips/include/uapi/asm/ioctls.h b/arch/mips/include/uapi/asm/ioctls.h index addd56b6069..b1e637757fe 100644 --- a/arch/mips/include/uapi/asm/ioctls.h +++ b/arch/mips/include/uapi/asm/ioctls.h @@ -41,7 +41,7 @@ #define TIOCPKT_START 0x08 /* start output */ #define TIOCPKT_NOSTOP 0x10 /* no more ^S, ^Q */ #define TIOCPKT_DOSTOP 0x20 /* now do ^S ^Q */ -#define TIOCPKT_IOCTL 0x40 /* state change of pty driver */ +#define TIOCPKT_IOCTL 0x40 /* state change of pty driver */ #define TIOCSWINSZ _IOW('t', 103, struct winsize) /* set window size */ #define TIOCGWINSZ _IOR('t', 104, struct winsize) /* get window size */ #define TIOCNOTTY 0x5471 /* void tty association */ @@ -63,9 +63,9 @@ #define FIONREAD 0x467f #define TIOCINQ FIONREAD -#define TIOCGETP 0x7408 -#define TIOCSETP 0x7409 -#define TIOCSETN 0x740a /* TIOCSETP wo flush */ +#define TIOCGETP 0x7408 +#define TIOCSETP 0x7409 +#define TIOCSETN 0x740a /* TIOCSETP wo flush */ /* #define TIOCSETA _IOW('t', 20, struct termios) set termios struct */ /* #define TIOCSETAW _IOW('t', 21, struct termios) drain output, set */ @@ -74,9 +74,9 @@ /* #define TIOCSETD _IOW('t', 27, int) set line discipline */ /* 127-124 compat */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x7416 /* Return the session ID of FD */ +#define TIOCSBRK 0x5427 /* BSD compatibility */ +#define TIOCCBRK 0x5428 /* BSD compatibility */ +#define TIOCGSID 0x7416 /* Return the session ID of FD */ #define TCGETS2 _IOR('T', 0x2A, struct termios2) #define TCSETS2 _IOW('T', 0x2B, struct termios2) #define TCSETSW2 _IOW('T', 0x2C, struct termios2) @@ -104,10 +104,10 @@ #define TIOCGLCKTRMIOS 0x548b #define TIOCSLCKTRMIOS 0x548c #define TIOCSERGSTRUCT 0x548d /* For debugging only */ -#define TIOCSERGETLSR 0x548e /* Get line status register */ -#define TIOCSERGETMULTI 0x548f /* Get multiport config */ +#define TIOCSERGETLSR 0x548e /* Get line status register */ +#define TIOCSERGETMULTI 0x548f /* Get multiport config */ #define TIOCSERSETMULTI 0x5490 /* Set multiport config */ -#define TIOCMIWAIT 0x5491 /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x5492 /* read serial port inline interrupt counts */ +#define TIOCMIWAIT 0x5491 /* wait for a change on serial input line(s) */ +#define TIOCGICOUNT 0x5492 /* read serial port inline interrupt counts */ #endif /* __ASM_IOCTLS_H */ diff --git a/arch/mips/include/uapi/asm/ipcbuf.h b/arch/mips/include/uapi/asm/ipcbuf.h deleted file mode 100644 index 84c7e51cb6d..00000000000 --- a/arch/mips/include/uapi/asm/ipcbuf.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/ipcbuf.h> diff --git a/arch/mips/include/uapi/asm/kvm.h b/arch/mips/include/uapi/asm/kvm.h new file mode 100644 index 00000000000..2c04b6d9ff8 --- /dev/null +++ b/arch/mips/include/uapi/asm/kvm.h @@ -0,0 +1,170 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2013 Cavium, Inc. + * Authors: Sanjay Lal <sanjayl@kymasys.com> + */ + +#ifndef __LINUX_KVM_MIPS_H +#define __LINUX_KVM_MIPS_H + +#include <linux/types.h> + +/* + * KVM MIPS specific structures and definitions. + * + * Some parts derived from the x86 version of this file. + */ + +/* + * for KVM_GET_REGS and KVM_SET_REGS + * + * If Config[AT] is zero (32-bit CPU), the register contents are + * stored in the lower 32-bits of the struct kvm_regs fields and sign + * extended to 64-bits. + */ +struct kvm_regs { + /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ + __u64 gpr[32]; + __u64 hi; + __u64 lo; + __u64 pc; +}; + +/* + * for KVM_GET_FPU and KVM_SET_FPU + * + * If Status[FR] is zero (32-bit FPU), the upper 32-bits of the FPRs + * are zero filled. + */ +struct kvm_fpu { + __u64 fpr[32]; + __u32 fir; + __u32 fccr; + __u32 fexr; + __u32 fenr; + __u32 fcsr; + __u32 pad; +}; + + +/* + * For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access CP0 + * registers. The id field is broken down as follows: + * + * bits[2..0] - Register 'sel' index. + * bits[7..3] - Register 'rd' index. + * bits[15..8] - Must be zero. + * bits[31..16] - 1 -> CP0 registers. + * bits[51..32] - Must be zero. + * bits[63..52] - As per linux/kvm.h + * + * Other sets registers may be added in the future. Each set would + * have its own identifier in bits[31..16]. + * + * The registers defined in struct kvm_regs are also accessible, the + * id values for these are below. + */ + +#define KVM_REG_MIPS_R0 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0) +#define KVM_REG_MIPS_R1 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 1) +#define KVM_REG_MIPS_R2 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 2) +#define KVM_REG_MIPS_R3 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 3) +#define KVM_REG_MIPS_R4 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 4) +#define KVM_REG_MIPS_R5 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 5) +#define KVM_REG_MIPS_R6 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 6) +#define KVM_REG_MIPS_R7 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 7) +#define KVM_REG_MIPS_R8 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 8) +#define KVM_REG_MIPS_R9 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 9) +#define KVM_REG_MIPS_R10 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 10) +#define KVM_REG_MIPS_R11 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 11) +#define KVM_REG_MIPS_R12 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 12) +#define KVM_REG_MIPS_R13 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 13) +#define KVM_REG_MIPS_R14 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 14) +#define KVM_REG_MIPS_R15 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 15) +#define KVM_REG_MIPS_R16 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 16) +#define KVM_REG_MIPS_R17 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 17) +#define KVM_REG_MIPS_R18 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 18) +#define KVM_REG_MIPS_R19 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 19) +#define KVM_REG_MIPS_R20 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 20) +#define KVM_REG_MIPS_R21 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 21) +#define KVM_REG_MIPS_R22 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 22) +#define KVM_REG_MIPS_R23 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 23) +#define KVM_REG_MIPS_R24 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 24) +#define KVM_REG_MIPS_R25 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 25) +#define KVM_REG_MIPS_R26 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 26) +#define KVM_REG_MIPS_R27 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 27) +#define KVM_REG_MIPS_R28 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 28) +#define KVM_REG_MIPS_R29 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 29) +#define KVM_REG_MIPS_R30 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 30) +#define KVM_REG_MIPS_R31 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 31) + +#define KVM_REG_MIPS_HI (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 32) +#define KVM_REG_MIPS_LO (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 33) +#define KVM_REG_MIPS_PC (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 34) + +/* KVM specific control registers */ + +/* + * CP0_Count control + * DC: Set 0: Master disable CP0_Count and set COUNT_RESUME to now + * Set 1: Master re-enable CP0_Count with unchanged bias, handling timer + * interrupts since COUNT_RESUME + * This can be used to freeze the timer to get a consistent snapshot of + * the CP0_Count and timer interrupt pending state, while also resuming + * safely without losing time or guest timer interrupts. + * Other: Reserved, do not change. + */ +#define KVM_REG_MIPS_COUNT_CTL (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \ + 0x20000 | 0) +#define KVM_REG_MIPS_COUNT_CTL_DC 0x00000001 + +/* + * CP0_Count resume monotonic nanoseconds + * The monotonic nanosecond time of the last set of COUNT_CTL.DC (master + * disable). Any reads and writes of Count related registers while + * COUNT_CTL.DC=1 will appear to occur at this time. When COUNT_CTL.DC is + * cleared again (master enable) any timer interrupts since this time will be + * emulated. + * Modifications to times in the future are rejected. + */ +#define KVM_REG_MIPS_COUNT_RESUME (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \ + 0x20000 | 1) +/* + * CP0_Count rate in Hz + * Specifies the rate of the CP0_Count timer in Hz. Modifications occur without + * discontinuities in CP0_Count. + */ +#define KVM_REG_MIPS_COUNT_HZ (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \ + 0x20000 | 2) + +/* + * KVM MIPS specific structures and definitions + * + */ +struct kvm_debug_exit_arch { + __u64 epc; +}; + +/* for KVM_SET_GUEST_DEBUG */ +struct kvm_guest_debug_arch { +}; + +/* definition of registers in kvm_run */ +struct kvm_sync_regs { +}; + +/* dummy definition */ +struct kvm_sregs { +}; + +struct kvm_mips_interrupt { + /* in */ + __u32 cpu; + __u32 irq; +}; + +#endif /* __LINUX_KVM_MIPS_H */ diff --git a/arch/mips/include/uapi/asm/kvm_para.h b/arch/mips/include/uapi/asm/kvm_para.h index 14fab8f0b95..7e16d7c42e6 100644 --- a/arch/mips/include/uapi/asm/kvm_para.h +++ b/arch/mips/include/uapi/asm/kvm_para.h @@ -1 +1,5 @@ -#include <asm-generic/kvm_para.h> +#ifndef _UAPI_ASM_MIPS_KVM_PARA_H +#define _UAPI_ASM_MIPS_KVM_PARA_H + + +#endif /* _UAPI_ASM_MIPS_KVM_PARA_H */ diff --git a/arch/mips/include/uapi/asm/mman.h b/arch/mips/include/uapi/asm/mman.h index 9a936ac9a94..cfcb876cae6 100644 --- a/arch/mips/include/uapi/asm/mman.h +++ b/arch/mips/include/uapi/asm/mman.h @@ -64,7 +64,7 @@ #define MADV_NORMAL 0 /* no further special treatment */ #define MADV_RANDOM 1 /* expect random page references */ -#define MADV_SEQUENTIAL 2 /* expect sequential page references */ +#define MADV_SEQUENTIAL 2 /* expect sequential page references */ #define MADV_WILLNEED 3 /* will need these pages */ #define MADV_DONTNEED 4 /* don't need these pages */ @@ -73,14 +73,14 @@ #define MADV_DONTFORK 10 /* don't inherit across fork */ #define MADV_DOFORK 11 /* do inherit across fork */ -#define MADV_MERGEABLE 12 /* KSM may merge identical pages */ +#define MADV_MERGEABLE 12 /* KSM may merge identical pages */ #define MADV_UNMERGEABLE 13 /* KSM may not merge identical pages */ -#define MADV_HWPOISON 100 /* poison a page for testing */ +#define MADV_HWPOISON 100 /* poison a page for testing */ #define MADV_HUGEPAGE 14 /* Worth backing with hugepages */ -#define MADV_NOHUGEPAGE 15 /* Not worth backing with hugepages */ +#define MADV_NOHUGEPAGE 15 /* Not worth backing with hugepages */ -#define MADV_DONTDUMP 16 /* Explicity exclude from the core dump, +#define MADV_DONTDUMP 16 /* Explicity exclude from the core dump, overrides the coredump filter bits */ #define MADV_DODUMP 17 /* Clear the MADV_NODUMP flag */ diff --git a/arch/mips/include/uapi/asm/msgbuf.h b/arch/mips/include/uapi/asm/msgbuf.h index 0d6c7f14de3..df849e87d9a 100644 --- a/arch/mips/include/uapi/asm/msgbuf.h +++ b/arch/mips/include/uapi/asm/msgbuf.h @@ -14,25 +14,25 @@ struct msqid64_ds { struct ipc64_perm msg_perm; -#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) +#if !defined(__mips64) && defined(__MIPSEB__) unsigned long __unused1; #endif __kernel_time_t msg_stime; /* last msgsnd time */ -#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) +#if !defined(__mips64) && defined(__MIPSEL__) unsigned long __unused1; #endif -#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) +#if !defined(__mips64) && defined(__MIPSEB__) unsigned long __unused2; #endif __kernel_time_t msg_rtime; /* last msgrcv time */ -#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) +#if !defined(__mips64) && defined(__MIPSEL__) unsigned long __unused2; #endif -#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) +#if !defined(__mips64) && defined(__MIPSEB__) unsigned long __unused3; #endif __kernel_time_t msg_ctime; /* last change time */ -#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) +#if !defined(__mips64) && defined(__MIPSEL__) unsigned long __unused3; #endif unsigned long msg_cbytes; /* current number of bytes on queue */ diff --git a/arch/mips/include/uapi/asm/ptrace.h b/arch/mips/include/uapi/asm/ptrace.h index 1bc1f52f40d..b26f7e31727 100644 --- a/arch/mips/include/uapi/asm/ptrace.h +++ b/arch/mips/include/uapi/asm/ptrace.h @@ -22,16 +22,12 @@ #define DSP_CONTROL 77 #define ACX 78 +#ifndef __KERNEL__ /* * This struct defines the way the registers are stored on the stack during a * system call/exception. As usual the registers k0/k1 aren't being saved. */ struct pt_regs { -#ifdef CONFIG_32BIT - /* Pad bytes for argument save space on the stack. */ - unsigned long pad0[6]; -#endif - /* Saved main processor registers. */ unsigned long regs[32]; @@ -39,20 +35,11 @@ struct pt_regs { unsigned long cp0_status; unsigned long hi; unsigned long lo; -#ifdef CONFIG_CPU_HAS_SMARTMIPS - unsigned long acx; -#endif unsigned long cp0_badvaddr; unsigned long cp0_cause; unsigned long cp0_epc; -#ifdef CONFIG_MIPS_MT_SMTC - unsigned long cp0_tcstatus; -#endif /* CONFIG_MIPS_MT_SMTC */ -#ifdef CONFIG_CPU_CAVIUM_OCTEON - unsigned long long mpl[3]; /* MTM{0,1,2} */ - unsigned long long mtp[3]; /* MTP{0,1,2} */ -#endif } __attribute__ ((aligned (8))); +#endif /* __KERNEL__ */ /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ #define PTRACE_GETREGS 12 @@ -67,14 +54,14 @@ struct pt_regs { #define PTRACE_GET_THREAD_AREA 25 #define PTRACE_SET_THREAD_AREA 26 -/* Calls to trace a 64bit program from a 32bit program. */ +/* Calls to trace a 64bit program from a 32bit program. */ #define PTRACE_PEEKTEXT_3264 0xc0 #define PTRACE_PEEKDATA_3264 0xc1 #define PTRACE_POKETEXT_3264 0xc2 #define PTRACE_POKEDATA_3264 0xc3 #define PTRACE_GET_THREAD_AREA_3264 0xc4 -/* Read and write watchpoint registers. */ +/* Read and write watchpoint registers. */ enum pt_watch_style { pt_watch_style_mips32, pt_watch_style_mips64 diff --git a/arch/mips/include/uapi/asm/resource.h b/arch/mips/include/uapi/asm/resource.h index 87cb3085269..b26439d4ab0 100644 --- a/arch/mips/include/uapi/asm/resource.h +++ b/arch/mips/include/uapi/asm/resource.h @@ -26,7 +26,7 @@ * but we keep the old value on MIPS32, * for compatibility: */ -#ifdef CONFIG_32BIT +#ifndef __mips64 # define RLIM_INFINITY 0x7fffffffUL #endif diff --git a/arch/mips/include/uapi/asm/sembuf.h b/arch/mips/include/uapi/asm/sembuf.h index 7281a4decaa..e1085ac880f 100644 --- a/arch/mips/include/uapi/asm/sembuf.h +++ b/arch/mips/include/uapi/asm/sembuf.h @@ -12,8 +12,8 @@ struct semid64_ds { struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ - __kernel_time_t sem_otime; /* last semop time */ - __kernel_time_t sem_ctime; /* last change time */ + __kernel_time_t sem_otime; /* last semop time */ + __kernel_time_t sem_ctime; /* last change time */ unsigned long sem_nsems; /* no. of semaphores in array */ unsigned long __unused1; unsigned long __unused2; diff --git a/arch/mips/include/uapi/asm/siginfo.h b/arch/mips/include/uapi/asm/siginfo.h index 73446508d84..e81174432ba 100644 --- a/arch/mips/include/uapi/asm/siginfo.h +++ b/arch/mips/include/uapi/asm/siginfo.h @@ -11,7 +11,7 @@ #define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(long) + 2*sizeof(int)) -#undef __ARCH_SI_TRAPNO /* exception code needs to fill this ... */ +#undef __ARCH_SI_TRAPNO /* exception code needs to fill this ... */ #define HAVE_ARCH_SIGINFO_T @@ -25,13 +25,16 @@ struct siginfo; /* * Careful to keep union _sifields from shifting ... */ -#ifdef CONFIG_32BIT +#if _MIPS_SZLONG == 32 #define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int)) -#endif -#ifdef CONFIG_64BIT +#elif _MIPS_SZLONG == 64 #define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) +#else +#error _MIPS_SZLONG neither 32 nor 64 #endif +#define __ARCH_SIGSYS + #include <asm-generic/siginfo.h> typedef struct siginfo { @@ -55,7 +58,7 @@ typedef struct siginfo { int _overrun; /* overrun count */ char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)]; sigval_t _sigval; /* same as below */ - int _sys_private; /* not to be passed to user */ + int _sys_private; /* not to be passed to user */ } _timer; /* POSIX.1b signals */ @@ -91,11 +94,18 @@ typedef struct siginfo { short _addr_lsb; } _sigfault; - /* SIGPOLL, SIGXFSZ (To do ...) */ + /* SIGPOLL, SIGXFSZ (To do ...) */ struct { - __ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */ + __ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */ int _fd; } _sigpoll; + + /* SIGSYS */ + struct { + void __user *_call_addr; /* calling user insn */ + int _syscall; /* triggering system call number */ + unsigned int _arch; /* AUDIT_ARCH_* of syscall */ + } _sigsys; } _sifields; } siginfo_t; diff --git a/arch/mips/include/uapi/asm/signal.h b/arch/mips/include/uapi/asm/signal.h index 770732cb8d0..addb9f556b7 100644 --- a/arch/mips/include/uapi/asm/signal.h +++ b/arch/mips/include/uapi/asm/signal.h @@ -24,28 +24,28 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */ #define SIGHUP 1 /* Hangup (POSIX). */ #define SIGINT 2 /* Interrupt (ANSI). */ #define SIGQUIT 3 /* Quit (POSIX). */ -#define SIGILL 4 /* Illegal instruction (ANSI). */ -#define SIGTRAP 5 /* Trace trap (POSIX). */ -#define SIGIOT 6 /* IOT trap (4.2 BSD). */ -#define SIGABRT SIGIOT /* Abort (ANSI). */ +#define SIGILL 4 /* Illegal instruction (ANSI). */ +#define SIGTRAP 5 /* Trace trap (POSIX). */ +#define SIGIOT 6 /* IOT trap (4.2 BSD). */ +#define SIGABRT SIGIOT /* Abort (ANSI). */ #define SIGEMT 7 #define SIGFPE 8 /* Floating-point exception (ANSI). */ #define SIGKILL 9 /* Kill, unblockable (POSIX). */ -#define SIGBUS 10 /* BUS error (4.2 BSD). */ +#define SIGBUS 10 /* BUS error (4.2 BSD). */ #define SIGSEGV 11 /* Segmentation violation (ANSI). */ #define SIGSYS 12 -#define SIGPIPE 13 /* Broken pipe (POSIX). */ -#define SIGALRM 14 /* Alarm clock (POSIX). */ -#define SIGTERM 15 /* Termination (ANSI). */ +#define SIGPIPE 13 /* Broken pipe (POSIX). */ +#define SIGALRM 14 /* Alarm clock (POSIX). */ +#define SIGTERM 15 /* Termination (ANSI). */ #define SIGUSR1 16 /* User-defined signal 1 (POSIX). */ #define SIGUSR2 17 /* User-defined signal 2 (POSIX). */ #define SIGCHLD 18 /* Child status has changed (POSIX). */ -#define SIGCLD SIGCHLD /* Same as SIGCHLD (System V). */ +#define SIGCLD SIGCHLD /* Same as SIGCHLD (System V). */ #define SIGPWR 19 /* Power failure restart (System V). */ #define SIGWINCH 20 /* Window size change (4.3 BSD, Sun). */ #define SIGURG 21 /* Urgent condition on socket (4.2 BSD). */ -#define SIGIO 22 /* I/O now possible (4.2 BSD). */ -#define SIGPOLL SIGIO /* Pollable event occurred (System V). */ +#define SIGIO 22 /* I/O now possible (4.2 BSD). */ +#define SIGPOLL SIGIO /* Pollable event occurred (System V). */ #define SIGSTOP 23 /* Stop, unblockable (POSIX). */ #define SIGTSTP 24 /* Keyboard stop (POSIX). */ #define SIGCONT 25 /* Continue (POSIX). */ @@ -54,7 +54,7 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */ #define SIGVTALRM 28 /* Virtual alarm clock (4.2 BSD). */ #define SIGPROF 29 /* Profiling alarm clock (4.2 BSD). */ #define SIGXCPU 30 /* CPU limit exceeded (4.2 BSD). */ -#define SIGXFSZ 31 /* File size limit exceeded (4.2 BSD). */ +#define SIGXFSZ 31 /* File size limit exceeded (4.2 BSD). */ /* These should not be considered constants from userland. */ #define SIGRTMIN 32 @@ -72,6 +72,12 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */ * * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single * Unix names RESETHAND and NODEFER respectively. + * + * SA_RESTORER used to be defined as 0x04000000 but only the O32 ABI ever + * supported its use and no libc was using it, so the entire sa-restorer + * functionality was removed with lmo commit 39bffc12c3580ab for 2.5.48 + * retaining only the SA_RESTORER definition as a reminder to avoid + * accidental reuse of the mask bit. */ #define SA_ONSTACK 0x08000000 #define SA_RESETHAND 0x80000000 @@ -84,8 +90,6 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */ #define SA_NOMASK SA_NODEFER #define SA_ONESHOT SA_RESETHAND -#define SA_RESTORER 0x04000000 /* Only for o32 */ - #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 @@ -96,15 +100,13 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */ #include <asm-generic/signal-defs.h> +#ifndef __KERNEL__ struct sigaction { unsigned int sa_flags; __sighandler_t sa_handler; sigset_t sa_mask; }; - -struct k_sigaction { - struct sigaction sa; -}; +#endif /* IRIX compatible stack_t */ typedef struct sigaltstack { diff --git a/arch/mips/include/uapi/asm/socket.h b/arch/mips/include/uapi/asm/socket.h index 17307ab9047..a14baa218c7 100644 --- a/arch/mips/include/uapi/asm/socket.h +++ b/arch/mips/include/uapi/asm/socket.h @@ -24,23 +24,21 @@ SIGPIPE when they die. */ #define SO_DONTROUTE 0x0010 /* Don't do local routing. */ #define SO_BROADCAST 0x0020 /* Allow transmission of - broadcast messages. */ + broadcast messages. */ #define SO_LINGER 0x0080 /* Block on close of a reliable socket to transmit pending data. */ #define SO_OOBINLINE 0x0100 /* Receive out-of-band data in-band. */ -#if 0 -To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */ -#endif +#define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */ #define SO_TYPE 0x1008 /* Compatible name for SO_STYLE. */ -#define SO_STYLE SO_TYPE /* Synonym */ +#define SO_STYLE SO_TYPE /* Synonym */ #define SO_ERROR 0x1007 /* get error status and clear */ #define SO_SNDBUF 0x1001 /* Send buffer size. */ #define SO_RCVBUF 0x1002 /* Receive buffer. */ #define SO_SNDLOWAT 0x1003 /* send low-water mark */ #define SO_RCVLOWAT 0x1004 /* receive low-water mark */ #define SO_SNDTIMEO 0x1005 /* send timeout */ -#define SO_RCVTIMEO 0x1006 /* receive timeout */ +#define SO_RCVTIMEO 0x1006 /* receive timeout */ #define SO_ACCEPTCONN 0x1009 #define SO_PROTOCOL 0x1028 /* protocol type */ #define SO_DOMAIN 0x1029 /* domain/socket family */ @@ -61,11 +59,11 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */ #define SO_BINDTODEVICE 25 /* Socket filtering */ -#define SO_ATTACH_FILTER 26 -#define SO_DETACH_FILTER 27 +#define SO_ATTACH_FILTER 26 +#define SO_DETACH_FILTER 27 #define SO_GET_FILTER SO_ATTACH_FILTER -#define SO_PEERNAME 28 +#define SO_PEERNAME 28 #define SO_TIMESTAMP 29 #define SCM_TIMESTAMP SO_TIMESTAMP @@ -81,7 +79,7 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */ #define SO_TIMESTAMPING 37 #define SCM_TIMESTAMPING SO_TIMESTAMPING -#define SO_RXQ_OVFL 40 +#define SO_RXQ_OVFL 40 #define SO_WIFI_STATUS 41 #define SCM_WIFI_STATUS SO_WIFI_STATUS @@ -90,5 +88,14 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */ /* Instruct lower device to use last 4-bytes of skb data as FCS */ #define SO_NOFCS 43 +#define SO_LOCK_FILTER 44 + +#define SO_SELECT_ERR_QUEUE 45 + +#define SO_BUSY_POLL 46 + +#define SO_MAX_PACING_RATE 47 + +#define SO_BPF_EXTENSIONS 48 #endif /* _UAPI_ASM_SOCKET_H */ diff --git a/arch/mips/include/uapi/asm/sockios.h b/arch/mips/include/uapi/asm/sockios.h index ed1a5f78d22..419fbe661da 100644 --- a/arch/mips/include/uapi/asm/sockios.h +++ b/arch/mips/include/uapi/asm/sockios.h @@ -14,7 +14,7 @@ /* Socket-level I/O control calls. */ #define FIOGETOWN _IOR('f', 123, int) -#define FIOSETOWN _IOW('f', 124, int) +#define FIOSETOWN _IOW('f', 124, int) #define SIOCATMARK _IOR('s', 7, int) #define SIOCSPGRP _IOW('s', 8, pid_t) diff --git a/arch/mips/include/uapi/asm/stat.h b/arch/mips/include/uapi/asm/stat.h index fe9a4c3ec5a..b47bc541bbc 100644 --- a/arch/mips/include/uapi/asm/stat.h +++ b/arch/mips/include/uapi/asm/stat.h @@ -23,7 +23,7 @@ struct stat { __u32 st_nlink; uid_t st_uid; gid_t st_gid; - unsigned st_rdev; + unsigned st_rdev; long st_pad2[2]; off_t st_size; long st_pad3; diff --git a/arch/mips/include/uapi/asm/statfs.h b/arch/mips/include/uapi/asm/statfs.h index 0f805c7a42a..3305c834fc1 100644 --- a/arch/mips/include/uapi/asm/statfs.h +++ b/arch/mips/include/uapi/asm/statfs.h @@ -15,7 +15,7 @@ #include <linux/types.h> -typedef __kernel_fsid_t fsid_t; +typedef __kernel_fsid_t fsid_t; #endif @@ -31,7 +31,7 @@ struct statfs { long f_bavail; /* Linux specials */ - __kernel_fsid_t f_fsid; + __kernel_fsid_t f_fsid; long f_namelen; long f_flags; long f_spare[5]; @@ -73,7 +73,7 @@ struct statfs64 { /* Same as struct statfs */ long f_bavail; /* Linux specials */ - __kernel_fsid_t f_fsid; + __kernel_fsid_t f_fsid; long f_namelen; long f_flags; long f_spare[5]; diff --git a/arch/mips/include/uapi/asm/swab.h b/arch/mips/include/uapi/asm/swab.h index 97c2f81b4b4..ac9a8f9cd1f 100644 --- a/arch/mips/include/uapi/asm/swab.h +++ b/arch/mips/include/uapi/asm/swab.h @@ -13,7 +13,7 @@ #define __SWAB_64_THRU_32__ -#ifdef CONFIG_CPU_MIPSR2 +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) static inline __attribute_const__ __u16 __arch_swab16(__u16 x) { @@ -39,10 +39,10 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x) #define __arch_swab32 __arch_swab32 /* - * Having already checked for CONFIG_CPU_MIPSR2, enable the - * optimized version for 64-bit kernel on r2 CPUs. + * Having already checked for MIPS R2, enable the optimized version for + * 64-bit kernel on r2 CPUs. */ -#ifdef CONFIG_64BIT +#ifdef __mips64 static inline __attribute_const__ __u64 __arch_swab64(__u64 x) { __asm__( @@ -54,6 +54,6 @@ static inline __attribute_const__ __u64 __arch_swab64(__u64 x) return x; } #define __arch_swab64 __arch_swab64 -#endif /* CONFIG_64BIT */ -#endif /* CONFIG_CPU_MIPSR2 */ +#endif /* __mips64 */ +#endif /* MIPS R2 or newer */ #endif /* _ASM_SWAB_H */ diff --git a/arch/mips/include/uapi/asm/sysmips.h b/arch/mips/include/uapi/asm/sysmips.h index 4f47b7d6a5f..ae637e90785 100644 --- a/arch/mips/include/uapi/asm/sysmips.h +++ b/arch/mips/include/uapi/asm/sysmips.h @@ -16,10 +16,10 @@ * sysmips(2) is deprecated - though some existing software uses it. * We only support the following commands. */ -#define SETNAME 1 /* set hostname */ +#define SETNAME 1 /* set hostname */ #define FLUSH_CACHE 3 /* writeback and invalidate caches */ -#define MIPS_FIXADE 7 /* control address error fixing */ -#define MIPS_RDNVRAM 10 /* read NVRAM */ -#define MIPS_ATOMIC_SET 2001 /* atomically set variable */ +#define MIPS_FIXADE 7 /* control address error fixing */ +#define MIPS_RDNVRAM 10 /* read NVRAM */ +#define MIPS_ATOMIC_SET 2001 /* atomically set variable */ #endif /* _ASM_SYSMIPS_H */ diff --git a/arch/mips/include/uapi/asm/termbits.h b/arch/mips/include/uapi/asm/termbits.h index 76630b396fa..2750203e1e7 100644 --- a/arch/mips/include/uapi/asm/termbits.h +++ b/arch/mips/include/uapi/asm/termbits.h @@ -53,7 +53,7 @@ struct ktermios { }; /* c_cc characters */ -#define VINTR 0 /* Interrupt character [ISIG]. */ +#define VINTR 0 /* Interrupt character [ISIG]. */ #define VQUIT 1 /* Quit character [ISIG]. */ #define VERASE 2 /* Erase character [ICANON]. */ #define VKILL 3 /* Kill-line character [ICANON]. */ @@ -72,7 +72,7 @@ struct ktermios { #define VDSUSP 11 /* Delayed suspend character [ISIG]. */ #endif #define VREPRINT 12 /* Reprint-line character [ICANON]. */ -#define VDISCARD 13 /* Discard character [IEXTEN]. */ +#define VDISCARD 13 /* Discard character [IEXTEN]. */ #define VWERASE 14 /* Word-erase character [ICANON]. */ #define VLNEXT 15 /* Literal-next character [IEXTEN]. */ #define VEOF 16 /* End-of-file character [ICANON]. */ @@ -92,7 +92,7 @@ struct ktermios { #define IXON 0002000 /* Enable start/stop output control. */ #define IXANY 0004000 /* Any character will restart after stop. */ #define IXOFF 0010000 /* Enable start/stop input control. */ -#define IMAXBEL 0020000 /* Ring bell when input queue is full. */ +#define IMAXBEL 0020000 /* Ring bell when input queue is full. */ #define IUTF8 0040000 /* Input is UTF-8 */ /* c_oflag bits */ @@ -105,123 +105,123 @@ struct ktermios { #define OFILL 0000100 #define OFDEL 0000200 #define NLDLY 0000400 -#define NL0 0000000 -#define NL1 0000400 +#define NL0 0000000 +#define NL1 0000400 #define CRDLY 0003000 -#define CR0 0000000 -#define CR1 0001000 -#define CR2 0002000 -#define CR3 0003000 +#define CR0 0000000 +#define CR1 0001000 +#define CR2 0002000 +#define CR3 0003000 #define TABDLY 0014000 -#define TAB0 0000000 -#define TAB1 0004000 -#define TAB2 0010000 -#define TAB3 0014000 -#define XTABS 0014000 +#define TAB0 0000000 +#define TAB1 0004000 +#define TAB2 0010000 +#define TAB3 0014000 +#define XTABS 0014000 #define BSDLY 0020000 -#define BS0 0000000 -#define BS1 0020000 +#define BS0 0000000 +#define BS1 0020000 #define VTDLY 0040000 -#define VT0 0000000 -#define VT1 0040000 +#define VT0 0000000 +#define VT1 0040000 #define FFDLY 0100000 -#define FF0 0000000 -#define FF1 0100000 +#define FF0 0000000 +#define FF1 0100000 /* #define PAGEOUT ??? -#define WRAP ??? +#define WRAP ??? */ /* c_cflag bit meaning */ #define CBAUD 0010017 -#define B0 0000000 /* hang up */ -#define B50 0000001 -#define B75 0000002 -#define B110 0000003 -#define B134 0000004 -#define B150 0000005 -#define B200 0000006 -#define B300 0000007 -#define B600 0000010 -#define B1200 0000011 -#define B1800 0000012 -#define B2400 0000013 -#define B4800 0000014 -#define B9600 0000015 -#define B19200 0000016 -#define B38400 0000017 +#define B0 0000000 /* hang up */ +#define B50 0000001 +#define B75 0000002 +#define B110 0000003 +#define B134 0000004 +#define B150 0000005 +#define B200 0000006 +#define B300 0000007 +#define B600 0000010 +#define B1200 0000011 +#define B1800 0000012 +#define B2400 0000013 +#define B4800 0000014 +#define B9600 0000015 +#define B19200 0000016 +#define B38400 0000017 #define EXTA B19200 #define EXTB B38400 #define CSIZE 0000060 /* Number of bits per byte (mask). */ -#define CS5 0000000 /* 5 bits per byte. */ -#define CS6 0000020 /* 6 bits per byte. */ -#define CS7 0000040 /* 7 bits per byte. */ -#define CS8 0000060 /* 8 bits per byte. */ +#define CS5 0000000 /* 5 bits per byte. */ +#define CS6 0000020 /* 6 bits per byte. */ +#define CS7 0000040 /* 7 bits per byte. */ +#define CS8 0000060 /* 8 bits per byte. */ #define CSTOPB 0000100 /* Two stop bits instead of one. */ #define CREAD 0000200 /* Enable receiver. */ #define PARENB 0000400 /* Parity enable. */ -#define PARODD 0001000 /* Odd parity instead of even. */ +#define PARODD 0001000 /* Odd parity instead of even. */ #define HUPCL 0002000 /* Hang up on last close. */ #define CLOCAL 0004000 /* Ignore modem status lines. */ #define CBAUDEX 0010000 -#define BOTHER 0010000 -#define B57600 0010001 -#define B115200 0010002 -#define B230400 0010003 -#define B460800 0010004 -#define B500000 0010005 -#define B576000 0010006 -#define B921600 0010007 -#define B1000000 0010010 -#define B1152000 0010011 -#define B1500000 0010012 -#define B2000000 0010013 -#define B2500000 0010014 -#define B3000000 0010015 -#define B3500000 0010016 -#define B4000000 0010017 +#define BOTHER 0010000 +#define B57600 0010001 +#define B115200 0010002 +#define B230400 0010003 +#define B460800 0010004 +#define B500000 0010005 +#define B576000 0010006 +#define B921600 0010007 +#define B1000000 0010010 +#define B1152000 0010011 +#define B1500000 0010012 +#define B2000000 0010013 +#define B2500000 0010014 +#define B3000000 0010015 +#define B3500000 0010016 +#define B4000000 0010017 #define CIBAUD 002003600000 /* input baud rate */ -#define CMSPAR 010000000000 /* mark or space (stick) parity */ +#define CMSPAR 010000000000 /* mark or space (stick) parity */ #define CRTSCTS 020000000000 /* flow control */ -#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ +#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ /* c_lflag bits */ #define ISIG 0000001 /* Enable signals. */ #define ICANON 0000002 /* Do erase and kill processing. */ #define XCASE 0000004 -#define ECHO 0000010 /* Enable echo. */ +#define ECHO 0000010 /* Enable echo. */ #define ECHOE 0000020 /* Visual erase for ERASE. */ -#define ECHOK 0000040 /* Echo NL after KILL. */ -#define ECHONL 0000100 /* Echo NL even if ECHO is off. */ +#define ECHOK 0000040 /* Echo NL after KILL. */ +#define ECHONL 0000100 /* Echo NL even if ECHO is off. */ #define NOFLSH 0000200 /* Disable flush after interrupt. */ #define IEXTEN 0000400 /* Enable DISCARD and LNEXT. */ -#define ECHOCTL 0001000 /* Echo control characters as ^X. */ -#define ECHOPRT 0002000 /* Hardcopy visual erase. */ +#define ECHOCTL 0001000 /* Echo control characters as ^X. */ +#define ECHOPRT 0002000 /* Hardcopy visual erase. */ #define ECHOKE 0004000 /* Visual erase for KILL. */ #define FLUSHO 0020000 #define PENDIN 0040000 /* Retype pending input (state). */ -#define TOSTOP 0100000 /* Send SIGTTOU for background output. */ -#define ITOSTOP TOSTOP -#define EXTPROC 0200000 /* External processing on pty */ +#define TOSTOP 0100000 /* Send SIGTTOU for background output. */ +#define ITOSTOP TOSTOP +#define EXTPROC 0200000 /* External processing on pty */ /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ +#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ /* tcflow() and TCXONC use these */ -#define TCOOFF 0 /* Suspend output. */ -#define TCOON 1 /* Restart suspended output. */ -#define TCIOFF 2 /* Send a STOP character. */ -#define TCION 3 /* Send a START character. */ +#define TCOOFF 0 /* Suspend output. */ +#define TCOON 1 /* Restart suspended output. */ +#define TCIOFF 2 /* Send a STOP character. */ +#define TCION 3 /* Send a START character. */ /* tcflush() and TCFLSH use these */ -#define TCIFLUSH 0 /* Discard data received but not yet read. */ -#define TCOFLUSH 1 /* Discard data written but not yet sent. */ -#define TCIOFLUSH 2 /* Discard all pending data. */ +#define TCIFLUSH 0 /* Discard data received but not yet read. */ +#define TCOFLUSH 1 /* Discard data written but not yet sent. */ +#define TCIOFLUSH 2 /* Discard all pending data. */ /* tcsetattr uses these */ -#define TCSANOW TCSETS /* Change immediately. */ -#define TCSADRAIN TCSETSW /* Change when pending output is written. */ -#define TCSAFLUSH TCSETSF /* Flush pending input before changing. */ +#define TCSANOW TCSETS /* Change immediately. */ +#define TCSADRAIN TCSETSW /* Change when pending output is written. */ +#define TCSAFLUSH TCSETSF /* Flush pending input before changing. */ #endif /* _ASM_TERMBITS_H */ diff --git a/arch/mips/include/uapi/asm/termios.h b/arch/mips/include/uapi/asm/termios.h index 574fbdfb720..baeb2fa8745 100644 --- a/arch/mips/include/uapi/asm/termios.h +++ b/arch/mips/include/uapi/asm/termios.h @@ -31,12 +31,12 @@ struct tchars { }; struct ltchars { - char t_suspc; /* stop process signal */ - char t_dsuspc; /* delayed stop process signal */ - char t_rprntc; /* reprint line */ - char t_flushc; /* flush output (toggles) */ - char t_werasc; /* word erase */ - char t_lnextc; /* literal next character */ + char t_suspc; /* stop process signal */ + char t_dsuspc; /* delayed stop process signal */ + char t_rprntc; /* reprint line */ + char t_flushc; /* flush output (toggles) */ + char t_werasc; /* word erase */ + char t_lnextc; /* literal next character */ }; /* TIOCGSIZE, TIOCSSIZE not defined yet. Only needed for SunOS source diff --git a/arch/mips/include/uapi/asm/types.h b/arch/mips/include/uapi/asm/types.h index 7ac9d0baad8..f3dd9ff0cc0 100644 --- a/arch/mips/include/uapi/asm/types.h +++ b/arch/mips/include/uapi/asm/types.h @@ -14,9 +14,12 @@ /* * We don't use int-l64.h for the kernel anymore but still use it for * userspace to avoid code changes. + * + * However, some user programs (e.g. perf) may not want this. They can + * flag __SANE_USERSPACE_TYPES__ to get int-ll64.h here. */ #ifndef __KERNEL__ -# if _MIPS_SZLONG == 64 +# if _MIPS_SZLONG == 64 && !defined(__SANE_USERSPACE_TYPES__) # include <asm-generic/int-l64.h> # else # include <asm-generic/int-ll64.h> diff --git a/arch/mips/include/uapi/asm/unistd.h b/arch/mips/include/uapi/asm/unistd.h index 0eebf3c3e03..5805414777e 100644 --- a/arch/mips/include/uapi/asm/unistd.h +++ b/arch/mips/include/uapi/asm/unistd.h @@ -20,16 +20,16 @@ * Linux o32 style syscalls are in the range from 4000 to 4999. */ #define __NR_Linux 4000 -#define __NR_syscall (__NR_Linux + 0) -#define __NR_exit (__NR_Linux + 1) -#define __NR_fork (__NR_Linux + 2) -#define __NR_read (__NR_Linux + 3) -#define __NR_write (__NR_Linux + 4) -#define __NR_open (__NR_Linux + 5) -#define __NR_close (__NR_Linux + 6) -#define __NR_waitpid (__NR_Linux + 7) -#define __NR_creat (__NR_Linux + 8) -#define __NR_link (__NR_Linux + 9) +#define __NR_syscall (__NR_Linux + 0) +#define __NR_exit (__NR_Linux + 1) +#define __NR_fork (__NR_Linux + 2) +#define __NR_read (__NR_Linux + 3) +#define __NR_write (__NR_Linux + 4) +#define __NR_open (__NR_Linux + 5) +#define __NR_close (__NR_Linux + 6) +#define __NR_waitpid (__NR_Linux + 7) +#define __NR_creat (__NR_Linux + 8) +#define __NR_link (__NR_Linux + 9) #define __NR_unlink (__NR_Linux + 10) #define __NR_execve (__NR_Linux + 11) #define __NR_chdir (__NR_Linux + 12) @@ -369,16 +369,19 @@ #define __NR_process_vm_writev (__NR_Linux + 346) #define __NR_kcmp (__NR_Linux + 347) #define __NR_finit_module (__NR_Linux + 348) +#define __NR_sched_setattr (__NR_Linux + 349) +#define __NR_sched_getattr (__NR_Linux + 350) +#define __NR_renameat2 (__NR_Linux + 351) /* * Offset of the last Linux o32 flavoured syscall */ -#define __NR_Linux_syscalls 348 +#define __NR_Linux_syscalls 351 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ #define __NR_O32_Linux 4000 -#define __NR_O32_Linux_syscalls 348 +#define __NR_O32_Linux_syscalls 351 #if _MIPS_SIM == _MIPS_SIM_ABI64 @@ -386,16 +389,16 @@ * Linux 64-bit syscalls are in the range from 5000 to 5999. */ #define __NR_Linux 5000 -#define __NR_read (__NR_Linux + 0) -#define __NR_write (__NR_Linux + 1) -#define __NR_open (__NR_Linux + 2) -#define __NR_close (__NR_Linux + 3) -#define __NR_stat (__NR_Linux + 4) -#define __NR_fstat (__NR_Linux + 5) -#define __NR_lstat (__NR_Linux + 6) -#define __NR_poll (__NR_Linux + 7) -#define __NR_lseek (__NR_Linux + 8) -#define __NR_mmap (__NR_Linux + 9) +#define __NR_read (__NR_Linux + 0) +#define __NR_write (__NR_Linux + 1) +#define __NR_open (__NR_Linux + 2) +#define __NR_close (__NR_Linux + 3) +#define __NR_stat (__NR_Linux + 4) +#define __NR_fstat (__NR_Linux + 5) +#define __NR_lstat (__NR_Linux + 6) +#define __NR_poll (__NR_Linux + 7) +#define __NR_lseek (__NR_Linux + 8) +#define __NR_mmap (__NR_Linux + 9) #define __NR_mprotect (__NR_Linux + 10) #define __NR_munmap (__NR_Linux + 11) #define __NR_brk (__NR_Linux + 12) @@ -694,16 +697,20 @@ #define __NR_process_vm_writev (__NR_Linux + 305) #define __NR_kcmp (__NR_Linux + 306) #define __NR_finit_module (__NR_Linux + 307) +#define __NR_getdents64 (__NR_Linux + 308) +#define __NR_sched_setattr (__NR_Linux + 309) +#define __NR_sched_getattr (__NR_Linux + 310) +#define __NR_renameat2 (__NR_Linux + 311) /* * Offset of the last Linux 64-bit flavoured syscall */ -#define __NR_Linux_syscalls 307 +#define __NR_Linux_syscalls 311 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ #define __NR_64_Linux 5000 -#define __NR_64_Linux_syscalls 307 +#define __NR_64_Linux_syscalls 311 #if _MIPS_SIM == _MIPS_SIM_NABI32 @@ -711,16 +718,16 @@ * Linux N32 syscalls are in the range from 6000 to 6999. */ #define __NR_Linux 6000 -#define __NR_read (__NR_Linux + 0) -#define __NR_write (__NR_Linux + 1) -#define __NR_open (__NR_Linux + 2) -#define __NR_close (__NR_Linux + 3) -#define __NR_stat (__NR_Linux + 4) -#define __NR_fstat (__NR_Linux + 5) -#define __NR_lstat (__NR_Linux + 6) -#define __NR_poll (__NR_Linux + 7) -#define __NR_lseek (__NR_Linux + 8) -#define __NR_mmap (__NR_Linux + 9) +#define __NR_read (__NR_Linux + 0) +#define __NR_write (__NR_Linux + 1) +#define __NR_open (__NR_Linux + 2) +#define __NR_close (__NR_Linux + 3) +#define __NR_stat (__NR_Linux + 4) +#define __NR_fstat (__NR_Linux + 5) +#define __NR_lstat (__NR_Linux + 6) +#define __NR_poll (__NR_Linux + 7) +#define __NR_lseek (__NR_Linux + 8) +#define __NR_mmap (__NR_Linux + 9) #define __NR_mprotect (__NR_Linux + 10) #define __NR_munmap (__NR_Linux + 11) #define __NR_brk (__NR_Linux + 12) @@ -1024,15 +1031,18 @@ #define __NR_process_vm_writev (__NR_Linux + 310) #define __NR_kcmp (__NR_Linux + 311) #define __NR_finit_module (__NR_Linux + 312) +#define __NR_sched_setattr (__NR_Linux + 313) +#define __NR_sched_getattr (__NR_Linux + 314) +#define __NR_renameat2 (__NR_Linux + 315) /* * Offset of the last N32 flavoured syscall */ -#define __NR_Linux_syscalls 312 +#define __NR_Linux_syscalls 315 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ #define __NR_N32_Linux 6000 -#define __NR_N32_Linux_syscalls 312 +#define __NR_N32_Linux_syscalls 315 #endif /* _UAPI_ASM_UNISTD_H */ |