diff options
Diffstat (limited to 'arch/mips/include/asm/octeon')
71 files changed, 47628 insertions, 3422 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-address.h b/arch/mips/include/asm/octeon/cvmx-address.h index 3c74d826e2e..e2d874e681f 100644 --- a/arch/mips/include/asm/octeon/cvmx-address.h +++ b/arch/mips/include/asm/octeon/cvmx-address.h @@ -84,20 +84,20 @@ typedef enum { * Octeon-I HW never interprets this X (<39:36> reserved * for future expansion), software should set to 0. * - * - 0x0 XXX0 0000 0000 to DRAM Cached + * - 0x0 XXX0 0000 0000 to DRAM Cached * - 0x0 XXX0 0FFF FFFF * - * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000 - * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF) + * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000 + * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF) * - * - 0x0 XXX0 2000 0000 to DRAM Cached + * - 0x0 XXX0 2000 0000 to DRAM Cached * - 0x0 XXXF FFFF FFFF * - * - 0x1 00X0 0000 0000 to Boot Bus Uncached + * - 0x1 00X0 0000 0000 to Boot Bus Uncached * - 0x1 00XF FFFF FFFF * - * - 0x1 01X0 0000 0000 to Other NCB Uncached - * - 0x1 FFXF FFFF FFFF devices + * - 0x1 01X0 0000 0000 to Other NCB Uncached + * - 0x1 FFXF FFFF FFFF devices * * Decode of all Octeon addresses */ @@ -129,9 +129,9 @@ typedef union { */ struct { uint64_t R:2; /* CVMX_MIPS_SPACE_XKPHYS in this case */ - uint64_t cca:3; /* ignored by octeon */ + uint64_t cca:3; /* ignored by octeon */ uint64_t mbz:10; - uint64_t pa:49; /* physical address */ + uint64_t pa:49; /* physical address */ } sxkphys; /* physical address */ @@ -253,22 +253,22 @@ typedef union { #define CVMX_OCT_DID_ASX1 23ULL #define CVMX_OCT_DID_IOB 30ULL -#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL) -#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL) -#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL) -#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL) -#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL) +#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL) +#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL) +#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL) +#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL) +#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL) #define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL) -#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL) -#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL) -#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL) -#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL) -#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL) -#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL) -#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL) -#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL) -#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL) -#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL) -#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL) +#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL) +#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL) +#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL) +#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL) +#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL) +#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL) +#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL) +#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL) +#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL) +#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL) +#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL) #endif /* __CVMX_ADDRESS_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/arch/mips/include/asm/octeon/cvmx-agl-defs.h index 30d68f2365e..542ee09510b 100644 --- a/arch/mips/include/asm/octeon/cvmx-agl-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -106,6 +106,7 @@ union cvmx_agl_gmx_bad_reg { uint64_t u64; struct cvmx_agl_gmx_bad_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t txpsh1:1; uint64_t txpop1:1; @@ -120,8 +121,25 @@ union cvmx_agl_gmx_bad_reg { uint64_t reserved_4_21:18; uint64_t out_ovr:2; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t out_ovr:2; + uint64_t reserved_4_21:18; + uint64_t loststat:2; + uint64_t reserved_24_25:2; + uint64_t statovr:1; + uint64_t reserved_27_31:5; + uint64_t ovrflw:1; + uint64_t txpop:1; + uint64_t txpsh:1; + uint64_t ovrflw1:1; + uint64_t txpop1:1; + uint64_t txpsh1:1; + uint64_t reserved_38_63:26; +#endif } s; struct cvmx_agl_gmx_bad_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t txpsh1:1; uint64_t txpop1:1; @@ -136,9 +154,26 @@ union cvmx_agl_gmx_bad_reg { uint64_t reserved_4_21:18; uint64_t out_ovr:2; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t out_ovr:2; + uint64_t reserved_4_21:18; + uint64_t loststat:1; + uint64_t reserved_23_25:3; + uint64_t statovr:1; + uint64_t reserved_27_31:5; + uint64_t ovrflw:1; + uint64_t txpop:1; + uint64_t txpsh:1; + uint64_t ovrflw1:1; + uint64_t txpop1:1; + uint64_t txpsh1:1; + uint64_t reserved_38_63:26; +#endif } cn52xx; struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1; struct cvmx_agl_gmx_bad_reg_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t txpsh:1; uint64_t txpop:1; @@ -150,32 +185,64 @@ union cvmx_agl_gmx_bad_reg { uint64_t reserved_3_21:19; uint64_t out_ovr:1; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t out_ovr:1; + uint64_t reserved_3_21:19; + uint64_t loststat:1; + uint64_t reserved_23_25:3; + uint64_t statovr:1; + uint64_t reserved_27_31:5; + uint64_t ovrflw:1; + uint64_t txpop:1; + uint64_t txpsh:1; + uint64_t reserved_35_63:29; +#endif } cn56xx; struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1; + struct cvmx_agl_gmx_bad_reg_s cn61xx; struct cvmx_agl_gmx_bad_reg_s cn63xx; struct cvmx_agl_gmx_bad_reg_s cn63xxp1; + struct cvmx_agl_gmx_bad_reg_s cn66xx; + struct cvmx_agl_gmx_bad_reg_s cn68xx; + struct cvmx_agl_gmx_bad_reg_s cn68xxp1; }; union cvmx_agl_gmx_bist { uint64_t u64; struct cvmx_agl_gmx_bist_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t status:25; +#else + uint64_t status:25; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_agl_gmx_bist_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t status:10; +#else + uint64_t status:10; + uint64_t reserved_10_63:54; +#endif } cn52xx; struct cvmx_agl_gmx_bist_cn52xx cn52xxp1; struct cvmx_agl_gmx_bist_cn52xx cn56xx; struct cvmx_agl_gmx_bist_cn52xx cn56xxp1; + struct cvmx_agl_gmx_bist_s cn61xx; struct cvmx_agl_gmx_bist_s cn63xx; struct cvmx_agl_gmx_bist_s cn63xxp1; + struct cvmx_agl_gmx_bist_s cn66xx; + struct cvmx_agl_gmx_bist_s cn68xx; + struct cvmx_agl_gmx_bist_s cn68xxp1; }; union cvmx_agl_gmx_drv_ctl { uint64_t u64; struct cvmx_agl_gmx_drv_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t byp_en1:1; uint64_t reserved_45_47:3; @@ -188,16 +255,39 @@ union cvmx_agl_gmx_drv_ctl { uint64_t pctl:5; uint64_t reserved_5_7:3; uint64_t nctl:5; +#else + uint64_t nctl:5; + uint64_t reserved_5_7:3; + uint64_t pctl:5; + uint64_t reserved_13_15:3; + uint64_t byp_en:1; + uint64_t reserved_17_31:15; + uint64_t nctl1:5; + uint64_t reserved_37_39:3; + uint64_t pctl1:5; + uint64_t reserved_45_47:3; + uint64_t byp_en1:1; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_agl_gmx_drv_ctl_s cn52xx; struct cvmx_agl_gmx_drv_ctl_s cn52xxp1; struct cvmx_agl_gmx_drv_ctl_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t byp_en:1; uint64_t reserved_13_15:3; uint64_t pctl:5; uint64_t reserved_5_7:3; uint64_t nctl:5; +#else + uint64_t nctl:5; + uint64_t reserved_5_7:3; + uint64_t pctl:5; + uint64_t reserved_13_15:3; + uint64_t byp_en:1; + uint64_t reserved_17_63:47; +#endif } cn56xx; struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1; }; @@ -205,9 +295,15 @@ union cvmx_agl_gmx_drv_ctl { union cvmx_agl_gmx_inf_mode { uint64_t u64; struct cvmx_agl_gmx_inf_mode_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t en:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t en:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_agl_gmx_inf_mode_s cn52xx; struct cvmx_agl_gmx_inf_mode_s cn52xxp1; @@ -218,6 +314,7 @@ union cvmx_agl_gmx_inf_mode { union cvmx_agl_gmx_prtx_cfg { uint64_t u64; struct cvmx_agl_gmx_prtx_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t tx_idle:1; uint64_t rx_idle:1; @@ -231,8 +328,24 @@ union cvmx_agl_gmx_prtx_cfg { uint64_t duplex:1; uint64_t speed:1; uint64_t en:1; +#else + uint64_t en:1; + uint64_t speed:1; + uint64_t duplex:1; + uint64_t slottime:1; + uint64_t rx_en:1; + uint64_t tx_en:1; + uint64_t burst:1; + uint64_t reserved_7_7:1; + uint64_t speed_msb:1; + uint64_t reserved_9_11:3; + uint64_t rx_idle:1; + uint64_t tx_idle:1; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_agl_gmx_prtx_cfg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t tx_en:1; uint64_t rx_en:1; @@ -240,139 +353,230 @@ union cvmx_agl_gmx_prtx_cfg { uint64_t duplex:1; uint64_t speed:1; uint64_t en:1; +#else + uint64_t en:1; + uint64_t speed:1; + uint64_t duplex:1; + uint64_t slottime:1; + uint64_t rx_en:1; + uint64_t tx_en:1; + uint64_t reserved_6_63:58; +#endif } cn52xx; struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1; struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx; struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1; + struct cvmx_agl_gmx_prtx_cfg_s cn61xx; struct cvmx_agl_gmx_prtx_cfg_s cn63xx; struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1; + struct cvmx_agl_gmx_prtx_cfg_s cn66xx; + struct cvmx_agl_gmx_prtx_cfg_s cn68xx; + struct cvmx_agl_gmx_prtx_cfg_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam0 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; +#else + uint64_t adr:64; +#endif } s; struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1; + struct cvmx_agl_gmx_rxx_adr_cam0_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1; + struct cvmx_agl_gmx_rxx_adr_cam0_s cn66xx; + struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xx; + struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam1 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; +#else + uint64_t adr:64; +#endif } s; struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1; + struct cvmx_agl_gmx_rxx_adr_cam1_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1; + struct cvmx_agl_gmx_rxx_adr_cam1_s cn66xx; + struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xx; + struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam2 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; +#else + uint64_t adr:64; +#endif } s; struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1; + struct cvmx_agl_gmx_rxx_adr_cam2_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1; + struct cvmx_agl_gmx_rxx_adr_cam2_s cn66xx; + struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xx; + struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam3 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; +#else + uint64_t adr:64; +#endif } s; struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1; + struct cvmx_agl_gmx_rxx_adr_cam3_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1; + struct cvmx_agl_gmx_rxx_adr_cam3_s cn66xx; + struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xx; + struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam4 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam4_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; +#else + uint64_t adr:64; +#endif } s; struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1; + struct cvmx_agl_gmx_rxx_adr_cam4_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1; + struct cvmx_agl_gmx_rxx_adr_cam4_s cn66xx; + struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xx; + struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam5 { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam5_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t adr:64; +#else uint64_t adr:64; +#endif } s; struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1; + struct cvmx_agl_gmx_rxx_adr_cam5_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1; + struct cvmx_agl_gmx_rxx_adr_cam5_s cn66xx; + struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xx; + struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_cam_en { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_cam_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t en:8; +#else + uint64_t en:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1; + struct cvmx_agl_gmx_rxx_adr_cam_en_s cn61xx; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx; struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1; + struct cvmx_agl_gmx_rxx_adr_cam_en_s cn66xx; + struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xx; + struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xxp1; }; union cvmx_agl_gmx_rxx_adr_ctl { uint64_t u64; struct cvmx_agl_gmx_rxx_adr_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t cam_mode:1; uint64_t mcst:2; uint64_t bcst:1; +#else + uint64_t bcst:1; + uint64_t mcst:2; + uint64_t cam_mode:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx; struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1; struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx; struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1; + struct cvmx_agl_gmx_rxx_adr_ctl_s cn61xx; struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx; struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1; + struct cvmx_agl_gmx_rxx_adr_ctl_s cn66xx; + struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xx; + struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xxp1; }; union cvmx_agl_gmx_rxx_decision { uint64_t u64; struct cvmx_agl_gmx_rxx_decision_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t cnt:5; +#else + uint64_t cnt:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_agl_gmx_rxx_decision_s cn52xx; struct cvmx_agl_gmx_rxx_decision_s cn52xxp1; struct cvmx_agl_gmx_rxx_decision_s cn56xx; struct cvmx_agl_gmx_rxx_decision_s cn56xxp1; + struct cvmx_agl_gmx_rxx_decision_s cn61xx; struct cvmx_agl_gmx_rxx_decision_s cn63xx; struct cvmx_agl_gmx_rxx_decision_s cn63xxp1; + struct cvmx_agl_gmx_rxx_decision_s cn66xx; + struct cvmx_agl_gmx_rxx_decision_s cn68xx; + struct cvmx_agl_gmx_rxx_decision_s cn68xxp1; }; union cvmx_agl_gmx_rxx_frm_chk { uint64_t u64; struct cvmx_agl_gmx_rxx_frm_chk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t niberr:1; uint64_t skperr:1; @@ -384,8 +588,22 @@ union cvmx_agl_gmx_rxx_frm_chk { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_agl_gmx_rxx_frm_chk_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t skperr:1; uint64_t rcverr:1; @@ -396,17 +614,34 @@ union cvmx_agl_gmx_rxx_frm_chk { uint64_t maxerr:1; uint64_t reserved_1_1:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t reserved_1_1:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_63:55; +#endif } cn52xx; struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1; struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx; struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1; + struct cvmx_agl_gmx_rxx_frm_chk_s cn61xx; struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx; struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1; + struct cvmx_agl_gmx_rxx_frm_chk_s cn66xx; + struct cvmx_agl_gmx_rxx_frm_chk_s cn68xx; + struct cvmx_agl_gmx_rxx_frm_chk_s cn68xxp1; }; union cvmx_agl_gmx_rxx_frm_ctl { uint64_t u64; struct cvmx_agl_gmx_rxx_frm_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t ptp_mode:1; uint64_t reserved_11_11:1; @@ -421,8 +656,25 @@ union cvmx_agl_gmx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t pre_align:1; + uint64_t null_dis:1; + uint64_t reserved_11_11:1; + uint64_t ptp_mode:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pre_align:1; uint64_t pad_len:1; @@ -434,59 +686,104 @@ union cvmx_agl_gmx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t pre_align:1; + uint64_t reserved_10_63:54; +#endif } cn52xx; struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1; struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx; struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1; + struct cvmx_agl_gmx_rxx_frm_ctl_s cn61xx; struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx; struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1; + struct cvmx_agl_gmx_rxx_frm_ctl_s cn66xx; + struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xx; + struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xxp1; }; union cvmx_agl_gmx_rxx_frm_max { uint64_t u64; struct cvmx_agl_gmx_rxx_frm_max_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t len:16; +#else + uint64_t len:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_rxx_frm_max_s cn52xx; struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1; struct cvmx_agl_gmx_rxx_frm_max_s cn56xx; struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1; + struct cvmx_agl_gmx_rxx_frm_max_s cn61xx; struct cvmx_agl_gmx_rxx_frm_max_s cn63xx; struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1; + struct cvmx_agl_gmx_rxx_frm_max_s cn66xx; + struct cvmx_agl_gmx_rxx_frm_max_s cn68xx; + struct cvmx_agl_gmx_rxx_frm_max_s cn68xxp1; }; union cvmx_agl_gmx_rxx_frm_min { uint64_t u64; struct cvmx_agl_gmx_rxx_frm_min_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t len:16; +#else + uint64_t len:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_rxx_frm_min_s cn52xx; struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1; struct cvmx_agl_gmx_rxx_frm_min_s cn56xx; struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1; + struct cvmx_agl_gmx_rxx_frm_min_s cn61xx; struct cvmx_agl_gmx_rxx_frm_min_s cn63xx; struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1; + struct cvmx_agl_gmx_rxx_frm_min_s cn66xx; + struct cvmx_agl_gmx_rxx_frm_min_s cn68xx; + struct cvmx_agl_gmx_rxx_frm_min_s cn68xxp1; }; union cvmx_agl_gmx_rxx_ifg { uint64_t u64; struct cvmx_agl_gmx_rxx_ifg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t ifg:4; +#else + uint64_t ifg:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_agl_gmx_rxx_ifg_s cn52xx; struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1; struct cvmx_agl_gmx_rxx_ifg_s cn56xx; struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1; + struct cvmx_agl_gmx_rxx_ifg_s cn61xx; struct cvmx_agl_gmx_rxx_ifg_s cn63xx; struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1; + struct cvmx_agl_gmx_rxx_ifg_s cn66xx; + struct cvmx_agl_gmx_rxx_ifg_s cn68xx; + struct cvmx_agl_gmx_rxx_ifg_s cn68xxp1; }; union cvmx_agl_gmx_rxx_int_en { uint64_t u64; struct cvmx_agl_gmx_rxx_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -508,8 +805,32 @@ union cvmx_agl_gmx_rxx_int_en { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t pause_drp:1; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_agl_gmx_rxx_int_en_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t reserved_16_18:3; @@ -529,17 +850,43 @@ union cvmx_agl_gmx_rxx_int_en { uint64_t maxerr:1; uint64_t reserved_1_1:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t reserved_1_1:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_9:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t reserved_16_18:3; + uint64_t pause_drp:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1; struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx; struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1; + struct cvmx_agl_gmx_rxx_int_en_s cn61xx; struct cvmx_agl_gmx_rxx_int_en_s cn63xx; struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1; + struct cvmx_agl_gmx_rxx_int_en_s cn66xx; + struct cvmx_agl_gmx_rxx_int_en_s cn68xx; + struct cvmx_agl_gmx_rxx_int_en_s cn68xxp1; }; union cvmx_agl_gmx_rxx_int_reg { uint64_t u64; struct cvmx_agl_gmx_rxx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -561,8 +908,32 @@ union cvmx_agl_gmx_rxx_int_reg { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t pause_drp:1; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_agl_gmx_rxx_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t reserved_16_18:3; @@ -582,666 +953,1130 @@ union cvmx_agl_gmx_rxx_int_reg { uint64_t maxerr:1; uint64_t reserved_1_1:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t reserved_1_1:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_9:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t reserved_16_18:3; + uint64_t pause_drp:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1; struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx; struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1; + struct cvmx_agl_gmx_rxx_int_reg_s cn61xx; struct cvmx_agl_gmx_rxx_int_reg_s cn63xx; struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1; + struct cvmx_agl_gmx_rxx_int_reg_s cn66xx; + struct cvmx_agl_gmx_rxx_int_reg_s cn68xx; + struct cvmx_agl_gmx_rxx_int_reg_s cn68xxp1; }; union cvmx_agl_gmx_rxx_jabber { uint64_t u64; struct cvmx_agl_gmx_rxx_jabber_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt:16; +#else + uint64_t cnt:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_rxx_jabber_s cn52xx; struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1; struct cvmx_agl_gmx_rxx_jabber_s cn56xx; struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1; + struct cvmx_agl_gmx_rxx_jabber_s cn61xx; struct cvmx_agl_gmx_rxx_jabber_s cn63xx; struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1; + struct cvmx_agl_gmx_rxx_jabber_s cn66xx; + struct cvmx_agl_gmx_rxx_jabber_s cn68xx; + struct cvmx_agl_gmx_rxx_jabber_s cn68xxp1; }; union cvmx_agl_gmx_rxx_pause_drop_time { uint64_t u64; struct cvmx_agl_gmx_rxx_pause_drop_time_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t status:16; +#else + uint64_t status:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1; + struct cvmx_agl_gmx_rxx_pause_drop_time_s cn61xx; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx; struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1; + struct cvmx_agl_gmx_rxx_pause_drop_time_s cn66xx; + struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xx; + struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xxp1; }; union cvmx_agl_gmx_rxx_rx_inbnd { uint64_t u64; struct cvmx_agl_gmx_rxx_rx_inbnd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t duplex:1; uint64_t speed:2; uint64_t status:1; +#else + uint64_t status:1; + uint64_t speed:2; + uint64_t duplex:1; + uint64_t reserved_4_63:60; +#endif } s; + struct cvmx_agl_gmx_rxx_rx_inbnd_s cn61xx; struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx; struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1; + struct cvmx_agl_gmx_rxx_rx_inbnd_s cn66xx; + struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xx; + struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_ctl { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rd_clr:1; +#else + uint64_t rd_clr:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx; struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx; struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_ctl_s cn61xx; struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx; struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_ctl_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_octs { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_octs_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; +#else + uint64_t cnt:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx; struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx; struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_s cn61xx; struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx; struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_octs_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_octs_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_octs_ctl { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; +#else + uint64_t cnt:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn61xx; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx; struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_octs_dmac { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; +#else + uint64_t cnt:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn61xx; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx; struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_octs_drp { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_octs_drp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; +#else + uint64_t cnt:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn61xx; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx; struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_pkts { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_pkts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx; struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx; struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_s cn61xx; struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx; struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_pkts_bad { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn61xx; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx; struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_pkts_ctl { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn61xx; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx; struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_pkts_dmac { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn61xx; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx; struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xxp1; }; union cvmx_agl_gmx_rxx_stats_pkts_drp { uint64_t u64; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn61xx; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx; struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn66xx; + struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xx; + struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xxp1; }; union cvmx_agl_gmx_rxx_udd_skp { uint64_t u64; struct cvmx_agl_gmx_rxx_udd_skp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t fcssel:1; uint64_t reserved_7_7:1; uint64_t len:7; +#else + uint64_t len:7; + uint64_t reserved_7_7:1; + uint64_t fcssel:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx; struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1; struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx; struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1; + struct cvmx_agl_gmx_rxx_udd_skp_s cn61xx; struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx; struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1; + struct cvmx_agl_gmx_rxx_udd_skp_s cn66xx; + struct cvmx_agl_gmx_rxx_udd_skp_s cn68xx; + struct cvmx_agl_gmx_rxx_udd_skp_s cn68xxp1; }; union cvmx_agl_gmx_rx_bp_dropx { uint64_t u64; struct cvmx_agl_gmx_rx_bp_dropx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mark:6; +#else + uint64_t mark:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx; struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1; struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx; struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1; + struct cvmx_agl_gmx_rx_bp_dropx_s cn61xx; struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx; struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1; + struct cvmx_agl_gmx_rx_bp_dropx_s cn66xx; + struct cvmx_agl_gmx_rx_bp_dropx_s cn68xx; + struct cvmx_agl_gmx_rx_bp_dropx_s cn68xxp1; }; union cvmx_agl_gmx_rx_bp_offx { uint64_t u64; struct cvmx_agl_gmx_rx_bp_offx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mark:6; +#else + uint64_t mark:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_agl_gmx_rx_bp_offx_s cn52xx; struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1; struct cvmx_agl_gmx_rx_bp_offx_s cn56xx; struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1; + struct cvmx_agl_gmx_rx_bp_offx_s cn61xx; struct cvmx_agl_gmx_rx_bp_offx_s cn63xx; struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1; + struct cvmx_agl_gmx_rx_bp_offx_s cn66xx; + struct cvmx_agl_gmx_rx_bp_offx_s cn68xx; + struct cvmx_agl_gmx_rx_bp_offx_s cn68xxp1; }; union cvmx_agl_gmx_rx_bp_onx { uint64_t u64; struct cvmx_agl_gmx_rx_bp_onx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t mark:9; +#else + uint64_t mark:9; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_agl_gmx_rx_bp_onx_s cn52xx; struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1; struct cvmx_agl_gmx_rx_bp_onx_s cn56xx; struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1; + struct cvmx_agl_gmx_rx_bp_onx_s cn61xx; struct cvmx_agl_gmx_rx_bp_onx_s cn63xx; struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1; + struct cvmx_agl_gmx_rx_bp_onx_s cn66xx; + struct cvmx_agl_gmx_rx_bp_onx_s cn68xx; + struct cvmx_agl_gmx_rx_bp_onx_s cn68xxp1; }; union cvmx_agl_gmx_rx_prt_info { uint64_t u64; struct cvmx_agl_gmx_rx_prt_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t drop:2; uint64_t reserved_2_15:14; uint64_t commit:2; +#else + uint64_t commit:2; + uint64_t reserved_2_15:14; + uint64_t drop:2; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_agl_gmx_rx_prt_info_s cn52xx; struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1; struct cvmx_agl_gmx_rx_prt_info_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t drop:1; uint64_t reserved_1_15:15; uint64_t commit:1; +#else + uint64_t commit:1; + uint64_t reserved_1_15:15; + uint64_t drop:1; + uint64_t reserved_17_63:47; +#endif } cn56xx; struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1; + struct cvmx_agl_gmx_rx_prt_info_s cn61xx; struct cvmx_agl_gmx_rx_prt_info_s cn63xx; struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1; + struct cvmx_agl_gmx_rx_prt_info_s cn66xx; + struct cvmx_agl_gmx_rx_prt_info_s cn68xx; + struct cvmx_agl_gmx_rx_prt_info_s cn68xxp1; }; union cvmx_agl_gmx_rx_tx_status { uint64_t u64; struct cvmx_agl_gmx_rx_tx_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t tx:2; uint64_t reserved_2_3:2; uint64_t rx:2; +#else + uint64_t rx:2; + uint64_t reserved_2_3:2; + uint64_t tx:2; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_agl_gmx_rx_tx_status_s cn52xx; struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1; struct cvmx_agl_gmx_rx_tx_status_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t tx:1; uint64_t reserved_1_3:3; uint64_t rx:1; +#else + uint64_t rx:1; + uint64_t reserved_1_3:3; + uint64_t tx:1; + uint64_t reserved_5_63:59; +#endif } cn56xx; struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1; + struct cvmx_agl_gmx_rx_tx_status_s cn61xx; struct cvmx_agl_gmx_rx_tx_status_s cn63xx; struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1; + struct cvmx_agl_gmx_rx_tx_status_s cn66xx; + struct cvmx_agl_gmx_rx_tx_status_s cn68xx; + struct cvmx_agl_gmx_rx_tx_status_s cn68xxp1; }; union cvmx_agl_gmx_smacx { uint64_t u64; struct cvmx_agl_gmx_smacx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t smac:48; +#else + uint64_t smac:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_agl_gmx_smacx_s cn52xx; struct cvmx_agl_gmx_smacx_s cn52xxp1; struct cvmx_agl_gmx_smacx_s cn56xx; struct cvmx_agl_gmx_smacx_s cn56xxp1; + struct cvmx_agl_gmx_smacx_s cn61xx; struct cvmx_agl_gmx_smacx_s cn63xx; struct cvmx_agl_gmx_smacx_s cn63xxp1; + struct cvmx_agl_gmx_smacx_s cn66xx; + struct cvmx_agl_gmx_smacx_s cn68xx; + struct cvmx_agl_gmx_smacx_s cn68xxp1; }; union cvmx_agl_gmx_stat_bp { uint64_t u64; struct cvmx_agl_gmx_stat_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t bp:1; uint64_t cnt:16; +#else + uint64_t cnt:16; + uint64_t bp:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_agl_gmx_stat_bp_s cn52xx; struct cvmx_agl_gmx_stat_bp_s cn52xxp1; struct cvmx_agl_gmx_stat_bp_s cn56xx; struct cvmx_agl_gmx_stat_bp_s cn56xxp1; + struct cvmx_agl_gmx_stat_bp_s cn61xx; struct cvmx_agl_gmx_stat_bp_s cn63xx; struct cvmx_agl_gmx_stat_bp_s cn63xxp1; + struct cvmx_agl_gmx_stat_bp_s cn66xx; + struct cvmx_agl_gmx_stat_bp_s cn68xx; + struct cvmx_agl_gmx_stat_bp_s cn68xxp1; }; union cvmx_agl_gmx_txx_append { uint64_t u64; struct cvmx_agl_gmx_txx_append_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t force_fcs:1; uint64_t fcs:1; uint64_t pad:1; uint64_t preamble:1; +#else + uint64_t preamble:1; + uint64_t pad:1; + uint64_t fcs:1; + uint64_t force_fcs:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_agl_gmx_txx_append_s cn52xx; struct cvmx_agl_gmx_txx_append_s cn52xxp1; struct cvmx_agl_gmx_txx_append_s cn56xx; struct cvmx_agl_gmx_txx_append_s cn56xxp1; + struct cvmx_agl_gmx_txx_append_s cn61xx; struct cvmx_agl_gmx_txx_append_s cn63xx; struct cvmx_agl_gmx_txx_append_s cn63xxp1; + struct cvmx_agl_gmx_txx_append_s cn66xx; + struct cvmx_agl_gmx_txx_append_s cn68xx; + struct cvmx_agl_gmx_txx_append_s cn68xxp1; }; union cvmx_agl_gmx_txx_clk { uint64_t u64; struct cvmx_agl_gmx_txx_clk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t clk_cnt:6; +#else + uint64_t clk_cnt:6; + uint64_t reserved_6_63:58; +#endif } s; + struct cvmx_agl_gmx_txx_clk_s cn61xx; struct cvmx_agl_gmx_txx_clk_s cn63xx; struct cvmx_agl_gmx_txx_clk_s cn63xxp1; + struct cvmx_agl_gmx_txx_clk_s cn66xx; + struct cvmx_agl_gmx_txx_clk_s cn68xx; + struct cvmx_agl_gmx_txx_clk_s cn68xxp1; }; union cvmx_agl_gmx_txx_ctl { uint64_t u64; struct cvmx_agl_gmx_txx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t xsdef_en:1; uint64_t xscol_en:1; +#else + uint64_t xscol_en:1; + uint64_t xsdef_en:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_agl_gmx_txx_ctl_s cn52xx; struct cvmx_agl_gmx_txx_ctl_s cn52xxp1; struct cvmx_agl_gmx_txx_ctl_s cn56xx; struct cvmx_agl_gmx_txx_ctl_s cn56xxp1; + struct cvmx_agl_gmx_txx_ctl_s cn61xx; struct cvmx_agl_gmx_txx_ctl_s cn63xx; struct cvmx_agl_gmx_txx_ctl_s cn63xxp1; + struct cvmx_agl_gmx_txx_ctl_s cn66xx; + struct cvmx_agl_gmx_txx_ctl_s cn68xx; + struct cvmx_agl_gmx_txx_ctl_s cn68xxp1; }; union cvmx_agl_gmx_txx_min_pkt { uint64_t u64; struct cvmx_agl_gmx_txx_min_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t min_size:8; +#else + uint64_t min_size:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_agl_gmx_txx_min_pkt_s cn52xx; struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1; struct cvmx_agl_gmx_txx_min_pkt_s cn56xx; struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1; + struct cvmx_agl_gmx_txx_min_pkt_s cn61xx; struct cvmx_agl_gmx_txx_min_pkt_s cn63xx; struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1; + struct cvmx_agl_gmx_txx_min_pkt_s cn66xx; + struct cvmx_agl_gmx_txx_min_pkt_s cn68xx; + struct cvmx_agl_gmx_txx_min_pkt_s cn68xxp1; }; union cvmx_agl_gmx_txx_pause_pkt_interval { uint64_t u64; struct cvmx_agl_gmx_txx_pause_pkt_interval_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t interval:16; +#else + uint64_t interval:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1; + struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn61xx; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx; struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1; + struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn66xx; + struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xx; + struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xxp1; }; union cvmx_agl_gmx_txx_pause_pkt_time { uint64_t u64; struct cvmx_agl_gmx_txx_pause_pkt_time_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; +#else + uint64_t time:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1; + struct cvmx_agl_gmx_txx_pause_pkt_time_s cn61xx; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx; struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1; + struct cvmx_agl_gmx_txx_pause_pkt_time_s cn66xx; + struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xx; + struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xxp1; }; union cvmx_agl_gmx_txx_pause_togo { uint64_t u64; struct cvmx_agl_gmx_txx_pause_togo_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; +#else + uint64_t time:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_txx_pause_togo_s cn52xx; struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1; struct cvmx_agl_gmx_txx_pause_togo_s cn56xx; struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1; + struct cvmx_agl_gmx_txx_pause_togo_s cn61xx; struct cvmx_agl_gmx_txx_pause_togo_s cn63xx; struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1; + struct cvmx_agl_gmx_txx_pause_togo_s cn66xx; + struct cvmx_agl_gmx_txx_pause_togo_s cn68xx; + struct cvmx_agl_gmx_txx_pause_togo_s cn68xxp1; }; union cvmx_agl_gmx_txx_pause_zero { uint64_t u64; struct cvmx_agl_gmx_txx_pause_zero_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t send:1; +#else + uint64_t send:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_agl_gmx_txx_pause_zero_s cn52xx; struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1; struct cvmx_agl_gmx_txx_pause_zero_s cn56xx; struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1; + struct cvmx_agl_gmx_txx_pause_zero_s cn61xx; struct cvmx_agl_gmx_txx_pause_zero_s cn63xx; struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1; + struct cvmx_agl_gmx_txx_pause_zero_s cn66xx; + struct cvmx_agl_gmx_txx_pause_zero_s cn68xx; + struct cvmx_agl_gmx_txx_pause_zero_s cn68xxp1; }; union cvmx_agl_gmx_txx_soft_pause { uint64_t u64; struct cvmx_agl_gmx_txx_soft_pause_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; +#else + uint64_t time:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_txx_soft_pause_s cn52xx; struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1; struct cvmx_agl_gmx_txx_soft_pause_s cn56xx; struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1; + struct cvmx_agl_gmx_txx_soft_pause_s cn61xx; struct cvmx_agl_gmx_txx_soft_pause_s cn63xx; struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1; + struct cvmx_agl_gmx_txx_soft_pause_s cn66xx; + struct cvmx_agl_gmx_txx_soft_pause_s cn68xx; + struct cvmx_agl_gmx_txx_soft_pause_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat0 { uint64_t u64; struct cvmx_agl_gmx_txx_stat0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t xsdef:32; uint64_t xscol:32; +#else + uint64_t xscol:32; + uint64_t xsdef:32; +#endif } s; struct cvmx_agl_gmx_txx_stat0_s cn52xx; struct cvmx_agl_gmx_txx_stat0_s cn52xxp1; struct cvmx_agl_gmx_txx_stat0_s cn56xx; struct cvmx_agl_gmx_txx_stat0_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat0_s cn61xx; struct cvmx_agl_gmx_txx_stat0_s cn63xx; struct cvmx_agl_gmx_txx_stat0_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat0_s cn66xx; + struct cvmx_agl_gmx_txx_stat0_s cn68xx; + struct cvmx_agl_gmx_txx_stat0_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat1 { uint64_t u64; struct cvmx_agl_gmx_txx_stat1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t scol:32; uint64_t mcol:32; +#else + uint64_t mcol:32; + uint64_t scol:32; +#endif } s; struct cvmx_agl_gmx_txx_stat1_s cn52xx; struct cvmx_agl_gmx_txx_stat1_s cn52xxp1; struct cvmx_agl_gmx_txx_stat1_s cn56xx; struct cvmx_agl_gmx_txx_stat1_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat1_s cn61xx; struct cvmx_agl_gmx_txx_stat1_s cn63xx; struct cvmx_agl_gmx_txx_stat1_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat1_s cn66xx; + struct cvmx_agl_gmx_txx_stat1_s cn68xx; + struct cvmx_agl_gmx_txx_stat1_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat2 { uint64_t u64; struct cvmx_agl_gmx_txx_stat2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t octs:48; +#else + uint64_t octs:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_agl_gmx_txx_stat2_s cn52xx; struct cvmx_agl_gmx_txx_stat2_s cn52xxp1; struct cvmx_agl_gmx_txx_stat2_s cn56xx; struct cvmx_agl_gmx_txx_stat2_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat2_s cn61xx; struct cvmx_agl_gmx_txx_stat2_s cn63xx; struct cvmx_agl_gmx_txx_stat2_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat2_s cn66xx; + struct cvmx_agl_gmx_txx_stat2_s cn68xx; + struct cvmx_agl_gmx_txx_stat2_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat3 { uint64_t u64; struct cvmx_agl_gmx_txx_stat3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pkts:32; +#else + uint64_t pkts:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_agl_gmx_txx_stat3_s cn52xx; struct cvmx_agl_gmx_txx_stat3_s cn52xxp1; struct cvmx_agl_gmx_txx_stat3_s cn56xx; struct cvmx_agl_gmx_txx_stat3_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat3_s cn61xx; struct cvmx_agl_gmx_txx_stat3_s cn63xx; struct cvmx_agl_gmx_txx_stat3_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat3_s cn66xx; + struct cvmx_agl_gmx_txx_stat3_s cn68xx; + struct cvmx_agl_gmx_txx_stat3_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat4 { uint64_t u64; struct cvmx_agl_gmx_txx_stat4_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist1:32; uint64_t hist0:32; +#else + uint64_t hist0:32; + uint64_t hist1:32; +#endif } s; struct cvmx_agl_gmx_txx_stat4_s cn52xx; struct cvmx_agl_gmx_txx_stat4_s cn52xxp1; struct cvmx_agl_gmx_txx_stat4_s cn56xx; struct cvmx_agl_gmx_txx_stat4_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat4_s cn61xx; struct cvmx_agl_gmx_txx_stat4_s cn63xx; struct cvmx_agl_gmx_txx_stat4_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat4_s cn66xx; + struct cvmx_agl_gmx_txx_stat4_s cn68xx; + struct cvmx_agl_gmx_txx_stat4_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat5 { uint64_t u64; struct cvmx_agl_gmx_txx_stat5_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist3:32; uint64_t hist2:32; +#else + uint64_t hist2:32; + uint64_t hist3:32; +#endif } s; struct cvmx_agl_gmx_txx_stat5_s cn52xx; struct cvmx_agl_gmx_txx_stat5_s cn52xxp1; struct cvmx_agl_gmx_txx_stat5_s cn56xx; struct cvmx_agl_gmx_txx_stat5_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat5_s cn61xx; struct cvmx_agl_gmx_txx_stat5_s cn63xx; struct cvmx_agl_gmx_txx_stat5_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat5_s cn66xx; + struct cvmx_agl_gmx_txx_stat5_s cn68xx; + struct cvmx_agl_gmx_txx_stat5_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat6 { uint64_t u64; struct cvmx_agl_gmx_txx_stat6_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist5:32; uint64_t hist4:32; +#else + uint64_t hist4:32; + uint64_t hist5:32; +#endif } s; struct cvmx_agl_gmx_txx_stat6_s cn52xx; struct cvmx_agl_gmx_txx_stat6_s cn52xxp1; struct cvmx_agl_gmx_txx_stat6_s cn56xx; struct cvmx_agl_gmx_txx_stat6_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat6_s cn61xx; struct cvmx_agl_gmx_txx_stat6_s cn63xx; struct cvmx_agl_gmx_txx_stat6_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat6_s cn66xx; + struct cvmx_agl_gmx_txx_stat6_s cn68xx; + struct cvmx_agl_gmx_txx_stat6_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat7 { uint64_t u64; struct cvmx_agl_gmx_txx_stat7_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist7:32; uint64_t hist6:32; +#else + uint64_t hist6:32; + uint64_t hist7:32; +#endif } s; struct cvmx_agl_gmx_txx_stat7_s cn52xx; struct cvmx_agl_gmx_txx_stat7_s cn52xxp1; struct cvmx_agl_gmx_txx_stat7_s cn56xx; struct cvmx_agl_gmx_txx_stat7_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat7_s cn61xx; struct cvmx_agl_gmx_txx_stat7_s cn63xx; struct cvmx_agl_gmx_txx_stat7_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat7_s cn66xx; + struct cvmx_agl_gmx_txx_stat7_s cn68xx; + struct cvmx_agl_gmx_txx_stat7_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat8 { uint64_t u64; struct cvmx_agl_gmx_txx_stat8_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mcst:32; uint64_t bcst:32; +#else + uint64_t bcst:32; + uint64_t mcst:32; +#endif } s; struct cvmx_agl_gmx_txx_stat8_s cn52xx; struct cvmx_agl_gmx_txx_stat8_s cn52xxp1; struct cvmx_agl_gmx_txx_stat8_s cn56xx; struct cvmx_agl_gmx_txx_stat8_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat8_s cn61xx; struct cvmx_agl_gmx_txx_stat8_s cn63xx; struct cvmx_agl_gmx_txx_stat8_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat8_s cn66xx; + struct cvmx_agl_gmx_txx_stat8_s cn68xx; + struct cvmx_agl_gmx_txx_stat8_s cn68xxp1; }; union cvmx_agl_gmx_txx_stat9 { uint64_t u64; struct cvmx_agl_gmx_txx_stat9_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t undflw:32; uint64_t ctl:32; +#else + uint64_t ctl:32; + uint64_t undflw:32; +#endif } s; struct cvmx_agl_gmx_txx_stat9_s cn52xx; struct cvmx_agl_gmx_txx_stat9_s cn52xxp1; struct cvmx_agl_gmx_txx_stat9_s cn56xx; struct cvmx_agl_gmx_txx_stat9_s cn56xxp1; + struct cvmx_agl_gmx_txx_stat9_s cn61xx; struct cvmx_agl_gmx_txx_stat9_s cn63xx; struct cvmx_agl_gmx_txx_stat9_s cn63xxp1; + struct cvmx_agl_gmx_txx_stat9_s cn66xx; + struct cvmx_agl_gmx_txx_stat9_s cn68xx; + struct cvmx_agl_gmx_txx_stat9_s cn68xxp1; }; union cvmx_agl_gmx_txx_stats_ctl { uint64_t u64; struct cvmx_agl_gmx_txx_stats_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rd_clr:1; +#else + uint64_t rd_clr:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx; struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1; struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx; struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1; + struct cvmx_agl_gmx_txx_stats_ctl_s cn61xx; struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx; struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1; + struct cvmx_agl_gmx_txx_stats_ctl_s cn66xx; + struct cvmx_agl_gmx_txx_stats_ctl_s cn68xx; + struct cvmx_agl_gmx_txx_stats_ctl_s cn68xxp1; }; union cvmx_agl_gmx_txx_thresh { uint64_t u64; struct cvmx_agl_gmx_txx_thresh_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t cnt:6; +#else + uint64_t cnt:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_agl_gmx_txx_thresh_s cn52xx; struct cvmx_agl_gmx_txx_thresh_s cn52xxp1; struct cvmx_agl_gmx_txx_thresh_s cn56xx; struct cvmx_agl_gmx_txx_thresh_s cn56xxp1; + struct cvmx_agl_gmx_txx_thresh_s cn61xx; struct cvmx_agl_gmx_txx_thresh_s cn63xx; struct cvmx_agl_gmx_txx_thresh_s cn63xxp1; + struct cvmx_agl_gmx_txx_thresh_s cn66xx; + struct cvmx_agl_gmx_txx_thresh_s cn68xx; + struct cvmx_agl_gmx_txx_thresh_s cn68xxp1; }; union cvmx_agl_gmx_tx_bp { uint64_t u64; struct cvmx_agl_gmx_tx_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t bp:2; +#else + uint64_t bp:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_agl_gmx_tx_bp_s cn52xx; struct cvmx_agl_gmx_tx_bp_s cn52xxp1; struct cvmx_agl_gmx_tx_bp_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t bp:1; +#else + uint64_t bp:1; + uint64_t reserved_1_63:63; +#endif } cn56xx; struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1; + struct cvmx_agl_gmx_tx_bp_s cn61xx; struct cvmx_agl_gmx_tx_bp_s cn63xx; struct cvmx_agl_gmx_tx_bp_s cn63xxp1; + struct cvmx_agl_gmx_tx_bp_s cn66xx; + struct cvmx_agl_gmx_tx_bp_s cn68xx; + struct cvmx_agl_gmx_tx_bp_s cn68xxp1; }; union cvmx_agl_gmx_tx_col_attempt { uint64_t u64; struct cvmx_agl_gmx_tx_col_attempt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t limit:5; +#else + uint64_t limit:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_agl_gmx_tx_col_attempt_s cn52xx; struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1; struct cvmx_agl_gmx_tx_col_attempt_s cn56xx; struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1; + struct cvmx_agl_gmx_tx_col_attempt_s cn61xx; struct cvmx_agl_gmx_tx_col_attempt_s cn63xx; struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1; + struct cvmx_agl_gmx_tx_col_attempt_s cn66xx; + struct cvmx_agl_gmx_tx_col_attempt_s cn68xx; + struct cvmx_agl_gmx_tx_col_attempt_s cn68xxp1; }; union cvmx_agl_gmx_tx_ifg { uint64_t u64; struct cvmx_agl_gmx_tx_ifg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ifg2:4; uint64_t ifg1:4; +#else + uint64_t ifg1:4; + uint64_t ifg2:4; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_agl_gmx_tx_ifg_s cn52xx; struct cvmx_agl_gmx_tx_ifg_s cn52xxp1; struct cvmx_agl_gmx_tx_ifg_s cn56xx; struct cvmx_agl_gmx_tx_ifg_s cn56xxp1; + struct cvmx_agl_gmx_tx_ifg_s cn61xx; struct cvmx_agl_gmx_tx_ifg_s cn63xx; struct cvmx_agl_gmx_tx_ifg_s cn63xxp1; + struct cvmx_agl_gmx_tx_ifg_s cn66xx; + struct cvmx_agl_gmx_tx_ifg_s cn68xx; + struct cvmx_agl_gmx_tx_ifg_s cn68xxp1; }; union cvmx_agl_gmx_tx_int_en { uint64_t u64; struct cvmx_agl_gmx_tx_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t ptp_lost:2; uint64_t reserved_18_19:2; @@ -1254,8 +2089,23 @@ union cvmx_agl_gmx_tx_int_en { uint64_t undflw:2; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:2; + uint64_t reserved_4_7:4; + uint64_t xscol:2; + uint64_t reserved_10_11:2; + uint64_t xsdef:2; + uint64_t reserved_14_15:2; + uint64_t late_col:2; + uint64_t reserved_18_19:2; + uint64_t ptp_lost:2; + uint64_t reserved_22_63:42; +#endif } s; struct cvmx_agl_gmx_tx_int_en_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t late_col:2; uint64_t reserved_14_15:2; @@ -1266,9 +2116,22 @@ union cvmx_agl_gmx_tx_int_en { uint64_t undflw:2; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:2; + uint64_t reserved_4_7:4; + uint64_t xscol:2; + uint64_t reserved_10_11:2; + uint64_t xsdef:2; + uint64_t reserved_14_15:2; + uint64_t late_col:2; + uint64_t reserved_18_63:46; +#endif } cn52xx; struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1; struct cvmx_agl_gmx_tx_int_en_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t late_col:1; uint64_t reserved_13_15:3; @@ -1279,15 +2142,32 @@ union cvmx_agl_gmx_tx_int_en { uint64_t undflw:1; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:1; + uint64_t reserved_3_7:5; + uint64_t xscol:1; + uint64_t reserved_9_11:3; + uint64_t xsdef:1; + uint64_t reserved_13_15:3; + uint64_t late_col:1; + uint64_t reserved_17_63:47; +#endif } cn56xx; struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1; + struct cvmx_agl_gmx_tx_int_en_s cn61xx; struct cvmx_agl_gmx_tx_int_en_s cn63xx; struct cvmx_agl_gmx_tx_int_en_s cn63xxp1; + struct cvmx_agl_gmx_tx_int_en_s cn66xx; + struct cvmx_agl_gmx_tx_int_en_s cn68xx; + struct cvmx_agl_gmx_tx_int_en_s cn68xxp1; }; union cvmx_agl_gmx_tx_int_reg { uint64_t u64; struct cvmx_agl_gmx_tx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t ptp_lost:2; uint64_t reserved_18_19:2; @@ -1300,8 +2180,23 @@ union cvmx_agl_gmx_tx_int_reg { uint64_t undflw:2; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:2; + uint64_t reserved_4_7:4; + uint64_t xscol:2; + uint64_t reserved_10_11:2; + uint64_t xsdef:2; + uint64_t reserved_14_15:2; + uint64_t late_col:2; + uint64_t reserved_18_19:2; + uint64_t ptp_lost:2; + uint64_t reserved_22_63:42; +#endif } s; struct cvmx_agl_gmx_tx_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t late_col:2; uint64_t reserved_14_15:2; @@ -1312,9 +2207,22 @@ union cvmx_agl_gmx_tx_int_reg { uint64_t undflw:2; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:2; + uint64_t reserved_4_7:4; + uint64_t xscol:2; + uint64_t reserved_10_11:2; + uint64_t xsdef:2; + uint64_t reserved_14_15:2; + uint64_t late_col:2; + uint64_t reserved_18_63:46; +#endif } cn52xx; struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1; struct cvmx_agl_gmx_tx_int_reg_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t late_col:1; uint64_t reserved_13_15:3; @@ -1325,96 +2233,171 @@ union cvmx_agl_gmx_tx_int_reg { uint64_t undflw:1; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:1; + uint64_t reserved_3_7:5; + uint64_t xscol:1; + uint64_t reserved_9_11:3; + uint64_t xsdef:1; + uint64_t reserved_13_15:3; + uint64_t late_col:1; + uint64_t reserved_17_63:47; +#endif } cn56xx; struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1; + struct cvmx_agl_gmx_tx_int_reg_s cn61xx; struct cvmx_agl_gmx_tx_int_reg_s cn63xx; struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1; + struct cvmx_agl_gmx_tx_int_reg_s cn66xx; + struct cvmx_agl_gmx_tx_int_reg_s cn68xx; + struct cvmx_agl_gmx_tx_int_reg_s cn68xxp1; }; union cvmx_agl_gmx_tx_jam { uint64_t u64; struct cvmx_agl_gmx_tx_jam_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t jam:8; +#else + uint64_t jam:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_agl_gmx_tx_jam_s cn52xx; struct cvmx_agl_gmx_tx_jam_s cn52xxp1; struct cvmx_agl_gmx_tx_jam_s cn56xx; struct cvmx_agl_gmx_tx_jam_s cn56xxp1; + struct cvmx_agl_gmx_tx_jam_s cn61xx; struct cvmx_agl_gmx_tx_jam_s cn63xx; struct cvmx_agl_gmx_tx_jam_s cn63xxp1; + struct cvmx_agl_gmx_tx_jam_s cn66xx; + struct cvmx_agl_gmx_tx_jam_s cn68xx; + struct cvmx_agl_gmx_tx_jam_s cn68xxp1; }; union cvmx_agl_gmx_tx_lfsr { uint64_t u64; struct cvmx_agl_gmx_tx_lfsr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t lfsr:16; +#else + uint64_t lfsr:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_tx_lfsr_s cn52xx; struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1; struct cvmx_agl_gmx_tx_lfsr_s cn56xx; struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1; + struct cvmx_agl_gmx_tx_lfsr_s cn61xx; struct cvmx_agl_gmx_tx_lfsr_s cn63xx; struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1; + struct cvmx_agl_gmx_tx_lfsr_s cn66xx; + struct cvmx_agl_gmx_tx_lfsr_s cn68xx; + struct cvmx_agl_gmx_tx_lfsr_s cn68xxp1; }; union cvmx_agl_gmx_tx_ovr_bp { uint64_t u64; struct cvmx_agl_gmx_tx_ovr_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t en:2; uint64_t reserved_6_7:2; uint64_t bp:2; uint64_t reserved_2_3:2; uint64_t ign_full:2; +#else + uint64_t ign_full:2; + uint64_t reserved_2_3:2; + uint64_t bp:2; + uint64_t reserved_6_7:2; + uint64_t en:2; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx; struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1; struct cvmx_agl_gmx_tx_ovr_bp_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t en:1; uint64_t reserved_5_7:3; uint64_t bp:1; uint64_t reserved_1_3:3; uint64_t ign_full:1; +#else + uint64_t ign_full:1; + uint64_t reserved_1_3:3; + uint64_t bp:1; + uint64_t reserved_5_7:3; + uint64_t en:1; + uint64_t reserved_9_63:55; +#endif } cn56xx; struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1; + struct cvmx_agl_gmx_tx_ovr_bp_s cn61xx; struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx; struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1; + struct cvmx_agl_gmx_tx_ovr_bp_s cn66xx; + struct cvmx_agl_gmx_tx_ovr_bp_s cn68xx; + struct cvmx_agl_gmx_tx_ovr_bp_s cn68xxp1; }; union cvmx_agl_gmx_tx_pause_pkt_dmac { uint64_t u64; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t dmac:48; +#else + uint64_t dmac:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1; + struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn61xx; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx; struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1; + struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn66xx; + struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xx; + struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xxp1; }; union cvmx_agl_gmx_tx_pause_pkt_type { uint64_t u64; struct cvmx_agl_gmx_tx_pause_pkt_type_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t type:16; +#else + uint64_t type:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1; + struct cvmx_agl_gmx_tx_pause_pkt_type_s cn61xx; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx; struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1; + struct cvmx_agl_gmx_tx_pause_pkt_type_s cn66xx; + struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xx; + struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xxp1; }; union cvmx_agl_prtx_ctl { uint64_t u64; struct cvmx_agl_prtx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t drv_byp:1; uint64_t reserved_62_62:1; uint64_t cmp_pctl:6; @@ -1438,9 +2421,38 @@ union cvmx_agl_prtx_ctl { uint64_t enable:1; uint64_t clkrst:1; uint64_t mode:1; +#else + uint64_t mode:1; + uint64_t clkrst:1; + uint64_t enable:1; + uint64_t comp:1; + uint64_t dllrst:1; + uint64_t reserved_5_7:3; + uint64_t clktx_set:5; + uint64_t reserved_13_14:2; + uint64_t clktx_byp:1; + uint64_t clkrx_set:5; + uint64_t reserved_21_22:2; + uint64_t clkrx_byp:1; + uint64_t clk_set:5; + uint64_t reserved_29_31:3; + uint64_t drv_nctl:6; + uint64_t reserved_38_39:2; + uint64_t drv_pctl:6; + uint64_t reserved_46_47:2; + uint64_t cmp_nctl:6; + uint64_t reserved_54_55:2; + uint64_t cmp_pctl:6; + uint64_t reserved_62_62:1; + uint64_t drv_byp:1; +#endif } s; + struct cvmx_agl_prtx_ctl_s cn61xx; struct cvmx_agl_prtx_ctl_s cn63xx; struct cvmx_agl_prtx_ctl_s cn63xxp1; + struct cvmx_agl_prtx_ctl_s cn66xx; + struct cvmx_agl_prtx_ctl_s cn68xx; + struct cvmx_agl_prtx_ctl_s cn68xxp1; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-asm.h b/arch/mips/include/asm/octeon/cvmx-asm.h index 5de5de95311..31eacc24b77 100644 --- a/arch/mips/include/asm/octeon/cvmx-asm.h +++ b/arch/mips/include/asm/octeon/cvmx-asm.h @@ -32,7 +32,7 @@ #ifndef __CVMX_ASM_H__ #define __CVMX_ASM_H__ -#include "octeon-model.h" +#include <asm/octeon/octeon-model.h> /* other useful stuff */ #define CVMX_SYNC asm volatile ("sync" : : : "memory") diff --git a/arch/mips/include/asm/octeon/cvmx-asxx-defs.h b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h index 91415a85e8d..a1e21a3854c 100644 --- a/arch/mips/include/asm/octeon/cvmx-asxx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,64 +28,43 @@ #ifndef __CVMX_ASXX_DEFS_H__ #define __CVMX_ASXX_DEFS_H__ -#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000180ull + (((block_id) & 0) * 0x8000000ull)) -#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000188ull + (((block_id) & 0) * 0x8000000ull)) -#define CVMX_ASXX_INT_EN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000018ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_INT_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000010ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_MII_RX_DAT_SET(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000190ull + (((block_id) & 0) * 0x8000000ull)) -#define CVMX_ASXX_PRT_LOOP(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000040ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_BYPASS(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000248ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000250ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_COMP(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000220ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_DATA_DRV(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000218ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000210ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000230ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000240ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000228ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000238ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_SETTING(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000258ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000020ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_PRT_EN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000000ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_WOL(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000100ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_WOL_MSK(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000108ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_WOL_POWOK(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000118ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_WOL_SIG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000110ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000048ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_TX_COMP_BYP(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000068ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000080ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_TX_PRT_EN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000008ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull)) +#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull)) +#define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull)) +#define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull) union cvmx_asxx_gmii_rx_clk_set { uint64_t u64; struct cvmx_asxx_gmii_rx_clk_set_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; +#else + uint64_t setting:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_gmii_rx_clk_set_s cn30xx; struct cvmx_asxx_gmii_rx_clk_set_s cn31xx; @@ -95,8 +74,13 @@ union cvmx_asxx_gmii_rx_clk_set { union cvmx_asxx_gmii_rx_dat_set { uint64_t u64; struct cvmx_asxx_gmii_rx_dat_set_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; +#else + uint64_t setting:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_gmii_rx_dat_set_s cn30xx; struct cvmx_asxx_gmii_rx_dat_set_s cn31xx; @@ -106,18 +90,34 @@ union cvmx_asxx_gmii_rx_dat_set { union cvmx_asxx_int_en { uint64_t u64; struct cvmx_asxx_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t txpsh:4; uint64_t txpop:4; uint64_t ovrflw:4; +#else + uint64_t ovrflw:4; + uint64_t txpop:4; + uint64_t txpsh:4; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_asxx_int_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t txpsh:3; uint64_t reserved_7_7:1; uint64_t txpop:3; uint64_t reserved_3_3:1; uint64_t ovrflw:3; +#else + uint64_t ovrflw:3; + uint64_t reserved_3_3:1; + uint64_t txpop:3; + uint64_t reserved_7_7:1; + uint64_t txpsh:3; + uint64_t reserved_11_63:53; +#endif } cn30xx; struct cvmx_asxx_int_en_cn30xx cn31xx; struct cvmx_asxx_int_en_s cn38xx; @@ -130,18 +130,34 @@ union cvmx_asxx_int_en { union cvmx_asxx_int_reg { uint64_t u64; struct cvmx_asxx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t txpsh:4; uint64_t txpop:4; uint64_t ovrflw:4; +#else + uint64_t ovrflw:4; + uint64_t txpop:4; + uint64_t txpsh:4; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_asxx_int_reg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t txpsh:3; uint64_t reserved_7_7:1; uint64_t txpop:3; uint64_t reserved_3_3:1; uint64_t ovrflw:3; +#else + uint64_t ovrflw:3; + uint64_t reserved_3_3:1; + uint64_t txpop:3; + uint64_t reserved_7_7:1; + uint64_t txpsh:3; + uint64_t reserved_11_63:53; +#endif } cn30xx; struct cvmx_asxx_int_reg_cn30xx cn31xx; struct cvmx_asxx_int_reg_s cn38xx; @@ -154,8 +170,13 @@ union cvmx_asxx_int_reg { union cvmx_asxx_mii_rx_dat_set { uint64_t u64; struct cvmx_asxx_mii_rx_dat_set_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; +#else + uint64_t setting:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_mii_rx_dat_set_s cn30xx; struct cvmx_asxx_mii_rx_dat_set_s cn50xx; @@ -164,15 +185,28 @@ union cvmx_asxx_mii_rx_dat_set { union cvmx_asxx_prt_loop { uint64_t u64; struct cvmx_asxx_prt_loop_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ext_loop:4; uint64_t int_loop:4; +#else + uint64_t int_loop:4; + uint64_t ext_loop:4; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_asxx_prt_loop_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t ext_loop:3; uint64_t reserved_3_3:1; uint64_t int_loop:3; +#else + uint64_t int_loop:3; + uint64_t reserved_3_3:1; + uint64_t ext_loop:3; + uint64_t reserved_7_63:57; +#endif } cn30xx; struct cvmx_asxx_prt_loop_cn30xx cn31xx; struct cvmx_asxx_prt_loop_s cn38xx; @@ -185,8 +219,13 @@ union cvmx_asxx_prt_loop { union cvmx_asxx_rld_bypass { uint64_t u64; struct cvmx_asxx_rld_bypass_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t bypass:1; +#else + uint64_t bypass:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_asxx_rld_bypass_s cn38xx; struct cvmx_asxx_rld_bypass_s cn38xxp2; @@ -197,8 +236,13 @@ union cvmx_asxx_rld_bypass { union cvmx_asxx_rld_bypass_setting { uint64_t u64; struct cvmx_asxx_rld_bypass_setting_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; +#else + uint64_t setting:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_rld_bypass_setting_s cn38xx; struct cvmx_asxx_rld_bypass_setting_s cn38xxp2; @@ -209,14 +253,26 @@ union cvmx_asxx_rld_bypass_setting { union cvmx_asxx_rld_comp { uint64_t u64; struct cvmx_asxx_rld_comp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t pctl:5; uint64_t nctl:4; +#else + uint64_t nctl:4; + uint64_t pctl:5; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_asxx_rld_comp_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t pctl:4; uint64_t nctl:4; +#else + uint64_t nctl:4; + uint64_t pctl:4; + uint64_t reserved_8_63:56; +#endif } cn38xx; struct cvmx_asxx_rld_comp_cn38xx cn38xxp2; struct cvmx_asxx_rld_comp_s cn58xx; @@ -226,9 +282,15 @@ union cvmx_asxx_rld_comp { union cvmx_asxx_rld_data_drv { uint64_t u64; struct cvmx_asxx_rld_data_drv_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t pctl:4; uint64_t nctl:4; +#else + uint64_t nctl:4; + uint64_t pctl:4; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_asxx_rld_data_drv_s cn38xx; struct cvmx_asxx_rld_data_drv_s cn38xxp2; @@ -239,8 +301,13 @@ union cvmx_asxx_rld_data_drv { union cvmx_asxx_rld_fcram_mode { uint64_t u64; struct cvmx_asxx_rld_fcram_mode_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t mode:1; +#else + uint64_t mode:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_asxx_rld_fcram_mode_s cn38xx; struct cvmx_asxx_rld_fcram_mode_s cn38xxp2; @@ -249,8 +316,13 @@ union cvmx_asxx_rld_fcram_mode { union cvmx_asxx_rld_nctl_strong { uint64_t u64; struct cvmx_asxx_rld_nctl_strong_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t nctl:5; +#else + uint64_t nctl:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_rld_nctl_strong_s cn38xx; struct cvmx_asxx_rld_nctl_strong_s cn38xxp2; @@ -261,8 +333,13 @@ union cvmx_asxx_rld_nctl_strong { union cvmx_asxx_rld_nctl_weak { uint64_t u64; struct cvmx_asxx_rld_nctl_weak_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t nctl:5; +#else + uint64_t nctl:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_rld_nctl_weak_s cn38xx; struct cvmx_asxx_rld_nctl_weak_s cn38xxp2; @@ -273,8 +350,13 @@ union cvmx_asxx_rld_nctl_weak { union cvmx_asxx_rld_pctl_strong { uint64_t u64; struct cvmx_asxx_rld_pctl_strong_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t pctl:5; +#else + uint64_t pctl:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_rld_pctl_strong_s cn38xx; struct cvmx_asxx_rld_pctl_strong_s cn38xxp2; @@ -285,8 +367,13 @@ union cvmx_asxx_rld_pctl_strong { union cvmx_asxx_rld_pctl_weak { uint64_t u64; struct cvmx_asxx_rld_pctl_weak_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t pctl:5; +#else + uint64_t pctl:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_rld_pctl_weak_s cn38xx; struct cvmx_asxx_rld_pctl_weak_s cn38xxp2; @@ -297,16 +384,30 @@ union cvmx_asxx_rld_pctl_weak { union cvmx_asxx_rld_setting { uint64_t u64; struct cvmx_asxx_rld_setting_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t dfaset:5; uint64_t dfalag:1; uint64_t dfalead:1; uint64_t dfalock:1; uint64_t setting:5; +#else + uint64_t setting:5; + uint64_t dfalock:1; + uint64_t dfalead:1; + uint64_t dfalag:1; + uint64_t dfaset:5; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_asxx_rld_setting_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; +#else + uint64_t setting:5; + uint64_t reserved_5_63:59; +#endif } cn38xx; struct cvmx_asxx_rld_setting_cn38xx cn38xxp2; struct cvmx_asxx_rld_setting_s cn58xx; @@ -316,8 +417,13 @@ union cvmx_asxx_rld_setting { union cvmx_asxx_rx_clk_setx { uint64_t u64; struct cvmx_asxx_rx_clk_setx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; +#else + uint64_t setting:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_rx_clk_setx_s cn30xx; struct cvmx_asxx_rx_clk_setx_s cn31xx; @@ -331,12 +437,22 @@ union cvmx_asxx_rx_clk_setx { union cvmx_asxx_rx_prt_en { uint64_t u64; struct cvmx_asxx_rx_prt_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t prt_en:4; +#else + uint64_t prt_en:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_asxx_rx_prt_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t prt_en:3; +#else + uint64_t prt_en:3; + uint64_t reserved_3_63:61; +#endif } cn30xx; struct cvmx_asxx_rx_prt_en_cn30xx cn31xx; struct cvmx_asxx_rx_prt_en_s cn38xx; @@ -349,9 +465,15 @@ union cvmx_asxx_rx_prt_en { union cvmx_asxx_rx_wol { uint64_t u64; struct cvmx_asxx_rx_wol_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t status:1; uint64_t enable:1; +#else + uint64_t enable:1; + uint64_t status:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_asxx_rx_wol_s cn38xx; struct cvmx_asxx_rx_wol_s cn38xxp2; @@ -360,7 +482,11 @@ union cvmx_asxx_rx_wol { union cvmx_asxx_rx_wol_msk { uint64_t u64; struct cvmx_asxx_rx_wol_msk_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t msk:64; +#else uint64_t msk:64; +#endif } s; struct cvmx_asxx_rx_wol_msk_s cn38xx; struct cvmx_asxx_rx_wol_msk_s cn38xxp2; @@ -369,8 +495,13 @@ union cvmx_asxx_rx_wol_msk { union cvmx_asxx_rx_wol_powok { uint64_t u64; struct cvmx_asxx_rx_wol_powok_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t powerok:1; +#else + uint64_t powerok:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_asxx_rx_wol_powok_s cn38xx; struct cvmx_asxx_rx_wol_powok_s cn38xxp2; @@ -379,8 +510,13 @@ union cvmx_asxx_rx_wol_powok { union cvmx_asxx_rx_wol_sig { uint64_t u64; struct cvmx_asxx_rx_wol_sig_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t sig:32; +#else + uint64_t sig:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_asxx_rx_wol_sig_s cn38xx; struct cvmx_asxx_rx_wol_sig_s cn38xxp2; @@ -389,8 +525,13 @@ union cvmx_asxx_rx_wol_sig { union cvmx_asxx_tx_clk_setx { uint64_t u64; struct cvmx_asxx_tx_clk_setx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t setting:5; +#else + uint64_t setting:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_asxx_tx_clk_setx_s cn30xx; struct cvmx_asxx_tx_clk_setx_s cn31xx; @@ -404,34 +545,67 @@ union cvmx_asxx_tx_clk_setx { union cvmx_asxx_tx_comp_byp { uint64_t u64; struct cvmx_asxx_tx_comp_byp_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else uint64_t reserved_0_63:64; +#endif } s; struct cvmx_asxx_tx_comp_byp_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t bypass:1; uint64_t pctl:4; uint64_t nctl:4; +#else + uint64_t nctl:4; + uint64_t pctl:4; + uint64_t bypass:1; + uint64_t reserved_9_63:55; +#endif } cn30xx; struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx; struct cvmx_asxx_tx_comp_byp_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t pctl:4; uint64_t nctl:4; +#else + uint64_t nctl:4; + uint64_t pctl:4; + uint64_t reserved_8_63:56; +#endif } cn38xx; struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2; struct cvmx_asxx_tx_comp_byp_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t bypass:1; uint64_t reserved_13_15:3; uint64_t pctl:5; uint64_t reserved_5_7:3; uint64_t nctl:5; +#else + uint64_t nctl:5; + uint64_t reserved_5_7:3; + uint64_t pctl:5; + uint64_t reserved_13_15:3; + uint64_t bypass:1; + uint64_t reserved_17_63:47; +#endif } cn50xx; struct cvmx_asxx_tx_comp_byp_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t pctl:5; uint64_t reserved_5_7:3; uint64_t nctl:5; +#else + uint64_t nctl:5; + uint64_t reserved_5_7:3; + uint64_t pctl:5; + uint64_t reserved_13_63:51; +#endif } cn58xx; struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1; }; @@ -439,12 +613,22 @@ union cvmx_asxx_tx_comp_byp { union cvmx_asxx_tx_hi_waterx { uint64_t u64; struct cvmx_asxx_tx_hi_waterx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t mark:4; +#else + uint64_t mark:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_asxx_tx_hi_waterx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t mark:3; +#else + uint64_t mark:3; + uint64_t reserved_3_63:61; +#endif } cn30xx; struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx; struct cvmx_asxx_tx_hi_waterx_s cn38xx; @@ -457,12 +641,22 @@ union cvmx_asxx_tx_hi_waterx { union cvmx_asxx_tx_prt_en { uint64_t u64; struct cvmx_asxx_tx_prt_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t prt_en:4; +#else + uint64_t prt_en:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_asxx_tx_prt_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t prt_en:3; +#else + uint64_t prt_en:3; + uint64_t reserved_3_63:61; +#endif } cn30xx; struct cvmx_asxx_tx_prt_en_cn30xx cn31xx; struct cvmx_asxx_tx_prt_en_s cn38xx; diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h index 1db1dc2724c..7b7818d1e4d 100644 --- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h +++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h @@ -91,11 +91,11 @@ struct cvmx_bootinfo { #if (CVMX_BOOTINFO_MIN_VER >= 1) /* * Several boards support compact flash on the Octeon boot - * bus. The CF memory spaces may be mapped to different + * bus. The CF memory spaces may be mapped to different * addresses on different boards. These are the physical * addresses, so care must be taken to use the correct * XKPHYS/KSEG0 addressing depending on the application's - * ABI. These values will be 0 if CF is not present. + * ABI. These values will be 0 if CF is not present. */ uint64_t compact_flash_common_base_addr; uint64_t compact_flash_attribute_base_addr; @@ -131,7 +131,7 @@ struct cvmx_bootinfo { #define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC (1ull << 3) /* This flag is set if the TLB mappings are not contained in the * 0x10000000 - 0x20000000 boot bus region. */ -#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING (1ull << 4) +#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING (1ull << 4) #define CVMX_BOOTINFO_CFG_FLAG_BREAK (1ull << 5) #endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */ @@ -164,9 +164,9 @@ enum cvmx_board_types_enum { CVMX_BOARD_TYPE_EBT5600 = 22, CVMX_BOARD_TYPE_EBH5201 = 23, CVMX_BOARD_TYPE_EBT5200 = 24, - CVMX_BOARD_TYPE_CB5600 = 25, - CVMX_BOARD_TYPE_CB5601 = 26, - CVMX_BOARD_TYPE_CB5200 = 27, + CVMX_BOARD_TYPE_CB5600 = 25, + CVMX_BOARD_TYPE_CB5601 = 26, + CVMX_BOARD_TYPE_CB5200 = 27, /* Special 'generic' board type, supports many boards */ CVMX_BOARD_TYPE_GENERIC = 28, CVMX_BOARD_TYPE_EBH5610 = 29, @@ -223,10 +223,11 @@ enum cvmx_board_types_enum { CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000, /* - * Set aside a range for customer private use. The SDK won't + * Set aside a range for customer private use. The SDK won't * use any numbers in this range. */ CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, + CVMX_BOARD_TYPE_UBNT_E100 = 20002, CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, /* The remaining range is reserved for future use. */ @@ -325,6 +326,7 @@ static inline const char *cvmx_board_type_to_string(enum /* Customer private range */ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX) } return "Unsupported Board"; diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h index 877845b84b1..352f1dc2508 100644 --- a/arch/mips/include/asm/octeon/cvmx-bootmem.h +++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h @@ -39,7 +39,7 @@ #define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64 /* minimum alignment of bootmem alloced blocks */ -#define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull) +#define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull) /* Flags for cvmx_bootmem_phy_mem* functions */ /* Allocate from end of block instead of beginning */ @@ -151,8 +151,8 @@ extern void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment); * memory cannot be allocated at the specified address. * * @size: Size in bytes of block to allocate - * @address: Physical address to allocate memory at. If this memory is not - * available, the allocation fails. + * @address: Physical address to allocate memory at. If this memory is not + * available, the allocation fails. * @alignment: Alignment required - must be power of 2 * Returns pointer to block of memory, NULL on error */ @@ -181,7 +181,7 @@ extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment, * @name: name of block to free * * Returns 0 on failure, - * !0 on success + * !0 on success */ @@ -210,9 +210,9 @@ extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, * * @size: Size in bytes of block to allocate * @address: Physical address to allocate memory at. If this - * memory is not available, the allocation fails. + * memory is not available, the allocation fails. * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN - * bytes + * bytes * * Returns a pointer to block of memory, NULL on error */ @@ -249,7 +249,7 @@ extern int cvmx_bootmem_free_named(char *name); * @name: name of block to free * * Returns pointer to named block descriptor on success - * 0 on failure + * 0 on failure */ struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name); @@ -258,20 +258,20 @@ struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name); * (optional) requested address and alignment. * * @req_size: size of region to allocate. All requests are rounded up - * to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size + * to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size * * @address_min: Minimum address that block can occupy. * * @address_max: Specifies the maximum address_min (inclusive) that - * the allocation can use. + * the allocation can use. * * @alignment: Requested alignment of the block. If this alignment - * cannot be met, the allocation fails. This must be a - * power of 2. (Note: Alignment of - * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and - * internally enforced. Requested alignments of less than - * CVMX_BOOTMEM_ALIGNMENT_SIZE are set to - * CVMX_BOOTMEM_ALIGNMENT_SIZE.) + * cannot be met, the allocation fails. This must be a + * power of 2. (Note: Alignment of + * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and + * internally enforced. Requested alignments of less than + * CVMX_BOOTMEM_ALIGNMENT_SIZE are set to + * CVMX_BOOTMEM_ALIGNMENT_SIZE.) * * @flags: Flags to control options for the allocation. * @@ -285,21 +285,21 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, * Allocates a named block of physical memory from the free list, at * (optional) requested address and alignment. * - * @param size size of region to allocate. All requests are rounded - * up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE - * bytes size + * @param size size of region to allocate. All requests are rounded + * up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE + * bytes size * @param min_addr Minimum address that block can occupy. * @param max_addr Specifies the maximum address_min (inclusive) that - * the allocation can use. + * the allocation can use. * @param alignment Requested alignment of the block. If this - * alignment cannot be met, the allocation fails. - * This must be a power of 2. (Note: Alignment of - * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and - * internally enforced. Requested alignments of less - * than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to - * CVMX_BOOTMEM_ALIGNMENT_SIZE.) - * @param name name to assign to named block - * @param flags Flags to control options for the allocation. + * alignment cannot be met, the allocation fails. + * This must be a power of 2. (Note: Alignment of + * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and + * internally enforced. Requested alignments of less + * than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to + * CVMX_BOOTMEM_ALIGNMENT_SIZE.) + * @param name name to assign to named block + * @param flags Flags to control options for the allocation. * * @return physical address of block allocated, or -1 on failure */ @@ -312,14 +312,14 @@ int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr, * Finds a named memory block by name. * Also used for finding an unused entry in the named block table. * - * @name: Name of memory block to find. If NULL pointer given, then - * finds unused descriptor, if available. + * @name: Name of memory block to find. If NULL pointer given, then + * finds unused descriptor, if available. * * @flags: Flags to control options for the allocation. * * Returns Pointer to memory block descriptor, NULL if not found. - * If NULL returned when name parameter is NULL, then no memory - * block descriptors are available. + * If NULL returned when name parameter is NULL, then no memory + * block descriptors are available. */ struct cvmx_bootmem_named_block_desc * cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags); @@ -331,31 +331,31 @@ cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags); * @flags: flags for passing options * * Returns 0 on failure - * 1 on success + * 1 on success */ int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags); /** - * Frees a block to the bootmem allocator list. This must + * Frees a block to the bootmem allocator list. This must * be used with care, as the size provided must match the size * of the block that was allocated, or the list will become * corrupted. * * IMPORTANT: This is only intended to be used as part of named block * frees and initial population of the free memory list. - * * + * * * * @phy_addr: physical address of block * @size: size of block in bytes. * @flags: flags for passing options * * Returns 1 on success, - * 0 on failure + * 0 on failure */ int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags); /** - * Locks the bootmem allocator. This is useful in certain situations + * Locks the bootmem allocator. This is useful in certain situations * where multiple allocations must be made without being interrupted. * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag. * @@ -370,4 +370,6 @@ void cvmx_bootmem_lock(void); */ void cvmx_bootmem_unlock(void); +extern struct cvmx_bootmem_desc *cvmx_bootmem_get_desc(void); + #endif /* __CVMX_BOOTMEM_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h index 27cead37041..0dd0e40c96d 100644 --- a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -31,6 +31,18 @@ #define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull)) #define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull)) #define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull)) +#define CVMX_CIU_EN2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x000107000000A600ull) + ((offset) & 1) * 8) +#define CVMX_CIU_EN2_IOX_INT_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8) +#define CVMX_CIU_EN2_IOX_INT_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8) +#define CVMX_CIU_EN2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x000107000000A000ull) + ((offset) & 15) * 8) +#define CVMX_CIU_EN2_PPX_IP2_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8) +#define CVMX_CIU_EN2_PPX_IP2_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8) +#define CVMX_CIU_EN2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x000107000000A200ull) + ((offset) & 15) * 8) +#define CVMX_CIU_EN2_PPX_IP3_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8) +#define CVMX_CIU_EN2_PPX_IP3_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8) +#define CVMX_CIU_EN2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8) +#define CVMX_CIU_EN2_PPX_IP4_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8) +#define CVMX_CIU_EN2_PPX_IP4_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8) #define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull)) #define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull)) #define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull)) @@ -50,59 +62,378 @@ #define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8) #define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull)) #define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull)) -#define CVMX_CIU_MBOX_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8) -#define CVMX_CIU_MBOX_SETX(offset) (CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8) +static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070100100600ull) + (offset) * 8; + } + return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; +} + +static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070100100400ull) + (offset) * 8; + } + return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; +} + #define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull)) #define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull)) +#define CVMX_CIU_PP_BIST_STAT (CVMX_ADD_IO_SEG(0x00010700000007E0ull)) #define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull)) -#define CVMX_CIU_PP_POKEX(offset) (CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8) +static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070100100200ull) + (offset) * 8; + } + return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; +} + #define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull)) #define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull)) #define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull)) #define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull)) +#define CVMX_CIU_QLM3 (CVMX_ADD_IO_SEG(0x0001070000000798ull)) +#define CVMX_CIU_QLM4 (CVMX_ADD_IO_SEG(0x00010700000007A0ull)) #define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull)) #define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull)) #define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull)) #define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull)) #define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull)) #define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull)) +#define CVMX_CIU_SOFT_PRST2 (CVMX_ADD_IO_SEG(0x00010700000007D8ull)) +#define CVMX_CIU_SOFT_PRST3 (CVMX_ADD_IO_SEG(0x00010700000007E0ull)) #define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull)) -#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8) -#define CVMX_CIU_WDOGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8) +#define CVMX_CIU_SUM1_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008600ull) + ((offset) & 1) * 8) +#define CVMX_CIU_SUM1_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008000ull) + ((offset) & 15) * 8) +#define CVMX_CIU_SUM1_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008200ull) + ((offset) & 15) * 8) +#define CVMX_CIU_SUM1_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008400ull) + ((offset) & 15) * 8) +#define CVMX_CIU_SUM2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008E00ull) + ((offset) & 1) * 8) +#define CVMX_CIU_SUM2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008800ull) + ((offset) & 15) * 8) +#define CVMX_CIU_SUM2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008A00ull) + ((offset) & 15) * 8) +#define CVMX_CIU_SUM2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8) +#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8) +#define CVMX_CIU_TIM_MULTI_CAST (CVMX_ADD_IO_SEG(0x000107000000C200ull)) +static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001070100100000ull) + (offset) * 8; + } + return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; +} union cvmx_ciu_bist { uint64_t u64; struct cvmx_ciu_bist_s { - uint64_t reserved_5_63:59; - uint64_t bist:5; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t bist:7; +#else + uint64_t bist:7; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_ciu_bist_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t bist:4; +#else + uint64_t bist:4; + uint64_t reserved_4_63:60; +#endif } cn30xx; struct cvmx_ciu_bist_cn30xx cn31xx; struct cvmx_ciu_bist_cn30xx cn38xx; struct cvmx_ciu_bist_cn30xx cn38xxp2; struct cvmx_ciu_bist_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t bist:2; +#else + uint64_t bist:2; + uint64_t reserved_2_63:62; +#endif } cn50xx; struct cvmx_ciu_bist_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t bist:3; +#else + uint64_t bist:3; + uint64_t reserved_3_63:61; +#endif } cn52xx; struct cvmx_ciu_bist_cn52xx cn52xxp1; struct cvmx_ciu_bist_cn30xx cn56xx; struct cvmx_ciu_bist_cn30xx cn56xxp1; struct cvmx_ciu_bist_cn30xx cn58xx; struct cvmx_ciu_bist_cn30xx cn58xxp1; - struct cvmx_ciu_bist_s cn63xx; - struct cvmx_ciu_bist_s cn63xxp1; + struct cvmx_ciu_bist_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_6_63:58; + uint64_t bist:6; +#else + uint64_t bist:6; + uint64_t reserved_6_63:58; +#endif + } cn61xx; + struct cvmx_ciu_bist_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_5_63:59; + uint64_t bist:5; +#else + uint64_t bist:5; + uint64_t reserved_5_63:59; +#endif + } cn63xx; + struct cvmx_ciu_bist_cn63xx cn63xxp1; + struct cvmx_ciu_bist_cn61xx cn66xx; + struct cvmx_ciu_bist_s cn68xx; + struct cvmx_ciu_bist_s cn68xxp1; + struct cvmx_ciu_bist_cn61xx cnf71xx; }; union cvmx_ciu_block_int { uint64_t u64; struct cvmx_ciu_block_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_62_63:2; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_43_59:17; + uint64_t ptp:1; + uint64_t dpi:1; + uint64_t dfm:1; + uint64_t reserved_34_39:6; + uint64_t srio1:1; + uint64_t srio0:1; + uint64_t reserved_31_31:1; + uint64_t iob:1; + uint64_t reserved_29_29:1; + uint64_t agl:1; + uint64_t reserved_27_27:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t reserved_24_24:1; + uint64_t asxpcs1:1; + uint64_t asxpcs0:1; + uint64_t reserved_21_21:1; + uint64_t pip:1; + uint64_t reserved_18_19:2; + uint64_t lmc0:1; + uint64_t l2c:1; + uint64_t reserved_15_15:1; + uint64_t rad:1; + uint64_t usb:1; + uint64_t pow:1; + uint64_t tim:1; + uint64_t pko:1; + uint64_t ipd:1; + uint64_t reserved_8_8:1; + uint64_t zip:1; + uint64_t dfa:1; + uint64_t fpa:1; + uint64_t key:1; + uint64_t sli:1; + uint64_t gmx1:1; + uint64_t gmx0:1; + uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t gmx1:1; + uint64_t sli:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t reserved_8_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t usb:1; + uint64_t rad:1; + uint64_t reserved_15_15:1; + uint64_t l2c:1; + uint64_t lmc0:1; + uint64_t reserved_18_19:2; + uint64_t pip:1; + uint64_t reserved_21_21:1; + uint64_t asxpcs0:1; + uint64_t asxpcs1:1; + uint64_t reserved_24_24:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_27_27:1; + uint64_t agl:1; + uint64_t reserved_29_29:1; + uint64_t iob:1; + uint64_t reserved_31_31:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t reserved_34_39:6; + uint64_t dfm:1; + uint64_t dpi:1; + uint64_t ptp:1; + uint64_t reserved_43_59:17; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_63:2; +#endif + } s; + struct cvmx_ciu_block_int_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_43_63:21; + uint64_t ptp:1; + uint64_t dpi:1; + uint64_t reserved_31_40:10; + uint64_t iob:1; + uint64_t reserved_29_29:1; + uint64_t agl:1; + uint64_t reserved_27_27:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t reserved_24_24:1; + uint64_t asxpcs1:1; + uint64_t asxpcs0:1; + uint64_t reserved_21_21:1; + uint64_t pip:1; + uint64_t reserved_18_19:2; + uint64_t lmc0:1; + uint64_t l2c:1; + uint64_t reserved_15_15:1; + uint64_t rad:1; + uint64_t usb:1; + uint64_t pow:1; + uint64_t tim:1; + uint64_t pko:1; + uint64_t ipd:1; + uint64_t reserved_8_8:1; + uint64_t zip:1; + uint64_t dfa:1; + uint64_t fpa:1; + uint64_t key:1; + uint64_t sli:1; + uint64_t gmx1:1; + uint64_t gmx0:1; + uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t gmx1:1; + uint64_t sli:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t reserved_8_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t usb:1; + uint64_t rad:1; + uint64_t reserved_15_15:1; + uint64_t l2c:1; + uint64_t lmc0:1; + uint64_t reserved_18_19:2; + uint64_t pip:1; + uint64_t reserved_21_21:1; + uint64_t asxpcs0:1; + uint64_t asxpcs1:1; + uint64_t reserved_24_24:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_27_27:1; + uint64_t agl:1; + uint64_t reserved_29_29:1; + uint64_t iob:1; + uint64_t reserved_31_40:10; + uint64_t dpi:1; + uint64_t ptp:1; + uint64_t reserved_43_63:21; +#endif + } cn61xx; + struct cvmx_ciu_block_int_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_43_63:21; uint64_t ptp:1; uint64_t dpi:1; @@ -140,88 +471,789 @@ union cvmx_ciu_block_int { uint64_t reserved_2_2:1; uint64_t gmx0:1; uint64_t mio:1; - } s; - struct cvmx_ciu_block_int_s cn63xx; - struct cvmx_ciu_block_int_s cn63xxp1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t reserved_2_2:1; + uint64_t sli:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t reserved_8_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t usb:1; + uint64_t rad:1; + uint64_t reserved_15_15:1; + uint64_t l2c:1; + uint64_t lmc0:1; + uint64_t reserved_18_19:2; + uint64_t pip:1; + uint64_t reserved_21_21:1; + uint64_t asxpcs0:1; + uint64_t reserved_23_24:2; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_27_27:1; + uint64_t agl:1; + uint64_t reserved_29_29:1; + uint64_t iob:1; + uint64_t reserved_31_31:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t reserved_34_39:6; + uint64_t dfm:1; + uint64_t dpi:1; + uint64_t ptp:1; + uint64_t reserved_43_63:21; +#endif + } cn63xx; + struct cvmx_ciu_block_int_cn63xx cn63xxp1; + struct cvmx_ciu_block_int_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_62_63:2; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_43_59:17; + uint64_t ptp:1; + uint64_t dpi:1; + uint64_t dfm:1; + uint64_t reserved_33_39:7; + uint64_t srio0:1; + uint64_t reserved_31_31:1; + uint64_t iob:1; + uint64_t reserved_29_29:1; + uint64_t agl:1; + uint64_t reserved_27_27:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t reserved_24_24:1; + uint64_t asxpcs1:1; + uint64_t asxpcs0:1; + uint64_t reserved_21_21:1; + uint64_t pip:1; + uint64_t reserved_18_19:2; + uint64_t lmc0:1; + uint64_t l2c:1; + uint64_t reserved_15_15:1; + uint64_t rad:1; + uint64_t usb:1; + uint64_t pow:1; + uint64_t tim:1; + uint64_t pko:1; + uint64_t ipd:1; + uint64_t reserved_8_8:1; + uint64_t zip:1; + uint64_t dfa:1; + uint64_t fpa:1; + uint64_t key:1; + uint64_t sli:1; + uint64_t gmx1:1; + uint64_t gmx0:1; + uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t gmx1:1; + uint64_t sli:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t reserved_8_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t usb:1; + uint64_t rad:1; + uint64_t reserved_15_15:1; + uint64_t l2c:1; + uint64_t lmc0:1; + uint64_t reserved_18_19:2; + uint64_t pip:1; + uint64_t reserved_21_21:1; + uint64_t asxpcs0:1; + uint64_t asxpcs1:1; + uint64_t reserved_24_24:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_27_27:1; + uint64_t agl:1; + uint64_t reserved_29_29:1; + uint64_t iob:1; + uint64_t reserved_31_31:1; + uint64_t srio0:1; + uint64_t reserved_33_39:7; + uint64_t dfm:1; + uint64_t dpi:1; + uint64_t ptp:1; + uint64_t reserved_43_59:17; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_63:2; +#endif + } cn66xx; + struct cvmx_ciu_block_int_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_43_63:21; + uint64_t ptp:1; + uint64_t dpi:1; + uint64_t reserved_31_40:10; + uint64_t iob:1; + uint64_t reserved_27_29:3; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t reserved_23_24:2; + uint64_t asxpcs0:1; + uint64_t reserved_21_21:1; + uint64_t pip:1; + uint64_t reserved_18_19:2; + uint64_t lmc0:1; + uint64_t l2c:1; + uint64_t reserved_15_15:1; + uint64_t rad:1; + uint64_t usb:1; + uint64_t pow:1; + uint64_t tim:1; + uint64_t pko:1; + uint64_t ipd:1; + uint64_t reserved_6_8:3; + uint64_t fpa:1; + uint64_t key:1; + uint64_t sli:1; + uint64_t reserved_2_2:1; + uint64_t gmx0:1; + uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t reserved_2_2:1; + uint64_t sli:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t reserved_6_8:3; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t usb:1; + uint64_t rad:1; + uint64_t reserved_15_15:1; + uint64_t l2c:1; + uint64_t lmc0:1; + uint64_t reserved_18_19:2; + uint64_t pip:1; + uint64_t reserved_21_21:1; + uint64_t asxpcs0:1; + uint64_t reserved_23_24:2; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_27_29:3; + uint64_t iob:1; + uint64_t reserved_31_40:10; + uint64_t dpi:1; + uint64_t ptp:1; + uint64_t reserved_43_63:21; +#endif + } cnf71xx; }; union cvmx_ciu_dint { uint64_t u64; struct cvmx_ciu_dint_s { - uint64_t reserved_16_63:48; - uint64_t dint:16; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t dint:32; +#else + uint64_t dint:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_ciu_dint_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t dint:1; +#else + uint64_t dint:1; + uint64_t reserved_1_63:63; +#endif } cn30xx; struct cvmx_ciu_dint_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dint:2; +#else + uint64_t dint:2; + uint64_t reserved_2_63:62; +#endif } cn31xx; - struct cvmx_ciu_dint_s cn38xx; - struct cvmx_ciu_dint_s cn38xxp2; + struct cvmx_ciu_dint_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t dint:16; +#else + uint64_t dint:16; + uint64_t reserved_16_63:48; +#endif + } cn38xx; + struct cvmx_ciu_dint_cn38xx cn38xxp2; struct cvmx_ciu_dint_cn31xx cn50xx; struct cvmx_ciu_dint_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t dint:4; +#else + uint64_t dint:4; + uint64_t reserved_4_63:60; +#endif } cn52xx; struct cvmx_ciu_dint_cn52xx cn52xxp1; struct cvmx_ciu_dint_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t dint:12; +#else + uint64_t dint:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_dint_cn56xx cn56xxp1; - struct cvmx_ciu_dint_s cn58xx; - struct cvmx_ciu_dint_s cn58xxp1; + struct cvmx_ciu_dint_cn38xx cn58xx; + struct cvmx_ciu_dint_cn38xx cn58xxp1; + struct cvmx_ciu_dint_cn52xx cn61xx; struct cvmx_ciu_dint_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t dint:6; +#else + uint64_t dint:6; + uint64_t reserved_6_63:58; +#endif } cn63xx; struct cvmx_ciu_dint_cn63xx cn63xxp1; + struct cvmx_ciu_dint_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t dint:10; +#else + uint64_t dint:10; + uint64_t reserved_10_63:54; +#endif + } cn66xx; + struct cvmx_ciu_dint_s cn68xx; + struct cvmx_ciu_dint_s cn68xxp1; + struct cvmx_ciu_dint_cn52xx cnf71xx; +}; + +union cvmx_ciu_en2_iox_int { + uint64_t u64; + struct cvmx_ciu_en2_iox_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_iox_int_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_iox_int_cn61xx cn66xx; + struct cvmx_ciu_en2_iox_int_s cnf71xx; +}; + +union cvmx_ciu_en2_iox_int_w1c { + uint64_t u64; + struct cvmx_ciu_en2_iox_int_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_iox_int_w1c_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_iox_int_w1c_cn61xx cn66xx; + struct cvmx_ciu_en2_iox_int_w1c_s cnf71xx; +}; + +union cvmx_ciu_en2_iox_int_w1s { + uint64_t u64; + struct cvmx_ciu_en2_iox_int_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_iox_int_w1s_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_iox_int_w1s_cn61xx cn66xx; + struct cvmx_ciu_en2_iox_int_w1s_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip2 { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip2_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip2_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip2_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip2_w1c { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip2_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip2_w1c_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip2_w1s { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip2_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip2_w1s_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip3 { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip3_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip3_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip3_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip3_w1c { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip3_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip3_w1c_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip3_w1s { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip3_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip3_w1s_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip4 { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip4_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip4_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip4_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip4_w1c { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip4_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip4_w1c_s cnf71xx; +}; + +union cvmx_ciu_en2_ppx_ip4_w1s { + uint64_t u64; + struct cvmx_ciu_en2_ppx_ip4_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx cn66xx; + struct cvmx_ciu_en2_ppx_ip4_w1s_s cnf71xx; }; union cvmx_ciu_fuse { uint64_t u64; struct cvmx_ciu_fuse_s { - uint64_t reserved_16_63:48; - uint64_t fuse:16; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t fuse:32; +#else + uint64_t fuse:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_ciu_fuse_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t fuse:1; +#else + uint64_t fuse:1; + uint64_t reserved_1_63:63; +#endif } cn30xx; struct cvmx_ciu_fuse_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t fuse:2; +#else + uint64_t fuse:2; + uint64_t reserved_2_63:62; +#endif } cn31xx; - struct cvmx_ciu_fuse_s cn38xx; - struct cvmx_ciu_fuse_s cn38xxp2; + struct cvmx_ciu_fuse_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t fuse:16; +#else + uint64_t fuse:16; + uint64_t reserved_16_63:48; +#endif + } cn38xx; + struct cvmx_ciu_fuse_cn38xx cn38xxp2; struct cvmx_ciu_fuse_cn31xx cn50xx; struct cvmx_ciu_fuse_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t fuse:4; +#else + uint64_t fuse:4; + uint64_t reserved_4_63:60; +#endif } cn52xx; struct cvmx_ciu_fuse_cn52xx cn52xxp1; struct cvmx_ciu_fuse_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t fuse:12; +#else + uint64_t fuse:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_fuse_cn56xx cn56xxp1; - struct cvmx_ciu_fuse_s cn58xx; - struct cvmx_ciu_fuse_s cn58xxp1; + struct cvmx_ciu_fuse_cn38xx cn58xx; + struct cvmx_ciu_fuse_cn38xx cn58xxp1; + struct cvmx_ciu_fuse_cn52xx cn61xx; struct cvmx_ciu_fuse_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t fuse:6; +#else + uint64_t fuse:6; + uint64_t reserved_6_63:58; +#endif } cn63xx; struct cvmx_ciu_fuse_cn63xx cn63xxp1; + struct cvmx_ciu_fuse_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t fuse:10; +#else + uint64_t fuse:10; + uint64_t reserved_10_63:54; +#endif + } cn66xx; + struct cvmx_ciu_fuse_s cn68xx; + struct cvmx_ciu_fuse_s cn68xxp1; + struct cvmx_ciu_fuse_cn52xx cnf71xx; }; union cvmx_ciu_gstop { uint64_t u64; struct cvmx_ciu_gstop_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t gstop:1; +#else + uint64_t gstop:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_ciu_gstop_s cn30xx; struct cvmx_ciu_gstop_s cn31xx; @@ -234,13 +1266,19 @@ union cvmx_ciu_gstop { struct cvmx_ciu_gstop_s cn56xxp1; struct cvmx_ciu_gstop_s cn58xx; struct cvmx_ciu_gstop_s cn58xxp1; + struct cvmx_ciu_gstop_s cn61xx; struct cvmx_ciu_gstop_s cn63xx; struct cvmx_ciu_gstop_s cn63xxp1; + struct cvmx_ciu_gstop_s cn66xx; + struct cvmx_ciu_gstop_s cn68xx; + struct cvmx_ciu_gstop_s cn68xxp1; + struct cvmx_ciu_gstop_s cnf71xx; }; union cvmx_ciu_intx_en0 { uint64_t u64; struct cvmx_ciu_intx_en0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -263,8 +1301,33 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } s; struct cvmx_ciu_intx_en0_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t mpi:1; uint64_t pcm:1; @@ -284,8 +1347,30 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t reserved_47_47:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t reserved_59_63:5; +#endif } cn30xx; struct cvmx_ciu_intx_en0_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t mpi:1; uint64_t pcm:1; @@ -305,8 +1390,30 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t reserved_59_63:5; +#endif } cn31xx; struct cvmx_ciu_intx_en0_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -322,10 +1429,28 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t reserved_56_63:8; +#endif } cn38xx; struct cvmx_ciu_intx_en0_cn38xx cn38xxp2; struct cvmx_ciu_intx_en0_cn30xx cn50xx; struct cvmx_ciu_intx_en0_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -348,9 +1473,34 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn52xx; struct cvmx_ciu_intx_en0_cn52xx cn52xxp1; struct cvmx_ciu_intx_en0_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -372,23 +1522,197 @@ union cvmx_ciu_intx_en0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn56xx; struct cvmx_ciu_intx_en0_cn56xx cn56xxp1; struct cvmx_ciu_intx_en0_cn38xx cn58xx; struct cvmx_ciu_intx_en0_cn38xx cn58xxp1; + struct cvmx_ciu_intx_en0_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en0_cn52xx cn63xx; struct cvmx_ciu_intx_en0_cn52xx cn63xxp1; + struct cvmx_ciu_intx_en0_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en0_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en0_w1c { uint64_t u64; struct cvmx_ciu_intx_en0_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; uint64_t powiq:1; uint64_t twsi2:1; - uint64_t reserved_57_58:2; + uint64_t mpi:1; + uint64_t pcm:1; uint64_t usb:1; uint64_t timer:4; uint64_t key_zero:1; @@ -404,8 +1728,33 @@ union cvmx_ciu_intx_en0_w1c { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } s; struct cvmx_ciu_intx_en0_w1c_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -428,9 +1777,80 @@ union cvmx_ciu_intx_en0_w1c { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn52xx; - struct cvmx_ciu_intx_en0_w1c_s cn56xx; + struct cvmx_ciu_intx_en0_w1c_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; + uint64_t usb:1; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn56xx; struct cvmx_ciu_intx_en0_w1c_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -446,20 +1866,188 @@ union cvmx_ciu_intx_en0_w1c { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t reserved_56_63:8; +#endif } cn58xx; + struct cvmx_ciu_intx_en0_w1c_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx; struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1; + struct cvmx_ciu_intx_en0_w1c_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en0_w1c_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en0_w1s { uint64_t u64; struct cvmx_ciu_intx_en0_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; uint64_t powiq:1; uint64_t twsi2:1; - uint64_t reserved_57_58:2; + uint64_t mpi:1; + uint64_t pcm:1; uint64_t usb:1; uint64_t timer:4; uint64_t key_zero:1; @@ -475,8 +2063,33 @@ union cvmx_ciu_intx_en0_w1s { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } s; struct cvmx_ciu_intx_en0_w1s_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -499,9 +2112,80 @@ union cvmx_ciu_intx_en0_w1s { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn52xx; - struct cvmx_ciu_intx_en0_w1s_s cn56xx; + struct cvmx_ciu_intx_en0_w1s_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; + uint64_t usb:1; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn56xx; struct cvmx_ciu_intx_en0_w1s_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -517,16 +2201,186 @@ union cvmx_ciu_intx_en0_w1s { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t reserved_56_63:8; +#endif } cn58xx; + struct cvmx_ciu_intx_en0_w1s_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx; struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1; + struct cvmx_ciu_intx_en0_w1s_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en0_w1s_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en1 { uint64_t u64; struct cvmx_ciu_intx_en1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; - uint64_t reserved_57_62:6; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; @@ -536,7 +2390,10 @@ union cvmx_ciu_intx_en1 { uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_37_45:9; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -559,22 +2416,80 @@ union cvmx_ciu_intx_en1 { uint64_t usb1:1; uint64_t uart2:1; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif } s; struct cvmx_ciu_intx_en1_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t wdog:1; +#else + uint64_t wdog:1; + uint64_t reserved_1_63:63; +#endif } cn30xx; struct cvmx_ciu_intx_en1_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t wdog:2; +#else + uint64_t wdog:2; + uint64_t reserved_2_63:62; +#endif } cn31xx; struct cvmx_ciu_intx_en1_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_ciu_intx_en1_cn38xx cn38xxp2; struct cvmx_ciu_intx_en1_cn31xx cn50xx; struct cvmx_ciu_intx_en1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t nand:1; uint64_t mii1:1; @@ -582,23 +2497,118 @@ union cvmx_ciu_intx_en1 { uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_ciu_intx_en1_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t mii1:1; uint64_t usb1:1; uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t reserved_19_63:45; +#endif } cn52xxp1; struct cvmx_ciu_intx_en1_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t wdog:12; +#else + uint64_t wdog:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_intx_en1_cn56xx cn56xxp1; struct cvmx_ciu_intx_en1_cn38xx cn58xx; struct cvmx_ciu_intx_en1_cn38xx cn58xxp1; + struct cvmx_ciu_intx_en1_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en1_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; uint64_t reserved_57_62:6; uint64_t dfm:1; @@ -632,15 +2642,198 @@ union cvmx_ciu_intx_en1 { uint64_t mii1:1; uint64_t reserved_6_17:12; uint64_t wdog:6; +#else + uint64_t wdog:6; + uint64_t reserved_6_17:12; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_45:9; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_62:6; + uint64_t rst:1; +#endif } cn63xx; struct cvmx_ciu_intx_en1_cn63xx cn63xxp1; + struct cvmx_ciu_intx_en1_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en1_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en1_w1c { uint64_t u64; struct cvmx_ciu_intx_en1_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; - uint64_t reserved_57_62:6; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; @@ -650,7 +2843,10 @@ union cvmx_ciu_intx_en1_w1c { uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_37_45:9; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -673,8 +2869,51 @@ union cvmx_ciu_intx_en1_w1c { uint64_t usb1:1; uint64_t uart2:1; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif } s; struct cvmx_ciu_intx_en1_w1c_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t nand:1; uint64_t mii1:1; @@ -682,16 +2921,107 @@ union cvmx_ciu_intx_en1_w1c { uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_ciu_intx_en1_w1c_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t wdog:12; +#else + uint64_t wdog:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_intx_en1_w1c_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t reserved_16_63:48; +#endif } cn58xx; + struct cvmx_ciu_intx_en1_w1c_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en1_w1c_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; uint64_t reserved_57_62:6; uint64_t dfm:1; @@ -725,15 +3055,198 @@ union cvmx_ciu_intx_en1_w1c { uint64_t mii1:1; uint64_t reserved_6_17:12; uint64_t wdog:6; +#else + uint64_t wdog:6; + uint64_t reserved_6_17:12; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_45:9; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_62:6; + uint64_t rst:1; +#endif } cn63xx; struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1; + struct cvmx_ciu_intx_en1_w1c_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en1_w1c_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en1_w1s { uint64_t u64; struct cvmx_ciu_intx_en1_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; - uint64_t reserved_57_62:6; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; @@ -743,7 +3256,10 @@ union cvmx_ciu_intx_en1_w1s { uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_37_45:9; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -766,8 +3282,51 @@ union cvmx_ciu_intx_en1_w1s { uint64_t usb1:1; uint64_t uart2:1; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif } s; struct cvmx_ciu_intx_en1_w1s_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t nand:1; uint64_t mii1:1; @@ -775,16 +3334,107 @@ union cvmx_ciu_intx_en1_w1s { uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_ciu_intx_en1_w1s_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t wdog:12; +#else + uint64_t wdog:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_intx_en1_w1s_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t reserved_16_63:48; +#endif } cn58xx; + struct cvmx_ciu_intx_en1_w1s_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en1_w1s_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; uint64_t reserved_57_62:6; uint64_t dfm:1; @@ -818,13 +3468,193 @@ union cvmx_ciu_intx_en1_w1s { uint64_t mii1:1; uint64_t reserved_6_17:12; uint64_t wdog:6; +#else + uint64_t wdog:6; + uint64_t reserved_6_17:12; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_45:9; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_62:6; + uint64_t rst:1; +#endif } cn63xx; struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1; + struct cvmx_ciu_intx_en1_w1s_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en1_w1s_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en4_0 { uint64_t u64; struct cvmx_ciu_intx_en4_0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -847,8 +3677,33 @@ union cvmx_ciu_intx_en4_0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } s; struct cvmx_ciu_intx_en4_0_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t mpi:1; uint64_t pcm:1; @@ -868,8 +3723,30 @@ union cvmx_ciu_intx_en4_0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t reserved_47_47:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t reserved_59_63:5; +#endif } cn50xx; struct cvmx_ciu_intx_en4_0_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -892,9 +3769,34 @@ union cvmx_ciu_intx_en4_0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn52xx; struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1; struct cvmx_ciu_intx_en4_0_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -916,9 +3818,33 @@ union cvmx_ciu_intx_en4_0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn56xx; struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1; struct cvmx_ciu_intx_en4_0_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -934,21 +3860,189 @@ union cvmx_ciu_intx_en4_0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t reserved_56_63:8; +#endif } cn58xx; struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1; + struct cvmx_ciu_intx_en4_0_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en4_0_cn52xx cn63xx; struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1; + struct cvmx_ciu_intx_en4_0_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en4_0_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en4_0_w1c { uint64_t u64; struct cvmx_ciu_intx_en4_0_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; uint64_t powiq:1; uint64_t twsi2:1; - uint64_t reserved_57_58:2; + uint64_t mpi:1; + uint64_t pcm:1; uint64_t usb:1; uint64_t timer:4; uint64_t key_zero:1; @@ -964,8 +4058,33 @@ union cvmx_ciu_intx_en4_0_w1c { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } s; struct cvmx_ciu_intx_en4_0_w1c_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -988,9 +4107,80 @@ union cvmx_ciu_intx_en4_0_w1c { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn52xx; - struct cvmx_ciu_intx_en4_0_w1c_s cn56xx; + struct cvmx_ciu_intx_en4_0_w1c_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; + uint64_t usb:1; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn56xx; struct cvmx_ciu_intx_en4_0_w1c_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -1006,20 +4196,188 @@ union cvmx_ciu_intx_en4_0_w1c { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t reserved_56_63:8; +#endif } cn58xx; + struct cvmx_ciu_intx_en4_0_w1c_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx; struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1; + struct cvmx_ciu_intx_en4_0_w1c_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en4_0_w1c_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en4_0_w1s { uint64_t u64; struct cvmx_ciu_intx_en4_0_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; uint64_t powiq:1; uint64_t twsi2:1; - uint64_t reserved_57_58:2; + uint64_t mpi:1; + uint64_t pcm:1; uint64_t usb:1; uint64_t timer:4; uint64_t key_zero:1; @@ -1035,8 +4393,33 @@ union cvmx_ciu_intx_en4_0_w1s { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } s; struct cvmx_ciu_intx_en4_0_w1s_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1059,9 +4442,80 @@ union cvmx_ciu_intx_en4_0_w1s { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn52xx; - struct cvmx_ciu_intx_en4_0_w1s_s cn56xx; + struct cvmx_ciu_intx_en4_0_w1s_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t reserved_57_58:2; + uint64_t usb:1; + uint64_t timer:4; + uint64_t key_zero:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn56xx; struct cvmx_ciu_intx_en4_0_w1s_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -1077,16 +4531,186 @@ union cvmx_ciu_intx_en4_0_w1s { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t reserved_56_63:8; +#endif } cn58xx; + struct cvmx_ciu_intx_en4_0_w1s_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx; struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1; + struct cvmx_ciu_intx_en4_0_w1s_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en4_0_w1s_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t reserved_51_51:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t reserved_44_44:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t reserved_44_44:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en4_1 { uint64_t u64; struct cvmx_ciu_intx_en4_1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; - uint64_t reserved_57_62:6; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; @@ -1096,7 +4720,10 @@ union cvmx_ciu_intx_en4_1 { uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_37_45:9; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -1119,12 +4746,60 @@ union cvmx_ciu_intx_en4_1 { uint64_t usb1:1; uint64_t uart2:1; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif } s; struct cvmx_ciu_intx_en4_1_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t wdog:2; +#else + uint64_t wdog:2; + uint64_t reserved_2_63:62; +#endif } cn50xx; struct cvmx_ciu_intx_en4_1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t nand:1; uint64_t mii1:1; @@ -1132,26 +4807,126 @@ union cvmx_ciu_intx_en4_1 { uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_ciu_intx_en4_1_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t mii1:1; uint64_t usb1:1; uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t reserved_19_63:45; +#endif } cn52xxp1; struct cvmx_ciu_intx_en4_1_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t wdog:12; +#else + uint64_t wdog:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1; struct cvmx_ciu_intx_en4_1_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t reserved_16_63:48; +#endif } cn58xx; struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1; + struct cvmx_ciu_intx_en4_1_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en4_1_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; uint64_t reserved_57_62:6; uint64_t dfm:1; @@ -1185,15 +4960,198 @@ union cvmx_ciu_intx_en4_1 { uint64_t mii1:1; uint64_t reserved_6_17:12; uint64_t wdog:6; +#else + uint64_t wdog:6; + uint64_t reserved_6_17:12; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_45:9; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_62:6; + uint64_t rst:1; +#endif } cn63xx; struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1; + struct cvmx_ciu_intx_en4_1_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en4_1_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en4_1_w1c { uint64_t u64; struct cvmx_ciu_intx_en4_1_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; - uint64_t reserved_57_62:6; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; @@ -1203,7 +5161,10 @@ union cvmx_ciu_intx_en4_1_w1c { uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_37_45:9; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -1226,8 +5187,51 @@ union cvmx_ciu_intx_en4_1_w1c { uint64_t usb1:1; uint64_t uart2:1; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif } s; struct cvmx_ciu_intx_en4_1_w1c_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t nand:1; uint64_t mii1:1; @@ -1235,16 +5239,107 @@ union cvmx_ciu_intx_en4_1_w1c { uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_ciu_intx_en4_1_w1c_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t wdog:12; +#else + uint64_t wdog:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_intx_en4_1_w1c_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t reserved_16_63:48; +#endif } cn58xx; + struct cvmx_ciu_intx_en4_1_w1c_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en4_1_w1c_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; uint64_t reserved_57_62:6; uint64_t dfm:1; @@ -1278,15 +5373,198 @@ union cvmx_ciu_intx_en4_1_w1c { uint64_t mii1:1; uint64_t reserved_6_17:12; uint64_t wdog:6; +#else + uint64_t wdog:6; + uint64_t reserved_6_17:12; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_45:9; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_62:6; + uint64_t rst:1; +#endif } cn63xx; struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1; + struct cvmx_ciu_intx_en4_1_w1c_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en4_1_w1c_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_en4_1_w1s { uint64_t u64; struct cvmx_ciu_intx_en4_1_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; - uint64_t reserved_57_62:6; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; @@ -1296,7 +5574,10 @@ union cvmx_ciu_intx_en4_1_w1s { uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_37_45:9; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -1319,8 +5600,51 @@ union cvmx_ciu_intx_en4_1_w1s { uint64_t usb1:1; uint64_t uart2:1; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif } s; struct cvmx_ciu_intx_en4_1_w1s_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t nand:1; uint64_t mii1:1; @@ -1328,16 +5652,107 @@ union cvmx_ciu_intx_en4_1_w1s { uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_ciu_intx_en4_1_w1s_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t wdog:12; +#else + uint64_t wdog:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_intx_en4_1_w1s_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t reserved_16_63:48; +#endif } cn58xx; + struct cvmx_ciu_intx_en4_1_w1s_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; struct cvmx_ciu_intx_en4_1_w1s_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; uint64_t reserved_57_62:6; uint64_t dfm:1; @@ -1371,13 +5786,193 @@ union cvmx_ciu_intx_en4_1_w1s { uint64_t mii1:1; uint64_t reserved_6_17:12; uint64_t wdog:6; +#else + uint64_t wdog:6; + uint64_t reserved_6_17:12; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_45:9; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_62:6; + uint64_t rst:1; +#endif } cn63xx; struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1; + struct cvmx_ciu_intx_en4_1_w1s_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_en4_1_w1s_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_sum0 { uint64_t u64; struct cvmx_ciu_intx_sum0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1387,7 +5982,7 @@ union cvmx_ciu_intx_sum0 { uint64_t pcm:1; uint64_t usb:1; uint64_t timer:4; - uint64_t key_zero:1; + uint64_t reserved_51_51:1; uint64_t ipd_drp:1; uint64_t gmx_drp:2; uint64_t trace:1; @@ -1400,8 +5995,33 @@ union cvmx_ciu_intx_sum0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } s; struct cvmx_ciu_intx_sum0_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t mpi:1; uint64_t pcm:1; @@ -1421,8 +6041,30 @@ union cvmx_ciu_intx_sum0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t reserved_47_47:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t reserved_59_63:5; +#endif } cn30xx; struct cvmx_ciu_intx_sum0_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t mpi:1; uint64_t pcm:1; @@ -1442,8 +6084,30 @@ union cvmx_ciu_intx_sum0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t reserved_59_63:5; +#endif } cn31xx; struct cvmx_ciu_intx_sum0_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -1459,10 +6123,28 @@ union cvmx_ciu_intx_sum0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t reserved_56_63:8; +#endif } cn38xx; struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2; struct cvmx_ciu_intx_sum0_cn30xx cn50xx; struct cvmx_ciu_intx_sum0_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1485,9 +6167,34 @@ union cvmx_ciu_intx_sum0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn52xx; struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1; struct cvmx_ciu_intx_sum0_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1509,17 +6216,190 @@ union cvmx_ciu_intx_sum0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn56xx; struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1; struct cvmx_ciu_intx_sum0_cn38xx cn58xx; struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1; + struct cvmx_ciu_intx_sum0_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn61xx; struct cvmx_ciu_intx_sum0_cn52xx cn63xx; struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1; + struct cvmx_ciu_intx_sum0_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_sum0_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_intx_sum4 { uint64_t u64; struct cvmx_ciu_intx_sum4_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1529,7 +6409,7 @@ union cvmx_ciu_intx_sum4 { uint64_t pcm:1; uint64_t usb:1; uint64_t timer:4; - uint64_t key_zero:1; + uint64_t reserved_51_51:1; uint64_t ipd_drp:1; uint64_t gmx_drp:2; uint64_t trace:1; @@ -1542,8 +6422,33 @@ union cvmx_ciu_intx_sum4 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } s; struct cvmx_ciu_intx_sum4_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t mpi:1; uint64_t pcm:1; @@ -1563,8 +6468,30 @@ union cvmx_ciu_intx_sum4 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t reserved_47_47:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t reserved_59_63:5; +#endif } cn50xx; struct cvmx_ciu_intx_sum4_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1587,9 +6514,34 @@ union cvmx_ciu_intx_sum4 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn52xx; struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1; struct cvmx_ciu_intx_sum4_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1611,9 +6563,33 @@ union cvmx_ciu_intx_sum4 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif } cn56xx; struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1; struct cvmx_ciu_intx_sum4_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t timer:4; uint64_t key_zero:1; @@ -1629,15 +6605,232 @@ union cvmx_ciu_intx_sum4 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t key_zero:1; + uint64_t timer:4; + uint64_t reserved_56_63:8; +#endif } cn58xx; struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1; + struct cvmx_ciu_intx_sum4_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn61xx; struct cvmx_ciu_intx_sum4_cn52xx cn63xx; struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1; + struct cvmx_ciu_intx_sum4_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_intx_sum4_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_int33_sum0 { uint64_t u64; struct cvmx_ciu_int33_sum0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } s; + struct cvmx_ciu_int33_sum0_s cn61xx; + struct cvmx_ciu_int33_sum0_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bootdma:1; uint64_t mii:1; uint64_t ipdppthr:1; @@ -1660,29 +6853,202 @@ union cvmx_ciu_int33_sum0 { uint64_t mbox:2; uint64_t gpio:16; uint64_t workq:16; - } s; - struct cvmx_ciu_int33_sum0_s cn63xx; - struct cvmx_ciu_int33_sum0_s cn63xxp1; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t reserved_51_51:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_58:2; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn63xx; + struct cvmx_ciu_int33_sum0_cn63xx cn63xxp1; + struct cvmx_ciu_int33_sum0_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t mii:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t reserved_57_57:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t gmx_drp:2; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:2; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t reserved_57_57:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t mii:1; + uint64_t bootdma:1; +#endif + } cn66xx; + struct cvmx_ciu_int33_sum0_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bootdma:1; + uint64_t reserved_62_62:1; + uint64_t ipdppthr:1; + uint64_t powiq:1; + uint64_t twsi2:1; + uint64_t mpi:1; + uint64_t pcm:1; + uint64_t usb:1; + uint64_t timer:4; + uint64_t sum2:1; + uint64_t ipd_drp:1; + uint64_t reserved_49_49:1; + uint64_t gmx_drp:1; + uint64_t trace:1; + uint64_t rml:1; + uint64_t twsi:1; + uint64_t wdog_sum:1; + uint64_t pci_msi:4; + uint64_t pci_int:4; + uint64_t uart:2; + uint64_t mbox:2; + uint64_t gpio:16; + uint64_t workq:16; +#else + uint64_t workq:16; + uint64_t gpio:16; + uint64_t mbox:2; + uint64_t uart:2; + uint64_t pci_int:4; + uint64_t pci_msi:4; + uint64_t wdog_sum:1; + uint64_t twsi:1; + uint64_t rml:1; + uint64_t trace:1; + uint64_t gmx_drp:1; + uint64_t reserved_49_49:1; + uint64_t ipd_drp:1; + uint64_t sum2:1; + uint64_t timer:4; + uint64_t usb:1; + uint64_t pcm:1; + uint64_t mpi:1; + uint64_t twsi2:1; + uint64_t powiq:1; + uint64_t ipdppthr:1; + uint64_t reserved_62_62:1; + uint64_t bootdma:1; +#endif + } cnf71xx; }; union cvmx_ciu_int_dbg_sel { uint64_t u64; struct cvmx_ciu_int_dbg_sel_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_19_63:45; + uint64_t sel:3; + uint64_t reserved_10_15:6; + uint64_t irq:2; + uint64_t reserved_5_7:3; + uint64_t pp:5; +#else + uint64_t pp:5; + uint64_t reserved_5_7:3; + uint64_t irq:2; + uint64_t reserved_10_15:6; + uint64_t sel:3; + uint64_t reserved_19_63:45; +#endif + } s; + struct cvmx_ciu_int_dbg_sel_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_19_63:45; + uint64_t sel:3; + uint64_t reserved_10_15:6; + uint64_t irq:2; + uint64_t reserved_4_7:4; + uint64_t pp:4; +#else + uint64_t pp:4; + uint64_t reserved_4_7:4; + uint64_t irq:2; + uint64_t reserved_10_15:6; + uint64_t sel:3; + uint64_t reserved_19_63:45; +#endif + } cn61xx; + struct cvmx_ciu_int_dbg_sel_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t sel:3; uint64_t reserved_10_15:6; uint64_t irq:2; uint64_t reserved_3_7:5; uint64_t pp:3; - } s; - struct cvmx_ciu_int_dbg_sel_s cn63xx; +#else + uint64_t pp:3; + uint64_t reserved_3_7:5; + uint64_t irq:2; + uint64_t reserved_10_15:6; + uint64_t sel:3; + uint64_t reserved_19_63:45; +#endif + } cn63xx; + struct cvmx_ciu_int_dbg_sel_cn61xx cn66xx; + struct cvmx_ciu_int_dbg_sel_s cn68xx; + struct cvmx_ciu_int_dbg_sel_s cn68xxp1; + struct cvmx_ciu_int_dbg_sel_cn61xx cnf71xx; }; union cvmx_ciu_int_sum1 { uint64_t u64; struct cvmx_ciu_int_sum1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; - uint64_t reserved_57_62:6; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; uint64_t dfm:1; uint64_t reserved_53_55:3; uint64_t lmc0:1; @@ -1692,7 +7058,8 @@ union cvmx_ciu_int_sum1 { uint64_t pem0:1; uint64_t ptp:1; uint64_t agl:1; - uint64_t reserved_37_45:9; + uint64_t reserved_38_45:8; + uint64_t agx1:1; uint64_t agx0:1; uint64_t dpi:1; uint64_t sli:1; @@ -1715,22 +7082,78 @@ union cvmx_ciu_int_sum1 { uint64_t usb1:1; uint64_t uart2:1; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif } s; struct cvmx_ciu_int_sum1_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t wdog:1; +#else + uint64_t wdog:1; + uint64_t reserved_1_63:63; +#endif } cn30xx; struct cvmx_ciu_int_sum1_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t wdog:2; +#else + uint64_t wdog:2; + uint64_t reserved_2_63:62; +#endif } cn31xx; struct cvmx_ciu_int_sum1_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t wdog:16; +#else + uint64_t wdog:16; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_ciu_int_sum1_cn38xx cn38xxp2; struct cvmx_ciu_int_sum1_cn31xx cn50xx; struct cvmx_ciu_int_sum1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t nand:1; uint64_t mii1:1; @@ -1738,23 +7161,114 @@ union cvmx_ciu_int_sum1 { uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_ciu_int_sum1_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t mii1:1; uint64_t usb1:1; uint64_t uart2:1; uint64_t reserved_4_15:12; uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_15:12; + uint64_t uart2:1; + uint64_t usb1:1; + uint64_t mii1:1; + uint64_t reserved_19_63:45; +#endif } cn52xxp1; struct cvmx_ciu_int_sum1_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t wdog:12; +#else + uint64_t wdog:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_int_sum1_cn56xx cn56xxp1; struct cvmx_ciu_int_sum1_cn38xx cn58xx; struct cvmx_ciu_int_sum1_cn38xx cn58xxp1; + struct cvmx_ciu_int_sum1_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; struct cvmx_ciu_int_sum1_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rst:1; uint64_t reserved_57_62:6; uint64_t dfm:1; @@ -1788,15 +7302,195 @@ union cvmx_ciu_int_sum1 { uint64_t mii1:1; uint64_t reserved_6_17:12; uint64_t wdog:6; +#else + uint64_t wdog:6; + uint64_t reserved_6_17:12; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_45:9; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t srio1:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_62:6; + uint64_t rst:1; +#endif } cn63xx; struct cvmx_ciu_int_sum1_cn63xx cn63xxp1; + struct cvmx_ciu_int_sum1_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_int_sum1_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_37_46:10; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_46:10; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; }; union cvmx_ciu_mbox_clrx { uint64_t u64; struct cvmx_ciu_mbox_clrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bits:32; +#else + uint64_t bits:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_ciu_mbox_clrx_s cn30xx; struct cvmx_ciu_mbox_clrx_s cn31xx; @@ -1809,15 +7503,25 @@ union cvmx_ciu_mbox_clrx { struct cvmx_ciu_mbox_clrx_s cn56xxp1; struct cvmx_ciu_mbox_clrx_s cn58xx; struct cvmx_ciu_mbox_clrx_s cn58xxp1; + struct cvmx_ciu_mbox_clrx_s cn61xx; struct cvmx_ciu_mbox_clrx_s cn63xx; struct cvmx_ciu_mbox_clrx_s cn63xxp1; + struct cvmx_ciu_mbox_clrx_s cn66xx; + struct cvmx_ciu_mbox_clrx_s cn68xx; + struct cvmx_ciu_mbox_clrx_s cn68xxp1; + struct cvmx_ciu_mbox_clrx_s cnf71xx; }; union cvmx_ciu_mbox_setx { uint64_t u64; struct cvmx_ciu_mbox_setx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bits:32; +#else + uint64_t bits:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_ciu_mbox_setx_s cn30xx; struct cvmx_ciu_mbox_setx_s cn31xx; @@ -1830,51 +7534,112 @@ union cvmx_ciu_mbox_setx { struct cvmx_ciu_mbox_setx_s cn56xxp1; struct cvmx_ciu_mbox_setx_s cn58xx; struct cvmx_ciu_mbox_setx_s cn58xxp1; + struct cvmx_ciu_mbox_setx_s cn61xx; struct cvmx_ciu_mbox_setx_s cn63xx; struct cvmx_ciu_mbox_setx_s cn63xxp1; + struct cvmx_ciu_mbox_setx_s cn66xx; + struct cvmx_ciu_mbox_setx_s cn68xx; + struct cvmx_ciu_mbox_setx_s cn68xxp1; + struct cvmx_ciu_mbox_setx_s cnf71xx; }; union cvmx_ciu_nmi { uint64_t u64; struct cvmx_ciu_nmi_s { - uint64_t reserved_16_63:48; - uint64_t nmi:16; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t nmi:32; +#else + uint64_t nmi:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_ciu_nmi_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t nmi:1; +#else + uint64_t nmi:1; + uint64_t reserved_1_63:63; +#endif } cn30xx; struct cvmx_ciu_nmi_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t nmi:2; +#else + uint64_t nmi:2; + uint64_t reserved_2_63:62; +#endif } cn31xx; - struct cvmx_ciu_nmi_s cn38xx; - struct cvmx_ciu_nmi_s cn38xxp2; + struct cvmx_ciu_nmi_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t nmi:16; +#else + uint64_t nmi:16; + uint64_t reserved_16_63:48; +#endif + } cn38xx; + struct cvmx_ciu_nmi_cn38xx cn38xxp2; struct cvmx_ciu_nmi_cn31xx cn50xx; struct cvmx_ciu_nmi_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t nmi:4; +#else + uint64_t nmi:4; + uint64_t reserved_4_63:60; +#endif } cn52xx; struct cvmx_ciu_nmi_cn52xx cn52xxp1; struct cvmx_ciu_nmi_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t nmi:12; +#else + uint64_t nmi:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_nmi_cn56xx cn56xxp1; - struct cvmx_ciu_nmi_s cn58xx; - struct cvmx_ciu_nmi_s cn58xxp1; + struct cvmx_ciu_nmi_cn38xx cn58xx; + struct cvmx_ciu_nmi_cn38xx cn58xxp1; + struct cvmx_ciu_nmi_cn52xx cn61xx; struct cvmx_ciu_nmi_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t nmi:6; +#else + uint64_t nmi:6; + uint64_t reserved_6_63:58; +#endif } cn63xx; struct cvmx_ciu_nmi_cn63xx cn63xxp1; + struct cvmx_ciu_nmi_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t nmi:10; +#else + uint64_t nmi:10; + uint64_t reserved_10_63:54; +#endif + } cn66xx; + struct cvmx_ciu_nmi_s cn68xx; + struct cvmx_ciu_nmi_s cn68xxp1; + struct cvmx_ciu_nmi_cn52xx cnf71xx; }; union cvmx_ciu_pci_inta { uint64_t u64; struct cvmx_ciu_pci_inta_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t intr:2; +#else + uint64_t intr:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_ciu_pci_inta_s cn30xx; struct cvmx_ciu_pci_inta_s cn31xx; @@ -1887,50 +7652,125 @@ union cvmx_ciu_pci_inta { struct cvmx_ciu_pci_inta_s cn56xxp1; struct cvmx_ciu_pci_inta_s cn58xx; struct cvmx_ciu_pci_inta_s cn58xxp1; + struct cvmx_ciu_pci_inta_s cn61xx; struct cvmx_ciu_pci_inta_s cn63xx; struct cvmx_ciu_pci_inta_s cn63xxp1; + struct cvmx_ciu_pci_inta_s cn66xx; + struct cvmx_ciu_pci_inta_s cn68xx; + struct cvmx_ciu_pci_inta_s cn68xxp1; + struct cvmx_ciu_pci_inta_s cnf71xx; +}; + +union cvmx_ciu_pp_bist_stat { + uint64_t u64; + struct cvmx_ciu_pp_bist_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t pp_bist:32; +#else + uint64_t pp_bist:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu_pp_bist_stat_s cn68xx; + struct cvmx_ciu_pp_bist_stat_s cn68xxp1; }; union cvmx_ciu_pp_dbg { uint64_t u64; struct cvmx_ciu_pp_dbg_s { - uint64_t reserved_16_63:48; - uint64_t ppdbg:16; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t ppdbg:32; +#else + uint64_t ppdbg:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_ciu_pp_dbg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t ppdbg:1; +#else + uint64_t ppdbg:1; + uint64_t reserved_1_63:63; +#endif } cn30xx; struct cvmx_ciu_pp_dbg_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t ppdbg:2; +#else + uint64_t ppdbg:2; + uint64_t reserved_2_63:62; +#endif } cn31xx; - struct cvmx_ciu_pp_dbg_s cn38xx; - struct cvmx_ciu_pp_dbg_s cn38xxp2; + struct cvmx_ciu_pp_dbg_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t ppdbg:16; +#else + uint64_t ppdbg:16; + uint64_t reserved_16_63:48; +#endif + } cn38xx; + struct cvmx_ciu_pp_dbg_cn38xx cn38xxp2; struct cvmx_ciu_pp_dbg_cn31xx cn50xx; struct cvmx_ciu_pp_dbg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t ppdbg:4; +#else + uint64_t ppdbg:4; + uint64_t reserved_4_63:60; +#endif } cn52xx; struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1; struct cvmx_ciu_pp_dbg_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t ppdbg:12; +#else + uint64_t ppdbg:12; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1; - struct cvmx_ciu_pp_dbg_s cn58xx; - struct cvmx_ciu_pp_dbg_s cn58xxp1; + struct cvmx_ciu_pp_dbg_cn38xx cn58xx; + struct cvmx_ciu_pp_dbg_cn38xx cn58xxp1; + struct cvmx_ciu_pp_dbg_cn52xx cn61xx; struct cvmx_ciu_pp_dbg_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t ppdbg:6; +#else + uint64_t ppdbg:6; + uint64_t reserved_6_63:58; +#endif } cn63xx; struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1; + struct cvmx_ciu_pp_dbg_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t ppdbg:10; +#else + uint64_t ppdbg:10; + uint64_t reserved_10_63:54; +#endif + } cn66xx; + struct cvmx_ciu_pp_dbg_s cn68xx; + struct cvmx_ciu_pp_dbg_s cn68xxp1; + struct cvmx_ciu_pp_dbg_cn52xx cnf71xx; }; union cvmx_ciu_pp_pokex { uint64_t u64; struct cvmx_ciu_pp_pokex_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t poke:64; +#else + uint64_t poke:64; +#endif } s; struct cvmx_ciu_pp_pokex_s cn30xx; struct cvmx_ciu_pp_pokex_s cn31xx; @@ -1943,54 +7783,120 @@ union cvmx_ciu_pp_pokex { struct cvmx_ciu_pp_pokex_s cn56xxp1; struct cvmx_ciu_pp_pokex_s cn58xx; struct cvmx_ciu_pp_pokex_s cn58xxp1; + struct cvmx_ciu_pp_pokex_s cn61xx; struct cvmx_ciu_pp_pokex_s cn63xx; struct cvmx_ciu_pp_pokex_s cn63xxp1; + struct cvmx_ciu_pp_pokex_s cn66xx; + struct cvmx_ciu_pp_pokex_s cn68xx; + struct cvmx_ciu_pp_pokex_s cn68xxp1; + struct cvmx_ciu_pp_pokex_s cnf71xx; }; union cvmx_ciu_pp_rst { uint64_t u64; struct cvmx_ciu_pp_rst_s { - uint64_t reserved_16_63:48; - uint64_t rst:15; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t rst:31; + uint64_t rst0:1; +#else uint64_t rst0:1; + uint64_t rst:31; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_ciu_pp_rst_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rst0:1; +#else + uint64_t rst0:1; + uint64_t reserved_1_63:63; +#endif } cn30xx; struct cvmx_ciu_pp_rst_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t rst:1; uint64_t rst0:1; +#else + uint64_t rst0:1; + uint64_t rst:1; + uint64_t reserved_2_63:62; +#endif } cn31xx; - struct cvmx_ciu_pp_rst_s cn38xx; - struct cvmx_ciu_pp_rst_s cn38xxp2; + struct cvmx_ciu_pp_rst_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t rst:15; + uint64_t rst0:1; +#else + uint64_t rst0:1; + uint64_t rst:15; + uint64_t reserved_16_63:48; +#endif + } cn38xx; + struct cvmx_ciu_pp_rst_cn38xx cn38xxp2; struct cvmx_ciu_pp_rst_cn31xx cn50xx; struct cvmx_ciu_pp_rst_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t rst:3; uint64_t rst0:1; +#else + uint64_t rst0:1; + uint64_t rst:3; + uint64_t reserved_4_63:60; +#endif } cn52xx; struct cvmx_ciu_pp_rst_cn52xx cn52xxp1; struct cvmx_ciu_pp_rst_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t rst:11; uint64_t rst0:1; +#else + uint64_t rst0:1; + uint64_t rst:11; + uint64_t reserved_12_63:52; +#endif } cn56xx; struct cvmx_ciu_pp_rst_cn56xx cn56xxp1; - struct cvmx_ciu_pp_rst_s cn58xx; - struct cvmx_ciu_pp_rst_s cn58xxp1; + struct cvmx_ciu_pp_rst_cn38xx cn58xx; + struct cvmx_ciu_pp_rst_cn38xx cn58xxp1; + struct cvmx_ciu_pp_rst_cn52xx cn61xx; struct cvmx_ciu_pp_rst_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t rst:5; uint64_t rst0:1; +#else + uint64_t rst0:1; + uint64_t rst:5; + uint64_t reserved_6_63:58; +#endif } cn63xx; struct cvmx_ciu_pp_rst_cn63xx cn63xxp1; + struct cvmx_ciu_pp_rst_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t rst:9; + uint64_t rst0:1; +#else + uint64_t rst0:1; + uint64_t rst:9; + uint64_t reserved_10_63:54; +#endif + } cn66xx; + struct cvmx_ciu_pp_rst_s cn68xx; + struct cvmx_ciu_pp_rst_s cn68xxp1; + struct cvmx_ciu_pp_rst_cn52xx cnf71xx; }; union cvmx_ciu_qlm0 { uint64_t u64; struct cvmx_ciu_qlm0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t g2bypass:1; uint64_t reserved_53_62:10; uint64_t g2deemph:5; @@ -2004,9 +7910,26 @@ union cvmx_ciu_qlm0 { uint64_t txmargin:5; uint64_t reserved_4_7:4; uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:5; + uint64_t reserved_21_30:10; + uint64_t txbypass:1; + uint64_t reserved_32_39:8; + uint64_t g2margin:5; + uint64_t reserved_45_47:3; + uint64_t g2deemph:5; + uint64_t reserved_53_62:10; + uint64_t g2bypass:1; +#endif } s; + struct cvmx_ciu_qlm0_s cn61xx; struct cvmx_ciu_qlm0_s cn63xx; struct cvmx_ciu_qlm0_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t txbypass:1; uint64_t reserved_20_30:11; @@ -2015,12 +7938,47 @@ union cvmx_ciu_qlm0 { uint64_t txmargin:5; uint64_t reserved_4_7:4; uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:4; + uint64_t reserved_20_30:11; + uint64_t txbypass:1; + uint64_t reserved_32_63:32; +#endif } cn63xxp1; + struct cvmx_ciu_qlm0_s cn66xx; + struct cvmx_ciu_qlm0_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t txbypass:1; + uint64_t reserved_21_30:10; + uint64_t txdeemph:5; + uint64_t reserved_13_15:3; + uint64_t txmargin:5; + uint64_t reserved_4_7:4; + uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:5; + uint64_t reserved_21_30:10; + uint64_t txbypass:1; + uint64_t reserved_32_63:32; +#endif + } cn68xx; + struct cvmx_ciu_qlm0_cn68xx cn68xxp1; + struct cvmx_ciu_qlm0_s cnf71xx; }; union cvmx_ciu_qlm1 { uint64_t u64; struct cvmx_ciu_qlm1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t g2bypass:1; uint64_t reserved_53_62:10; uint64_t g2deemph:5; @@ -2034,9 +7992,26 @@ union cvmx_ciu_qlm1 { uint64_t txmargin:5; uint64_t reserved_4_7:4; uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:5; + uint64_t reserved_21_30:10; + uint64_t txbypass:1; + uint64_t reserved_32_39:8; + uint64_t g2margin:5; + uint64_t reserved_45_47:3; + uint64_t g2deemph:5; + uint64_t reserved_53_62:10; + uint64_t g2bypass:1; +#endif } s; + struct cvmx_ciu_qlm1_s cn61xx; struct cvmx_ciu_qlm1_s cn63xx; struct cvmx_ciu_qlm1_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t txbypass:1; uint64_t reserved_20_30:11; @@ -2045,13 +8020,33 @@ union cvmx_ciu_qlm1 { uint64_t txmargin:5; uint64_t reserved_4_7:4; uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:4; + uint64_t reserved_20_30:11; + uint64_t txbypass:1; + uint64_t reserved_32_63:32; +#endif } cn63xxp1; + struct cvmx_ciu_qlm1_s cn66xx; + struct cvmx_ciu_qlm1_s cn68xx; + struct cvmx_ciu_qlm1_s cn68xxp1; + struct cvmx_ciu_qlm1_s cnf71xx; }; union cvmx_ciu_qlm2 { uint64_t u64; struct cvmx_ciu_qlm2_s { - uint64_t reserved_32_63:32; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t g2bypass:1; + uint64_t reserved_53_62:10; + uint64_t g2deemph:5; + uint64_t reserved_45_47:3; + uint64_t g2margin:5; + uint64_t reserved_32_39:8; uint64_t txbypass:1; uint64_t reserved_21_30:10; uint64_t txdeemph:5; @@ -2059,9 +8054,46 @@ union cvmx_ciu_qlm2 { uint64_t txmargin:5; uint64_t reserved_4_7:4; uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:5; + uint64_t reserved_21_30:10; + uint64_t txbypass:1; + uint64_t reserved_32_39:8; + uint64_t g2margin:5; + uint64_t reserved_45_47:3; + uint64_t g2deemph:5; + uint64_t reserved_53_62:10; + uint64_t g2bypass:1; +#endif } s; - struct cvmx_ciu_qlm2_s cn63xx; + struct cvmx_ciu_qlm2_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t txbypass:1; + uint64_t reserved_21_30:10; + uint64_t txdeemph:5; + uint64_t reserved_13_15:3; + uint64_t txmargin:5; + uint64_t reserved_4_7:4; + uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:5; + uint64_t reserved_21_30:10; + uint64_t txbypass:1; + uint64_t reserved_32_63:32; +#endif + } cn61xx; + struct cvmx_ciu_qlm2_cn61xx cn63xx; struct cvmx_ciu_qlm2_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t txbypass:1; uint64_t reserved_20_30:11; @@ -2070,18 +8102,116 @@ union cvmx_ciu_qlm2 { uint64_t txmargin:5; uint64_t reserved_4_7:4; uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:4; + uint64_t reserved_20_30:11; + uint64_t txbypass:1; + uint64_t reserved_32_63:32; +#endif } cn63xxp1; + struct cvmx_ciu_qlm2_cn61xx cn66xx; + struct cvmx_ciu_qlm2_s cn68xx; + struct cvmx_ciu_qlm2_s cn68xxp1; + struct cvmx_ciu_qlm2_cn61xx cnf71xx; +}; + +union cvmx_ciu_qlm3 { + uint64_t u64; + struct cvmx_ciu_qlm3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t g2bypass:1; + uint64_t reserved_53_62:10; + uint64_t g2deemph:5; + uint64_t reserved_45_47:3; + uint64_t g2margin:5; + uint64_t reserved_32_39:8; + uint64_t txbypass:1; + uint64_t reserved_21_30:10; + uint64_t txdeemph:5; + uint64_t reserved_13_15:3; + uint64_t txmargin:5; + uint64_t reserved_4_7:4; + uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:5; + uint64_t reserved_21_30:10; + uint64_t txbypass:1; + uint64_t reserved_32_39:8; + uint64_t g2margin:5; + uint64_t reserved_45_47:3; + uint64_t g2deemph:5; + uint64_t reserved_53_62:10; + uint64_t g2bypass:1; +#endif + } s; + struct cvmx_ciu_qlm3_s cn68xx; + struct cvmx_ciu_qlm3_s cn68xxp1; +}; + +union cvmx_ciu_qlm4 { + uint64_t u64; + struct cvmx_ciu_qlm4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t g2bypass:1; + uint64_t reserved_53_62:10; + uint64_t g2deemph:5; + uint64_t reserved_45_47:3; + uint64_t g2margin:5; + uint64_t reserved_32_39:8; + uint64_t txbypass:1; + uint64_t reserved_21_30:10; + uint64_t txdeemph:5; + uint64_t reserved_13_15:3; + uint64_t txmargin:5; + uint64_t reserved_4_7:4; + uint64_t lane_en:4; +#else + uint64_t lane_en:4; + uint64_t reserved_4_7:4; + uint64_t txmargin:5; + uint64_t reserved_13_15:3; + uint64_t txdeemph:5; + uint64_t reserved_21_30:10; + uint64_t txbypass:1; + uint64_t reserved_32_39:8; + uint64_t g2margin:5; + uint64_t reserved_45_47:3; + uint64_t g2deemph:5; + uint64_t reserved_53_62:10; + uint64_t g2bypass:1; +#endif + } s; + struct cvmx_ciu_qlm4_s cn68xx; + struct cvmx_ciu_qlm4_s cn68xxp1; }; union cvmx_ciu_qlm_dcok { uint64_t u64; struct cvmx_ciu_qlm_dcok_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t qlm_dcok:4; +#else + uint64_t qlm_dcok:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_ciu_qlm_dcok_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t qlm_dcok:2; +#else + uint64_t qlm_dcok:2; + uint64_t reserved_2_63:62; +#endif } cn52xx; struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1; struct cvmx_ciu_qlm_dcok_s cn56xx; @@ -2091,47 +8221,108 @@ union cvmx_ciu_qlm_dcok { union cvmx_ciu_qlm_jtgc { uint64_t u64; struct cvmx_ciu_qlm_jtgc_s { - uint64_t reserved_11_63:53; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_17_63:47; + uint64_t bypass_ext:1; + uint64_t reserved_11_15:5; uint64_t clk_div:3; - uint64_t reserved_6_7:2; - uint64_t mux_sel:2; + uint64_t reserved_7_7:1; + uint64_t mux_sel:3; uint64_t bypass:4; +#else + uint64_t bypass:4; + uint64_t mux_sel:3; + uint64_t reserved_7_7:1; + uint64_t clk_div:3; + uint64_t reserved_11_15:5; + uint64_t bypass_ext:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_ciu_qlm_jtgc_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t clk_div:3; uint64_t reserved_5_7:3; uint64_t mux_sel:1; uint64_t reserved_2_3:2; uint64_t bypass:2; +#else + uint64_t bypass:2; + uint64_t reserved_2_3:2; + uint64_t mux_sel:1; + uint64_t reserved_5_7:3; + uint64_t clk_div:3; + uint64_t reserved_11_63:53; +#endif } cn52xx; struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1; - struct cvmx_ciu_qlm_jtgc_s cn56xx; - struct cvmx_ciu_qlm_jtgc_s cn56xxp1; - struct cvmx_ciu_qlm_jtgc_cn63xx { + struct cvmx_ciu_qlm_jtgc_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t clk_div:3; + uint64_t reserved_6_7:2; + uint64_t mux_sel:2; + uint64_t bypass:4; +#else + uint64_t bypass:4; + uint64_t mux_sel:2; + uint64_t reserved_6_7:2; + uint64_t clk_div:3; + uint64_t reserved_11_63:53; +#endif + } cn56xx; + struct cvmx_ciu_qlm_jtgc_cn56xx cn56xxp1; + struct cvmx_ciu_qlm_jtgc_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t clk_div:3; uint64_t reserved_6_7:2; uint64_t mux_sel:2; uint64_t reserved_3_3:1; uint64_t bypass:3; - } cn63xx; - struct cvmx_ciu_qlm_jtgc_cn63xx cn63xxp1; +#else + uint64_t bypass:3; + uint64_t reserved_3_3:1; + uint64_t mux_sel:2; + uint64_t reserved_6_7:2; + uint64_t clk_div:3; + uint64_t reserved_11_63:53; +#endif + } cn61xx; + struct cvmx_ciu_qlm_jtgc_cn61xx cn63xx; + struct cvmx_ciu_qlm_jtgc_cn61xx cn63xxp1; + struct cvmx_ciu_qlm_jtgc_cn61xx cn66xx; + struct cvmx_ciu_qlm_jtgc_s cn68xx; + struct cvmx_ciu_qlm_jtgc_s cn68xxp1; + struct cvmx_ciu_qlm_jtgc_cn61xx cnf71xx; }; union cvmx_ciu_qlm_jtgd { uint64_t u64; struct cvmx_ciu_qlm_jtgd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t capture:1; uint64_t shift:1; uint64_t update:1; - uint64_t reserved_44_60:17; - uint64_t select:4; + uint64_t reserved_45_60:16; + uint64_t select:5; uint64_t reserved_37_39:3; uint64_t shft_cnt:5; uint64_t shft_reg:32; +#else + uint64_t shft_reg:32; + uint64_t shft_cnt:5; + uint64_t reserved_37_39:3; + uint64_t select:5; + uint64_t reserved_45_60:16; + uint64_t update:1; + uint64_t shift:1; + uint64_t capture:1; +#endif } s; struct cvmx_ciu_qlm_jtgd_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t capture:1; uint64_t shift:1; uint64_t update:1; @@ -2140,18 +8331,58 @@ union cvmx_ciu_qlm_jtgd { uint64_t reserved_37_39:3; uint64_t shft_cnt:5; uint64_t shft_reg:32; +#else + uint64_t shft_reg:32; + uint64_t shft_cnt:5; + uint64_t reserved_37_39:3; + uint64_t select:2; + uint64_t reserved_42_60:19; + uint64_t update:1; + uint64_t shift:1; + uint64_t capture:1; +#endif } cn52xx; struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1; - struct cvmx_ciu_qlm_jtgd_s cn56xx; + struct cvmx_ciu_qlm_jtgd_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t capture:1; + uint64_t shift:1; + uint64_t update:1; + uint64_t reserved_44_60:17; + uint64_t select:4; + uint64_t reserved_37_39:3; + uint64_t shft_cnt:5; + uint64_t shft_reg:32; +#else + uint64_t shft_reg:32; + uint64_t shft_cnt:5; + uint64_t reserved_37_39:3; + uint64_t select:4; + uint64_t reserved_44_60:17; + uint64_t update:1; + uint64_t shift:1; + uint64_t capture:1; +#endif + } cn56xx; struct cvmx_ciu_qlm_jtgd_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t capture:1; uint64_t shift:1; uint64_t update:1; uint64_t reserved_37_60:24; uint64_t shft_cnt:5; uint64_t shft_reg:32; +#else + uint64_t shft_reg:32; + uint64_t shft_cnt:5; + uint64_t reserved_37_60:24; + uint64_t update:1; + uint64_t shift:1; + uint64_t capture:1; +#endif } cn56xxp1; - struct cvmx_ciu_qlm_jtgd_cn63xx { + struct cvmx_ciu_qlm_jtgd_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t capture:1; uint64_t shift:1; uint64_t update:1; @@ -2160,15 +8391,35 @@ union cvmx_ciu_qlm_jtgd { uint64_t reserved_37_39:3; uint64_t shft_cnt:5; uint64_t shft_reg:32; - } cn63xx; - struct cvmx_ciu_qlm_jtgd_cn63xx cn63xxp1; +#else + uint64_t shft_reg:32; + uint64_t shft_cnt:5; + uint64_t reserved_37_39:3; + uint64_t select:3; + uint64_t reserved_43_60:18; + uint64_t update:1; + uint64_t shift:1; + uint64_t capture:1; +#endif + } cn61xx; + struct cvmx_ciu_qlm_jtgd_cn61xx cn63xx; + struct cvmx_ciu_qlm_jtgd_cn61xx cn63xxp1; + struct cvmx_ciu_qlm_jtgd_cn61xx cn66xx; + struct cvmx_ciu_qlm_jtgd_s cn68xx; + struct cvmx_ciu_qlm_jtgd_s cn68xxp1; + struct cvmx_ciu_qlm_jtgd_cn61xx cnf71xx; }; union cvmx_ciu_soft_bist { uint64_t u64; struct cvmx_ciu_soft_bist_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t soft_bist:1; +#else + uint64_t soft_bist:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_ciu_soft_bist_s cn30xx; struct cvmx_ciu_soft_bist_s cn31xx; @@ -2181,17 +8432,29 @@ union cvmx_ciu_soft_bist { struct cvmx_ciu_soft_bist_s cn56xxp1; struct cvmx_ciu_soft_bist_s cn58xx; struct cvmx_ciu_soft_bist_s cn58xxp1; + struct cvmx_ciu_soft_bist_s cn61xx; struct cvmx_ciu_soft_bist_s cn63xx; struct cvmx_ciu_soft_bist_s cn63xxp1; + struct cvmx_ciu_soft_bist_s cn66xx; + struct cvmx_ciu_soft_bist_s cn68xx; + struct cvmx_ciu_soft_bist_s cn68xxp1; + struct cvmx_ciu_soft_bist_s cnf71xx; }; union cvmx_ciu_soft_prst { uint64_t u64; struct cvmx_ciu_soft_prst_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t host64:1; uint64_t npi:1; uint64_t soft_prst:1; +#else + uint64_t soft_prst:1; + uint64_t npi:1; + uint64_t host64:1; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_ciu_soft_prst_s cn30xx; struct cvmx_ciu_soft_prst_s cn31xx; @@ -2199,37 +8462,90 @@ union cvmx_ciu_soft_prst { struct cvmx_ciu_soft_prst_s cn38xxp2; struct cvmx_ciu_soft_prst_s cn50xx; struct cvmx_ciu_soft_prst_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t soft_prst:1; +#else + uint64_t soft_prst:1; + uint64_t reserved_1_63:63; +#endif } cn52xx; struct cvmx_ciu_soft_prst_cn52xx cn52xxp1; struct cvmx_ciu_soft_prst_cn52xx cn56xx; struct cvmx_ciu_soft_prst_cn52xx cn56xxp1; struct cvmx_ciu_soft_prst_s cn58xx; struct cvmx_ciu_soft_prst_s cn58xxp1; + struct cvmx_ciu_soft_prst_cn52xx cn61xx; struct cvmx_ciu_soft_prst_cn52xx cn63xx; struct cvmx_ciu_soft_prst_cn52xx cn63xxp1; + struct cvmx_ciu_soft_prst_cn52xx cn66xx; + struct cvmx_ciu_soft_prst_cn52xx cn68xx; + struct cvmx_ciu_soft_prst_cn52xx cn68xxp1; + struct cvmx_ciu_soft_prst_cn52xx cnf71xx; }; union cvmx_ciu_soft_prst1 { uint64_t u64; struct cvmx_ciu_soft_prst1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t soft_prst:1; +#else + uint64_t soft_prst:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_ciu_soft_prst1_s cn52xx; struct cvmx_ciu_soft_prst1_s cn52xxp1; struct cvmx_ciu_soft_prst1_s cn56xx; struct cvmx_ciu_soft_prst1_s cn56xxp1; + struct cvmx_ciu_soft_prst1_s cn61xx; struct cvmx_ciu_soft_prst1_s cn63xx; struct cvmx_ciu_soft_prst1_s cn63xxp1; + struct cvmx_ciu_soft_prst1_s cn66xx; + struct cvmx_ciu_soft_prst1_s cn68xx; + struct cvmx_ciu_soft_prst1_s cn68xxp1; + struct cvmx_ciu_soft_prst1_s cnf71xx; +}; + +union cvmx_ciu_soft_prst2 { + uint64_t u64; + struct cvmx_ciu_soft_prst2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t soft_prst:1; +#else + uint64_t soft_prst:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu_soft_prst2_s cn66xx; +}; + +union cvmx_ciu_soft_prst3 { + uint64_t u64; + struct cvmx_ciu_soft_prst3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t soft_prst:1; +#else + uint64_t soft_prst:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu_soft_prst3_s cn66xx; }; union cvmx_ciu_soft_rst { uint64_t u64; struct cvmx_ciu_soft_rst_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t soft_rst:1; +#else + uint64_t soft_rst:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_ciu_soft_rst_s cn30xx; struct cvmx_ciu_soft_rst_s cn31xx; @@ -2242,16 +8558,1371 @@ union cvmx_ciu_soft_rst { struct cvmx_ciu_soft_rst_s cn56xxp1; struct cvmx_ciu_soft_rst_s cn58xx; struct cvmx_ciu_soft_rst_s cn58xxp1; + struct cvmx_ciu_soft_rst_s cn61xx; struct cvmx_ciu_soft_rst_s cn63xx; struct cvmx_ciu_soft_rst_s cn63xxp1; + struct cvmx_ciu_soft_rst_s cn66xx; + struct cvmx_ciu_soft_rst_s cn68xx; + struct cvmx_ciu_soft_rst_s cn68xxp1; + struct cvmx_ciu_soft_rst_s cnf71xx; +}; + +union cvmx_ciu_sum1_iox_int { + uint64_t u64; + struct cvmx_ciu_sum1_iox_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu_sum1_iox_int_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; + struct cvmx_ciu_sum1_iox_int_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_sum1_iox_int_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; +}; + +union cvmx_ciu_sum1_ppx_ip2 { + uint64_t u64; + struct cvmx_ciu_sum1_ppx_ip2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu_sum1_ppx_ip2_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; + struct cvmx_ciu_sum1_ppx_ip2_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_sum1_ppx_ip2_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; +}; + +union cvmx_ciu_sum1_ppx_ip3 { + uint64_t u64; + struct cvmx_ciu_sum1_ppx_ip3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu_sum1_ppx_ip3_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; + struct cvmx_ciu_sum1_ppx_ip3_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_sum1_ppx_ip3_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; +}; + +union cvmx_ciu_sum1_ppx_ip4 { + uint64_t u64; + struct cvmx_ciu_sum1_ppx_ip4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu_sum1_ppx_ip4_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_41_45:5; + uint64_t dpi_dma:1; + uint64_t reserved_38_39:2; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_4_17:14; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_17:14; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_39:2; + uint64_t dpi_dma:1; + uint64_t reserved_41_45:5; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cn61xx; + struct cvmx_ciu_sum1_ppx_ip4_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_62_62:1; + uint64_t srio3:1; + uint64_t srio2:1; + uint64_t reserved_57_59:3; + uint64_t dfm:1; + uint64_t reserved_53_55:3; + uint64_t lmc0:1; + uint64_t reserved_51_51:1; + uint64_t srio0:1; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t agl:1; + uint64_t reserved_38_45:8; + uint64_t agx1:1; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t dfa:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t zip:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t mii1:1; + uint64_t reserved_10_17:8; + uint64_t wdog:10; +#else + uint64_t wdog:10; + uint64_t reserved_10_17:8; + uint64_t mii1:1; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t zip:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t dfa:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t agx1:1; + uint64_t reserved_38_45:8; + uint64_t agl:1; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t srio0:1; + uint64_t reserved_51_51:1; + uint64_t lmc0:1; + uint64_t reserved_53_55:3; + uint64_t dfm:1; + uint64_t reserved_57_59:3; + uint64_t srio2:1; + uint64_t srio3:1; + uint64_t reserved_62_62:1; + uint64_t rst:1; +#endif + } cn66xx; + struct cvmx_ciu_sum1_ppx_ip4_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_53_62:10; + uint64_t lmc0:1; + uint64_t reserved_50_51:2; + uint64_t pem1:1; + uint64_t pem0:1; + uint64_t ptp:1; + uint64_t reserved_41_46:6; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t agx0:1; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t usb:1; + uint64_t reserved_32_32:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_28_28:1; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t l2c:1; + uint64_t pow:1; + uint64_t fpa:1; + uint64_t iob:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_4_18:15; + uint64_t wdog:4; +#else + uint64_t wdog:4; + uint64_t reserved_4_18:15; + uint64_t nand:1; + uint64_t mio:1; + uint64_t iob:1; + uint64_t fpa:1; + uint64_t pow:1; + uint64_t l2c:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_28_28:1; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_32_32:1; + uint64_t usb:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t agx0:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_41_46:6; + uint64_t ptp:1; + uint64_t pem0:1; + uint64_t pem1:1; + uint64_t reserved_50_51:2; + uint64_t lmc0:1; + uint64_t reserved_53_62:10; + uint64_t rst:1; +#endif + } cnf71xx; +}; + +union cvmx_ciu_sum2_iox_int { + uint64_t u64; + struct cvmx_ciu_sum2_iox_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_sum2_iox_int_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_sum2_iox_int_cn61xx cn66xx; + struct cvmx_ciu_sum2_iox_int_s cnf71xx; +}; + +union cvmx_ciu_sum2_ppx_ip2 { + uint64_t u64; + struct cvmx_ciu_sum2_ppx_ip2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_sum2_ppx_ip2_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_sum2_ppx_ip2_cn61xx cn66xx; + struct cvmx_ciu_sum2_ppx_ip2_s cnf71xx; +}; + +union cvmx_ciu_sum2_ppx_ip3 { + uint64_t u64; + struct cvmx_ciu_sum2_ppx_ip3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_sum2_ppx_ip3_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_sum2_ppx_ip3_cn61xx cn66xx; + struct cvmx_ciu_sum2_ppx_ip3_s cnf71xx; +}; + +union cvmx_ciu_sum2_ppx_ip4 { + uint64_t u64; + struct cvmx_ciu_sum2_ppx_ip4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t endor:2; + uint64_t eoi:1; + uint64_t reserved_10_11:2; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_11:2; + uint64_t eoi:1; + uint64_t endor:2; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_ciu_sum2_ppx_ip4_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t timer:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t timer:6; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_ciu_sum2_ppx_ip4_cn61xx cn66xx; + struct cvmx_ciu_sum2_ppx_ip4_s cnf71xx; }; union cvmx_ciu_timx { uint64_t u64; struct cvmx_ciu_timx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t one_shot:1; uint64_t len:36; +#else + uint64_t len:36; + uint64_t one_shot:1; + uint64_t reserved_37_63:27; +#endif } s; struct cvmx_ciu_timx_s cn30xx; struct cvmx_ciu_timx_s cn31xx; @@ -2264,13 +9935,35 @@ union cvmx_ciu_timx { struct cvmx_ciu_timx_s cn56xxp1; struct cvmx_ciu_timx_s cn58xx; struct cvmx_ciu_timx_s cn58xxp1; + struct cvmx_ciu_timx_s cn61xx; struct cvmx_ciu_timx_s cn63xx; struct cvmx_ciu_timx_s cn63xxp1; + struct cvmx_ciu_timx_s cn66xx; + struct cvmx_ciu_timx_s cn68xx; + struct cvmx_ciu_timx_s cn68xxp1; + struct cvmx_ciu_timx_s cnf71xx; +}; + +union cvmx_ciu_tim_multi_cast { + uint64_t u64; + struct cvmx_ciu_tim_multi_cast_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t en:1; +#else + uint64_t en:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu_tim_multi_cast_s cn61xx; + struct cvmx_ciu_tim_multi_cast_s cn66xx; + struct cvmx_ciu_tim_multi_cast_s cnf71xx; }; union cvmx_ciu_wdogx { uint64_t u64; struct cvmx_ciu_wdogx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_46_63:18; uint64_t gstopen:1; uint64_t dstop:1; @@ -2278,6 +9971,15 @@ union cvmx_ciu_wdogx { uint64_t len:16; uint64_t state:2; uint64_t mode:2; +#else + uint64_t mode:2; + uint64_t state:2; + uint64_t len:16; + uint64_t cnt:24; + uint64_t dstop:1; + uint64_t gstopen:1; + uint64_t reserved_46_63:18; +#endif } s; struct cvmx_ciu_wdogx_s cn30xx; struct cvmx_ciu_wdogx_s cn31xx; @@ -2290,8 +9992,13 @@ union cvmx_ciu_wdogx { struct cvmx_ciu_wdogx_s cn56xxp1; struct cvmx_ciu_wdogx_s cn58xx; struct cvmx_ciu_wdogx_s cn58xxp1; + struct cvmx_ciu_wdogx_s cn61xx; struct cvmx_ciu_wdogx_s cn63xx; struct cvmx_ciu_wdogx_s cn63xxp1; + struct cvmx_ciu_wdogx_s cn66xx; + struct cvmx_ciu_wdogx_s cn68xx; + struct cvmx_ciu_wdogx_s cn68xxp1; + struct cvmx_ciu_wdogx_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h new file mode 100644 index 00000000000..148bc9a0085 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h @@ -0,0 +1,7108 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_CIU2_DEFS_H__ +#define __CVMX_CIU2_DEFS_H__ + +#define CVMX_CIU2_ACK_IOX_INT(block_id) (CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_ACK_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108097800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B7800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A7800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108094800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B4800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A4800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108098800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B8800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A8800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108095800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B5800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A5800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108093800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B3800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A3800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108096800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B6800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A6800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108092800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B2800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A2800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108091800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B1800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A1800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108090800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B0800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A0800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_INTR_CIU_READY (CVMX_ADD_IO_SEG(0x0001070100102008ull)) +#define CVMX_CIU2_INTR_RAM_ECC_CTL (CVMX_ADD_IO_SEG(0x0001070100102010ull)) +#define CVMX_CIU2_INTR_RAM_ECC_ST (CVMX_ADD_IO_SEG(0x0001070100102018ull)) +#define CVMX_CIU2_INTR_SLOWDOWN (CVMX_ADD_IO_SEG(0x0001070100102000ull)) +#define CVMX_CIU2_MSIRED_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_MSIRED_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_MSIRED_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_MSI_RCVX(offset) (CVMX_ADD_IO_SEG(0x00010701000C2000ull) + ((offset) & 255) * 8) +#define CVMX_CIU2_MSI_SELX(offset) (CVMX_ADD_IO_SEG(0x00010701000C3000ull) + ((offset) & 255) * 8) +#define CVMX_CIU2_RAW_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108047800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_RAW_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108044800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_RAW_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108045800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_RAW_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108043800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_RAW_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108046800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_RAW_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108042800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_RAW_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108041800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_RAW_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108040800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_RAW_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108087800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108084800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108088800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108085800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108083800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108086800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108082800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108081800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108080800ull) + ((block_id) & 1) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080400ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SUM_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070100000800ull) + ((offset) & 1) * 8) +#define CVMX_CIU2_SUM_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8) +#define CVMX_CIU2_SUM_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8) +#define CVMX_CIU2_SUM_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070100000400ull) + ((offset) & 31) * 8) + +union cvmx_ciu2_ack_iox_int { + uint64_t u64; + struct cvmx_ciu2_ack_iox_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t ack:1; +#else + uint64_t ack:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu2_ack_iox_int_s cn68xx; + struct cvmx_ciu2_ack_iox_int_s cn68xxp1; +}; + +union cvmx_ciu2_ack_ppx_ip2 { + uint64_t u64; + struct cvmx_ciu2_ack_ppx_ip2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t ack:1; +#else + uint64_t ack:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu2_ack_ppx_ip2_s cn68xx; + struct cvmx_ciu2_ack_ppx_ip2_s cn68xxp1; +}; + +union cvmx_ciu2_ack_ppx_ip3 { + uint64_t u64; + struct cvmx_ciu2_ack_ppx_ip3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t ack:1; +#else + uint64_t ack:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu2_ack_ppx_ip3_s cn68xx; + struct cvmx_ciu2_ack_ppx_ip3_s cn68xxp1; +}; + +union cvmx_ciu2_ack_ppx_ip4 { + uint64_t u64; + struct cvmx_ciu2_ack_ppx_ip4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t ack:1; +#else + uint64_t ack:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu2_ack_ppx_ip4_s cn68xx; + struct cvmx_ciu2_ack_ppx_ip4_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_gpio { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_iox_int_gpio_s cn68xx; + struct cvmx_ciu2_en_iox_int_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_gpio_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_gpio_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_gpio_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_gpio_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_io { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_iox_int_io_s cn68xx; + struct cvmx_ciu2_en_iox_int_io_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_io_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_io_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_io_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_io_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mbox { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mbox_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mbox_s cn68xx; + struct cvmx_ciu2_en_iox_int_mbox_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mbox_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mbox_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mbox_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mbox_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mem { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mem_s cn68xx; + struct cvmx_ciu2_en_iox_int_mem_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mem_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mem_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mem_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mem_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mio { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mio_s cn68xx; + struct cvmx_ciu2_en_iox_int_mio_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mio_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mio_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_mio_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_mio_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_pkt { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_iox_int_pkt_s cn68xx; + struct cvmx_ciu2_en_iox_int_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_pkt_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_pkt_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_iox_int_pkt_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_pkt_w1c_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_pkt_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_pkt_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_iox_int_pkt_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_pkt_w1s_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_rml { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_iox_int_rml_s cn68xx; + struct cvmx_ciu2_en_iox_int_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_rml_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_rml_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_iox_int_rml_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_rml_w1c_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_rml_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_rml_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_iox_int_rml_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_rml_w1s_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_wdog { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_iox_int_wdog_s cn68xx; + struct cvmx_ciu2_en_iox_int_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_wdog_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_wdog_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_wdog_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_wdog_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_wrkq { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_iox_int_wrkq_s cn68xx; + struct cvmx_ciu2_en_iox_int_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_wrkq_w1c { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_wrkq_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xx; + struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_iox_int_wrkq_w1s { + uint64_t u64; + struct cvmx_ciu2_en_iox_int_wrkq_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xx; + struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_gpio { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_gpio_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_gpio_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_io { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_io_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_io_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_io_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_io_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_io_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_io_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mbox { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mbox_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mbox_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mbox_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mem { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mem_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mem_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mio { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mio_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_mio_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_pkt { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_pkt_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_pkt_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_pkt_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_rml { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_rml_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_rml_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_rml_w1c_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_rml_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_rml_w1s_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_wdog { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_wdog_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_wdog_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_wrkq { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_wrkq_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip2_wrkq_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_gpio { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_gpio_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_gpio_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_io { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_io_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_io_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_io_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_io_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_io_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_io_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mbox { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mbox_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mbox_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mbox_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mem { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mem_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mem_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mio { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mio_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_mio_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_pkt { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_pkt_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_pkt_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_pkt_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_rml { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_rml_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_rml_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_rml_w1c_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_rml_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_rml_w1s_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_wdog { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_wdog_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_wdog_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_wrkq { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_wrkq_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip3_wrkq_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_gpio { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_gpio_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_gpio_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_io { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_io_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_io_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_io_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_io_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_io_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_io_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mbox { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mbox_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mbox_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mbox_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mem { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mem_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mem_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mio { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mio_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_mio_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_pkt { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_pkt_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_pkt_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_pkt_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_rml { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_rml_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_rml_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_rml_w1c_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_rml_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_rml_w1s_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_wdog { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_wdog_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_wdog_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_wrkq { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_wrkq_w1c { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xxp1; +}; + +union cvmx_ciu2_en_ppx_ip4_wrkq_w1s { + uint64_t u64; + struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xx; + struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xxp1; +}; + +union cvmx_ciu2_intr_ciu_ready { + uint64_t u64; + struct cvmx_ciu2_intr_ciu_ready_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t ready:1; +#else + uint64_t ready:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu2_intr_ciu_ready_s cn68xx; + struct cvmx_ciu2_intr_ciu_ready_s cn68xxp1; +}; + +union cvmx_ciu2_intr_ram_ecc_ctl { + uint64_t u64; + struct cvmx_ciu2_intr_ram_ecc_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_3_63:61; + uint64_t flip_synd:2; + uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t flip_synd:2; + uint64_t reserved_3_63:61; +#endif + } s; + struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xx; + struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xxp1; +}; + +union cvmx_ciu2_intr_ram_ecc_st { + uint64_t u64; + struct cvmx_ciu2_intr_ram_ecc_st_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_23_63:41; + uint64_t addr:7; + uint64_t reserved_13_15:3; + uint64_t syndrom:9; + uint64_t reserved_2_3:2; + uint64_t dbe:1; + uint64_t sbe:1; +#else + uint64_t sbe:1; + uint64_t dbe:1; + uint64_t reserved_2_3:2; + uint64_t syndrom:9; + uint64_t reserved_13_15:3; + uint64_t addr:7; + uint64_t reserved_23_63:41; +#endif + } s; + struct cvmx_ciu2_intr_ram_ecc_st_s cn68xx; + struct cvmx_ciu2_intr_ram_ecc_st_s cn68xxp1; +}; + +union cvmx_ciu2_intr_slowdown { + uint64_t u64; + struct cvmx_ciu2_intr_slowdown_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_3_63:61; + uint64_t ctl:3; +#else + uint64_t ctl:3; + uint64_t reserved_3_63:61; +#endif + } s; + struct cvmx_ciu2_intr_slowdown_s cn68xx; + struct cvmx_ciu2_intr_slowdown_s cn68xxp1; +}; + +union cvmx_ciu2_msi_rcvx { + uint64_t u64; + struct cvmx_ciu2_msi_rcvx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t msi_rcv:1; +#else + uint64_t msi_rcv:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_ciu2_msi_rcvx_s cn68xx; + struct cvmx_ciu2_msi_rcvx_s cn68xxp1; +}; + +union cvmx_ciu2_msi_selx { + uint64_t u64; + struct cvmx_ciu2_msi_selx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_13_63:51; + uint64_t pp_num:5; + uint64_t reserved_6_7:2; + uint64_t ip_num:2; + uint64_t reserved_1_3:3; + uint64_t en:1; +#else + uint64_t en:1; + uint64_t reserved_1_3:3; + uint64_t ip_num:2; + uint64_t reserved_6_7:2; + uint64_t pp_num:5; + uint64_t reserved_13_63:51; +#endif + } s; + struct cvmx_ciu2_msi_selx_s cn68xx; + struct cvmx_ciu2_msi_selx_s cn68xxp1; +}; + +union cvmx_ciu2_msired_ppx_ip2 { + uint64_t u64; + struct cvmx_ciu2_msired_ppx_ip2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_21_63:43; + uint64_t intr:1; + uint64_t reserved_17_19:3; + uint64_t newint:1; + uint64_t reserved_8_15:8; + uint64_t msi_num:8; +#else + uint64_t msi_num:8; + uint64_t reserved_8_15:8; + uint64_t newint:1; + uint64_t reserved_17_19:3; + uint64_t intr:1; + uint64_t reserved_21_63:43; +#endif + } s; + struct cvmx_ciu2_msired_ppx_ip2_s cn68xx; + struct cvmx_ciu2_msired_ppx_ip2_s cn68xxp1; +}; + +union cvmx_ciu2_msired_ppx_ip3 { + uint64_t u64; + struct cvmx_ciu2_msired_ppx_ip3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_21_63:43; + uint64_t intr:1; + uint64_t reserved_17_19:3; + uint64_t newint:1; + uint64_t reserved_8_15:8; + uint64_t msi_num:8; +#else + uint64_t msi_num:8; + uint64_t reserved_8_15:8; + uint64_t newint:1; + uint64_t reserved_17_19:3; + uint64_t intr:1; + uint64_t reserved_21_63:43; +#endif + } s; + struct cvmx_ciu2_msired_ppx_ip3_s cn68xx; + struct cvmx_ciu2_msired_ppx_ip3_s cn68xxp1; +}; + +union cvmx_ciu2_msired_ppx_ip4 { + uint64_t u64; + struct cvmx_ciu2_msired_ppx_ip4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_21_63:43; + uint64_t intr:1; + uint64_t reserved_17_19:3; + uint64_t newint:1; + uint64_t reserved_8_15:8; + uint64_t msi_num:8; +#else + uint64_t msi_num:8; + uint64_t reserved_8_15:8; + uint64_t newint:1; + uint64_t reserved_17_19:3; + uint64_t intr:1; + uint64_t reserved_21_63:43; +#endif + } s; + struct cvmx_ciu2_msired_ppx_ip4_s cn68xx; + struct cvmx_ciu2_msired_ppx_ip4_s cn68xxp1; +}; + +union cvmx_ciu2_raw_iox_int_gpio { + uint64_t u64; + struct cvmx_ciu2_raw_iox_int_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_raw_iox_int_gpio_s cn68xx; + struct cvmx_ciu2_raw_iox_int_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_raw_iox_int_io { + uint64_t u64; + struct cvmx_ciu2_raw_iox_int_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_raw_iox_int_io_s cn68xx; + struct cvmx_ciu2_raw_iox_int_io_s cn68xxp1; +}; + +union cvmx_ciu2_raw_iox_int_mem { + uint64_t u64; + struct cvmx_ciu2_raw_iox_int_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_raw_iox_int_mem_s cn68xx; + struct cvmx_ciu2_raw_iox_int_mem_s cn68xxp1; +}; + +union cvmx_ciu2_raw_iox_int_mio { + uint64_t u64; + struct cvmx_ciu2_raw_iox_int_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_raw_iox_int_mio_s cn68xx; + struct cvmx_ciu2_raw_iox_int_mio_s cn68xxp1; +}; + +union cvmx_ciu2_raw_iox_int_pkt { + uint64_t u64; + struct cvmx_ciu2_raw_iox_int_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_raw_iox_int_pkt_s cn68xx; + struct cvmx_ciu2_raw_iox_int_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_raw_iox_int_rml { + uint64_t u64; + struct cvmx_ciu2_raw_iox_int_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_raw_iox_int_rml_s cn68xx; + struct cvmx_ciu2_raw_iox_int_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_raw_iox_int_wdog { + uint64_t u64; + struct cvmx_ciu2_raw_iox_int_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_raw_iox_int_wdog_s cn68xx; + struct cvmx_ciu2_raw_iox_int_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_raw_iox_int_wrkq { + uint64_t u64; + struct cvmx_ciu2_raw_iox_int_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xx; + struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip2_gpio { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip2_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip2_io { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip2_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip2_mem { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip2_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip2_mio { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip2_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip2_pkt { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip2_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip2_pkt_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip2_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip2_rml { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip2_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip2_rml_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip2_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip2_wdog { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip2_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip2_wrkq { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip2_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip3_gpio { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip3_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip3_io { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip3_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip3_mem { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip3_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip3_mio { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip3_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip3_pkt { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip3_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip3_pkt_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip3_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip3_rml { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip3_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip3_rml_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip3_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip3_wdog { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip3_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip3_wrkq { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip3_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip4_gpio { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip4_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip4_io { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip4_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip4_mem { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip4_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip4_mio { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip4_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip4_pkt { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip4_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip4_pkt_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip4_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip4_rml { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip4_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip4_rml_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip4_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip4_wdog { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip4_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_raw_ppx_ip4_wrkq { + uint64_t u64; + struct cvmx_ciu2_raw_ppx_ip4_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xx; + struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_gpio { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_src_iox_int_gpio_s cn68xx; + struct cvmx_ciu2_src_iox_int_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_io { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_src_iox_int_io_s cn68xx; + struct cvmx_ciu2_src_iox_int_io_s cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_mbox { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_mbox_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_src_iox_int_mbox_s cn68xx; + struct cvmx_ciu2_src_iox_int_mbox_s cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_mem { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_src_iox_int_mem_s cn68xx; + struct cvmx_ciu2_src_iox_int_mem_s cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_mio { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_src_iox_int_mio_s cn68xx; + struct cvmx_ciu2_src_iox_int_mio_s cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_pkt { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_src_iox_int_pkt_s cn68xx; + struct cvmx_ciu2_src_iox_int_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_rml { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_src_iox_int_rml_s cn68xx; + struct cvmx_ciu2_src_iox_int_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_wdog { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_src_iox_int_wdog_s cn68xx; + struct cvmx_ciu2_src_iox_int_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_src_iox_int_wrkq { + uint64_t u64; + struct cvmx_ciu2_src_iox_int_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_src_iox_int_wrkq_s cn68xx; + struct cvmx_ciu2_src_iox_int_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_gpio { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_io { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_io_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_io_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_mbox { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_mbox_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_mem { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_mio { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_pkt { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_pkt_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_rml { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_rml_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_wdog { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip2_wrkq { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip2_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xx; + struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_gpio { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_io { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_io_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_io_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_mbox { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_mbox_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_mem { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_mio { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_pkt { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_pkt_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_rml { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_rml_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_wdog { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip3_wrkq { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip3_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xx; + struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_gpio { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_gpio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t gpio:16; +#else + uint64_t gpio:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_io { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t pem:2; + uint64_t reserved_18_31:14; + uint64_t pci_inta:2; + uint64_t reserved_13_15:3; + uint64_t msired:1; + uint64_t pci_msi:4; + uint64_t reserved_4_7:4; + uint64_t pci_intr:4; +#else + uint64_t pci_intr:4; + uint64_t reserved_4_7:4; + uint64_t pci_msi:4; + uint64_t msired:1; + uint64_t reserved_13_15:3; + uint64_t pci_inta:2; + uint64_t reserved_18_31:14; + uint64_t pem:2; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_io_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_io_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_mbox { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_mbox_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_mem { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_mem_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t lmc:4; +#else + uint64_t lmc:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_mio { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_mio_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rst:1; + uint64_t reserved_49_62:14; + uint64_t ptp:1; + uint64_t reserved_45_47:3; + uint64_t usb_hci:1; + uint64_t reserved_41_43:3; + uint64_t usb_uctl:1; + uint64_t reserved_38_39:2; + uint64_t uart:2; + uint64_t reserved_34_35:2; + uint64_t twsi:2; + uint64_t reserved_19_31:13; + uint64_t bootdma:1; + uint64_t mio:1; + uint64_t nand:1; + uint64_t reserved_12_15:4; + uint64_t timer:4; + uint64_t reserved_3_7:5; + uint64_t ipd_drp:1; + uint64_t ssoiq:1; + uint64_t ipdppthr:1; +#else + uint64_t ipdppthr:1; + uint64_t ssoiq:1; + uint64_t ipd_drp:1; + uint64_t reserved_3_7:5; + uint64_t timer:4; + uint64_t reserved_12_15:4; + uint64_t nand:1; + uint64_t mio:1; + uint64_t bootdma:1; + uint64_t reserved_19_31:13; + uint64_t twsi:2; + uint64_t reserved_34_35:2; + uint64_t uart:2; + uint64_t reserved_38_39:2; + uint64_t usb_uctl:1; + uint64_t reserved_41_43:3; + uint64_t usb_hci:1; + uint64_t reserved_45_47:3; + uint64_t ptp:1; + uint64_t reserved_49_62:14; + uint64_t rst:1; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_pkt { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t ilk_drp:2; + uint64_t reserved_49_51:3; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_51:3; + uint64_t ilk_drp:2; + uint64_t reserved_54_63:10; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_pkt_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_pkt_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_49_63:15; + uint64_t ilk:1; + uint64_t reserved_41_47:7; + uint64_t mii:1; + uint64_t reserved_33_39:7; + uint64_t agl:1; + uint64_t reserved_13_31:19; + uint64_t gmx_drp:5; + uint64_t reserved_5_7:3; + uint64_t agx:5; +#else + uint64_t agx:5; + uint64_t reserved_5_7:3; + uint64_t gmx_drp:5; + uint64_t reserved_13_31:19; + uint64_t agl:1; + uint64_t reserved_33_39:7; + uint64_t mii:1; + uint64_t reserved_41_47:7; + uint64_t ilk:1; + uint64_t reserved_49_63:15; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_rml { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_rml_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_37_39:3; + uint64_t dpi_dma:1; + uint64_t reserved_34_35:2; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_35:2; + uint64_t dpi_dma:1; + uint64_t reserved_37_39:3; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_rml_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_rml_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t trace:4; + uint64_t reserved_49_51:3; + uint64_t l2c:1; + uint64_t reserved_41_47:7; + uint64_t dfa:1; + uint64_t reserved_34_39:6; + uint64_t dpi:1; + uint64_t sli:1; + uint64_t reserved_31_31:1; + uint64_t key:1; + uint64_t rad:1; + uint64_t tim:1; + uint64_t reserved_25_27:3; + uint64_t zip:1; + uint64_t reserved_17_23:7; + uint64_t sso:1; + uint64_t reserved_8_15:8; + uint64_t pko:1; + uint64_t pip:1; + uint64_t ipd:1; + uint64_t fpa:1; + uint64_t reserved_1_3:3; + uint64_t iob:1; +#else + uint64_t iob:1; + uint64_t reserved_1_3:3; + uint64_t fpa:1; + uint64_t ipd:1; + uint64_t pip:1; + uint64_t pko:1; + uint64_t reserved_8_15:8; + uint64_t sso:1; + uint64_t reserved_17_23:7; + uint64_t zip:1; + uint64_t reserved_25_27:3; + uint64_t tim:1; + uint64_t rad:1; + uint64_t key:1; + uint64_t reserved_31_31:1; + uint64_t sli:1; + uint64_t dpi:1; + uint64_t reserved_34_39:6; + uint64_t dfa:1; + uint64_t reserved_41_47:7; + uint64_t l2c:1; + uint64_t reserved_49_51:3; + uint64_t trace:4; + uint64_t reserved_56_63:8; +#endif + } cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_wdog { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wdog:32; +#else + uint64_t wdog:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xxp1; +}; + +union cvmx_ciu2_src_ppx_ip4_wrkq { + uint64_t u64; + struct cvmx_ciu2_src_ppx_ip4_wrkq_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t workq:64; +#else + uint64_t workq:64; +#endif + } s; + struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xx; + struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xxp1; +}; + +union cvmx_ciu2_sum_iox_int { + uint64_t u64; + struct cvmx_ciu2_sum_iox_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t mbox:4; + uint64_t reserved_8_59:52; + uint64_t gpio:1; + uint64_t pkt:1; + uint64_t mem:1; + uint64_t io:1; + uint64_t mio:1; + uint64_t rml:1; + uint64_t wdog:1; + uint64_t workq:1; +#else + uint64_t workq:1; + uint64_t wdog:1; + uint64_t rml:1; + uint64_t mio:1; + uint64_t io:1; + uint64_t mem:1; + uint64_t pkt:1; + uint64_t gpio:1; + uint64_t reserved_8_59:52; + uint64_t mbox:4; +#endif + } s; + struct cvmx_ciu2_sum_iox_int_s cn68xx; + struct cvmx_ciu2_sum_iox_int_s cn68xxp1; +}; + +union cvmx_ciu2_sum_ppx_ip2 { + uint64_t u64; + struct cvmx_ciu2_sum_ppx_ip2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t mbox:4; + uint64_t reserved_8_59:52; + uint64_t gpio:1; + uint64_t pkt:1; + uint64_t mem:1; + uint64_t io:1; + uint64_t mio:1; + uint64_t rml:1; + uint64_t wdog:1; + uint64_t workq:1; +#else + uint64_t workq:1; + uint64_t wdog:1; + uint64_t rml:1; + uint64_t mio:1; + uint64_t io:1; + uint64_t mem:1; + uint64_t pkt:1; + uint64_t gpio:1; + uint64_t reserved_8_59:52; + uint64_t mbox:4; +#endif + } s; + struct cvmx_ciu2_sum_ppx_ip2_s cn68xx; + struct cvmx_ciu2_sum_ppx_ip2_s cn68xxp1; +}; + +union cvmx_ciu2_sum_ppx_ip3 { + uint64_t u64; + struct cvmx_ciu2_sum_ppx_ip3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t mbox:4; + uint64_t reserved_8_59:52; + uint64_t gpio:1; + uint64_t pkt:1; + uint64_t mem:1; + uint64_t io:1; + uint64_t mio:1; + uint64_t rml:1; + uint64_t wdog:1; + uint64_t workq:1; +#else + uint64_t workq:1; + uint64_t wdog:1; + uint64_t rml:1; + uint64_t mio:1; + uint64_t io:1; + uint64_t mem:1; + uint64_t pkt:1; + uint64_t gpio:1; + uint64_t reserved_8_59:52; + uint64_t mbox:4; +#endif + } s; + struct cvmx_ciu2_sum_ppx_ip3_s cn68xx; + struct cvmx_ciu2_sum_ppx_ip3_s cn68xxp1; +}; + +union cvmx_ciu2_sum_ppx_ip4 { + uint64_t u64; + struct cvmx_ciu2_sum_ppx_ip4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t mbox:4; + uint64_t reserved_8_59:52; + uint64_t gpio:1; + uint64_t pkt:1; + uint64_t mem:1; + uint64_t io:1; + uint64_t mio:1; + uint64_t rml:1; + uint64_t wdog:1; + uint64_t workq:1; +#else + uint64_t workq:1; + uint64_t wdog:1; + uint64_t rml:1; + uint64_t mio:1; + uint64_t io:1; + uint64_t mem:1; + uint64_t pkt:1; + uint64_t gpio:1; + uint64_t reserved_8_59:52; + uint64_t mbox:4; +#endif + } s; + struct cvmx_ciu2_sum_ppx_ip4_s cn68xx; + struct cvmx_ciu2_sum_ppx_ip4_s cn68xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h index 614653b686a..024a71b2bff 100644 --- a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h +++ b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h @@ -76,7 +76,7 @@ #include <linux/prefetch.h> -#include "cvmx-fpa.h" +#include <asm/octeon/cvmx-fpa.h> /** * By default we disable the max depth support. Most programs * don't use it and it slows down the command queue processing @@ -244,33 +244,33 @@ static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id, ".set noreorder\n" "1:\n" /* Atomic add one to ticket_ptr */ - "ll %[my_ticket], %[ticket_ptr]\n" + "ll %[my_ticket], %[ticket_ptr]\n" /* and store the original value */ - "li %[ticket], 1\n" + "li %[ticket], 1\n" /* in my_ticket */ - "baddu %[ticket], %[my_ticket]\n" - "sc %[ticket], %[ticket_ptr]\n" - "beqz %[ticket], 1b\n" + "baddu %[ticket], %[my_ticket]\n" + "sc %[ticket], %[ticket_ptr]\n" + "beqz %[ticket], 1b\n" " nop\n" /* Load the current now_serving ticket */ - "lbu %[ticket], %[now_serving]\n" + "lbu %[ticket], %[now_serving]\n" "2:\n" /* Jump out if now_serving == my_ticket */ - "beq %[ticket], %[my_ticket], 4f\n" + "beq %[ticket], %[my_ticket], 4f\n" /* Find out how many tickets are in front of me */ - " subu %[ticket], %[my_ticket], %[ticket]\n" + " subu %[ticket], %[my_ticket], %[ticket]\n" /* Use tickets in front of me minus one to delay */ "subu %[ticket], 1\n" /* Delay will be ((tickets in front)-1)*32 loops */ - "cins %[ticket], %[ticket], 5, 7\n" + "cins %[ticket], %[ticket], 5, 7\n" "3:\n" /* Loop here until our ticket might be up */ - "bnez %[ticket], 3b\n" - " subu %[ticket], 1\n" + "bnez %[ticket], 3b\n" + " subu %[ticket], 1\n" /* Jump back up to check out ticket again */ - "b 2b\n" + "b 2b\n" /* Load the current now_serving ticket */ - " lbu %[ticket], %[now_serving]\n" + " lbu %[ticket], %[now_serving]\n" "4:\n" ".set pop\n" : [ticket_ptr] "=m"(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]), @@ -313,9 +313,9 @@ static inline __cvmx_cmd_queue_state_t * * @queue_id: Hardware command queue to write to * @use_locking: - * Use internal locking to ensure exclusive access for queue - * updates. If you don't use this locking you must ensure - * exclusivity some other way. Locking is strongly recommended. + * Use internal locking to ensure exclusive access for queue + * updates. If you don't use this locking you must ensure + * exclusivity some other way. Locking is strongly recommended. * @cmd_count: Number of command words to write * @cmds: Array of commands to write * @@ -411,9 +411,9 @@ static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write(cvmx_cmd_queue_id_t * * @queue_id: Hardware command queue to write to * @use_locking: - * Use internal locking to ensure exclusive access for queue - * updates. If you don't use this locking you must ensure - * exclusivity some other way. Locking is strongly recommended. + * Use internal locking to ensure exclusive access for queue + * updates. If you don't use this locking you must ensure + * exclusivity some other way. Locking is strongly recommended. * @cmd1: Command * @cmd2: Command * @@ -510,9 +510,9 @@ static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t * * @queue_id: Hardware command queue to write to * @use_locking: - * Use internal locking to ensure exclusive access for queue - * updates. If you don't use this locking you must ensure - * exclusivity some other way. Locking is strongly recommended. + * Use internal locking to ensure exclusive access for queue + * updates. If you don't use this locking you must ensure + * exclusivity some other way. Locking is strongly recommended. * @cmd1: Command * @cmd2: Command * @cmd3: Command diff --git a/arch/mips/include/asm/octeon/cvmx-config.h b/arch/mips/include/asm/octeon/cvmx-config.h index 26835d1b43b..f7dd17d0dc2 100644 --- a/arch/mips/include/asm/octeon/cvmx-config.h +++ b/arch/mips/include/asm/octeon/cvmx-config.h @@ -31,13 +31,13 @@ /* Pools in use */ /* Packet buffers */ -#define CVMX_FPA_PACKET_POOL (0) -#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE +#define CVMX_FPA_PACKET_POOL (0) +#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE /* Work queue entrys */ -#define CVMX_FPA_WQE_POOL (1) -#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE +#define CVMX_FPA_WQE_POOL (1) +#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE /* PKO queue command buffers */ -#define CVMX_FPA_OUTPUT_BUFFER_POOL (2) +#define CVMX_FPA_OUTPUT_BUFFER_POOL (2) #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE /************************* FAU allocation ********************************/ @@ -45,7 +45,7 @@ * in order of descending size so that all alignment constraints are * automatically met. The enums are linked so that the following enum * continues allocating where the previous one left off, so the - * numbering within each enum always starts with zero. The macros + * numbering within each enum always starts with zero. The macros * take care of the address increment size, so the values entered * always increase by 1. FAU registers are accessed with byte * addresses. @@ -90,9 +90,9 @@ typedef enum { * be taken into account. */ /* Generic scratch iobdma area */ -#define CVMX_SCR_SCRATCH (0) +#define CVMX_SCR_SCRATCH (0) /* First location available after cvmx-config.h allocated region. */ -#define CVMX_SCR_REG_AVAIL_BASE (8) +#define CVMX_SCR_REG_AVAIL_BASE (8) /* * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve @@ -145,14 +145,14 @@ typedef enum { * 1: include */ #define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP 0 -#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP 0 -#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0 -#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0 -#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0 #define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP 0 -#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP 0 -#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0 -#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0 #define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL 0 #define CVMX_HELPER_INPUT_TAG_INPUT_PORT 1 diff --git a/arch/mips/include/asm/octeon/cvmx-dbg-defs.h b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h index abbf42d05e5..40799cdae69 100644 --- a/arch/mips/include/asm/octeon/cvmx-dbg-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,27 +28,43 @@ #ifndef __CVMX_DBG_DEFS_H__ #define __CVMX_DBG_DEFS_H__ -#define CVMX_DBG_DATA \ - CVMX_ADD_IO_SEG(0x00011F00000001E8ull) +#define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull)) union cvmx_dbg_data { uint64_t u64; struct cvmx_dbg_data_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; +#else + uint64_t data:17; + uint64_t dsel_ext:1; + uint64_t c_mul:5; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_dbg_data_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t pll_mul:3; uint64_t reserved_23_27:5; uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; +#else + uint64_t data:17; + uint64_t dsel_ext:1; + uint64_t c_mul:5; + uint64_t reserved_23_27:5; + uint64_t pll_mul:3; + uint64_t reserved_31_63:33; +#endif } cn30xx; struct cvmx_dbg_data_cn30xx cn31xx; struct cvmx_dbg_data_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t d_mul:4; uint64_t dclk_mul2:1; @@ -56,15 +72,32 @@ union cvmx_dbg_data { uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; +#else + uint64_t data:17; + uint64_t dsel_ext:1; + uint64_t c_mul:5; + uint64_t cclk_div2:1; + uint64_t dclk_mul2:1; + uint64_t d_mul:4; + uint64_t reserved_29_63:35; +#endif } cn38xx; struct cvmx_dbg_data_cn38xx cn38xxp2; struct cvmx_dbg_data_cn30xx cn50xx; struct cvmx_dbg_data_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t rem:6; uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; +#else + uint64_t data:17; + uint64_t dsel_ext:1; + uint64_t c_mul:5; + uint64_t rem:6; + uint64_t reserved_29_63:35; +#endif } cn58xx; struct cvmx_dbg_data_cn58xx cn58xxp1; }; diff --git a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h index c34ad04789c..dd5b0428de3 100644 --- a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2011 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -55,52 +55,107 @@ #define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull)) #define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull)) #define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8) +static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + + if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1)) + return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8; + + if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2)) + return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8; + return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8; + } + return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8; +} + #define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8) union cvmx_dpi_bist_status { uint64_t u64; struct cvmx_dpi_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_47_63:17; uint64_t bist:47; +#else + uint64_t bist:47; + uint64_t reserved_47_63:17; +#endif } s; struct cvmx_dpi_bist_status_s cn61xx; struct cvmx_dpi_bist_status_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t bist:45; +#else + uint64_t bist:45; + uint64_t reserved_45_63:19; +#endif } cn63xx; struct cvmx_dpi_bist_status_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t bist:37; +#else + uint64_t bist:37; + uint64_t reserved_37_63:27; +#endif } cn63xxp1; struct cvmx_dpi_bist_status_s cn66xx; struct cvmx_dpi_bist_status_cn63xx cn68xx; struct cvmx_dpi_bist_status_cn63xx cn68xxp1; + struct cvmx_dpi_bist_status_s cnf71xx; }; union cvmx_dpi_ctl { uint64_t u64; struct cvmx_dpi_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t clk:1; uint64_t en:1; +#else + uint64_t en:1; + uint64_t clk:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_dpi_ctl_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t en:1; +#else + uint64_t en:1; + uint64_t reserved_1_63:63; +#endif } cn61xx; struct cvmx_dpi_ctl_s cn63xx; struct cvmx_dpi_ctl_s cn63xxp1; struct cvmx_dpi_ctl_s cn66xx; struct cvmx_dpi_ctl_s cn68xx; struct cvmx_dpi_ctl_s cn68xxp1; + struct cvmx_dpi_ctl_cn61xx cnf71xx; }; union cvmx_dpi_dmax_counts { uint64_t u64; struct cvmx_dpi_dmax_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t fcnt:7; uint64_t dbell:32; +#else + uint64_t dbell:32; + uint64_t fcnt:7; + uint64_t reserved_39_63:25; +#endif } s; struct cvmx_dpi_dmax_counts_s cn61xx; struct cvmx_dpi_dmax_counts_s cn63xx; @@ -108,13 +163,19 @@ union cvmx_dpi_dmax_counts { struct cvmx_dpi_dmax_counts_s cn66xx; struct cvmx_dpi_dmax_counts_s cn68xx; struct cvmx_dpi_dmax_counts_s cn68xxp1; + struct cvmx_dpi_dmax_counts_s cnf71xx; }; union cvmx_dpi_dmax_dbell { uint64_t u64; struct cvmx_dpi_dmax_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dbell:16; +#else + uint64_t dbell:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_dpi_dmax_dbell_s cn61xx; struct cvmx_dpi_dmax_dbell_s cn63xx; @@ -122,31 +183,48 @@ union cvmx_dpi_dmax_dbell { struct cvmx_dpi_dmax_dbell_s cn66xx; struct cvmx_dpi_dmax_dbell_s cn68xx; struct cvmx_dpi_dmax_dbell_s cn68xxp1; + struct cvmx_dpi_dmax_dbell_s cnf71xx; }; union cvmx_dpi_dmax_err_rsp_status { uint64_t u64; struct cvmx_dpi_dmax_err_rsp_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t status:6; +#else + uint64_t status:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_dpi_dmax_err_rsp_status_s cn61xx; struct cvmx_dpi_dmax_err_rsp_status_s cn66xx; struct cvmx_dpi_dmax_err_rsp_status_s cn68xx; struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1; + struct cvmx_dpi_dmax_err_rsp_status_s cnf71xx; }; union cvmx_dpi_dmax_ibuff_saddr { uint64_t u64; struct cvmx_dpi_dmax_ibuff_saddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t csize:14; uint64_t reserved_41_47:7; uint64_t idle:1; uint64_t saddr:33; uint64_t reserved_0_6:7; +#else + uint64_t reserved_0_6:7; + uint64_t saddr:33; + uint64_t idle:1; + uint64_t reserved_41_47:7; + uint64_t csize:14; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_dpi_dmax_ibuff_saddr_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t csize:14; uint64_t reserved_41_47:7; @@ -154,47 +232,78 @@ union cvmx_dpi_dmax_ibuff_saddr { uint64_t reserved_36_39:4; uint64_t saddr:29; uint64_t reserved_0_6:7; +#else + uint64_t reserved_0_6:7; + uint64_t saddr:29; + uint64_t reserved_36_39:4; + uint64_t idle:1; + uint64_t reserved_41_47:7; + uint64_t csize:14; + uint64_t reserved_62_63:2; +#endif } cn61xx; struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx; struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1; struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx; struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx; struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1; + struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx; }; union cvmx_dpi_dmax_iflight { uint64_t u64; struct cvmx_dpi_dmax_iflight_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t cnt:3; +#else + uint64_t cnt:3; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_dpi_dmax_iflight_s cn61xx; struct cvmx_dpi_dmax_iflight_s cn66xx; struct cvmx_dpi_dmax_iflight_s cn68xx; struct cvmx_dpi_dmax_iflight_s cn68xxp1; + struct cvmx_dpi_dmax_iflight_s cnf71xx; }; union cvmx_dpi_dmax_naddr { uint64_t u64; struct cvmx_dpi_dmax_naddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t addr:40; +#else + uint64_t addr:40; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_dpi_dmax_naddr_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t addr:36; +#else + uint64_t addr:36; + uint64_t reserved_36_63:28; +#endif } cn61xx; struct cvmx_dpi_dmax_naddr_cn61xx cn63xx; struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1; struct cvmx_dpi_dmax_naddr_cn61xx cn66xx; struct cvmx_dpi_dmax_naddr_s cn68xx; struct cvmx_dpi_dmax_naddr_s cn68xxp1; + struct cvmx_dpi_dmax_naddr_cn61xx cnf71xx; }; union cvmx_dpi_dmax_reqbnk0 { uint64_t u64; struct cvmx_dpi_dmax_reqbnk0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t state:64; +#else + uint64_t state:64; +#endif } s; struct cvmx_dpi_dmax_reqbnk0_s cn61xx; struct cvmx_dpi_dmax_reqbnk0_s cn63xx; @@ -202,12 +311,17 @@ union cvmx_dpi_dmax_reqbnk0 { struct cvmx_dpi_dmax_reqbnk0_s cn66xx; struct cvmx_dpi_dmax_reqbnk0_s cn68xx; struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1; + struct cvmx_dpi_dmax_reqbnk0_s cnf71xx; }; union cvmx_dpi_dmax_reqbnk1 { uint64_t u64; struct cvmx_dpi_dmax_reqbnk1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t state:64; +#else uint64_t state:64; +#endif } s; struct cvmx_dpi_dmax_reqbnk1_s cn61xx; struct cvmx_dpi_dmax_reqbnk1_s cn63xx; @@ -215,11 +329,13 @@ union cvmx_dpi_dmax_reqbnk1 { struct cvmx_dpi_dmax_reqbnk1_s cn66xx; struct cvmx_dpi_dmax_reqbnk1_s cn68xx; struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1; + struct cvmx_dpi_dmax_reqbnk1_s cnf71xx; }; union cvmx_dpi_dma_control { uint64_t u64; struct cvmx_dpi_dma_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t dici_mode:1; uint64_t pkt_en1:1; @@ -240,9 +356,32 @@ union cvmx_dpi_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t reserved_0_13:14; +#else + uint64_t reserved_0_13:14; + uint64_t o_mode:1; + uint64_t o_es:2; + uint64_t o_ns:1; + uint64_t o_ro:1; + uint64_t o_add1:1; + uint64_t fpa_que:3; + uint64_t dwb_ichk:9; + uint64_t dwb_denb:1; + uint64_t b0_lend:1; + uint64_t reserved_34_47:14; + uint64_t dma_enb:6; + uint64_t reserved_54_55:2; + uint64_t pkt_en:1; + uint64_t pkt_hp:1; + uint64_t commit_mode:1; + uint64_t ffp_dis:1; + uint64_t pkt_en1:1; + uint64_t dici_mode:1; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_dpi_dma_control_s cn61xx; struct cvmx_dpi_dma_control_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t pkt_en1:1; uint64_t ffp_dis:1; @@ -262,8 +401,30 @@ union cvmx_dpi_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t reserved_0_13:14; +#else + uint64_t reserved_0_13:14; + uint64_t o_mode:1; + uint64_t o_es:2; + uint64_t o_ns:1; + uint64_t o_ro:1; + uint64_t o_add1:1; + uint64_t fpa_que:3; + uint64_t dwb_ichk:9; + uint64_t dwb_denb:1; + uint64_t b0_lend:1; + uint64_t reserved_34_47:14; + uint64_t dma_enb:6; + uint64_t reserved_54_55:2; + uint64_t pkt_en:1; + uint64_t pkt_hp:1; + uint64_t commit_mode:1; + uint64_t ffp_dis:1; + uint64_t pkt_en1:1; + uint64_t reserved_61_63:3; +#endif } cn63xx; struct cvmx_dpi_dma_control_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t commit_mode:1; uint64_t pkt_hp:1; @@ -281,17 +442,42 @@ union cvmx_dpi_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t reserved_0_13:14; +#else + uint64_t reserved_0_13:14; + uint64_t o_mode:1; + uint64_t o_es:2; + uint64_t o_ns:1; + uint64_t o_ro:1; + uint64_t o_add1:1; + uint64_t fpa_que:3; + uint64_t dwb_ichk:9; + uint64_t dwb_denb:1; + uint64_t b0_lend:1; + uint64_t reserved_34_47:14; + uint64_t dma_enb:6; + uint64_t reserved_54_55:2; + uint64_t pkt_en:1; + uint64_t pkt_hp:1; + uint64_t commit_mode:1; + uint64_t reserved_59_63:5; +#endif } cn63xxp1; struct cvmx_dpi_dma_control_cn63xx cn66xx; struct cvmx_dpi_dma_control_s cn68xx; struct cvmx_dpi_dma_control_cn63xx cn68xxp1; + struct cvmx_dpi_dma_control_s cnf71xx; }; union cvmx_dpi_dma_engx_en { uint64_t u64; struct cvmx_dpi_dma_engx_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t qen:8; +#else + uint64_t qen:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_dpi_dma_engx_en_s cn61xx; struct cvmx_dpi_dma_engx_en_s cn63xx; @@ -299,63 +485,101 @@ union cvmx_dpi_dma_engx_en { struct cvmx_dpi_dma_engx_en_s cn66xx; struct cvmx_dpi_dma_engx_en_s cn68xx; struct cvmx_dpi_dma_engx_en_s cn68xxp1; + struct cvmx_dpi_dma_engx_en_s cnf71xx; }; union cvmx_dpi_dma_ppx_cnt { uint64_t u64; struct cvmx_dpi_dma_ppx_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt:16; +#else + uint64_t cnt:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_dpi_dma_ppx_cnt_s cn61xx; struct cvmx_dpi_dma_ppx_cnt_s cn68xx; + struct cvmx_dpi_dma_ppx_cnt_s cnf71xx; }; union cvmx_dpi_engx_buf { uint64_t u64; struct cvmx_dpi_engx_buf_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t compblks:5; uint64_t reserved_9_31:23; uint64_t base:5; uint64_t blks:4; +#else + uint64_t blks:4; + uint64_t base:5; + uint64_t reserved_9_31:23; + uint64_t compblks:5; + uint64_t reserved_37_63:27; +#endif } s; struct cvmx_dpi_engx_buf_s cn61xx; struct cvmx_dpi_engx_buf_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t base:4; uint64_t blks:4; +#else + uint64_t blks:4; + uint64_t base:4; + uint64_t reserved_8_63:56; +#endif } cn63xx; struct cvmx_dpi_engx_buf_cn63xx cn63xxp1; struct cvmx_dpi_engx_buf_s cn66xx; struct cvmx_dpi_engx_buf_s cn68xx; struct cvmx_dpi_engx_buf_s cn68xxp1; + struct cvmx_dpi_engx_buf_s cnf71xx; }; union cvmx_dpi_info_reg { uint64_t u64; struct cvmx_dpi_info_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ffp:4; uint64_t reserved_2_3:2; uint64_t ncb:1; uint64_t rsl:1; +#else + uint64_t rsl:1; + uint64_t ncb:1; + uint64_t reserved_2_3:2; + uint64_t ffp:4; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_dpi_info_reg_s cn61xx; struct cvmx_dpi_info_reg_s cn63xx; struct cvmx_dpi_info_reg_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t ncb:1; uint64_t rsl:1; +#else + uint64_t rsl:1; + uint64_t ncb:1; + uint64_t reserved_2_63:62; +#endif } cn63xxp1; struct cvmx_dpi_info_reg_s cn66xx; struct cvmx_dpi_info_reg_s cn68xx; struct cvmx_dpi_info_reg_s cn68xxp1; + struct cvmx_dpi_info_reg_s cnf71xx; }; union cvmx_dpi_int_en { uint64_t u64; struct cvmx_dpi_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t sprt3_rst:1; uint64_t sprt2_rst:1; @@ -373,9 +597,29 @@ union cvmx_dpi_int_en { uint64_t reserved_2_7:6; uint64_t nfovr:1; uint64_t nderr:1; +#else + uint64_t nderr:1; + uint64_t nfovr:1; + uint64_t reserved_2_7:6; + uint64_t dmadbo:8; + uint64_t req_badadr:1; + uint64_t req_badlen:1; + uint64_t req_ovrflw:1; + uint64_t req_undflw:1; + uint64_t req_anull:1; + uint64_t req_inull:1; + uint64_t req_badfil:1; + uint64_t reserved_23_23:1; + uint64_t sprt0_rst:1; + uint64_t sprt1_rst:1; + uint64_t sprt2_rst:1; + uint64_t sprt3_rst:1; + uint64_t reserved_28_63:36; +#endif } s; struct cvmx_dpi_int_en_s cn61xx; struct cvmx_dpi_int_en_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t sprt1_rst:1; uint64_t sprt0_rst:1; @@ -391,16 +635,35 @@ union cvmx_dpi_int_en { uint64_t reserved_2_7:6; uint64_t nfovr:1; uint64_t nderr:1; +#else + uint64_t nderr:1; + uint64_t nfovr:1; + uint64_t reserved_2_7:6; + uint64_t dmadbo:8; + uint64_t req_badadr:1; + uint64_t req_badlen:1; + uint64_t req_ovrflw:1; + uint64_t req_undflw:1; + uint64_t req_anull:1; + uint64_t req_inull:1; + uint64_t req_badfil:1; + uint64_t reserved_23_23:1; + uint64_t sprt0_rst:1; + uint64_t sprt1_rst:1; + uint64_t reserved_26_63:38; +#endif } cn63xx; struct cvmx_dpi_int_en_cn63xx cn63xxp1; struct cvmx_dpi_int_en_s cn66xx; struct cvmx_dpi_int_en_cn63xx cn68xx; struct cvmx_dpi_int_en_cn63xx cn68xxp1; + struct cvmx_dpi_int_en_s cnf71xx; }; union cvmx_dpi_int_reg { uint64_t u64; struct cvmx_dpi_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t sprt3_rst:1; uint64_t sprt2_rst:1; @@ -418,9 +681,29 @@ union cvmx_dpi_int_reg { uint64_t reserved_2_7:6; uint64_t nfovr:1; uint64_t nderr:1; +#else + uint64_t nderr:1; + uint64_t nfovr:1; + uint64_t reserved_2_7:6; + uint64_t dmadbo:8; + uint64_t req_badadr:1; + uint64_t req_badlen:1; + uint64_t req_ovrflw:1; + uint64_t req_undflw:1; + uint64_t req_anull:1; + uint64_t req_inull:1; + uint64_t req_badfil:1; + uint64_t reserved_23_23:1; + uint64_t sprt0_rst:1; + uint64_t sprt1_rst:1; + uint64_t sprt2_rst:1; + uint64_t sprt3_rst:1; + uint64_t reserved_28_63:36; +#endif } s; struct cvmx_dpi_int_reg_s cn61xx; struct cvmx_dpi_int_reg_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t sprt1_rst:1; uint64_t sprt0_rst:1; @@ -436,31 +719,62 @@ union cvmx_dpi_int_reg { uint64_t reserved_2_7:6; uint64_t nfovr:1; uint64_t nderr:1; +#else + uint64_t nderr:1; + uint64_t nfovr:1; + uint64_t reserved_2_7:6; + uint64_t dmadbo:8; + uint64_t req_badadr:1; + uint64_t req_badlen:1; + uint64_t req_ovrflw:1; + uint64_t req_undflw:1; + uint64_t req_anull:1; + uint64_t req_inull:1; + uint64_t req_badfil:1; + uint64_t reserved_23_23:1; + uint64_t sprt0_rst:1; + uint64_t sprt1_rst:1; + uint64_t reserved_26_63:38; +#endif } cn63xx; struct cvmx_dpi_int_reg_cn63xx cn63xxp1; struct cvmx_dpi_int_reg_s cn66xx; struct cvmx_dpi_int_reg_cn63xx cn68xx; struct cvmx_dpi_int_reg_cn63xx cn68xxp1; + struct cvmx_dpi_int_reg_s cnf71xx; }; union cvmx_dpi_ncbx_cfg { uint64_t u64; struct cvmx_dpi_ncbx_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t molr:6; +#else + uint64_t molr:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_dpi_ncbx_cfg_s cn61xx; struct cvmx_dpi_ncbx_cfg_s cn66xx; struct cvmx_dpi_ncbx_cfg_s cn68xx; + struct cvmx_dpi_ncbx_cfg_s cnf71xx; }; union cvmx_dpi_pint_info { uint64_t u64; struct cvmx_dpi_pint_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t iinfo:6; uint64_t reserved_6_7:2; uint64_t sinfo:6; +#else + uint64_t sinfo:6; + uint64_t reserved_6_7:2; + uint64_t iinfo:6; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_dpi_pint_info_s cn61xx; struct cvmx_dpi_pint_info_s cn63xx; @@ -468,13 +782,19 @@ union cvmx_dpi_pint_info { struct cvmx_dpi_pint_info_s cn66xx; struct cvmx_dpi_pint_info_s cn68xx; struct cvmx_dpi_pint_info_s cn68xxp1; + struct cvmx_dpi_pint_info_s cnf71xx; }; union cvmx_dpi_pkt_err_rsp { uint64_t u64; struct cvmx_dpi_pkt_err_rsp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t pkterr:1; +#else + uint64_t pkterr:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_dpi_pkt_err_rsp_s cn61xx; struct cvmx_dpi_pkt_err_rsp_s cn63xx; @@ -482,13 +802,19 @@ union cvmx_dpi_pkt_err_rsp { struct cvmx_dpi_pkt_err_rsp_s cn66xx; struct cvmx_dpi_pkt_err_rsp_s cn68xx; struct cvmx_dpi_pkt_err_rsp_s cn68xxp1; + struct cvmx_dpi_pkt_err_rsp_s cnf71xx; }; union cvmx_dpi_req_err_rsp { uint64_t u64; struct cvmx_dpi_req_err_rsp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t qerr:8; +#else + uint64_t qerr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_dpi_req_err_rsp_s cn61xx; struct cvmx_dpi_req_err_rsp_s cn63xx; @@ -496,13 +822,19 @@ union cvmx_dpi_req_err_rsp { struct cvmx_dpi_req_err_rsp_s cn66xx; struct cvmx_dpi_req_err_rsp_s cn68xx; struct cvmx_dpi_req_err_rsp_s cn68xxp1; + struct cvmx_dpi_req_err_rsp_s cnf71xx; }; union cvmx_dpi_req_err_rsp_en { uint64_t u64; struct cvmx_dpi_req_err_rsp_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t en:8; +#else + uint64_t en:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_dpi_req_err_rsp_en_s cn61xx; struct cvmx_dpi_req_err_rsp_en_s cn63xx; @@ -510,13 +842,19 @@ union cvmx_dpi_req_err_rsp_en { struct cvmx_dpi_req_err_rsp_en_s cn66xx; struct cvmx_dpi_req_err_rsp_en_s cn68xx; struct cvmx_dpi_req_err_rsp_en_s cn68xxp1; + struct cvmx_dpi_req_err_rsp_en_s cnf71xx; }; union cvmx_dpi_req_err_rst { uint64_t u64; struct cvmx_dpi_req_err_rst_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t qerr:8; +#else + uint64_t qerr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_dpi_req_err_rst_s cn61xx; struct cvmx_dpi_req_err_rst_s cn63xx; @@ -524,13 +862,19 @@ union cvmx_dpi_req_err_rst { struct cvmx_dpi_req_err_rst_s cn66xx; struct cvmx_dpi_req_err_rst_s cn68xx; struct cvmx_dpi_req_err_rst_s cn68xxp1; + struct cvmx_dpi_req_err_rst_s cnf71xx; }; union cvmx_dpi_req_err_rst_en { uint64_t u64; struct cvmx_dpi_req_err_rst_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t en:8; +#else + uint64_t en:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_dpi_req_err_rst_en_s cn61xx; struct cvmx_dpi_req_err_rst_en_s cn63xx; @@ -538,27 +882,41 @@ union cvmx_dpi_req_err_rst_en { struct cvmx_dpi_req_err_rst_en_s cn66xx; struct cvmx_dpi_req_err_rst_en_s cn68xx; struct cvmx_dpi_req_err_rst_en_s cn68xxp1; + struct cvmx_dpi_req_err_rst_en_s cnf71xx; }; union cvmx_dpi_req_err_skip_comp { uint64_t u64; struct cvmx_dpi_req_err_skip_comp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t en_rst:8; uint64_t reserved_8_15:8; uint64_t en_rsp:8; +#else + uint64_t en_rsp:8; + uint64_t reserved_8_15:8; + uint64_t en_rst:8; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_dpi_req_err_skip_comp_s cn61xx; struct cvmx_dpi_req_err_skip_comp_s cn66xx; struct cvmx_dpi_req_err_skip_comp_s cn68xx; struct cvmx_dpi_req_err_skip_comp_s cn68xxp1; + struct cvmx_dpi_req_err_skip_comp_s cnf71xx; }; union cvmx_dpi_req_gbl_en { uint64_t u64; struct cvmx_dpi_req_gbl_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t qen:8; +#else + uint64_t qen:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_dpi_req_gbl_en_s cn61xx; struct cvmx_dpi_req_gbl_en_s cn63xx; @@ -566,11 +924,13 @@ union cvmx_dpi_req_gbl_en { struct cvmx_dpi_req_gbl_en_s cn66xx; struct cvmx_dpi_req_gbl_en_s cn68xx; struct cvmx_dpi_req_gbl_en_s cn68xxp1; + struct cvmx_dpi_req_gbl_en_s cnf71xx; }; union cvmx_dpi_sli_prtx_cfg { uint64_t u64; struct cvmx_dpi_sli_prtx_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t halt:1; uint64_t qlm_cfg:4; @@ -584,9 +944,25 @@ union cvmx_dpi_sli_prtx_cfg { uint64_t mrrs_lim:1; uint64_t reserved_2_2:1; uint64_t mrrs:2; +#else + uint64_t mrrs:2; + uint64_t reserved_2_2:1; + uint64_t mrrs_lim:1; + uint64_t mps:1; + uint64_t reserved_5_6:2; + uint64_t mps_lim:1; + uint64_t molr:6; + uint64_t reserved_14_15:2; + uint64_t rd_mode:1; + uint64_t reserved_17_19:3; + uint64_t qlm_cfg:4; + uint64_t halt:1; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_dpi_sli_prtx_cfg_s cn61xx; struct cvmx_dpi_sli_prtx_cfg_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t halt:1; uint64_t reserved_21_23:3; @@ -601,18 +977,40 @@ union cvmx_dpi_sli_prtx_cfg { uint64_t mrrs_lim:1; uint64_t reserved_2_2:1; uint64_t mrrs:2; +#else + uint64_t mrrs:2; + uint64_t reserved_2_2:1; + uint64_t mrrs_lim:1; + uint64_t mps:1; + uint64_t reserved_5_6:2; + uint64_t mps_lim:1; + uint64_t molr:6; + uint64_t reserved_14_15:2; + uint64_t rd_mode:1; + uint64_t reserved_17_19:3; + uint64_t qlm_cfg:1; + uint64_t reserved_21_23:3; + uint64_t halt:1; + uint64_t reserved_25_63:39; +#endif } cn63xx; struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1; struct cvmx_dpi_sli_prtx_cfg_s cn66xx; struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx; struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1; + struct cvmx_dpi_sli_prtx_cfg_s cnf71xx; }; union cvmx_dpi_sli_prtx_err { uint64_t u64; struct cvmx_dpi_sli_prtx_err_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:61; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t addr:61; +#endif } s; struct cvmx_dpi_sli_prtx_err_s cn61xx; struct cvmx_dpi_sli_prtx_err_s cn63xx; @@ -620,17 +1018,27 @@ union cvmx_dpi_sli_prtx_err { struct cvmx_dpi_sli_prtx_err_s cn66xx; struct cvmx_dpi_sli_prtx_err_s cn68xx; struct cvmx_dpi_sli_prtx_err_s cn68xxp1; + struct cvmx_dpi_sli_prtx_err_s cnf71xx; }; union cvmx_dpi_sli_prtx_err_info { uint64_t u64; struct cvmx_dpi_sli_prtx_err_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t lock:1; uint64_t reserved_5_7:3; uint64_t type:1; uint64_t reserved_3_3:1; uint64_t reqq:3; +#else + uint64_t reqq:3; + uint64_t reserved_3_3:1; + uint64_t type:1; + uint64_t reserved_5_7:3; + uint64_t lock:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_dpi_sli_prtx_err_info_s cn61xx; struct cvmx_dpi_sli_prtx_err_info_s cn63xx; @@ -638,6 +1046,7 @@ union cvmx_dpi_sli_prtx_err_info { struct cvmx_dpi_sli_prtx_err_info_s cn66xx; struct cvmx_dpi_sli_prtx_err_info_s cn68xx; struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1; + struct cvmx_dpi_sli_prtx_err_info_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-fau.h b/arch/mips/include/asm/octeon/cvmx-fau.h index a6939fc8ba1..ef98f7fc102 100644 --- a/arch/mips/include/asm/octeon/cvmx-fau.h +++ b/arch/mips/include/asm/octeon/cvmx-fau.h @@ -37,13 +37,13 @@ */ #define CVMX_FAU_LOAD_IO_ADDRESS cvmx_build_io_address(0x1e, 0) -#define CVMX_FAU_BITS_SCRADDR 63, 56 -#define CVMX_FAU_BITS_LEN 55, 48 -#define CVMX_FAU_BITS_INEVAL 35, 14 -#define CVMX_FAU_BITS_TAGWAIT 13, 13 -#define CVMX_FAU_BITS_NOADD 13, 13 -#define CVMX_FAU_BITS_SIZE 12, 11 -#define CVMX_FAU_BITS_REGISTER 10, 0 +#define CVMX_FAU_BITS_SCRADDR 63, 56 +#define CVMX_FAU_BITS_LEN 55, 48 +#define CVMX_FAU_BITS_INEVAL 35, 14 +#define CVMX_FAU_BITS_TAGWAIT 13, 13 +#define CVMX_FAU_BITS_NOADD 13, 13 +#define CVMX_FAU_BITS_SIZE 12, 11 +#define CVMX_FAU_BITS_REGISTER 10, 0 typedef enum { CVMX_FAU_OP_SIZE_8 = 0, @@ -109,11 +109,11 @@ typedef union { * Builds a store I/O address for writing to the FAU * * @noadd: 0 = Store value is atomically added to the current value - * 1 = Store value is atomically written over the current value + * 1 = Store value is atomically written over the current value * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. - * - Step by 4 for 32 bit access. - * - Step by 8 for 64 bit access. + * - Step by 2 for 16 bit access. + * - Step by 4 for 32 bit access. + * - Step by 8 for 64 bit access. * Returns Address to store for atomic update */ static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) @@ -127,16 +127,16 @@ static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) * Builds a I/O address for accessing the FAU * * @tagwait: Should the atomic add wait for the current tag switch - * operation to complete. - * - 0 = Don't wait - * - 1 = Wait for tag switch to complete + * operation to complete. + * - 0 = Don't wait + * - 1 = Wait for tag switch to complete * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. - * - Step by 4 for 32 bit access. - * - Step by 8 for 64 bit access. + * - Step by 2 for 16 bit access. + * - Step by 4 for 32 bit access. + * - Step by 8 for 64 bit access. * @value: Signed value to add. - * Note: When performing 32 and 64 bit access, only the low - * 22 bits are available. + * Note: When performing 32 and 64 bit access, only the low + * 22 bits are available. * Returns Address to read from for atomic update */ static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, @@ -152,9 +152,9 @@ static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, * Perform an atomic 64 bit add * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. + * - Step by 8 for 64 bit access. * @value: Signed value to add. - * Note: Only the low 22 bits are available. + * Note: Only the low 22 bits are available. * Returns Value of the register before the update */ static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, @@ -167,9 +167,9 @@ static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, * Perform an atomic 32 bit add * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. + * - Step by 4 for 32 bit access. * @value: Signed value to add. - * Note: Only the low 22 bits are available. + * Note: Only the low 22 bits are available. * Returns Value of the register before the update */ static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, @@ -182,7 +182,7 @@ static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, * Perform an atomic 16 bit add * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. + * - Step by 2 for 16 bit access. * @value: Signed value to add. * Returns Value of the register before the update */ @@ -209,12 +209,12 @@ static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) * completes * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. + * - Step by 8 for 64 bit access. * @value: Signed value to add. - * Note: Only the low 22 bits are available. + * Note: Only the low 22 bits are available. * Returns If a timeout occurs, the error bit will be set. Otherwise - * the value of the register before the update will be - * returned + * the value of the register before the update will be + * returned */ static inline cvmx_fau_tagwait64_t cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value) @@ -233,12 +233,12 @@ cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value) * completes * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. + * - Step by 4 for 32 bit access. * @value: Signed value to add. - * Note: Only the low 22 bits are available. + * Note: Only the low 22 bits are available. * Returns If a timeout occurs, the error bit will be set. Otherwise - * the value of the register before the update will be - * returned + * the value of the register before the update will be + * returned */ static inline cvmx_fau_tagwait32_t cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value) @@ -257,11 +257,11 @@ cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value) * completes * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. + * - Step by 2 for 16 bit access. * @value: Signed value to add. * Returns If a timeout occurs, the error bit will be set. Otherwise - * the value of the register before the update will be - * returned + * the value of the register before the update will be + * returned */ static inline cvmx_fau_tagwait16_t cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value) @@ -282,8 +282,8 @@ cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value) * @reg: FAU atomic register to access. 0 <= reg < 2048. * @value: Signed value to add. * Returns If a timeout occurs, the error bit will be set. Otherwise - * the value of the register before the update will be - * returned + * the value of the register before the update will be + * returned */ static inline cvmx_fau_tagwait8_t cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) @@ -301,21 +301,21 @@ cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) * * @scraddr: Scratch pad byte address to write to. Must be 8 byte aligned * @value: Signed value to add. - * Note: When performing 32 and 64 bit access, only the low - * 22 bits are available. + * Note: When performing 32 and 64 bit access, only the low + * 22 bits are available. * @tagwait: Should the atomic add wait for the current tag switch - * operation to complete. - * - 0 = Don't wait - * - 1 = Wait for tag switch to complete + * operation to complete. + * - 0 = Don't wait + * - 1 = Wait for tag switch to complete * @size: The size of the operation: - * - CVMX_FAU_OP_SIZE_8 (0) = 8 bits - * - CVMX_FAU_OP_SIZE_16 (1) = 16 bits - * - CVMX_FAU_OP_SIZE_32 (2) = 32 bits - * - CVMX_FAU_OP_SIZE_64 (3) = 64 bits + * - CVMX_FAU_OP_SIZE_8 (0) = 8 bits + * - CVMX_FAU_OP_SIZE_16 (1) = 16 bits + * - CVMX_FAU_OP_SIZE_32 (2) = 32 bits + * - CVMX_FAU_OP_SIZE_64 (3) = 64 bits * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. - * - Step by 4 for 32 bit access. - * - Step by 8 for 64 bit access. + * - Step by 2 for 16 bit access. + * - Step by 4 for 32 bit access. + * - Step by 8 for 64 bit access. * Returns Data to write using cvmx_send_single */ static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value, @@ -337,11 +337,11 @@ static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value, * placed in the scratch memory at byte address scraddr. * * @scraddr: Scratch memory byte address to put response in. - * Must be 8 byte aligned. + * Must be 8 byte aligned. * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. + * - Step by 8 for 64 bit access. * @value: Signed value to add. - * Note: Only the low 22 bits are available. + * Note: Only the low 22 bits are available. * Returns Placed in the scratch pad register */ static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr, @@ -357,11 +357,11 @@ static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr, * placed in the scratch memory at byte address scraddr. * * @scraddr: Scratch memory byte address to put response in. - * Must be 8 byte aligned. + * Must be 8 byte aligned. * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. + * - Step by 4 for 32 bit access. * @value: Signed value to add. - * Note: Only the low 22 bits are available. + * Note: Only the low 22 bits are available. * Returns Placed in the scratch pad register */ static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr, @@ -377,9 +377,9 @@ static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr, * placed in the scratch memory at byte address scraddr. * * @scraddr: Scratch memory byte address to put response in. - * Must be 8 byte aligned. + * Must be 8 byte aligned. * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. + * - Step by 2 for 16 bit access. * @value: Signed value to add. * Returns Placed in the scratch pad register */ @@ -396,7 +396,7 @@ static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr, * placed in the scratch memory at byte address scraddr. * * @scraddr: Scratch memory byte address to put response in. - * Must be 8 byte aligned. + * Must be 8 byte aligned. * @reg: FAU atomic register to access. 0 <= reg < 2048. * @value: Signed value to add. * Returns Placed in the scratch pad register @@ -414,14 +414,14 @@ static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr, * switch completes. * * @scraddr: Scratch memory byte address to put response in. Must be - * 8 byte aligned. If a timeout occurs, the error bit (63) - * will be set. Otherwise the value of the register before - * the update will be returned + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. + * - Step by 8 for 64 bit access. * @value: Signed value to add. - * Note: Only the low 22 bits are available. + * Note: Only the low 22 bits are available. * Returns Placed in the scratch pad register */ static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr, @@ -437,14 +437,14 @@ static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr, * switch completes. * * @scraddr: Scratch memory byte address to put response in. Must be - * 8 byte aligned. If a timeout occurs, the error bit (63) - * will be set. Otherwise the value of the register before - * the update will be returned + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. + * - Step by 4 for 32 bit access. * @value: Signed value to add. - * Note: Only the low 22 bits are available. + * Note: Only the low 22 bits are available. * Returns Placed in the scratch pad register */ static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr, @@ -460,12 +460,12 @@ static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr, * switch completes. * * @scraddr: Scratch memory byte address to put response in. Must be - * 8 byte aligned. If a timeout occurs, the error bit (63) - * will be set. Otherwise the value of the register before - * the update will be returned + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. + * - Step by 2 for 16 bit access. * @value: Signed value to add. * * Returns Placed in the scratch pad register @@ -483,9 +483,9 @@ static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr, * switch completes. * * @scraddr: Scratch memory byte address to put response in. Must be - * 8 byte aligned. If a timeout occurs, the error bit (63) - * will be set. Otherwise the value of the register before - * the update will be returned + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned * * @reg: FAU atomic register to access. 0 <= reg < 2048. * @value: Signed value to add. @@ -504,7 +504,7 @@ static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr, * Perform an atomic 64 bit add * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. + * - Step by 8 for 64 bit access. * @value: Signed value to add. */ static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value) @@ -516,7 +516,7 @@ static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value) * Perform an atomic 32 bit add * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. + * - Step by 4 for 32 bit access. * @value: Signed value to add. */ static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value) @@ -528,7 +528,7 @@ static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value) * Perform an atomic 16 bit add * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. + * - Step by 2 for 16 bit access. * @value: Signed value to add. */ static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value) @@ -551,7 +551,7 @@ static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value) * Perform an atomic 64 bit write * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. + * - Step by 8 for 64 bit access. * @value: Signed value to write. */ static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value) @@ -563,7 +563,7 @@ static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value) * Perform an atomic 32 bit write * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. + * - Step by 4 for 32 bit access. * @value: Signed value to write. */ static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value) @@ -575,7 +575,7 @@ static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value) * Perform an atomic 16 bit write * * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. + * - Step by 2 for 16 bit access. * @value: Signed value to write. */ static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value) diff --git a/arch/mips/include/asm/octeon/cvmx-fpa-defs.h b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h index bf5546b9011..1d79e3c7040 100644 --- a/arch/mips/include/asm/octeon/cvmx-fpa-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,74 +28,83 @@ #ifndef __CVMX_FPA_DEFS_H__ #define __CVMX_FPA_DEFS_H__ -#define CVMX_FPA_BIST_STATUS \ - CVMX_ADD_IO_SEG(0x00011800280000E8ull) -#define CVMX_FPA_CTL_STATUS \ - CVMX_ADD_IO_SEG(0x0001180028000050ull) -#define CVMX_FPA_FPF0_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000000ull) -#define CVMX_FPA_FPF0_SIZE \ - CVMX_ADD_IO_SEG(0x0001180028000058ull) -#define CVMX_FPA_FPF1_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000008ull) -#define CVMX_FPA_FPF2_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000010ull) -#define CVMX_FPA_FPF3_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000018ull) -#define CVMX_FPA_FPF4_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000020ull) -#define CVMX_FPA_FPF5_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000028ull) -#define CVMX_FPA_FPF6_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000030ull) -#define CVMX_FPA_FPF7_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000038ull) -#define CVMX_FPA_FPFX_MARKS(offset) \ - CVMX_ADD_IO_SEG(0x0001180028000008ull + (((offset) & 7) * 8) - 8 * 1) -#define CVMX_FPA_FPFX_SIZE(offset) \ - CVMX_ADD_IO_SEG(0x0001180028000060ull + (((offset) & 7) * 8) - 8 * 1) -#define CVMX_FPA_INT_ENB \ - CVMX_ADD_IO_SEG(0x0001180028000048ull) -#define CVMX_FPA_INT_SUM \ - CVMX_ADD_IO_SEG(0x0001180028000040ull) -#define CVMX_FPA_QUE0_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x00011800280000F0ull) -#define CVMX_FPA_QUE1_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x00011800280000F8ull) -#define CVMX_FPA_QUE2_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000100ull) -#define CVMX_FPA_QUE3_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000108ull) -#define CVMX_FPA_QUE4_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000110ull) -#define CVMX_FPA_QUE5_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000118ull) -#define CVMX_FPA_QUE6_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000120ull) -#define CVMX_FPA_QUE7_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000128ull) -#define CVMX_FPA_QUEX_AVAILABLE(offset) \ - CVMX_ADD_IO_SEG(0x0001180028000098ull + (((offset) & 7) * 8)) -#define CVMX_FPA_QUEX_PAGE_INDEX(offset) \ - CVMX_ADD_IO_SEG(0x00011800280000F0ull + (((offset) & 7) * 8)) -#define CVMX_FPA_QUE_ACT \ - CVMX_ADD_IO_SEG(0x0001180028000138ull) -#define CVMX_FPA_QUE_EXP \ - CVMX_ADD_IO_SEG(0x0001180028000130ull) -#define CVMX_FPA_WART_CTL \ - CVMX_ADD_IO_SEG(0x00011800280000D8ull) -#define CVMX_FPA_WART_STATUS \ - CVMX_ADD_IO_SEG(0x00011800280000E0ull) +#define CVMX_FPA_ADDR_RANGE_ERROR (CVMX_ADD_IO_SEG(0x0001180028000458ull)) +#define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull)) +#define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull)) +#define CVMX_FPA_FPF0_MARKS (CVMX_ADD_IO_SEG(0x0001180028000000ull)) +#define CVMX_FPA_FPF0_SIZE (CVMX_ADD_IO_SEG(0x0001180028000058ull)) +#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1) +#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2) +#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3) +#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4) +#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5) +#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6) +#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7) +#define CVMX_FPA_FPF8_MARKS (CVMX_ADD_IO_SEG(0x0001180028000240ull)) +#define CVMX_FPA_FPF8_SIZE (CVMX_ADD_IO_SEG(0x0001180028000248ull)) +#define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1) +#define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1) +#define CVMX_FPA_INT_ENB (CVMX_ADD_IO_SEG(0x0001180028000048ull)) +#define CVMX_FPA_INT_SUM (CVMX_ADD_IO_SEG(0x0001180028000040ull)) +#define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull)) +#define CVMX_FPA_POOLX_END_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8) +#define CVMX_FPA_POOLX_START_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8) +#define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8) +#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0) +#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1) +#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2) +#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3) +#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4) +#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5) +#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6) +#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7) +#define CVMX_FPA_QUE8_PAGE_INDEX (CVMX_ADD_IO_SEG(0x0001180028000250ull)) +#define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8) +#define CVMX_FPA_QUEX_PAGE_INDEX(offset) (CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8) +#define CVMX_FPA_QUE_ACT (CVMX_ADD_IO_SEG(0x0001180028000138ull)) +#define CVMX_FPA_QUE_EXP (CVMX_ADD_IO_SEG(0x0001180028000130ull)) +#define CVMX_FPA_WART_CTL (CVMX_ADD_IO_SEG(0x00011800280000D8ull)) +#define CVMX_FPA_WART_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E0ull)) +#define CVMX_FPA_WQE_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000468ull)) + +union cvmx_fpa_addr_range_error { + uint64_t u64; + struct cvmx_fpa_addr_range_error_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_38_63:26; + uint64_t pool:5; + uint64_t addr:33; +#else + uint64_t addr:33; + uint64_t pool:5; + uint64_t reserved_38_63:26; +#endif + } s; + struct cvmx_fpa_addr_range_error_s cn61xx; + struct cvmx_fpa_addr_range_error_s cn66xx; + struct cvmx_fpa_addr_range_error_s cn68xx; + struct cvmx_fpa_addr_range_error_s cn68xxp1; + struct cvmx_fpa_addr_range_error_s cnf71xx; +}; union cvmx_fpa_bist_status { uint64_t u64; struct cvmx_fpa_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t frd:1; uint64_t fpf0:1; uint64_t fpf1:1; uint64_t ffr:1; uint64_t fdr:1; +#else + uint64_t fdr:1; + uint64_t ffr:1; + uint64_t fpf1:1; + uint64_t fpf0:1; + uint64_t frd:1; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_fpa_bist_status_s cn30xx; struct cvmx_fpa_bist_status_s cn31xx; @@ -108,38 +117,92 @@ union cvmx_fpa_bist_status { struct cvmx_fpa_bist_status_s cn56xxp1; struct cvmx_fpa_bist_status_s cn58xx; struct cvmx_fpa_bist_status_s cn58xxp1; + struct cvmx_fpa_bist_status_s cn61xx; + struct cvmx_fpa_bist_status_s cn63xx; + struct cvmx_fpa_bist_status_s cn63xxp1; + struct cvmx_fpa_bist_status_s cn66xx; + struct cvmx_fpa_bist_status_s cn68xx; + struct cvmx_fpa_bist_status_s cn68xxp1; + struct cvmx_fpa_bist_status_s cnf71xx; }; union cvmx_fpa_ctl_status { uint64_t u64; struct cvmx_fpa_ctl_status_s { - uint64_t reserved_18_63:46; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_21_63:43; + uint64_t free_en:1; + uint64_t ret_off:1; + uint64_t req_off:1; uint64_t reset:1; uint64_t use_ldt:1; uint64_t use_stt:1; uint64_t enb:1; uint64_t mem1_err:7; uint64_t mem0_err:7; +#else + uint64_t mem0_err:7; + uint64_t mem1_err:7; + uint64_t enb:1; + uint64_t use_stt:1; + uint64_t use_ldt:1; + uint64_t reset:1; + uint64_t req_off:1; + uint64_t ret_off:1; + uint64_t free_en:1; + uint64_t reserved_21_63:43; +#endif } s; - struct cvmx_fpa_ctl_status_s cn30xx; - struct cvmx_fpa_ctl_status_s cn31xx; - struct cvmx_fpa_ctl_status_s cn38xx; - struct cvmx_fpa_ctl_status_s cn38xxp2; - struct cvmx_fpa_ctl_status_s cn50xx; - struct cvmx_fpa_ctl_status_s cn52xx; - struct cvmx_fpa_ctl_status_s cn52xxp1; - struct cvmx_fpa_ctl_status_s cn56xx; - struct cvmx_fpa_ctl_status_s cn56xxp1; - struct cvmx_fpa_ctl_status_s cn58xx; - struct cvmx_fpa_ctl_status_s cn58xxp1; + struct cvmx_fpa_ctl_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_18_63:46; + uint64_t reset:1; + uint64_t use_ldt:1; + uint64_t use_stt:1; + uint64_t enb:1; + uint64_t mem1_err:7; + uint64_t mem0_err:7; +#else + uint64_t mem0_err:7; + uint64_t mem1_err:7; + uint64_t enb:1; + uint64_t use_stt:1; + uint64_t use_ldt:1; + uint64_t reset:1; + uint64_t reserved_18_63:46; +#endif + } cn30xx; + struct cvmx_fpa_ctl_status_cn30xx cn31xx; + struct cvmx_fpa_ctl_status_cn30xx cn38xx; + struct cvmx_fpa_ctl_status_cn30xx cn38xxp2; + struct cvmx_fpa_ctl_status_cn30xx cn50xx; + struct cvmx_fpa_ctl_status_cn30xx cn52xx; + struct cvmx_fpa_ctl_status_cn30xx cn52xxp1; + struct cvmx_fpa_ctl_status_cn30xx cn56xx; + struct cvmx_fpa_ctl_status_cn30xx cn56xxp1; + struct cvmx_fpa_ctl_status_cn30xx cn58xx; + struct cvmx_fpa_ctl_status_cn30xx cn58xxp1; + struct cvmx_fpa_ctl_status_s cn61xx; + struct cvmx_fpa_ctl_status_s cn63xx; + struct cvmx_fpa_ctl_status_cn30xx cn63xxp1; + struct cvmx_fpa_ctl_status_s cn66xx; + struct cvmx_fpa_ctl_status_s cn68xx; + struct cvmx_fpa_ctl_status_s cn68xxp1; + struct cvmx_fpa_ctl_status_s cnf71xx; }; union cvmx_fpa_fpfx_marks { uint64_t u64; struct cvmx_fpa_fpfx_marks_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t fpf_wr:11; uint64_t fpf_rd:11; +#else + uint64_t fpf_rd:11; + uint64_t fpf_wr:11; + uint64_t reserved_22_63:42; +#endif } s; struct cvmx_fpa_fpfx_marks_s cn38xx; struct cvmx_fpa_fpfx_marks_s cn38xxp2; @@ -147,13 +210,25 @@ union cvmx_fpa_fpfx_marks { struct cvmx_fpa_fpfx_marks_s cn56xxp1; struct cvmx_fpa_fpfx_marks_s cn58xx; struct cvmx_fpa_fpfx_marks_s cn58xxp1; + struct cvmx_fpa_fpfx_marks_s cn61xx; + struct cvmx_fpa_fpfx_marks_s cn63xx; + struct cvmx_fpa_fpfx_marks_s cn63xxp1; + struct cvmx_fpa_fpfx_marks_s cn66xx; + struct cvmx_fpa_fpfx_marks_s cn68xx; + struct cvmx_fpa_fpfx_marks_s cn68xxp1; + struct cvmx_fpa_fpfx_marks_s cnf71xx; }; union cvmx_fpa_fpfx_size { uint64_t u64; struct cvmx_fpa_fpfx_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t fpf_siz:11; +#else + uint64_t fpf_siz:11; + uint64_t reserved_11_63:53; +#endif } s; struct cvmx_fpa_fpfx_size_s cn38xx; struct cvmx_fpa_fpfx_size_s cn38xxp2; @@ -161,14 +236,27 @@ union cvmx_fpa_fpfx_size { struct cvmx_fpa_fpfx_size_s cn56xxp1; struct cvmx_fpa_fpfx_size_s cn58xx; struct cvmx_fpa_fpfx_size_s cn58xxp1; + struct cvmx_fpa_fpfx_size_s cn61xx; + struct cvmx_fpa_fpfx_size_s cn63xx; + struct cvmx_fpa_fpfx_size_s cn63xxp1; + struct cvmx_fpa_fpfx_size_s cn66xx; + struct cvmx_fpa_fpfx_size_s cn68xx; + struct cvmx_fpa_fpfx_size_s cn68xxp1; + struct cvmx_fpa_fpfx_size_s cnf71xx; }; union cvmx_fpa_fpf0_marks { uint64_t u64; struct cvmx_fpa_fpf0_marks_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t fpf_wr:12; uint64_t fpf_rd:12; +#else + uint64_t fpf_rd:12; + uint64_t fpf_wr:12; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_fpa_fpf0_marks_s cn38xx; struct cvmx_fpa_fpf0_marks_s cn38xxp2; @@ -176,13 +264,25 @@ union cvmx_fpa_fpf0_marks { struct cvmx_fpa_fpf0_marks_s cn56xxp1; struct cvmx_fpa_fpf0_marks_s cn58xx; struct cvmx_fpa_fpf0_marks_s cn58xxp1; + struct cvmx_fpa_fpf0_marks_s cn61xx; + struct cvmx_fpa_fpf0_marks_s cn63xx; + struct cvmx_fpa_fpf0_marks_s cn63xxp1; + struct cvmx_fpa_fpf0_marks_s cn66xx; + struct cvmx_fpa_fpf0_marks_s cn68xx; + struct cvmx_fpa_fpf0_marks_s cn68xxp1; + struct cvmx_fpa_fpf0_marks_s cnf71xx; }; union cvmx_fpa_fpf0_size { uint64_t u64; struct cvmx_fpa_fpf0_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t fpf_siz:12; +#else + uint64_t fpf_siz:12; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_fpa_fpf0_size_s cn38xx; struct cvmx_fpa_fpf0_size_s cn38xxp2; @@ -190,12 +290,70 @@ union cvmx_fpa_fpf0_size { struct cvmx_fpa_fpf0_size_s cn56xxp1; struct cvmx_fpa_fpf0_size_s cn58xx; struct cvmx_fpa_fpf0_size_s cn58xxp1; + struct cvmx_fpa_fpf0_size_s cn61xx; + struct cvmx_fpa_fpf0_size_s cn63xx; + struct cvmx_fpa_fpf0_size_s cn63xxp1; + struct cvmx_fpa_fpf0_size_s cn66xx; + struct cvmx_fpa_fpf0_size_s cn68xx; + struct cvmx_fpa_fpf0_size_s cn68xxp1; + struct cvmx_fpa_fpf0_size_s cnf71xx; +}; + +union cvmx_fpa_fpf8_marks { + uint64_t u64; + struct cvmx_fpa_fpf8_marks_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_22_63:42; + uint64_t fpf_wr:11; + uint64_t fpf_rd:11; +#else + uint64_t fpf_rd:11; + uint64_t fpf_wr:11; + uint64_t reserved_22_63:42; +#endif + } s; + struct cvmx_fpa_fpf8_marks_s cn68xx; + struct cvmx_fpa_fpf8_marks_s cn68xxp1; +}; + +union cvmx_fpa_fpf8_size { + uint64_t u64; + struct cvmx_fpa_fpf8_size_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t fpf_siz:12; +#else + uint64_t fpf_siz:12; + uint64_t reserved_12_63:52; +#endif + } s; + struct cvmx_fpa_fpf8_size_s cn68xx; + struct cvmx_fpa_fpf8_size_s cn68xxp1; }; union cvmx_fpa_int_enb { uint64_t u64; struct cvmx_fpa_int_enb_s { - uint64_t reserved_28_63:36; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_50_63:14; + uint64_t paddr_e:1; + uint64_t reserved_44_48:5; + uint64_t free7:1; + uint64_t free6:1; + uint64_t free5:1; + uint64_t free4:1; + uint64_t free3:1; + uint64_t free2:1; + uint64_t free1:1; + uint64_t free0:1; + uint64_t pool7th:1; + uint64_t pool6th:1; + uint64_t pool5th:1; + uint64_t pool4th:1; + uint64_t pool3th:1; + uint64_t pool2th:1; + uint64_t pool1th:1; + uint64_t pool0th:1; uint64_t q7_perr:1; uint64_t q7_coff:1; uint64_t q7_und:1; @@ -224,23 +382,547 @@ union cvmx_fpa_int_enb { uint64_t fed1_sbe:1; uint64_t fed0_dbe:1; uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t pool0th:1; + uint64_t pool1th:1; + uint64_t pool2th:1; + uint64_t pool3th:1; + uint64_t pool4th:1; + uint64_t pool5th:1; + uint64_t pool6th:1; + uint64_t pool7th:1; + uint64_t free0:1; + uint64_t free1:1; + uint64_t free2:1; + uint64_t free3:1; + uint64_t free4:1; + uint64_t free5:1; + uint64_t free6:1; + uint64_t free7:1; + uint64_t reserved_44_48:5; + uint64_t paddr_e:1; + uint64_t reserved_50_63:14; +#endif } s; - struct cvmx_fpa_int_enb_s cn30xx; - struct cvmx_fpa_int_enb_s cn31xx; - struct cvmx_fpa_int_enb_s cn38xx; - struct cvmx_fpa_int_enb_s cn38xxp2; - struct cvmx_fpa_int_enb_s cn50xx; - struct cvmx_fpa_int_enb_s cn52xx; - struct cvmx_fpa_int_enb_s cn52xxp1; - struct cvmx_fpa_int_enb_s cn56xx; - struct cvmx_fpa_int_enb_s cn56xxp1; - struct cvmx_fpa_int_enb_s cn58xx; - struct cvmx_fpa_int_enb_s cn58xxp1; + struct cvmx_fpa_int_enb_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_28_63:36; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t reserved_28_63:36; +#endif + } cn30xx; + struct cvmx_fpa_int_enb_cn30xx cn31xx; + struct cvmx_fpa_int_enb_cn30xx cn38xx; + struct cvmx_fpa_int_enb_cn30xx cn38xxp2; + struct cvmx_fpa_int_enb_cn30xx cn50xx; + struct cvmx_fpa_int_enb_cn30xx cn52xx; + struct cvmx_fpa_int_enb_cn30xx cn52xxp1; + struct cvmx_fpa_int_enb_cn30xx cn56xx; + struct cvmx_fpa_int_enb_cn30xx cn56xxp1; + struct cvmx_fpa_int_enb_cn30xx cn58xx; + struct cvmx_fpa_int_enb_cn30xx cn58xxp1; + struct cvmx_fpa_int_enb_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_50_63:14; + uint64_t paddr_e:1; + uint64_t res_44:5; + uint64_t free7:1; + uint64_t free6:1; + uint64_t free5:1; + uint64_t free4:1; + uint64_t free3:1; + uint64_t free2:1; + uint64_t free1:1; + uint64_t free0:1; + uint64_t pool7th:1; + uint64_t pool6th:1; + uint64_t pool5th:1; + uint64_t pool4th:1; + uint64_t pool3th:1; + uint64_t pool2th:1; + uint64_t pool1th:1; + uint64_t pool0th:1; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t pool0th:1; + uint64_t pool1th:1; + uint64_t pool2th:1; + uint64_t pool3th:1; + uint64_t pool4th:1; + uint64_t pool5th:1; + uint64_t pool6th:1; + uint64_t pool7th:1; + uint64_t free0:1; + uint64_t free1:1; + uint64_t free2:1; + uint64_t free3:1; + uint64_t free4:1; + uint64_t free5:1; + uint64_t free6:1; + uint64_t free7:1; + uint64_t res_44:5; + uint64_t paddr_e:1; + uint64_t reserved_50_63:14; +#endif + } cn61xx; + struct cvmx_fpa_int_enb_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_44_63:20; + uint64_t free7:1; + uint64_t free6:1; + uint64_t free5:1; + uint64_t free4:1; + uint64_t free3:1; + uint64_t free2:1; + uint64_t free1:1; + uint64_t free0:1; + uint64_t pool7th:1; + uint64_t pool6th:1; + uint64_t pool5th:1; + uint64_t pool4th:1; + uint64_t pool3th:1; + uint64_t pool2th:1; + uint64_t pool1th:1; + uint64_t pool0th:1; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t pool0th:1; + uint64_t pool1th:1; + uint64_t pool2th:1; + uint64_t pool3th:1; + uint64_t pool4th:1; + uint64_t pool5th:1; + uint64_t pool6th:1; + uint64_t pool7th:1; + uint64_t free0:1; + uint64_t free1:1; + uint64_t free2:1; + uint64_t free3:1; + uint64_t free4:1; + uint64_t free5:1; + uint64_t free6:1; + uint64_t free7:1; + uint64_t reserved_44_63:20; +#endif + } cn63xx; + struct cvmx_fpa_int_enb_cn30xx cn63xxp1; + struct cvmx_fpa_int_enb_cn61xx cn66xx; + struct cvmx_fpa_int_enb_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_50_63:14; + uint64_t paddr_e:1; + uint64_t pool8th:1; + uint64_t q8_perr:1; + uint64_t q8_coff:1; + uint64_t q8_und:1; + uint64_t free8:1; + uint64_t free7:1; + uint64_t free6:1; + uint64_t free5:1; + uint64_t free4:1; + uint64_t free3:1; + uint64_t free2:1; + uint64_t free1:1; + uint64_t free0:1; + uint64_t pool7th:1; + uint64_t pool6th:1; + uint64_t pool5th:1; + uint64_t pool4th:1; + uint64_t pool3th:1; + uint64_t pool2th:1; + uint64_t pool1th:1; + uint64_t pool0th:1; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t pool0th:1; + uint64_t pool1th:1; + uint64_t pool2th:1; + uint64_t pool3th:1; + uint64_t pool4th:1; + uint64_t pool5th:1; + uint64_t pool6th:1; + uint64_t pool7th:1; + uint64_t free0:1; + uint64_t free1:1; + uint64_t free2:1; + uint64_t free3:1; + uint64_t free4:1; + uint64_t free5:1; + uint64_t free6:1; + uint64_t free7:1; + uint64_t free8:1; + uint64_t q8_und:1; + uint64_t q8_coff:1; + uint64_t q8_perr:1; + uint64_t pool8th:1; + uint64_t paddr_e:1; + uint64_t reserved_50_63:14; +#endif + } cn68xx; + struct cvmx_fpa_int_enb_cn68xx cn68xxp1; + struct cvmx_fpa_int_enb_cn61xx cnf71xx; }; union cvmx_fpa_int_sum { uint64_t u64; struct cvmx_fpa_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_50_63:14; + uint64_t paddr_e:1; + uint64_t pool8th:1; + uint64_t q8_perr:1; + uint64_t q8_coff:1; + uint64_t q8_und:1; + uint64_t free8:1; + uint64_t free7:1; + uint64_t free6:1; + uint64_t free5:1; + uint64_t free4:1; + uint64_t free3:1; + uint64_t free2:1; + uint64_t free1:1; + uint64_t free0:1; + uint64_t pool7th:1; + uint64_t pool6th:1; + uint64_t pool5th:1; + uint64_t pool4th:1; + uint64_t pool3th:1; + uint64_t pool2th:1; + uint64_t pool1th:1; + uint64_t pool0th:1; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t pool0th:1; + uint64_t pool1th:1; + uint64_t pool2th:1; + uint64_t pool3th:1; + uint64_t pool4th:1; + uint64_t pool5th:1; + uint64_t pool6th:1; + uint64_t pool7th:1; + uint64_t free0:1; + uint64_t free1:1; + uint64_t free2:1; + uint64_t free3:1; + uint64_t free4:1; + uint64_t free5:1; + uint64_t free6:1; + uint64_t free7:1; + uint64_t free8:1; + uint64_t q8_und:1; + uint64_t q8_coff:1; + uint64_t q8_perr:1; + uint64_t pool8th:1; + uint64_t paddr_e:1; + uint64_t reserved_50_63:14; +#endif + } s; + struct cvmx_fpa_int_sum_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t q7_perr:1; uint64_t q7_coff:1; @@ -270,44 +952,380 @@ union cvmx_fpa_int_sum { uint64_t fed1_sbe:1; uint64_t fed0_dbe:1; uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t reserved_28_63:36; +#endif + } cn30xx; + struct cvmx_fpa_int_sum_cn30xx cn31xx; + struct cvmx_fpa_int_sum_cn30xx cn38xx; + struct cvmx_fpa_int_sum_cn30xx cn38xxp2; + struct cvmx_fpa_int_sum_cn30xx cn50xx; + struct cvmx_fpa_int_sum_cn30xx cn52xx; + struct cvmx_fpa_int_sum_cn30xx cn52xxp1; + struct cvmx_fpa_int_sum_cn30xx cn56xx; + struct cvmx_fpa_int_sum_cn30xx cn56xxp1; + struct cvmx_fpa_int_sum_cn30xx cn58xx; + struct cvmx_fpa_int_sum_cn30xx cn58xxp1; + struct cvmx_fpa_int_sum_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_50_63:14; + uint64_t paddr_e:1; + uint64_t reserved_44_48:5; + uint64_t free7:1; + uint64_t free6:1; + uint64_t free5:1; + uint64_t free4:1; + uint64_t free3:1; + uint64_t free2:1; + uint64_t free1:1; + uint64_t free0:1; + uint64_t pool7th:1; + uint64_t pool6th:1; + uint64_t pool5th:1; + uint64_t pool4th:1; + uint64_t pool3th:1; + uint64_t pool2th:1; + uint64_t pool1th:1; + uint64_t pool0th:1; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t pool0th:1; + uint64_t pool1th:1; + uint64_t pool2th:1; + uint64_t pool3th:1; + uint64_t pool4th:1; + uint64_t pool5th:1; + uint64_t pool6th:1; + uint64_t pool7th:1; + uint64_t free0:1; + uint64_t free1:1; + uint64_t free2:1; + uint64_t free3:1; + uint64_t free4:1; + uint64_t free5:1; + uint64_t free6:1; + uint64_t free7:1; + uint64_t reserved_44_48:5; + uint64_t paddr_e:1; + uint64_t reserved_50_63:14; +#endif + } cn61xx; + struct cvmx_fpa_int_sum_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_44_63:20; + uint64_t free7:1; + uint64_t free6:1; + uint64_t free5:1; + uint64_t free4:1; + uint64_t free3:1; + uint64_t free2:1; + uint64_t free1:1; + uint64_t free0:1; + uint64_t pool7th:1; + uint64_t pool6th:1; + uint64_t pool5th:1; + uint64_t pool4th:1; + uint64_t pool3th:1; + uint64_t pool2th:1; + uint64_t pool1th:1; + uint64_t pool0th:1; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; +#else + uint64_t fed0_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed1_dbe:1; + uint64_t q0_und:1; + uint64_t q0_coff:1; + uint64_t q0_perr:1; + uint64_t q1_und:1; + uint64_t q1_coff:1; + uint64_t q1_perr:1; + uint64_t q2_und:1; + uint64_t q2_coff:1; + uint64_t q2_perr:1; + uint64_t q3_und:1; + uint64_t q3_coff:1; + uint64_t q3_perr:1; + uint64_t q4_und:1; + uint64_t q4_coff:1; + uint64_t q4_perr:1; + uint64_t q5_und:1; + uint64_t q5_coff:1; + uint64_t q5_perr:1; + uint64_t q6_und:1; + uint64_t q6_coff:1; + uint64_t q6_perr:1; + uint64_t q7_und:1; + uint64_t q7_coff:1; + uint64_t q7_perr:1; + uint64_t pool0th:1; + uint64_t pool1th:1; + uint64_t pool2th:1; + uint64_t pool3th:1; + uint64_t pool4th:1; + uint64_t pool5th:1; + uint64_t pool6th:1; + uint64_t pool7th:1; + uint64_t free0:1; + uint64_t free1:1; + uint64_t free2:1; + uint64_t free3:1; + uint64_t free4:1; + uint64_t free5:1; + uint64_t free6:1; + uint64_t free7:1; + uint64_t reserved_44_63:20; +#endif + } cn63xx; + struct cvmx_fpa_int_sum_cn30xx cn63xxp1; + struct cvmx_fpa_int_sum_cn61xx cn66xx; + struct cvmx_fpa_int_sum_s cn68xx; + struct cvmx_fpa_int_sum_s cn68xxp1; + struct cvmx_fpa_int_sum_cn61xx cnf71xx; +}; + +union cvmx_fpa_packet_threshold { + uint64_t u64; + struct cvmx_fpa_packet_threshold_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t thresh:32; +#else + uint64_t thresh:32; + uint64_t reserved_32_63:32; +#endif } s; - struct cvmx_fpa_int_sum_s cn30xx; - struct cvmx_fpa_int_sum_s cn31xx; - struct cvmx_fpa_int_sum_s cn38xx; - struct cvmx_fpa_int_sum_s cn38xxp2; - struct cvmx_fpa_int_sum_s cn50xx; - struct cvmx_fpa_int_sum_s cn52xx; - struct cvmx_fpa_int_sum_s cn52xxp1; - struct cvmx_fpa_int_sum_s cn56xx; - struct cvmx_fpa_int_sum_s cn56xxp1; - struct cvmx_fpa_int_sum_s cn58xx; - struct cvmx_fpa_int_sum_s cn58xxp1; + struct cvmx_fpa_packet_threshold_s cn61xx; + struct cvmx_fpa_packet_threshold_s cn63xx; + struct cvmx_fpa_packet_threshold_s cn66xx; + struct cvmx_fpa_packet_threshold_s cn68xx; + struct cvmx_fpa_packet_threshold_s cn68xxp1; + struct cvmx_fpa_packet_threshold_s cnf71xx; +}; + +union cvmx_fpa_poolx_end_addr { + uint64_t u64; + struct cvmx_fpa_poolx_end_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t addr:33; +#else + uint64_t addr:33; + uint64_t reserved_33_63:31; +#endif + } s; + struct cvmx_fpa_poolx_end_addr_s cn61xx; + struct cvmx_fpa_poolx_end_addr_s cn66xx; + struct cvmx_fpa_poolx_end_addr_s cn68xx; + struct cvmx_fpa_poolx_end_addr_s cn68xxp1; + struct cvmx_fpa_poolx_end_addr_s cnf71xx; +}; + +union cvmx_fpa_poolx_start_addr { + uint64_t u64; + struct cvmx_fpa_poolx_start_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t addr:33; +#else + uint64_t addr:33; + uint64_t reserved_33_63:31; +#endif + } s; + struct cvmx_fpa_poolx_start_addr_s cn61xx; + struct cvmx_fpa_poolx_start_addr_s cn66xx; + struct cvmx_fpa_poolx_start_addr_s cn68xx; + struct cvmx_fpa_poolx_start_addr_s cn68xxp1; + struct cvmx_fpa_poolx_start_addr_s cnf71xx; +}; + +union cvmx_fpa_poolx_threshold { + uint64_t u64; + struct cvmx_fpa_poolx_threshold_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t thresh:32; +#else + uint64_t thresh:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_fpa_poolx_threshold_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t thresh:29; +#else + uint64_t thresh:29; + uint64_t reserved_29_63:35; +#endif + } cn61xx; + struct cvmx_fpa_poolx_threshold_cn61xx cn63xx; + struct cvmx_fpa_poolx_threshold_cn61xx cn66xx; + struct cvmx_fpa_poolx_threshold_s cn68xx; + struct cvmx_fpa_poolx_threshold_s cn68xxp1; + struct cvmx_fpa_poolx_threshold_cn61xx cnf71xx; }; union cvmx_fpa_quex_available { uint64_t u64; struct cvmx_fpa_quex_available_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t que_siz:32; +#else + uint64_t que_siz:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_fpa_quex_available_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t que_siz:29; - } s; - struct cvmx_fpa_quex_available_s cn30xx; - struct cvmx_fpa_quex_available_s cn31xx; - struct cvmx_fpa_quex_available_s cn38xx; - struct cvmx_fpa_quex_available_s cn38xxp2; - struct cvmx_fpa_quex_available_s cn50xx; - struct cvmx_fpa_quex_available_s cn52xx; - struct cvmx_fpa_quex_available_s cn52xxp1; - struct cvmx_fpa_quex_available_s cn56xx; - struct cvmx_fpa_quex_available_s cn56xxp1; - struct cvmx_fpa_quex_available_s cn58xx; - struct cvmx_fpa_quex_available_s cn58xxp1; +#else + uint64_t que_siz:29; + uint64_t reserved_29_63:35; +#endif + } cn30xx; + struct cvmx_fpa_quex_available_cn30xx cn31xx; + struct cvmx_fpa_quex_available_cn30xx cn38xx; + struct cvmx_fpa_quex_available_cn30xx cn38xxp2; + struct cvmx_fpa_quex_available_cn30xx cn50xx; + struct cvmx_fpa_quex_available_cn30xx cn52xx; + struct cvmx_fpa_quex_available_cn30xx cn52xxp1; + struct cvmx_fpa_quex_available_cn30xx cn56xx; + struct cvmx_fpa_quex_available_cn30xx cn56xxp1; + struct cvmx_fpa_quex_available_cn30xx cn58xx; + struct cvmx_fpa_quex_available_cn30xx cn58xxp1; + struct cvmx_fpa_quex_available_cn30xx cn61xx; + struct cvmx_fpa_quex_available_cn30xx cn63xx; + struct cvmx_fpa_quex_available_cn30xx cn63xxp1; + struct cvmx_fpa_quex_available_cn30xx cn66xx; + struct cvmx_fpa_quex_available_s cn68xx; + struct cvmx_fpa_quex_available_s cn68xxp1; + struct cvmx_fpa_quex_available_cn30xx cnf71xx; }; union cvmx_fpa_quex_page_index { uint64_t u64; struct cvmx_fpa_quex_page_index_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t pg_num:25; +#else + uint64_t pg_num:25; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_fpa_quex_page_index_s cn30xx; struct cvmx_fpa_quex_page_index_s cn31xx; @@ -320,14 +1338,42 @@ union cvmx_fpa_quex_page_index { struct cvmx_fpa_quex_page_index_s cn56xxp1; struct cvmx_fpa_quex_page_index_s cn58xx; struct cvmx_fpa_quex_page_index_s cn58xxp1; + struct cvmx_fpa_quex_page_index_s cn61xx; + struct cvmx_fpa_quex_page_index_s cn63xx; + struct cvmx_fpa_quex_page_index_s cn63xxp1; + struct cvmx_fpa_quex_page_index_s cn66xx; + struct cvmx_fpa_quex_page_index_s cn68xx; + struct cvmx_fpa_quex_page_index_s cn68xxp1; + struct cvmx_fpa_quex_page_index_s cnf71xx; +}; + +union cvmx_fpa_que8_page_index { + uint64_t u64; + struct cvmx_fpa_que8_page_index_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t pg_num:25; +#else + uint64_t pg_num:25; + uint64_t reserved_25_63:39; +#endif + } s; + struct cvmx_fpa_que8_page_index_s cn68xx; + struct cvmx_fpa_que8_page_index_s cn68xxp1; }; union cvmx_fpa_que_act { uint64_t u64; struct cvmx_fpa_que_act_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t act_que:3; uint64_t act_indx:26; +#else + uint64_t act_indx:26; + uint64_t act_que:3; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_fpa_que_act_s cn30xx; struct cvmx_fpa_que_act_s cn31xx; @@ -340,14 +1386,27 @@ union cvmx_fpa_que_act { struct cvmx_fpa_que_act_s cn56xxp1; struct cvmx_fpa_que_act_s cn58xx; struct cvmx_fpa_que_act_s cn58xxp1; + struct cvmx_fpa_que_act_s cn61xx; + struct cvmx_fpa_que_act_s cn63xx; + struct cvmx_fpa_que_act_s cn63xxp1; + struct cvmx_fpa_que_act_s cn66xx; + struct cvmx_fpa_que_act_s cn68xx; + struct cvmx_fpa_que_act_s cn68xxp1; + struct cvmx_fpa_que_act_s cnf71xx; }; union cvmx_fpa_que_exp { uint64_t u64; struct cvmx_fpa_que_exp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t exp_que:3; uint64_t exp_indx:26; +#else + uint64_t exp_indx:26; + uint64_t exp_que:3; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_fpa_que_exp_s cn30xx; struct cvmx_fpa_que_exp_s cn31xx; @@ -360,13 +1419,25 @@ union cvmx_fpa_que_exp { struct cvmx_fpa_que_exp_s cn56xxp1; struct cvmx_fpa_que_exp_s cn58xx; struct cvmx_fpa_que_exp_s cn58xxp1; + struct cvmx_fpa_que_exp_s cn61xx; + struct cvmx_fpa_que_exp_s cn63xx; + struct cvmx_fpa_que_exp_s cn63xxp1; + struct cvmx_fpa_que_exp_s cn66xx; + struct cvmx_fpa_que_exp_s cn68xx; + struct cvmx_fpa_que_exp_s cn68xxp1; + struct cvmx_fpa_que_exp_s cnf71xx; }; union cvmx_fpa_wart_ctl { uint64_t u64; struct cvmx_fpa_wart_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ctl:16; +#else + uint64_t ctl:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_fpa_wart_ctl_s cn30xx; struct cvmx_fpa_wart_ctl_s cn31xx; @@ -384,8 +1455,13 @@ union cvmx_fpa_wart_ctl { union cvmx_fpa_wart_status { uint64_t u64; struct cvmx_fpa_wart_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t status:32; +#else + uint64_t status:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_fpa_wart_status_s cn30xx; struct cvmx_fpa_wart_status_s cn31xx; @@ -400,4 +1476,23 @@ union cvmx_fpa_wart_status { struct cvmx_fpa_wart_status_s cn58xxp1; }; +union cvmx_fpa_wqe_threshold { + uint64_t u64; + struct cvmx_fpa_wqe_threshold_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t thresh:32; +#else + uint64_t thresh:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_fpa_wqe_threshold_s cn61xx; + struct cvmx_fpa_wqe_threshold_s cn63xx; + struct cvmx_fpa_wqe_threshold_s cn66xx; + struct cvmx_fpa_wqe_threshold_s cn68xx; + struct cvmx_fpa_wqe_threshold_s cn68xxp1; + struct cvmx_fpa_wqe_threshold_s cnf71xx; +}; + #endif diff --git a/arch/mips/include/asm/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h index 1f04f965873..aa26a2ce5a0 100644 --- a/arch/mips/include/asm/octeon/cvmx-fpa.h +++ b/arch/mips/include/asm/octeon/cvmx-fpa.h @@ -36,12 +36,12 @@ #ifndef __CVMX_FPA_H__ #define __CVMX_FPA_H__ -#include "cvmx-address.h" -#include "cvmx-fpa-defs.h" +#include <asm/octeon/cvmx-address.h> +#include <asm/octeon/cvmx-fpa-defs.h> -#define CVMX_FPA_NUM_POOLS 8 +#define CVMX_FPA_NUM_POOLS 8 #define CVMX_FPA_MIN_BLOCK_SIZE 128 -#define CVMX_FPA_ALIGNMENT 128 +#define CVMX_FPA_ALIGNMENT 128 /** * Structure describing the data format used for stores to the FPA. @@ -186,8 +186,8 @@ static inline void *cvmx_fpa_alloc(uint64_t pool) /** * Asynchronously get a new block from the FPA * - * @scr_addr: Local scratch address to put response in. This is a byte address, - * but must be 8 byte aligned. + * @scr_addr: Local scratch address to put response in. This is a byte address, + * but must be 8 byte aligned. * @pool: Pool to get the block from */ static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool) @@ -212,7 +212,7 @@ static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool) * @ptr: Block to free * @pool: Pool to put it in * @num_cache_lines: - * Cache lines to invalidate + * Cache lines to invalidate */ static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool, uint64_t num_cache_lines) @@ -234,7 +234,7 @@ static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool, * @ptr: Block to free * @pool: Pool to put it in * @num_cache_lines: - * Cache lines to invalidate + * Cache lines to invalidate */ static inline void cvmx_fpa_free(void *ptr, uint64_t pool, uint64_t num_cache_lines) @@ -245,7 +245,7 @@ static inline void cvmx_fpa_free(void *ptr, uint64_t pool, CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)); /* * Make sure that any previous writes to memory go out before - * we free this buffer. This also serves as a barrier to + * we free this buffer. This also serves as a barrier to * prevent GCC from reordering operations to after the * free. */ @@ -259,17 +259,17 @@ static inline void cvmx_fpa_free(void *ptr, uint64_t pool, * This can only be called once per pool. Make sure proper * locking enforces this. * - * @pool: Pool to initialize - * 0 <= pool < 8 - * @name: Constant character string to name this pool. - * String is not copied. - * @buffer: Pointer to the block of memory to use. This must be - * accessible by all processors and external hardware. + * @pool: Pool to initialize + * 0 <= pool < 8 + * @name: Constant character string to name this pool. + * String is not copied. + * @buffer: Pointer to the block of memory to use. This must be + * accessible by all processors and external hardware. * @block_size: Size for each block controlled by the FPA * @num_blocks: Number of blocks * * Returns 0 on Success, - * -1 on failure + * -1 on failure */ extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer, uint64_t block_size, uint64_t num_blocks); @@ -282,8 +282,8 @@ extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer, * * @pool: Pool to shutdown * Returns Zero on success - * - Positive is count of missing buffers - * - Negative is too many buffers or corrupted pointers + * - Positive is count of missing buffers + * - Negative is too many buffers or corrupted pointers */ extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool); diff --git a/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h index 946a43a73fd..e347496a33c 100644 --- a/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,208 +28,2052 @@ #ifndef __CVMX_GMXX_DEFS_H__ #define __CVMX_GMXX_DEFS_H__ -#define CVMX_GMXX_BAD_REG(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000518ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_BIST(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000400ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_CLK_EN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080007F0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_HG2_CONTROL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000550ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_INF_MODE(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080007F8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_NXA_ADR(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000510ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_PRTX_CBFC_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000580ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_PRTX_CFG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000010ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM0(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000180ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM1(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000188ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM2(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000190ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM3(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000198ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM4(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080001A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM5(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080001A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM_EN(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000108ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000100ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_DECISION(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000040ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_FRM_CHK(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000020ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_FRM_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000018ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000030ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000028ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_IFG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000058ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_INT_EN(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000008ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_INT_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000000ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_JABBER(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000038ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_PAUSE_DROP_TIME(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000068ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000060ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000050ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_OCTS(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000088ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_OCTS_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000098ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_OCTS_DMAC(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080000A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_OCTS_DRP(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080000B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_PKTS(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000080ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_PKTS_BAD(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080000C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_PKTS_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000090ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_PKTS_DMAC(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080000A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_PKTS_DRP(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080000B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_UDD_SKP(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000048ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_BP_DROPX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000420ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_BP_OFFX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000460ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_BP_ONX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000440ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_HG2_STATUS(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000548ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_PASS_EN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080005F8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000600ull + (((offset) & 15) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_PRTS(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000410ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_PRT_INFO(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004E8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_TX_STATUS(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080007E8ull + (((block_id) & 0) * 0x8000000ull)) -#define CVMX_GMXX_RX_XAUI_BAD_COL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000538ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_XAUI_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000530ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_SMACX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000230ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_STAT_BP(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000520ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_APPEND(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000218ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_BURST(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000228ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_CBFC_XOFF(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080005A0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_CBFC_XON(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080005C0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_CLK(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000208ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000270ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_MIN_PKT(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000240ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000248ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_PAUSE_PKT_TIME(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000238ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_PAUSE_TOGO(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000258ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_PAUSE_ZERO(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000260ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_SGMII_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000300ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_SLOT(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000220ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_SOFT_PAUSE(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000250ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT0(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000280ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT1(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000288ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT2(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000290ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT3(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000298ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT4(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT5(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT6(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT7(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT8(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT9(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002C8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STATS_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000268ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_THRESH(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000210ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_BP(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004D0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000780ull + (((offset) & 1) * 8) + (((block_id) & 0) * 0x0ull)) -#define CVMX_GMXX_TX_COL_ATTEMPT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000498ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_CORRUPT(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004D8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_HG2_REG1(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000558ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_HG2_REG2(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000560ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_IFG(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000488ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_INT_EN(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000508ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_INT_REG(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000500ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_JAM(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000490ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_LFSR(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004F8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_OVR_BP(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004C8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_PAUSE_PKT_DMAC(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004A0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_PAUSE_PKT_TYPE(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004A8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_PRTS(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000480ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_SPI_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004C0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_SPI_DRAIN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004E0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_SPI_MAX(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004B0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000680ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_SPI_THRESH(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004B8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_XAUI_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000528ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_XAUI_EXT_LOOPBACK(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000540ull + (((block_id) & 1) * 0x8000000ull)) +static inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_BIST(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_BPID_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8) +#define CVMX_GMXX_BPID_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000700ull) + ((block_id) & 7) * 0x1000000ull) +static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_EBP_DIS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000608ull) + ((block_id) & 7) * 0x1000000ull) +#define CVMX_GMXX_EBP_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((block_id) & 7) * 0x1000000ull) +static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_PIPE_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000760ull) + ((block_id) & 7) * 0x1000000ull) +static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +#define CVMX_GMXX_RXAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000740ull) + ((block_id) & 7) * 0x1000000ull) +static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_ALL_EN(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) +#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) +static inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) +static inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x0ull) * 8; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x200000ull) * 8; + } + return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; +} + +static inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x0ull) * 8; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x200000ull) * 8; + } + return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; +} + +static inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x0ull) * 8; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x200000ull) * 8; + } + return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; +} + +static inline uint64_t CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_RX_PASS_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800080005F8ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8) +static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_RX_PRT_INFO(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_RX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800080007E8ull)) +static inline uint64_t CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_SOFT_BIST(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_GMXX_STAT_BP(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TB_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) +static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +#define CVMX_GMXX_TXX_PIPE(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000310ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048) +static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline uint64_t CVMX_GMXX_TX_BP(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000780ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8) +static inline uint64_t CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_CORRUPT(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_HG2_REG1(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_HG2_REG2(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_IFG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_JAM(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_LFSR(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_GMXX_TX_SPI_DRAIN(block_id) (CVMX_ADD_IO_SEG(0x00011800080004E0ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull) +static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull; +} + +static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull; +} union cvmx_gmxx_bad_reg { uint64_t u64; struct cvmx_gmxx_bad_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t inb_nxa:4; uint64_t statovr:1; @@ -238,8 +2082,19 @@ union cvmx_gmxx_bad_reg { uint64_t out_ovr:16; uint64_t ncb_ovr:1; uint64_t out_col:1; +#else + uint64_t out_col:1; + uint64_t ncb_ovr:1; + uint64_t out_ovr:16; + uint64_t reserved_18_21:4; + uint64_t loststat:4; + uint64_t statovr:1; + uint64_t inb_nxa:4; + uint64_t reserved_31_63:33; +#endif } s; struct cvmx_gmxx_bad_reg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t inb_nxa:4; uint64_t statovr:1; @@ -248,12 +2103,23 @@ union cvmx_gmxx_bad_reg { uint64_t reserved_5_21:17; uint64_t out_ovr:3; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t out_ovr:3; + uint64_t reserved_5_21:17; + uint64_t loststat:3; + uint64_t reserved_25_25:1; + uint64_t statovr:1; + uint64_t inb_nxa:4; + uint64_t reserved_31_63:33; +#endif } cn30xx; struct cvmx_gmxx_bad_reg_cn30xx cn31xx; struct cvmx_gmxx_bad_reg_s cn38xx; struct cvmx_gmxx_bad_reg_s cn38xxp2; struct cvmx_gmxx_bad_reg_cn30xx cn50xx; struct cvmx_gmxx_bad_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t inb_nxa:4; uint64_t statovr:1; @@ -261,95 +2127,274 @@ union cvmx_gmxx_bad_reg { uint64_t reserved_6_21:16; uint64_t out_ovr:4; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t out_ovr:4; + uint64_t reserved_6_21:16; + uint64_t loststat:4; + uint64_t statovr:1; + uint64_t inb_nxa:4; + uint64_t reserved_31_63:33; +#endif } cn52xx; struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1; struct cvmx_gmxx_bad_reg_cn52xx cn56xx; struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1; struct cvmx_gmxx_bad_reg_s cn58xx; struct cvmx_gmxx_bad_reg_s cn58xxp1; + struct cvmx_gmxx_bad_reg_cn52xx cn61xx; + struct cvmx_gmxx_bad_reg_cn52xx cn63xx; + struct cvmx_gmxx_bad_reg_cn52xx cn63xxp1; + struct cvmx_gmxx_bad_reg_cn52xx cn66xx; + struct cvmx_gmxx_bad_reg_cn52xx cn68xx; + struct cvmx_gmxx_bad_reg_cn52xx cn68xxp1; + struct cvmx_gmxx_bad_reg_cn52xx cnf71xx; }; union cvmx_gmxx_bist { uint64_t u64; struct cvmx_gmxx_bist_s { - uint64_t reserved_17_63:47; - uint64_t status:17; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t status:25; +#else + uint64_t status:25; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_gmxx_bist_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t status:10; +#else + uint64_t status:10; + uint64_t reserved_10_63:54; +#endif } cn30xx; struct cvmx_gmxx_bist_cn30xx cn31xx; struct cvmx_gmxx_bist_cn30xx cn38xx; struct cvmx_gmxx_bist_cn30xx cn38xxp2; struct cvmx_gmxx_bist_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t status:12; +#else + uint64_t status:12; + uint64_t reserved_12_63:52; +#endif } cn50xx; struct cvmx_gmxx_bist_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t status:16; +#else + uint64_t status:16; + uint64_t reserved_16_63:48; +#endif } cn52xx; struct cvmx_gmxx_bist_cn52xx cn52xxp1; struct cvmx_gmxx_bist_cn52xx cn56xx; struct cvmx_gmxx_bist_cn52xx cn56xxp1; - struct cvmx_gmxx_bist_s cn58xx; - struct cvmx_gmxx_bist_s cn58xxp1; + struct cvmx_gmxx_bist_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_17_63:47; + uint64_t status:17; +#else + uint64_t status:17; + uint64_t reserved_17_63:47; +#endif + } cn58xx; + struct cvmx_gmxx_bist_cn58xx cn58xxp1; + struct cvmx_gmxx_bist_s cn61xx; + struct cvmx_gmxx_bist_s cn63xx; + struct cvmx_gmxx_bist_s cn63xxp1; + struct cvmx_gmxx_bist_s cn66xx; + struct cvmx_gmxx_bist_s cn68xx; + struct cvmx_gmxx_bist_s cn68xxp1; + struct cvmx_gmxx_bist_s cnf71xx; +}; + +union cvmx_gmxx_bpid_mapx { + uint64_t u64; + struct cvmx_gmxx_bpid_mapx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_17_63:47; + uint64_t status:1; + uint64_t reserved_9_15:7; + uint64_t val:1; + uint64_t reserved_6_7:2; + uint64_t bpid:6; +#else + uint64_t bpid:6; + uint64_t reserved_6_7:2; + uint64_t val:1; + uint64_t reserved_9_15:7; + uint64_t status:1; + uint64_t reserved_17_63:47; +#endif + } s; + struct cvmx_gmxx_bpid_mapx_s cn68xx; + struct cvmx_gmxx_bpid_mapx_s cn68xxp1; +}; + +union cvmx_gmxx_bpid_msk { + uint64_t u64; + struct cvmx_gmxx_bpid_msk_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t msk_or:16; + uint64_t reserved_16_31:16; + uint64_t msk_and:16; +#else + uint64_t msk_and:16; + uint64_t reserved_16_31:16; + uint64_t msk_or:16; + uint64_t reserved_48_63:16; +#endif + } s; + struct cvmx_gmxx_bpid_msk_s cn68xx; + struct cvmx_gmxx_bpid_msk_s cn68xxp1; }; union cvmx_gmxx_clk_en { uint64_t u64; struct cvmx_gmxx_clk_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t clk_en:1; +#else + uint64_t clk_en:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_gmxx_clk_en_s cn52xx; struct cvmx_gmxx_clk_en_s cn52xxp1; struct cvmx_gmxx_clk_en_s cn56xx; struct cvmx_gmxx_clk_en_s cn56xxp1; + struct cvmx_gmxx_clk_en_s cn61xx; + struct cvmx_gmxx_clk_en_s cn63xx; + struct cvmx_gmxx_clk_en_s cn63xxp1; + struct cvmx_gmxx_clk_en_s cn66xx; + struct cvmx_gmxx_clk_en_s cn68xx; + struct cvmx_gmxx_clk_en_s cn68xxp1; + struct cvmx_gmxx_clk_en_s cnf71xx; +}; + +union cvmx_gmxx_ebp_dis { + uint64_t u64; + struct cvmx_gmxx_ebp_dis_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t dis:16; +#else + uint64_t dis:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_gmxx_ebp_dis_s cn68xx; + struct cvmx_gmxx_ebp_dis_s cn68xxp1; +}; + +union cvmx_gmxx_ebp_msk { + uint64_t u64; + struct cvmx_gmxx_ebp_msk_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t msk:16; +#else + uint64_t msk:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_gmxx_ebp_msk_s cn68xx; + struct cvmx_gmxx_ebp_msk_s cn68xxp1; }; union cvmx_gmxx_hg2_control { uint64_t u64; struct cvmx_gmxx_hg2_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t hg2tx_en:1; uint64_t hg2rx_en:1; uint64_t phys_en:1; uint64_t logl_en:16; +#else + uint64_t logl_en:16; + uint64_t phys_en:1; + uint64_t hg2rx_en:1; + uint64_t hg2tx_en:1; + uint64_t reserved_19_63:45; +#endif } s; struct cvmx_gmxx_hg2_control_s cn52xx; struct cvmx_gmxx_hg2_control_s cn52xxp1; struct cvmx_gmxx_hg2_control_s cn56xx; + struct cvmx_gmxx_hg2_control_s cn61xx; + struct cvmx_gmxx_hg2_control_s cn63xx; + struct cvmx_gmxx_hg2_control_s cn63xxp1; + struct cvmx_gmxx_hg2_control_s cn66xx; + struct cvmx_gmxx_hg2_control_s cn68xx; + struct cvmx_gmxx_hg2_control_s cn68xxp1; + struct cvmx_gmxx_hg2_control_s cnf71xx; }; union cvmx_gmxx_inf_mode { uint64_t u64; struct cvmx_gmxx_inf_mode_s { - uint64_t reserved_10_63:54; - uint64_t speed:2; - uint64_t reserved_6_7:2; - uint64_t mode:2; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t rate:4; + uint64_t reserved_12_15:4; + uint64_t speed:4; + uint64_t reserved_7_7:1; + uint64_t mode:3; uint64_t reserved_3_3:1; uint64_t p0mii:1; uint64_t en:1; uint64_t type:1; +#else + uint64_t type:1; + uint64_t en:1; + uint64_t p0mii:1; + uint64_t reserved_3_3:1; + uint64_t mode:3; + uint64_t reserved_7_7:1; + uint64_t speed:4; + uint64_t reserved_12_15:4; + uint64_t rate:4; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_gmxx_inf_mode_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t p0mii:1; uint64_t en:1; uint64_t type:1; +#else + uint64_t type:1; + uint64_t en:1; + uint64_t p0mii:1; + uint64_t reserved_3_63:61; +#endif } cn30xx; struct cvmx_gmxx_inf_mode_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t en:1; uint64_t type:1; +#else + uint64_t type:1; + uint64_t en:1; + uint64_t reserved_2_63:62; +#endif } cn31xx; struct cvmx_gmxx_inf_mode_cn31xx cn38xx; struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2; struct cvmx_gmxx_inf_mode_cn30xx cn50xx; struct cvmx_gmxx_inf_mode_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t speed:2; uint64_t reserved_6_7:2; @@ -357,36 +2402,158 @@ union cvmx_gmxx_inf_mode { uint64_t reserved_2_3:2; uint64_t en:1; uint64_t type:1; +#else + uint64_t type:1; + uint64_t en:1; + uint64_t reserved_2_3:2; + uint64_t mode:2; + uint64_t reserved_6_7:2; + uint64_t speed:2; + uint64_t reserved_10_63:54; +#endif } cn52xx; struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1; struct cvmx_gmxx_inf_mode_cn52xx cn56xx; struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1; struct cvmx_gmxx_inf_mode_cn31xx cn58xx; struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1; + struct cvmx_gmxx_inf_mode_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t speed:4; + uint64_t reserved_5_7:3; + uint64_t mode:1; + uint64_t reserved_2_3:2; + uint64_t en:1; + uint64_t type:1; +#else + uint64_t type:1; + uint64_t en:1; + uint64_t reserved_2_3:2; + uint64_t mode:1; + uint64_t reserved_5_7:3; + uint64_t speed:4; + uint64_t reserved_12_63:52; +#endif + } cn61xx; + struct cvmx_gmxx_inf_mode_cn61xx cn63xx; + struct cvmx_gmxx_inf_mode_cn61xx cn63xxp1; + struct cvmx_gmxx_inf_mode_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t rate:4; + uint64_t reserved_12_15:4; + uint64_t speed:4; + uint64_t reserved_5_7:3; + uint64_t mode:1; + uint64_t reserved_2_3:2; + uint64_t en:1; + uint64_t type:1; +#else + uint64_t type:1; + uint64_t en:1; + uint64_t reserved_2_3:2; + uint64_t mode:1; + uint64_t reserved_5_7:3; + uint64_t speed:4; + uint64_t reserved_12_15:4; + uint64_t rate:4; + uint64_t reserved_20_63:44; +#endif + } cn66xx; + struct cvmx_gmxx_inf_mode_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t speed:4; + uint64_t reserved_7_7:1; + uint64_t mode:3; + uint64_t reserved_2_3:2; + uint64_t en:1; + uint64_t type:1; +#else + uint64_t type:1; + uint64_t en:1; + uint64_t reserved_2_3:2; + uint64_t mode:3; + uint64_t reserved_7_7:1; + uint64_t speed:4; + uint64_t reserved_12_63:52; +#endif + } cn68xx; + struct cvmx_gmxx_inf_mode_cn68xx cn68xxp1; + struct cvmx_gmxx_inf_mode_cn61xx cnf71xx; }; union cvmx_gmxx_nxa_adr { uint64_t u64; struct cvmx_gmxx_nxa_adr_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_23_63:41; + uint64_t pipe:7; + uint64_t reserved_6_15:10; + uint64_t prt:6; +#else + uint64_t prt:6; + uint64_t reserved_6_15:10; + uint64_t pipe:7; + uint64_t reserved_23_63:41; +#endif + } s; + struct cvmx_gmxx_nxa_adr_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t prt:6; +#else + uint64_t prt:6; + uint64_t reserved_6_63:58; +#endif + } cn30xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn31xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn38xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn38xxp2; + struct cvmx_gmxx_nxa_adr_cn30xx cn50xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn52xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn52xxp1; + struct cvmx_gmxx_nxa_adr_cn30xx cn56xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn56xxp1; + struct cvmx_gmxx_nxa_adr_cn30xx cn58xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn58xxp1; + struct cvmx_gmxx_nxa_adr_cn30xx cn61xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn63xx; + struct cvmx_gmxx_nxa_adr_cn30xx cn63xxp1; + struct cvmx_gmxx_nxa_adr_cn30xx cn66xx; + struct cvmx_gmxx_nxa_adr_s cn68xx; + struct cvmx_gmxx_nxa_adr_s cn68xxp1; + struct cvmx_gmxx_nxa_adr_cn30xx cnf71xx; +}; + +union cvmx_gmxx_pipe_status { + uint64_t u64; + struct cvmx_gmxx_pipe_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t ovr:4; + uint64_t reserved_12_15:4; + uint64_t bp:4; + uint64_t reserved_4_7:4; + uint64_t stop:4; +#else + uint64_t stop:4; + uint64_t reserved_4_7:4; + uint64_t bp:4; + uint64_t reserved_12_15:4; + uint64_t ovr:4; + uint64_t reserved_20_63:44; +#endif } s; - struct cvmx_gmxx_nxa_adr_s cn30xx; - struct cvmx_gmxx_nxa_adr_s cn31xx; - struct cvmx_gmxx_nxa_adr_s cn38xx; - struct cvmx_gmxx_nxa_adr_s cn38xxp2; - struct cvmx_gmxx_nxa_adr_s cn50xx; - struct cvmx_gmxx_nxa_adr_s cn52xx; - struct cvmx_gmxx_nxa_adr_s cn52xxp1; - struct cvmx_gmxx_nxa_adr_s cn56xx; - struct cvmx_gmxx_nxa_adr_s cn56xxp1; - struct cvmx_gmxx_nxa_adr_s cn58xx; - struct cvmx_gmxx_nxa_adr_s cn58xxp1; + struct cvmx_gmxx_pipe_status_s cn68xx; + struct cvmx_gmxx_pipe_status_s cn68xxp1; }; union cvmx_gmxx_prtx_cbfc_ctl { uint64_t u64; struct cvmx_gmxx_prtx_cbfc_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t phys_en:16; uint64_t logl_en:16; uint64_t phys_bp:16; @@ -395,15 +2562,35 @@ union cvmx_gmxx_prtx_cbfc_ctl { uint64_t drp_en:1; uint64_t tx_en:1; uint64_t rx_en:1; +#else + uint64_t rx_en:1; + uint64_t tx_en:1; + uint64_t drp_en:1; + uint64_t bck_en:1; + uint64_t reserved_4_15:12; + uint64_t phys_bp:16; + uint64_t logl_en:16; + uint64_t phys_en:16; +#endif } s; struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx; struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx; + struct cvmx_gmxx_prtx_cbfc_ctl_s cn61xx; + struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xx; + struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xxp1; + struct cvmx_gmxx_prtx_cbfc_ctl_s cn66xx; + struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xx; + struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xxp1; + struct cvmx_gmxx_prtx_cbfc_ctl_s cnf71xx; }; union cvmx_gmxx_prtx_cfg { uint64_t u64; struct cvmx_gmxx_prtx_cfg_s { - uint64_t reserved_14_63:50; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_22_63:42; + uint64_t pknd:6; + uint64_t reserved_14_15:2; uint64_t tx_idle:1; uint64_t rx_idle:1; uint64_t reserved_9_11:3; @@ -413,30 +2600,87 @@ union cvmx_gmxx_prtx_cfg { uint64_t duplex:1; uint64_t speed:1; uint64_t en:1; +#else + uint64_t en:1; + uint64_t speed:1; + uint64_t duplex:1; + uint64_t slottime:1; + uint64_t reserved_4_7:4; + uint64_t speed_msb:1; + uint64_t reserved_9_11:3; + uint64_t rx_idle:1; + uint64_t tx_idle:1; + uint64_t reserved_14_15:2; + uint64_t pknd:6; + uint64_t reserved_22_63:42; +#endif } s; struct cvmx_gmxx_prtx_cfg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t slottime:1; uint64_t duplex:1; uint64_t speed:1; uint64_t en:1; +#else + uint64_t en:1; + uint64_t speed:1; + uint64_t duplex:1; + uint64_t slottime:1; + uint64_t reserved_4_63:60; +#endif } cn30xx; struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx; struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx; struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2; struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx; - struct cvmx_gmxx_prtx_cfg_s cn52xx; - struct cvmx_gmxx_prtx_cfg_s cn52xxp1; - struct cvmx_gmxx_prtx_cfg_s cn56xx; - struct cvmx_gmxx_prtx_cfg_s cn56xxp1; + struct cvmx_gmxx_prtx_cfg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_14_63:50; + uint64_t tx_idle:1; + uint64_t rx_idle:1; + uint64_t reserved_9_11:3; + uint64_t speed_msb:1; + uint64_t reserved_4_7:4; + uint64_t slottime:1; + uint64_t duplex:1; + uint64_t speed:1; + uint64_t en:1; +#else + uint64_t en:1; + uint64_t speed:1; + uint64_t duplex:1; + uint64_t slottime:1; + uint64_t reserved_4_7:4; + uint64_t speed_msb:1; + uint64_t reserved_9_11:3; + uint64_t rx_idle:1; + uint64_t tx_idle:1; + uint64_t reserved_14_63:50; +#endif + } cn52xx; + struct cvmx_gmxx_prtx_cfg_cn52xx cn52xxp1; + struct cvmx_gmxx_prtx_cfg_cn52xx cn56xx; + struct cvmx_gmxx_prtx_cfg_cn52xx cn56xxp1; struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx; struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1; + struct cvmx_gmxx_prtx_cfg_cn52xx cn61xx; + struct cvmx_gmxx_prtx_cfg_cn52xx cn63xx; + struct cvmx_gmxx_prtx_cfg_cn52xx cn63xxp1; + struct cvmx_gmxx_prtx_cfg_cn52xx cn66xx; + struct cvmx_gmxx_prtx_cfg_s cn68xx; + struct cvmx_gmxx_prtx_cfg_s cn68xxp1; + struct cvmx_gmxx_prtx_cfg_cn52xx cnf71xx; }; union cvmx_gmxx_rxx_adr_cam0 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t adr:64; +#else uint64_t adr:64; +#endif } s; struct cvmx_gmxx_rxx_adr_cam0_s cn30xx; struct cvmx_gmxx_rxx_adr_cam0_s cn31xx; @@ -449,12 +2693,23 @@ union cvmx_gmxx_rxx_adr_cam0 { struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam0_s cn58xx; struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1; + struct cvmx_gmxx_rxx_adr_cam0_s cn61xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn63xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn63xxp1; + struct cvmx_gmxx_rxx_adr_cam0_s cn66xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn68xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn68xxp1; + struct cvmx_gmxx_rxx_adr_cam0_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam1 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; +#else + uint64_t adr:64; +#endif } s; struct cvmx_gmxx_rxx_adr_cam1_s cn30xx; struct cvmx_gmxx_rxx_adr_cam1_s cn31xx; @@ -467,12 +2722,23 @@ union cvmx_gmxx_rxx_adr_cam1 { struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam1_s cn58xx; struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1; + struct cvmx_gmxx_rxx_adr_cam1_s cn61xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn63xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn63xxp1; + struct cvmx_gmxx_rxx_adr_cam1_s cn66xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn68xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn68xxp1; + struct cvmx_gmxx_rxx_adr_cam1_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam2 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t adr:64; +#else uint64_t adr:64; +#endif } s; struct cvmx_gmxx_rxx_adr_cam2_s cn30xx; struct cvmx_gmxx_rxx_adr_cam2_s cn31xx; @@ -485,12 +2751,23 @@ union cvmx_gmxx_rxx_adr_cam2 { struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam2_s cn58xx; struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1; + struct cvmx_gmxx_rxx_adr_cam2_s cn61xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn63xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn63xxp1; + struct cvmx_gmxx_rxx_adr_cam2_s cn66xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn68xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn68xxp1; + struct cvmx_gmxx_rxx_adr_cam2_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam3 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t adr:64; +#else uint64_t adr:64; +#endif } s; struct cvmx_gmxx_rxx_adr_cam3_s cn30xx; struct cvmx_gmxx_rxx_adr_cam3_s cn31xx; @@ -503,12 +2780,23 @@ union cvmx_gmxx_rxx_adr_cam3 { struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam3_s cn58xx; struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1; + struct cvmx_gmxx_rxx_adr_cam3_s cn61xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn63xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn63xxp1; + struct cvmx_gmxx_rxx_adr_cam3_s cn66xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn68xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn68xxp1; + struct cvmx_gmxx_rxx_adr_cam3_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam4 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam4_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t adr:64; +#else + uint64_t adr:64; +#endif } s; struct cvmx_gmxx_rxx_adr_cam4_s cn30xx; struct cvmx_gmxx_rxx_adr_cam4_s cn31xx; @@ -521,12 +2809,23 @@ union cvmx_gmxx_rxx_adr_cam4 { struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam4_s cn58xx; struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1; + struct cvmx_gmxx_rxx_adr_cam4_s cn61xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn63xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn63xxp1; + struct cvmx_gmxx_rxx_adr_cam4_s cn66xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn68xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn68xxp1; + struct cvmx_gmxx_rxx_adr_cam4_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam5 { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam5_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t adr:64; +#else uint64_t adr:64; +#endif } s; struct cvmx_gmxx_rxx_adr_cam5_s cn30xx; struct cvmx_gmxx_rxx_adr_cam5_s cn31xx; @@ -539,13 +2838,42 @@ union cvmx_gmxx_rxx_adr_cam5 { struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam5_s cn58xx; struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1; + struct cvmx_gmxx_rxx_adr_cam5_s cn61xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn63xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn63xxp1; + struct cvmx_gmxx_rxx_adr_cam5_s cn66xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn68xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn68xxp1; + struct cvmx_gmxx_rxx_adr_cam5_s cnf71xx; +}; + +union cvmx_gmxx_rxx_adr_cam_all_en { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_cam_all_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t en:32; +#else + uint64_t en:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_gmxx_rxx_adr_cam_all_en_s cn61xx; + struct cvmx_gmxx_rxx_adr_cam_all_en_s cn66xx; + struct cvmx_gmxx_rxx_adr_cam_all_en_s cn68xx; + struct cvmx_gmxx_rxx_adr_cam_all_en_s cnf71xx; }; union cvmx_gmxx_rxx_adr_cam_en { uint64_t u64; struct cvmx_gmxx_rxx_adr_cam_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t en:8; +#else + uint64_t en:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx; struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx; @@ -558,15 +2886,29 @@ union cvmx_gmxx_rxx_adr_cam_en { struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1; struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx; struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1; + struct cvmx_gmxx_rxx_adr_cam_en_s cn61xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn63xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn63xxp1; + struct cvmx_gmxx_rxx_adr_cam_en_s cn66xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn68xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn68xxp1; + struct cvmx_gmxx_rxx_adr_cam_en_s cnf71xx; }; union cvmx_gmxx_rxx_adr_ctl { uint64_t u64; struct cvmx_gmxx_rxx_adr_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t cam_mode:1; uint64_t mcst:2; uint64_t bcst:1; +#else + uint64_t bcst:1; + uint64_t mcst:2; + uint64_t cam_mode:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_gmxx_rxx_adr_ctl_s cn30xx; struct cvmx_gmxx_rxx_adr_ctl_s cn31xx; @@ -579,13 +2921,25 @@ union cvmx_gmxx_rxx_adr_ctl { struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1; struct cvmx_gmxx_rxx_adr_ctl_s cn58xx; struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1; + struct cvmx_gmxx_rxx_adr_ctl_s cn61xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn63xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn63xxp1; + struct cvmx_gmxx_rxx_adr_ctl_s cn66xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn68xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn68xxp1; + struct cvmx_gmxx_rxx_adr_ctl_s cnf71xx; }; union cvmx_gmxx_rxx_decision { uint64_t u64; struct cvmx_gmxx_rxx_decision_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t cnt:5; +#else + uint64_t cnt:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_gmxx_rxx_decision_s cn30xx; struct cvmx_gmxx_rxx_decision_s cn31xx; @@ -598,11 +2952,19 @@ union cvmx_gmxx_rxx_decision { struct cvmx_gmxx_rxx_decision_s cn56xxp1; struct cvmx_gmxx_rxx_decision_s cn58xx; struct cvmx_gmxx_rxx_decision_s cn58xxp1; + struct cvmx_gmxx_rxx_decision_s cn61xx; + struct cvmx_gmxx_rxx_decision_s cn63xx; + struct cvmx_gmxx_rxx_decision_s cn63xxp1; + struct cvmx_gmxx_rxx_decision_s cn66xx; + struct cvmx_gmxx_rxx_decision_s cn68xx; + struct cvmx_gmxx_rxx_decision_s cn68xxp1; + struct cvmx_gmxx_rxx_decision_s cnf71xx; }; union cvmx_gmxx_rxx_frm_chk { uint64_t u64; struct cvmx_gmxx_rxx_frm_chk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t niberr:1; uint64_t skperr:1; @@ -614,12 +2976,26 @@ union cvmx_gmxx_rxx_frm_chk { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_gmxx_rxx_frm_chk_s cn30xx; struct cvmx_gmxx_rxx_frm_chk_s cn31xx; struct cvmx_gmxx_rxx_frm_chk_s cn38xx; struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2; struct cvmx_gmxx_rxx_frm_chk_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t niberr:1; uint64_t skperr:1; @@ -631,8 +3007,22 @@ union cvmx_gmxx_rxx_frm_chk { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t reserved_6_6:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t reserved_10_63:54; +#endif } cn50xx; struct cvmx_gmxx_rxx_frm_chk_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t skperr:1; uint64_t rcverr:1; @@ -642,18 +3032,61 @@ union cvmx_gmxx_rxx_frm_chk { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t reserved_5_6:2; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_63:55; +#endif } cn52xx; struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1; struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx; struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1; struct cvmx_gmxx_rxx_frm_chk_s cn58xx; struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1; + struct cvmx_gmxx_rxx_frm_chk_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_9_63:55; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_5_6:2; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t reserved_5_6:2; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_63:55; +#endif + } cn61xx; + struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xx; + struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xxp1; + struct cvmx_gmxx_rxx_frm_chk_cn61xx cn66xx; + struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xx; + struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xxp1; + struct cvmx_gmxx_rxx_frm_chk_cn61xx cnf71xx; }; union cvmx_gmxx_rxx_frm_ctl { uint64_t u64; struct cvmx_gmxx_rxx_frm_ctl_s { - uint64_t reserved_11_63:53; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_13_63:51; + uint64_t ptp_mode:1; + uint64_t reserved_11_11:1; uint64_t null_dis:1; uint64_t pre_align:1; uint64_t pad_len:1; @@ -665,8 +3098,25 @@ union cvmx_gmxx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t pre_align:1; + uint64_t null_dis:1; + uint64_t reserved_11_11:1; + uint64_t ptp_mode:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_gmxx_rxx_frm_ctl_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t pad_len:1; uint64_t vlan_len:1; @@ -677,8 +3127,21 @@ union cvmx_gmxx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t reserved_9_63:55; +#endif } cn30xx; struct cvmx_gmxx_rxx_frm_ctl_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t vlan_len:1; uint64_t pre_free:1; @@ -688,10 +3151,22 @@ union cvmx_gmxx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t vlan_len:1; + uint64_t reserved_8_63:56; +#endif } cn31xx; struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx; struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2; struct cvmx_gmxx_rxx_frm_ctl_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t null_dis:1; uint64_t pre_align:1; @@ -703,11 +3178,25 @@ union cvmx_gmxx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t reserved_7_8:2; + uint64_t pre_align:1; + uint64_t null_dis:1; + uint64_t reserved_11_63:53; +#endif } cn50xx; struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx; struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1; struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx; struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pre_align:1; uint64_t reserved_7_8:2; @@ -718,16 +3207,98 @@ union cvmx_gmxx_rxx_frm_ctl { uint64_t ctl_drp:1; uint64_t pre_strp:1; uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t reserved_7_8:2; + uint64_t pre_align:1; + uint64_t reserved_10_63:54; +#endif } cn56xxp1; - struct cvmx_gmxx_rxx_frm_ctl_s cn58xx; + struct cvmx_gmxx_rxx_frm_ctl_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t null_dis:1; + uint64_t pre_align:1; + uint64_t pad_len:1; + uint64_t vlan_len:1; + uint64_t pre_free:1; + uint64_t ctl_smac:1; + uint64_t ctl_mcst:1; + uint64_t ctl_bck:1; + uint64_t ctl_drp:1; + uint64_t pre_strp:1; + uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t pre_align:1; + uint64_t null_dis:1; + uint64_t reserved_11_63:53; +#endif + } cn58xx; struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1; + struct cvmx_gmxx_rxx_frm_ctl_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_13_63:51; + uint64_t ptp_mode:1; + uint64_t reserved_11_11:1; + uint64_t null_dis:1; + uint64_t pre_align:1; + uint64_t reserved_7_8:2; + uint64_t pre_free:1; + uint64_t ctl_smac:1; + uint64_t ctl_mcst:1; + uint64_t ctl_bck:1; + uint64_t ctl_drp:1; + uint64_t pre_strp:1; + uint64_t pre_chk:1; +#else + uint64_t pre_chk:1; + uint64_t pre_strp:1; + uint64_t ctl_drp:1; + uint64_t ctl_bck:1; + uint64_t ctl_mcst:1; + uint64_t ctl_smac:1; + uint64_t pre_free:1; + uint64_t reserved_7_8:2; + uint64_t pre_align:1; + uint64_t null_dis:1; + uint64_t reserved_11_11:1; + uint64_t ptp_mode:1; + uint64_t reserved_13_63:51; +#endif + } cn61xx; + struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xx; + struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xxp1; + struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn66xx; + struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xx; + struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xxp1; + struct cvmx_gmxx_rxx_frm_ctl_cn61xx cnf71xx; }; union cvmx_gmxx_rxx_frm_max { uint64_t u64; struct cvmx_gmxx_rxx_frm_max_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t len:16; +#else + uint64_t len:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_rxx_frm_max_s cn30xx; struct cvmx_gmxx_rxx_frm_max_s cn31xx; @@ -740,8 +3311,13 @@ union cvmx_gmxx_rxx_frm_max { union cvmx_gmxx_rxx_frm_min { uint64_t u64; struct cvmx_gmxx_rxx_frm_min_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t len:16; +#else + uint64_t len:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_rxx_frm_min_s cn30xx; struct cvmx_gmxx_rxx_frm_min_s cn31xx; @@ -754,8 +3330,13 @@ union cvmx_gmxx_rxx_frm_min { union cvmx_gmxx_rxx_ifg { uint64_t u64; struct cvmx_gmxx_rxx_ifg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t ifg:4; +#else + uint64_t ifg:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_gmxx_rxx_ifg_s cn30xx; struct cvmx_gmxx_rxx_ifg_s cn31xx; @@ -768,11 +3349,19 @@ union cvmx_gmxx_rxx_ifg { struct cvmx_gmxx_rxx_ifg_s cn56xxp1; struct cvmx_gmxx_rxx_ifg_s cn58xx; struct cvmx_gmxx_rxx_ifg_s cn58xxp1; + struct cvmx_gmxx_rxx_ifg_s cn61xx; + struct cvmx_gmxx_rxx_ifg_s cn63xx; + struct cvmx_gmxx_rxx_ifg_s cn63xxp1; + struct cvmx_gmxx_rxx_ifg_s cn66xx; + struct cvmx_gmxx_rxx_ifg_s cn68xx; + struct cvmx_gmxx_rxx_ifg_s cn68xxp1; + struct cvmx_gmxx_rxx_ifg_s cnf71xx; }; union cvmx_gmxx_rxx_int_en { uint64_t u64; struct cvmx_gmxx_rxx_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t hg2cc:1; uint64_t hg2fld:1; @@ -803,8 +3392,41 @@ union cvmx_gmxx_rxx_int_en { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t pause_drp:1; + uint64_t loc_fault:1; + uint64_t rem_fault:1; + uint64_t bad_seq:1; + uint64_t bad_term:1; + uint64_t unsop:1; + uint64_t uneop:1; + uint64_t undat:1; + uint64_t hg2fld:1; + uint64_t hg2cc:1; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_gmxx_rxx_int_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t phy_dupx:1; uint64_t phy_spd:1; @@ -825,11 +3447,34 @@ union cvmx_gmxx_rxx_int_en { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t reserved_19_63:45; +#endif } cn30xx; struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx; struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx; struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2; struct cvmx_gmxx_rxx_int_en_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -851,8 +3496,32 @@ union cvmx_gmxx_rxx_int_en { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t reserved_6_6:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t pause_drp:1; + uint64_t reserved_20_63:44; +#endif } cn50xx; struct cvmx_gmxx_rxx_int_en_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t hg2cc:1; uint64_t hg2fld:1; @@ -880,10 +3549,40 @@ union cvmx_gmxx_rxx_int_en { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t reserved_5_6:2; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_9:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t reserved_16_18:3; + uint64_t pause_drp:1; + uint64_t loc_fault:1; + uint64_t rem_fault:1; + uint64_t bad_seq:1; + uint64_t bad_term:1; + uint64_t unsop:1; + uint64_t uneop:1; + uint64_t undat:1; + uint64_t hg2fld:1; + uint64_t hg2cc:1; + uint64_t reserved_29_63:35; +#endif } cn52xx; struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1; struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx; struct cvmx_gmxx_rxx_int_en_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t undat:1; uint64_t uneop:1; @@ -909,8 +3608,36 @@ union cvmx_gmxx_rxx_int_en { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t reserved_5_6:2; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_9:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t reserved_16_18:3; + uint64_t pause_drp:1; + uint64_t loc_fault:1; + uint64_t rem_fault:1; + uint64_t bad_seq:1; + uint64_t bad_term:1; + uint64_t unsop:1; + uint64_t uneop:1; + uint64_t undat:1; + uint64_t reserved_27_63:37; +#endif } cn56xxp1; struct cvmx_gmxx_rxx_int_en_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -932,13 +3659,102 @@ union cvmx_gmxx_rxx_int_en { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t pause_drp:1; + uint64_t reserved_20_63:44; +#endif } cn58xx; struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1; + struct cvmx_gmxx_rxx_int_en_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t hg2cc:1; + uint64_t hg2fld:1; + uint64_t undat:1; + uint64_t uneop:1; + uint64_t unsop:1; + uint64_t bad_term:1; + uint64_t bad_seq:1; + uint64_t rem_fault:1; + uint64_t loc_fault:1; + uint64_t pause_drp:1; + uint64_t reserved_16_18:3; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t reserved_9_9:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_5_6:2; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t reserved_5_6:2; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_9:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t reserved_16_18:3; + uint64_t pause_drp:1; + uint64_t loc_fault:1; + uint64_t rem_fault:1; + uint64_t bad_seq:1; + uint64_t bad_term:1; + uint64_t unsop:1; + uint64_t uneop:1; + uint64_t undat:1; + uint64_t hg2fld:1; + uint64_t hg2cc:1; + uint64_t reserved_29_63:35; +#endif + } cn61xx; + struct cvmx_gmxx_rxx_int_en_cn61xx cn63xx; + struct cvmx_gmxx_rxx_int_en_cn61xx cn63xxp1; + struct cvmx_gmxx_rxx_int_en_cn61xx cn66xx; + struct cvmx_gmxx_rxx_int_en_cn61xx cn68xx; + struct cvmx_gmxx_rxx_int_en_cn61xx cn68xxp1; + struct cvmx_gmxx_rxx_int_en_cn61xx cnf71xx; }; union cvmx_gmxx_rxx_int_reg { uint64_t u64; struct cvmx_gmxx_rxx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t hg2cc:1; uint64_t hg2fld:1; @@ -969,8 +3785,41 @@ union cvmx_gmxx_rxx_int_reg { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t pause_drp:1; + uint64_t loc_fault:1; + uint64_t rem_fault:1; + uint64_t bad_seq:1; + uint64_t bad_term:1; + uint64_t unsop:1; + uint64_t uneop:1; + uint64_t undat:1; + uint64_t hg2fld:1; + uint64_t hg2cc:1; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_gmxx_rxx_int_reg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t phy_dupx:1; uint64_t phy_spd:1; @@ -991,11 +3840,34 @@ union cvmx_gmxx_rxx_int_reg { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t reserved_19_63:45; +#endif } cn30xx; struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx; struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx; struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2; struct cvmx_gmxx_rxx_int_reg_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -1017,8 +3889,32 @@ union cvmx_gmxx_rxx_int_reg { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t reserved_6_6:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t pause_drp:1; + uint64_t reserved_20_63:44; +#endif } cn50xx; struct cvmx_gmxx_rxx_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t hg2cc:1; uint64_t hg2fld:1; @@ -1046,10 +3942,40 @@ union cvmx_gmxx_rxx_int_reg { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t reserved_5_6:2; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_9:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t reserved_16_18:3; + uint64_t pause_drp:1; + uint64_t loc_fault:1; + uint64_t rem_fault:1; + uint64_t bad_seq:1; + uint64_t bad_term:1; + uint64_t unsop:1; + uint64_t uneop:1; + uint64_t undat:1; + uint64_t hg2fld:1; + uint64_t hg2cc:1; + uint64_t reserved_29_63:35; +#endif } cn52xx; struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1; struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx; struct cvmx_gmxx_rxx_int_reg_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t undat:1; uint64_t uneop:1; @@ -1075,8 +4001,36 @@ union cvmx_gmxx_rxx_int_reg { uint64_t reserved_2_2:1; uint64_t carext:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t reserved_5_6:2; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_9:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t reserved_16_18:3; + uint64_t pause_drp:1; + uint64_t loc_fault:1; + uint64_t rem_fault:1; + uint64_t bad_seq:1; + uint64_t bad_term:1; + uint64_t unsop:1; + uint64_t uneop:1; + uint64_t undat:1; + uint64_t reserved_27_63:37; +#endif } cn56xxp1; struct cvmx_gmxx_rxx_int_reg_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pause_drp:1; uint64_t phy_dupx:1; @@ -1098,15 +4052,108 @@ union cvmx_gmxx_rxx_int_reg { uint64_t maxerr:1; uint64_t carext:1; uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t maxerr:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t alnerr:1; + uint64_t lenerr:1; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t niberr:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t phy_link:1; + uint64_t phy_spd:1; + uint64_t phy_dupx:1; + uint64_t pause_drp:1; + uint64_t reserved_20_63:44; +#endif } cn58xx; struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1; + struct cvmx_gmxx_rxx_int_reg_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t hg2cc:1; + uint64_t hg2fld:1; + uint64_t undat:1; + uint64_t uneop:1; + uint64_t unsop:1; + uint64_t bad_term:1; + uint64_t bad_seq:1; + uint64_t rem_fault:1; + uint64_t loc_fault:1; + uint64_t pause_drp:1; + uint64_t reserved_16_18:3; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t reserved_9_9:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_5_6:2; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t minerr:1; +#else + uint64_t minerr:1; + uint64_t carext:1; + uint64_t reserved_2_2:1; + uint64_t jabber:1; + uint64_t fcserr:1; + uint64_t reserved_5_6:2; + uint64_t rcverr:1; + uint64_t skperr:1; + uint64_t reserved_9_9:1; + uint64_t ovrerr:1; + uint64_t pcterr:1; + uint64_t rsverr:1; + uint64_t falerr:1; + uint64_t coldet:1; + uint64_t ifgerr:1; + uint64_t reserved_16_18:3; + uint64_t pause_drp:1; + uint64_t loc_fault:1; + uint64_t rem_fault:1; + uint64_t bad_seq:1; + uint64_t bad_term:1; + uint64_t unsop:1; + uint64_t uneop:1; + uint64_t undat:1; + uint64_t hg2fld:1; + uint64_t hg2cc:1; + uint64_t reserved_29_63:35; +#endif + } cn61xx; + struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xx; + struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xxp1; + struct cvmx_gmxx_rxx_int_reg_cn61xx cn66xx; + struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xx; + struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xxp1; + struct cvmx_gmxx_rxx_int_reg_cn61xx cnf71xx; }; union cvmx_gmxx_rxx_jabber { uint64_t u64; struct cvmx_gmxx_rxx_jabber_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt:16; +#else + uint64_t cnt:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_rxx_jabber_s cn30xx; struct cvmx_gmxx_rxx_jabber_s cn31xx; @@ -1119,13 +4166,25 @@ union cvmx_gmxx_rxx_jabber { struct cvmx_gmxx_rxx_jabber_s cn56xxp1; struct cvmx_gmxx_rxx_jabber_s cn58xx; struct cvmx_gmxx_rxx_jabber_s cn58xxp1; + struct cvmx_gmxx_rxx_jabber_s cn61xx; + struct cvmx_gmxx_rxx_jabber_s cn63xx; + struct cvmx_gmxx_rxx_jabber_s cn63xxp1; + struct cvmx_gmxx_rxx_jabber_s cn66xx; + struct cvmx_gmxx_rxx_jabber_s cn68xx; + struct cvmx_gmxx_rxx_jabber_s cn68xxp1; + struct cvmx_gmxx_rxx_jabber_s cnf71xx; }; union cvmx_gmxx_rxx_pause_drop_time { uint64_t u64; struct cvmx_gmxx_rxx_pause_drop_time_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t status:16; +#else + uint64_t status:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx; struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx; @@ -1134,15 +4193,29 @@ union cvmx_gmxx_rxx_pause_drop_time { struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1; struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx; struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1; + struct cvmx_gmxx_rxx_pause_drop_time_s cn61xx; + struct cvmx_gmxx_rxx_pause_drop_time_s cn63xx; + struct cvmx_gmxx_rxx_pause_drop_time_s cn63xxp1; + struct cvmx_gmxx_rxx_pause_drop_time_s cn66xx; + struct cvmx_gmxx_rxx_pause_drop_time_s cn68xx; + struct cvmx_gmxx_rxx_pause_drop_time_s cn68xxp1; + struct cvmx_gmxx_rxx_pause_drop_time_s cnf71xx; }; union cvmx_gmxx_rxx_rx_inbnd { uint64_t u64; struct cvmx_gmxx_rxx_rx_inbnd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t duplex:1; uint64_t speed:2; uint64_t status:1; +#else + uint64_t status:1; + uint64_t speed:2; + uint64_t duplex:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx; struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx; @@ -1156,8 +4229,13 @@ union cvmx_gmxx_rxx_rx_inbnd { union cvmx_gmxx_rxx_stats_ctl { uint64_t u64; struct cvmx_gmxx_rxx_stats_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rd_clr:1; +#else + uint64_t rd_clr:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_gmxx_rxx_stats_ctl_s cn30xx; struct cvmx_gmxx_rxx_stats_ctl_s cn31xx; @@ -1170,13 +4248,25 @@ union cvmx_gmxx_rxx_stats_ctl { struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1; struct cvmx_gmxx_rxx_stats_ctl_s cn58xx; struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_ctl_s cn61xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn63xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_ctl_s cn66xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn68xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_ctl_s cnf71xx; }; union cvmx_gmxx_rxx_stats_octs { uint64_t u64; struct cvmx_gmxx_rxx_stats_octs_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; +#else + uint64_t cnt:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_rxx_stats_octs_s cn30xx; struct cvmx_gmxx_rxx_stats_octs_s cn31xx; @@ -1189,13 +4279,25 @@ union cvmx_gmxx_rxx_stats_octs { struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1; struct cvmx_gmxx_rxx_stats_octs_s cn58xx; struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_octs_s cn61xx; + struct cvmx_gmxx_rxx_stats_octs_s cn63xx; + struct cvmx_gmxx_rxx_stats_octs_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_octs_s cn66xx; + struct cvmx_gmxx_rxx_stats_octs_s cn68xx; + struct cvmx_gmxx_rxx_stats_octs_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_octs_s cnf71xx; }; union cvmx_gmxx_rxx_stats_octs_ctl { uint64_t u64; struct cvmx_gmxx_rxx_stats_octs_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; +#else + uint64_t cnt:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx; struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx; @@ -1208,13 +4310,25 @@ union cvmx_gmxx_rxx_stats_octs_ctl { struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1; struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx; struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn61xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn66xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cnf71xx; }; union cvmx_gmxx_rxx_stats_octs_dmac { uint64_t u64; struct cvmx_gmxx_rxx_stats_octs_dmac_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; +#else + uint64_t cnt:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx; struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx; @@ -1227,13 +4341,25 @@ union cvmx_gmxx_rxx_stats_octs_dmac { struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1; struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx; struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn61xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn66xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cnf71xx; }; union cvmx_gmxx_rxx_stats_octs_drp { uint64_t u64; struct cvmx_gmxx_rxx_stats_octs_drp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t cnt:48; +#else + uint64_t cnt:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx; struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx; @@ -1246,13 +4372,25 @@ union cvmx_gmxx_rxx_stats_octs_drp { struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1; struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx; struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn61xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn66xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_octs_drp_s cnf71xx; }; union cvmx_gmxx_rxx_stats_pkts { uint64_t u64; struct cvmx_gmxx_rxx_stats_pkts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gmxx_rxx_stats_pkts_s cn30xx; struct cvmx_gmxx_rxx_stats_pkts_s cn31xx; @@ -1265,13 +4403,25 @@ union cvmx_gmxx_rxx_stats_pkts { struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1; struct cvmx_gmxx_rxx_stats_pkts_s cn58xx; struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_pkts_s cn61xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn63xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_pkts_s cn66xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn68xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_pkts_s cnf71xx; }; union cvmx_gmxx_rxx_stats_pkts_bad { uint64_t u64; struct cvmx_gmxx_rxx_stats_pkts_bad_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx; struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx; @@ -1284,13 +4434,25 @@ union cvmx_gmxx_rxx_stats_pkts_bad { struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1; struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx; struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn61xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn66xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cnf71xx; }; union cvmx_gmxx_rxx_stats_pkts_ctl { uint64_t u64; struct cvmx_gmxx_rxx_stats_pkts_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx; struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx; @@ -1303,13 +4465,25 @@ union cvmx_gmxx_rxx_stats_pkts_ctl { struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1; struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx; struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn61xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn66xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cnf71xx; }; union cvmx_gmxx_rxx_stats_pkts_dmac { uint64_t u64; struct cvmx_gmxx_rxx_stats_pkts_dmac_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx; struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx; @@ -1322,13 +4496,25 @@ union cvmx_gmxx_rxx_stats_pkts_dmac { struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1; struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx; struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn61xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn66xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cnf71xx; }; union cvmx_gmxx_rxx_stats_pkts_drp { uint64_t u64; struct cvmx_gmxx_rxx_stats_pkts_drp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx; struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx; @@ -1341,15 +4527,29 @@ union cvmx_gmxx_rxx_stats_pkts_drp { struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1; struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx; struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn61xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xxp1; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn66xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xxp1; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cnf71xx; }; union cvmx_gmxx_rxx_udd_skp { uint64_t u64; struct cvmx_gmxx_rxx_udd_skp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t fcssel:1; uint64_t reserved_7_7:1; uint64_t len:7; +#else + uint64_t len:7; + uint64_t reserved_7_7:1; + uint64_t fcssel:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_gmxx_rxx_udd_skp_s cn30xx; struct cvmx_gmxx_rxx_udd_skp_s cn31xx; @@ -1362,13 +4562,25 @@ union cvmx_gmxx_rxx_udd_skp { struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1; struct cvmx_gmxx_rxx_udd_skp_s cn58xx; struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1; + struct cvmx_gmxx_rxx_udd_skp_s cn61xx; + struct cvmx_gmxx_rxx_udd_skp_s cn63xx; + struct cvmx_gmxx_rxx_udd_skp_s cn63xxp1; + struct cvmx_gmxx_rxx_udd_skp_s cn66xx; + struct cvmx_gmxx_rxx_udd_skp_s cn68xx; + struct cvmx_gmxx_rxx_udd_skp_s cn68xxp1; + struct cvmx_gmxx_rxx_udd_skp_s cnf71xx; }; union cvmx_gmxx_rx_bp_dropx { uint64_t u64; struct cvmx_gmxx_rx_bp_dropx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mark:6; +#else + uint64_t mark:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_gmxx_rx_bp_dropx_s cn30xx; struct cvmx_gmxx_rx_bp_dropx_s cn31xx; @@ -1381,13 +4593,25 @@ union cvmx_gmxx_rx_bp_dropx { struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1; struct cvmx_gmxx_rx_bp_dropx_s cn58xx; struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1; + struct cvmx_gmxx_rx_bp_dropx_s cn61xx; + struct cvmx_gmxx_rx_bp_dropx_s cn63xx; + struct cvmx_gmxx_rx_bp_dropx_s cn63xxp1; + struct cvmx_gmxx_rx_bp_dropx_s cn66xx; + struct cvmx_gmxx_rx_bp_dropx_s cn68xx; + struct cvmx_gmxx_rx_bp_dropx_s cn68xxp1; + struct cvmx_gmxx_rx_bp_dropx_s cnf71xx; }; union cvmx_gmxx_rx_bp_offx { uint64_t u64; struct cvmx_gmxx_rx_bp_offx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mark:6; +#else + uint64_t mark:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_gmxx_rx_bp_offx_s cn30xx; struct cvmx_gmxx_rx_bp_offx_s cn31xx; @@ -1400,45 +4624,91 @@ union cvmx_gmxx_rx_bp_offx { struct cvmx_gmxx_rx_bp_offx_s cn56xxp1; struct cvmx_gmxx_rx_bp_offx_s cn58xx; struct cvmx_gmxx_rx_bp_offx_s cn58xxp1; + struct cvmx_gmxx_rx_bp_offx_s cn61xx; + struct cvmx_gmxx_rx_bp_offx_s cn63xx; + struct cvmx_gmxx_rx_bp_offx_s cn63xxp1; + struct cvmx_gmxx_rx_bp_offx_s cn66xx; + struct cvmx_gmxx_rx_bp_offx_s cn68xx; + struct cvmx_gmxx_rx_bp_offx_s cn68xxp1; + struct cvmx_gmxx_rx_bp_offx_s cnf71xx; }; union cvmx_gmxx_rx_bp_onx { uint64_t u64; struct cvmx_gmxx_rx_bp_onx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t mark:11; +#else + uint64_t mark:11; + uint64_t reserved_11_63:53; +#endif + } s; + struct cvmx_gmxx_rx_bp_onx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t mark:9; - } s; - struct cvmx_gmxx_rx_bp_onx_s cn30xx; - struct cvmx_gmxx_rx_bp_onx_s cn31xx; - struct cvmx_gmxx_rx_bp_onx_s cn38xx; - struct cvmx_gmxx_rx_bp_onx_s cn38xxp2; - struct cvmx_gmxx_rx_bp_onx_s cn50xx; - struct cvmx_gmxx_rx_bp_onx_s cn52xx; - struct cvmx_gmxx_rx_bp_onx_s cn52xxp1; - struct cvmx_gmxx_rx_bp_onx_s cn56xx; - struct cvmx_gmxx_rx_bp_onx_s cn56xxp1; - struct cvmx_gmxx_rx_bp_onx_s cn58xx; - struct cvmx_gmxx_rx_bp_onx_s cn58xxp1; +#else + uint64_t mark:9; + uint64_t reserved_9_63:55; +#endif + } cn30xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn31xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xxp2; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn50xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xxp1; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xxp1; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xxp1; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn61xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xx; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xxp1; + struct cvmx_gmxx_rx_bp_onx_cn30xx cn66xx; + struct cvmx_gmxx_rx_bp_onx_s cn68xx; + struct cvmx_gmxx_rx_bp_onx_s cn68xxp1; + struct cvmx_gmxx_rx_bp_onx_cn30xx cnf71xx; }; union cvmx_gmxx_rx_hg2_status { uint64_t u64; struct cvmx_gmxx_rx_hg2_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t phtim2go:16; uint64_t xof:16; uint64_t lgtim2go:16; +#else + uint64_t lgtim2go:16; + uint64_t xof:16; + uint64_t phtim2go:16; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_rx_hg2_status_s cn52xx; struct cvmx_gmxx_rx_hg2_status_s cn52xxp1; struct cvmx_gmxx_rx_hg2_status_s cn56xx; + struct cvmx_gmxx_rx_hg2_status_s cn61xx; + struct cvmx_gmxx_rx_hg2_status_s cn63xx; + struct cvmx_gmxx_rx_hg2_status_s cn63xxp1; + struct cvmx_gmxx_rx_hg2_status_s cn66xx; + struct cvmx_gmxx_rx_hg2_status_s cn68xx; + struct cvmx_gmxx_rx_hg2_status_s cn68xxp1; + struct cvmx_gmxx_rx_hg2_status_s cnf71xx; }; union cvmx_gmxx_rx_pass_en { uint64_t u64; struct cvmx_gmxx_rx_pass_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t en:16; +#else + uint64_t en:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_rx_pass_en_s cn38xx; struct cvmx_gmxx_rx_pass_en_s cn38xxp2; @@ -1449,8 +4719,13 @@ union cvmx_gmxx_rx_pass_en { union cvmx_gmxx_rx_pass_mapx { uint64_t u64; struct cvmx_gmxx_rx_pass_mapx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t dprt:4; +#else + uint64_t dprt:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_gmxx_rx_pass_mapx_s cn38xx; struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2; @@ -1461,37 +4736,81 @@ union cvmx_gmxx_rx_pass_mapx { union cvmx_gmxx_rx_prt_info { uint64_t u64; struct cvmx_gmxx_rx_prt_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t drop:16; uint64_t commit:16; +#else + uint64_t commit:16; + uint64_t drop:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gmxx_rx_prt_info_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t drop:3; uint64_t reserved_3_15:13; uint64_t commit:3; +#else + uint64_t commit:3; + uint64_t reserved_3_15:13; + uint64_t drop:3; + uint64_t reserved_19_63:45; +#endif } cn30xx; struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx; struct cvmx_gmxx_rx_prt_info_s cn38xx; struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx; struct cvmx_gmxx_rx_prt_info_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t drop:4; uint64_t reserved_4_15:12; uint64_t commit:4; +#else + uint64_t commit:4; + uint64_t reserved_4_15:12; + uint64_t drop:4; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1; struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx; struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1; struct cvmx_gmxx_rx_prt_info_s cn58xx; struct cvmx_gmxx_rx_prt_info_s cn58xxp1; + struct cvmx_gmxx_rx_prt_info_cn52xx cn61xx; + struct cvmx_gmxx_rx_prt_info_cn52xx cn63xx; + struct cvmx_gmxx_rx_prt_info_cn52xx cn63xxp1; + struct cvmx_gmxx_rx_prt_info_cn52xx cn66xx; + struct cvmx_gmxx_rx_prt_info_cn52xx cn68xx; + struct cvmx_gmxx_rx_prt_info_cn52xx cn68xxp1; + struct cvmx_gmxx_rx_prt_info_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_18_63:46; + uint64_t drop:2; + uint64_t reserved_2_15:14; + uint64_t commit:2; +#else + uint64_t commit:2; + uint64_t reserved_2_15:14; + uint64_t drop:2; + uint64_t reserved_18_63:46; +#endif + } cnf71xx; }; union cvmx_gmxx_rx_prts { uint64_t u64; struct cvmx_gmxx_rx_prts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t prts:3; +#else + uint64_t prts:3; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_gmxx_rx_prts_s cn30xx; struct cvmx_gmxx_rx_prts_s cn31xx; @@ -1504,15 +4823,29 @@ union cvmx_gmxx_rx_prts { struct cvmx_gmxx_rx_prts_s cn56xxp1; struct cvmx_gmxx_rx_prts_s cn58xx; struct cvmx_gmxx_rx_prts_s cn58xxp1; + struct cvmx_gmxx_rx_prts_s cn61xx; + struct cvmx_gmxx_rx_prts_s cn63xx; + struct cvmx_gmxx_rx_prts_s cn63xxp1; + struct cvmx_gmxx_rx_prts_s cn66xx; + struct cvmx_gmxx_rx_prts_s cn68xx; + struct cvmx_gmxx_rx_prts_s cn68xxp1; + struct cvmx_gmxx_rx_prts_s cnf71xx; }; union cvmx_gmxx_rx_tx_status { uint64_t u64; struct cvmx_gmxx_rx_tx_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t tx:3; uint64_t reserved_3_3:1; uint64_t rx:3; +#else + uint64_t rx:3; + uint64_t reserved_3_3:1; + uint64_t tx:3; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_gmxx_rx_tx_status_s cn30xx; struct cvmx_gmxx_rx_tx_status_s cn31xx; @@ -1522,35 +4855,82 @@ union cvmx_gmxx_rx_tx_status { union cvmx_gmxx_rx_xaui_bad_col { uint64_t u64; struct cvmx_gmxx_rx_xaui_bad_col_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t val:1; uint64_t state:3; uint64_t lane_rxc:4; uint64_t lane_rxd:32; +#else + uint64_t lane_rxd:32; + uint64_t lane_rxc:4; + uint64_t state:3; + uint64_t val:1; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx; struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1; struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx; struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1; + struct cvmx_gmxx_rx_xaui_bad_col_s cn61xx; + struct cvmx_gmxx_rx_xaui_bad_col_s cn63xx; + struct cvmx_gmxx_rx_xaui_bad_col_s cn63xxp1; + struct cvmx_gmxx_rx_xaui_bad_col_s cn66xx; + struct cvmx_gmxx_rx_xaui_bad_col_s cn68xx; + struct cvmx_gmxx_rx_xaui_bad_col_s cn68xxp1; + struct cvmx_gmxx_rx_xaui_bad_col_s cnf71xx; }; union cvmx_gmxx_rx_xaui_ctl { uint64_t u64; struct cvmx_gmxx_rx_xaui_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t status:2; +#else + uint64_t status:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_gmxx_rx_xaui_ctl_s cn52xx; struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1; struct cvmx_gmxx_rx_xaui_ctl_s cn56xx; struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1; + struct cvmx_gmxx_rx_xaui_ctl_s cn61xx; + struct cvmx_gmxx_rx_xaui_ctl_s cn63xx; + struct cvmx_gmxx_rx_xaui_ctl_s cn63xxp1; + struct cvmx_gmxx_rx_xaui_ctl_s cn66xx; + struct cvmx_gmxx_rx_xaui_ctl_s cn68xx; + struct cvmx_gmxx_rx_xaui_ctl_s cn68xxp1; + struct cvmx_gmxx_rx_xaui_ctl_s cnf71xx; +}; + +union cvmx_gmxx_rxaui_ctl { + uint64_t u64; + struct cvmx_gmxx_rxaui_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t disparity:1; +#else + uint64_t disparity:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_gmxx_rxaui_ctl_s cn68xx; + struct cvmx_gmxx_rxaui_ctl_s cn68xxp1; }; union cvmx_gmxx_smacx { uint64_t u64; struct cvmx_gmxx_smacx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t smac:48; +#else + uint64_t smac:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_smacx_s cn30xx; struct cvmx_gmxx_smacx_s cn31xx; @@ -1563,14 +4943,47 @@ union cvmx_gmxx_smacx { struct cvmx_gmxx_smacx_s cn56xxp1; struct cvmx_gmxx_smacx_s cn58xx; struct cvmx_gmxx_smacx_s cn58xxp1; + struct cvmx_gmxx_smacx_s cn61xx; + struct cvmx_gmxx_smacx_s cn63xx; + struct cvmx_gmxx_smacx_s cn63xxp1; + struct cvmx_gmxx_smacx_s cn66xx; + struct cvmx_gmxx_smacx_s cn68xx; + struct cvmx_gmxx_smacx_s cn68xxp1; + struct cvmx_gmxx_smacx_s cnf71xx; +}; + +union cvmx_gmxx_soft_bist { + uint64_t u64; + struct cvmx_gmxx_soft_bist_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_2_63:62; + uint64_t start_bist:1; + uint64_t clear_bist:1; +#else + uint64_t clear_bist:1; + uint64_t start_bist:1; + uint64_t reserved_2_63:62; +#endif + } s; + struct cvmx_gmxx_soft_bist_s cn63xx; + struct cvmx_gmxx_soft_bist_s cn63xxp1; + struct cvmx_gmxx_soft_bist_s cn66xx; + struct cvmx_gmxx_soft_bist_s cn68xx; + struct cvmx_gmxx_soft_bist_s cn68xxp1; }; union cvmx_gmxx_stat_bp { uint64_t u64; struct cvmx_gmxx_stat_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t bp:1; uint64_t cnt:16; +#else + uint64_t cnt:16; + uint64_t bp:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_gmxx_stat_bp_s cn30xx; struct cvmx_gmxx_stat_bp_s cn31xx; @@ -1583,16 +4996,48 @@ union cvmx_gmxx_stat_bp { struct cvmx_gmxx_stat_bp_s cn56xxp1; struct cvmx_gmxx_stat_bp_s cn58xx; struct cvmx_gmxx_stat_bp_s cn58xxp1; + struct cvmx_gmxx_stat_bp_s cn61xx; + struct cvmx_gmxx_stat_bp_s cn63xx; + struct cvmx_gmxx_stat_bp_s cn63xxp1; + struct cvmx_gmxx_stat_bp_s cn66xx; + struct cvmx_gmxx_stat_bp_s cn68xx; + struct cvmx_gmxx_stat_bp_s cn68xxp1; + struct cvmx_gmxx_stat_bp_s cnf71xx; +}; + +union cvmx_gmxx_tb_reg { + uint64_t u64; + struct cvmx_gmxx_tb_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t wr_magic:1; +#else + uint64_t wr_magic:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_gmxx_tb_reg_s cn61xx; + struct cvmx_gmxx_tb_reg_s cn66xx; + struct cvmx_gmxx_tb_reg_s cn68xx; + struct cvmx_gmxx_tb_reg_s cnf71xx; }; union cvmx_gmxx_txx_append { uint64_t u64; struct cvmx_gmxx_txx_append_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t force_fcs:1; uint64_t fcs:1; uint64_t pad:1; uint64_t preamble:1; +#else + uint64_t preamble:1; + uint64_t pad:1; + uint64_t fcs:1; + uint64_t force_fcs:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_gmxx_txx_append_s cn30xx; struct cvmx_gmxx_txx_append_s cn31xx; @@ -1605,13 +5050,25 @@ union cvmx_gmxx_txx_append { struct cvmx_gmxx_txx_append_s cn56xxp1; struct cvmx_gmxx_txx_append_s cn58xx; struct cvmx_gmxx_txx_append_s cn58xxp1; + struct cvmx_gmxx_txx_append_s cn61xx; + struct cvmx_gmxx_txx_append_s cn63xx; + struct cvmx_gmxx_txx_append_s cn63xxp1; + struct cvmx_gmxx_txx_append_s cn66xx; + struct cvmx_gmxx_txx_append_s cn68xx; + struct cvmx_gmxx_txx_append_s cn68xxp1; + struct cvmx_gmxx_txx_append_s cnf71xx; }; union cvmx_gmxx_txx_burst { uint64_t u64; struct cvmx_gmxx_txx_burst_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t burst:16; +#else + uint64_t burst:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_txx_burst_s cn30xx; struct cvmx_gmxx_txx_burst_s cn31xx; @@ -1624,33 +5081,69 @@ union cvmx_gmxx_txx_burst { struct cvmx_gmxx_txx_burst_s cn56xxp1; struct cvmx_gmxx_txx_burst_s cn58xx; struct cvmx_gmxx_txx_burst_s cn58xxp1; + struct cvmx_gmxx_txx_burst_s cn61xx; + struct cvmx_gmxx_txx_burst_s cn63xx; + struct cvmx_gmxx_txx_burst_s cn63xxp1; + struct cvmx_gmxx_txx_burst_s cn66xx; + struct cvmx_gmxx_txx_burst_s cn68xx; + struct cvmx_gmxx_txx_burst_s cn68xxp1; + struct cvmx_gmxx_txx_burst_s cnf71xx; }; union cvmx_gmxx_txx_cbfc_xoff { uint64_t u64; struct cvmx_gmxx_txx_cbfc_xoff_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t xoff:16; +#else + uint64_t xoff:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx; struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx; + struct cvmx_gmxx_txx_cbfc_xoff_s cn61xx; + struct cvmx_gmxx_txx_cbfc_xoff_s cn63xx; + struct cvmx_gmxx_txx_cbfc_xoff_s cn63xxp1; + struct cvmx_gmxx_txx_cbfc_xoff_s cn66xx; + struct cvmx_gmxx_txx_cbfc_xoff_s cn68xx; + struct cvmx_gmxx_txx_cbfc_xoff_s cn68xxp1; + struct cvmx_gmxx_txx_cbfc_xoff_s cnf71xx; }; union cvmx_gmxx_txx_cbfc_xon { uint64_t u64; struct cvmx_gmxx_txx_cbfc_xon_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t xon:16; +#else + uint64_t xon:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_txx_cbfc_xon_s cn52xx; struct cvmx_gmxx_txx_cbfc_xon_s cn56xx; + struct cvmx_gmxx_txx_cbfc_xon_s cn61xx; + struct cvmx_gmxx_txx_cbfc_xon_s cn63xx; + struct cvmx_gmxx_txx_cbfc_xon_s cn63xxp1; + struct cvmx_gmxx_txx_cbfc_xon_s cn66xx; + struct cvmx_gmxx_txx_cbfc_xon_s cn68xx; + struct cvmx_gmxx_txx_cbfc_xon_s cn68xxp1; + struct cvmx_gmxx_txx_cbfc_xon_s cnf71xx; }; union cvmx_gmxx_txx_clk { uint64_t u64; struct cvmx_gmxx_txx_clk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t clk_cnt:6; +#else + uint64_t clk_cnt:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_gmxx_txx_clk_s cn30xx; struct cvmx_gmxx_txx_clk_s cn31xx; @@ -1664,9 +5157,15 @@ union cvmx_gmxx_txx_clk { union cvmx_gmxx_txx_ctl { uint64_t u64; struct cvmx_gmxx_txx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t xsdef_en:1; uint64_t xscol_en:1; +#else + uint64_t xscol_en:1; + uint64_t xsdef_en:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_gmxx_txx_ctl_s cn30xx; struct cvmx_gmxx_txx_ctl_s cn31xx; @@ -1679,13 +5178,25 @@ union cvmx_gmxx_txx_ctl { struct cvmx_gmxx_txx_ctl_s cn56xxp1; struct cvmx_gmxx_txx_ctl_s cn58xx; struct cvmx_gmxx_txx_ctl_s cn58xxp1; + struct cvmx_gmxx_txx_ctl_s cn61xx; + struct cvmx_gmxx_txx_ctl_s cn63xx; + struct cvmx_gmxx_txx_ctl_s cn63xxp1; + struct cvmx_gmxx_txx_ctl_s cn66xx; + struct cvmx_gmxx_txx_ctl_s cn68xx; + struct cvmx_gmxx_txx_ctl_s cn68xxp1; + struct cvmx_gmxx_txx_ctl_s cnf71xx; }; union cvmx_gmxx_txx_min_pkt { uint64_t u64; struct cvmx_gmxx_txx_min_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t min_size:8; +#else + uint64_t min_size:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_gmxx_txx_min_pkt_s cn30xx; struct cvmx_gmxx_txx_min_pkt_s cn31xx; @@ -1698,13 +5209,25 @@ union cvmx_gmxx_txx_min_pkt { struct cvmx_gmxx_txx_min_pkt_s cn56xxp1; struct cvmx_gmxx_txx_min_pkt_s cn58xx; struct cvmx_gmxx_txx_min_pkt_s cn58xxp1; + struct cvmx_gmxx_txx_min_pkt_s cn61xx; + struct cvmx_gmxx_txx_min_pkt_s cn63xx; + struct cvmx_gmxx_txx_min_pkt_s cn63xxp1; + struct cvmx_gmxx_txx_min_pkt_s cn66xx; + struct cvmx_gmxx_txx_min_pkt_s cn68xx; + struct cvmx_gmxx_txx_min_pkt_s cn68xxp1; + struct cvmx_gmxx_txx_min_pkt_s cnf71xx; }; union cvmx_gmxx_txx_pause_pkt_interval { uint64_t u64; struct cvmx_gmxx_txx_pause_pkt_interval_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t interval:16; +#else + uint64_t interval:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx; struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx; @@ -1717,13 +5240,25 @@ union cvmx_gmxx_txx_pause_pkt_interval { struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1; struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx; struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn61xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xxp1; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn66xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xxp1; + struct cvmx_gmxx_txx_pause_pkt_interval_s cnf71xx; }; union cvmx_gmxx_txx_pause_pkt_time { uint64_t u64; struct cvmx_gmxx_txx_pause_pkt_time_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; +#else + uint64_t time:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx; struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx; @@ -1736,18 +5271,36 @@ union cvmx_gmxx_txx_pause_pkt_time { struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1; struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx; struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1; + struct cvmx_gmxx_txx_pause_pkt_time_s cn61xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn63xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn63xxp1; + struct cvmx_gmxx_txx_pause_pkt_time_s cn66xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn68xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn68xxp1; + struct cvmx_gmxx_txx_pause_pkt_time_s cnf71xx; }; union cvmx_gmxx_txx_pause_togo { uint64_t u64; struct cvmx_gmxx_txx_pause_togo_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t msg_time:16; uint64_t time:16; +#else + uint64_t time:16; + uint64_t msg_time:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gmxx_txx_pause_togo_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; +#else + uint64_t time:16; + uint64_t reserved_16_63:48; +#endif } cn30xx; struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx; struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx; @@ -1759,13 +5312,25 @@ union cvmx_gmxx_txx_pause_togo { struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1; struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx; struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1; + struct cvmx_gmxx_txx_pause_togo_s cn61xx; + struct cvmx_gmxx_txx_pause_togo_s cn63xx; + struct cvmx_gmxx_txx_pause_togo_s cn63xxp1; + struct cvmx_gmxx_txx_pause_togo_s cn66xx; + struct cvmx_gmxx_txx_pause_togo_s cn68xx; + struct cvmx_gmxx_txx_pause_togo_s cn68xxp1; + struct cvmx_gmxx_txx_pause_togo_s cnf71xx; }; union cvmx_gmxx_txx_pause_zero { uint64_t u64; struct cvmx_gmxx_txx_pause_zero_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t send:1; +#else + uint64_t send:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_gmxx_txx_pause_zero_s cn30xx; struct cvmx_gmxx_txx_pause_zero_s cn31xx; @@ -1778,25 +5343,72 @@ union cvmx_gmxx_txx_pause_zero { struct cvmx_gmxx_txx_pause_zero_s cn56xxp1; struct cvmx_gmxx_txx_pause_zero_s cn58xx; struct cvmx_gmxx_txx_pause_zero_s cn58xxp1; + struct cvmx_gmxx_txx_pause_zero_s cn61xx; + struct cvmx_gmxx_txx_pause_zero_s cn63xx; + struct cvmx_gmxx_txx_pause_zero_s cn63xxp1; + struct cvmx_gmxx_txx_pause_zero_s cn66xx; + struct cvmx_gmxx_txx_pause_zero_s cn68xx; + struct cvmx_gmxx_txx_pause_zero_s cn68xxp1; + struct cvmx_gmxx_txx_pause_zero_s cnf71xx; +}; + +union cvmx_gmxx_txx_pipe { + uint64_t u64; + struct cvmx_gmxx_txx_pipe_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t ign_bp:1; + uint64_t reserved_21_31:11; + uint64_t nump:5; + uint64_t reserved_7_15:9; + uint64_t base:7; +#else + uint64_t base:7; + uint64_t reserved_7_15:9; + uint64_t nump:5; + uint64_t reserved_21_31:11; + uint64_t ign_bp:1; + uint64_t reserved_33_63:31; +#endif + } s; + struct cvmx_gmxx_txx_pipe_s cn68xx; + struct cvmx_gmxx_txx_pipe_s cn68xxp1; }; union cvmx_gmxx_txx_sgmii_ctl { uint64_t u64; struct cvmx_gmxx_txx_sgmii_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t align:1; +#else + uint64_t align:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx; struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1; struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx; struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1; + struct cvmx_gmxx_txx_sgmii_ctl_s cn61xx; + struct cvmx_gmxx_txx_sgmii_ctl_s cn63xx; + struct cvmx_gmxx_txx_sgmii_ctl_s cn63xxp1; + struct cvmx_gmxx_txx_sgmii_ctl_s cn66xx; + struct cvmx_gmxx_txx_sgmii_ctl_s cn68xx; + struct cvmx_gmxx_txx_sgmii_ctl_s cn68xxp1; + struct cvmx_gmxx_txx_sgmii_ctl_s cnf71xx; }; union cvmx_gmxx_txx_slot { uint64_t u64; struct cvmx_gmxx_txx_slot_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t slot:10; +#else + uint64_t slot:10; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_gmxx_txx_slot_s cn30xx; struct cvmx_gmxx_txx_slot_s cn31xx; @@ -1809,13 +5421,25 @@ union cvmx_gmxx_txx_slot { struct cvmx_gmxx_txx_slot_s cn56xxp1; struct cvmx_gmxx_txx_slot_s cn58xx; struct cvmx_gmxx_txx_slot_s cn58xxp1; + struct cvmx_gmxx_txx_slot_s cn61xx; + struct cvmx_gmxx_txx_slot_s cn63xx; + struct cvmx_gmxx_txx_slot_s cn63xxp1; + struct cvmx_gmxx_txx_slot_s cn66xx; + struct cvmx_gmxx_txx_slot_s cn68xx; + struct cvmx_gmxx_txx_slot_s cn68xxp1; + struct cvmx_gmxx_txx_slot_s cnf71xx; }; union cvmx_gmxx_txx_soft_pause { uint64_t u64; struct cvmx_gmxx_txx_soft_pause_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t time:16; +#else + uint64_t time:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_txx_soft_pause_s cn30xx; struct cvmx_gmxx_txx_soft_pause_s cn31xx; @@ -1828,13 +5452,25 @@ union cvmx_gmxx_txx_soft_pause { struct cvmx_gmxx_txx_soft_pause_s cn56xxp1; struct cvmx_gmxx_txx_soft_pause_s cn58xx; struct cvmx_gmxx_txx_soft_pause_s cn58xxp1; + struct cvmx_gmxx_txx_soft_pause_s cn61xx; + struct cvmx_gmxx_txx_soft_pause_s cn63xx; + struct cvmx_gmxx_txx_soft_pause_s cn63xxp1; + struct cvmx_gmxx_txx_soft_pause_s cn66xx; + struct cvmx_gmxx_txx_soft_pause_s cn68xx; + struct cvmx_gmxx_txx_soft_pause_s cn68xxp1; + struct cvmx_gmxx_txx_soft_pause_s cnf71xx; }; union cvmx_gmxx_txx_stat0 { uint64_t u64; struct cvmx_gmxx_txx_stat0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t xsdef:32; uint64_t xscol:32; +#else + uint64_t xscol:32; + uint64_t xsdef:32; +#endif } s; struct cvmx_gmxx_txx_stat0_s cn30xx; struct cvmx_gmxx_txx_stat0_s cn31xx; @@ -1847,13 +5483,25 @@ union cvmx_gmxx_txx_stat0 { struct cvmx_gmxx_txx_stat0_s cn56xxp1; struct cvmx_gmxx_txx_stat0_s cn58xx; struct cvmx_gmxx_txx_stat0_s cn58xxp1; + struct cvmx_gmxx_txx_stat0_s cn61xx; + struct cvmx_gmxx_txx_stat0_s cn63xx; + struct cvmx_gmxx_txx_stat0_s cn63xxp1; + struct cvmx_gmxx_txx_stat0_s cn66xx; + struct cvmx_gmxx_txx_stat0_s cn68xx; + struct cvmx_gmxx_txx_stat0_s cn68xxp1; + struct cvmx_gmxx_txx_stat0_s cnf71xx; }; union cvmx_gmxx_txx_stat1 { uint64_t u64; struct cvmx_gmxx_txx_stat1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t scol:32; uint64_t mcol:32; +#else + uint64_t mcol:32; + uint64_t scol:32; +#endif } s; struct cvmx_gmxx_txx_stat1_s cn30xx; struct cvmx_gmxx_txx_stat1_s cn31xx; @@ -1866,13 +5514,25 @@ union cvmx_gmxx_txx_stat1 { struct cvmx_gmxx_txx_stat1_s cn56xxp1; struct cvmx_gmxx_txx_stat1_s cn58xx; struct cvmx_gmxx_txx_stat1_s cn58xxp1; + struct cvmx_gmxx_txx_stat1_s cn61xx; + struct cvmx_gmxx_txx_stat1_s cn63xx; + struct cvmx_gmxx_txx_stat1_s cn63xxp1; + struct cvmx_gmxx_txx_stat1_s cn66xx; + struct cvmx_gmxx_txx_stat1_s cn68xx; + struct cvmx_gmxx_txx_stat1_s cn68xxp1; + struct cvmx_gmxx_txx_stat1_s cnf71xx; }; union cvmx_gmxx_txx_stat2 { uint64_t u64; struct cvmx_gmxx_txx_stat2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t octs:48; +#else + uint64_t octs:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_txx_stat2_s cn30xx; struct cvmx_gmxx_txx_stat2_s cn31xx; @@ -1885,13 +5545,25 @@ union cvmx_gmxx_txx_stat2 { struct cvmx_gmxx_txx_stat2_s cn56xxp1; struct cvmx_gmxx_txx_stat2_s cn58xx; struct cvmx_gmxx_txx_stat2_s cn58xxp1; + struct cvmx_gmxx_txx_stat2_s cn61xx; + struct cvmx_gmxx_txx_stat2_s cn63xx; + struct cvmx_gmxx_txx_stat2_s cn63xxp1; + struct cvmx_gmxx_txx_stat2_s cn66xx; + struct cvmx_gmxx_txx_stat2_s cn68xx; + struct cvmx_gmxx_txx_stat2_s cn68xxp1; + struct cvmx_gmxx_txx_stat2_s cnf71xx; }; union cvmx_gmxx_txx_stat3 { uint64_t u64; struct cvmx_gmxx_txx_stat3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pkts:32; +#else + uint64_t pkts:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gmxx_txx_stat3_s cn30xx; struct cvmx_gmxx_txx_stat3_s cn31xx; @@ -1904,13 +5576,25 @@ union cvmx_gmxx_txx_stat3 { struct cvmx_gmxx_txx_stat3_s cn56xxp1; struct cvmx_gmxx_txx_stat3_s cn58xx; struct cvmx_gmxx_txx_stat3_s cn58xxp1; + struct cvmx_gmxx_txx_stat3_s cn61xx; + struct cvmx_gmxx_txx_stat3_s cn63xx; + struct cvmx_gmxx_txx_stat3_s cn63xxp1; + struct cvmx_gmxx_txx_stat3_s cn66xx; + struct cvmx_gmxx_txx_stat3_s cn68xx; + struct cvmx_gmxx_txx_stat3_s cn68xxp1; + struct cvmx_gmxx_txx_stat3_s cnf71xx; }; union cvmx_gmxx_txx_stat4 { uint64_t u64; struct cvmx_gmxx_txx_stat4_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist1:32; uint64_t hist0:32; +#else + uint64_t hist0:32; + uint64_t hist1:32; +#endif } s; struct cvmx_gmxx_txx_stat4_s cn30xx; struct cvmx_gmxx_txx_stat4_s cn31xx; @@ -1923,13 +5607,25 @@ union cvmx_gmxx_txx_stat4 { struct cvmx_gmxx_txx_stat4_s cn56xxp1; struct cvmx_gmxx_txx_stat4_s cn58xx; struct cvmx_gmxx_txx_stat4_s cn58xxp1; + struct cvmx_gmxx_txx_stat4_s cn61xx; + struct cvmx_gmxx_txx_stat4_s cn63xx; + struct cvmx_gmxx_txx_stat4_s cn63xxp1; + struct cvmx_gmxx_txx_stat4_s cn66xx; + struct cvmx_gmxx_txx_stat4_s cn68xx; + struct cvmx_gmxx_txx_stat4_s cn68xxp1; + struct cvmx_gmxx_txx_stat4_s cnf71xx; }; union cvmx_gmxx_txx_stat5 { uint64_t u64; struct cvmx_gmxx_txx_stat5_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist3:32; uint64_t hist2:32; +#else + uint64_t hist2:32; + uint64_t hist3:32; +#endif } s; struct cvmx_gmxx_txx_stat5_s cn30xx; struct cvmx_gmxx_txx_stat5_s cn31xx; @@ -1942,13 +5638,25 @@ union cvmx_gmxx_txx_stat5 { struct cvmx_gmxx_txx_stat5_s cn56xxp1; struct cvmx_gmxx_txx_stat5_s cn58xx; struct cvmx_gmxx_txx_stat5_s cn58xxp1; + struct cvmx_gmxx_txx_stat5_s cn61xx; + struct cvmx_gmxx_txx_stat5_s cn63xx; + struct cvmx_gmxx_txx_stat5_s cn63xxp1; + struct cvmx_gmxx_txx_stat5_s cn66xx; + struct cvmx_gmxx_txx_stat5_s cn68xx; + struct cvmx_gmxx_txx_stat5_s cn68xxp1; + struct cvmx_gmxx_txx_stat5_s cnf71xx; }; union cvmx_gmxx_txx_stat6 { uint64_t u64; struct cvmx_gmxx_txx_stat6_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist5:32; uint64_t hist4:32; +#else + uint64_t hist4:32; + uint64_t hist5:32; +#endif } s; struct cvmx_gmxx_txx_stat6_s cn30xx; struct cvmx_gmxx_txx_stat6_s cn31xx; @@ -1961,13 +5669,25 @@ union cvmx_gmxx_txx_stat6 { struct cvmx_gmxx_txx_stat6_s cn56xxp1; struct cvmx_gmxx_txx_stat6_s cn58xx; struct cvmx_gmxx_txx_stat6_s cn58xxp1; + struct cvmx_gmxx_txx_stat6_s cn61xx; + struct cvmx_gmxx_txx_stat6_s cn63xx; + struct cvmx_gmxx_txx_stat6_s cn63xxp1; + struct cvmx_gmxx_txx_stat6_s cn66xx; + struct cvmx_gmxx_txx_stat6_s cn68xx; + struct cvmx_gmxx_txx_stat6_s cn68xxp1; + struct cvmx_gmxx_txx_stat6_s cnf71xx; }; union cvmx_gmxx_txx_stat7 { uint64_t u64; struct cvmx_gmxx_txx_stat7_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t hist7:32; uint64_t hist6:32; +#else + uint64_t hist6:32; + uint64_t hist7:32; +#endif } s; struct cvmx_gmxx_txx_stat7_s cn30xx; struct cvmx_gmxx_txx_stat7_s cn31xx; @@ -1980,13 +5700,25 @@ union cvmx_gmxx_txx_stat7 { struct cvmx_gmxx_txx_stat7_s cn56xxp1; struct cvmx_gmxx_txx_stat7_s cn58xx; struct cvmx_gmxx_txx_stat7_s cn58xxp1; + struct cvmx_gmxx_txx_stat7_s cn61xx; + struct cvmx_gmxx_txx_stat7_s cn63xx; + struct cvmx_gmxx_txx_stat7_s cn63xxp1; + struct cvmx_gmxx_txx_stat7_s cn66xx; + struct cvmx_gmxx_txx_stat7_s cn68xx; + struct cvmx_gmxx_txx_stat7_s cn68xxp1; + struct cvmx_gmxx_txx_stat7_s cnf71xx; }; union cvmx_gmxx_txx_stat8 { uint64_t u64; struct cvmx_gmxx_txx_stat8_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mcst:32; uint64_t bcst:32; +#else + uint64_t bcst:32; + uint64_t mcst:32; +#endif } s; struct cvmx_gmxx_txx_stat8_s cn30xx; struct cvmx_gmxx_txx_stat8_s cn31xx; @@ -1999,13 +5731,25 @@ union cvmx_gmxx_txx_stat8 { struct cvmx_gmxx_txx_stat8_s cn56xxp1; struct cvmx_gmxx_txx_stat8_s cn58xx; struct cvmx_gmxx_txx_stat8_s cn58xxp1; + struct cvmx_gmxx_txx_stat8_s cn61xx; + struct cvmx_gmxx_txx_stat8_s cn63xx; + struct cvmx_gmxx_txx_stat8_s cn63xxp1; + struct cvmx_gmxx_txx_stat8_s cn66xx; + struct cvmx_gmxx_txx_stat8_s cn68xx; + struct cvmx_gmxx_txx_stat8_s cn68xxp1; + struct cvmx_gmxx_txx_stat8_s cnf71xx; }; union cvmx_gmxx_txx_stat9 { uint64_t u64; struct cvmx_gmxx_txx_stat9_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t undflw:32; uint64_t ctl:32; +#else + uint64_t ctl:32; + uint64_t undflw:32; +#endif } s; struct cvmx_gmxx_txx_stat9_s cn30xx; struct cvmx_gmxx_txx_stat9_s cn31xx; @@ -2018,13 +5762,25 @@ union cvmx_gmxx_txx_stat9 { struct cvmx_gmxx_txx_stat9_s cn56xxp1; struct cvmx_gmxx_txx_stat9_s cn58xx; struct cvmx_gmxx_txx_stat9_s cn58xxp1; + struct cvmx_gmxx_txx_stat9_s cn61xx; + struct cvmx_gmxx_txx_stat9_s cn63xx; + struct cvmx_gmxx_txx_stat9_s cn63xxp1; + struct cvmx_gmxx_txx_stat9_s cn66xx; + struct cvmx_gmxx_txx_stat9_s cn68xx; + struct cvmx_gmxx_txx_stat9_s cn68xxp1; + struct cvmx_gmxx_txx_stat9_s cnf71xx; }; union cvmx_gmxx_txx_stats_ctl { uint64_t u64; struct cvmx_gmxx_txx_stats_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rd_clr:1; +#else + uint64_t rd_clr:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_gmxx_txx_stats_ctl_s cn30xx; struct cvmx_gmxx_txx_stats_ctl_s cn31xx; @@ -2037,39 +5793,81 @@ union cvmx_gmxx_txx_stats_ctl { struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1; struct cvmx_gmxx_txx_stats_ctl_s cn58xx; struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1; + struct cvmx_gmxx_txx_stats_ctl_s cn61xx; + struct cvmx_gmxx_txx_stats_ctl_s cn63xx; + struct cvmx_gmxx_txx_stats_ctl_s cn63xxp1; + struct cvmx_gmxx_txx_stats_ctl_s cn66xx; + struct cvmx_gmxx_txx_stats_ctl_s cn68xx; + struct cvmx_gmxx_txx_stats_ctl_s cn68xxp1; + struct cvmx_gmxx_txx_stats_ctl_s cnf71xx; }; union cvmx_gmxx_txx_thresh { uint64_t u64; struct cvmx_gmxx_txx_thresh_s { - uint64_t reserved_9_63:55; - uint64_t cnt:9; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t cnt:10; +#else + uint64_t cnt:10; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_gmxx_txx_thresh_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t cnt:7; +#else + uint64_t cnt:7; + uint64_t reserved_7_63:57; +#endif } cn30xx; struct cvmx_gmxx_txx_thresh_cn30xx cn31xx; - struct cvmx_gmxx_txx_thresh_s cn38xx; - struct cvmx_gmxx_txx_thresh_s cn38xxp2; + struct cvmx_gmxx_txx_thresh_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_9_63:55; + uint64_t cnt:9; +#else + uint64_t cnt:9; + uint64_t reserved_9_63:55; +#endif + } cn38xx; + struct cvmx_gmxx_txx_thresh_cn38xx cn38xxp2; struct cvmx_gmxx_txx_thresh_cn30xx cn50xx; - struct cvmx_gmxx_txx_thresh_s cn52xx; - struct cvmx_gmxx_txx_thresh_s cn52xxp1; - struct cvmx_gmxx_txx_thresh_s cn56xx; - struct cvmx_gmxx_txx_thresh_s cn56xxp1; - struct cvmx_gmxx_txx_thresh_s cn58xx; - struct cvmx_gmxx_txx_thresh_s cn58xxp1; + struct cvmx_gmxx_txx_thresh_cn38xx cn52xx; + struct cvmx_gmxx_txx_thresh_cn38xx cn52xxp1; + struct cvmx_gmxx_txx_thresh_cn38xx cn56xx; + struct cvmx_gmxx_txx_thresh_cn38xx cn56xxp1; + struct cvmx_gmxx_txx_thresh_cn38xx cn58xx; + struct cvmx_gmxx_txx_thresh_cn38xx cn58xxp1; + struct cvmx_gmxx_txx_thresh_cn38xx cn61xx; + struct cvmx_gmxx_txx_thresh_cn38xx cn63xx; + struct cvmx_gmxx_txx_thresh_cn38xx cn63xxp1; + struct cvmx_gmxx_txx_thresh_cn38xx cn66xx; + struct cvmx_gmxx_txx_thresh_s cn68xx; + struct cvmx_gmxx_txx_thresh_s cn68xxp1; + struct cvmx_gmxx_txx_thresh_cn38xx cnf71xx; }; union cvmx_gmxx_tx_bp { uint64_t u64; struct cvmx_gmxx_tx_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t bp:4; +#else + uint64_t bp:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_gmxx_tx_bp_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t bp:3; +#else + uint64_t bp:3; + uint64_t reserved_3_63:61; +#endif } cn30xx; struct cvmx_gmxx_tx_bp_cn30xx cn31xx; struct cvmx_gmxx_tx_bp_s cn38xx; @@ -2081,13 +5879,33 @@ union cvmx_gmxx_tx_bp { struct cvmx_gmxx_tx_bp_s cn56xxp1; struct cvmx_gmxx_tx_bp_s cn58xx; struct cvmx_gmxx_tx_bp_s cn58xxp1; + struct cvmx_gmxx_tx_bp_s cn61xx; + struct cvmx_gmxx_tx_bp_s cn63xx; + struct cvmx_gmxx_tx_bp_s cn63xxp1; + struct cvmx_gmxx_tx_bp_s cn66xx; + struct cvmx_gmxx_tx_bp_s cn68xx; + struct cvmx_gmxx_tx_bp_s cn68xxp1; + struct cvmx_gmxx_tx_bp_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_2_63:62; + uint64_t bp:2; +#else + uint64_t bp:2; + uint64_t reserved_2_63:62; +#endif + } cnf71xx; }; union cvmx_gmxx_tx_clk_mskx { uint64_t u64; struct cvmx_gmxx_tx_clk_mskx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t msk:1; +#else + uint64_t msk:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_gmxx_tx_clk_mskx_s cn30xx; struct cvmx_gmxx_tx_clk_mskx_s cn50xx; @@ -2096,8 +5914,13 @@ union cvmx_gmxx_tx_clk_mskx { union cvmx_gmxx_tx_col_attempt { uint64_t u64; struct cvmx_gmxx_tx_col_attempt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t limit:5; +#else + uint64_t limit:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_gmxx_tx_col_attempt_s cn30xx; struct cvmx_gmxx_tx_col_attempt_s cn31xx; @@ -2110,17 +5933,34 @@ union cvmx_gmxx_tx_col_attempt { struct cvmx_gmxx_tx_col_attempt_s cn56xxp1; struct cvmx_gmxx_tx_col_attempt_s cn58xx; struct cvmx_gmxx_tx_col_attempt_s cn58xxp1; + struct cvmx_gmxx_tx_col_attempt_s cn61xx; + struct cvmx_gmxx_tx_col_attempt_s cn63xx; + struct cvmx_gmxx_tx_col_attempt_s cn63xxp1; + struct cvmx_gmxx_tx_col_attempt_s cn66xx; + struct cvmx_gmxx_tx_col_attempt_s cn68xx; + struct cvmx_gmxx_tx_col_attempt_s cn68xxp1; + struct cvmx_gmxx_tx_col_attempt_s cnf71xx; }; union cvmx_gmxx_tx_corrupt { uint64_t u64; struct cvmx_gmxx_tx_corrupt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t corrupt:4; +#else + uint64_t corrupt:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_gmxx_tx_corrupt_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t corrupt:3; +#else + uint64_t corrupt:3; + uint64_t reserved_3_63:61; +#endif } cn30xx; struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx; struct cvmx_gmxx_tx_corrupt_s cn38xx; @@ -2132,36 +5972,81 @@ union cvmx_gmxx_tx_corrupt { struct cvmx_gmxx_tx_corrupt_s cn56xxp1; struct cvmx_gmxx_tx_corrupt_s cn58xx; struct cvmx_gmxx_tx_corrupt_s cn58xxp1; + struct cvmx_gmxx_tx_corrupt_s cn61xx; + struct cvmx_gmxx_tx_corrupt_s cn63xx; + struct cvmx_gmxx_tx_corrupt_s cn63xxp1; + struct cvmx_gmxx_tx_corrupt_s cn66xx; + struct cvmx_gmxx_tx_corrupt_s cn68xx; + struct cvmx_gmxx_tx_corrupt_s cn68xxp1; + struct cvmx_gmxx_tx_corrupt_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_2_63:62; + uint64_t corrupt:2; +#else + uint64_t corrupt:2; + uint64_t reserved_2_63:62; +#endif + } cnf71xx; }; union cvmx_gmxx_tx_hg2_reg1 { uint64_t u64; struct cvmx_gmxx_tx_hg2_reg1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t tx_xof:16; +#else + uint64_t tx_xof:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_tx_hg2_reg1_s cn52xx; struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1; struct cvmx_gmxx_tx_hg2_reg1_s cn56xx; + struct cvmx_gmxx_tx_hg2_reg1_s cn61xx; + struct cvmx_gmxx_tx_hg2_reg1_s cn63xx; + struct cvmx_gmxx_tx_hg2_reg1_s cn63xxp1; + struct cvmx_gmxx_tx_hg2_reg1_s cn66xx; + struct cvmx_gmxx_tx_hg2_reg1_s cn68xx; + struct cvmx_gmxx_tx_hg2_reg1_s cn68xxp1; + struct cvmx_gmxx_tx_hg2_reg1_s cnf71xx; }; union cvmx_gmxx_tx_hg2_reg2 { uint64_t u64; struct cvmx_gmxx_tx_hg2_reg2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t tx_xon:16; +#else + uint64_t tx_xon:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_tx_hg2_reg2_s cn52xx; struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1; struct cvmx_gmxx_tx_hg2_reg2_s cn56xx; + struct cvmx_gmxx_tx_hg2_reg2_s cn61xx; + struct cvmx_gmxx_tx_hg2_reg2_s cn63xx; + struct cvmx_gmxx_tx_hg2_reg2_s cn63xxp1; + struct cvmx_gmxx_tx_hg2_reg2_s cn66xx; + struct cvmx_gmxx_tx_hg2_reg2_s cn68xx; + struct cvmx_gmxx_tx_hg2_reg2_s cn68xxp1; + struct cvmx_gmxx_tx_hg2_reg2_s cnf71xx; }; union cvmx_gmxx_tx_ifg { uint64_t u64; struct cvmx_gmxx_tx_ifg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ifg2:4; uint64_t ifg1:4; +#else + uint64_t ifg1:4; + uint64_t ifg2:4; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_gmxx_tx_ifg_s cn30xx; struct cvmx_gmxx_tx_ifg_s cn31xx; @@ -2174,21 +6059,44 @@ union cvmx_gmxx_tx_ifg { struct cvmx_gmxx_tx_ifg_s cn56xxp1; struct cvmx_gmxx_tx_ifg_s cn58xx; struct cvmx_gmxx_tx_ifg_s cn58xxp1; + struct cvmx_gmxx_tx_ifg_s cn61xx; + struct cvmx_gmxx_tx_ifg_s cn63xx; + struct cvmx_gmxx_tx_ifg_s cn63xxp1; + struct cvmx_gmxx_tx_ifg_s cn66xx; + struct cvmx_gmxx_tx_ifg_s cn68xx; + struct cvmx_gmxx_tx_ifg_s cn68xxp1; + struct cvmx_gmxx_tx_ifg_s cnf71xx; }; union cvmx_gmxx_tx_int_en { uint64_t u64; struct cvmx_gmxx_tx_int_en_s { - uint64_t reserved_20_63:44; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t xchange:1; + uint64_t ptp_lost:4; uint64_t late_col:4; uint64_t xsdef:4; uint64_t xscol:4; uint64_t reserved_6_7:2; uint64_t undflw:4; - uint64_t ncb_nxa:1; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; +#else uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t ptp_lost:4; + uint64_t xchange:1; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_gmxx_tx_int_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t late_col:3; uint64_t reserved_15_15:1; @@ -2199,8 +6107,21 @@ union cvmx_gmxx_tx_int_en { uint64_t undflw:3; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:3; + uint64_t reserved_5_7:3; + uint64_t xscol:3; + uint64_t reserved_11_11:1; + uint64_t xsdef:3; + uint64_t reserved_15_15:1; + uint64_t late_col:3; + uint64_t reserved_19_63:45; +#endif } cn30xx; struct cvmx_gmxx_tx_int_en_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t xsdef:3; uint64_t reserved_11_11:1; @@ -2209,9 +6130,40 @@ union cvmx_gmxx_tx_int_en { uint64_t undflw:3; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:3; + uint64_t reserved_5_7:3; + uint64_t xscol:3; + uint64_t reserved_11_11:1; + uint64_t xsdef:3; + uint64_t reserved_15_63:49; +#endif } cn31xx; - struct cvmx_gmxx_tx_int_en_s cn38xx; + struct cvmx_gmxx_tx_int_en_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t ncb_nxa:1; + uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t ncb_nxa:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t reserved_20_63:44; +#endif + } cn38xx; struct cvmx_gmxx_tx_int_en_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t xsdef:4; uint64_t xscol:4; @@ -2219,9 +6171,19 @@ union cvmx_gmxx_tx_int_en { uint64_t undflw:4; uint64_t ncb_nxa:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t ncb_nxa:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t reserved_16_63:48; +#endif } cn38xxp2; struct cvmx_gmxx_tx_int_en_cn30xx cn50xx; struct cvmx_gmxx_tx_int_en_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t late_col:4; uint64_t xsdef:4; @@ -2230,27 +6192,138 @@ union cvmx_gmxx_tx_int_en { uint64_t undflw:4; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1; struct cvmx_gmxx_tx_int_en_cn52xx cn56xx; struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1; - struct cvmx_gmxx_tx_int_en_s cn58xx; - struct cvmx_gmxx_tx_int_en_s cn58xxp1; + struct cvmx_gmxx_tx_int_en_cn38xx cn58xx; + struct cvmx_gmxx_tx_int_en_cn38xx cn58xxp1; + struct cvmx_gmxx_tx_int_en_s cn61xx; + struct cvmx_gmxx_tx_int_en_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_24_63:40; + uint64_t ptp_lost:4; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t ptp_lost:4; + uint64_t reserved_24_63:40; +#endif + } cn63xx; + struct cvmx_gmxx_tx_int_en_cn63xx cn63xxp1; + struct cvmx_gmxx_tx_int_en_s cn66xx; + struct cvmx_gmxx_tx_int_en_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t xchange:1; + uint64_t ptp_lost:4; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t pko_nxp:1; + uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t pko_nxp:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t ptp_lost:4; + uint64_t xchange:1; + uint64_t reserved_25_63:39; +#endif + } cn68xx; + struct cvmx_gmxx_tx_int_en_cn68xx cn68xxp1; + struct cvmx_gmxx_tx_int_en_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t xchange:1; + uint64_t reserved_22_23:2; + uint64_t ptp_lost:2; + uint64_t reserved_18_19:2; + uint64_t late_col:2; + uint64_t reserved_14_15:2; + uint64_t xsdef:2; + uint64_t reserved_10_11:2; + uint64_t xscol:2; + uint64_t reserved_4_7:4; + uint64_t undflw:2; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:2; + uint64_t reserved_4_7:4; + uint64_t xscol:2; + uint64_t reserved_10_11:2; + uint64_t xsdef:2; + uint64_t reserved_14_15:2; + uint64_t late_col:2; + uint64_t reserved_18_19:2; + uint64_t ptp_lost:2; + uint64_t reserved_22_23:2; + uint64_t xchange:1; + uint64_t reserved_25_63:39; +#endif + } cnf71xx; }; union cvmx_gmxx_tx_int_reg { uint64_t u64; struct cvmx_gmxx_tx_int_reg_s { - uint64_t reserved_20_63:44; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t xchange:1; + uint64_t ptp_lost:4; uint64_t late_col:4; uint64_t xsdef:4; uint64_t xscol:4; uint64_t reserved_6_7:2; uint64_t undflw:4; - uint64_t ncb_nxa:1; + uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t ptp_lost:4; + uint64_t xchange:1; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_gmxx_tx_int_reg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t late_col:3; uint64_t reserved_15_15:1; @@ -2261,8 +6334,21 @@ union cvmx_gmxx_tx_int_reg { uint64_t undflw:3; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:3; + uint64_t reserved_5_7:3; + uint64_t xscol:3; + uint64_t reserved_11_11:1; + uint64_t xsdef:3; + uint64_t reserved_15_15:1; + uint64_t late_col:3; + uint64_t reserved_19_63:45; +#endif } cn30xx; struct cvmx_gmxx_tx_int_reg_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t xsdef:3; uint64_t reserved_11_11:1; @@ -2271,9 +6357,40 @@ union cvmx_gmxx_tx_int_reg { uint64_t undflw:3; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:3; + uint64_t reserved_5_7:3; + uint64_t xscol:3; + uint64_t reserved_11_11:1; + uint64_t xsdef:3; + uint64_t reserved_15_63:49; +#endif } cn31xx; - struct cvmx_gmxx_tx_int_reg_s cn38xx; + struct cvmx_gmxx_tx_int_reg_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t ncb_nxa:1; + uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t ncb_nxa:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t reserved_20_63:44; +#endif + } cn38xx; struct cvmx_gmxx_tx_int_reg_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t xsdef:4; uint64_t xscol:4; @@ -2281,9 +6398,19 @@ union cvmx_gmxx_tx_int_reg { uint64_t undflw:4; uint64_t ncb_nxa:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t ncb_nxa:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t reserved_16_63:48; +#endif } cn38xxp2; struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx; struct cvmx_gmxx_tx_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t late_col:4; uint64_t xsdef:4; @@ -2292,19 +6419,119 @@ union cvmx_gmxx_tx_int_reg { uint64_t undflw:4; uint64_t reserved_1_1:1; uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1; struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx; struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1; - struct cvmx_gmxx_tx_int_reg_s cn58xx; - struct cvmx_gmxx_tx_int_reg_s cn58xxp1; + struct cvmx_gmxx_tx_int_reg_cn38xx cn58xx; + struct cvmx_gmxx_tx_int_reg_cn38xx cn58xxp1; + struct cvmx_gmxx_tx_int_reg_s cn61xx; + struct cvmx_gmxx_tx_int_reg_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_24_63:40; + uint64_t ptp_lost:4; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t ptp_lost:4; + uint64_t reserved_24_63:40; +#endif + } cn63xx; + struct cvmx_gmxx_tx_int_reg_cn63xx cn63xxp1; + struct cvmx_gmxx_tx_int_reg_s cn66xx; + struct cvmx_gmxx_tx_int_reg_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t xchange:1; + uint64_t ptp_lost:4; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t pko_nxp:1; + uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t pko_nxp:1; + uint64_t undflw:4; + uint64_t reserved_6_7:2; + uint64_t xscol:4; + uint64_t xsdef:4; + uint64_t late_col:4; + uint64_t ptp_lost:4; + uint64_t xchange:1; + uint64_t reserved_25_63:39; +#endif + } cn68xx; + struct cvmx_gmxx_tx_int_reg_cn68xx cn68xxp1; + struct cvmx_gmxx_tx_int_reg_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t xchange:1; + uint64_t reserved_22_23:2; + uint64_t ptp_lost:2; + uint64_t reserved_18_19:2; + uint64_t late_col:2; + uint64_t reserved_14_15:2; + uint64_t xsdef:2; + uint64_t reserved_10_11:2; + uint64_t xscol:2; + uint64_t reserved_4_7:4; + uint64_t undflw:2; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; +#else + uint64_t pko_nxa:1; + uint64_t reserved_1_1:1; + uint64_t undflw:2; + uint64_t reserved_4_7:4; + uint64_t xscol:2; + uint64_t reserved_10_11:2; + uint64_t xsdef:2; + uint64_t reserved_14_15:2; + uint64_t late_col:2; + uint64_t reserved_18_19:2; + uint64_t ptp_lost:2; + uint64_t reserved_22_23:2; + uint64_t xchange:1; + uint64_t reserved_25_63:39; +#endif + } cnf71xx; }; union cvmx_gmxx_tx_jam { uint64_t u64; struct cvmx_gmxx_tx_jam_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t jam:8; +#else + uint64_t jam:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_gmxx_tx_jam_s cn30xx; struct cvmx_gmxx_tx_jam_s cn31xx; @@ -2317,13 +6544,25 @@ union cvmx_gmxx_tx_jam { struct cvmx_gmxx_tx_jam_s cn56xxp1; struct cvmx_gmxx_tx_jam_s cn58xx; struct cvmx_gmxx_tx_jam_s cn58xxp1; + struct cvmx_gmxx_tx_jam_s cn61xx; + struct cvmx_gmxx_tx_jam_s cn63xx; + struct cvmx_gmxx_tx_jam_s cn63xxp1; + struct cvmx_gmxx_tx_jam_s cn66xx; + struct cvmx_gmxx_tx_jam_s cn68xx; + struct cvmx_gmxx_tx_jam_s cn68xxp1; + struct cvmx_gmxx_tx_jam_s cnf71xx; }; union cvmx_gmxx_tx_lfsr { uint64_t u64; struct cvmx_gmxx_tx_lfsr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t lfsr:16; +#else + uint64_t lfsr:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_tx_lfsr_s cn30xx; struct cvmx_gmxx_tx_lfsr_s cn31xx; @@ -2336,32 +6575,64 @@ union cvmx_gmxx_tx_lfsr { struct cvmx_gmxx_tx_lfsr_s cn56xxp1; struct cvmx_gmxx_tx_lfsr_s cn58xx; struct cvmx_gmxx_tx_lfsr_s cn58xxp1; + struct cvmx_gmxx_tx_lfsr_s cn61xx; + struct cvmx_gmxx_tx_lfsr_s cn63xx; + struct cvmx_gmxx_tx_lfsr_s cn63xxp1; + struct cvmx_gmxx_tx_lfsr_s cn66xx; + struct cvmx_gmxx_tx_lfsr_s cn68xx; + struct cvmx_gmxx_tx_lfsr_s cn68xxp1; + struct cvmx_gmxx_tx_lfsr_s cnf71xx; }; union cvmx_gmxx_tx_ovr_bp { uint64_t u64; struct cvmx_gmxx_tx_ovr_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t tx_prt_bp:16; uint64_t reserved_12_31:20; uint64_t en:4; uint64_t bp:4; uint64_t ign_full:4; +#else + uint64_t ign_full:4; + uint64_t bp:4; + uint64_t en:4; + uint64_t reserved_12_31:20; + uint64_t tx_prt_bp:16; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_tx_ovr_bp_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t en:3; uint64_t reserved_7_7:1; uint64_t bp:3; uint64_t reserved_3_3:1; uint64_t ign_full:3; +#else + uint64_t ign_full:3; + uint64_t reserved_3_3:1; + uint64_t bp:3; + uint64_t reserved_7_7:1; + uint64_t en:3; + uint64_t reserved_11_63:53; +#endif } cn30xx; struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx; struct cvmx_gmxx_tx_ovr_bp_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t en:4; uint64_t bp:4; uint64_t ign_full:4; +#else + uint64_t ign_full:4; + uint64_t bp:4; + uint64_t en:4; + uint64_t reserved_12_63:52; +#endif } cn38xx; struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2; struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx; @@ -2371,13 +6642,45 @@ union cvmx_gmxx_tx_ovr_bp { struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1; struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx; struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1; + struct cvmx_gmxx_tx_ovr_bp_s cn61xx; + struct cvmx_gmxx_tx_ovr_bp_s cn63xx; + struct cvmx_gmxx_tx_ovr_bp_s cn63xxp1; + struct cvmx_gmxx_tx_ovr_bp_s cn66xx; + struct cvmx_gmxx_tx_ovr_bp_s cn68xx; + struct cvmx_gmxx_tx_ovr_bp_s cn68xxp1; + struct cvmx_gmxx_tx_ovr_bp_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t tx_prt_bp:16; + uint64_t reserved_10_31:22; + uint64_t en:2; + uint64_t reserved_6_7:2; + uint64_t bp:2; + uint64_t reserved_2_3:2; + uint64_t ign_full:2; +#else + uint64_t ign_full:2; + uint64_t reserved_2_3:2; + uint64_t bp:2; + uint64_t reserved_6_7:2; + uint64_t en:2; + uint64_t reserved_10_31:22; + uint64_t tx_prt_bp:16; + uint64_t reserved_48_63:16; +#endif + } cnf71xx; }; union cvmx_gmxx_tx_pause_pkt_dmac { uint64_t u64; struct cvmx_gmxx_tx_pause_pkt_dmac_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t dmac:48; +#else + uint64_t dmac:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx; struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx; @@ -2390,13 +6693,25 @@ union cvmx_gmxx_tx_pause_pkt_dmac { struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1; struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx; struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn61xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xxp1; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn66xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xxp1; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cnf71xx; }; union cvmx_gmxx_tx_pause_pkt_type { uint64_t u64; struct cvmx_gmxx_tx_pause_pkt_type_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t type:16; +#else + uint64_t type:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx; struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx; @@ -2409,13 +6724,25 @@ union cvmx_gmxx_tx_pause_pkt_type { struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1; struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx; struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1; + struct cvmx_gmxx_tx_pause_pkt_type_s cn61xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn63xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn63xxp1; + struct cvmx_gmxx_tx_pause_pkt_type_s cn66xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn68xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn68xxp1; + struct cvmx_gmxx_tx_pause_pkt_type_s cnf71xx; }; union cvmx_gmxx_tx_prts { uint64_t u64; struct cvmx_gmxx_tx_prts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t prts:5; +#else + uint64_t prts:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_gmxx_tx_prts_s cn30xx; struct cvmx_gmxx_tx_prts_s cn31xx; @@ -2428,14 +6755,27 @@ union cvmx_gmxx_tx_prts { struct cvmx_gmxx_tx_prts_s cn56xxp1; struct cvmx_gmxx_tx_prts_s cn58xx; struct cvmx_gmxx_tx_prts_s cn58xxp1; + struct cvmx_gmxx_tx_prts_s cn61xx; + struct cvmx_gmxx_tx_prts_s cn63xx; + struct cvmx_gmxx_tx_prts_s cn63xxp1; + struct cvmx_gmxx_tx_prts_s cn66xx; + struct cvmx_gmxx_tx_prts_s cn68xx; + struct cvmx_gmxx_tx_prts_s cn68xxp1; + struct cvmx_gmxx_tx_prts_s cnf71xx; }; union cvmx_gmxx_tx_spi_ctl { uint64_t u64; struct cvmx_gmxx_tx_spi_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t tpa_clr:1; uint64_t cont_pkt:1; +#else + uint64_t cont_pkt:1; + uint64_t tpa_clr:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_gmxx_tx_spi_ctl_s cn38xx; struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2; @@ -2446,8 +6786,13 @@ union cvmx_gmxx_tx_spi_ctl { union cvmx_gmxx_tx_spi_drain { uint64_t u64; struct cvmx_gmxx_tx_spi_drain_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t drain:16; +#else + uint64_t drain:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_tx_spi_drain_s cn38xx; struct cvmx_gmxx_tx_spi_drain_s cn58xx; @@ -2457,15 +6802,28 @@ union cvmx_gmxx_tx_spi_drain { union cvmx_gmxx_tx_spi_max { uint64_t u64; struct cvmx_gmxx_tx_spi_max_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t slice:7; uint64_t max2:8; uint64_t max1:8; +#else + uint64_t max1:8; + uint64_t max2:8; + uint64_t slice:7; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_gmxx_tx_spi_max_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t max2:8; uint64_t max1:8; +#else + uint64_t max1:8; + uint64_t max2:8; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2; struct cvmx_gmxx_tx_spi_max_s cn58xx; @@ -2475,8 +6833,13 @@ union cvmx_gmxx_tx_spi_max { union cvmx_gmxx_tx_spi_roundx { uint64_t u64; struct cvmx_gmxx_tx_spi_roundx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t round:16; +#else + uint64_t round:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gmxx_tx_spi_roundx_s cn58xx; struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1; @@ -2485,8 +6848,13 @@ union cvmx_gmxx_tx_spi_roundx { union cvmx_gmxx_tx_spi_thresh { uint64_t u64; struct cvmx_gmxx_tx_spi_thresh_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t thresh:6; +#else + uint64_t thresh:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_gmxx_tx_spi_thresh_s cn38xx; struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2; @@ -2497,6 +6865,7 @@ union cvmx_gmxx_tx_spi_thresh { union cvmx_gmxx_tx_xaui_ctl { uint64_t u64; struct cvmx_gmxx_tx_xaui_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t hg_pause_hgi:2; uint64_t hg_en:1; @@ -2506,24 +6875,55 @@ union cvmx_gmxx_tx_xaui_ctl { uint64_t reserved_2_3:2; uint64_t uni_en:1; uint64_t dic_en:1; +#else + uint64_t dic_en:1; + uint64_t uni_en:1; + uint64_t reserved_2_3:2; + uint64_t ls:2; + uint64_t ls_byp:1; + uint64_t reserved_7_7:1; + uint64_t hg_en:1; + uint64_t hg_pause_hgi:2; + uint64_t reserved_11_63:53; +#endif } s; struct cvmx_gmxx_tx_xaui_ctl_s cn52xx; struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1; struct cvmx_gmxx_tx_xaui_ctl_s cn56xx; struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1; + struct cvmx_gmxx_tx_xaui_ctl_s cn61xx; + struct cvmx_gmxx_tx_xaui_ctl_s cn63xx; + struct cvmx_gmxx_tx_xaui_ctl_s cn63xxp1; + struct cvmx_gmxx_tx_xaui_ctl_s cn66xx; + struct cvmx_gmxx_tx_xaui_ctl_s cn68xx; + struct cvmx_gmxx_tx_xaui_ctl_s cn68xxp1; + struct cvmx_gmxx_tx_xaui_ctl_s cnf71xx; }; union cvmx_gmxx_xaui_ext_loopback { uint64_t u64; struct cvmx_gmxx_xaui_ext_loopback_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t en:1; uint64_t thresh:4; +#else + uint64_t thresh:4; + uint64_t en:1; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_gmxx_xaui_ext_loopback_s cn52xx; struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1; struct cvmx_gmxx_xaui_ext_loopback_s cn56xx; struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1; + struct cvmx_gmxx_xaui_ext_loopback_s cn61xx; + struct cvmx_gmxx_xaui_ext_loopback_s cn63xx; + struct cvmx_gmxx_xaui_ext_loopback_s cn63xxp1; + struct cvmx_gmxx_xaui_ext_loopback_s cn66xx; + struct cvmx_gmxx_xaui_ext_loopback_s cn68xx; + struct cvmx_gmxx_xaui_ext_loopback_s cn68xxp1; + struct cvmx_gmxx_xaui_ext_loopback_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h index 395564e8d1f..4719fcfa886 100644 --- a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -34,7 +34,10 @@ #define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8) #define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull)) #define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull)) +#define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull)) +#define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull)) #define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull)) +#define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull)) #define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull)) #define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull)) #define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16) @@ -42,6 +45,7 @@ union cvmx_gpio_bit_cfgx { uint64_t u64; struct cvmx_gpio_bit_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t synce_sel:2; uint64_t clk_gen:1; @@ -52,8 +56,21 @@ union cvmx_gpio_bit_cfgx { uint64_t int_en:1; uint64_t rx_xor:1; uint64_t tx_oe:1; +#else + uint64_t tx_oe:1; + uint64_t rx_xor:1; + uint64_t int_en:1; + uint64_t int_type:1; + uint64_t fil_cnt:4; + uint64_t fil_sel:4; + uint64_t clk_sel:2; + uint64_t clk_gen:1; + uint64_t synce_sel:2; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_gpio_bit_cfgx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t fil_sel:4; uint64_t fil_cnt:4; @@ -61,12 +78,22 @@ union cvmx_gpio_bit_cfgx { uint64_t int_en:1; uint64_t rx_xor:1; uint64_t tx_oe:1; +#else + uint64_t tx_oe:1; + uint64_t rx_xor:1; + uint64_t int_en:1; + uint64_t int_type:1; + uint64_t fil_cnt:4; + uint64_t fil_sel:4; + uint64_t reserved_12_63:52; +#endif } cn30xx; struct cvmx_gpio_bit_cfgx_cn30xx cn31xx; struct cvmx_gpio_bit_cfgx_cn30xx cn38xx; struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2; struct cvmx_gpio_bit_cfgx_cn30xx cn50xx; struct cvmx_gpio_bit_cfgx_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t clk_gen:1; uint64_t clk_sel:2; @@ -76,22 +103,44 @@ union cvmx_gpio_bit_cfgx { uint64_t int_en:1; uint64_t rx_xor:1; uint64_t tx_oe:1; +#else + uint64_t tx_oe:1; + uint64_t rx_xor:1; + uint64_t int_en:1; + uint64_t int_type:1; + uint64_t fil_cnt:4; + uint64_t fil_sel:4; + uint64_t clk_sel:2; + uint64_t clk_gen:1; + uint64_t reserved_15_63:49; +#endif } cn52xx; struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1; struct cvmx_gpio_bit_cfgx_cn52xx cn56xx; struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1; struct cvmx_gpio_bit_cfgx_cn30xx cn58xx; struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1; + struct cvmx_gpio_bit_cfgx_s cn61xx; struct cvmx_gpio_bit_cfgx_s cn63xx; struct cvmx_gpio_bit_cfgx_s cn63xxp1; + struct cvmx_gpio_bit_cfgx_s cn66xx; + struct cvmx_gpio_bit_cfgx_s cn68xx; + struct cvmx_gpio_bit_cfgx_s cn68xxp1; + struct cvmx_gpio_bit_cfgx_s cnf71xx; }; union cvmx_gpio_boot_ena { uint64_t u64; struct cvmx_gpio_boot_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t boot_ena:4; uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t boot_ena:4; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_gpio_boot_ena_s cn30xx; struct cvmx_gpio_boot_ena_s cn31xx; @@ -101,33 +150,87 @@ union cvmx_gpio_boot_ena { union cvmx_gpio_clk_genx { uint64_t u64; struct cvmx_gpio_clk_genx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t n:32; +#else + uint64_t n:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_gpio_clk_genx_s cn52xx; struct cvmx_gpio_clk_genx_s cn52xxp1; struct cvmx_gpio_clk_genx_s cn56xx; struct cvmx_gpio_clk_genx_s cn56xxp1; + struct cvmx_gpio_clk_genx_s cn61xx; struct cvmx_gpio_clk_genx_s cn63xx; struct cvmx_gpio_clk_genx_s cn63xxp1; + struct cvmx_gpio_clk_genx_s cn66xx; + struct cvmx_gpio_clk_genx_s cn68xx; + struct cvmx_gpio_clk_genx_s cn68xxp1; + struct cvmx_gpio_clk_genx_s cnf71xx; }; union cvmx_gpio_clk_qlmx { uint64_t u64; struct cvmx_gpio_clk_qlmx_s { - uint64_t reserved_3_63:61; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t qlm_sel:3; + uint64_t reserved_3_7:5; uint64_t div:1; uint64_t lane_sel:2; +#else + uint64_t lane_sel:2; + uint64_t div:1; + uint64_t reserved_3_7:5; + uint64_t qlm_sel:3; + uint64_t reserved_11_63:53; +#endif } s; - struct cvmx_gpio_clk_qlmx_s cn63xx; - struct cvmx_gpio_clk_qlmx_s cn63xxp1; + struct cvmx_gpio_clk_qlmx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t qlm_sel:2; + uint64_t reserved_3_7:5; + uint64_t div:1; + uint64_t lane_sel:2; +#else + uint64_t lane_sel:2; + uint64_t div:1; + uint64_t reserved_3_7:5; + uint64_t qlm_sel:2; + uint64_t reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_gpio_clk_qlmx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_3_63:61; + uint64_t div:1; + uint64_t lane_sel:2; +#else + uint64_t lane_sel:2; + uint64_t div:1; + uint64_t reserved_3_63:61; +#endif + } cn63xx; + struct cvmx_gpio_clk_qlmx_cn63xx cn63xxp1; + struct cvmx_gpio_clk_qlmx_cn61xx cn66xx; + struct cvmx_gpio_clk_qlmx_s cn68xx; + struct cvmx_gpio_clk_qlmx_s cn68xxp1; + struct cvmx_gpio_clk_qlmx_cn61xx cnf71xx; }; union cvmx_gpio_dbg_ena { uint64_t u64; struct cvmx_gpio_dbg_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t dbg_ena:21; +#else + uint64_t dbg_ena:21; + uint64_t reserved_21_63:43; +#endif } s; struct cvmx_gpio_dbg_ena_s cn30xx; struct cvmx_gpio_dbg_ena_s cn31xx; @@ -137,8 +240,13 @@ union cvmx_gpio_dbg_ena { union cvmx_gpio_int_clr { uint64_t u64; struct cvmx_gpio_int_clr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t type:16; +#else + uint64_t type:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_gpio_int_clr_s cn30xx; struct cvmx_gpio_int_clr_s cn31xx; @@ -151,21 +259,69 @@ union cvmx_gpio_int_clr { struct cvmx_gpio_int_clr_s cn56xxp1; struct cvmx_gpio_int_clr_s cn58xx; struct cvmx_gpio_int_clr_s cn58xxp1; + struct cvmx_gpio_int_clr_s cn61xx; struct cvmx_gpio_int_clr_s cn63xx; struct cvmx_gpio_int_clr_s cn63xxp1; + struct cvmx_gpio_int_clr_s cn66xx; + struct cvmx_gpio_int_clr_s cn68xx; + struct cvmx_gpio_int_clr_s cn68xxp1; + struct cvmx_gpio_int_clr_s cnf71xx; +}; + +union cvmx_gpio_multi_cast { + uint64_t u64; + struct cvmx_gpio_multi_cast_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t en:1; +#else + uint64_t en:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_gpio_multi_cast_s cn61xx; + struct cvmx_gpio_multi_cast_s cnf71xx; +}; + +union cvmx_gpio_pin_ena { + uint64_t u64; + struct cvmx_gpio_pin_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t ena19:1; + uint64_t ena18:1; + uint64_t reserved_0_17:18; +#else + uint64_t reserved_0_17:18; + uint64_t ena18:1; + uint64_t ena19:1; + uint64_t reserved_20_63:44; +#endif + } s; + struct cvmx_gpio_pin_ena_s cn66xx; }; union cvmx_gpio_rx_dat { uint64_t u64; struct cvmx_gpio_rx_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t dat:24; +#else + uint64_t dat:24; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_gpio_rx_dat_s cn30xx; struct cvmx_gpio_rx_dat_s cn31xx; struct cvmx_gpio_rx_dat_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dat:16; +#else + uint64_t dat:16; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_gpio_rx_dat_cn38xx cn38xxp2; struct cvmx_gpio_rx_dat_s cn50xx; @@ -175,21 +331,59 @@ union cvmx_gpio_rx_dat { struct cvmx_gpio_rx_dat_cn38xx cn56xxp1; struct cvmx_gpio_rx_dat_cn38xx cn58xx; struct cvmx_gpio_rx_dat_cn38xx cn58xxp1; + struct cvmx_gpio_rx_dat_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t dat:20; +#else + uint64_t dat:20; + uint64_t reserved_20_63:44; +#endif + } cn61xx; struct cvmx_gpio_rx_dat_cn38xx cn63xx; struct cvmx_gpio_rx_dat_cn38xx cn63xxp1; + struct cvmx_gpio_rx_dat_cn61xx cn66xx; + struct cvmx_gpio_rx_dat_cn38xx cn68xx; + struct cvmx_gpio_rx_dat_cn38xx cn68xxp1; + struct cvmx_gpio_rx_dat_cn61xx cnf71xx; +}; + +union cvmx_gpio_tim_ctl { + uint64_t u64; + struct cvmx_gpio_tim_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t sel:4; +#else + uint64_t sel:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_gpio_tim_ctl_s cn68xx; + struct cvmx_gpio_tim_ctl_s cn68xxp1; }; union cvmx_gpio_tx_clr { uint64_t u64; struct cvmx_gpio_tx_clr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t clr:24; +#else + uint64_t clr:24; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_gpio_tx_clr_s cn30xx; struct cvmx_gpio_tx_clr_s cn31xx; struct cvmx_gpio_tx_clr_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t clr:16; +#else + uint64_t clr:16; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_gpio_tx_clr_cn38xx cn38xxp2; struct cvmx_gpio_tx_clr_s cn50xx; @@ -199,21 +393,44 @@ union cvmx_gpio_tx_clr { struct cvmx_gpio_tx_clr_cn38xx cn56xxp1; struct cvmx_gpio_tx_clr_cn38xx cn58xx; struct cvmx_gpio_tx_clr_cn38xx cn58xxp1; + struct cvmx_gpio_tx_clr_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t clr:20; +#else + uint64_t clr:20; + uint64_t reserved_20_63:44; +#endif + } cn61xx; struct cvmx_gpio_tx_clr_cn38xx cn63xx; struct cvmx_gpio_tx_clr_cn38xx cn63xxp1; + struct cvmx_gpio_tx_clr_cn61xx cn66xx; + struct cvmx_gpio_tx_clr_cn38xx cn68xx; + struct cvmx_gpio_tx_clr_cn38xx cn68xxp1; + struct cvmx_gpio_tx_clr_cn61xx cnf71xx; }; union cvmx_gpio_tx_set { uint64_t u64; struct cvmx_gpio_tx_set_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t set:24; +#else + uint64_t set:24; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_gpio_tx_set_s cn30xx; struct cvmx_gpio_tx_set_s cn31xx; struct cvmx_gpio_tx_set_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t set:16; +#else + uint64_t set:16; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_gpio_tx_set_cn38xx cn38xxp2; struct cvmx_gpio_tx_set_s cn50xx; @@ -223,23 +440,72 @@ union cvmx_gpio_tx_set { struct cvmx_gpio_tx_set_cn38xx cn56xxp1; struct cvmx_gpio_tx_set_cn38xx cn58xx; struct cvmx_gpio_tx_set_cn38xx cn58xxp1; + struct cvmx_gpio_tx_set_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t set:20; +#else + uint64_t set:20; + uint64_t reserved_20_63:44; +#endif + } cn61xx; struct cvmx_gpio_tx_set_cn38xx cn63xx; struct cvmx_gpio_tx_set_cn38xx cn63xxp1; + struct cvmx_gpio_tx_set_cn61xx cn66xx; + struct cvmx_gpio_tx_set_cn38xx cn68xx; + struct cvmx_gpio_tx_set_cn38xx cn68xxp1; + struct cvmx_gpio_tx_set_cn61xx cnf71xx; }; union cvmx_gpio_xbit_cfgx { uint64_t u64; struct cvmx_gpio_xbit_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_17_63:47; + uint64_t synce_sel:2; + uint64_t clk_gen:1; + uint64_t clk_sel:2; + uint64_t fil_sel:4; + uint64_t fil_cnt:4; + uint64_t int_type:1; + uint64_t int_en:1; + uint64_t rx_xor:1; + uint64_t tx_oe:1; +#else + uint64_t tx_oe:1; + uint64_t rx_xor:1; + uint64_t int_en:1; + uint64_t int_type:1; + uint64_t fil_cnt:4; + uint64_t fil_sel:4; + uint64_t clk_sel:2; + uint64_t clk_gen:1; + uint64_t synce_sel:2; + uint64_t reserved_17_63:47; +#endif + } s; + struct cvmx_gpio_xbit_cfgx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t fil_sel:4; uint64_t fil_cnt:4; uint64_t reserved_2_3:2; uint64_t rx_xor:1; uint64_t tx_oe:1; - } s; - struct cvmx_gpio_xbit_cfgx_s cn30xx; - struct cvmx_gpio_xbit_cfgx_s cn31xx; - struct cvmx_gpio_xbit_cfgx_s cn50xx; +#else + uint64_t tx_oe:1; + uint64_t rx_xor:1; + uint64_t reserved_2_3:2; + uint64_t fil_cnt:4; + uint64_t fil_sel:4; + uint64_t reserved_12_63:52; +#endif + } cn30xx; + struct cvmx_gpio_xbit_cfgx_cn30xx cn31xx; + struct cvmx_gpio_xbit_cfgx_cn30xx cn50xx; + struct cvmx_gpio_xbit_cfgx_s cn61xx; + struct cvmx_gpio_xbit_cfgx_s cn66xx; + struct cvmx_gpio_xbit_cfgx_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h index 88527fa835c..893320375ae 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-board.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-board.h @@ -34,7 +34,14 @@ #ifndef __CVMX_HELPER_BOARD_H__ #define __CVMX_HELPER_BOARD_H__ -#include "cvmx-helper.h" +#include <asm/octeon/cvmx-helper.h> + +enum cvmx_helper_board_usb_clock_types { + USB_CLOCK_TYPE_REF_12, + USB_CLOCK_TYPE_REF_24, + USB_CLOCK_TYPE_REF_48, + USB_CLOCK_TYPE_CRYSTAL_12, +}; typedef enum { set_phy_link_flags_autoneg = 0x1, @@ -48,7 +55,7 @@ typedef enum { * Fake IPD port, the RGMII/MII interface may use different PHY, use * this macro to return appropriate MIX address to read the PHY. */ -#define CVMX_HELPER_BOARD_MGMT_IPD_PORT -10 +#define CVMX_HELPER_BOARD_MGMT_IPD_PORT -10 /** * cvmx_override_board_link_get(int ipd_port) is a function @@ -86,10 +93,10 @@ extern int cvmx_helper_board_get_mii_address(int ipd_port); * * @phy_addr: The address of the PHY to program * @link_flags: - * Flags to control autonegotiation. Bit 0 is autonegotiation - * enable/disable to maintain backware compatibility. + * Flags to control autonegotiation. Bit 0 is autonegotiation + * enable/disable to maintain backware compatibility. * @link_info: Link speed to program. If the speed is zero and autonegotiation - * is enabled, all possible negotiation speeds are advertised. + * is enabled, all possible negotiation speeds are advertised. * * Returns Zero on success, negative on failure */ @@ -111,10 +118,10 @@ int cvmx_helper_board_link_set_phy(int phy_addr, * enumeration from the bootloader. * * @ipd_port: IPD input port associated with the port we want to get link - * status for. + * status for. * * Returns The ports link status. If the link isn't fully resolved, this must - * return zero. + * return zero. */ extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port); @@ -134,10 +141,10 @@ extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port); * * @interface: Interface to probe * @supported_ports: - * Number of ports Octeon supports. + * Number of ports Octeon supports. * * Returns Number of ports the actual board supports. Many times this will - * simple be "support_ports". + * simple be "support_ports". */ extern int __cvmx_helper_board_interface_probe(int interface, int supported_ports); @@ -154,4 +161,6 @@ extern int __cvmx_helper_board_interface_probe(int interface, */ extern int __cvmx_helper_board_hardware_enable(int interface); +enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void); + #endif /* __CVMX_HELPER_BOARD_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-helper-fpa.h b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h deleted file mode 100644 index 5ff8c93198d..00000000000 --- a/arch/mips/include/asm/octeon/cvmx-helper-fpa.h +++ /dev/null @@ -1,64 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * @file - * - * Helper functions for FPA setup. - * - */ -#ifndef __CVMX_HELPER_H_FPA__ -#define __CVMX_HELPER_H_FPA__ - -/** - * Allocate memory and initialize the FPA pools using memory - * from cvmx-bootmem. Sizes of each element in the pools is - * controlled by the cvmx-config.h header file. Specifying - * zero for any parameter will cause that FPA pool to not be - * setup. This is useful if you aren't using some of the - * hardware and want to save memory. - * - * @packet_buffers: - * Number of packet buffers to allocate - * @work_queue_entries: - * Number of work queue entries - * @pko_buffers: - * PKO Command buffers. You should at minimum have two per - * each PKO queue. - * @tim_buffers: - * TIM ring buffer command queues. At least two per timer bucket - * is recommened. - * @dfa_buffers: - * DFA command buffer. A relatively small (32 for example) - * number should work. - * Returns Zero on success, non-zero if out of memory - */ -extern int cvmx_helper_initialize_fpa(int packet_buffers, - int work_queue_entries, int pko_buffers, - int tim_buffers, int dfa_buffers); - -#endif /* __CVMX_HELPER_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h index 78295ba0050..4d7a3db3a9f 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h @@ -98,9 +98,9 @@ extern int __cvmx_helper_rgmii_link_set(int ipd_port, * * @ipd_port: IPD/PKO port to loopback. * @enable_internal: - * Non zero if you want internal loopback + * Non zero if you want internal loopback * @enable_external: - * Non zero if you want external loopback + * Non zero if you want external loopback * * Returns Zero on success, negative on failure. */ diff --git a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h index 9a9b6c103ed..4debb1c5153 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h @@ -92,9 +92,9 @@ extern int __cvmx_helper_sgmii_link_set(int ipd_port, * * @ipd_port: IPD/PKO port to loopback. * @enable_internal: - * Non zero if you want internal loopback + * Non zero if you want internal loopback * @enable_external: - * Non zero if you want external loopback + * Non zero if you want external loopback * * Returns Zero on success, negative on failure. */ diff --git a/arch/mips/include/asm/octeon/cvmx-helper-util.h b/arch/mips/include/asm/octeon/cvmx-helper-util.h index 6a6e52fc22c..f446f212bbd 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-util.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-util.h @@ -57,11 +57,11 @@ extern int cvmx_helper_dump_packet(cvmx_wqe_t *work); * * @queue: Input queue to setup RED on (0-7) * @pass_thresh: - * Packets will begin slowly dropping when there are less than - * this many packet buffers free in FPA 0. + * Packets will begin slowly dropping when there are less than + * this many packet buffers free in FPA 0. * @drop_thresh: - * All incomming packets will be dropped when there are less - * than this many free packet buffers in FPA 0. + * All incoming packets will be dropped when there are less + * than this many free packet buffers in FPA 0. * Returns Zero on success. Negative on failure */ extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh, @@ -71,11 +71,11 @@ extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh, * Setup Random Early Drop to automatically begin dropping packets. * * @pass_thresh: - * Packets will begin slowly dropping when there are less than - * this many packet buffers free in FPA 0. + * Packets will begin slowly dropping when there are less than + * this many packet buffers free in FPA 0. * @drop_thresh: - * All incomming packets will be dropped when there are less - * than this many free packet buffers in FPA 0. + * All incoming packets will be dropped when there are less + * than this many free packet buffers in FPA 0. * Returns Zero on success. Negative on failure */ extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh); @@ -84,7 +84,7 @@ extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh); * Get the version of the CVMX libraries. * * Returns Version string. Note this buffer is allocated statically - * and will be shared by all callers. + * and will be shared by all callers. */ extern const char *cvmx_helper_get_version(void); diff --git a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h index f6fbc4f45b5..5e89ed703ea 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h +++ b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h @@ -92,9 +92,9 @@ extern int __cvmx_helper_xaui_link_set(int ipd_port, * * @ipd_port: IPD/PKO port to loopback. * @enable_internal: - * Non zero if you want internal loopback + * Non zero if you want internal loopback * @enable_external: - * Non zero if you want external loopback + * Non zero if you want external loopback * * Returns Zero on success, negative on failure. */ diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h index 3169cd79f2a..5a3090dc6f2 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper.h +++ b/arch/mips/include/asm/octeon/cvmx-helper.h @@ -34,9 +34,9 @@ #ifndef __CVMX_HELPER_H__ #define __CVMX_HELPER_H__ -#include "cvmx-config.h" -#include "cvmx-fpa.h" -#include "cvmx-wqe.h" +#include <asm/octeon/cvmx-config.h> +#include <asm/octeon/cvmx-fpa.h> +#include <asm/octeon/cvmx-wqe.h> typedef enum { CVMX_HELPER_INTERFACE_MODE_DISABLED, @@ -61,16 +61,14 @@ typedef union { } s; } cvmx_helper_link_info_t; -#include "cvmx-helper-fpa.h" - #include <asm/octeon/cvmx-helper-errata.h> -#include "cvmx-helper-loop.h" -#include "cvmx-helper-npi.h" -#include "cvmx-helper-rgmii.h" -#include "cvmx-helper-sgmii.h" -#include "cvmx-helper-spi.h" -#include "cvmx-helper-util.h" -#include "cvmx-helper-xaui.h" +#include <asm/octeon/cvmx-helper-loop.h> +#include <asm/octeon/cvmx-helper-npi.h> +#include <asm/octeon/cvmx-helper-rgmii.h> +#include <asm/octeon/cvmx-helper-sgmii.h> +#include <asm/octeon/cvmx-helper-spi.h> +#include <asm/octeon/cvmx-helper-util.h> +#include <asm/octeon/cvmx-helper-xaui.h> /** * cvmx_override_pko_queue_priority(int ipd_port, uint64_t @@ -95,12 +93,12 @@ extern void (*cvmx_override_ipd_port_setup) (int ipd_port); /** * This function enables the IPD and also enables the packet interfaces. * The packet interfaces (RGMII and SPI) must be enabled after the - * IPD. This should be called by the user program after any additional + * IPD. This should be called by the user program after any additional * IPD configuration changes are made if CVMX_HELPER_ENABLE_IPD * is not set in the executive-config.h file. * * Returns 0 on success - * -1 on failure + * -1 on failure */ extern int cvmx_helper_ipd_and_packet_input_enable(void); @@ -130,7 +128,7 @@ extern int cvmx_helper_initialize_packet_io_local(void); * @interface: Which interface to return port count for. * * Returns Port count for interface - * -1 for uninitialized interface + * -1 for uninitialized interface */ extern int cvmx_helper_ports_on_interface(int interface); @@ -152,7 +150,7 @@ extern int cvmx_helper_get_number_of_interfaces(void); * @interface: Interface to probe * * Returns Mode of the interface. Unknown or unsupported interfaces return - * DISABLED. + * DISABLED. */ extern cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface); @@ -216,9 +214,9 @@ extern int cvmx_helper_interface_enumerate(int interface); * * @ipd_port: IPD/PKO port to loopback. * @enable_internal: - * Non zero if you want internal loopback + * Non zero if you want internal loopback * @enable_external: - * Non zero if you want external loopback + * Non zero if you want external loopback * * Returns Zero on success, negative on failure. */ diff --git a/arch/mips/include/asm/octeon/cvmx-iob-defs.h b/arch/mips/include/asm/octeon/cvmx-iob-defs.h index d7d856c2483..7936f816e93 100644 --- a/arch/mips/include/asm/octeon/cvmx-iob-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-iob-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -51,10 +51,86 @@ #define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull)) #define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull)) #define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull)) +#define CVMX_IOB_TO_NCB_DID_00_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000800ull)) +#define CVMX_IOB_TO_NCB_DID_111_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B78ull)) +#define CVMX_IOB_TO_NCB_DID_223_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000EF8ull)) +#define CVMX_IOB_TO_NCB_DID_24_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00008C0ull)) +#define CVMX_IOB_TO_NCB_DID_32_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000900ull)) +#define CVMX_IOB_TO_NCB_DID_40_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000940ull)) +#define CVMX_IOB_TO_NCB_DID_55_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00009B8ull)) +#define CVMX_IOB_TO_NCB_DID_64_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A00ull)) +#define CVMX_IOB_TO_NCB_DID_79_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A78ull)) +#define CVMX_IOB_TO_NCB_DID_96_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B00ull)) +#define CVMX_IOB_TO_NCB_DID_98_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B10ull)) union cvmx_iob_bist_status { uint64_t u64; struct cvmx_iob_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_2_63:62; + uint64_t ibd:1; + uint64_t icd:1; +#else + uint64_t icd:1; + uint64_t ibd:1; + uint64_t reserved_2_63:62; +#endif + } s; + struct cvmx_iob_bist_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_18_63:46; + uint64_t icnrcb:1; + uint64_t icr0:1; + uint64_t icr1:1; + uint64_t icnr1:1; + uint64_t icnr0:1; + uint64_t ibdr0:1; + uint64_t ibdr1:1; + uint64_t ibr0:1; + uint64_t ibr1:1; + uint64_t icnrt:1; + uint64_t ibrq0:1; + uint64_t ibrq1:1; + uint64_t icrn0:1; + uint64_t icrn1:1; + uint64_t icrp0:1; + uint64_t icrp1:1; + uint64_t ibd:1; + uint64_t icd:1; +#else + uint64_t icd:1; + uint64_t ibd:1; + uint64_t icrp1:1; + uint64_t icrp0:1; + uint64_t icrn1:1; + uint64_t icrn0:1; + uint64_t ibrq1:1; + uint64_t ibrq0:1; + uint64_t icnrt:1; + uint64_t ibr1:1; + uint64_t ibr0:1; + uint64_t ibdr1:1; + uint64_t ibdr0:1; + uint64_t icnr0:1; + uint64_t icnr1:1; + uint64_t icr1:1; + uint64_t icr0:1; + uint64_t icnrcb:1; + uint64_t reserved_18_63:46; +#endif + } cn30xx; + struct cvmx_iob_bist_status_cn30xx cn31xx; + struct cvmx_iob_bist_status_cn30xx cn38xx; + struct cvmx_iob_bist_status_cn30xx cn38xxp2; + struct cvmx_iob_bist_status_cn30xx cn50xx; + struct cvmx_iob_bist_status_cn30xx cn52xx; + struct cvmx_iob_bist_status_cn30xx cn52xxp1; + struct cvmx_iob_bist_status_cn30xx cn56xx; + struct cvmx_iob_bist_status_cn30xx cn56xxp1; + struct cvmx_iob_bist_status_cn30xx cn58xx; + struct cvmx_iob_bist_status_cn30xx cn58xxp1; + struct cvmx_iob_bist_status_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t xmdfif:1; uint64_t xmcfif:1; @@ -79,16 +155,48 @@ union cvmx_iob_bist_status { uint64_t icrp1:1; uint64_t ibd:1; uint64_t icd:1; - } s; - struct cvmx_iob_bist_status_cn30xx { +#else + uint64_t icd:1; + uint64_t ibd:1; + uint64_t icrp1:1; + uint64_t icrp0:1; + uint64_t icrn1:1; + uint64_t icrn0:1; + uint64_t ibrq1:1; + uint64_t ibrq0:1; + uint64_t icnrt:1; + uint64_t ibr1:1; + uint64_t ibr0:1; + uint64_t ibdr1:1; + uint64_t ibdr0:1; + uint64_t icnr0:1; + uint64_t icnr1:1; + uint64_t icr1:1; + uint64_t icr0:1; + uint64_t icnrcb:1; + uint64_t iocfif:1; + uint64_t rsdfif:1; + uint64_t iorfif:1; + uint64_t xmcfif:1; + uint64_t xmdfif:1; + uint64_t reserved_23_63:41; +#endif + } cn61xx; + struct cvmx_iob_bist_status_cn61xx cn63xx; + struct cvmx_iob_bist_status_cn61xx cn63xxp1; + struct cvmx_iob_bist_status_cn61xx cn66xx; + struct cvmx_iob_bist_status_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; + uint64_t xmdfif:1; + uint64_t xmcfif:1; + uint64_t iorfif:1; + uint64_t rsdfif:1; + uint64_t iocfif:1; uint64_t icnrcb:1; uint64_t icr0:1; uint64_t icr1:1; - uint64_t icnr1:1; uint64_t icnr0:1; - uint64_t ibdr0:1; - uint64_t ibdr1:1; uint64_t ibr0:1; uint64_t ibr1:1; uint64_t icnrt:1; @@ -96,50 +204,82 @@ union cvmx_iob_bist_status { uint64_t ibrq1:1; uint64_t icrn0:1; uint64_t icrn1:1; - uint64_t icrp0:1; - uint64_t icrp1:1; uint64_t ibd:1; uint64_t icd:1; - } cn30xx; - struct cvmx_iob_bist_status_cn30xx cn31xx; - struct cvmx_iob_bist_status_cn30xx cn38xx; - struct cvmx_iob_bist_status_cn30xx cn38xxp2; - struct cvmx_iob_bist_status_cn30xx cn50xx; - struct cvmx_iob_bist_status_cn30xx cn52xx; - struct cvmx_iob_bist_status_cn30xx cn52xxp1; - struct cvmx_iob_bist_status_cn30xx cn56xx; - struct cvmx_iob_bist_status_cn30xx cn56xxp1; - struct cvmx_iob_bist_status_cn30xx cn58xx; - struct cvmx_iob_bist_status_cn30xx cn58xxp1; - struct cvmx_iob_bist_status_s cn63xx; - struct cvmx_iob_bist_status_s cn63xxp1; +#else + uint64_t icd:1; + uint64_t ibd:1; + uint64_t icrn1:1; + uint64_t icrn0:1; + uint64_t ibrq1:1; + uint64_t ibrq0:1; + uint64_t icnrt:1; + uint64_t ibr1:1; + uint64_t ibr0:1; + uint64_t icnr0:1; + uint64_t icr1:1; + uint64_t icr0:1; + uint64_t icnrcb:1; + uint64_t iocfif:1; + uint64_t rsdfif:1; + uint64_t iorfif:1; + uint64_t xmcfif:1; + uint64_t xmdfif:1; + uint64_t reserved_18_63:46; +#endif + } cn68xx; + struct cvmx_iob_bist_status_cn68xx cn68xxp1; + struct cvmx_iob_bist_status_cn61xx cnf71xx; }; union cvmx_iob_ctl_status { uint64_t u64; struct cvmx_iob_ctl_status_s { - uint64_t reserved_10_63:54; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t fif_dly:1; uint64_t xmc_per:4; - uint64_t rr_mode:1; + uint64_t reserved_5_5:1; uint64_t outb_mat:1; uint64_t inb_mat:1; uint64_t pko_enb:1; uint64_t dwb_enb:1; uint64_t fau_end:1; +#else + uint64_t fau_end:1; + uint64_t dwb_enb:1; + uint64_t pko_enb:1; + uint64_t inb_mat:1; + uint64_t outb_mat:1; + uint64_t reserved_5_5:1; + uint64_t xmc_per:4; + uint64_t fif_dly:1; + uint64_t reserved_11_63:53; +#endif } s; struct cvmx_iob_ctl_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t outb_mat:1; uint64_t inb_mat:1; uint64_t pko_enb:1; uint64_t dwb_enb:1; uint64_t fau_end:1; +#else + uint64_t fau_end:1; + uint64_t dwb_enb:1; + uint64_t pko_enb:1; + uint64_t inb_mat:1; + uint64_t outb_mat:1; + uint64_t reserved_5_63:59; +#endif } cn30xx; struct cvmx_iob_ctl_status_cn30xx cn31xx; struct cvmx_iob_ctl_status_cn30xx cn38xx; struct cvmx_iob_ctl_status_cn30xx cn38xxp2; struct cvmx_iob_ctl_status_cn30xx cn50xx; struct cvmx_iob_ctl_status_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t rr_mode:1; uint64_t outb_mat:1; @@ -147,22 +287,106 @@ union cvmx_iob_ctl_status { uint64_t pko_enb:1; uint64_t dwb_enb:1; uint64_t fau_end:1; +#else + uint64_t fau_end:1; + uint64_t dwb_enb:1; + uint64_t pko_enb:1; + uint64_t inb_mat:1; + uint64_t outb_mat:1; + uint64_t rr_mode:1; + uint64_t reserved_6_63:58; +#endif } cn52xx; struct cvmx_iob_ctl_status_cn30xx cn52xxp1; struct cvmx_iob_ctl_status_cn30xx cn56xx; struct cvmx_iob_ctl_status_cn30xx cn56xxp1; struct cvmx_iob_ctl_status_cn30xx cn58xx; struct cvmx_iob_ctl_status_cn30xx cn58xxp1; - struct cvmx_iob_ctl_status_s cn63xx; - struct cvmx_iob_ctl_status_s cn63xxp1; + struct cvmx_iob_ctl_status_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t fif_dly:1; + uint64_t xmc_per:4; + uint64_t rr_mode:1; + uint64_t outb_mat:1; + uint64_t inb_mat:1; + uint64_t pko_enb:1; + uint64_t dwb_enb:1; + uint64_t fau_end:1; +#else + uint64_t fau_end:1; + uint64_t dwb_enb:1; + uint64_t pko_enb:1; + uint64_t inb_mat:1; + uint64_t outb_mat:1; + uint64_t rr_mode:1; + uint64_t xmc_per:4; + uint64_t fif_dly:1; + uint64_t reserved_11_63:53; +#endif + } cn61xx; + struct cvmx_iob_ctl_status_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t xmc_per:4; + uint64_t rr_mode:1; + uint64_t outb_mat:1; + uint64_t inb_mat:1; + uint64_t pko_enb:1; + uint64_t dwb_enb:1; + uint64_t fau_end:1; +#else + uint64_t fau_end:1; + uint64_t dwb_enb:1; + uint64_t pko_enb:1; + uint64_t inb_mat:1; + uint64_t outb_mat:1; + uint64_t rr_mode:1; + uint64_t xmc_per:4; + uint64_t reserved_10_63:54; +#endif + } cn63xx; + struct cvmx_iob_ctl_status_cn63xx cn63xxp1; + struct cvmx_iob_ctl_status_cn61xx cn66xx; + struct cvmx_iob_ctl_status_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t fif_dly:1; + uint64_t xmc_per:4; + uint64_t rsvr5:1; + uint64_t outb_mat:1; + uint64_t inb_mat:1; + uint64_t pko_enb:1; + uint64_t dwb_enb:1; + uint64_t fau_end:1; +#else + uint64_t fau_end:1; + uint64_t dwb_enb:1; + uint64_t pko_enb:1; + uint64_t inb_mat:1; + uint64_t outb_mat:1; + uint64_t rsvr5:1; + uint64_t xmc_per:4; + uint64_t fif_dly:1; + uint64_t reserved_11_63:53; +#endif + } cn68xx; + struct cvmx_iob_ctl_status_cn68xx cn68xxp1; + struct cvmx_iob_ctl_status_cn61xx cnf71xx; }; union cvmx_iob_dwb_pri_cnt { uint64_t u64; struct cvmx_iob_dwb_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; +#else + uint64_t cnt_val:15; + uint64_t cnt_enb:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_iob_dwb_pri_cnt_s cn38xx; struct cvmx_iob_dwb_pri_cnt_s cn38xxp2; @@ -172,16 +396,25 @@ union cvmx_iob_dwb_pri_cnt { struct cvmx_iob_dwb_pri_cnt_s cn56xxp1; struct cvmx_iob_dwb_pri_cnt_s cn58xx; struct cvmx_iob_dwb_pri_cnt_s cn58xxp1; + struct cvmx_iob_dwb_pri_cnt_s cn61xx; struct cvmx_iob_dwb_pri_cnt_s cn63xx; struct cvmx_iob_dwb_pri_cnt_s cn63xxp1; + struct cvmx_iob_dwb_pri_cnt_s cn66xx; + struct cvmx_iob_dwb_pri_cnt_s cnf71xx; }; union cvmx_iob_fau_timeout { uint64_t u64; struct cvmx_iob_fau_timeout_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t tout_enb:1; uint64_t tout_val:12; +#else + uint64_t tout_val:12; + uint64_t tout_enb:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_iob_fau_timeout_s cn30xx; struct cvmx_iob_fau_timeout_s cn31xx; @@ -194,16 +427,27 @@ union cvmx_iob_fau_timeout { struct cvmx_iob_fau_timeout_s cn56xxp1; struct cvmx_iob_fau_timeout_s cn58xx; struct cvmx_iob_fau_timeout_s cn58xxp1; + struct cvmx_iob_fau_timeout_s cn61xx; struct cvmx_iob_fau_timeout_s cn63xx; struct cvmx_iob_fau_timeout_s cn63xxp1; + struct cvmx_iob_fau_timeout_s cn66xx; + struct cvmx_iob_fau_timeout_s cn68xx; + struct cvmx_iob_fau_timeout_s cn68xxp1; + struct cvmx_iob_fau_timeout_s cnf71xx; }; union cvmx_iob_i2c_pri_cnt { uint64_t u64; struct cvmx_iob_i2c_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; +#else + uint64_t cnt_val:15; + uint64_t cnt_enb:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_iob_i2c_pri_cnt_s cn38xx; struct cvmx_iob_i2c_pri_cnt_s cn38xxp2; @@ -213,18 +457,29 @@ union cvmx_iob_i2c_pri_cnt { struct cvmx_iob_i2c_pri_cnt_s cn56xxp1; struct cvmx_iob_i2c_pri_cnt_s cn58xx; struct cvmx_iob_i2c_pri_cnt_s cn58xxp1; + struct cvmx_iob_i2c_pri_cnt_s cn61xx; struct cvmx_iob_i2c_pri_cnt_s cn63xx; struct cvmx_iob_i2c_pri_cnt_s cn63xxp1; + struct cvmx_iob_i2c_pri_cnt_s cn66xx; + struct cvmx_iob_i2c_pri_cnt_s cnf71xx; }; union cvmx_iob_inb_control_match { uint64_t u64; struct cvmx_iob_inb_control_match_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t mask:8; uint64_t opc:4; uint64_t dst:9; uint64_t src:8; +#else + uint64_t src:8; + uint64_t dst:9; + uint64_t opc:4; + uint64_t mask:8; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_iob_inb_control_match_s cn30xx; struct cvmx_iob_inb_control_match_s cn31xx; @@ -237,18 +492,31 @@ union cvmx_iob_inb_control_match { struct cvmx_iob_inb_control_match_s cn56xxp1; struct cvmx_iob_inb_control_match_s cn58xx; struct cvmx_iob_inb_control_match_s cn58xxp1; + struct cvmx_iob_inb_control_match_s cn61xx; struct cvmx_iob_inb_control_match_s cn63xx; struct cvmx_iob_inb_control_match_s cn63xxp1; + struct cvmx_iob_inb_control_match_s cn66xx; + struct cvmx_iob_inb_control_match_s cn68xx; + struct cvmx_iob_inb_control_match_s cn68xxp1; + struct cvmx_iob_inb_control_match_s cnf71xx; }; union cvmx_iob_inb_control_match_enb { uint64_t u64; struct cvmx_iob_inb_control_match_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t mask:8; uint64_t opc:4; uint64_t dst:9; uint64_t src:8; +#else + uint64_t src:8; + uint64_t dst:9; + uint64_t opc:4; + uint64_t mask:8; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_iob_inb_control_match_enb_s cn30xx; struct cvmx_iob_inb_control_match_enb_s cn31xx; @@ -261,14 +529,23 @@ union cvmx_iob_inb_control_match_enb { struct cvmx_iob_inb_control_match_enb_s cn56xxp1; struct cvmx_iob_inb_control_match_enb_s cn58xx; struct cvmx_iob_inb_control_match_enb_s cn58xxp1; + struct cvmx_iob_inb_control_match_enb_s cn61xx; struct cvmx_iob_inb_control_match_enb_s cn63xx; struct cvmx_iob_inb_control_match_enb_s cn63xxp1; + struct cvmx_iob_inb_control_match_enb_s cn66xx; + struct cvmx_iob_inb_control_match_enb_s cn68xx; + struct cvmx_iob_inb_control_match_enb_s cn68xxp1; + struct cvmx_iob_inb_control_match_enb_s cnf71xx; }; union cvmx_iob_inb_data_match { uint64_t u64; struct cvmx_iob_inb_data_match_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_iob_inb_data_match_s cn30xx; struct cvmx_iob_inb_data_match_s cn31xx; @@ -281,14 +558,23 @@ union cvmx_iob_inb_data_match { struct cvmx_iob_inb_data_match_s cn56xxp1; struct cvmx_iob_inb_data_match_s cn58xx; struct cvmx_iob_inb_data_match_s cn58xxp1; + struct cvmx_iob_inb_data_match_s cn61xx; struct cvmx_iob_inb_data_match_s cn63xx; struct cvmx_iob_inb_data_match_s cn63xxp1; + struct cvmx_iob_inb_data_match_s cn66xx; + struct cvmx_iob_inb_data_match_s cn68xx; + struct cvmx_iob_inb_data_match_s cn68xxp1; + struct cvmx_iob_inb_data_match_s cnf71xx; }; union cvmx_iob_inb_data_match_enb { uint64_t u64; struct cvmx_iob_inb_data_match_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; +#else + uint64_t data:64; +#endif } s; struct cvmx_iob_inb_data_match_enb_s cn30xx; struct cvmx_iob_inb_data_match_enb_s cn31xx; @@ -301,13 +587,19 @@ union cvmx_iob_inb_data_match_enb { struct cvmx_iob_inb_data_match_enb_s cn56xxp1; struct cvmx_iob_inb_data_match_enb_s cn58xx; struct cvmx_iob_inb_data_match_enb_s cn58xxp1; + struct cvmx_iob_inb_data_match_enb_s cn61xx; struct cvmx_iob_inb_data_match_enb_s cn63xx; struct cvmx_iob_inb_data_match_enb_s cn63xxp1; + struct cvmx_iob_inb_data_match_enb_s cn66xx; + struct cvmx_iob_inb_data_match_enb_s cn68xx; + struct cvmx_iob_inb_data_match_enb_s cn68xxp1; + struct cvmx_iob_inb_data_match_enb_s cnf71xx; }; union cvmx_iob_int_enb { uint64_t u64; struct cvmx_iob_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t p_dat:1; uint64_t np_dat:1; @@ -315,13 +607,30 @@ union cvmx_iob_int_enb { uint64_t p_sop:1; uint64_t np_eop:1; uint64_t np_sop:1; +#else + uint64_t np_sop:1; + uint64_t np_eop:1; + uint64_t p_sop:1; + uint64_t p_eop:1; + uint64_t np_dat:1; + uint64_t p_dat:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_iob_int_enb_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t p_eop:1; uint64_t p_sop:1; uint64_t np_eop:1; uint64_t np_sop:1; +#else + uint64_t np_sop:1; + uint64_t np_eop:1; + uint64_t p_sop:1; + uint64_t p_eop:1; + uint64_t reserved_4_63:60; +#endif } cn30xx; struct cvmx_iob_int_enb_cn30xx cn31xx; struct cvmx_iob_int_enb_cn30xx cn38xx; @@ -333,13 +642,25 @@ union cvmx_iob_int_enb { struct cvmx_iob_int_enb_s cn56xxp1; struct cvmx_iob_int_enb_s cn58xx; struct cvmx_iob_int_enb_s cn58xxp1; + struct cvmx_iob_int_enb_s cn61xx; struct cvmx_iob_int_enb_s cn63xx; struct cvmx_iob_int_enb_s cn63xxp1; + struct cvmx_iob_int_enb_s cn66xx; + struct cvmx_iob_int_enb_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif + } cn68xx; + struct cvmx_iob_int_enb_cn68xx cn68xxp1; + struct cvmx_iob_int_enb_s cnf71xx; }; union cvmx_iob_int_sum { uint64_t u64; struct cvmx_iob_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t p_dat:1; uint64_t np_dat:1; @@ -347,13 +668,30 @@ union cvmx_iob_int_sum { uint64_t p_sop:1; uint64_t np_eop:1; uint64_t np_sop:1; +#else + uint64_t np_sop:1; + uint64_t np_eop:1; + uint64_t p_sop:1; + uint64_t p_eop:1; + uint64_t np_dat:1; + uint64_t p_dat:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_iob_int_sum_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t p_eop:1; uint64_t p_sop:1; uint64_t np_eop:1; uint64_t np_sop:1; +#else + uint64_t np_sop:1; + uint64_t np_eop:1; + uint64_t p_sop:1; + uint64_t p_eop:1; + uint64_t reserved_4_63:60; +#endif } cn30xx; struct cvmx_iob_int_sum_cn30xx cn31xx; struct cvmx_iob_int_sum_cn30xx cn38xx; @@ -365,16 +703,33 @@ union cvmx_iob_int_sum { struct cvmx_iob_int_sum_s cn56xxp1; struct cvmx_iob_int_sum_s cn58xx; struct cvmx_iob_int_sum_s cn58xxp1; + struct cvmx_iob_int_sum_s cn61xx; struct cvmx_iob_int_sum_s cn63xx; struct cvmx_iob_int_sum_s cn63xxp1; + struct cvmx_iob_int_sum_s cn66xx; + struct cvmx_iob_int_sum_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif + } cn68xx; + struct cvmx_iob_int_sum_cn68xx cn68xxp1; + struct cvmx_iob_int_sum_s cnf71xx; }; union cvmx_iob_n2c_l2c_pri_cnt { uint64_t u64; struct cvmx_iob_n2c_l2c_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; +#else + uint64_t cnt_val:15; + uint64_t cnt_enb:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xx; struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xxp2; @@ -384,16 +739,25 @@ union cvmx_iob_n2c_l2c_pri_cnt { struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1; struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx; struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1; + struct cvmx_iob_n2c_l2c_pri_cnt_s cn61xx; struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xx; struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xxp1; + struct cvmx_iob_n2c_l2c_pri_cnt_s cn66xx; + struct cvmx_iob_n2c_l2c_pri_cnt_s cnf71xx; }; union cvmx_iob_n2c_rsp_pri_cnt { uint64_t u64; struct cvmx_iob_n2c_rsp_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; +#else + uint64_t cnt_val:15; + uint64_t cnt_enb:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xx; struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xxp2; @@ -403,16 +767,25 @@ union cvmx_iob_n2c_rsp_pri_cnt { struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1; struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx; struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1; + struct cvmx_iob_n2c_rsp_pri_cnt_s cn61xx; struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xx; struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xxp1; + struct cvmx_iob_n2c_rsp_pri_cnt_s cn66xx; + struct cvmx_iob_n2c_rsp_pri_cnt_s cnf71xx; }; union cvmx_iob_outb_com_pri_cnt { uint64_t u64; struct cvmx_iob_outb_com_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; +#else + uint64_t cnt_val:15; + uint64_t cnt_enb:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_iob_outb_com_pri_cnt_s cn38xx; struct cvmx_iob_outb_com_pri_cnt_s cn38xxp2; @@ -422,18 +795,31 @@ union cvmx_iob_outb_com_pri_cnt { struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1; struct cvmx_iob_outb_com_pri_cnt_s cn58xx; struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1; + struct cvmx_iob_outb_com_pri_cnt_s cn61xx; struct cvmx_iob_outb_com_pri_cnt_s cn63xx; struct cvmx_iob_outb_com_pri_cnt_s cn63xxp1; + struct cvmx_iob_outb_com_pri_cnt_s cn66xx; + struct cvmx_iob_outb_com_pri_cnt_s cn68xx; + struct cvmx_iob_outb_com_pri_cnt_s cn68xxp1; + struct cvmx_iob_outb_com_pri_cnt_s cnf71xx; }; union cvmx_iob_outb_control_match { uint64_t u64; struct cvmx_iob_outb_control_match_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t mask:8; uint64_t eot:1; uint64_t dst:8; uint64_t src:9; +#else + uint64_t src:9; + uint64_t dst:8; + uint64_t eot:1; + uint64_t mask:8; + uint64_t reserved_26_63:38; +#endif } s; struct cvmx_iob_outb_control_match_s cn30xx; struct cvmx_iob_outb_control_match_s cn31xx; @@ -446,18 +832,31 @@ union cvmx_iob_outb_control_match { struct cvmx_iob_outb_control_match_s cn56xxp1; struct cvmx_iob_outb_control_match_s cn58xx; struct cvmx_iob_outb_control_match_s cn58xxp1; + struct cvmx_iob_outb_control_match_s cn61xx; struct cvmx_iob_outb_control_match_s cn63xx; struct cvmx_iob_outb_control_match_s cn63xxp1; + struct cvmx_iob_outb_control_match_s cn66xx; + struct cvmx_iob_outb_control_match_s cn68xx; + struct cvmx_iob_outb_control_match_s cn68xxp1; + struct cvmx_iob_outb_control_match_s cnf71xx; }; union cvmx_iob_outb_control_match_enb { uint64_t u64; struct cvmx_iob_outb_control_match_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t mask:8; uint64_t eot:1; uint64_t dst:8; uint64_t src:9; +#else + uint64_t src:9; + uint64_t dst:8; + uint64_t eot:1; + uint64_t mask:8; + uint64_t reserved_26_63:38; +#endif } s; struct cvmx_iob_outb_control_match_enb_s cn30xx; struct cvmx_iob_outb_control_match_enb_s cn31xx; @@ -470,14 +869,23 @@ union cvmx_iob_outb_control_match_enb { struct cvmx_iob_outb_control_match_enb_s cn56xxp1; struct cvmx_iob_outb_control_match_enb_s cn58xx; struct cvmx_iob_outb_control_match_enb_s cn58xxp1; + struct cvmx_iob_outb_control_match_enb_s cn61xx; struct cvmx_iob_outb_control_match_enb_s cn63xx; struct cvmx_iob_outb_control_match_enb_s cn63xxp1; + struct cvmx_iob_outb_control_match_enb_s cn66xx; + struct cvmx_iob_outb_control_match_enb_s cn68xx; + struct cvmx_iob_outb_control_match_enb_s cn68xxp1; + struct cvmx_iob_outb_control_match_enb_s cnf71xx; }; union cvmx_iob_outb_data_match { uint64_t u64; struct cvmx_iob_outb_data_match_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; +#else + uint64_t data:64; +#endif } s; struct cvmx_iob_outb_data_match_s cn30xx; struct cvmx_iob_outb_data_match_s cn31xx; @@ -490,14 +898,23 @@ union cvmx_iob_outb_data_match { struct cvmx_iob_outb_data_match_s cn56xxp1; struct cvmx_iob_outb_data_match_s cn58xx; struct cvmx_iob_outb_data_match_s cn58xxp1; + struct cvmx_iob_outb_data_match_s cn61xx; struct cvmx_iob_outb_data_match_s cn63xx; struct cvmx_iob_outb_data_match_s cn63xxp1; + struct cvmx_iob_outb_data_match_s cn66xx; + struct cvmx_iob_outb_data_match_s cn68xx; + struct cvmx_iob_outb_data_match_s cn68xxp1; + struct cvmx_iob_outb_data_match_s cnf71xx; }; union cvmx_iob_outb_data_match_enb { uint64_t u64; struct cvmx_iob_outb_data_match_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_iob_outb_data_match_enb_s cn30xx; struct cvmx_iob_outb_data_match_enb_s cn31xx; @@ -510,16 +927,27 @@ union cvmx_iob_outb_data_match_enb { struct cvmx_iob_outb_data_match_enb_s cn56xxp1; struct cvmx_iob_outb_data_match_enb_s cn58xx; struct cvmx_iob_outb_data_match_enb_s cn58xxp1; + struct cvmx_iob_outb_data_match_enb_s cn61xx; struct cvmx_iob_outb_data_match_enb_s cn63xx; struct cvmx_iob_outb_data_match_enb_s cn63xxp1; + struct cvmx_iob_outb_data_match_enb_s cn66xx; + struct cvmx_iob_outb_data_match_enb_s cn68xx; + struct cvmx_iob_outb_data_match_enb_s cn68xxp1; + struct cvmx_iob_outb_data_match_enb_s cnf71xx; }; union cvmx_iob_outb_fpa_pri_cnt { uint64_t u64; struct cvmx_iob_outb_fpa_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; +#else + uint64_t cnt_val:15; + uint64_t cnt_enb:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_iob_outb_fpa_pri_cnt_s cn38xx; struct cvmx_iob_outb_fpa_pri_cnt_s cn38xxp2; @@ -529,16 +957,27 @@ union cvmx_iob_outb_fpa_pri_cnt { struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1; struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx; struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1; + struct cvmx_iob_outb_fpa_pri_cnt_s cn61xx; struct cvmx_iob_outb_fpa_pri_cnt_s cn63xx; struct cvmx_iob_outb_fpa_pri_cnt_s cn63xxp1; + struct cvmx_iob_outb_fpa_pri_cnt_s cn66xx; + struct cvmx_iob_outb_fpa_pri_cnt_s cn68xx; + struct cvmx_iob_outb_fpa_pri_cnt_s cn68xxp1; + struct cvmx_iob_outb_fpa_pri_cnt_s cnf71xx; }; union cvmx_iob_outb_req_pri_cnt { uint64_t u64; struct cvmx_iob_outb_req_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; +#else + uint64_t cnt_val:15; + uint64_t cnt_enb:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_iob_outb_req_pri_cnt_s cn38xx; struct cvmx_iob_outb_req_pri_cnt_s cn38xxp2; @@ -548,16 +987,27 @@ union cvmx_iob_outb_req_pri_cnt { struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1; struct cvmx_iob_outb_req_pri_cnt_s cn58xx; struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1; + struct cvmx_iob_outb_req_pri_cnt_s cn61xx; struct cvmx_iob_outb_req_pri_cnt_s cn63xx; struct cvmx_iob_outb_req_pri_cnt_s cn63xxp1; + struct cvmx_iob_outb_req_pri_cnt_s cn66xx; + struct cvmx_iob_outb_req_pri_cnt_s cn68xx; + struct cvmx_iob_outb_req_pri_cnt_s cn68xxp1; + struct cvmx_iob_outb_req_pri_cnt_s cnf71xx; }; union cvmx_iob_p2c_req_pri_cnt { uint64_t u64; struct cvmx_iob_p2c_req_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t cnt_enb:1; uint64_t cnt_val:15; +#else + uint64_t cnt_val:15; + uint64_t cnt_enb:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_iob_p2c_req_pri_cnt_s cn38xx; struct cvmx_iob_p2c_req_pri_cnt_s cn38xxp2; @@ -567,20 +1017,34 @@ union cvmx_iob_p2c_req_pri_cnt { struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1; struct cvmx_iob_p2c_req_pri_cnt_s cn58xx; struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1; + struct cvmx_iob_p2c_req_pri_cnt_s cn61xx; struct cvmx_iob_p2c_req_pri_cnt_s cn63xx; struct cvmx_iob_p2c_req_pri_cnt_s cn63xxp1; + struct cvmx_iob_p2c_req_pri_cnt_s cn66xx; + struct cvmx_iob_p2c_req_pri_cnt_s cnf71xx; }; union cvmx_iob_pkt_err { uint64_t u64; struct cvmx_iob_pkt_err_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t vport:6; uint64_t port:6; +#else + uint64_t port:6; + uint64_t vport:6; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_iob_pkt_err_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t port:6; +#else + uint64_t port:6; + uint64_t reserved_6_63:58; +#endif } cn30xx; struct cvmx_iob_pkt_err_cn30xx cn31xx; struct cvmx_iob_pkt_err_cn30xx cn38xx; @@ -592,21 +1056,223 @@ union cvmx_iob_pkt_err { struct cvmx_iob_pkt_err_cn30xx cn56xxp1; struct cvmx_iob_pkt_err_cn30xx cn58xx; struct cvmx_iob_pkt_err_cn30xx cn58xxp1; + struct cvmx_iob_pkt_err_s cn61xx; struct cvmx_iob_pkt_err_s cn63xx; struct cvmx_iob_pkt_err_s cn63xxp1; + struct cvmx_iob_pkt_err_s cn66xx; + struct cvmx_iob_pkt_err_s cnf71xx; }; union cvmx_iob_to_cmb_credits { uint64_t u64; struct cvmx_iob_to_cmb_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_6_63:58; + uint64_t ncb_rd:3; + uint64_t ncb_wr:3; +#else + uint64_t ncb_wr:3; + uint64_t ncb_rd:3; + uint64_t reserved_6_63:58; +#endif + } s; + struct cvmx_iob_to_cmb_credits_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t pko_rd:3; uint64_t ncb_rd:3; uint64_t ncb_wr:3; +#else + uint64_t ncb_wr:3; + uint64_t ncb_rd:3; + uint64_t pko_rd:3; + uint64_t reserved_9_63:55; +#endif + } cn52xx; + struct cvmx_iob_to_cmb_credits_cn52xx cn61xx; + struct cvmx_iob_to_cmb_credits_cn52xx cn63xx; + struct cvmx_iob_to_cmb_credits_cn52xx cn63xxp1; + struct cvmx_iob_to_cmb_credits_cn52xx cn66xx; + struct cvmx_iob_to_cmb_credits_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_9_63:55; + uint64_t dwb:3; + uint64_t ncb_rd:3; + uint64_t ncb_wr:3; +#else + uint64_t ncb_wr:3; + uint64_t ncb_rd:3; + uint64_t dwb:3; + uint64_t reserved_9_63:55; +#endif + } cn68xx; + struct cvmx_iob_to_cmb_credits_cn68xx cn68xxp1; + struct cvmx_iob_to_cmb_credits_cn52xx cnf71xx; +}; + +union cvmx_iob_to_ncb_did_00_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_00_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_00_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_00_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_111_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_111_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_111_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_111_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_223_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_223_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_223_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_223_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_24_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_24_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_24_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_24_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_32_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_32_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_32_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_32_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_40_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_40_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_40_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_40_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_55_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_55_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_55_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_55_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_64_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_64_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_64_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_64_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_79_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_79_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_79_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_79_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_96_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_96_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_iob_to_ncb_did_96_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_96_credits_s cn68xxp1; +}; + +union cvmx_iob_to_ncb_did_98_credits { + uint64_t u64; + struct cvmx_iob_to_ncb_did_98_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t crd:7; +#else + uint64_t crd:7; + uint64_t reserved_7_63:57; +#endif } s; - struct cvmx_iob_to_cmb_credits_s cn52xx; - struct cvmx_iob_to_cmb_credits_s cn63xx; - struct cvmx_iob_to_cmb_credits_s cn63xxp1; + struct cvmx_iob_to_ncb_did_98_credits_s cn68xx; + struct cvmx_iob_to_ncb_did_98_credits_s cn68xxp1; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h index e0a5bfe88d0..1193f73bb74 100644 --- a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -32,23 +32,37 @@ #define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull)) #define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull)) #define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull)) +#define CVMX_IPD_BPIDX_MBUF_TH(offset) (CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8) +#define CVMX_IPD_BPID_BP_COUNTERX(offset) (CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8) #define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull)) #define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull)) +#define CVMX_IPD_CREDITS (CVMX_ADD_IO_SEG(0x00014F0000004410ull)) #define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull)) +#define CVMX_IPD_ECC_CTL (CVMX_ADD_IO_SEG(0x00014F0000004408ull)) +#define CVMX_IPD_FREE_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000780ull)) +#define CVMX_IPD_FREE_PTR_VALUE (CVMX_ADD_IO_SEG(0x00014F0000000788ull)) +#define CVMX_IPD_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000790ull)) #define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull)) #define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull)) +#define CVMX_IPD_NEXT_PKT_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A0ull)) +#define CVMX_IPD_NEXT_WQE_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A8ull)) #define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull)) +#define CVMX_IPD_ON_BP_DROP_PKTX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004100ull)) #define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull)) +#define CVMX_IPD_PKT_ERR (CVMX_ADD_IO_SEG(0x00014F00000003F0ull)) #define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull)) #define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8) #define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36) #define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40) #define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36) #define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40) +#define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44) #define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8) +#define CVMX_IPD_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000798ull)) #define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8) #define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8) #define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8) +#define CVMX_IPD_PORT_SOPX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004400ull)) #define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull)) #define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull)) #define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull)) @@ -63,6 +77,8 @@ #define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7) #define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8) #define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull)) +#define CVMX_IPD_RED_BPID_ENABLEX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004200ull)) +#define CVMX_IPD_RED_DELAY (CVMX_ADD_IO_SEG(0x00014F0000004300ull)) #define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull)) #define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull)) #define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0) @@ -74,6 +90,7 @@ #define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6) #define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7) #define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8) +#define CVMX_IPD_REQ_WGT (CVMX_ADD_IO_SEG(0x00014F0000004418ull)) #define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull)) #define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull)) #define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull)) @@ -83,8 +100,13 @@ union cvmx_ipd_1st_mbuff_skip { uint64_t u64; struct cvmx_ipd_1st_mbuff_skip_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t skip_sz:6; +#else + uint64_t skip_sz:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_ipd_1st_mbuff_skip_s cn30xx; struct cvmx_ipd_1st_mbuff_skip_s cn31xx; @@ -97,15 +119,25 @@ union cvmx_ipd_1st_mbuff_skip { struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1; struct cvmx_ipd_1st_mbuff_skip_s cn58xx; struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1; + struct cvmx_ipd_1st_mbuff_skip_s cn61xx; struct cvmx_ipd_1st_mbuff_skip_s cn63xx; struct cvmx_ipd_1st_mbuff_skip_s cn63xxp1; + struct cvmx_ipd_1st_mbuff_skip_s cn66xx; + struct cvmx_ipd_1st_mbuff_skip_s cn68xx; + struct cvmx_ipd_1st_mbuff_skip_s cn68xxp1; + struct cvmx_ipd_1st_mbuff_skip_s cnf71xx; }; union cvmx_ipd_1st_next_ptr_back { uint64_t u64; struct cvmx_ipd_1st_next_ptr_back_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t back:4; +#else + uint64_t back:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_ipd_1st_next_ptr_back_s cn30xx; struct cvmx_ipd_1st_next_ptr_back_s cn31xx; @@ -118,15 +150,25 @@ union cvmx_ipd_1st_next_ptr_back { struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1; struct cvmx_ipd_1st_next_ptr_back_s cn58xx; struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1; + struct cvmx_ipd_1st_next_ptr_back_s cn61xx; struct cvmx_ipd_1st_next_ptr_back_s cn63xx; struct cvmx_ipd_1st_next_ptr_back_s cn63xxp1; + struct cvmx_ipd_1st_next_ptr_back_s cn66xx; + struct cvmx_ipd_1st_next_ptr_back_s cn68xx; + struct cvmx_ipd_1st_next_ptr_back_s cn68xxp1; + struct cvmx_ipd_1st_next_ptr_back_s cnf71xx; }; union cvmx_ipd_2nd_next_ptr_back { uint64_t u64; struct cvmx_ipd_2nd_next_ptr_back_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t back:4; +#else + uint64_t back:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_ipd_2nd_next_ptr_back_s cn30xx; struct cvmx_ipd_2nd_next_ptr_back_s cn31xx; @@ -139,14 +181,25 @@ union cvmx_ipd_2nd_next_ptr_back { struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1; struct cvmx_ipd_2nd_next_ptr_back_s cn58xx; struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1; + struct cvmx_ipd_2nd_next_ptr_back_s cn61xx; struct cvmx_ipd_2nd_next_ptr_back_s cn63xx; struct cvmx_ipd_2nd_next_ptr_back_s cn63xxp1; + struct cvmx_ipd_2nd_next_ptr_back_s cn66xx; + struct cvmx_ipd_2nd_next_ptr_back_s cn68xx; + struct cvmx_ipd_2nd_next_ptr_back_s cn68xxp1; + struct cvmx_ipd_2nd_next_ptr_back_s cnf71xx; }; union cvmx_ipd_bist_status { uint64_t u64; struct cvmx_ipd_bist_status_s { - uint64_t reserved_18_63:46; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_23_63:41; + uint64_t iiwo1:1; + uint64_t iiwo0:1; + uint64_t iio1:1; + uint64_t iio0:1; + uint64_t pbm4:1; uint64_t csr_mem:1; uint64_t csr_ncmd:1; uint64_t pwq_wqed:1; @@ -165,8 +218,35 @@ union cvmx_ipd_bist_status { uint64_t ipd_old:1; uint64_t ipd_new:1; uint64_t pwp:1; +#else + uint64_t pwp:1; + uint64_t ipd_new:1; + uint64_t ipd_old:1; + uint64_t prc_off:1; + uint64_t pwq0:1; + uint64_t pwq1:1; + uint64_t pbm_word:1; + uint64_t pbm0:1; + uint64_t pbm1:1; + uint64_t pbm2:1; + uint64_t pbm3:1; + uint64_t ipq_pbe0:1; + uint64_t ipq_pbe1:1; + uint64_t pwq_pow:1; + uint64_t pwq_wp1:1; + uint64_t pwq_wqed:1; + uint64_t csr_ncmd:1; + uint64_t csr_mem:1; + uint64_t pbm4:1; + uint64_t iio0:1; + uint64_t iio1:1; + uint64_t iiwo0:1; + uint64_t iiwo1:1; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_ipd_bist_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t pwq_wqed:1; uint64_t pwq_wp1:1; @@ -184,52 +264,180 @@ union cvmx_ipd_bist_status { uint64_t ipd_old:1; uint64_t ipd_new:1; uint64_t pwp:1; +#else + uint64_t pwp:1; + uint64_t ipd_new:1; + uint64_t ipd_old:1; + uint64_t prc_off:1; + uint64_t pwq0:1; + uint64_t pwq1:1; + uint64_t pbm_word:1; + uint64_t pbm0:1; + uint64_t pbm1:1; + uint64_t pbm2:1; + uint64_t pbm3:1; + uint64_t ipq_pbe0:1; + uint64_t ipq_pbe1:1; + uint64_t pwq_pow:1; + uint64_t pwq_wp1:1; + uint64_t pwq_wqed:1; + uint64_t reserved_16_63:48; +#endif } cn30xx; struct cvmx_ipd_bist_status_cn30xx cn31xx; struct cvmx_ipd_bist_status_cn30xx cn38xx; struct cvmx_ipd_bist_status_cn30xx cn38xxp2; struct cvmx_ipd_bist_status_cn30xx cn50xx; - struct cvmx_ipd_bist_status_s cn52xx; - struct cvmx_ipd_bist_status_s cn52xxp1; - struct cvmx_ipd_bist_status_s cn56xx; - struct cvmx_ipd_bist_status_s cn56xxp1; + struct cvmx_ipd_bist_status_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_18_63:46; + uint64_t csr_mem:1; + uint64_t csr_ncmd:1; + uint64_t pwq_wqed:1; + uint64_t pwq_wp1:1; + uint64_t pwq_pow:1; + uint64_t ipq_pbe1:1; + uint64_t ipq_pbe0:1; + uint64_t pbm3:1; + uint64_t pbm2:1; + uint64_t pbm1:1; + uint64_t pbm0:1; + uint64_t pbm_word:1; + uint64_t pwq1:1; + uint64_t pwq0:1; + uint64_t prc_off:1; + uint64_t ipd_old:1; + uint64_t ipd_new:1; + uint64_t pwp:1; +#else + uint64_t pwp:1; + uint64_t ipd_new:1; + uint64_t ipd_old:1; + uint64_t prc_off:1; + uint64_t pwq0:1; + uint64_t pwq1:1; + uint64_t pbm_word:1; + uint64_t pbm0:1; + uint64_t pbm1:1; + uint64_t pbm2:1; + uint64_t pbm3:1; + uint64_t ipq_pbe0:1; + uint64_t ipq_pbe1:1; + uint64_t pwq_pow:1; + uint64_t pwq_wp1:1; + uint64_t pwq_wqed:1; + uint64_t csr_ncmd:1; + uint64_t csr_mem:1; + uint64_t reserved_18_63:46; +#endif + } cn52xx; + struct cvmx_ipd_bist_status_cn52xx cn52xxp1; + struct cvmx_ipd_bist_status_cn52xx cn56xx; + struct cvmx_ipd_bist_status_cn52xx cn56xxp1; struct cvmx_ipd_bist_status_cn30xx cn58xx; struct cvmx_ipd_bist_status_cn30xx cn58xxp1; - struct cvmx_ipd_bist_status_s cn63xx; - struct cvmx_ipd_bist_status_s cn63xxp1; + struct cvmx_ipd_bist_status_cn52xx cn61xx; + struct cvmx_ipd_bist_status_cn52xx cn63xx; + struct cvmx_ipd_bist_status_cn52xx cn63xxp1; + struct cvmx_ipd_bist_status_cn52xx cn66xx; + struct cvmx_ipd_bist_status_s cn68xx; + struct cvmx_ipd_bist_status_s cn68xxp1; + struct cvmx_ipd_bist_status_cn52xx cnf71xx; }; union cvmx_ipd_bp_prt_red_end { uint64_t u64; struct cvmx_ipd_bp_prt_red_end_s { - uint64_t reserved_44_63:20; - uint64_t prt_enb:44; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t prt_enb:48; +#else + uint64_t prt_enb:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_ipd_bp_prt_red_end_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t prt_enb:36; +#else + uint64_t prt_enb:36; + uint64_t reserved_36_63:28; +#endif } cn30xx; struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx; struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx; struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2; struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx; struct cvmx_ipd_bp_prt_red_end_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t prt_enb:40; +#else + uint64_t prt_enb:40; + uint64_t reserved_40_63:24; +#endif } cn52xx; struct cvmx_ipd_bp_prt_red_end_cn52xx cn52xxp1; struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xx; struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xxp1; struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx; struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1; - struct cvmx_ipd_bp_prt_red_end_s cn63xx; - struct cvmx_ipd_bp_prt_red_end_s cn63xxp1; + struct cvmx_ipd_bp_prt_red_end_s cn61xx; + struct cvmx_ipd_bp_prt_red_end_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_44_63:20; + uint64_t prt_enb:44; +#else + uint64_t prt_enb:44; + uint64_t reserved_44_63:20; +#endif + } cn63xx; + struct cvmx_ipd_bp_prt_red_end_cn63xx cn63xxp1; + struct cvmx_ipd_bp_prt_red_end_s cn66xx; + struct cvmx_ipd_bp_prt_red_end_s cnf71xx; +}; + +union cvmx_ipd_bpidx_mbuf_th { + uint64_t u64; + struct cvmx_ipd_bpidx_mbuf_th_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_18_63:46; + uint64_t bp_enb:1; + uint64_t page_cnt:17; +#else + uint64_t page_cnt:17; + uint64_t bp_enb:1; + uint64_t reserved_18_63:46; +#endif + } s; + struct cvmx_ipd_bpidx_mbuf_th_s cn68xx; + struct cvmx_ipd_bpidx_mbuf_th_s cn68xxp1; +}; + +union cvmx_ipd_bpid_bp_counterx { + uint64_t u64; + struct cvmx_ipd_bpid_bp_counterx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t cnt_val:25; +#else + uint64_t cnt_val:25; + uint64_t reserved_25_63:39; +#endif + } s; + struct cvmx_ipd_bpid_bp_counterx_s cn68xx; + struct cvmx_ipd_bpid_bp_counterx_s cn68xxp1; }; union cvmx_ipd_clk_count { uint64_t u64; struct cvmx_ipd_clk_count_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t clk_cnt:64; +#else + uint64_t clk_cnt:64; +#endif } s; struct cvmx_ipd_clk_count_s cn30xx; struct cvmx_ipd_clk_count_s cn31xx; @@ -242,13 +450,36 @@ union cvmx_ipd_clk_count { struct cvmx_ipd_clk_count_s cn56xxp1; struct cvmx_ipd_clk_count_s cn58xx; struct cvmx_ipd_clk_count_s cn58xxp1; + struct cvmx_ipd_clk_count_s cn61xx; struct cvmx_ipd_clk_count_s cn63xx; struct cvmx_ipd_clk_count_s cn63xxp1; + struct cvmx_ipd_clk_count_s cn66xx; + struct cvmx_ipd_clk_count_s cn68xx; + struct cvmx_ipd_clk_count_s cn68xxp1; + struct cvmx_ipd_clk_count_s cnf71xx; +}; + +union cvmx_ipd_credits { + uint64_t u64; + struct cvmx_ipd_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t iob_wrc:8; + uint64_t iob_wr:8; +#else + uint64_t iob_wr:8; + uint64_t iob_wrc:8; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_ipd_credits_s cn68xx; + struct cvmx_ipd_credits_s cn68xxp1; }; union cvmx_ipd_ctl_status { uint64_t u64; struct cvmx_ipd_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t use_sop:1; uint64_t rst_done:1; @@ -267,8 +498,29 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t len_m8:1; + uint64_t pkt_off:1; + uint64_t ipd_full:1; + uint64_t pq_nabuf:1; + uint64_t pq_apkt:1; + uint64_t no_wptr:1; + uint64_t clken:1; + uint64_t rst_done:1; + uint64_t use_sop:1; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_ipd_ctl_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t len_m8:1; uint64_t reset:1; @@ -279,10 +531,23 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t len_m8:1; + uint64_t reserved_10_63:54; +#endif } cn30xx; struct cvmx_ipd_ctl_status_cn30xx cn31xx; struct cvmx_ipd_ctl_status_cn30xx cn38xx; struct cvmx_ipd_ctl_status_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t reset:1; uint64_t addpkt:1; @@ -292,8 +557,20 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t reserved_9_63:55; +#endif } cn38xxp2; struct cvmx_ipd_ctl_status_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t no_wptr:1; uint64_t pq_apkt:1; @@ -309,12 +586,30 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t len_m8:1; + uint64_t pkt_off:1; + uint64_t ipd_full:1; + uint64_t pq_nabuf:1; + uint64_t pq_apkt:1; + uint64_t no_wptr:1; + uint64_t reserved_15_63:49; +#endif } cn50xx; struct cvmx_ipd_ctl_status_cn50xx cn52xx; struct cvmx_ipd_ctl_status_cn50xx cn52xxp1; struct cvmx_ipd_ctl_status_cn50xx cn56xx; struct cvmx_ipd_ctl_status_cn50xx cn56xxp1; struct cvmx_ipd_ctl_status_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t ipd_full:1; uint64_t pkt_off:1; @@ -327,10 +622,26 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t len_m8:1; + uint64_t pkt_off:1; + uint64_t ipd_full:1; + uint64_t reserved_12_63:52; +#endif } cn58xx; struct cvmx_ipd_ctl_status_cn58xx cn58xxp1; + struct cvmx_ipd_ctl_status_s cn61xx; struct cvmx_ipd_ctl_status_s cn63xx; struct cvmx_ipd_ctl_status_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t clken:1; uint64_t no_wptr:1; @@ -347,13 +658,129 @@ union cvmx_ipd_ctl_status { uint64_t pbp_en:1; uint64_t opc_mode:2; uint64_t ipd_en:1; +#else + uint64_t ipd_en:1; + uint64_t opc_mode:2; + uint64_t pbp_en:1; + uint64_t wqe_lend:1; + uint64_t pkt_lend:1; + uint64_t naddbuf:1; + uint64_t addpkt:1; + uint64_t reset:1; + uint64_t len_m8:1; + uint64_t pkt_off:1; + uint64_t ipd_full:1; + uint64_t pq_nabuf:1; + uint64_t pq_apkt:1; + uint64_t no_wptr:1; + uint64_t clken:1; + uint64_t reserved_16_63:48; +#endif } cn63xxp1; + struct cvmx_ipd_ctl_status_s cn66xx; + struct cvmx_ipd_ctl_status_s cn68xx; + struct cvmx_ipd_ctl_status_s cn68xxp1; + struct cvmx_ipd_ctl_status_s cnf71xx; +}; + +union cvmx_ipd_ecc_ctl { + uint64_t u64; + struct cvmx_ipd_ecc_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_8_63:56; + uint64_t pm3_syn:2; + uint64_t pm2_syn:2; + uint64_t pm1_syn:2; + uint64_t pm0_syn:2; +#else + uint64_t pm0_syn:2; + uint64_t pm1_syn:2; + uint64_t pm2_syn:2; + uint64_t pm3_syn:2; + uint64_t reserved_8_63:56; +#endif + } s; + struct cvmx_ipd_ecc_ctl_s cn68xx; + struct cvmx_ipd_ecc_ctl_s cn68xxp1; +}; + +union cvmx_ipd_free_ptr_fifo_ctl { + uint64_t u64; + struct cvmx_ipd_free_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t max_cnts:7; + uint64_t wraddr:8; + uint64_t praddr:8; + uint64_t cena:1; + uint64_t raddr:8; +#else + uint64_t raddr:8; + uint64_t cena:1; + uint64_t praddr:8; + uint64_t wraddr:8; + uint64_t max_cnts:7; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_ipd_free_ptr_fifo_ctl_s cn68xx; + struct cvmx_ipd_free_ptr_fifo_ctl_s cn68xxp1; +}; + +union cvmx_ipd_free_ptr_value { + uint64_t u64; + struct cvmx_ipd_free_ptr_value_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t ptr:33; +#else + uint64_t ptr:33; + uint64_t reserved_33_63:31; +#endif + } s; + struct cvmx_ipd_free_ptr_value_s cn68xx; + struct cvmx_ipd_free_ptr_value_s cn68xxp1; +}; + +union cvmx_ipd_hold_ptr_fifo_ctl { + uint64_t u64; + struct cvmx_ipd_hold_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_43_63:21; + uint64_t ptr:33; + uint64_t max_pkt:3; + uint64_t praddr:3; + uint64_t cena:1; + uint64_t raddr:3; +#else + uint64_t raddr:3; + uint64_t cena:1; + uint64_t praddr:3; + uint64_t max_pkt:3; + uint64_t ptr:33; + uint64_t reserved_43_63:21; +#endif + } s; + struct cvmx_ipd_hold_ptr_fifo_ctl_s cn68xx; + struct cvmx_ipd_hold_ptr_fifo_ctl_s cn68xxp1; }; union cvmx_ipd_int_enb { uint64_t u64; struct cvmx_ipd_int_enb_s { - uint64_t reserved_12_63:52; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_23_63:41; + uint64_t pw3_dbe:1; + uint64_t pw3_sbe:1; + uint64_t pw2_dbe:1; + uint64_t pw2_sbe:1; + uint64_t pw1_dbe:1; + uint64_t pw1_sbe:1; + uint64_t pw0_dbe:1; + uint64_t pw0_sbe:1; + uint64_t dat:1; + uint64_t eop:1; + uint64_t sop:1; uint64_t pq_sub:1; uint64_t pq_add:1; uint64_t bc_ovr:1; @@ -366,17 +793,53 @@ union cvmx_ipd_int_enb { uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t pq_add:1; + uint64_t pq_sub:1; + uint64_t sop:1; + uint64_t eop:1; + uint64_t dat:1; + uint64_t pw0_sbe:1; + uint64_t pw0_dbe:1; + uint64_t pw1_sbe:1; + uint64_t pw1_dbe:1; + uint64_t pw2_sbe:1; + uint64_t pw2_dbe:1; + uint64_t pw3_sbe:1; + uint64_t pw3_dbe:1; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_ipd_int_enb_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t bp_sub:1; uint64_t prc_par3:1; uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t reserved_5_63:59; +#endif } cn30xx; struct cvmx_ipd_int_enb_cn30xx cn31xx; struct cvmx_ipd_int_enb_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t bc_ovr:1; uint64_t d_coll:1; @@ -388,23 +851,83 @@ union cvmx_ipd_int_enb { uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t reserved_10_63:54; +#endif } cn38xx; struct cvmx_ipd_int_enb_cn30xx cn38xxp2; struct cvmx_ipd_int_enb_cn38xx cn50xx; - struct cvmx_ipd_int_enb_s cn52xx; - struct cvmx_ipd_int_enb_s cn52xxp1; - struct cvmx_ipd_int_enb_s cn56xx; - struct cvmx_ipd_int_enb_s cn56xxp1; + struct cvmx_ipd_int_enb_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t pq_sub:1; + uint64_t pq_add:1; + uint64_t bc_ovr:1; + uint64_t d_coll:1; + uint64_t c_coll:1; + uint64_t cc_ovr:1; + uint64_t dc_ovr:1; + uint64_t bp_sub:1; + uint64_t prc_par3:1; + uint64_t prc_par2:1; + uint64_t prc_par1:1; + uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t pq_add:1; + uint64_t pq_sub:1; + uint64_t reserved_12_63:52; +#endif + } cn52xx; + struct cvmx_ipd_int_enb_cn52xx cn52xxp1; + struct cvmx_ipd_int_enb_cn52xx cn56xx; + struct cvmx_ipd_int_enb_cn52xx cn56xxp1; struct cvmx_ipd_int_enb_cn38xx cn58xx; struct cvmx_ipd_int_enb_cn38xx cn58xxp1; - struct cvmx_ipd_int_enb_s cn63xx; - struct cvmx_ipd_int_enb_s cn63xxp1; + struct cvmx_ipd_int_enb_cn52xx cn61xx; + struct cvmx_ipd_int_enb_cn52xx cn63xx; + struct cvmx_ipd_int_enb_cn52xx cn63xxp1; + struct cvmx_ipd_int_enb_cn52xx cn66xx; + struct cvmx_ipd_int_enb_s cn68xx; + struct cvmx_ipd_int_enb_s cn68xxp1; + struct cvmx_ipd_int_enb_cn52xx cnf71xx; }; union cvmx_ipd_int_sum { uint64_t u64; struct cvmx_ipd_int_sum_s { - uint64_t reserved_12_63:52; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_23_63:41; + uint64_t pw3_dbe:1; + uint64_t pw3_sbe:1; + uint64_t pw2_dbe:1; + uint64_t pw2_sbe:1; + uint64_t pw1_dbe:1; + uint64_t pw1_sbe:1; + uint64_t pw0_dbe:1; + uint64_t pw0_sbe:1; + uint64_t dat:1; + uint64_t eop:1; + uint64_t sop:1; uint64_t pq_sub:1; uint64_t pq_add:1; uint64_t bc_ovr:1; @@ -417,17 +940,53 @@ union cvmx_ipd_int_sum { uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t pq_add:1; + uint64_t pq_sub:1; + uint64_t sop:1; + uint64_t eop:1; + uint64_t dat:1; + uint64_t pw0_sbe:1; + uint64_t pw0_dbe:1; + uint64_t pw1_sbe:1; + uint64_t pw1_dbe:1; + uint64_t pw2_sbe:1; + uint64_t pw2_dbe:1; + uint64_t pw3_sbe:1; + uint64_t pw3_dbe:1; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_ipd_int_sum_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t bp_sub:1; uint64_t prc_par3:1; uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t reserved_5_63:59; +#endif } cn30xx; struct cvmx_ipd_int_sum_cn30xx cn31xx; struct cvmx_ipd_int_sum_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t bc_ovr:1; uint64_t d_coll:1; @@ -439,24 +998,107 @@ union cvmx_ipd_int_sum { uint64_t prc_par2:1; uint64_t prc_par1:1; uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t reserved_10_63:54; +#endif } cn38xx; struct cvmx_ipd_int_sum_cn30xx cn38xxp2; struct cvmx_ipd_int_sum_cn38xx cn50xx; - struct cvmx_ipd_int_sum_s cn52xx; - struct cvmx_ipd_int_sum_s cn52xxp1; - struct cvmx_ipd_int_sum_s cn56xx; - struct cvmx_ipd_int_sum_s cn56xxp1; + struct cvmx_ipd_int_sum_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t pq_sub:1; + uint64_t pq_add:1; + uint64_t bc_ovr:1; + uint64_t d_coll:1; + uint64_t c_coll:1; + uint64_t cc_ovr:1; + uint64_t dc_ovr:1; + uint64_t bp_sub:1; + uint64_t prc_par3:1; + uint64_t prc_par2:1; + uint64_t prc_par1:1; + uint64_t prc_par0:1; +#else + uint64_t prc_par0:1; + uint64_t prc_par1:1; + uint64_t prc_par2:1; + uint64_t prc_par3:1; + uint64_t bp_sub:1; + uint64_t dc_ovr:1; + uint64_t cc_ovr:1; + uint64_t c_coll:1; + uint64_t d_coll:1; + uint64_t bc_ovr:1; + uint64_t pq_add:1; + uint64_t pq_sub:1; + uint64_t reserved_12_63:52; +#endif + } cn52xx; + struct cvmx_ipd_int_sum_cn52xx cn52xxp1; + struct cvmx_ipd_int_sum_cn52xx cn56xx; + struct cvmx_ipd_int_sum_cn52xx cn56xxp1; struct cvmx_ipd_int_sum_cn38xx cn58xx; struct cvmx_ipd_int_sum_cn38xx cn58xxp1; - struct cvmx_ipd_int_sum_s cn63xx; - struct cvmx_ipd_int_sum_s cn63xxp1; + struct cvmx_ipd_int_sum_cn52xx cn61xx; + struct cvmx_ipd_int_sum_cn52xx cn63xx; + struct cvmx_ipd_int_sum_cn52xx cn63xxp1; + struct cvmx_ipd_int_sum_cn52xx cn66xx; + struct cvmx_ipd_int_sum_s cn68xx; + struct cvmx_ipd_int_sum_s cn68xxp1; + struct cvmx_ipd_int_sum_cn52xx cnf71xx; +}; + +union cvmx_ipd_next_pkt_ptr { + uint64_t u64; + struct cvmx_ipd_next_pkt_ptr_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t ptr:33; +#else + uint64_t ptr:33; + uint64_t reserved_33_63:31; +#endif + } s; + struct cvmx_ipd_next_pkt_ptr_s cn68xx; + struct cvmx_ipd_next_pkt_ptr_s cn68xxp1; +}; + +union cvmx_ipd_next_wqe_ptr { + uint64_t u64; + struct cvmx_ipd_next_wqe_ptr_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t ptr:33; +#else + uint64_t ptr:33; + uint64_t reserved_33_63:31; +#endif + } s; + struct cvmx_ipd_next_wqe_ptr_s cn68xx; + struct cvmx_ipd_next_wqe_ptr_s cn68xxp1; }; union cvmx_ipd_not_1st_mbuff_skip { uint64_t u64; struct cvmx_ipd_not_1st_mbuff_skip_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t skip_sz:6; +#else + uint64_t skip_sz:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_ipd_not_1st_mbuff_skip_s cn30xx; struct cvmx_ipd_not_1st_mbuff_skip_s cn31xx; @@ -469,15 +1111,38 @@ union cvmx_ipd_not_1st_mbuff_skip { struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1; struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx; struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1; + struct cvmx_ipd_not_1st_mbuff_skip_s cn61xx; struct cvmx_ipd_not_1st_mbuff_skip_s cn63xx; struct cvmx_ipd_not_1st_mbuff_skip_s cn63xxp1; + struct cvmx_ipd_not_1st_mbuff_skip_s cn66xx; + struct cvmx_ipd_not_1st_mbuff_skip_s cn68xx; + struct cvmx_ipd_not_1st_mbuff_skip_s cn68xxp1; + struct cvmx_ipd_not_1st_mbuff_skip_s cnf71xx; +}; + +union cvmx_ipd_on_bp_drop_pktx { + uint64_t u64; + struct cvmx_ipd_on_bp_drop_pktx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t prt_enb:64; +#else + uint64_t prt_enb:64; +#endif + } s; + struct cvmx_ipd_on_bp_drop_pktx_s cn68xx; + struct cvmx_ipd_on_bp_drop_pktx_s cn68xxp1; }; union cvmx_ipd_packet_mbuff_size { uint64_t u64; struct cvmx_ipd_packet_mbuff_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t mb_size:12; +#else + uint64_t mb_size:12; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_ipd_packet_mbuff_size_s cn30xx; struct cvmx_ipd_packet_mbuff_size_s cn31xx; @@ -490,15 +1155,40 @@ union cvmx_ipd_packet_mbuff_size { struct cvmx_ipd_packet_mbuff_size_s cn56xxp1; struct cvmx_ipd_packet_mbuff_size_s cn58xx; struct cvmx_ipd_packet_mbuff_size_s cn58xxp1; + struct cvmx_ipd_packet_mbuff_size_s cn61xx; struct cvmx_ipd_packet_mbuff_size_s cn63xx; struct cvmx_ipd_packet_mbuff_size_s cn63xxp1; + struct cvmx_ipd_packet_mbuff_size_s cn66xx; + struct cvmx_ipd_packet_mbuff_size_s cn68xx; + struct cvmx_ipd_packet_mbuff_size_s cn68xxp1; + struct cvmx_ipd_packet_mbuff_size_s cnf71xx; +}; + +union cvmx_ipd_pkt_err { + uint64_t u64; + struct cvmx_ipd_pkt_err_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_6_63:58; + uint64_t reasm:6; +#else + uint64_t reasm:6; + uint64_t reserved_6_63:58; +#endif + } s; + struct cvmx_ipd_pkt_err_s cn68xx; + struct cvmx_ipd_pkt_err_s cn68xxp1; }; union cvmx_ipd_pkt_ptr_valid { uint64_t u64; struct cvmx_ipd_pkt_ptr_valid_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t ptr:29; +#else + uint64_t ptr:29; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_ipd_pkt_ptr_valid_s cn30xx; struct cvmx_ipd_pkt_ptr_valid_s cn31xx; @@ -510,16 +1200,25 @@ union cvmx_ipd_pkt_ptr_valid { struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1; struct cvmx_ipd_pkt_ptr_valid_s cn58xx; struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1; + struct cvmx_ipd_pkt_ptr_valid_s cn61xx; struct cvmx_ipd_pkt_ptr_valid_s cn63xx; struct cvmx_ipd_pkt_ptr_valid_s cn63xxp1; + struct cvmx_ipd_pkt_ptr_valid_s cn66xx; + struct cvmx_ipd_pkt_ptr_valid_s cnf71xx; }; union cvmx_ipd_portx_bp_page_cnt { uint64_t u64; struct cvmx_ipd_portx_bp_page_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t bp_enb:1; uint64_t page_cnt:17; +#else + uint64_t page_cnt:17; + uint64_t bp_enb:1; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_ipd_portx_bp_page_cnt_s cn30xx; struct cvmx_ipd_portx_bp_page_cnt_s cn31xx; @@ -532,65 +1231,123 @@ union cvmx_ipd_portx_bp_page_cnt { struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1; struct cvmx_ipd_portx_bp_page_cnt_s cn58xx; struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1; + struct cvmx_ipd_portx_bp_page_cnt_s cn61xx; struct cvmx_ipd_portx_bp_page_cnt_s cn63xx; struct cvmx_ipd_portx_bp_page_cnt_s cn63xxp1; + struct cvmx_ipd_portx_bp_page_cnt_s cn66xx; + struct cvmx_ipd_portx_bp_page_cnt_s cnf71xx; }; union cvmx_ipd_portx_bp_page_cnt2 { uint64_t u64; struct cvmx_ipd_portx_bp_page_cnt2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t bp_enb:1; uint64_t page_cnt:17; +#else + uint64_t page_cnt:17; + uint64_t bp_enb:1; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_ipd_portx_bp_page_cnt2_s cn52xx; struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1; struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx; struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1; + struct cvmx_ipd_portx_bp_page_cnt2_s cn61xx; struct cvmx_ipd_portx_bp_page_cnt2_s cn63xx; struct cvmx_ipd_portx_bp_page_cnt2_s cn63xxp1; + struct cvmx_ipd_portx_bp_page_cnt2_s cn66xx; + struct cvmx_ipd_portx_bp_page_cnt2_s cnf71xx; }; union cvmx_ipd_portx_bp_page_cnt3 { uint64_t u64; struct cvmx_ipd_portx_bp_page_cnt3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t bp_enb:1; uint64_t page_cnt:17; +#else + uint64_t page_cnt:17; + uint64_t bp_enb:1; + uint64_t reserved_18_63:46; +#endif } s; + struct cvmx_ipd_portx_bp_page_cnt3_s cn61xx; struct cvmx_ipd_portx_bp_page_cnt3_s cn63xx; struct cvmx_ipd_portx_bp_page_cnt3_s cn63xxp1; + struct cvmx_ipd_portx_bp_page_cnt3_s cn66xx; + struct cvmx_ipd_portx_bp_page_cnt3_s cnf71xx; }; union cvmx_ipd_port_bp_counters2_pairx { uint64_t u64; struct cvmx_ipd_port_bp_counters2_pairx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t cnt_val:25; +#else + uint64_t cnt_val:25; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx; struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1; struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx; struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1; + struct cvmx_ipd_port_bp_counters2_pairx_s cn61xx; struct cvmx_ipd_port_bp_counters2_pairx_s cn63xx; struct cvmx_ipd_port_bp_counters2_pairx_s cn63xxp1; + struct cvmx_ipd_port_bp_counters2_pairx_s cn66xx; + struct cvmx_ipd_port_bp_counters2_pairx_s cnf71xx; }; union cvmx_ipd_port_bp_counters3_pairx { uint64_t u64; struct cvmx_ipd_port_bp_counters3_pairx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t cnt_val:25; +#else + uint64_t cnt_val:25; + uint64_t reserved_25_63:39; +#endif } s; + struct cvmx_ipd_port_bp_counters3_pairx_s cn61xx; struct cvmx_ipd_port_bp_counters3_pairx_s cn63xx; struct cvmx_ipd_port_bp_counters3_pairx_s cn63xxp1; + struct cvmx_ipd_port_bp_counters3_pairx_s cn66xx; + struct cvmx_ipd_port_bp_counters3_pairx_s cnf71xx; +}; + +union cvmx_ipd_port_bp_counters4_pairx { + uint64_t u64; + struct cvmx_ipd_port_bp_counters4_pairx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t cnt_val:25; +#else + uint64_t cnt_val:25; + uint64_t reserved_25_63:39; +#endif + } s; + struct cvmx_ipd_port_bp_counters4_pairx_s cn61xx; + struct cvmx_ipd_port_bp_counters4_pairx_s cn66xx; + struct cvmx_ipd_port_bp_counters4_pairx_s cnf71xx; }; union cvmx_ipd_port_bp_counters_pairx { uint64_t u64; struct cvmx_ipd_port_bp_counters_pairx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t cnt_val:25; +#else + uint64_t cnt_val:25; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_ipd_port_bp_counters_pairx_s cn30xx; struct cvmx_ipd_port_bp_counters_pairx_s cn31xx; @@ -603,59 +1360,133 @@ union cvmx_ipd_port_bp_counters_pairx { struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1; struct cvmx_ipd_port_bp_counters_pairx_s cn58xx; struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1; + struct cvmx_ipd_port_bp_counters_pairx_s cn61xx; struct cvmx_ipd_port_bp_counters_pairx_s cn63xx; struct cvmx_ipd_port_bp_counters_pairx_s cn63xxp1; + struct cvmx_ipd_port_bp_counters_pairx_s cn66xx; + struct cvmx_ipd_port_bp_counters_pairx_s cnf71xx; +}; + +union cvmx_ipd_port_ptr_fifo_ctl { + uint64_t u64; + struct cvmx_ipd_port_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t ptr:33; + uint64_t max_pkt:7; + uint64_t cena:1; + uint64_t raddr:7; +#else + uint64_t raddr:7; + uint64_t cena:1; + uint64_t max_pkt:7; + uint64_t ptr:33; + uint64_t reserved_48_63:16; +#endif + } s; + struct cvmx_ipd_port_ptr_fifo_ctl_s cn68xx; + struct cvmx_ipd_port_ptr_fifo_ctl_s cn68xxp1; }; union cvmx_ipd_port_qos_x_cnt { uint64_t u64; struct cvmx_ipd_port_qos_x_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wmark:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t wmark:32; +#endif } s; struct cvmx_ipd_port_qos_x_cnt_s cn52xx; struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1; struct cvmx_ipd_port_qos_x_cnt_s cn56xx; struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1; + struct cvmx_ipd_port_qos_x_cnt_s cn61xx; struct cvmx_ipd_port_qos_x_cnt_s cn63xx; struct cvmx_ipd_port_qos_x_cnt_s cn63xxp1; + struct cvmx_ipd_port_qos_x_cnt_s cn66xx; + struct cvmx_ipd_port_qos_x_cnt_s cn68xx; + struct cvmx_ipd_port_qos_x_cnt_s cn68xxp1; + struct cvmx_ipd_port_qos_x_cnt_s cnf71xx; }; union cvmx_ipd_port_qos_intx { uint64_t u64; struct cvmx_ipd_port_qos_intx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t intr:64; +#else uint64_t intr:64; +#endif } s; struct cvmx_ipd_port_qos_intx_s cn52xx; struct cvmx_ipd_port_qos_intx_s cn52xxp1; struct cvmx_ipd_port_qos_intx_s cn56xx; struct cvmx_ipd_port_qos_intx_s cn56xxp1; + struct cvmx_ipd_port_qos_intx_s cn61xx; struct cvmx_ipd_port_qos_intx_s cn63xx; struct cvmx_ipd_port_qos_intx_s cn63xxp1; + struct cvmx_ipd_port_qos_intx_s cn66xx; + struct cvmx_ipd_port_qos_intx_s cn68xx; + struct cvmx_ipd_port_qos_intx_s cn68xxp1; + struct cvmx_ipd_port_qos_intx_s cnf71xx; }; union cvmx_ipd_port_qos_int_enbx { uint64_t u64; struct cvmx_ipd_port_qos_int_enbx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t enb:64; +#else uint64_t enb:64; +#endif } s; struct cvmx_ipd_port_qos_int_enbx_s cn52xx; struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1; struct cvmx_ipd_port_qos_int_enbx_s cn56xx; struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1; + struct cvmx_ipd_port_qos_int_enbx_s cn61xx; struct cvmx_ipd_port_qos_int_enbx_s cn63xx; struct cvmx_ipd_port_qos_int_enbx_s cn63xxp1; + struct cvmx_ipd_port_qos_int_enbx_s cn66xx; + struct cvmx_ipd_port_qos_int_enbx_s cn68xx; + struct cvmx_ipd_port_qos_int_enbx_s cn68xxp1; + struct cvmx_ipd_port_qos_int_enbx_s cnf71xx; +}; + +union cvmx_ipd_port_sopx { + uint64_t u64; + struct cvmx_ipd_port_sopx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t sop:64; +#else + uint64_t sop:64; +#endif + } s; + struct cvmx_ipd_port_sopx_s cn68xx; + struct cvmx_ipd_port_sopx_s cn68xxp1; }; union cvmx_ipd_prc_hold_ptr_fifo_ctl { uint64_t u64; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t max_pkt:3; uint64_t praddr:3; uint64_t ptr:29; uint64_t cena:1; uint64_t raddr:3; +#else + uint64_t raddr:3; + uint64_t cena:1; + uint64_t ptr:29; + uint64_t praddr:3; + uint64_t max_pkt:3; + uint64_t reserved_39_63:25; +#endif } s; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx; @@ -667,18 +1498,29 @@ union cvmx_ipd_prc_hold_ptr_fifo_ctl { struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1; + struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn61xx; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xx; struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xxp1; + struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn66xx; + struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cnf71xx; }; union cvmx_ipd_prc_port_ptr_fifo_ctl { uint64_t u64; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t max_pkt:7; uint64_t ptr:29; uint64_t cena:1; uint64_t raddr:7; +#else + uint64_t raddr:7; + uint64_t cena:1; + uint64_t ptr:29; + uint64_t max_pkt:7; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx; @@ -690,19 +1532,31 @@ union cvmx_ipd_prc_port_ptr_fifo_ctl { struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1; + struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn61xx; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xx; struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xxp1; + struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn66xx; + struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cnf71xx; }; union cvmx_ipd_ptr_count { uint64_t u64; struct cvmx_ipd_ptr_count_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t pktv_cnt:1; uint64_t wqev_cnt:1; uint64_t pfif_cnt:3; uint64_t pkt_pcnt:7; uint64_t wqe_pcnt:7; +#else + uint64_t wqe_pcnt:7; + uint64_t pkt_pcnt:7; + uint64_t pfif_cnt:3; + uint64_t wqev_cnt:1; + uint64_t pktv_cnt:1; + uint64_t reserved_19_63:45; +#endif } s; struct cvmx_ipd_ptr_count_s cn30xx; struct cvmx_ipd_ptr_count_s cn31xx; @@ -715,13 +1569,19 @@ union cvmx_ipd_ptr_count { struct cvmx_ipd_ptr_count_s cn56xxp1; struct cvmx_ipd_ptr_count_s cn58xx; struct cvmx_ipd_ptr_count_s cn58xxp1; + struct cvmx_ipd_ptr_count_s cn61xx; struct cvmx_ipd_ptr_count_s cn63xx; struct cvmx_ipd_ptr_count_s cn63xxp1; + struct cvmx_ipd_ptr_count_s cn66xx; + struct cvmx_ipd_ptr_count_s cn68xx; + struct cvmx_ipd_ptr_count_s cn68xxp1; + struct cvmx_ipd_ptr_count_s cnf71xx; }; union cvmx_ipd_pwp_ptr_fifo_ctl { uint64_t u64; struct cvmx_ipd_pwp_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t max_cnts:7; uint64_t wraddr:8; @@ -729,6 +1589,15 @@ union cvmx_ipd_pwp_ptr_fifo_ctl { uint64_t ptr:29; uint64_t cena:1; uint64_t raddr:8; +#else + uint64_t raddr:8; + uint64_t cena:1; + uint64_t ptr:29; + uint64_t praddr:8; + uint64_t wraddr:8; + uint64_t max_cnts:7; + uint64_t reserved_61_63:3; +#endif } s; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn30xx; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn31xx; @@ -740,15 +1609,23 @@ union cvmx_ipd_pwp_ptr_fifo_ctl { struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1; + struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn61xx; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xx; struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xxp1; + struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn66xx; + struct cvmx_ipd_pwp_ptr_fifo_ctl_s cnf71xx; }; union cvmx_ipd_qosx_red_marks { uint64_t u64; struct cvmx_ipd_qosx_red_marks_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t drop:32; uint64_t pass:32; +#else + uint64_t pass:32; + uint64_t drop:32; +#endif } s; struct cvmx_ipd_qosx_red_marks_s cn30xx; struct cvmx_ipd_qosx_red_marks_s cn31xx; @@ -761,15 +1638,25 @@ union cvmx_ipd_qosx_red_marks { struct cvmx_ipd_qosx_red_marks_s cn56xxp1; struct cvmx_ipd_qosx_red_marks_s cn58xx; struct cvmx_ipd_qosx_red_marks_s cn58xxp1; + struct cvmx_ipd_qosx_red_marks_s cn61xx; struct cvmx_ipd_qosx_red_marks_s cn63xx; struct cvmx_ipd_qosx_red_marks_s cn63xxp1; + struct cvmx_ipd_qosx_red_marks_s cn66xx; + struct cvmx_ipd_qosx_red_marks_s cn68xx; + struct cvmx_ipd_qosx_red_marks_s cn68xxp1; + struct cvmx_ipd_qosx_red_marks_s cnf71xx; }; union cvmx_ipd_que0_free_page_cnt { uint64_t u64; struct cvmx_ipd_que0_free_page_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t q0_pcnt:32; +#else + uint64_t q0_pcnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_ipd_que0_free_page_cnt_s cn30xx; struct cvmx_ipd_que0_free_page_cnt_s cn31xx; @@ -782,16 +1669,57 @@ union cvmx_ipd_que0_free_page_cnt { struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1; struct cvmx_ipd_que0_free_page_cnt_s cn58xx; struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1; + struct cvmx_ipd_que0_free_page_cnt_s cn61xx; struct cvmx_ipd_que0_free_page_cnt_s cn63xx; struct cvmx_ipd_que0_free_page_cnt_s cn63xxp1; + struct cvmx_ipd_que0_free_page_cnt_s cn66xx; + struct cvmx_ipd_que0_free_page_cnt_s cn68xx; + struct cvmx_ipd_que0_free_page_cnt_s cn68xxp1; + struct cvmx_ipd_que0_free_page_cnt_s cnf71xx; +}; + +union cvmx_ipd_red_bpid_enablex { + uint64_t u64; + struct cvmx_ipd_red_bpid_enablex_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t prt_enb:64; +#else + uint64_t prt_enb:64; +#endif + } s; + struct cvmx_ipd_red_bpid_enablex_s cn68xx; + struct cvmx_ipd_red_bpid_enablex_s cn68xxp1; +}; + +union cvmx_ipd_red_delay { + uint64_t u64; + struct cvmx_ipd_red_delay_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_28_63:36; + uint64_t prb_dly:14; + uint64_t avg_dly:14; +#else + uint64_t avg_dly:14; + uint64_t prb_dly:14; + uint64_t reserved_28_63:36; +#endif + } s; + struct cvmx_ipd_red_delay_s cn68xx; + struct cvmx_ipd_red_delay_s cn68xxp1; }; union cvmx_ipd_red_port_enable { uint64_t u64; struct cvmx_ipd_red_port_enable_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t prb_dly:14; uint64_t avg_dly:14; uint64_t prt_enb:36; +#else + uint64_t prt_enb:36; + uint64_t avg_dly:14; + uint64_t prb_dly:14; +#endif } s; struct cvmx_ipd_red_port_enable_s cn30xx; struct cvmx_ipd_red_port_enable_s cn31xx; @@ -804,35 +1732,67 @@ union cvmx_ipd_red_port_enable { struct cvmx_ipd_red_port_enable_s cn56xxp1; struct cvmx_ipd_red_port_enable_s cn58xx; struct cvmx_ipd_red_port_enable_s cn58xxp1; + struct cvmx_ipd_red_port_enable_s cn61xx; struct cvmx_ipd_red_port_enable_s cn63xx; struct cvmx_ipd_red_port_enable_s cn63xxp1; + struct cvmx_ipd_red_port_enable_s cn66xx; + struct cvmx_ipd_red_port_enable_s cnf71xx; }; union cvmx_ipd_red_port_enable2 { uint64_t u64; struct cvmx_ipd_red_port_enable2_s { - uint64_t reserved_8_63:56; - uint64_t prt_enb:8; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t prt_enb:12; +#else + uint64_t prt_enb:12; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_ipd_red_port_enable2_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t prt_enb:4; +#else + uint64_t prt_enb:4; + uint64_t reserved_4_63:60; +#endif } cn52xx; struct cvmx_ipd_red_port_enable2_cn52xx cn52xxp1; struct cvmx_ipd_red_port_enable2_cn52xx cn56xx; struct cvmx_ipd_red_port_enable2_cn52xx cn56xxp1; - struct cvmx_ipd_red_port_enable2_s cn63xx; - struct cvmx_ipd_red_port_enable2_s cn63xxp1; + struct cvmx_ipd_red_port_enable2_s cn61xx; + struct cvmx_ipd_red_port_enable2_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_8_63:56; + uint64_t prt_enb:8; +#else + uint64_t prt_enb:8; + uint64_t reserved_8_63:56; +#endif + } cn63xx; + struct cvmx_ipd_red_port_enable2_cn63xx cn63xxp1; + struct cvmx_ipd_red_port_enable2_s cn66xx; + struct cvmx_ipd_red_port_enable2_s cnf71xx; }; union cvmx_ipd_red_quex_param { uint64_t u64; struct cvmx_ipd_red_quex_param_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t use_pcnt:1; uint64_t new_con:8; uint64_t avg_con:8; uint64_t prb_con:32; +#else + uint64_t prb_con:32; + uint64_t avg_con:8; + uint64_t new_con:8; + uint64_t use_pcnt:1; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_ipd_red_quex_param_s cn30xx; struct cvmx_ipd_red_quex_param_s cn31xx; @@ -845,16 +1805,53 @@ union cvmx_ipd_red_quex_param { struct cvmx_ipd_red_quex_param_s cn56xxp1; struct cvmx_ipd_red_quex_param_s cn58xx; struct cvmx_ipd_red_quex_param_s cn58xxp1; + struct cvmx_ipd_red_quex_param_s cn61xx; struct cvmx_ipd_red_quex_param_s cn63xx; struct cvmx_ipd_red_quex_param_s cn63xxp1; + struct cvmx_ipd_red_quex_param_s cn66xx; + struct cvmx_ipd_red_quex_param_s cn68xx; + struct cvmx_ipd_red_quex_param_s cn68xxp1; + struct cvmx_ipd_red_quex_param_s cnf71xx; +}; + +union cvmx_ipd_req_wgt { + uint64_t u64; + struct cvmx_ipd_req_wgt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t wgt7:8; + uint64_t wgt6:8; + uint64_t wgt5:8; + uint64_t wgt4:8; + uint64_t wgt3:8; + uint64_t wgt2:8; + uint64_t wgt1:8; + uint64_t wgt0:8; +#else + uint64_t wgt0:8; + uint64_t wgt1:8; + uint64_t wgt2:8; + uint64_t wgt3:8; + uint64_t wgt4:8; + uint64_t wgt5:8; + uint64_t wgt6:8; + uint64_t wgt7:8; +#endif + } s; + struct cvmx_ipd_req_wgt_s cn68xx; }; union cvmx_ipd_sub_port_bp_page_cnt { uint64_t u64; struct cvmx_ipd_sub_port_bp_page_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t port:6; uint64_t page_cnt:25; +#else + uint64_t page_cnt:25; + uint64_t port:6; + uint64_t reserved_31_63:33; +#endif } s; struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx; struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx; @@ -867,26 +1864,48 @@ union cvmx_ipd_sub_port_bp_page_cnt { struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1; struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx; struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1; + struct cvmx_ipd_sub_port_bp_page_cnt_s cn61xx; struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xx; struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xxp1; + struct cvmx_ipd_sub_port_bp_page_cnt_s cn66xx; + struct cvmx_ipd_sub_port_bp_page_cnt_s cn68xx; + struct cvmx_ipd_sub_port_bp_page_cnt_s cn68xxp1; + struct cvmx_ipd_sub_port_bp_page_cnt_s cnf71xx; }; union cvmx_ipd_sub_port_fcs { uint64_t u64; struct cvmx_ipd_sub_port_fcs_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t port_bit2:4; uint64_t reserved_32_35:4; uint64_t port_bit:32; +#else + uint64_t port_bit:32; + uint64_t reserved_32_35:4; + uint64_t port_bit2:4; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_ipd_sub_port_fcs_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t port_bit:3; +#else + uint64_t port_bit:3; + uint64_t reserved_3_63:61; +#endif } cn30xx; struct cvmx_ipd_sub_port_fcs_cn30xx cn31xx; struct cvmx_ipd_sub_port_fcs_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port_bit:32; +#else + uint64_t port_bit:32; + uint64_t reserved_32_63:32; +#endif } cn38xx; struct cvmx_ipd_sub_port_fcs_cn38xx cn38xxp2; struct cvmx_ipd_sub_port_fcs_cn30xx cn50xx; @@ -896,30 +1915,49 @@ union cvmx_ipd_sub_port_fcs { struct cvmx_ipd_sub_port_fcs_s cn56xxp1; struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx; struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1; + struct cvmx_ipd_sub_port_fcs_s cn61xx; struct cvmx_ipd_sub_port_fcs_s cn63xx; struct cvmx_ipd_sub_port_fcs_s cn63xxp1; + struct cvmx_ipd_sub_port_fcs_s cn66xx; + struct cvmx_ipd_sub_port_fcs_s cnf71xx; }; union cvmx_ipd_sub_port_qos_cnt { uint64_t u64; struct cvmx_ipd_sub_port_qos_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_41_63:23; uint64_t port_qos:9; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t port_qos:9; + uint64_t reserved_41_63:23; +#endif } s; struct cvmx_ipd_sub_port_qos_cnt_s cn52xx; struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1; struct cvmx_ipd_sub_port_qos_cnt_s cn56xx; struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1; + struct cvmx_ipd_sub_port_qos_cnt_s cn61xx; struct cvmx_ipd_sub_port_qos_cnt_s cn63xx; struct cvmx_ipd_sub_port_qos_cnt_s cn63xxp1; + struct cvmx_ipd_sub_port_qos_cnt_s cn66xx; + struct cvmx_ipd_sub_port_qos_cnt_s cn68xx; + struct cvmx_ipd_sub_port_qos_cnt_s cn68xxp1; + struct cvmx_ipd_sub_port_qos_cnt_s cnf71xx; }; union cvmx_ipd_wqe_fpa_queue { uint64_t u64; struct cvmx_ipd_wqe_fpa_queue_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t wqe_pool:3; +#else + uint64_t wqe_pool:3; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_ipd_wqe_fpa_queue_s cn30xx; struct cvmx_ipd_wqe_fpa_queue_s cn31xx; @@ -932,15 +1970,25 @@ union cvmx_ipd_wqe_fpa_queue { struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1; struct cvmx_ipd_wqe_fpa_queue_s cn58xx; struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1; + struct cvmx_ipd_wqe_fpa_queue_s cn61xx; struct cvmx_ipd_wqe_fpa_queue_s cn63xx; struct cvmx_ipd_wqe_fpa_queue_s cn63xxp1; + struct cvmx_ipd_wqe_fpa_queue_s cn66xx; + struct cvmx_ipd_wqe_fpa_queue_s cn68xx; + struct cvmx_ipd_wqe_fpa_queue_s cn68xxp1; + struct cvmx_ipd_wqe_fpa_queue_s cnf71xx; }; union cvmx_ipd_wqe_ptr_valid { uint64_t u64; struct cvmx_ipd_wqe_ptr_valid_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t ptr:29; +#else + uint64_t ptr:29; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_ipd_wqe_ptr_valid_s cn30xx; struct cvmx_ipd_wqe_ptr_valid_s cn31xx; @@ -952,8 +2000,11 @@ union cvmx_ipd_wqe_ptr_valid { struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1; struct cvmx_ipd_wqe_ptr_valid_s cn58xx; struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1; + struct cvmx_ipd_wqe_ptr_valid_s cn61xx; struct cvmx_ipd_wqe_ptr_valid_s cn63xx; struct cvmx_ipd_wqe_ptr_valid_s cn63xxp1; + struct cvmx_ipd_wqe_ptr_valid_s cn66xx; + struct cvmx_ipd_wqe_ptr_valid_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-ipd.h b/arch/mips/include/asm/octeon/cvmx-ipd.h index 115a552c5c7..e13490ebbb2 100644 --- a/arch/mips/include/asm/octeon/cvmx-ipd.h +++ b/arch/mips/include/asm/octeon/cvmx-ipd.h @@ -38,8 +38,8 @@ #include <asm/octeon/cvmx-ipd-defs.h> enum cvmx_ipd_mode { - CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */ - CVMX_IPD_OPC_MODE_STF = 1LL, /* All bloccks into L2 */ + CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */ + CVMX_IPD_OPC_MODE_STF = 1LL, /* All bloccks into L2 */ CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */ CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */ }; @@ -60,17 +60,17 @@ typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t; * * @mbuff_size: Packets buffer size in 8 byte words * @first_mbuff_skip: - * Number of 8 byte words to skip in the first buffer + * Number of 8 byte words to skip in the first buffer * @not_first_mbuff_skip: - * Number of 8 byte words to skip in each following buffer + * Number of 8 byte words to skip in each following buffer * @first_back: Must be same as first_mbuff_skip / 128 * @second_back: - * Must be same as not_first_mbuff_skip / 128 + * Must be same as not_first_mbuff_skip / 128 * @wqe_fpa_pool: - * FPA pool to get work entries from + * FPA pool to get work entries from * @cache_mode: * @back_pres_enable_flag: - * Enable or disable port back pressure + * Enable or disable port back pressure */ static inline void cvmx_ipd_config(uint64_t mbuff_size, uint64_t first_mbuff_skip, diff --git a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h index 7a50a0beb47..10262cb6ff5 100644 --- a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -33,18 +33,18 @@ #define CVMX_L2C_BST0 (CVMX_ADD_IO_SEG(0x00011800800007F8ull)) #define CVMX_L2C_BST1 (CVMX_ADD_IO_SEG(0x00011800800007F0ull)) #define CVMX_L2C_BST2 (CVMX_ADD_IO_SEG(0x00011800800007E8ull)) -#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull)) -#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull)) -#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull)) +#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull) + ((block_id) & 3) * 0x40000ull) #define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull)) #define CVMX_L2C_COP0_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8) #define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull)) #define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull)) #define CVMX_L2C_DUT (CVMX_ADD_IO_SEG(0x0001180080000050ull)) -#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 2047) * 8) -#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull)) -#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull)) -#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull)) +#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 8191) * 8) +#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull) + ((block_id) & 3) * 0x40000ull) #define CVMX_L2C_ERR_XMC (CVMX_ADD_IO_SEG(0x00011800808007D8ull)) #define CVMX_L2C_GRPWRR0 (CVMX_ADD_IO_SEG(0x00011800800000C8ull)) #define CVMX_L2C_GRPWRR1 (CVMX_ADD_IO_SEG(0x00011800800000D0ull)) @@ -71,54 +71,119 @@ #define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull)) #define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + ((offset) & 3) * 8) #define CVMX_L2C_PPGRP (CVMX_ADD_IO_SEG(0x00011800800000C0ull)) -#define CVMX_L2C_QOS_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080880200ull)) -#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 7) * 8) +#define CVMX_L2C_QOS_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080880200ull) + ((offset) & 1) * 8) +#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 31) * 8) #define CVMX_L2C_QOS_WGT (CVMX_ADD_IO_SEG(0x0001180080800008ull)) -#define CVMX_L2C_RSCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800410ull)) -#define CVMX_L2C_RSDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800418ull)) +#define CVMX_L2C_RSCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800410ull) + ((offset) & 3) * 64) +#define CVMX_L2C_RSDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800418ull) + ((offset) & 3) * 64) #define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull)) #define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull)) #define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull)) #define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull)) #define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull)) -#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull)) -#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull)) -#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull)) -#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull)) -#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull)) -#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull)) -#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull)) -#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull)) -#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull)) -#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull)) +#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull) + ((block_id) & 3) * 0x40000ull) #define CVMX_L2C_VER_ID (CVMX_ADD_IO_SEG(0x00011800808007E0ull)) #define CVMX_L2C_VER_IOB (CVMX_ADD_IO_SEG(0x00011800808007F0ull)) #define CVMX_L2C_VER_MSC (CVMX_ADD_IO_SEG(0x00011800808007D0ull)) #define CVMX_L2C_VER_PP (CVMX_ADD_IO_SEG(0x00011800808007E8ull)) -#define CVMX_L2C_VIRTID_IOBX(block_id) (CVMX_ADD_IO_SEG(0x00011800808C0200ull)) -#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 7) * 8) +#define CVMX_L2C_VIRTID_IOBX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0200ull) + ((offset) & 1) * 8) +#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 31) * 8) #define CVMX_L2C_VRT_CTL (CVMX_ADD_IO_SEG(0x0001180080800010ull)) #define CVMX_L2C_VRT_MEMX(offset) (CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8) -#define CVMX_L2C_WPAR_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080840200ull)) -#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 7) * 8) -#define CVMX_L2C_XMCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800400ull)) +#define CVMX_L2C_WPAR_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080840200ull) + ((offset) & 1) * 8) +#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 31) * 8) +#define CVMX_L2C_XMCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800400ull) + ((offset) & 3) * 64) #define CVMX_L2C_XMC_CMD (CVMX_ADD_IO_SEG(0x0001180080800028ull)) -#define CVMX_L2C_XMDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800408ull)) +#define CVMX_L2C_XMDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800408ull) + ((offset) & 3) * 64) union cvmx_l2c_big_ctl { uint64_t u64; struct cvmx_l2c_big_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t maxdram:4; uint64_t reserved_1_3:3; uint64_t disable:1; +#else + uint64_t disable:1; + uint64_t reserved_1_3:3; + uint64_t maxdram:4; + uint64_t reserved_8_63:56; +#endif } s; + struct cvmx_l2c_big_ctl_s cn61xx; struct cvmx_l2c_big_ctl_s cn63xx; + struct cvmx_l2c_big_ctl_s cn66xx; + struct cvmx_l2c_big_ctl_s cn68xx; + struct cvmx_l2c_big_ctl_s cn68xxp1; + struct cvmx_l2c_big_ctl_s cnf71xx; }; union cvmx_l2c_bst { uint64_t u64; struct cvmx_l2c_bst_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dutfl:32; + uint64_t rbffl:4; + uint64_t xbffl:4; + uint64_t tdpfl:4; + uint64_t ioccmdfl:4; + uint64_t iocdatfl:4; + uint64_t dutresfl:4; + uint64_t vrtfl:4; + uint64_t tdffl:4; +#else + uint64_t tdffl:4; + uint64_t vrtfl:4; + uint64_t dutresfl:4; + uint64_t iocdatfl:4; + uint64_t ioccmdfl:4; + uint64_t tdpfl:4; + uint64_t xbffl:4; + uint64_t rbffl:4; + uint64_t dutfl:32; +#endif + } s; + struct cvmx_l2c_bst_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_36_63:28; + uint64_t dutfl:4; + uint64_t reserved_17_31:15; + uint64_t ioccmdfl:1; + uint64_t reserved_13_15:3; + uint64_t iocdatfl:1; + uint64_t reserved_9_11:3; + uint64_t dutresfl:1; + uint64_t reserved_5_7:3; + uint64_t vrtfl:1; + uint64_t reserved_1_3:3; + uint64_t tdffl:1; +#else + uint64_t tdffl:1; + uint64_t reserved_1_3:3; + uint64_t vrtfl:1; + uint64_t reserved_5_7:3; + uint64_t dutresfl:1; + uint64_t reserved_9_11:3; + uint64_t iocdatfl:1; + uint64_t reserved_13_15:3; + uint64_t ioccmdfl:1; + uint64_t reserved_17_31:15; + uint64_t dutfl:4; + uint64_t reserved_36_63:28; +#endif + } cn61xx; + struct cvmx_l2c_bst_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t dutfl:6; uint64_t reserved_17_31:15; @@ -131,14 +196,60 @@ union cvmx_l2c_bst { uint64_t vrtfl:1; uint64_t reserved_1_3:3; uint64_t tdffl:1; - } s; - struct cvmx_l2c_bst_s cn63xx; - struct cvmx_l2c_bst_s cn63xxp1; +#else + uint64_t tdffl:1; + uint64_t reserved_1_3:3; + uint64_t vrtfl:1; + uint64_t reserved_5_7:3; + uint64_t dutresfl:1; + uint64_t reserved_9_11:3; + uint64_t iocdatfl:1; + uint64_t reserved_13_15:3; + uint64_t ioccmdfl:1; + uint64_t reserved_17_31:15; + uint64_t dutfl:6; + uint64_t reserved_38_63:26; +#endif + } cn63xx; + struct cvmx_l2c_bst_cn63xx cn63xxp1; + struct cvmx_l2c_bst_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_42_63:22; + uint64_t dutfl:10; + uint64_t reserved_17_31:15; + uint64_t ioccmdfl:1; + uint64_t reserved_13_15:3; + uint64_t iocdatfl:1; + uint64_t reserved_9_11:3; + uint64_t dutresfl:1; + uint64_t reserved_5_7:3; + uint64_t vrtfl:1; + uint64_t reserved_1_3:3; + uint64_t tdffl:1; +#else + uint64_t tdffl:1; + uint64_t reserved_1_3:3; + uint64_t vrtfl:1; + uint64_t reserved_5_7:3; + uint64_t dutresfl:1; + uint64_t reserved_9_11:3; + uint64_t iocdatfl:1; + uint64_t reserved_13_15:3; + uint64_t ioccmdfl:1; + uint64_t reserved_17_31:15; + uint64_t dutfl:10; + uint64_t reserved_42_63:22; +#endif + } cn66xx; + struct cvmx_l2c_bst_s cn68xx; + struct cvmx_l2c_bst_s cn68xxp1; + struct cvmx_l2c_bst_cn61xx cnf71xx; }; union cvmx_l2c_bst0 { uint64_t u64; struct cvmx_l2c_bst0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t dtbnk:1; uint64_t wlb_msk:4; @@ -146,8 +257,18 @@ union cvmx_l2c_bst0 { uint64_t dt:1; uint64_t stin_msk:1; uint64_t wlb_dat:4; +#else + uint64_t wlb_dat:4; + uint64_t stin_msk:1; + uint64_t dt:1; + uint64_t dtcnt:13; + uint64_t wlb_msk:4; + uint64_t dtbnk:1; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_l2c_bst0_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t wlb_msk:4; uint64_t reserved_15_18:4; @@ -155,8 +276,18 @@ union cvmx_l2c_bst0 { uint64_t dt:1; uint64_t reserved_4_4:1; uint64_t wlb_dat:4; +#else + uint64_t wlb_dat:4; + uint64_t reserved_4_4:1; + uint64_t dt:1; + uint64_t dtcnt:9; + uint64_t reserved_15_18:4; + uint64_t wlb_msk:4; + uint64_t reserved_23_63:41; +#endif } cn30xx; struct cvmx_l2c_bst0_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t wlb_msk:4; uint64_t reserved_16_18:3; @@ -164,16 +295,34 @@ union cvmx_l2c_bst0 { uint64_t dt:1; uint64_t stin_msk:1; uint64_t wlb_dat:4; +#else + uint64_t wlb_dat:4; + uint64_t stin_msk:1; + uint64_t dt:1; + uint64_t dtcnt:10; + uint64_t reserved_16_18:3; + uint64_t wlb_msk:4; + uint64_t reserved_23_63:41; +#endif } cn31xx; struct cvmx_l2c_bst0_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t dtcnt:13; uint64_t dt:1; uint64_t stin_msk:1; uint64_t wlb_dat:4; +#else + uint64_t wlb_dat:4; + uint64_t stin_msk:1; + uint64_t dt:1; + uint64_t dtcnt:13; + uint64_t reserved_19_63:45; +#endif } cn38xx; struct cvmx_l2c_bst0_cn38xx cn38xxp2; struct cvmx_l2c_bst0_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t dtbnk:1; uint64_t wlb_msk:4; @@ -182,6 +331,16 @@ union cvmx_l2c_bst0 { uint64_t dt:1; uint64_t stin_msk:1; uint64_t wlb_dat:4; +#else + uint64_t wlb_dat:4; + uint64_t stin_msk:1; + uint64_t dt:1; + uint64_t dtcnt:10; + uint64_t reserved_16_18:3; + uint64_t wlb_msk:4; + uint64_t dtbnk:1; + uint64_t reserved_24_63:40; +#endif } cn50xx; struct cvmx_l2c_bst0_cn50xx cn52xx; struct cvmx_l2c_bst0_cn50xx cn52xxp1; @@ -194,28 +353,51 @@ union cvmx_l2c_bst0 { union cvmx_l2c_bst1 { uint64_t u64; struct cvmx_l2c_bst1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t l2t:9; +#else + uint64_t l2t:9; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_l2c_bst1_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t vwdf:4; uint64_t lrf:2; uint64_t vab_vwcf:1; uint64_t reserved_5_8:4; uint64_t l2t:5; +#else + uint64_t l2t:5; + uint64_t reserved_5_8:4; + uint64_t vab_vwcf:1; + uint64_t lrf:2; + uint64_t vwdf:4; + uint64_t reserved_16_63:48; +#endif } cn30xx; struct cvmx_l2c_bst1_cn30xx cn31xx; struct cvmx_l2c_bst1_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t vwdf:4; uint64_t lrf:2; uint64_t vab_vwcf:1; uint64_t l2t:9; +#else + uint64_t l2t:9; + uint64_t vab_vwcf:1; + uint64_t lrf:2; + uint64_t vwdf:4; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_l2c_bst1_cn38xx cn38xxp2; struct cvmx_l2c_bst1_cn38xx cn50xx; struct cvmx_l2c_bst1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t plc2:1; uint64_t plc1:1; @@ -225,9 +407,21 @@ union cvmx_l2c_bst1 { uint64_t ilc:1; uint64_t vab_vwcf:1; uint64_t l2t:9; +#else + uint64_t l2t:9; + uint64_t vab_vwcf:1; + uint64_t ilc:1; + uint64_t reserved_11_11:1; + uint64_t vwdf:4; + uint64_t plc0:1; + uint64_t plc1:1; + uint64_t plc2:1; + uint64_t reserved_19_63:45; +#endif } cn52xx; struct cvmx_l2c_bst1_cn52xx cn52xxp1; struct cvmx_l2c_bst1_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t plc2:1; uint64_t plc1:1; @@ -239,6 +433,19 @@ union cvmx_l2c_bst1 { uint64_t reserved_10_10:1; uint64_t vab_vwcf0:1; uint64_t l2t:9; +#else + uint64_t l2t:9; + uint64_t vab_vwcf0:1; + uint64_t reserved_10_10:1; + uint64_t vab_vwcf1:1; + uint64_t vwdf0:4; + uint64_t vwdf1:4; + uint64_t ilc:1; + uint64_t plc0:1; + uint64_t plc1:1; + uint64_t plc2:1; + uint64_t reserved_24_63:40; +#endif } cn56xx; struct cvmx_l2c_bst1_cn56xx cn56xxp1; struct cvmx_l2c_bst1_cn38xx cn58xx; @@ -248,6 +455,7 @@ union cvmx_l2c_bst1 { union cvmx_l2c_bst2 { uint64_t u64; struct cvmx_l2c_bst2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mrb:4; uint64_t reserved_4_11:8; @@ -255,8 +463,18 @@ union cvmx_l2c_bst2 { uint64_t picbst:1; uint64_t xrdmsk:1; uint64_t xrddat:1; +#else + uint64_t xrddat:1; + uint64_t xrdmsk:1; + uint64_t picbst:1; + uint64_t ipcbst:1; + uint64_t reserved_4_11:8; + uint64_t mrb:4; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_l2c_bst2_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mrb:4; uint64_t rmdf:4; @@ -265,9 +483,20 @@ union cvmx_l2c_bst2 { uint64_t reserved_2_2:1; uint64_t xrdmsk:1; uint64_t xrddat:1; +#else + uint64_t xrddat:1; + uint64_t xrdmsk:1; + uint64_t reserved_2_2:1; + uint64_t ipcbst:1; + uint64_t reserved_4_7:4; + uint64_t rmdf:4; + uint64_t mrb:4; + uint64_t reserved_16_63:48; +#endif } cn30xx; struct cvmx_l2c_bst2_cn30xx cn31xx; struct cvmx_l2c_bst2_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mrb:4; uint64_t rmdf:4; @@ -276,12 +505,23 @@ union cvmx_l2c_bst2 { uint64_t picbst:1; uint64_t xrdmsk:1; uint64_t xrddat:1; +#else + uint64_t xrddat:1; + uint64_t xrdmsk:1; + uint64_t picbst:1; + uint64_t ipcbst:1; + uint64_t rhdf:4; + uint64_t rmdf:4; + uint64_t mrb:4; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_l2c_bst2_cn38xx cn38xxp2; struct cvmx_l2c_bst2_cn30xx cn50xx; struct cvmx_l2c_bst2_cn30xx cn52xx; struct cvmx_l2c_bst2_cn30xx cn52xxp1; struct cvmx_l2c_bst2_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mrb:4; uint64_t rmdb:4; @@ -290,6 +530,16 @@ union cvmx_l2c_bst2 { uint64_t picbst:1; uint64_t xrdmsk:1; uint64_t xrddat:1; +#else + uint64_t xrddat:1; + uint64_t xrdmsk:1; + uint64_t picbst:1; + uint64_t ipcbst:1; + uint64_t rhdb:4; + uint64_t rmdb:4; + uint64_t mrb:4; + uint64_t reserved_16_63:48; +#endif } cn56xx; struct cvmx_l2c_bst2_cn56xx cn56xxp1; struct cvmx_l2c_bst2_cn56xx cn58xx; @@ -299,48 +549,93 @@ union cvmx_l2c_bst2 { union cvmx_l2c_bst_memx { uint64_t u64; struct cvmx_l2c_bst_memx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t start_bist:1; uint64_t clear_bist:1; uint64_t reserved_5_61:57; uint64_t rdffl:1; uint64_t vbffl:4; +#else + uint64_t vbffl:4; + uint64_t rdffl:1; + uint64_t reserved_5_61:57; + uint64_t clear_bist:1; + uint64_t start_bist:1; +#endif } s; + struct cvmx_l2c_bst_memx_s cn61xx; struct cvmx_l2c_bst_memx_s cn63xx; struct cvmx_l2c_bst_memx_s cn63xxp1; + struct cvmx_l2c_bst_memx_s cn66xx; + struct cvmx_l2c_bst_memx_s cn68xx; + struct cvmx_l2c_bst_memx_s cn68xxp1; + struct cvmx_l2c_bst_memx_s cnf71xx; }; union cvmx_l2c_bst_tdtx { uint64_t u64; struct cvmx_l2c_bst_tdtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t fbfrspfl:8; uint64_t sbffl:8; uint64_t fbffl:8; uint64_t l2dfl:8; +#else + uint64_t l2dfl:8; + uint64_t fbffl:8; + uint64_t sbffl:8; + uint64_t fbfrspfl:8; + uint64_t reserved_32_63:32; +#endif } s; + struct cvmx_l2c_bst_tdtx_s cn61xx; struct cvmx_l2c_bst_tdtx_s cn63xx; struct cvmx_l2c_bst_tdtx_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t sbffl:8; uint64_t fbffl:8; uint64_t l2dfl:8; +#else + uint64_t l2dfl:8; + uint64_t fbffl:8; + uint64_t sbffl:8; + uint64_t reserved_24_63:40; +#endif } cn63xxp1; + struct cvmx_l2c_bst_tdtx_s cn66xx; + struct cvmx_l2c_bst_tdtx_s cn68xx; + struct cvmx_l2c_bst_tdtx_s cn68xxp1; + struct cvmx_l2c_bst_tdtx_s cnf71xx; }; union cvmx_l2c_bst_ttgx { uint64_t u64; struct cvmx_l2c_bst_ttgx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t lrufl:1; uint64_t tagfl:16; +#else + uint64_t tagfl:16; + uint64_t lrufl:1; + uint64_t reserved_17_63:47; +#endif } s; + struct cvmx_l2c_bst_ttgx_s cn61xx; struct cvmx_l2c_bst_ttgx_s cn63xx; struct cvmx_l2c_bst_ttgx_s cn63xxp1; + struct cvmx_l2c_bst_ttgx_s cn66xx; + struct cvmx_l2c_bst_ttgx_s cn68xx; + struct cvmx_l2c_bst_ttgx_s cn68xxp1; + struct cvmx_l2c_bst_ttgx_s cnf71xx; }; union cvmx_l2c_cfg { uint64_t u64; struct cvmx_l2c_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t bstrun:1; uint64_t lbist:1; @@ -356,8 +651,26 @@ union cvmx_l2c_cfg { uint64_t rsp_arb_mode:1; uint64_t rfb_arb_mode:1; uint64_t lrf_arb_mode:1; +#else + uint64_t lrf_arb_mode:1; + uint64_t rfb_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t mwf_crd:4; + uint64_t idxalias:1; + uint64_t fpen:1; + uint64_t fpempty:1; + uint64_t fpexp:4; + uint64_t dfill_dis:1; + uint64_t dpres0:1; + uint64_t dpres1:1; + uint64_t xor_bank:1; + uint64_t lbist:1; + uint64_t bstrun:1; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_l2c_cfg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t fpexp:4; uint64_t fpempty:1; @@ -367,11 +680,23 @@ union cvmx_l2c_cfg { uint64_t rsp_arb_mode:1; uint64_t rfb_arb_mode:1; uint64_t lrf_arb_mode:1; +#else + uint64_t lrf_arb_mode:1; + uint64_t rfb_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t mwf_crd:4; + uint64_t idxalias:1; + uint64_t fpen:1; + uint64_t fpempty:1; + uint64_t fpexp:4; + uint64_t reserved_14_63:50; +#endif } cn30xx; struct cvmx_l2c_cfg_cn30xx cn31xx; struct cvmx_l2c_cfg_cn30xx cn38xx; struct cvmx_l2c_cfg_cn30xx cn38xxp2; struct cvmx_l2c_cfg_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t bstrun:1; uint64_t lbist:1; @@ -384,12 +709,27 @@ union cvmx_l2c_cfg { uint64_t rsp_arb_mode:1; uint64_t rfb_arb_mode:1; uint64_t lrf_arb_mode:1; +#else + uint64_t lrf_arb_mode:1; + uint64_t rfb_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t mwf_crd:4; + uint64_t idxalias:1; + uint64_t fpen:1; + uint64_t fpempty:1; + uint64_t fpexp:4; + uint64_t reserved_14_17:4; + uint64_t lbist:1; + uint64_t bstrun:1; + uint64_t reserved_20_63:44; +#endif } cn50xx; struct cvmx_l2c_cfg_cn50xx cn52xx; struct cvmx_l2c_cfg_cn50xx cn52xxp1; struct cvmx_l2c_cfg_s cn56xx; struct cvmx_l2c_cfg_s cn56xxp1; struct cvmx_l2c_cfg_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t bstrun:1; uint64_t lbist:1; @@ -403,8 +743,24 @@ union cvmx_l2c_cfg { uint64_t rsp_arb_mode:1; uint64_t rfb_arb_mode:1; uint64_t lrf_arb_mode:1; +#else + uint64_t lrf_arb_mode:1; + uint64_t rfb_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t mwf_crd:4; + uint64_t idxalias:1; + uint64_t fpen:1; + uint64_t fpempty:1; + uint64_t fpexp:4; + uint64_t dfill_dis:1; + uint64_t reserved_15_17:3; + uint64_t lbist:1; + uint64_t bstrun:1; + uint64_t reserved_20_63:44; +#endif } cn58xx; struct cvmx_l2c_cfg_cn58xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t dfill_dis:1; uint64_t fpexp:4; @@ -415,22 +771,46 @@ union cvmx_l2c_cfg { uint64_t rsp_arb_mode:1; uint64_t rfb_arb_mode:1; uint64_t lrf_arb_mode:1; +#else + uint64_t lrf_arb_mode:1; + uint64_t rfb_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t mwf_crd:4; + uint64_t idxalias:1; + uint64_t fpen:1; + uint64_t fpempty:1; + uint64_t fpexp:4; + uint64_t dfill_dis:1; + uint64_t reserved_15_63:49; +#endif } cn58xxp1; }; union cvmx_l2c_cop0_mapx { uint64_t u64; struct cvmx_l2c_cop0_mapx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; +#else + uint64_t data:64; +#endif } s; + struct cvmx_l2c_cop0_mapx_s cn61xx; struct cvmx_l2c_cop0_mapx_s cn63xx; struct cvmx_l2c_cop0_mapx_s cn63xxp1; + struct cvmx_l2c_cop0_mapx_s cn66xx; + struct cvmx_l2c_cop0_mapx_s cn68xx; + struct cvmx_l2c_cop0_mapx_s cn68xxp1; + struct cvmx_l2c_cop0_mapx_s cnf71xx; }; union cvmx_l2c_ctl { uint64_t u64; struct cvmx_l2c_ctl_s { - uint64_t reserved_28_63:36; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_30_63:34; + uint64_t sepcmt:1; + uint64_t rdf_fast:1; uint64_t disstgl2i:1; uint64_t l2dfsbe:1; uint64_t l2dfdbe:1; @@ -444,9 +824,95 @@ union cvmx_l2c_ctl { uint64_t vab_thresh:4; uint64_t disecc:1; uint64_t disidxalias:1; +#else + uint64_t disidxalias:1; + uint64_t disecc:1; + uint64_t vab_thresh:4; + uint64_t ef_cnt:7; + uint64_t ef_ena:1; + uint64_t xmc_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t maxlfb:4; + uint64_t maxvab:4; + uint64_t discclk:1; + uint64_t l2dfdbe:1; + uint64_t l2dfsbe:1; + uint64_t disstgl2i:1; + uint64_t rdf_fast:1; + uint64_t sepcmt:1; + uint64_t reserved_30_63:34; +#endif } s; - struct cvmx_l2c_ctl_s cn63xx; + struct cvmx_l2c_ctl_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t rdf_fast:1; + uint64_t disstgl2i:1; + uint64_t l2dfsbe:1; + uint64_t l2dfdbe:1; + uint64_t discclk:1; + uint64_t maxvab:4; + uint64_t maxlfb:4; + uint64_t rsp_arb_mode:1; + uint64_t xmc_arb_mode:1; + uint64_t ef_ena:1; + uint64_t ef_cnt:7; + uint64_t vab_thresh:4; + uint64_t disecc:1; + uint64_t disidxalias:1; +#else + uint64_t disidxalias:1; + uint64_t disecc:1; + uint64_t vab_thresh:4; + uint64_t ef_cnt:7; + uint64_t ef_ena:1; + uint64_t xmc_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t maxlfb:4; + uint64_t maxvab:4; + uint64_t discclk:1; + uint64_t l2dfdbe:1; + uint64_t l2dfsbe:1; + uint64_t disstgl2i:1; + uint64_t rdf_fast:1; + uint64_t reserved_29_63:35; +#endif + } cn61xx; + struct cvmx_l2c_ctl_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_28_63:36; + uint64_t disstgl2i:1; + uint64_t l2dfsbe:1; + uint64_t l2dfdbe:1; + uint64_t discclk:1; + uint64_t maxvab:4; + uint64_t maxlfb:4; + uint64_t rsp_arb_mode:1; + uint64_t xmc_arb_mode:1; + uint64_t ef_ena:1; + uint64_t ef_cnt:7; + uint64_t vab_thresh:4; + uint64_t disecc:1; + uint64_t disidxalias:1; +#else + uint64_t disidxalias:1; + uint64_t disecc:1; + uint64_t vab_thresh:4; + uint64_t ef_cnt:7; + uint64_t ef_ena:1; + uint64_t xmc_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t maxlfb:4; + uint64_t maxvab:4; + uint64_t discclk:1; + uint64_t l2dfdbe:1; + uint64_t l2dfsbe:1; + uint64_t disstgl2i:1; + uint64_t reserved_28_63:36; +#endif + } cn63xx; struct cvmx_l2c_ctl_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t discclk:1; uint64_t maxvab:4; @@ -458,12 +924,30 @@ union cvmx_l2c_ctl { uint64_t vab_thresh:4; uint64_t disecc:1; uint64_t disidxalias:1; +#else + uint64_t disidxalias:1; + uint64_t disecc:1; + uint64_t vab_thresh:4; + uint64_t ef_cnt:7; + uint64_t ef_ena:1; + uint64_t xmc_arb_mode:1; + uint64_t rsp_arb_mode:1; + uint64_t maxlfb:4; + uint64_t maxvab:4; + uint64_t discclk:1; + uint64_t reserved_25_63:39; +#endif } cn63xxp1; + struct cvmx_l2c_ctl_cn61xx cn66xx; + struct cvmx_l2c_ctl_s cn68xx; + struct cvmx_l2c_ctl_cn63xx cn68xxp1; + struct cvmx_l2c_ctl_cn61xx cnf71xx; }; union cvmx_l2c_dbg { uint64_t u64; struct cvmx_l2c_dbg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t lfb_enum:4; uint64_t lfb_dmp:1; @@ -472,8 +956,19 @@ union cvmx_l2c_dbg { uint64_t finv:1; uint64_t l2d:1; uint64_t l2t:1; +#else + uint64_t l2t:1; + uint64_t l2d:1; + uint64_t finv:1; + uint64_t set:3; + uint64_t ppnum:4; + uint64_t lfb_dmp:1; + uint64_t lfb_enum:4; + uint64_t reserved_15_63:49; +#endif } s; struct cvmx_l2c_dbg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t lfb_enum:2; uint64_t lfb_dmp:1; @@ -484,8 +979,21 @@ union cvmx_l2c_dbg { uint64_t finv:1; uint64_t l2d:1; uint64_t l2t:1; +#else + uint64_t l2t:1; + uint64_t l2d:1; + uint64_t finv:1; + uint64_t set:2; + uint64_t reserved_5_5:1; + uint64_t ppnum:1; + uint64_t reserved_7_9:3; + uint64_t lfb_dmp:1; + uint64_t lfb_enum:2; + uint64_t reserved_13_63:51; +#endif } cn30xx; struct cvmx_l2c_dbg_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t lfb_enum:3; uint64_t lfb_dmp:1; @@ -496,10 +1004,23 @@ union cvmx_l2c_dbg { uint64_t finv:1; uint64_t l2d:1; uint64_t l2t:1; +#else + uint64_t l2t:1; + uint64_t l2d:1; + uint64_t finv:1; + uint64_t set:2; + uint64_t reserved_5_5:1; + uint64_t ppnum:1; + uint64_t reserved_7_9:3; + uint64_t lfb_dmp:1; + uint64_t lfb_enum:3; + uint64_t reserved_14_63:50; +#endif } cn31xx; struct cvmx_l2c_dbg_s cn38xx; struct cvmx_l2c_dbg_s cn38xxp2; struct cvmx_l2c_dbg_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t lfb_enum:3; uint64_t lfb_dmp:1; @@ -509,8 +1030,20 @@ union cvmx_l2c_dbg { uint64_t finv:1; uint64_t l2d:1; uint64_t l2t:1; +#else + uint64_t l2t:1; + uint64_t l2d:1; + uint64_t finv:1; + uint64_t set:3; + uint64_t ppnum:1; + uint64_t reserved_7_9:3; + uint64_t lfb_dmp:1; + uint64_t lfb_enum:3; + uint64_t reserved_14_63:50; +#endif } cn50xx; struct cvmx_l2c_dbg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t lfb_enum:3; uint64_t lfb_dmp:1; @@ -520,6 +1053,17 @@ union cvmx_l2c_dbg { uint64_t finv:1; uint64_t l2d:1; uint64_t l2t:1; +#else + uint64_t l2t:1; + uint64_t l2d:1; + uint64_t finv:1; + uint64_t set:3; + uint64_t ppnum:2; + uint64_t reserved_8_9:2; + uint64_t lfb_dmp:1; + uint64_t lfb_enum:3; + uint64_t reserved_14_63:50; +#endif } cn52xx; struct cvmx_l2c_dbg_cn52xx cn52xxp1; struct cvmx_l2c_dbg_s cn56xx; @@ -531,11 +1075,19 @@ union cvmx_l2c_dbg { union cvmx_l2c_dut { uint64_t u64; struct cvmx_l2c_dut_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t dtena:1; uint64_t reserved_30_30:1; uint64_t dt_vld:1; uint64_t dt_tag:29; +#else + uint64_t dt_tag:29; + uint64_t dt_vld:1; + uint64_t reserved_30_30:1; + uint64_t dtena:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_l2c_dut_s cn30xx; struct cvmx_l2c_dut_s cn31xx; @@ -553,18 +1105,77 @@ union cvmx_l2c_dut { union cvmx_l2c_dut_mapx { uint64_t u64; struct cvmx_l2c_dut_mapx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t tag:28; uint64_t reserved_1_9:9; uint64_t valid:1; +#else + uint64_t valid:1; + uint64_t reserved_1_9:9; + uint64_t tag:28; + uint64_t reserved_38_63:26; +#endif } s; + struct cvmx_l2c_dut_mapx_s cn61xx; struct cvmx_l2c_dut_mapx_s cn63xx; struct cvmx_l2c_dut_mapx_s cn63xxp1; + struct cvmx_l2c_dut_mapx_s cn66xx; + struct cvmx_l2c_dut_mapx_s cn68xx; + struct cvmx_l2c_dut_mapx_s cn68xxp1; + struct cvmx_l2c_dut_mapx_s cnf71xx; }; union cvmx_l2c_err_tdtx { uint64_t u64; struct cvmx_l2c_err_tdtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dbe:1; + uint64_t sbe:1; + uint64_t vdbe:1; + uint64_t vsbe:1; + uint64_t syn:10; + uint64_t reserved_22_49:28; + uint64_t wayidx:18; + uint64_t reserved_2_3:2; + uint64_t type:2; +#else + uint64_t type:2; + uint64_t reserved_2_3:2; + uint64_t wayidx:18; + uint64_t reserved_22_49:28; + uint64_t syn:10; + uint64_t vsbe:1; + uint64_t vdbe:1; + uint64_t sbe:1; + uint64_t dbe:1; +#endif + } s; + struct cvmx_l2c_err_tdtx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dbe:1; + uint64_t sbe:1; + uint64_t vdbe:1; + uint64_t vsbe:1; + uint64_t syn:10; + uint64_t reserved_20_49:30; + uint64_t wayidx:16; + uint64_t reserved_2_3:2; + uint64_t type:2; +#else + uint64_t type:2; + uint64_t reserved_2_3:2; + uint64_t wayidx:16; + uint64_t reserved_20_49:30; + uint64_t syn:10; + uint64_t vsbe:1; + uint64_t vdbe:1; + uint64_t sbe:1; + uint64_t dbe:1; +#endif + } cn61xx; + struct cvmx_l2c_err_tdtx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dbe:1; uint64_t sbe:1; uint64_t vdbe:1; @@ -574,14 +1185,75 @@ union cvmx_l2c_err_tdtx { uint64_t wayidx:17; uint64_t reserved_2_3:2; uint64_t type:2; - } s; - struct cvmx_l2c_err_tdtx_s cn63xx; - struct cvmx_l2c_err_tdtx_s cn63xxp1; +#else + uint64_t type:2; + uint64_t reserved_2_3:2; + uint64_t wayidx:17; + uint64_t reserved_21_49:29; + uint64_t syn:10; + uint64_t vsbe:1; + uint64_t vdbe:1; + uint64_t sbe:1; + uint64_t dbe:1; +#endif + } cn63xx; + struct cvmx_l2c_err_tdtx_cn63xx cn63xxp1; + struct cvmx_l2c_err_tdtx_cn63xx cn66xx; + struct cvmx_l2c_err_tdtx_s cn68xx; + struct cvmx_l2c_err_tdtx_s cn68xxp1; + struct cvmx_l2c_err_tdtx_cn61xx cnf71xx; }; union cvmx_l2c_err_ttgx { uint64_t u64; struct cvmx_l2c_err_ttgx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dbe:1; + uint64_t sbe:1; + uint64_t noway:1; + uint64_t reserved_56_60:5; + uint64_t syn:6; + uint64_t reserved_22_49:28; + uint64_t wayidx:15; + uint64_t reserved_2_6:5; + uint64_t type:2; +#else + uint64_t type:2; + uint64_t reserved_2_6:5; + uint64_t wayidx:15; + uint64_t reserved_22_49:28; + uint64_t syn:6; + uint64_t reserved_56_60:5; + uint64_t noway:1; + uint64_t sbe:1; + uint64_t dbe:1; +#endif + } s; + struct cvmx_l2c_err_ttgx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dbe:1; + uint64_t sbe:1; + uint64_t noway:1; + uint64_t reserved_56_60:5; + uint64_t syn:6; + uint64_t reserved_20_49:30; + uint64_t wayidx:13; + uint64_t reserved_2_6:5; + uint64_t type:2; +#else + uint64_t type:2; + uint64_t reserved_2_6:5; + uint64_t wayidx:13; + uint64_t reserved_20_49:30; + uint64_t syn:6; + uint64_t reserved_56_60:5; + uint64_t noway:1; + uint64_t sbe:1; + uint64_t dbe:1; +#endif + } cn61xx; + struct cvmx_l2c_err_ttgx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dbe:1; uint64_t sbe:1; uint64_t noway:1; @@ -591,43 +1263,117 @@ union cvmx_l2c_err_ttgx { uint64_t wayidx:14; uint64_t reserved_2_6:5; uint64_t type:2; - } s; - struct cvmx_l2c_err_ttgx_s cn63xx; - struct cvmx_l2c_err_ttgx_s cn63xxp1; +#else + uint64_t type:2; + uint64_t reserved_2_6:5; + uint64_t wayidx:14; + uint64_t reserved_21_49:29; + uint64_t syn:6; + uint64_t reserved_56_60:5; + uint64_t noway:1; + uint64_t sbe:1; + uint64_t dbe:1; +#endif + } cn63xx; + struct cvmx_l2c_err_ttgx_cn63xx cn63xxp1; + struct cvmx_l2c_err_ttgx_cn63xx cn66xx; + struct cvmx_l2c_err_ttgx_s cn68xx; + struct cvmx_l2c_err_ttgx_s cn68xxp1; + struct cvmx_l2c_err_ttgx_cn61xx cnf71xx; }; union cvmx_l2c_err_vbfx { uint64_t u64; struct cvmx_l2c_err_vbfx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t vdbe:1; uint64_t vsbe:1; uint64_t vsyn:10; uint64_t reserved_2_49:48; uint64_t type:2; +#else + uint64_t type:2; + uint64_t reserved_2_49:48; + uint64_t vsyn:10; + uint64_t vsbe:1; + uint64_t vdbe:1; + uint64_t reserved_62_63:2; +#endif } s; + struct cvmx_l2c_err_vbfx_s cn61xx; struct cvmx_l2c_err_vbfx_s cn63xx; struct cvmx_l2c_err_vbfx_s cn63xxp1; + struct cvmx_l2c_err_vbfx_s cn66xx; + struct cvmx_l2c_err_vbfx_s cn68xx; + struct cvmx_l2c_err_vbfx_s cn68xxp1; + struct cvmx_l2c_err_vbfx_s cnf71xx; }; union cvmx_l2c_err_xmc { uint64_t u64; struct cvmx_l2c_err_xmc_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t cmd:6; + uint64_t reserved_54_57:4; + uint64_t sid:6; + uint64_t reserved_38_47:10; + uint64_t addr:38; +#else + uint64_t addr:38; + uint64_t reserved_38_47:10; + uint64_t sid:6; + uint64_t reserved_54_57:4; + uint64_t cmd:6; +#endif + } s; + struct cvmx_l2c_err_xmc_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t cmd:6; uint64_t reserved_52_57:6; uint64_t sid:4; uint64_t reserved_38_47:10; uint64_t addr:38; - } s; - struct cvmx_l2c_err_xmc_s cn63xx; - struct cvmx_l2c_err_xmc_s cn63xxp1; +#else + uint64_t addr:38; + uint64_t reserved_38_47:10; + uint64_t sid:4; + uint64_t reserved_52_57:6; + uint64_t cmd:6; +#endif + } cn61xx; + struct cvmx_l2c_err_xmc_cn61xx cn63xx; + struct cvmx_l2c_err_xmc_cn61xx cn63xxp1; + struct cvmx_l2c_err_xmc_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t cmd:6; + uint64_t reserved_53_57:5; + uint64_t sid:5; + uint64_t reserved_38_47:10; + uint64_t addr:38; +#else + uint64_t addr:38; + uint64_t reserved_38_47:10; + uint64_t sid:5; + uint64_t reserved_53_57:5; + uint64_t cmd:6; +#endif + } cn66xx; + struct cvmx_l2c_err_xmc_s cn68xx; + struct cvmx_l2c_err_xmc_s cn68xxp1; + struct cvmx_l2c_err_xmc_cn61xx cnf71xx; }; union cvmx_l2c_grpwrr0 { uint64_t u64; struct cvmx_l2c_grpwrr0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t plc1rmsk:32; uint64_t plc0rmsk:32; +#else + uint64_t plc0rmsk:32; + uint64_t plc1rmsk:32; +#endif } s; struct cvmx_l2c_grpwrr0_s cn52xx; struct cvmx_l2c_grpwrr0_s cn52xxp1; @@ -638,8 +1384,13 @@ union cvmx_l2c_grpwrr0 { union cvmx_l2c_grpwrr1 { uint64_t u64; struct cvmx_l2c_grpwrr1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t ilcrmsk:32; uint64_t plc2rmsk:32; +#else + uint64_t plc2rmsk:32; + uint64_t ilcrmsk:32; +#endif } s; struct cvmx_l2c_grpwrr1_s cn52xx; struct cvmx_l2c_grpwrr1_s cn52xxp1; @@ -650,6 +1401,7 @@ union cvmx_l2c_grpwrr1 { union cvmx_l2c_int_en { uint64_t u64; struct cvmx_l2c_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t lck2ena:1; uint64_t lckena:1; @@ -660,6 +1412,18 @@ union cvmx_l2c_int_en { uint64_t oob3en:1; uint64_t oob2en:1; uint64_t oob1en:1; +#else + uint64_t oob1en:1; + uint64_t oob2en:1; + uint64_t oob3en:1; + uint64_t l2tsecen:1; + uint64_t l2tdeden:1; + uint64_t l2dsecen:1; + uint64_t l2ddeden:1; + uint64_t lckena:1; + uint64_t lck2ena:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_l2c_int_en_s cn52xx; struct cvmx_l2c_int_en_s cn52xxp1; @@ -670,6 +1434,7 @@ union cvmx_l2c_int_en { union cvmx_l2c_int_ena { uint64_t u64; struct cvmx_l2c_int_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t bigrd:1; uint64_t bigwr:1; @@ -679,9 +1444,22 @@ union cvmx_l2c_int_ena { uint64_t vrtwr:1; uint64_t holewr:1; uint64_t holerd:1; +#else + uint64_t holerd:1; + uint64_t holewr:1; + uint64_t vrtwr:1; + uint64_t vrtidrng:1; + uint64_t vrtadrng:1; + uint64_t vrtpe:1; + uint64_t bigwr:1; + uint64_t bigrd:1; + uint64_t reserved_8_63:56; +#endif } s; + struct cvmx_l2c_int_ena_s cn61xx; struct cvmx_l2c_int_ena_s cn63xx; struct cvmx_l2c_int_ena_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t vrtpe:1; uint64_t vrtadrng:1; @@ -689,13 +1467,30 @@ union cvmx_l2c_int_ena { uint64_t vrtwr:1; uint64_t holewr:1; uint64_t holerd:1; +#else + uint64_t holerd:1; + uint64_t holewr:1; + uint64_t vrtwr:1; + uint64_t vrtidrng:1; + uint64_t vrtadrng:1; + uint64_t vrtpe:1; + uint64_t reserved_6_63:58; +#endif } cn63xxp1; + struct cvmx_l2c_int_ena_s cn66xx; + struct cvmx_l2c_int_ena_s cn68xx; + struct cvmx_l2c_int_ena_s cn68xxp1; + struct cvmx_l2c_int_ena_s cnf71xx; }; union cvmx_l2c_int_reg { uint64_t u64; struct cvmx_l2c_int_reg_s { - uint64_t reserved_17_63:47; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t tad3:1; + uint64_t tad2:1; + uint64_t tad1:1; uint64_t tad0:1; uint64_t reserved_8_15:8; uint64_t bigrd:1; @@ -706,9 +1501,53 @@ union cvmx_l2c_int_reg { uint64_t vrtwr:1; uint64_t holewr:1; uint64_t holerd:1; +#else + uint64_t holerd:1; + uint64_t holewr:1; + uint64_t vrtwr:1; + uint64_t vrtidrng:1; + uint64_t vrtadrng:1; + uint64_t vrtpe:1; + uint64_t bigwr:1; + uint64_t bigrd:1; + uint64_t reserved_8_15:8; + uint64_t tad0:1; + uint64_t tad1:1; + uint64_t tad2:1; + uint64_t tad3:1; + uint64_t reserved_20_63:44; +#endif } s; - struct cvmx_l2c_int_reg_s cn63xx; + struct cvmx_l2c_int_reg_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_17_63:47; + uint64_t tad0:1; + uint64_t reserved_8_15:8; + uint64_t bigrd:1; + uint64_t bigwr:1; + uint64_t vrtpe:1; + uint64_t vrtadrng:1; + uint64_t vrtidrng:1; + uint64_t vrtwr:1; + uint64_t holewr:1; + uint64_t holerd:1; +#else + uint64_t holerd:1; + uint64_t holewr:1; + uint64_t vrtwr:1; + uint64_t vrtidrng:1; + uint64_t vrtadrng:1; + uint64_t vrtpe:1; + uint64_t bigwr:1; + uint64_t bigrd:1; + uint64_t reserved_8_15:8; + uint64_t tad0:1; + uint64_t reserved_17_63:47; +#endif + } cn61xx; + struct cvmx_l2c_int_reg_cn61xx cn63xx; struct cvmx_l2c_int_reg_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t tad0:1; uint64_t reserved_6_15:10; @@ -718,12 +1557,28 @@ union cvmx_l2c_int_reg { uint64_t vrtwr:1; uint64_t holewr:1; uint64_t holerd:1; +#else + uint64_t holerd:1; + uint64_t holewr:1; + uint64_t vrtwr:1; + uint64_t vrtidrng:1; + uint64_t vrtadrng:1; + uint64_t vrtpe:1; + uint64_t reserved_6_15:10; + uint64_t tad0:1; + uint64_t reserved_17_63:47; +#endif } cn63xxp1; + struct cvmx_l2c_int_reg_cn61xx cn66xx; + struct cvmx_l2c_int_reg_s cn68xx; + struct cvmx_l2c_int_reg_s cn68xxp1; + struct cvmx_l2c_int_reg_cn61xx cnf71xx; }; union cvmx_l2c_int_stat { uint64_t u64; struct cvmx_l2c_int_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t lck2:1; uint64_t lck:1; @@ -734,6 +1589,18 @@ union cvmx_l2c_int_stat { uint64_t oob3:1; uint64_t oob2:1; uint64_t oob1:1; +#else + uint64_t oob1:1; + uint64_t oob2:1; + uint64_t oob3:1; + uint64_t l2tsec:1; + uint64_t l2tded:1; + uint64_t l2dsec:1; + uint64_t l2dded:1; + uint64_t lck:1; + uint64_t lck2:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_l2c_int_stat_s cn52xx; struct cvmx_l2c_int_stat_s cn52xxp1; @@ -744,28 +1611,53 @@ union cvmx_l2c_int_stat { union cvmx_l2c_iocx_pfc { uint64_t u64; struct cvmx_l2c_iocx_pfc_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t count:64; +#else uint64_t count:64; +#endif } s; + struct cvmx_l2c_iocx_pfc_s cn61xx; struct cvmx_l2c_iocx_pfc_s cn63xx; struct cvmx_l2c_iocx_pfc_s cn63xxp1; + struct cvmx_l2c_iocx_pfc_s cn66xx; + struct cvmx_l2c_iocx_pfc_s cn68xx; + struct cvmx_l2c_iocx_pfc_s cn68xxp1; + struct cvmx_l2c_iocx_pfc_s cnf71xx; }; union cvmx_l2c_iorx_pfc { uint64_t u64; struct cvmx_l2c_iorx_pfc_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t count:64; +#else uint64_t count:64; +#endif } s; + struct cvmx_l2c_iorx_pfc_s cn61xx; struct cvmx_l2c_iorx_pfc_s cn63xx; struct cvmx_l2c_iorx_pfc_s cn63xxp1; + struct cvmx_l2c_iorx_pfc_s cn66xx; + struct cvmx_l2c_iorx_pfc_s cn68xx; + struct cvmx_l2c_iorx_pfc_s cn68xxp1; + struct cvmx_l2c_iorx_pfc_s cnf71xx; }; union cvmx_l2c_lckbase { uint64_t u64; struct cvmx_l2c_lckbase_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t lck_base:27; uint64_t reserved_1_3:3; uint64_t lck_ena:1; +#else + uint64_t lck_ena:1; + uint64_t reserved_1_3:3; + uint64_t lck_base:27; + uint64_t reserved_31_63:33; +#endif } s; struct cvmx_l2c_lckbase_s cn30xx; struct cvmx_l2c_lckbase_s cn31xx; @@ -783,8 +1675,13 @@ union cvmx_l2c_lckbase { union cvmx_l2c_lckoff { uint64_t u64; struct cvmx_l2c_lckoff_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t lck_offset:10; +#else + uint64_t lck_offset:10; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_l2c_lckoff_s cn30xx; struct cvmx_l2c_lckoff_s cn31xx; @@ -802,6 +1699,7 @@ union cvmx_l2c_lckoff { union cvmx_l2c_lfb0 { uint64_t u64; struct cvmx_l2c_lfb0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t stcpnd:1; uint64_t stpnd:1; @@ -816,8 +1714,25 @@ union cvmx_l2c_lfb0 { uint64_t sid:9; uint64_t cmd:4; uint64_t vld:1; +#else + uint64_t vld:1; + uint64_t cmd:4; + uint64_t sid:9; + uint64_t vabnum:4; + uint64_t set:3; + uint64_t ihd:1; + uint64_t itl:1; + uint64_t inxt:4; + uint64_t vam:1; + uint64_t stcfl:1; + uint64_t stinv:1; + uint64_t stpnd:1; + uint64_t stcpnd:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_l2c_lfb0_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t stcpnd:1; uint64_t stpnd:1; @@ -835,8 +1750,28 @@ union cvmx_l2c_lfb0 { uint64_t sid:9; uint64_t cmd:4; uint64_t vld:1; +#else + uint64_t vld:1; + uint64_t cmd:4; + uint64_t sid:9; + uint64_t vabnum:2; + uint64_t reserved_16_17:2; + uint64_t set:2; + uint64_t reserved_20_20:1; + uint64_t ihd:1; + uint64_t itl:1; + uint64_t inxt:2; + uint64_t reserved_25_26:2; + uint64_t vam:1; + uint64_t stcfl:1; + uint64_t stinv:1; + uint64_t stpnd:1; + uint64_t stcpnd:1; + uint64_t reserved_32_63:32; +#endif } cn30xx; struct cvmx_l2c_lfb0_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t stcpnd:1; uint64_t stpnd:1; @@ -854,10 +1789,30 @@ union cvmx_l2c_lfb0 { uint64_t sid:9; uint64_t cmd:4; uint64_t vld:1; +#else + uint64_t vld:1; + uint64_t cmd:4; + uint64_t sid:9; + uint64_t vabnum:3; + uint64_t reserved_17_17:1; + uint64_t set:2; + uint64_t reserved_20_20:1; + uint64_t ihd:1; + uint64_t itl:1; + uint64_t inxt:3; + uint64_t reserved_26_26:1; + uint64_t vam:1; + uint64_t stcfl:1; + uint64_t stinv:1; + uint64_t stpnd:1; + uint64_t stcpnd:1; + uint64_t reserved_32_63:32; +#endif } cn31xx; struct cvmx_l2c_lfb0_s cn38xx; struct cvmx_l2c_lfb0_s cn38xxp2; struct cvmx_l2c_lfb0_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t stcpnd:1; uint64_t stpnd:1; @@ -874,6 +1829,24 @@ union cvmx_l2c_lfb0 { uint64_t sid:9; uint64_t cmd:4; uint64_t vld:1; +#else + uint64_t vld:1; + uint64_t cmd:4; + uint64_t sid:9; + uint64_t vabnum:3; + uint64_t reserved_17_17:1; + uint64_t set:3; + uint64_t ihd:1; + uint64_t itl:1; + uint64_t inxt:3; + uint64_t reserved_26_26:1; + uint64_t vam:1; + uint64_t stcfl:1; + uint64_t stinv:1; + uint64_t stpnd:1; + uint64_t stcpnd:1; + uint64_t reserved_32_63:32; +#endif } cn50xx; struct cvmx_l2c_lfb0_cn50xx cn52xx; struct cvmx_l2c_lfb0_cn50xx cn52xxp1; @@ -886,6 +1859,7 @@ union cvmx_l2c_lfb0 { union cvmx_l2c_lfb1 { uint64_t u64; struct cvmx_l2c_lfb1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t dsgoing:1; uint64_t bid:2; @@ -905,6 +1879,27 @@ union cvmx_l2c_lfb1 { uint64_t prbrty:1; uint64_t wtprb:1; uint64_t vld:1; +#else + uint64_t vld:1; + uint64_t wtprb:1; + uint64_t prbrty:1; + uint64_t wtmfl:1; + uint64_t wtvtm:1; + uint64_t wtstrsc:1; + uint64_t wtstrsp:1; + uint64_t wtstdt:1; + uint64_t wtrda:1; + uint64_t wtstm:1; + uint64_t wtwrm:1; + uint64_t wtwhf:1; + uint64_t wtwhp:1; + uint64_t wtdq:1; + uint64_t wtdw:1; + uint64_t wtrsp:1; + uint64_t bid:2; + uint64_t dsgoing:1; + uint64_t reserved_19_63:45; +#endif } s; struct cvmx_l2c_lfb1_s cn30xx; struct cvmx_l2c_lfb1_s cn31xx; @@ -922,35 +1917,69 @@ union cvmx_l2c_lfb1 { union cvmx_l2c_lfb2 { uint64_t u64; struct cvmx_l2c_lfb2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif } s; struct cvmx_l2c_lfb2_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t lfb_tag:19; uint64_t lfb_idx:8; +#else + uint64_t lfb_idx:8; + uint64_t lfb_tag:19; + uint64_t reserved_27_63:37; +#endif } cn30xx; struct cvmx_l2c_lfb2_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t lfb_tag:17; uint64_t lfb_idx:10; +#else + uint64_t lfb_idx:10; + uint64_t lfb_tag:17; + uint64_t reserved_27_63:37; +#endif } cn31xx; struct cvmx_l2c_lfb2_cn31xx cn38xx; struct cvmx_l2c_lfb2_cn31xx cn38xxp2; struct cvmx_l2c_lfb2_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t lfb_tag:20; uint64_t lfb_idx:7; +#else + uint64_t lfb_idx:7; + uint64_t lfb_tag:20; + uint64_t reserved_27_63:37; +#endif } cn50xx; struct cvmx_l2c_lfb2_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t lfb_tag:18; uint64_t lfb_idx:9; +#else + uint64_t lfb_idx:9; + uint64_t lfb_tag:18; + uint64_t reserved_27_63:37; +#endif } cn52xx; struct cvmx_l2c_lfb2_cn52xx cn52xxp1; struct cvmx_l2c_lfb2_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t lfb_tag:16; uint64_t lfb_idx:11; +#else + uint64_t lfb_idx:11; + uint64_t lfb_tag:16; + uint64_t reserved_27_63:37; +#endif } cn56xx; struct cvmx_l2c_lfb2_cn56xx cn56xxp1; struct cvmx_l2c_lfb2_cn56xx cn58xx; @@ -960,21 +1989,41 @@ union cvmx_l2c_lfb2 { union cvmx_l2c_lfb3 { uint64_t u64; struct cvmx_l2c_lfb3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t stpartdis:1; uint64_t lfb_hwm:4; +#else + uint64_t lfb_hwm:4; + uint64_t stpartdis:1; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_l2c_lfb3_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t stpartdis:1; uint64_t reserved_2_3:2; uint64_t lfb_hwm:2; +#else + uint64_t lfb_hwm:2; + uint64_t reserved_2_3:2; + uint64_t stpartdis:1; + uint64_t reserved_5_63:59; +#endif } cn30xx; struct cvmx_l2c_lfb3_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t stpartdis:1; uint64_t reserved_3_3:1; uint64_t lfb_hwm:3; +#else + uint64_t lfb_hwm:3; + uint64_t reserved_3_3:1; + uint64_t stpartdis:1; + uint64_t reserved_5_63:59; +#endif } cn31xx; struct cvmx_l2c_lfb3_s cn38xx; struct cvmx_l2c_lfb3_s cn38xxp2; @@ -990,9 +2039,15 @@ union cvmx_l2c_lfb3 { union cvmx_l2c_oob { uint64_t u64; struct cvmx_l2c_oob_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dwbena:1; uint64_t stena:1; +#else + uint64_t stena:1; + uint64_t dwbena:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_l2c_oob_s cn52xx; struct cvmx_l2c_oob_s cn52xxp1; @@ -1003,12 +2058,21 @@ union cvmx_l2c_oob { union cvmx_l2c_oob1 { uint64_t u64; struct cvmx_l2c_oob1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t fadr:27; uint64_t fsrc:1; uint64_t reserved_34_35:2; uint64_t sadr:14; uint64_t reserved_14_19:6; uint64_t size:14; +#else + uint64_t size:14; + uint64_t reserved_14_19:6; + uint64_t sadr:14; + uint64_t reserved_34_35:2; + uint64_t fsrc:1; + uint64_t fadr:27; +#endif } s; struct cvmx_l2c_oob1_s cn52xx; struct cvmx_l2c_oob1_s cn52xxp1; @@ -1019,12 +2083,21 @@ union cvmx_l2c_oob1 { union cvmx_l2c_oob2 { uint64_t u64; struct cvmx_l2c_oob2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t fadr:27; uint64_t fsrc:1; uint64_t reserved_34_35:2; uint64_t sadr:14; uint64_t reserved_14_19:6; uint64_t size:14; +#else + uint64_t size:14; + uint64_t reserved_14_19:6; + uint64_t sadr:14; + uint64_t reserved_34_35:2; + uint64_t fsrc:1; + uint64_t fadr:27; +#endif } s; struct cvmx_l2c_oob2_s cn52xx; struct cvmx_l2c_oob2_s cn52xxp1; @@ -1035,12 +2108,21 @@ union cvmx_l2c_oob2 { union cvmx_l2c_oob3 { uint64_t u64; struct cvmx_l2c_oob3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t fadr:27; uint64_t fsrc:1; uint64_t reserved_34_35:2; uint64_t sadr:14; uint64_t reserved_14_19:6; uint64_t size:14; +#else + uint64_t size:14; + uint64_t reserved_14_19:6; + uint64_t sadr:14; + uint64_t reserved_34_35:2; + uint64_t fsrc:1; + uint64_t fadr:27; +#endif } s; struct cvmx_l2c_oob3_s cn52xx; struct cvmx_l2c_oob3_s cn52xxp1; @@ -1051,8 +2133,13 @@ union cvmx_l2c_oob3 { union cvmx_l2c_pfcx { uint64_t u64; struct cvmx_l2c_pfcx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t pfcnt0:36; +#else + uint64_t pfcnt0:36; + uint64_t reserved_36_63:28; +#endif } s; struct cvmx_l2c_pfcx_s cn30xx; struct cvmx_l2c_pfcx_s cn31xx; @@ -1070,6 +2157,7 @@ union cvmx_l2c_pfcx { union cvmx_l2c_pfctl { uint64_t u64; struct cvmx_l2c_pfctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t cnt3rdclr:1; uint64_t cnt2rdclr:1; @@ -1087,6 +2175,25 @@ union cvmx_l2c_pfctl { uint64_t cnt0ena:1; uint64_t cnt0clr:1; uint64_t cnt0sel:6; +#else + uint64_t cnt0sel:6; + uint64_t cnt0clr:1; + uint64_t cnt0ena:1; + uint64_t cnt1sel:6; + uint64_t cnt1clr:1; + uint64_t cnt1ena:1; + uint64_t cnt2sel:6; + uint64_t cnt2clr:1; + uint64_t cnt2ena:1; + uint64_t cnt3sel:6; + uint64_t cnt3clr:1; + uint64_t cnt3ena:1; + uint64_t cnt0rdclr:1; + uint64_t cnt1rdclr:1; + uint64_t cnt2rdclr:1; + uint64_t cnt3rdclr:1; + uint64_t reserved_36_63:28; +#endif } s; struct cvmx_l2c_pfctl_s cn30xx; struct cvmx_l2c_pfctl_s cn31xx; @@ -1104,6 +2211,7 @@ union cvmx_l2c_pfctl { union cvmx_l2c_ppgrp { uint64_t u64; struct cvmx_l2c_ppgrp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t pp11grp:2; uint64_t pp10grp:2; @@ -1117,13 +2225,36 @@ union cvmx_l2c_ppgrp { uint64_t pp2grp:2; uint64_t pp1grp:2; uint64_t pp0grp:2; +#else + uint64_t pp0grp:2; + uint64_t pp1grp:2; + uint64_t pp2grp:2; + uint64_t pp3grp:2; + uint64_t pp4grp:2; + uint64_t pp5grp:2; + uint64_t pp6grp:2; + uint64_t pp7grp:2; + uint64_t pp8grp:2; + uint64_t pp9grp:2; + uint64_t pp10grp:2; + uint64_t pp11grp:2; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_l2c_ppgrp_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t pp3grp:2; uint64_t pp2grp:2; uint64_t pp1grp:2; uint64_t pp0grp:2; +#else + uint64_t pp0grp:2; + uint64_t pp1grp:2; + uint64_t pp2grp:2; + uint64_t pp3grp:2; + uint64_t reserved_8_63:56; +#endif } cn52xx; struct cvmx_l2c_ppgrp_cn52xx cn52xxp1; struct cvmx_l2c_ppgrp_s cn56xx; @@ -1133,81 +2264,200 @@ union cvmx_l2c_ppgrp { union cvmx_l2c_qos_iobx { uint64_t u64; struct cvmx_l2c_qos_iobx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t dwblvl:3; + uint64_t reserved_3_3:1; + uint64_t lvl:3; +#else + uint64_t lvl:3; + uint64_t reserved_3_3:1; + uint64_t dwblvl:3; + uint64_t reserved_7_63:57; +#endif + } s; + struct cvmx_l2c_qos_iobx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t dwblvl:2; uint64_t reserved_2_3:2; uint64_t lvl:2; - } s; - struct cvmx_l2c_qos_iobx_s cn63xx; - struct cvmx_l2c_qos_iobx_s cn63xxp1; +#else + uint64_t lvl:2; + uint64_t reserved_2_3:2; + uint64_t dwblvl:2; + uint64_t reserved_6_63:58; +#endif + } cn61xx; + struct cvmx_l2c_qos_iobx_cn61xx cn63xx; + struct cvmx_l2c_qos_iobx_cn61xx cn63xxp1; + struct cvmx_l2c_qos_iobx_cn61xx cn66xx; + struct cvmx_l2c_qos_iobx_s cn68xx; + struct cvmx_l2c_qos_iobx_s cn68xxp1; + struct cvmx_l2c_qos_iobx_cn61xx cnf71xx; }; union cvmx_l2c_qos_ppx { uint64_t u64; struct cvmx_l2c_qos_ppx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_3_63:61; + uint64_t lvl:3; +#else + uint64_t lvl:3; + uint64_t reserved_3_63:61; +#endif + } s; + struct cvmx_l2c_qos_ppx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t lvl:2; - } s; - struct cvmx_l2c_qos_ppx_s cn63xx; - struct cvmx_l2c_qos_ppx_s cn63xxp1; +#else + uint64_t lvl:2; + uint64_t reserved_2_63:62; +#endif + } cn61xx; + struct cvmx_l2c_qos_ppx_cn61xx cn63xx; + struct cvmx_l2c_qos_ppx_cn61xx cn63xxp1; + struct cvmx_l2c_qos_ppx_cn61xx cn66xx; + struct cvmx_l2c_qos_ppx_s cn68xx; + struct cvmx_l2c_qos_ppx_s cn68xxp1; + struct cvmx_l2c_qos_ppx_cn61xx cnf71xx; }; union cvmx_l2c_qos_wgt { uint64_t u64; struct cvmx_l2c_qos_wgt_s { - uint64_t reserved_32_63:32; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t wgt7:8; + uint64_t wgt6:8; + uint64_t wgt5:8; + uint64_t wgt4:8; uint64_t wgt3:8; uint64_t wgt2:8; uint64_t wgt1:8; uint64_t wgt0:8; +#else + uint64_t wgt0:8; + uint64_t wgt1:8; + uint64_t wgt2:8; + uint64_t wgt3:8; + uint64_t wgt4:8; + uint64_t wgt5:8; + uint64_t wgt6:8; + uint64_t wgt7:8; +#endif } s; - struct cvmx_l2c_qos_wgt_s cn63xx; - struct cvmx_l2c_qos_wgt_s cn63xxp1; + struct cvmx_l2c_qos_wgt_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wgt3:8; + uint64_t wgt2:8; + uint64_t wgt1:8; + uint64_t wgt0:8; +#else + uint64_t wgt0:8; + uint64_t wgt1:8; + uint64_t wgt2:8; + uint64_t wgt3:8; + uint64_t reserved_32_63:32; +#endif + } cn61xx; + struct cvmx_l2c_qos_wgt_cn61xx cn63xx; + struct cvmx_l2c_qos_wgt_cn61xx cn63xxp1; + struct cvmx_l2c_qos_wgt_cn61xx cn66xx; + struct cvmx_l2c_qos_wgt_s cn68xx; + struct cvmx_l2c_qos_wgt_s cn68xxp1; + struct cvmx_l2c_qos_wgt_cn61xx cnf71xx; }; union cvmx_l2c_rscx_pfc { uint64_t u64; struct cvmx_l2c_rscx_pfc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; +#else + uint64_t count:64; +#endif } s; + struct cvmx_l2c_rscx_pfc_s cn61xx; struct cvmx_l2c_rscx_pfc_s cn63xx; struct cvmx_l2c_rscx_pfc_s cn63xxp1; + struct cvmx_l2c_rscx_pfc_s cn66xx; + struct cvmx_l2c_rscx_pfc_s cn68xx; + struct cvmx_l2c_rscx_pfc_s cn68xxp1; + struct cvmx_l2c_rscx_pfc_s cnf71xx; }; union cvmx_l2c_rsdx_pfc { uint64_t u64; struct cvmx_l2c_rsdx_pfc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; +#else + uint64_t count:64; +#endif } s; + struct cvmx_l2c_rsdx_pfc_s cn61xx; struct cvmx_l2c_rsdx_pfc_s cn63xx; struct cvmx_l2c_rsdx_pfc_s cn63xxp1; + struct cvmx_l2c_rsdx_pfc_s cn66xx; + struct cvmx_l2c_rsdx_pfc_s cn68xx; + struct cvmx_l2c_rsdx_pfc_s cn68xxp1; + struct cvmx_l2c_rsdx_pfc_s cnf71xx; }; union cvmx_l2c_spar0 { uint64_t u64; struct cvmx_l2c_spar0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t umsk3:8; uint64_t umsk2:8; uint64_t umsk1:8; uint64_t umsk0:8; +#else + uint64_t umsk0:8; + uint64_t umsk1:8; + uint64_t umsk2:8; + uint64_t umsk3:8; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_l2c_spar0_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t umsk0:4; +#else + uint64_t umsk0:4; + uint64_t reserved_4_63:60; +#endif } cn30xx; struct cvmx_l2c_spar0_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t umsk1:4; uint64_t reserved_4_7:4; uint64_t umsk0:4; +#else + uint64_t umsk0:4; + uint64_t reserved_4_7:4; + uint64_t umsk1:4; + uint64_t reserved_12_63:52; +#endif } cn31xx; struct cvmx_l2c_spar0_s cn38xx; struct cvmx_l2c_spar0_s cn38xxp2; struct cvmx_l2c_spar0_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t umsk1:8; uint64_t umsk0:8; +#else + uint64_t umsk0:8; + uint64_t umsk1:8; + uint64_t reserved_16_63:48; +#endif } cn50xx; struct cvmx_l2c_spar0_s cn52xx; struct cvmx_l2c_spar0_s cn52xxp1; @@ -1220,11 +2470,19 @@ union cvmx_l2c_spar0 { union cvmx_l2c_spar1 { uint64_t u64; struct cvmx_l2c_spar1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t umsk7:8; uint64_t umsk6:8; uint64_t umsk5:8; uint64_t umsk4:8; +#else + uint64_t umsk4:8; + uint64_t umsk5:8; + uint64_t umsk6:8; + uint64_t umsk7:8; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_l2c_spar1_s cn38xx; struct cvmx_l2c_spar1_s cn38xxp2; @@ -1237,11 +2495,19 @@ union cvmx_l2c_spar1 { union cvmx_l2c_spar2 { uint64_t u64; struct cvmx_l2c_spar2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t umsk11:8; uint64_t umsk10:8; uint64_t umsk9:8; uint64_t umsk8:8; +#else + uint64_t umsk8:8; + uint64_t umsk9:8; + uint64_t umsk10:8; + uint64_t umsk11:8; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_l2c_spar2_s cn38xx; struct cvmx_l2c_spar2_s cn38xxp2; @@ -1254,11 +2520,19 @@ union cvmx_l2c_spar2 { union cvmx_l2c_spar3 { uint64_t u64; struct cvmx_l2c_spar3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t umsk15:8; uint64_t umsk14:8; uint64_t umsk13:8; uint64_t umsk12:8; +#else + uint64_t umsk12:8; + uint64_t umsk13:8; + uint64_t umsk14:8; + uint64_t umsk15:8; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_l2c_spar3_s cn38xx; struct cvmx_l2c_spar3_s cn38xxp2; @@ -1269,12 +2543,22 @@ union cvmx_l2c_spar3 { union cvmx_l2c_spar4 { uint64_t u64; struct cvmx_l2c_spar4_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t umskiob:8; +#else + uint64_t umskiob:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_l2c_spar4_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t umskiob:4; +#else + uint64_t umskiob:4; + uint64_t reserved_4_63:60; +#endif } cn30xx; struct cvmx_l2c_spar4_cn30xx cn31xx; struct cvmx_l2c_spar4_s cn38xx; @@ -1291,6 +2575,7 @@ union cvmx_l2c_spar4 { union cvmx_l2c_tadx_ecc0 { uint64_t u64; struct cvmx_l2c_tadx_ecc0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t ow3ecc:10; uint64_t reserved_42_47:6; @@ -1299,14 +2584,30 @@ union cvmx_l2c_tadx_ecc0 { uint64_t ow1ecc:10; uint64_t reserved_10_15:6; uint64_t ow0ecc:10; +#else + uint64_t ow0ecc:10; + uint64_t reserved_10_15:6; + uint64_t ow1ecc:10; + uint64_t reserved_26_31:6; + uint64_t ow2ecc:10; + uint64_t reserved_42_47:6; + uint64_t ow3ecc:10; + uint64_t reserved_58_63:6; +#endif } s; + struct cvmx_l2c_tadx_ecc0_s cn61xx; struct cvmx_l2c_tadx_ecc0_s cn63xx; struct cvmx_l2c_tadx_ecc0_s cn63xxp1; + struct cvmx_l2c_tadx_ecc0_s cn66xx; + struct cvmx_l2c_tadx_ecc0_s cn68xx; + struct cvmx_l2c_tadx_ecc0_s cn68xxp1; + struct cvmx_l2c_tadx_ecc0_s cnf71xx; }; union cvmx_l2c_tadx_ecc1 { uint64_t u64; struct cvmx_l2c_tadx_ecc1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t ow7ecc:10; uint64_t reserved_42_47:6; @@ -1315,14 +2616,30 @@ union cvmx_l2c_tadx_ecc1 { uint64_t ow5ecc:10; uint64_t reserved_10_15:6; uint64_t ow4ecc:10; +#else + uint64_t ow4ecc:10; + uint64_t reserved_10_15:6; + uint64_t ow5ecc:10; + uint64_t reserved_26_31:6; + uint64_t ow6ecc:10; + uint64_t reserved_42_47:6; + uint64_t ow7ecc:10; + uint64_t reserved_58_63:6; +#endif } s; + struct cvmx_l2c_tadx_ecc1_s cn61xx; struct cvmx_l2c_tadx_ecc1_s cn63xx; struct cvmx_l2c_tadx_ecc1_s cn63xxp1; + struct cvmx_l2c_tadx_ecc1_s cn66xx; + struct cvmx_l2c_tadx_ecc1_s cn68xx; + struct cvmx_l2c_tadx_ecc1_s cn68xxp1; + struct cvmx_l2c_tadx_ecc1_s cnf71xx; }; union cvmx_l2c_tadx_ien { uint64_t u64; struct cvmx_l2c_tadx_ien_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t wrdislmc:1; uint64_t rddislmc:1; @@ -1333,9 +2650,23 @@ union cvmx_l2c_tadx_ien { uint64_t tagsbe:1; uint64_t l2ddbe:1; uint64_t l2dsbe:1; +#else + uint64_t l2dsbe:1; + uint64_t l2ddbe:1; + uint64_t tagsbe:1; + uint64_t tagdbe:1; + uint64_t vbfsbe:1; + uint64_t vbfdbe:1; + uint64_t noway:1; + uint64_t rddislmc:1; + uint64_t wrdislmc:1; + uint64_t reserved_9_63:55; +#endif } s; + struct cvmx_l2c_tadx_ien_s cn61xx; struct cvmx_l2c_tadx_ien_s cn63xx; struct cvmx_l2c_tadx_ien_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t noway:1; uint64_t vbfdbe:1; @@ -1344,12 +2675,27 @@ union cvmx_l2c_tadx_ien { uint64_t tagsbe:1; uint64_t l2ddbe:1; uint64_t l2dsbe:1; +#else + uint64_t l2dsbe:1; + uint64_t l2ddbe:1; + uint64_t tagsbe:1; + uint64_t tagdbe:1; + uint64_t vbfsbe:1; + uint64_t vbfdbe:1; + uint64_t noway:1; + uint64_t reserved_7_63:57; +#endif } cn63xxp1; + struct cvmx_l2c_tadx_ien_s cn66xx; + struct cvmx_l2c_tadx_ien_s cn68xx; + struct cvmx_l2c_tadx_ien_s cn68xxp1; + struct cvmx_l2c_tadx_ien_s cnf71xx; }; union cvmx_l2c_tadx_int { uint64_t u64; struct cvmx_l2c_tadx_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t wrdislmc:1; uint64_t rddislmc:1; @@ -1360,62 +2706,129 @@ union cvmx_l2c_tadx_int { uint64_t tagsbe:1; uint64_t l2ddbe:1; uint64_t l2dsbe:1; +#else + uint64_t l2dsbe:1; + uint64_t l2ddbe:1; + uint64_t tagsbe:1; + uint64_t tagdbe:1; + uint64_t vbfsbe:1; + uint64_t vbfdbe:1; + uint64_t noway:1; + uint64_t rddislmc:1; + uint64_t wrdislmc:1; + uint64_t reserved_9_63:55; +#endif } s; + struct cvmx_l2c_tadx_int_s cn61xx; struct cvmx_l2c_tadx_int_s cn63xx; + struct cvmx_l2c_tadx_int_s cn66xx; + struct cvmx_l2c_tadx_int_s cn68xx; + struct cvmx_l2c_tadx_int_s cn68xxp1; + struct cvmx_l2c_tadx_int_s cnf71xx; }; union cvmx_l2c_tadx_pfc0 { uint64_t u64; struct cvmx_l2c_tadx_pfc0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; +#else + uint64_t count:64; +#endif } s; + struct cvmx_l2c_tadx_pfc0_s cn61xx; struct cvmx_l2c_tadx_pfc0_s cn63xx; struct cvmx_l2c_tadx_pfc0_s cn63xxp1; + struct cvmx_l2c_tadx_pfc0_s cn66xx; + struct cvmx_l2c_tadx_pfc0_s cn68xx; + struct cvmx_l2c_tadx_pfc0_s cn68xxp1; + struct cvmx_l2c_tadx_pfc0_s cnf71xx; }; union cvmx_l2c_tadx_pfc1 { uint64_t u64; struct cvmx_l2c_tadx_pfc1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; +#else + uint64_t count:64; +#endif } s; + struct cvmx_l2c_tadx_pfc1_s cn61xx; struct cvmx_l2c_tadx_pfc1_s cn63xx; struct cvmx_l2c_tadx_pfc1_s cn63xxp1; + struct cvmx_l2c_tadx_pfc1_s cn66xx; + struct cvmx_l2c_tadx_pfc1_s cn68xx; + struct cvmx_l2c_tadx_pfc1_s cn68xxp1; + struct cvmx_l2c_tadx_pfc1_s cnf71xx; }; union cvmx_l2c_tadx_pfc2 { uint64_t u64; struct cvmx_l2c_tadx_pfc2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; +#else + uint64_t count:64; +#endif } s; + struct cvmx_l2c_tadx_pfc2_s cn61xx; struct cvmx_l2c_tadx_pfc2_s cn63xx; struct cvmx_l2c_tadx_pfc2_s cn63xxp1; + struct cvmx_l2c_tadx_pfc2_s cn66xx; + struct cvmx_l2c_tadx_pfc2_s cn68xx; + struct cvmx_l2c_tadx_pfc2_s cn68xxp1; + struct cvmx_l2c_tadx_pfc2_s cnf71xx; }; union cvmx_l2c_tadx_pfc3 { uint64_t u64; struct cvmx_l2c_tadx_pfc3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; +#else + uint64_t count:64; +#endif } s; + struct cvmx_l2c_tadx_pfc3_s cn61xx; struct cvmx_l2c_tadx_pfc3_s cn63xx; struct cvmx_l2c_tadx_pfc3_s cn63xxp1; + struct cvmx_l2c_tadx_pfc3_s cn66xx; + struct cvmx_l2c_tadx_pfc3_s cn68xx; + struct cvmx_l2c_tadx_pfc3_s cn68xxp1; + struct cvmx_l2c_tadx_pfc3_s cnf71xx; }; union cvmx_l2c_tadx_prf { uint64_t u64; struct cvmx_l2c_tadx_prf_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt3sel:8; uint64_t cnt2sel:8; uint64_t cnt1sel:8; uint64_t cnt0sel:8; +#else + uint64_t cnt0sel:8; + uint64_t cnt1sel:8; + uint64_t cnt2sel:8; + uint64_t cnt3sel:8; + uint64_t reserved_32_63:32; +#endif } s; + struct cvmx_l2c_tadx_prf_s cn61xx; struct cvmx_l2c_tadx_prf_s cn63xx; struct cvmx_l2c_tadx_prf_s cn63xxp1; + struct cvmx_l2c_tadx_prf_s cn66xx; + struct cvmx_l2c_tadx_prf_s cn68xx; + struct cvmx_l2c_tadx_prf_s cn68xxp1; + struct cvmx_l2c_tadx_prf_s cnf71xx; }; union cvmx_l2c_tadx_tag { uint64_t u64; struct cvmx_l2c_tadx_tag_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_46_63:18; uint64_t ecc:6; uint64_t reserved_36_39:4; @@ -1425,145 +2838,330 @@ union cvmx_l2c_tadx_tag { uint64_t valid:1; uint64_t dirty:1; uint64_t lock:1; +#else + uint64_t lock:1; + uint64_t dirty:1; + uint64_t valid:1; + uint64_t use:1; + uint64_t reserved_4_16:13; + uint64_t tag:19; + uint64_t reserved_36_39:4; + uint64_t ecc:6; + uint64_t reserved_46_63:18; +#endif } s; + struct cvmx_l2c_tadx_tag_s cn61xx; struct cvmx_l2c_tadx_tag_s cn63xx; struct cvmx_l2c_tadx_tag_s cn63xxp1; + struct cvmx_l2c_tadx_tag_s cn66xx; + struct cvmx_l2c_tadx_tag_s cn68xx; + struct cvmx_l2c_tadx_tag_s cn68xxp1; + struct cvmx_l2c_tadx_tag_s cnf71xx; }; union cvmx_l2c_ver_id { uint64_t u64; struct cvmx_l2c_ver_id_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mask:64; +#else + uint64_t mask:64; +#endif } s; + struct cvmx_l2c_ver_id_s cn61xx; struct cvmx_l2c_ver_id_s cn63xx; struct cvmx_l2c_ver_id_s cn63xxp1; + struct cvmx_l2c_ver_id_s cn66xx; + struct cvmx_l2c_ver_id_s cn68xx; + struct cvmx_l2c_ver_id_s cn68xxp1; + struct cvmx_l2c_ver_id_s cnf71xx; }; union cvmx_l2c_ver_iob { uint64_t u64; struct cvmx_l2c_ver_iob_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_2_63:62; + uint64_t mask:2; +#else + uint64_t mask:2; + uint64_t reserved_2_63:62; +#endif + } s; + struct cvmx_l2c_ver_iob_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t mask:1; - } s; - struct cvmx_l2c_ver_iob_s cn63xx; - struct cvmx_l2c_ver_iob_s cn63xxp1; +#else + uint64_t mask:1; + uint64_t reserved_1_63:63; +#endif + } cn61xx; + struct cvmx_l2c_ver_iob_cn61xx cn63xx; + struct cvmx_l2c_ver_iob_cn61xx cn63xxp1; + struct cvmx_l2c_ver_iob_cn61xx cn66xx; + struct cvmx_l2c_ver_iob_s cn68xx; + struct cvmx_l2c_ver_iob_s cn68xxp1; + struct cvmx_l2c_ver_iob_cn61xx cnf71xx; }; union cvmx_l2c_ver_msc { uint64_t u64; struct cvmx_l2c_ver_msc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t invl2:1; uint64_t dwb:1; +#else + uint64_t dwb:1; + uint64_t invl2:1; + uint64_t reserved_2_63:62; +#endif } s; + struct cvmx_l2c_ver_msc_s cn61xx; struct cvmx_l2c_ver_msc_s cn63xx; + struct cvmx_l2c_ver_msc_s cn66xx; + struct cvmx_l2c_ver_msc_s cn68xx; + struct cvmx_l2c_ver_msc_s cn68xxp1; + struct cvmx_l2c_ver_msc_s cnf71xx; }; union cvmx_l2c_ver_pp { uint64_t u64; struct cvmx_l2c_ver_pp_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t mask:32; +#else + uint64_t mask:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_l2c_ver_pp_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t mask:4; +#else + uint64_t mask:4; + uint64_t reserved_4_63:60; +#endif + } cn61xx; + struct cvmx_l2c_ver_pp_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mask:6; - } s; - struct cvmx_l2c_ver_pp_s cn63xx; - struct cvmx_l2c_ver_pp_s cn63xxp1; +#else + uint64_t mask:6; + uint64_t reserved_6_63:58; +#endif + } cn63xx; + struct cvmx_l2c_ver_pp_cn63xx cn63xxp1; + struct cvmx_l2c_ver_pp_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t mask:10; +#else + uint64_t mask:10; + uint64_t reserved_10_63:54; +#endif + } cn66xx; + struct cvmx_l2c_ver_pp_s cn68xx; + struct cvmx_l2c_ver_pp_s cn68xxp1; + struct cvmx_l2c_ver_pp_cn61xx cnf71xx; }; union cvmx_l2c_virtid_iobx { uint64_t u64; struct cvmx_l2c_virtid_iobx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t dwbid:6; uint64_t reserved_6_7:2; uint64_t id:6; +#else + uint64_t id:6; + uint64_t reserved_6_7:2; + uint64_t dwbid:6; + uint64_t reserved_14_63:50; +#endif } s; + struct cvmx_l2c_virtid_iobx_s cn61xx; struct cvmx_l2c_virtid_iobx_s cn63xx; struct cvmx_l2c_virtid_iobx_s cn63xxp1; + struct cvmx_l2c_virtid_iobx_s cn66xx; + struct cvmx_l2c_virtid_iobx_s cn68xx; + struct cvmx_l2c_virtid_iobx_s cn68xxp1; + struct cvmx_l2c_virtid_iobx_s cnf71xx; }; union cvmx_l2c_virtid_ppx { uint64_t u64; struct cvmx_l2c_virtid_ppx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t id:6; +#else + uint64_t id:6; + uint64_t reserved_6_63:58; +#endif } s; + struct cvmx_l2c_virtid_ppx_s cn61xx; struct cvmx_l2c_virtid_ppx_s cn63xx; struct cvmx_l2c_virtid_ppx_s cn63xxp1; + struct cvmx_l2c_virtid_ppx_s cn66xx; + struct cvmx_l2c_virtid_ppx_s cn68xx; + struct cvmx_l2c_virtid_ppx_s cn68xxp1; + struct cvmx_l2c_virtid_ppx_s cnf71xx; }; union cvmx_l2c_vrt_ctl { uint64_t u64; struct cvmx_l2c_vrt_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t ooberr:1; uint64_t reserved_7_7:1; uint64_t memsz:3; uint64_t numid:3; uint64_t enable:1; +#else + uint64_t enable:1; + uint64_t numid:3; + uint64_t memsz:3; + uint64_t reserved_7_7:1; + uint64_t ooberr:1; + uint64_t reserved_9_63:55; +#endif } s; + struct cvmx_l2c_vrt_ctl_s cn61xx; struct cvmx_l2c_vrt_ctl_s cn63xx; struct cvmx_l2c_vrt_ctl_s cn63xxp1; + struct cvmx_l2c_vrt_ctl_s cn66xx; + struct cvmx_l2c_vrt_ctl_s cn68xx; + struct cvmx_l2c_vrt_ctl_s cn68xxp1; + struct cvmx_l2c_vrt_ctl_s cnf71xx; }; union cvmx_l2c_vrt_memx { uint64_t u64; struct cvmx_l2c_vrt_memx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t parity:4; uint64_t data:32; +#else + uint64_t data:32; + uint64_t parity:4; + uint64_t reserved_36_63:28; +#endif } s; + struct cvmx_l2c_vrt_memx_s cn61xx; struct cvmx_l2c_vrt_memx_s cn63xx; struct cvmx_l2c_vrt_memx_s cn63xxp1; + struct cvmx_l2c_vrt_memx_s cn66xx; + struct cvmx_l2c_vrt_memx_s cn68xx; + struct cvmx_l2c_vrt_memx_s cn68xxp1; + struct cvmx_l2c_vrt_memx_s cnf71xx; }; union cvmx_l2c_wpar_iobx { uint64_t u64; struct cvmx_l2c_wpar_iobx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mask:16; +#else + uint64_t mask:16; + uint64_t reserved_16_63:48; +#endif } s; + struct cvmx_l2c_wpar_iobx_s cn61xx; struct cvmx_l2c_wpar_iobx_s cn63xx; struct cvmx_l2c_wpar_iobx_s cn63xxp1; + struct cvmx_l2c_wpar_iobx_s cn66xx; + struct cvmx_l2c_wpar_iobx_s cn68xx; + struct cvmx_l2c_wpar_iobx_s cn68xxp1; + struct cvmx_l2c_wpar_iobx_s cnf71xx; }; union cvmx_l2c_wpar_ppx { uint64_t u64; struct cvmx_l2c_wpar_ppx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mask:16; +#else + uint64_t mask:16; + uint64_t reserved_16_63:48; +#endif } s; + struct cvmx_l2c_wpar_ppx_s cn61xx; struct cvmx_l2c_wpar_ppx_s cn63xx; struct cvmx_l2c_wpar_ppx_s cn63xxp1; + struct cvmx_l2c_wpar_ppx_s cn66xx; + struct cvmx_l2c_wpar_ppx_s cn68xx; + struct cvmx_l2c_wpar_ppx_s cn68xxp1; + struct cvmx_l2c_wpar_ppx_s cnf71xx; }; union cvmx_l2c_xmcx_pfc { uint64_t u64; struct cvmx_l2c_xmcx_pfc_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t count:64; +#else uint64_t count:64; +#endif } s; + struct cvmx_l2c_xmcx_pfc_s cn61xx; struct cvmx_l2c_xmcx_pfc_s cn63xx; struct cvmx_l2c_xmcx_pfc_s cn63xxp1; + struct cvmx_l2c_xmcx_pfc_s cn66xx; + struct cvmx_l2c_xmcx_pfc_s cn68xx; + struct cvmx_l2c_xmcx_pfc_s cn68xxp1; + struct cvmx_l2c_xmcx_pfc_s cnf71xx; }; union cvmx_l2c_xmc_cmd { uint64_t u64; struct cvmx_l2c_xmc_cmd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t inuse:1; uint64_t cmd:6; uint64_t reserved_38_56:19; uint64_t addr:38; +#else + uint64_t addr:38; + uint64_t reserved_38_56:19; + uint64_t cmd:6; + uint64_t inuse:1; +#endif } s; + struct cvmx_l2c_xmc_cmd_s cn61xx; struct cvmx_l2c_xmc_cmd_s cn63xx; struct cvmx_l2c_xmc_cmd_s cn63xxp1; + struct cvmx_l2c_xmc_cmd_s cn66xx; + struct cvmx_l2c_xmc_cmd_s cn68xx; + struct cvmx_l2c_xmc_cmd_s cn68xxp1; + struct cvmx_l2c_xmc_cmd_s cnf71xx; }; union cvmx_l2c_xmdx_pfc { uint64_t u64; struct cvmx_l2c_xmdx_pfc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t count:64; +#else + uint64_t count:64; +#endif } s; + struct cvmx_l2c_xmdx_pfc_s cn61xx; struct cvmx_l2c_xmdx_pfc_s cn63xx; struct cvmx_l2c_xmdx_pfc_s cn63xxp1; + struct cvmx_l2c_xmdx_pfc_s cn66xx; + struct cvmx_l2c_xmdx_pfc_s cn68xx; + struct cvmx_l2c_xmdx_pfc_s cn68xxp1; + struct cvmx_l2c_xmdx_pfc_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h index 2c8ff9e33ec..11c0a8fa8eb 100644 --- a/arch/mips/include/asm/octeon/cvmx-l2c.h +++ b/arch/mips/include/asm/octeon/cvmx-l2c.h @@ -33,13 +33,13 @@ #ifndef __CVMX_L2C_H__ #define __CVMX_L2C_H__ -#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */ +#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */ #define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro, use function */ -#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */ +#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */ #define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */ -#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1) +#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1) /* Defines for index aliasing computations */ #define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits()) @@ -67,91 +67,91 @@ union cvmx_l2c_tag { /* L2C Performance Counter events. */ enum cvmx_l2c_event { - CVMX_L2C_EVENT_CYCLES = 0, + CVMX_L2C_EVENT_CYCLES = 0, CVMX_L2C_EVENT_INSTRUCTION_MISS = 1, - CVMX_L2C_EVENT_INSTRUCTION_HIT = 2, - CVMX_L2C_EVENT_DATA_MISS = 3, - CVMX_L2C_EVENT_DATA_HIT = 4, - CVMX_L2C_EVENT_MISS = 5, - CVMX_L2C_EVENT_HIT = 6, - CVMX_L2C_EVENT_VICTIM_HIT = 7, - CVMX_L2C_EVENT_INDEX_CONFLICT = 8, - CVMX_L2C_EVENT_TAG_PROBE = 9, - CVMX_L2C_EVENT_TAG_UPDATE = 10, - CVMX_L2C_EVENT_TAG_COMPLETE = 11, - CVMX_L2C_EVENT_TAG_DIRTY = 12, - CVMX_L2C_EVENT_DATA_STORE_NOP = 13, - CVMX_L2C_EVENT_DATA_STORE_READ = 14, + CVMX_L2C_EVENT_INSTRUCTION_HIT = 2, + CVMX_L2C_EVENT_DATA_MISS = 3, + CVMX_L2C_EVENT_DATA_HIT = 4, + CVMX_L2C_EVENT_MISS = 5, + CVMX_L2C_EVENT_HIT = 6, + CVMX_L2C_EVENT_VICTIM_HIT = 7, + CVMX_L2C_EVENT_INDEX_CONFLICT = 8, + CVMX_L2C_EVENT_TAG_PROBE = 9, + CVMX_L2C_EVENT_TAG_UPDATE = 10, + CVMX_L2C_EVENT_TAG_COMPLETE = 11, + CVMX_L2C_EVENT_TAG_DIRTY = 12, + CVMX_L2C_EVENT_DATA_STORE_NOP = 13, + CVMX_L2C_EVENT_DATA_STORE_READ = 14, CVMX_L2C_EVENT_DATA_STORE_WRITE = 15, - CVMX_L2C_EVENT_FILL_DATA_VALID = 16, - CVMX_L2C_EVENT_WRITE_REQUEST = 17, - CVMX_L2C_EVENT_READ_REQUEST = 18, + CVMX_L2C_EVENT_FILL_DATA_VALID = 16, + CVMX_L2C_EVENT_WRITE_REQUEST = 17, + CVMX_L2C_EVENT_READ_REQUEST = 18, CVMX_L2C_EVENT_WRITE_DATA_VALID = 19, - CVMX_L2C_EVENT_XMC_NOP = 20, - CVMX_L2C_EVENT_XMC_LDT = 21, - CVMX_L2C_EVENT_XMC_LDI = 22, - CVMX_L2C_EVENT_XMC_LDD = 23, - CVMX_L2C_EVENT_XMC_STF = 24, - CVMX_L2C_EVENT_XMC_STT = 25, - CVMX_L2C_EVENT_XMC_STP = 26, - CVMX_L2C_EVENT_XMC_STC = 27, - CVMX_L2C_EVENT_XMC_DWB = 28, - CVMX_L2C_EVENT_XMC_PL2 = 29, - CVMX_L2C_EVENT_XMC_PSL1 = 30, - CVMX_L2C_EVENT_XMC_IOBLD = 31, - CVMX_L2C_EVENT_XMC_IOBST = 32, - CVMX_L2C_EVENT_XMC_IOBDMA = 33, - CVMX_L2C_EVENT_XMC_IOBRSP = 34, - CVMX_L2C_EVENT_XMC_BUS_VALID = 35, - CVMX_L2C_EVENT_XMC_MEM_DATA = 36, - CVMX_L2C_EVENT_XMC_REFL_DATA = 37, - CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38, - CVMX_L2C_EVENT_RSC_NOP = 39, - CVMX_L2C_EVENT_RSC_STDN = 40, - CVMX_L2C_EVENT_RSC_FILL = 41, - CVMX_L2C_EVENT_RSC_REFL = 42, - CVMX_L2C_EVENT_RSC_STIN = 43, - CVMX_L2C_EVENT_RSC_SCIN = 44, - CVMX_L2C_EVENT_RSC_SCFL = 45, - CVMX_L2C_EVENT_RSC_SCDN = 46, - CVMX_L2C_EVENT_RSC_DATA_VALID = 47, - CVMX_L2C_EVENT_RSC_VALID_FILL = 48, - CVMX_L2C_EVENT_RSC_VALID_STRSP = 49, - CVMX_L2C_EVENT_RSC_VALID_REFL = 50, - CVMX_L2C_EVENT_LRF_REQ = 51, - CVMX_L2C_EVENT_DT_RD_ALLOC = 52, - CVMX_L2C_EVENT_DT_WR_INVAL = 53, + CVMX_L2C_EVENT_XMC_NOP = 20, + CVMX_L2C_EVENT_XMC_LDT = 21, + CVMX_L2C_EVENT_XMC_LDI = 22, + CVMX_L2C_EVENT_XMC_LDD = 23, + CVMX_L2C_EVENT_XMC_STF = 24, + CVMX_L2C_EVENT_XMC_STT = 25, + CVMX_L2C_EVENT_XMC_STP = 26, + CVMX_L2C_EVENT_XMC_STC = 27, + CVMX_L2C_EVENT_XMC_DWB = 28, + CVMX_L2C_EVENT_XMC_PL2 = 29, + CVMX_L2C_EVENT_XMC_PSL1 = 30, + CVMX_L2C_EVENT_XMC_IOBLD = 31, + CVMX_L2C_EVENT_XMC_IOBST = 32, + CVMX_L2C_EVENT_XMC_IOBDMA = 33, + CVMX_L2C_EVENT_XMC_IOBRSP = 34, + CVMX_L2C_EVENT_XMC_BUS_VALID = 35, + CVMX_L2C_EVENT_XMC_MEM_DATA = 36, + CVMX_L2C_EVENT_XMC_REFL_DATA = 37, + CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38, + CVMX_L2C_EVENT_RSC_NOP = 39, + CVMX_L2C_EVENT_RSC_STDN = 40, + CVMX_L2C_EVENT_RSC_FILL = 41, + CVMX_L2C_EVENT_RSC_REFL = 42, + CVMX_L2C_EVENT_RSC_STIN = 43, + CVMX_L2C_EVENT_RSC_SCIN = 44, + CVMX_L2C_EVENT_RSC_SCFL = 45, + CVMX_L2C_EVENT_RSC_SCDN = 46, + CVMX_L2C_EVENT_RSC_DATA_VALID = 47, + CVMX_L2C_EVENT_RSC_VALID_FILL = 48, + CVMX_L2C_EVENT_RSC_VALID_STRSP = 49, + CVMX_L2C_EVENT_RSC_VALID_REFL = 50, + CVMX_L2C_EVENT_LRF_REQ = 51, + CVMX_L2C_EVENT_DT_RD_ALLOC = 52, + CVMX_L2C_EVENT_DT_WR_INVAL = 53, CVMX_L2C_EVENT_MAX }; /* L2C Performance Counter events for Octeon2. */ enum cvmx_l2c_tad_event { - CVMX_L2C_TAD_EVENT_NONE = 0, - CVMX_L2C_TAD_EVENT_TAG_HIT = 1, - CVMX_L2C_TAD_EVENT_TAG_MISS = 2, - CVMX_L2C_TAD_EVENT_TAG_NOALLOC = 3, - CVMX_L2C_TAD_EVENT_TAG_VICTIM = 4, - CVMX_L2C_TAD_EVENT_SC_FAIL = 5, - CVMX_L2C_TAD_EVENT_SC_PASS = 6, - CVMX_L2C_TAD_EVENT_LFB_VALID = 7, - CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB = 8, - CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB = 9, - CVMX_L2C_TAD_EVENT_QUAD0_INDEX = 128, - CVMX_L2C_TAD_EVENT_QUAD0_READ = 129, - CVMX_L2C_TAD_EVENT_QUAD0_BANK = 130, - CVMX_L2C_TAD_EVENT_QUAD0_WDAT = 131, - CVMX_L2C_TAD_EVENT_QUAD1_INDEX = 144, - CVMX_L2C_TAD_EVENT_QUAD1_READ = 145, - CVMX_L2C_TAD_EVENT_QUAD1_BANK = 146, - CVMX_L2C_TAD_EVENT_QUAD1_WDAT = 147, - CVMX_L2C_TAD_EVENT_QUAD2_INDEX = 160, - CVMX_L2C_TAD_EVENT_QUAD2_READ = 161, - CVMX_L2C_TAD_EVENT_QUAD2_BANK = 162, - CVMX_L2C_TAD_EVENT_QUAD2_WDAT = 163, - CVMX_L2C_TAD_EVENT_QUAD3_INDEX = 176, - CVMX_L2C_TAD_EVENT_QUAD3_READ = 177, - CVMX_L2C_TAD_EVENT_QUAD3_BANK = 178, - CVMX_L2C_TAD_EVENT_QUAD3_WDAT = 179, + CVMX_L2C_TAD_EVENT_NONE = 0, + CVMX_L2C_TAD_EVENT_TAG_HIT = 1, + CVMX_L2C_TAD_EVENT_TAG_MISS = 2, + CVMX_L2C_TAD_EVENT_TAG_NOALLOC = 3, + CVMX_L2C_TAD_EVENT_TAG_VICTIM = 4, + CVMX_L2C_TAD_EVENT_SC_FAIL = 5, + CVMX_L2C_TAD_EVENT_SC_PASS = 6, + CVMX_L2C_TAD_EVENT_LFB_VALID = 7, + CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB = 8, + CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB = 9, + CVMX_L2C_TAD_EVENT_QUAD0_INDEX = 128, + CVMX_L2C_TAD_EVENT_QUAD0_READ = 129, + CVMX_L2C_TAD_EVENT_QUAD0_BANK = 130, + CVMX_L2C_TAD_EVENT_QUAD0_WDAT = 131, + CVMX_L2C_TAD_EVENT_QUAD1_INDEX = 144, + CVMX_L2C_TAD_EVENT_QUAD1_READ = 145, + CVMX_L2C_TAD_EVENT_QUAD1_BANK = 146, + CVMX_L2C_TAD_EVENT_QUAD1_WDAT = 147, + CVMX_L2C_TAD_EVENT_QUAD2_INDEX = 160, + CVMX_L2C_TAD_EVENT_QUAD2_READ = 161, + CVMX_L2C_TAD_EVENT_QUAD2_BANK = 162, + CVMX_L2C_TAD_EVENT_QUAD2_WDAT = 163, + CVMX_L2C_TAD_EVENT_QUAD3_INDEX = 176, + CVMX_L2C_TAD_EVENT_QUAD3_READ = 177, + CVMX_L2C_TAD_EVENT_QUAD3_BANK = 178, + CVMX_L2C_TAD_EVENT_QUAD3_WDAT = 179, CVMX_L2C_TAD_EVENT_MAX }; @@ -159,10 +159,10 @@ enum cvmx_l2c_tad_event { * Configure one of the four L2 Cache performance counters to capture event * occurrences. * - * @counter: The counter to configure. Range 0..3. - * @event: The type of L2 Cache event occurrence to count. + * @counter: The counter to configure. Range 0..3. + * @event: The type of L2 Cache event occurrence to count. * @clear_on_read: When asserted, any read of the performance counter - * clears the counter. + * clears the counter. * * @note The routine does not clear the counter. */ @@ -184,8 +184,8 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter); * @core: The core processor of interest. * * Returns The mask specifying the partitioning. 0 bits in mask indicates - * the cache 'ways' that a core can evict from. - * -1 on error + * the cache 'ways' that a core can evict from. + * -1 on error */ int cvmx_l2c_get_core_way_partition(uint32_t core); @@ -194,16 +194,16 @@ int cvmx_l2c_get_core_way_partition(uint32_t core); * * @core: The core that the partitioning applies to. * @mask: The partitioning of the ways expressed as a binary - * mask. A 0 bit allows the core to evict cache lines from - * a way, while a 1 bit blocks the core from evicting any - * lines from that way. There must be at least one allowed - * way (0 bit) in the mask. + * mask. A 0 bit allows the core to evict cache lines from + * a way, while a 1 bit blocks the core from evicting any + * lines from that way. There must be at least one allowed + * way (0 bit) in the mask. * * @note If any ways are blocked for all cores and the HW blocks, then - * those ways will never have any cache lines evicted from them. - * All cores and the hardware blocks are free to read from all - * ways regardless of the partitioning. + * those ways will never have any cache lines evicted from them. + * All cores and the hardware blocks are free to read from all + * ways regardless of the partitioning. */ int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask); @@ -211,8 +211,8 @@ int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask); * Return the L2 Cache way partitioning for the hw blocks. * * Returns The mask specifying the reserved way. 0 bits in mask indicates - * the cache 'ways' that a core can evict from. - * -1 on error + * the cache 'ways' that a core can evict from. + * -1 on error */ int cvmx_l2c_get_hw_way_partition(void); @@ -220,16 +220,16 @@ int cvmx_l2c_get_hw_way_partition(void); * Partitions the L2 cache for the hardware blocks. * * @mask: The partitioning of the ways expressed as a binary - * mask. A 0 bit allows the core to evict cache lines from - * a way, while a 1 bit blocks the core from evicting any - * lines from that way. There must be at least one allowed - * way (0 bit) in the mask. + * mask. A 0 bit allows the core to evict cache lines from + * a way, while a 1 bit blocks the core from evicting any + * lines from that way. There must be at least one allowed + * way (0 bit) in the mask. * * @note If any ways are blocked for all cores and the HW blocks, then - * those ways will never have any cache lines evicted from them. - * All cores and the hardware blocks are free to read from all - * ways regardless of the partitioning. + * those ways will never have any cache lines evicted from them. + * All cores and the hardware blocks are free to read from all + * ways regardless of the partitioning. */ int cvmx_l2c_set_hw_way_partition(uint32_t mask); @@ -240,7 +240,7 @@ int cvmx_l2c_set_hw_way_partition(uint32_t mask); * @addr: physical address of line to lock * * Returns 0 on success, - * 1 if line not locked. + * 1 if line not locked. */ int cvmx_l2c_lock_line(uint64_t addr); @@ -258,7 +258,7 @@ int cvmx_l2c_lock_line(uint64_t addr); * @len: Length (in bytes) of region to lock * * Returns Number of requested lines that where not locked. - * 0 on success (all locked) + * 0 on success (all locked) */ int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len); @@ -272,7 +272,7 @@ int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len); * @address: Physical address to unlock * * Returns 0: line not unlocked - * 1: line unlocked + * 1: line unlocked */ int cvmx_l2c_unlock_line(uint64_t address); @@ -290,7 +290,7 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len); * Read the L2 controller tag for a given location in L2 * * @association: - * Which association to read line from + * Which association to read line from * @index: Which way to read from. * * Returns l2c tag structure for line requested. diff --git a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h index 60543e0e77f..11a45621563 100644 --- a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -44,9 +44,15 @@ union cvmx_l2d_bst0 { uint64_t u64; struct cvmx_l2d_bst0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t ftl:1; uint64_t q0stat:34; +#else + uint64_t q0stat:34; + uint64_t ftl:1; + uint64_t reserved_35_63:29; +#endif } s; struct cvmx_l2d_bst0_s cn30xx; struct cvmx_l2d_bst0_s cn31xx; @@ -64,8 +70,13 @@ union cvmx_l2d_bst0 { union cvmx_l2d_bst1 { uint64_t u64; struct cvmx_l2d_bst1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q1stat:34; +#else + uint64_t q1stat:34; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_l2d_bst1_s cn30xx; struct cvmx_l2d_bst1_s cn31xx; @@ -83,8 +94,13 @@ union cvmx_l2d_bst1 { union cvmx_l2d_bst2 { uint64_t u64; struct cvmx_l2d_bst2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q2stat:34; +#else + uint64_t q2stat:34; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_l2d_bst2_s cn30xx; struct cvmx_l2d_bst2_s cn31xx; @@ -102,8 +118,13 @@ union cvmx_l2d_bst2 { union cvmx_l2d_bst3 { uint64_t u64; struct cvmx_l2d_bst3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q3stat:34; +#else + uint64_t q3stat:34; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_l2d_bst3_s cn30xx; struct cvmx_l2d_bst3_s cn31xx; @@ -121,6 +142,7 @@ union cvmx_l2d_bst3 { union cvmx_l2d_err { uint64_t u64; struct cvmx_l2d_err_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t bmhclsel:1; uint64_t ded_err:1; @@ -128,6 +150,15 @@ union cvmx_l2d_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t bmhclsel:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_l2d_err_s cn30xx; struct cvmx_l2d_err_s cn31xx; @@ -145,48 +176,97 @@ union cvmx_l2d_err { union cvmx_l2d_fadr { uint64_t u64; struct cvmx_l2d_fadr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t fadru:1; uint64_t fowmsk:4; uint64_t fset:3; uint64_t fadr:11; +#else + uint64_t fadr:11; + uint64_t fset:3; + uint64_t fowmsk:4; + uint64_t fadru:1; + uint64_t reserved_19_63:45; +#endif } s; struct cvmx_l2d_fadr_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t fowmsk:4; uint64_t reserved_13_13:1; uint64_t fset:2; uint64_t reserved_9_10:2; uint64_t fadr:9; +#else + uint64_t fadr:9; + uint64_t reserved_9_10:2; + uint64_t fset:2; + uint64_t reserved_13_13:1; + uint64_t fowmsk:4; + uint64_t reserved_18_63:46; +#endif } cn30xx; struct cvmx_l2d_fadr_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t fowmsk:4; uint64_t reserved_13_13:1; uint64_t fset:2; uint64_t reserved_10_10:1; uint64_t fadr:10; +#else + uint64_t fadr:10; + uint64_t reserved_10_10:1; + uint64_t fset:2; + uint64_t reserved_13_13:1; + uint64_t fowmsk:4; + uint64_t reserved_18_63:46; +#endif } cn31xx; struct cvmx_l2d_fadr_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t fowmsk:4; uint64_t fset:3; uint64_t fadr:11; +#else + uint64_t fadr:11; + uint64_t fset:3; + uint64_t fowmsk:4; + uint64_t reserved_18_63:46; +#endif } cn38xx; struct cvmx_l2d_fadr_cn38xx cn38xxp2; struct cvmx_l2d_fadr_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t fowmsk:4; uint64_t fset:3; uint64_t reserved_8_10:3; uint64_t fadr:8; +#else + uint64_t fadr:8; + uint64_t reserved_8_10:3; + uint64_t fset:3; + uint64_t fowmsk:4; + uint64_t reserved_18_63:46; +#endif } cn50xx; struct cvmx_l2d_fadr_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t fowmsk:4; uint64_t fset:3; uint64_t reserved_10_10:1; uint64_t fadr:10; +#else + uint64_t fadr:10; + uint64_t reserved_10_10:1; + uint64_t fset:3; + uint64_t fowmsk:4; + uint64_t reserved_18_63:46; +#endif } cn52xx; struct cvmx_l2d_fadr_cn52xx cn52xxp1; struct cvmx_l2d_fadr_s cn56xx; @@ -198,9 +278,15 @@ union cvmx_l2d_fadr { union cvmx_l2d_fsyn0 { uint64_t u64; struct cvmx_l2d_fsyn0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t fsyn_ow1:10; uint64_t fsyn_ow0:10; +#else + uint64_t fsyn_ow0:10; + uint64_t fsyn_ow1:10; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_l2d_fsyn0_s cn30xx; struct cvmx_l2d_fsyn0_s cn31xx; @@ -218,9 +304,15 @@ union cvmx_l2d_fsyn0 { union cvmx_l2d_fsyn1 { uint64_t u64; struct cvmx_l2d_fsyn1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t fsyn_ow3:10; uint64_t fsyn_ow2:10; +#else + uint64_t fsyn_ow2:10; + uint64_t fsyn_ow3:10; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_l2d_fsyn1_s cn30xx; struct cvmx_l2d_fsyn1_s cn31xx; @@ -238,8 +330,13 @@ union cvmx_l2d_fsyn1 { union cvmx_l2d_fus0 { uint64_t u64; struct cvmx_l2d_fus0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q0fus:34; +#else + uint64_t q0fus:34; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_l2d_fus0_s cn30xx; struct cvmx_l2d_fus0_s cn31xx; @@ -257,8 +354,13 @@ union cvmx_l2d_fus0 { union cvmx_l2d_fus1 { uint64_t u64; struct cvmx_l2d_fus1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q1fus:34; +#else + uint64_t q1fus:34; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_l2d_fus1_s cn30xx; struct cvmx_l2d_fus1_s cn31xx; @@ -276,8 +378,13 @@ union cvmx_l2d_fus1 { union cvmx_l2d_fus2 { uint64_t u64; struct cvmx_l2d_fus2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t q2fus:34; +#else + uint64_t q2fus:34; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_l2d_fus2_s cn30xx; struct cvmx_l2d_fus2_s cn31xx; @@ -295,61 +402,123 @@ union cvmx_l2d_fus2 { union cvmx_l2d_fus3 { uint64_t u64; struct cvmx_l2d_fus3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ema_ctl:3; uint64_t reserved_34_36:3; uint64_t q3fus:34; +#else + uint64_t q3fus:34; + uint64_t reserved_34_36:3; + uint64_t ema_ctl:3; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_l2d_fus3_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t crip_64k:1; uint64_t q3fus:34; +#else + uint64_t q3fus:34; + uint64_t crip_64k:1; + uint64_t reserved_35_63:29; +#endif } cn30xx; struct cvmx_l2d_fus3_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t crip_128k:1; uint64_t q3fus:34; +#else + uint64_t q3fus:34; + uint64_t crip_128k:1; + uint64_t reserved_35_63:29; +#endif } cn31xx; struct cvmx_l2d_fus3_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t crip_256k:1; uint64_t crip_512k:1; uint64_t q3fus:34; +#else + uint64_t q3fus:34; + uint64_t crip_512k:1; + uint64_t crip_256k:1; + uint64_t reserved_36_63:28; +#endif } cn38xx; struct cvmx_l2d_fus3_cn38xx cn38xxp2; struct cvmx_l2d_fus3_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ema_ctl:3; uint64_t reserved_36_36:1; uint64_t crip_32k:1; uint64_t crip_64k:1; uint64_t q3fus:34; +#else + uint64_t q3fus:34; + uint64_t crip_64k:1; + uint64_t crip_32k:1; + uint64_t reserved_36_36:1; + uint64_t ema_ctl:3; + uint64_t reserved_40_63:24; +#endif } cn50xx; struct cvmx_l2d_fus3_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ema_ctl:3; uint64_t reserved_36_36:1; uint64_t crip_128k:1; uint64_t crip_256k:1; uint64_t q3fus:34; +#else + uint64_t q3fus:34; + uint64_t crip_256k:1; + uint64_t crip_128k:1; + uint64_t reserved_36_36:1; + uint64_t ema_ctl:3; + uint64_t reserved_40_63:24; +#endif } cn52xx; struct cvmx_l2d_fus3_cn52xx cn52xxp1; struct cvmx_l2d_fus3_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ema_ctl:3; uint64_t reserved_36_36:1; uint64_t crip_512k:1; uint64_t crip_1024k:1; uint64_t q3fus:34; +#else + uint64_t q3fus:34; + uint64_t crip_1024k:1; + uint64_t crip_512k:1; + uint64_t reserved_36_36:1; + uint64_t ema_ctl:3; + uint64_t reserved_40_63:24; +#endif } cn56xx; struct cvmx_l2d_fus3_cn56xx cn56xxp1; struct cvmx_l2d_fus3_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t ema_ctl:2; uint64_t reserved_36_36:1; uint64_t crip_512k:1; uint64_t crip_1024k:1; uint64_t q3fus:34; +#else + uint64_t q3fus:34; + uint64_t crip_1024k:1; + uint64_t crip_512k:1; + uint64_t reserved_36_36:1; + uint64_t ema_ctl:2; + uint64_t reserved_39_63:25; +#endif } cn58xx; struct cvmx_l2d_fus3_cn58xx cn58xxp1; }; diff --git a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h index 873968f55ee..83ce22c080e 100644 --- a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -33,6 +33,7 @@ union cvmx_l2t_err { uint64_t u64; struct cvmx_l2t_err_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t fadru:1; uint64_t lck_intena2:1; @@ -47,8 +48,25 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:10; + uint64_t fset:3; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t fadru:1; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_l2t_err_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -64,8 +82,26 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:8; + uint64_t reserved_19_20:2; + uint64_t fset:2; + uint64_t reserved_23_23:1; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t reserved_28_63:36; +#endif } cn30xx; struct cvmx_l2t_err_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -81,8 +117,26 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:9; + uint64_t reserved_20_20:1; + uint64_t fset:2; + uint64_t reserved_23_23:1; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t reserved_28_63:36; +#endif } cn31xx; struct cvmx_l2t_err_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -96,9 +150,25 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:10; + uint64_t fset:3; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t reserved_28_63:36; +#endif } cn38xx; struct cvmx_l2t_err_cn38xx cn38xxp2; struct cvmx_l2t_err_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -113,8 +183,25 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:7; + uint64_t reserved_18_20:3; + uint64_t fset:3; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t reserved_28_63:36; +#endif } cn50xx; struct cvmx_l2t_err_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t lck_intena2:1; uint64_t lckerr2:1; @@ -129,6 +216,22 @@ union cvmx_l2t_err { uint64_t ded_intena:1; uint64_t sec_intena:1; uint64_t ecc_ena:1; +#else + uint64_t ecc_ena:1; + uint64_t sec_intena:1; + uint64_t ded_intena:1; + uint64_t sec_err:1; + uint64_t ded_err:1; + uint64_t fsyn:6; + uint64_t fadr:9; + uint64_t reserved_20_20:1; + uint64_t fset:3; + uint64_t lckerr:1; + uint64_t lck_intena:1; + uint64_t lckerr2:1; + uint64_t lck_intena2:1; + uint64_t reserved_28_63:36; +#endif } cn52xx; struct cvmx_l2t_err_cn52xx cn52xxp1; struct cvmx_l2t_err_s cn56xx; diff --git a/arch/mips/include/asm/octeon/cvmx-led-defs.h b/arch/mips/include/asm/octeon/cvmx-led-defs.h index e25173bb8bb..d36d42b8307 100644 --- a/arch/mips/include/asm/octeon/cvmx-led-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-led-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -45,8 +45,13 @@ union cvmx_led_blink { uint64_t u64; struct cvmx_led_blink_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rate:8; +#else + uint64_t rate:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_led_blink_s cn38xx; struct cvmx_led_blink_s cn38xxp2; @@ -59,8 +64,13 @@ union cvmx_led_blink { union cvmx_led_clk_phase { uint64_t u64; struct cvmx_led_clk_phase_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t phase:7; +#else + uint64_t phase:7; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_led_clk_phase_s cn38xx; struct cvmx_led_clk_phase_s cn38xxp2; @@ -73,8 +83,13 @@ union cvmx_led_clk_phase { union cvmx_led_cylon { uint64_t u64; struct cvmx_led_cylon_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t rate:16; +#else + uint64_t rate:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_led_cylon_s cn38xx; struct cvmx_led_cylon_s cn38xxp2; @@ -87,8 +102,13 @@ union cvmx_led_cylon { union cvmx_led_dbg { uint64_t u64; struct cvmx_led_dbg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t dbg_en:1; +#else + uint64_t dbg_en:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_led_dbg_s cn38xx; struct cvmx_led_dbg_s cn38xxp2; @@ -101,8 +121,13 @@ union cvmx_led_dbg { union cvmx_led_en { uint64_t u64; struct cvmx_led_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t en:1; +#else + uint64_t en:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_led_en_s cn38xx; struct cvmx_led_en_s cn38xxp2; @@ -115,8 +140,13 @@ union cvmx_led_en { union cvmx_led_polarity { uint64_t u64; struct cvmx_led_polarity_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t polarity:1; +#else + uint64_t polarity:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_led_polarity_s cn38xx; struct cvmx_led_polarity_s cn38xxp2; @@ -129,8 +159,13 @@ union cvmx_led_polarity { union cvmx_led_prt { uint64_t u64; struct cvmx_led_prt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t prt_en:8; +#else + uint64_t prt_en:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_led_prt_s cn38xx; struct cvmx_led_prt_s cn38xxp2; @@ -143,8 +178,13 @@ union cvmx_led_prt { union cvmx_led_prt_fmt { uint64_t u64; struct cvmx_led_prt_fmt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t format:4; +#else + uint64_t format:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_led_prt_fmt_s cn38xx; struct cvmx_led_prt_fmt_s cn38xxp2; @@ -157,8 +197,13 @@ union cvmx_led_prt_fmt { union cvmx_led_prt_statusx { uint64_t u64; struct cvmx_led_prt_statusx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t status:6; +#else + uint64_t status:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_led_prt_statusx_s cn38xx; struct cvmx_led_prt_statusx_s cn38xxp2; @@ -171,8 +216,13 @@ union cvmx_led_prt_statusx { union cvmx_led_udd_cntx { uint64_t u64; struct cvmx_led_udd_cntx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t cnt:6; +#else + uint64_t cnt:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_led_udd_cntx_s cn38xx; struct cvmx_led_udd_cntx_s cn38xxp2; @@ -185,8 +235,13 @@ union cvmx_led_udd_cntx { union cvmx_led_udd_datx { uint64_t u64; struct cvmx_led_udd_datx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t dat:32; +#else + uint64_t dat:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_led_udd_datx_s cn38xx; struct cvmx_led_udd_datx_s cn38xxp2; @@ -199,8 +254,13 @@ union cvmx_led_udd_datx { union cvmx_led_udd_dat_clrx { uint64_t u64; struct cvmx_led_udd_dat_clrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t clr:32; +#else + uint64_t clr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_led_udd_dat_clrx_s cn38xx; struct cvmx_led_udd_dat_clrx_s cn38xxp2; @@ -213,8 +273,13 @@ union cvmx_led_udd_dat_clrx { union cvmx_led_udd_dat_setx { uint64_t u64; struct cvmx_led_udd_dat_setx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t set:32; +#else + uint64_t set:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_led_udd_dat_setx_s cn38xx; struct cvmx_led_udd_dat_setx_s cn38xxp2; diff --git a/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h b/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h new file mode 100644 index 00000000000..36f51072114 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h @@ -0,0 +1,3457 @@ +/***********************license start*************** + * Author: Cavium Inc. + * + * Contact: support@cavium.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Inc. for more information + ***********************license end**************************************/ + +#ifndef __CVMX_LMCX_DEFS_H__ +#define __CVMX_LMCX_DEFS_H__ + +#define CVMX_LMCX_BIST_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_BIST_RESULT(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F8ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_CHAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000220ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_CHAR_MASK0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000228ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_CHAR_MASK1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000230ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_CHAR_MASK2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000238ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_CHAR_MASK3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000240ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_CHAR_MASK4(block_id) (CVMX_ADD_IO_SEG(0x0001180088000318ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000028ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_COMP_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_CONFIG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000188ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_CONTROL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000190ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000010ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000090ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_DCLK_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E0ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_DCLK_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000070ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_DCLK_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000068ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_DCLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B8ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_DDR2_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000018ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_DDR_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000258ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_DELAY_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000088ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_DIMMX_PARAMS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_LMCX_DIMM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000310ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_DLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000C0ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_DLL_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001C8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_DLL_CTL3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000218ull) + ((block_id) & 3) * 0x1000000ull) +static inline uint64_t CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull; +} + +static inline uint64_t CVMX_LMCX_ECC_SYND(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull; +} + +static inline uint64_t CVMX_LMCX_FADR(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull; +} + +#define CVMX_LMCX_IFB_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D0ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_IFB_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000050ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_IFB_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000048ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F0ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_MEM_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000000ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_MEM_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000008ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_MODEREG_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_MODEREG_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000260ull) + ((block_id) & 3) * 0x1000000ull) +static inline uint64_t CVMX_LMCX_NXM(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull; +} + +#define CVMX_LMCX_OPS_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_OPS_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000060ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_OPS_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000058ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_PHY_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000210ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_PLL_BWCTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000040ull)) +#define CVMX_LMCX_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A8ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_PLL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B0ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_READ_LEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000140ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_READ_LEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000148ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_READ_LEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000100ull) + (((offset) & 3) + ((block_id) & 1) * 0xC000000ull) * 8) +#define CVMX_LMCX_RESET_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000180ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_RLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A0ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_RLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_RLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_LMCX_RODT_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A0ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_RODT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000078ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_RODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x0001180088000268ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_SCRAMBLED_FADR(block_id) (CVMX_ADD_IO_SEG(0x0001180088000330ull)) +#define CVMX_LMCX_SCRAMBLE_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000320ull)) +#define CVMX_LMCX_SCRAMBLE_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000328ull)) +#define CVMX_LMCX_SLOT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_SLOT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000200ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_SLOT_CTL2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000208ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_TIMING_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000198ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_TIMING_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A0ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_TRO_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000248ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_TRO_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180088000250ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_WLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000300ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_WLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000308ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_WLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_LMCX_WODT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000030ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_WODT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000080ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_WODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B0ull) + ((block_id) & 3) * 0x1000000ull) + +union cvmx_lmcx_bist_ctl { + uint64_t u64; + struct cvmx_lmcx_bist_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t start:1; +#else + uint64_t start:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_lmcx_bist_ctl_s cn50xx; + struct cvmx_lmcx_bist_ctl_s cn52xx; + struct cvmx_lmcx_bist_ctl_s cn52xxp1; + struct cvmx_lmcx_bist_ctl_s cn56xx; + struct cvmx_lmcx_bist_ctl_s cn56xxp1; +}; + +union cvmx_lmcx_bist_result { + uint64_t u64; + struct cvmx_lmcx_bist_result_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t csrd2e:1; + uint64_t csre2d:1; + uint64_t mwf:1; + uint64_t mwd:3; + uint64_t mwc:1; + uint64_t mrf:1; + uint64_t mrd:3; +#else + uint64_t mrd:3; + uint64_t mrf:1; + uint64_t mwc:1; + uint64_t mwd:3; + uint64_t mwf:1; + uint64_t csre2d:1; + uint64_t csrd2e:1; + uint64_t reserved_11_63:53; +#endif + } s; + struct cvmx_lmcx_bist_result_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_9_63:55; + uint64_t mwf:1; + uint64_t mwd:3; + uint64_t mwc:1; + uint64_t mrf:1; + uint64_t mrd:3; +#else + uint64_t mrd:3; + uint64_t mrf:1; + uint64_t mwc:1; + uint64_t mwd:3; + uint64_t mwf:1; + uint64_t reserved_9_63:55; +#endif + } cn50xx; + struct cvmx_lmcx_bist_result_s cn52xx; + struct cvmx_lmcx_bist_result_s cn52xxp1; + struct cvmx_lmcx_bist_result_s cn56xx; + struct cvmx_lmcx_bist_result_s cn56xxp1; +}; + +union cvmx_lmcx_char_ctl { + uint64_t u64; + struct cvmx_lmcx_char_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_44_63:20; + uint64_t dr:1; + uint64_t skew_on:1; + uint64_t en:1; + uint64_t sel:1; + uint64_t prog:8; + uint64_t prbs:32; +#else + uint64_t prbs:32; + uint64_t prog:8; + uint64_t sel:1; + uint64_t en:1; + uint64_t skew_on:1; + uint64_t dr:1; + uint64_t reserved_44_63:20; +#endif + } s; + struct cvmx_lmcx_char_ctl_s cn61xx; + struct cvmx_lmcx_char_ctl_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_42_63:22; + uint64_t en:1; + uint64_t sel:1; + uint64_t prog:8; + uint64_t prbs:32; +#else + uint64_t prbs:32; + uint64_t prog:8; + uint64_t sel:1; + uint64_t en:1; + uint64_t reserved_42_63:22; +#endif + } cn63xx; + struct cvmx_lmcx_char_ctl_cn63xx cn63xxp1; + struct cvmx_lmcx_char_ctl_s cn66xx; + struct cvmx_lmcx_char_ctl_s cn68xx; + struct cvmx_lmcx_char_ctl_cn63xx cn68xxp1; + struct cvmx_lmcx_char_ctl_s cnf71xx; +}; + +union cvmx_lmcx_char_mask0 { + uint64_t u64; + struct cvmx_lmcx_char_mask0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t mask:64; +#else + uint64_t mask:64; +#endif + } s; + struct cvmx_lmcx_char_mask0_s cn61xx; + struct cvmx_lmcx_char_mask0_s cn63xx; + struct cvmx_lmcx_char_mask0_s cn63xxp1; + struct cvmx_lmcx_char_mask0_s cn66xx; + struct cvmx_lmcx_char_mask0_s cn68xx; + struct cvmx_lmcx_char_mask0_s cn68xxp1; + struct cvmx_lmcx_char_mask0_s cnf71xx; +}; + +union cvmx_lmcx_char_mask1 { + uint64_t u64; + struct cvmx_lmcx_char_mask1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_8_63:56; + uint64_t mask:8; +#else + uint64_t mask:8; + uint64_t reserved_8_63:56; +#endif + } s; + struct cvmx_lmcx_char_mask1_s cn61xx; + struct cvmx_lmcx_char_mask1_s cn63xx; + struct cvmx_lmcx_char_mask1_s cn63xxp1; + struct cvmx_lmcx_char_mask1_s cn66xx; + struct cvmx_lmcx_char_mask1_s cn68xx; + struct cvmx_lmcx_char_mask1_s cn68xxp1; + struct cvmx_lmcx_char_mask1_s cnf71xx; +}; + +union cvmx_lmcx_char_mask2 { + uint64_t u64; + struct cvmx_lmcx_char_mask2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t mask:64; +#else + uint64_t mask:64; +#endif + } s; + struct cvmx_lmcx_char_mask2_s cn61xx; + struct cvmx_lmcx_char_mask2_s cn63xx; + struct cvmx_lmcx_char_mask2_s cn63xxp1; + struct cvmx_lmcx_char_mask2_s cn66xx; + struct cvmx_lmcx_char_mask2_s cn68xx; + struct cvmx_lmcx_char_mask2_s cn68xxp1; + struct cvmx_lmcx_char_mask2_s cnf71xx; +}; + +union cvmx_lmcx_char_mask3 { + uint64_t u64; + struct cvmx_lmcx_char_mask3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_8_63:56; + uint64_t mask:8; +#else + uint64_t mask:8; + uint64_t reserved_8_63:56; +#endif + } s; + struct cvmx_lmcx_char_mask3_s cn61xx; + struct cvmx_lmcx_char_mask3_s cn63xx; + struct cvmx_lmcx_char_mask3_s cn63xxp1; + struct cvmx_lmcx_char_mask3_s cn66xx; + struct cvmx_lmcx_char_mask3_s cn68xx; + struct cvmx_lmcx_char_mask3_s cn68xxp1; + struct cvmx_lmcx_char_mask3_s cnf71xx; +}; + +union cvmx_lmcx_char_mask4 { + uint64_t u64; + struct cvmx_lmcx_char_mask4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t reset_n_mask:1; + uint64_t a_mask:16; + uint64_t ba_mask:3; + uint64_t we_n_mask:1; + uint64_t cas_n_mask:1; + uint64_t ras_n_mask:1; + uint64_t odt1_mask:2; + uint64_t odt0_mask:2; + uint64_t cs1_n_mask:2; + uint64_t cs0_n_mask:2; + uint64_t cke_mask:2; +#else + uint64_t cke_mask:2; + uint64_t cs0_n_mask:2; + uint64_t cs1_n_mask:2; + uint64_t odt0_mask:2; + uint64_t odt1_mask:2; + uint64_t ras_n_mask:1; + uint64_t cas_n_mask:1; + uint64_t we_n_mask:1; + uint64_t ba_mask:3; + uint64_t a_mask:16; + uint64_t reset_n_mask:1; + uint64_t reserved_33_63:31; +#endif + } s; + struct cvmx_lmcx_char_mask4_s cn61xx; + struct cvmx_lmcx_char_mask4_s cn63xx; + struct cvmx_lmcx_char_mask4_s cn63xxp1; + struct cvmx_lmcx_char_mask4_s cn66xx; + struct cvmx_lmcx_char_mask4_s cn68xx; + struct cvmx_lmcx_char_mask4_s cn68xxp1; + struct cvmx_lmcx_char_mask4_s cnf71xx; +}; + +union cvmx_lmcx_comp_ctl { + uint64_t u64; + struct cvmx_lmcx_comp_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t nctl_csr:4; + uint64_t nctl_clk:4; + uint64_t nctl_cmd:4; + uint64_t nctl_dat:4; + uint64_t pctl_csr:4; + uint64_t pctl_clk:4; + uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t pctl_clk:4; + uint64_t pctl_csr:4; + uint64_t nctl_dat:4; + uint64_t nctl_cmd:4; + uint64_t nctl_clk:4; + uint64_t nctl_csr:4; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_comp_ctl_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t nctl_csr:4; + uint64_t nctl_clk:4; + uint64_t nctl_cmd:4; + uint64_t nctl_dat:4; + uint64_t pctl_csr:4; + uint64_t pctl_clk:4; + uint64_t pctl_cmd:4; + uint64_t pctl_dat:4; +#else + uint64_t pctl_dat:4; + uint64_t pctl_cmd:4; + uint64_t pctl_clk:4; + uint64_t pctl_csr:4; + uint64_t nctl_dat:4; + uint64_t nctl_cmd:4; + uint64_t nctl_clk:4; + uint64_t nctl_csr:4; + uint64_t reserved_32_63:32; +#endif + } cn30xx; + struct cvmx_lmcx_comp_ctl_cn30xx cn31xx; + struct cvmx_lmcx_comp_ctl_cn30xx cn38xx; + struct cvmx_lmcx_comp_ctl_cn30xx cn38xxp2; + struct cvmx_lmcx_comp_ctl_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t nctl_csr:4; + uint64_t reserved_20_27:8; + uint64_t nctl_dat:4; + uint64_t pctl_csr:4; + uint64_t reserved_5_11:7; + uint64_t pctl_dat:5; +#else + uint64_t pctl_dat:5; + uint64_t reserved_5_11:7; + uint64_t pctl_csr:4; + uint64_t nctl_dat:4; + uint64_t reserved_20_27:8; + uint64_t nctl_csr:4; + uint64_t reserved_32_63:32; +#endif + } cn50xx; + struct cvmx_lmcx_comp_ctl_cn50xx cn52xx; + struct cvmx_lmcx_comp_ctl_cn50xx cn52xxp1; + struct cvmx_lmcx_comp_ctl_cn50xx cn56xx; + struct cvmx_lmcx_comp_ctl_cn50xx cn56xxp1; + struct cvmx_lmcx_comp_ctl_cn50xx cn58xx; + struct cvmx_lmcx_comp_ctl_cn58xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t nctl_csr:4; + uint64_t reserved_20_27:8; + uint64_t nctl_dat:4; + uint64_t pctl_csr:4; + uint64_t reserved_4_11:8; + uint64_t pctl_dat:4; +#else + uint64_t pctl_dat:4; + uint64_t reserved_4_11:8; + uint64_t pctl_csr:4; + uint64_t nctl_dat:4; + uint64_t reserved_20_27:8; + uint64_t nctl_csr:4; + uint64_t reserved_32_63:32; +#endif + } cn58xxp1; +}; + +union cvmx_lmcx_comp_ctl2 { + uint64_t u64; + struct cvmx_lmcx_comp_ctl2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_34_63:30; + uint64_t ddr__ptune:4; + uint64_t ddr__ntune:4; + uint64_t m180:1; + uint64_t byp:1; + uint64_t ptune:4; + uint64_t ntune:4; + uint64_t rodt_ctl:4; + uint64_t cmd_ctl:4; + uint64_t ck_ctl:4; + uint64_t dqx_ctl:4; +#else + uint64_t dqx_ctl:4; + uint64_t ck_ctl:4; + uint64_t cmd_ctl:4; + uint64_t rodt_ctl:4; + uint64_t ntune:4; + uint64_t ptune:4; + uint64_t byp:1; + uint64_t m180:1; + uint64_t ddr__ntune:4; + uint64_t ddr__ptune:4; + uint64_t reserved_34_63:30; +#endif + } s; + struct cvmx_lmcx_comp_ctl2_s cn61xx; + struct cvmx_lmcx_comp_ctl2_s cn63xx; + struct cvmx_lmcx_comp_ctl2_s cn63xxp1; + struct cvmx_lmcx_comp_ctl2_s cn66xx; + struct cvmx_lmcx_comp_ctl2_s cn68xx; + struct cvmx_lmcx_comp_ctl2_s cn68xxp1; + struct cvmx_lmcx_comp_ctl2_s cnf71xx; +}; + +union cvmx_lmcx_config { + uint64_t u64; + struct cvmx_lmcx_config_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_61_63:3; + uint64_t mode32b:1; + uint64_t scrz:1; + uint64_t early_unload_d1_r1:1; + uint64_t early_unload_d1_r0:1; + uint64_t early_unload_d0_r1:1; + uint64_t early_unload_d0_r0:1; + uint64_t init_status:4; + uint64_t mirrmask:4; + uint64_t rankmask:4; + uint64_t rank_ena:1; + uint64_t sref_with_dll:1; + uint64_t early_dqx:1; + uint64_t sequence:3; + uint64_t ref_zqcs_int:19; + uint64_t reset:1; + uint64_t ecc_adr:1; + uint64_t forcewrite:4; + uint64_t idlepower:3; + uint64_t pbank_lsb:4; + uint64_t row_lsb:3; + uint64_t ecc_ena:1; + uint64_t init_start:1; +#else + uint64_t init_start:1; + uint64_t ecc_ena:1; + uint64_t row_lsb:3; + uint64_t pbank_lsb:4; + uint64_t idlepower:3; + uint64_t forcewrite:4; + uint64_t ecc_adr:1; + uint64_t reset:1; + uint64_t ref_zqcs_int:19; + uint64_t sequence:3; + uint64_t early_dqx:1; + uint64_t sref_with_dll:1; + uint64_t rank_ena:1; + uint64_t rankmask:4; + uint64_t mirrmask:4; + uint64_t init_status:4; + uint64_t early_unload_d0_r0:1; + uint64_t early_unload_d0_r1:1; + uint64_t early_unload_d1_r0:1; + uint64_t early_unload_d1_r1:1; + uint64_t scrz:1; + uint64_t mode32b:1; + uint64_t reserved_61_63:3; +#endif + } s; + struct cvmx_lmcx_config_s cn61xx; + struct cvmx_lmcx_config_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_59_63:5; + uint64_t early_unload_d1_r1:1; + uint64_t early_unload_d1_r0:1; + uint64_t early_unload_d0_r1:1; + uint64_t early_unload_d0_r0:1; + uint64_t init_status:4; + uint64_t mirrmask:4; + uint64_t rankmask:4; + uint64_t rank_ena:1; + uint64_t sref_with_dll:1; + uint64_t early_dqx:1; + uint64_t sequence:3; + uint64_t ref_zqcs_int:19; + uint64_t reset:1; + uint64_t ecc_adr:1; + uint64_t forcewrite:4; + uint64_t idlepower:3; + uint64_t pbank_lsb:4; + uint64_t row_lsb:3; + uint64_t ecc_ena:1; + uint64_t init_start:1; +#else + uint64_t init_start:1; + uint64_t ecc_ena:1; + uint64_t row_lsb:3; + uint64_t pbank_lsb:4; + uint64_t idlepower:3; + uint64_t forcewrite:4; + uint64_t ecc_adr:1; + uint64_t reset:1; + uint64_t ref_zqcs_int:19; + uint64_t sequence:3; + uint64_t early_dqx:1; + uint64_t sref_with_dll:1; + uint64_t rank_ena:1; + uint64_t rankmask:4; + uint64_t mirrmask:4; + uint64_t init_status:4; + uint64_t early_unload_d0_r0:1; + uint64_t early_unload_d0_r1:1; + uint64_t early_unload_d1_r0:1; + uint64_t early_unload_d1_r1:1; + uint64_t reserved_59_63:5; +#endif + } cn63xx; + struct cvmx_lmcx_config_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_55_63:9; + uint64_t init_status:4; + uint64_t mirrmask:4; + uint64_t rankmask:4; + uint64_t rank_ena:1; + uint64_t sref_with_dll:1; + uint64_t early_dqx:1; + uint64_t sequence:3; + uint64_t ref_zqcs_int:19; + uint64_t reset:1; + uint64_t ecc_adr:1; + uint64_t forcewrite:4; + uint64_t idlepower:3; + uint64_t pbank_lsb:4; + uint64_t row_lsb:3; + uint64_t ecc_ena:1; + uint64_t init_start:1; +#else + uint64_t init_start:1; + uint64_t ecc_ena:1; + uint64_t row_lsb:3; + uint64_t pbank_lsb:4; + uint64_t idlepower:3; + uint64_t forcewrite:4; + uint64_t ecc_adr:1; + uint64_t reset:1; + uint64_t ref_zqcs_int:19; + uint64_t sequence:3; + uint64_t early_dqx:1; + uint64_t sref_with_dll:1; + uint64_t rank_ena:1; + uint64_t rankmask:4; + uint64_t mirrmask:4; + uint64_t init_status:4; + uint64_t reserved_55_63:9; +#endif + } cn63xxp1; + struct cvmx_lmcx_config_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_60_63:4; + uint64_t scrz:1; + uint64_t early_unload_d1_r1:1; + uint64_t early_unload_d1_r0:1; + uint64_t early_unload_d0_r1:1; + uint64_t early_unload_d0_r0:1; + uint64_t init_status:4; + uint64_t mirrmask:4; + uint64_t rankmask:4; + uint64_t rank_ena:1; + uint64_t sref_with_dll:1; + uint64_t early_dqx:1; + uint64_t sequence:3; + uint64_t ref_zqcs_int:19; + uint64_t reset:1; + uint64_t ecc_adr:1; + uint64_t forcewrite:4; + uint64_t idlepower:3; + uint64_t pbank_lsb:4; + uint64_t row_lsb:3; + uint64_t ecc_ena:1; + uint64_t init_start:1; +#else + uint64_t init_start:1; + uint64_t ecc_ena:1; + uint64_t row_lsb:3; + uint64_t pbank_lsb:4; + uint64_t idlepower:3; + uint64_t forcewrite:4; + uint64_t ecc_adr:1; + uint64_t reset:1; + uint64_t ref_zqcs_int:19; + uint64_t sequence:3; + uint64_t early_dqx:1; + uint64_t sref_with_dll:1; + uint64_t rank_ena:1; + uint64_t rankmask:4; + uint64_t mirrmask:4; + uint64_t init_status:4; + uint64_t early_unload_d0_r0:1; + uint64_t early_unload_d0_r1:1; + uint64_t early_unload_d1_r0:1; + uint64_t early_unload_d1_r1:1; + uint64_t scrz:1; + uint64_t reserved_60_63:4; +#endif + } cn66xx; + struct cvmx_lmcx_config_cn63xx cn68xx; + struct cvmx_lmcx_config_cn63xx cn68xxp1; + struct cvmx_lmcx_config_s cnf71xx; +}; + +union cvmx_lmcx_control { + uint64_t u64; + struct cvmx_lmcx_control_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t scramble_ena:1; + uint64_t thrcnt:12; + uint64_t persub:8; + uint64_t thrmax:4; + uint64_t crm_cnt:5; + uint64_t crm_thr:5; + uint64_t crm_max:5; + uint64_t rodt_bprch:1; + uint64_t wodt_bprch:1; + uint64_t bprch:2; + uint64_t ext_zqcs_dis:1; + uint64_t int_zqcs_dis:1; + uint64_t auto_dclkdis:1; + uint64_t xor_bank:1; + uint64_t max_write_batch:4; + uint64_t nxm_write_en:1; + uint64_t elev_prio_dis:1; + uint64_t inorder_wr:1; + uint64_t inorder_rd:1; + uint64_t throttle_wr:1; + uint64_t throttle_rd:1; + uint64_t fprch2:2; + uint64_t pocas:1; + uint64_t ddr2t:1; + uint64_t bwcnt:1; + uint64_t rdimm_ena:1; +#else + uint64_t rdimm_ena:1; + uint64_t bwcnt:1; + uint64_t ddr2t:1; + uint64_t pocas:1; + uint64_t fprch2:2; + uint64_t throttle_rd:1; + uint64_t throttle_wr:1; + uint64_t inorder_rd:1; + uint64_t inorder_wr:1; + uint64_t elev_prio_dis:1; + uint64_t nxm_write_en:1; + uint64_t max_write_batch:4; + uint64_t xor_bank:1; + uint64_t auto_dclkdis:1; + uint64_t int_zqcs_dis:1; + uint64_t ext_zqcs_dis:1; + uint64_t bprch:2; + uint64_t wodt_bprch:1; + uint64_t rodt_bprch:1; + uint64_t crm_max:5; + uint64_t crm_thr:5; + uint64_t crm_cnt:5; + uint64_t thrmax:4; + uint64_t persub:8; + uint64_t thrcnt:12; + uint64_t scramble_ena:1; +#endif + } s; + struct cvmx_lmcx_control_s cn61xx; + struct cvmx_lmcx_control_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_24_63:40; + uint64_t rodt_bprch:1; + uint64_t wodt_bprch:1; + uint64_t bprch:2; + uint64_t ext_zqcs_dis:1; + uint64_t int_zqcs_dis:1; + uint64_t auto_dclkdis:1; + uint64_t xor_bank:1; + uint64_t max_write_batch:4; + uint64_t nxm_write_en:1; + uint64_t elev_prio_dis:1; + uint64_t inorder_wr:1; + uint64_t inorder_rd:1; + uint64_t throttle_wr:1; + uint64_t throttle_rd:1; + uint64_t fprch2:2; + uint64_t pocas:1; + uint64_t ddr2t:1; + uint64_t bwcnt:1; + uint64_t rdimm_ena:1; +#else + uint64_t rdimm_ena:1; + uint64_t bwcnt:1; + uint64_t ddr2t:1; + uint64_t pocas:1; + uint64_t fprch2:2; + uint64_t throttle_rd:1; + uint64_t throttle_wr:1; + uint64_t inorder_rd:1; + uint64_t inorder_wr:1; + uint64_t elev_prio_dis:1; + uint64_t nxm_write_en:1; + uint64_t max_write_batch:4; + uint64_t xor_bank:1; + uint64_t auto_dclkdis:1; + uint64_t int_zqcs_dis:1; + uint64_t ext_zqcs_dis:1; + uint64_t bprch:2; + uint64_t wodt_bprch:1; + uint64_t rodt_bprch:1; + uint64_t reserved_24_63:40; +#endif + } cn63xx; + struct cvmx_lmcx_control_cn63xx cn63xxp1; + struct cvmx_lmcx_control_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t scramble_ena:1; + uint64_t reserved_24_62:39; + uint64_t rodt_bprch:1; + uint64_t wodt_bprch:1; + uint64_t bprch:2; + uint64_t ext_zqcs_dis:1; + uint64_t int_zqcs_dis:1; + uint64_t auto_dclkdis:1; + uint64_t xor_bank:1; + uint64_t max_write_batch:4; + uint64_t nxm_write_en:1; + uint64_t elev_prio_dis:1; + uint64_t inorder_wr:1; + uint64_t inorder_rd:1; + uint64_t throttle_wr:1; + uint64_t throttle_rd:1; + uint64_t fprch2:2; + uint64_t pocas:1; + uint64_t ddr2t:1; + uint64_t bwcnt:1; + uint64_t rdimm_ena:1; +#else + uint64_t rdimm_ena:1; + uint64_t bwcnt:1; + uint64_t ddr2t:1; + uint64_t pocas:1; + uint64_t fprch2:2; + uint64_t throttle_rd:1; + uint64_t throttle_wr:1; + uint64_t inorder_rd:1; + uint64_t inorder_wr:1; + uint64_t elev_prio_dis:1; + uint64_t nxm_write_en:1; + uint64_t max_write_batch:4; + uint64_t xor_bank:1; + uint64_t auto_dclkdis:1; + uint64_t int_zqcs_dis:1; + uint64_t ext_zqcs_dis:1; + uint64_t bprch:2; + uint64_t wodt_bprch:1; + uint64_t rodt_bprch:1; + uint64_t reserved_24_62:39; + uint64_t scramble_ena:1; +#endif + } cn66xx; + struct cvmx_lmcx_control_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_63_63:1; + uint64_t thrcnt:12; + uint64_t persub:8; + uint64_t thrmax:4; + uint64_t crm_cnt:5; + uint64_t crm_thr:5; + uint64_t crm_max:5; + uint64_t rodt_bprch:1; + uint64_t wodt_bprch:1; + uint64_t bprch:2; + uint64_t ext_zqcs_dis:1; + uint64_t int_zqcs_dis:1; + uint64_t auto_dclkdis:1; + uint64_t xor_bank:1; + uint64_t max_write_batch:4; + uint64_t nxm_write_en:1; + uint64_t elev_prio_dis:1; + uint64_t inorder_wr:1; + uint64_t inorder_rd:1; + uint64_t throttle_wr:1; + uint64_t throttle_rd:1; + uint64_t fprch2:2; + uint64_t pocas:1; + uint64_t ddr2t:1; + uint64_t bwcnt:1; + uint64_t rdimm_ena:1; +#else + uint64_t rdimm_ena:1; + uint64_t bwcnt:1; + uint64_t ddr2t:1; + uint64_t pocas:1; + uint64_t fprch2:2; + uint64_t throttle_rd:1; + uint64_t throttle_wr:1; + uint64_t inorder_rd:1; + uint64_t inorder_wr:1; + uint64_t elev_prio_dis:1; + uint64_t nxm_write_en:1; + uint64_t max_write_batch:4; + uint64_t xor_bank:1; + uint64_t auto_dclkdis:1; + uint64_t int_zqcs_dis:1; + uint64_t ext_zqcs_dis:1; + uint64_t bprch:2; + uint64_t wodt_bprch:1; + uint64_t rodt_bprch:1; + uint64_t crm_max:5; + uint64_t crm_thr:5; + uint64_t crm_cnt:5; + uint64_t thrmax:4; + uint64_t persub:8; + uint64_t thrcnt:12; + uint64_t reserved_63_63:1; +#endif + } cn68xx; + struct cvmx_lmcx_control_cn68xx cn68xxp1; + struct cvmx_lmcx_control_cn66xx cnf71xx; +}; + +union cvmx_lmcx_ctl { + uint64_t u64; + struct cvmx_lmcx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t ddr__nctl:4; + uint64_t ddr__pctl:4; + uint64_t slow_scf:1; + uint64_t xor_bank:1; + uint64_t max_write_batch:4; + uint64_t pll_div2:1; + uint64_t pll_bypass:1; + uint64_t rdimm_ena:1; + uint64_t r2r_slot:1; + uint64_t inorder_mwf:1; + uint64_t inorder_mrf:1; + uint64_t reserved_10_11:2; + uint64_t fprch2:1; + uint64_t bprch:1; + uint64_t sil_lat:2; + uint64_t tskw:2; + uint64_t qs_dic:2; + uint64_t dic:2; +#else + uint64_t dic:2; + uint64_t qs_dic:2; + uint64_t tskw:2; + uint64_t sil_lat:2; + uint64_t bprch:1; + uint64_t fprch2:1; + uint64_t reserved_10_11:2; + uint64_t inorder_mrf:1; + uint64_t inorder_mwf:1; + uint64_t r2r_slot:1; + uint64_t rdimm_ena:1; + uint64_t pll_bypass:1; + uint64_t pll_div2:1; + uint64_t max_write_batch:4; + uint64_t xor_bank:1; + uint64_t slow_scf:1; + uint64_t ddr__pctl:4; + uint64_t ddr__nctl:4; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_ctl_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t ddr__nctl:4; + uint64_t ddr__pctl:4; + uint64_t slow_scf:1; + uint64_t xor_bank:1; + uint64_t max_write_batch:4; + uint64_t pll_div2:1; + uint64_t pll_bypass:1; + uint64_t rdimm_ena:1; + uint64_t r2r_slot:1; + uint64_t inorder_mwf:1; + uint64_t inorder_mrf:1; + uint64_t dreset:1; + uint64_t mode32b:1; + uint64_t fprch2:1; + uint64_t bprch:1; + uint64_t sil_lat:2; + uint64_t tskw:2; + uint64_t qs_dic:2; + uint64_t dic:2; +#else + uint64_t dic:2; + uint64_t qs_dic:2; + uint64_t tskw:2; + uint64_t sil_lat:2; + uint64_t bprch:1; + uint64_t fprch2:1; + uint64_t mode32b:1; + uint64_t dreset:1; + uint64_t inorder_mrf:1; + uint64_t inorder_mwf:1; + uint64_t r2r_slot:1; + uint64_t rdimm_ena:1; + uint64_t pll_bypass:1; + uint64_t pll_div2:1; + uint64_t max_write_batch:4; + uint64_t xor_bank:1; + uint64_t slow_scf:1; + uint64_t ddr__pctl:4; + uint64_t ddr__nctl:4; + uint64_t reserved_32_63:32; +#endif + } cn30xx; + struct cvmx_lmcx_ctl_cn30xx cn31xx; + struct cvmx_lmcx_ctl_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t ddr__nctl:4; + uint64_t ddr__pctl:4; + uint64_t slow_scf:1; + uint64_t xor_bank:1; + uint64_t max_write_batch:4; + uint64_t reserved_16_17:2; + uint64_t rdimm_ena:1; + uint64_t r2r_slot:1; + uint64_t inorder_mwf:1; + uint64_t inorder_mrf:1; + uint64_t set_zero:1; + uint64_t mode128b:1; + uint64_t fprch2:1; + uint64_t bprch:1; + uint64_t sil_lat:2; + uint64_t tskw:2; + uint64_t qs_dic:2; + uint64_t dic:2; +#else + uint64_t dic:2; + uint64_t qs_dic:2; + uint64_t tskw:2; + uint64_t sil_lat:2; + uint64_t bprch:1; + uint64_t fprch2:1; + uint64_t mode128b:1; + uint64_t set_zero:1; + uint64_t inorder_mrf:1; + uint64_t inorder_mwf:1; + uint64_t r2r_slot:1; + uint64_t rdimm_ena:1; + uint64_t reserved_16_17:2; + uint64_t max_write_batch:4; + uint64_t xor_bank:1; + uint64_t slow_scf:1; + uint64_t ddr__pctl:4; + uint64_t ddr__nctl:4; + uint64_t reserved_32_63:32; +#endif + } cn38xx; + struct cvmx_lmcx_ctl_cn38xx cn38xxp2; + struct cvmx_lmcx_ctl_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t ddr__nctl:4; + uint64_t ddr__pctl:4; + uint64_t slow_scf:1; + uint64_t xor_bank:1; + uint64_t max_write_batch:4; + uint64_t reserved_17_17:1; + uint64_t pll_bypass:1; + uint64_t rdimm_ena:1; + uint64_t r2r_slot:1; + uint64_t inorder_mwf:1; + uint64_t inorder_mrf:1; + uint64_t dreset:1; + uint64_t mode32b:1; + uint64_t fprch2:1; + uint64_t bprch:1; + uint64_t sil_lat:2; + uint64_t tskw:2; + uint64_t qs_dic:2; + uint64_t dic:2; +#else + uint64_t dic:2; + uint64_t qs_dic:2; + uint64_t tskw:2; + uint64_t sil_lat:2; + uint64_t bprch:1; + uint64_t fprch2:1; + uint64_t mode32b:1; + uint64_t dreset:1; + uint64_t inorder_mrf:1; + uint64_t inorder_mwf:1; + uint64_t r2r_slot:1; + uint64_t rdimm_ena:1; + uint64_t pll_bypass:1; + uint64_t reserved_17_17:1; + uint64_t max_write_batch:4; + uint64_t xor_bank:1; + uint64_t slow_scf:1; + uint64_t ddr__pctl:4; + uint64_t ddr__nctl:4; + uint64_t reserved_32_63:32; +#endif + } cn50xx; + struct cvmx_lmcx_ctl_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t ddr__nctl:4; + uint64_t ddr__pctl:4; + uint64_t slow_scf:1; + uint64_t xor_bank:1; + uint64_t max_write_batch:4; + uint64_t reserved_16_17:2; + uint64_t rdimm_ena:1; + uint64_t r2r_slot:1; + uint64_t inorder_mwf:1; + uint64_t inorder_mrf:1; + uint64_t dreset:1; + uint64_t mode32b:1; + uint64_t fprch2:1; + uint64_t bprch:1; + uint64_t sil_lat:2; + uint64_t tskw:2; + uint64_t qs_dic:2; + uint64_t dic:2; +#else + uint64_t dic:2; + uint64_t qs_dic:2; + uint64_t tskw:2; + uint64_t sil_lat:2; + uint64_t bprch:1; + uint64_t fprch2:1; + uint64_t mode32b:1; + uint64_t dreset:1; + uint64_t inorder_mrf:1; + uint64_t inorder_mwf:1; + uint64_t r2r_slot:1; + uint64_t rdimm_ena:1; + uint64_t reserved_16_17:2; + uint64_t max_write_batch:4; + uint64_t xor_bank:1; + uint64_t slow_scf:1; + uint64_t ddr__pctl:4; + uint64_t ddr__nctl:4; + uint64_t reserved_32_63:32; +#endif + } cn52xx; + struct cvmx_lmcx_ctl_cn52xx cn52xxp1; + struct cvmx_lmcx_ctl_cn52xx cn56xx; + struct cvmx_lmcx_ctl_cn52xx cn56xxp1; + struct cvmx_lmcx_ctl_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t ddr__nctl:4; + uint64_t ddr__pctl:4; + uint64_t slow_scf:1; + uint64_t xor_bank:1; + uint64_t max_write_batch:4; + uint64_t reserved_16_17:2; + uint64_t rdimm_ena:1; + uint64_t r2r_slot:1; + uint64_t inorder_mwf:1; + uint64_t inorder_mrf:1; + uint64_t dreset:1; + uint64_t mode128b:1; + uint64_t fprch2:1; + uint64_t bprch:1; + uint64_t sil_lat:2; + uint64_t tskw:2; + uint64_t qs_dic:2; + uint64_t dic:2; +#else + uint64_t dic:2; + uint64_t qs_dic:2; + uint64_t tskw:2; + uint64_t sil_lat:2; + uint64_t bprch:1; + uint64_t fprch2:1; + uint64_t mode128b:1; + uint64_t dreset:1; + uint64_t inorder_mrf:1; + uint64_t inorder_mwf:1; + uint64_t r2r_slot:1; + uint64_t rdimm_ena:1; + uint64_t reserved_16_17:2; + uint64_t max_write_batch:4; + uint64_t xor_bank:1; + uint64_t slow_scf:1; + uint64_t ddr__pctl:4; + uint64_t ddr__nctl:4; + uint64_t reserved_32_63:32; +#endif + } cn58xx; + struct cvmx_lmcx_ctl_cn58xx cn58xxp1; +}; + +union cvmx_lmcx_ctl1 { + uint64_t u64; + struct cvmx_lmcx_ctl1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_21_63:43; + uint64_t ecc_adr:1; + uint64_t forcewrite:4; + uint64_t idlepower:3; + uint64_t sequence:3; + uint64_t sil_mode:1; + uint64_t dcc_enable:1; + uint64_t reserved_2_7:6; + uint64_t data_layout:2; +#else + uint64_t data_layout:2; + uint64_t reserved_2_7:6; + uint64_t dcc_enable:1; + uint64_t sil_mode:1; + uint64_t sequence:3; + uint64_t idlepower:3; + uint64_t forcewrite:4; + uint64_t ecc_adr:1; + uint64_t reserved_21_63:43; +#endif + } s; + struct cvmx_lmcx_ctl1_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_2_63:62; + uint64_t data_layout:2; +#else + uint64_t data_layout:2; + uint64_t reserved_2_63:62; +#endif + } cn30xx; + struct cvmx_lmcx_ctl1_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t sil_mode:1; + uint64_t dcc_enable:1; + uint64_t reserved_2_7:6; + uint64_t data_layout:2; +#else + uint64_t data_layout:2; + uint64_t reserved_2_7:6; + uint64_t dcc_enable:1; + uint64_t sil_mode:1; + uint64_t reserved_10_63:54; +#endif + } cn50xx; + struct cvmx_lmcx_ctl1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_21_63:43; + uint64_t ecc_adr:1; + uint64_t forcewrite:4; + uint64_t idlepower:3; + uint64_t sequence:3; + uint64_t sil_mode:1; + uint64_t dcc_enable:1; + uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t dcc_enable:1; + uint64_t sil_mode:1; + uint64_t sequence:3; + uint64_t idlepower:3; + uint64_t forcewrite:4; + uint64_t ecc_adr:1; + uint64_t reserved_21_63:43; +#endif + } cn52xx; + struct cvmx_lmcx_ctl1_cn52xx cn52xxp1; + struct cvmx_lmcx_ctl1_cn52xx cn56xx; + struct cvmx_lmcx_ctl1_cn52xx cn56xxp1; + struct cvmx_lmcx_ctl1_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t sil_mode:1; + uint64_t dcc_enable:1; + uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t dcc_enable:1; + uint64_t sil_mode:1; + uint64_t reserved_10_63:54; +#endif + } cn58xx; + struct cvmx_lmcx_ctl1_cn58xx cn58xxp1; +}; + +union cvmx_lmcx_dclk_cnt { + uint64_t u64; + struct cvmx_lmcx_dclk_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dclkcnt:64; +#else + uint64_t dclkcnt:64; +#endif + } s; + struct cvmx_lmcx_dclk_cnt_s cn61xx; + struct cvmx_lmcx_dclk_cnt_s cn63xx; + struct cvmx_lmcx_dclk_cnt_s cn63xxp1; + struct cvmx_lmcx_dclk_cnt_s cn66xx; + struct cvmx_lmcx_dclk_cnt_s cn68xx; + struct cvmx_lmcx_dclk_cnt_s cn68xxp1; + struct cvmx_lmcx_dclk_cnt_s cnf71xx; +}; + +union cvmx_lmcx_dclk_cnt_hi { + uint64_t u64; + struct cvmx_lmcx_dclk_cnt_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t dclkcnt_hi:32; +#else + uint64_t dclkcnt_hi:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_dclk_cnt_hi_s cn30xx; + struct cvmx_lmcx_dclk_cnt_hi_s cn31xx; + struct cvmx_lmcx_dclk_cnt_hi_s cn38xx; + struct cvmx_lmcx_dclk_cnt_hi_s cn38xxp2; + struct cvmx_lmcx_dclk_cnt_hi_s cn50xx; + struct cvmx_lmcx_dclk_cnt_hi_s cn52xx; + struct cvmx_lmcx_dclk_cnt_hi_s cn52xxp1; + struct cvmx_lmcx_dclk_cnt_hi_s cn56xx; + struct cvmx_lmcx_dclk_cnt_hi_s cn56xxp1; + struct cvmx_lmcx_dclk_cnt_hi_s cn58xx; + struct cvmx_lmcx_dclk_cnt_hi_s cn58xxp1; +}; + +union cvmx_lmcx_dclk_cnt_lo { + uint64_t u64; + struct cvmx_lmcx_dclk_cnt_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t dclkcnt_lo:32; +#else + uint64_t dclkcnt_lo:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_dclk_cnt_lo_s cn30xx; + struct cvmx_lmcx_dclk_cnt_lo_s cn31xx; + struct cvmx_lmcx_dclk_cnt_lo_s cn38xx; + struct cvmx_lmcx_dclk_cnt_lo_s cn38xxp2; + struct cvmx_lmcx_dclk_cnt_lo_s cn50xx; + struct cvmx_lmcx_dclk_cnt_lo_s cn52xx; + struct cvmx_lmcx_dclk_cnt_lo_s cn52xxp1; + struct cvmx_lmcx_dclk_cnt_lo_s cn56xx; + struct cvmx_lmcx_dclk_cnt_lo_s cn56xxp1; + struct cvmx_lmcx_dclk_cnt_lo_s cn58xx; + struct cvmx_lmcx_dclk_cnt_lo_s cn58xxp1; +}; + +union cvmx_lmcx_dclk_ctl { + uint64_t u64; + struct cvmx_lmcx_dclk_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_8_63:56; + uint64_t off90_ena:1; + uint64_t dclk90_byp:1; + uint64_t dclk90_ld:1; + uint64_t dclk90_vlu:5; +#else + uint64_t dclk90_vlu:5; + uint64_t dclk90_ld:1; + uint64_t dclk90_byp:1; + uint64_t off90_ena:1; + uint64_t reserved_8_63:56; +#endif + } s; + struct cvmx_lmcx_dclk_ctl_s cn56xx; + struct cvmx_lmcx_dclk_ctl_s cn56xxp1; +}; + +union cvmx_lmcx_ddr2_ctl { + uint64_t u64; + struct cvmx_lmcx_ddr2_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t bank8:1; + uint64_t burst8:1; + uint64_t addlat:3; + uint64_t pocas:1; + uint64_t bwcnt:1; + uint64_t twr:3; + uint64_t silo_hc:1; + uint64_t ddr_eof:4; + uint64_t tfaw:5; + uint64_t crip_mode:1; + uint64_t ddr2t:1; + uint64_t odt_ena:1; + uint64_t qdll_ena:1; + uint64_t dll90_vlu:5; + uint64_t dll90_byp:1; + uint64_t rdqs:1; + uint64_t ddr2:1; +#else + uint64_t ddr2:1; + uint64_t rdqs:1; + uint64_t dll90_byp:1; + uint64_t dll90_vlu:5; + uint64_t qdll_ena:1; + uint64_t odt_ena:1; + uint64_t ddr2t:1; + uint64_t crip_mode:1; + uint64_t tfaw:5; + uint64_t ddr_eof:4; + uint64_t silo_hc:1; + uint64_t twr:3; + uint64_t bwcnt:1; + uint64_t pocas:1; + uint64_t addlat:3; + uint64_t burst8:1; + uint64_t bank8:1; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_ddr2_ctl_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t bank8:1; + uint64_t burst8:1; + uint64_t addlat:3; + uint64_t pocas:1; + uint64_t bwcnt:1; + uint64_t twr:3; + uint64_t silo_hc:1; + uint64_t ddr_eof:4; + uint64_t tfaw:5; + uint64_t crip_mode:1; + uint64_t ddr2t:1; + uint64_t odt_ena:1; + uint64_t qdll_ena:1; + uint64_t dll90_vlu:5; + uint64_t dll90_byp:1; + uint64_t reserved_1_1:1; + uint64_t ddr2:1; +#else + uint64_t ddr2:1; + uint64_t reserved_1_1:1; + uint64_t dll90_byp:1; + uint64_t dll90_vlu:5; + uint64_t qdll_ena:1; + uint64_t odt_ena:1; + uint64_t ddr2t:1; + uint64_t crip_mode:1; + uint64_t tfaw:5; + uint64_t ddr_eof:4; + uint64_t silo_hc:1; + uint64_t twr:3; + uint64_t bwcnt:1; + uint64_t pocas:1; + uint64_t addlat:3; + uint64_t burst8:1; + uint64_t bank8:1; + uint64_t reserved_32_63:32; +#endif + } cn30xx; + struct cvmx_lmcx_ddr2_ctl_cn30xx cn31xx; + struct cvmx_lmcx_ddr2_ctl_s cn38xx; + struct cvmx_lmcx_ddr2_ctl_s cn38xxp2; + struct cvmx_lmcx_ddr2_ctl_s cn50xx; + struct cvmx_lmcx_ddr2_ctl_s cn52xx; + struct cvmx_lmcx_ddr2_ctl_s cn52xxp1; + struct cvmx_lmcx_ddr2_ctl_s cn56xx; + struct cvmx_lmcx_ddr2_ctl_s cn56xxp1; + struct cvmx_lmcx_ddr2_ctl_s cn58xx; + struct cvmx_lmcx_ddr2_ctl_s cn58xxp1; +}; + +union cvmx_lmcx_ddr_pll_ctl { + uint64_t u64; + struct cvmx_lmcx_ddr_pll_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_27_63:37; + uint64_t jtg_test_mode:1; + uint64_t dfm_div_reset:1; + uint64_t dfm_ps_en:3; + uint64_t ddr_div_reset:1; + uint64_t ddr_ps_en:3; + uint64_t diffamp:4; + uint64_t cps:3; + uint64_t cpb:3; + uint64_t reset_n:1; + uint64_t clkf:7; +#else + uint64_t clkf:7; + uint64_t reset_n:1; + uint64_t cpb:3; + uint64_t cps:3; + uint64_t diffamp:4; + uint64_t ddr_ps_en:3; + uint64_t ddr_div_reset:1; + uint64_t dfm_ps_en:3; + uint64_t dfm_div_reset:1; + uint64_t jtg_test_mode:1; + uint64_t reserved_27_63:37; +#endif + } s; + struct cvmx_lmcx_ddr_pll_ctl_s cn61xx; + struct cvmx_lmcx_ddr_pll_ctl_s cn63xx; + struct cvmx_lmcx_ddr_pll_ctl_s cn63xxp1; + struct cvmx_lmcx_ddr_pll_ctl_s cn66xx; + struct cvmx_lmcx_ddr_pll_ctl_s cn68xx; + struct cvmx_lmcx_ddr_pll_ctl_s cn68xxp1; + struct cvmx_lmcx_ddr_pll_ctl_s cnf71xx; +}; + +union cvmx_lmcx_delay_cfg { + uint64_t u64; + struct cvmx_lmcx_delay_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t dq:5; + uint64_t cmd:5; + uint64_t clk:5; +#else + uint64_t clk:5; + uint64_t cmd:5; + uint64_t dq:5; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_lmcx_delay_cfg_s cn30xx; + struct cvmx_lmcx_delay_cfg_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_14_63:50; + uint64_t dq:4; + uint64_t reserved_9_9:1; + uint64_t cmd:4; + uint64_t reserved_4_4:1; + uint64_t clk:4; +#else + uint64_t clk:4; + uint64_t reserved_4_4:1; + uint64_t cmd:4; + uint64_t reserved_9_9:1; + uint64_t dq:4; + uint64_t reserved_14_63:50; +#endif + } cn38xx; + struct cvmx_lmcx_delay_cfg_cn38xx cn50xx; + struct cvmx_lmcx_delay_cfg_cn38xx cn52xx; + struct cvmx_lmcx_delay_cfg_cn38xx cn52xxp1; + struct cvmx_lmcx_delay_cfg_cn38xx cn56xx; + struct cvmx_lmcx_delay_cfg_cn38xx cn56xxp1; + struct cvmx_lmcx_delay_cfg_cn38xx cn58xx; + struct cvmx_lmcx_delay_cfg_cn38xx cn58xxp1; +}; + +union cvmx_lmcx_dimmx_params { + uint64_t u64; + struct cvmx_lmcx_dimmx_params_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rc15:4; + uint64_t rc14:4; + uint64_t rc13:4; + uint64_t rc12:4; + uint64_t rc11:4; + uint64_t rc10:4; + uint64_t rc9:4; + uint64_t rc8:4; + uint64_t rc7:4; + uint64_t rc6:4; + uint64_t rc5:4; + uint64_t rc4:4; + uint64_t rc3:4; + uint64_t rc2:4; + uint64_t rc1:4; + uint64_t rc0:4; +#else + uint64_t rc0:4; + uint64_t rc1:4; + uint64_t rc2:4; + uint64_t rc3:4; + uint64_t rc4:4; + uint64_t rc5:4; + uint64_t rc6:4; + uint64_t rc7:4; + uint64_t rc8:4; + uint64_t rc9:4; + uint64_t rc10:4; + uint64_t rc11:4; + uint64_t rc12:4; + uint64_t rc13:4; + uint64_t rc14:4; + uint64_t rc15:4; +#endif + } s; + struct cvmx_lmcx_dimmx_params_s cn61xx; + struct cvmx_lmcx_dimmx_params_s cn63xx; + struct cvmx_lmcx_dimmx_params_s cn63xxp1; + struct cvmx_lmcx_dimmx_params_s cn66xx; + struct cvmx_lmcx_dimmx_params_s cn68xx; + struct cvmx_lmcx_dimmx_params_s cn68xxp1; + struct cvmx_lmcx_dimmx_params_s cnf71xx; +}; + +union cvmx_lmcx_dimm_ctl { + uint64_t u64; + struct cvmx_lmcx_dimm_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_46_63:18; + uint64_t parity:1; + uint64_t tcws:13; + uint64_t dimm1_wmask:16; + uint64_t dimm0_wmask:16; +#else + uint64_t dimm0_wmask:16; + uint64_t dimm1_wmask:16; + uint64_t tcws:13; + uint64_t parity:1; + uint64_t reserved_46_63:18; +#endif + } s; + struct cvmx_lmcx_dimm_ctl_s cn61xx; + struct cvmx_lmcx_dimm_ctl_s cn63xx; + struct cvmx_lmcx_dimm_ctl_s cn63xxp1; + struct cvmx_lmcx_dimm_ctl_s cn66xx; + struct cvmx_lmcx_dimm_ctl_s cn68xx; + struct cvmx_lmcx_dimm_ctl_s cn68xxp1; + struct cvmx_lmcx_dimm_ctl_s cnf71xx; +}; + +union cvmx_lmcx_dll_ctl { + uint64_t u64; + struct cvmx_lmcx_dll_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_8_63:56; + uint64_t dreset:1; + uint64_t dll90_byp:1; + uint64_t dll90_ena:1; + uint64_t dll90_vlu:5; +#else + uint64_t dll90_vlu:5; + uint64_t dll90_ena:1; + uint64_t dll90_byp:1; + uint64_t dreset:1; + uint64_t reserved_8_63:56; +#endif + } s; + struct cvmx_lmcx_dll_ctl_s cn52xx; + struct cvmx_lmcx_dll_ctl_s cn52xxp1; + struct cvmx_lmcx_dll_ctl_s cn56xx; + struct cvmx_lmcx_dll_ctl_s cn56xxp1; +}; + +union cvmx_lmcx_dll_ctl2 { + uint64_t u64; + struct cvmx_lmcx_dll_ctl2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t intf_en:1; + uint64_t dll_bringup:1; + uint64_t dreset:1; + uint64_t quad_dll_ena:1; + uint64_t byp_sel:4; + uint64_t byp_setting:8; +#else + uint64_t byp_setting:8; + uint64_t byp_sel:4; + uint64_t quad_dll_ena:1; + uint64_t dreset:1; + uint64_t dll_bringup:1; + uint64_t intf_en:1; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_lmcx_dll_ctl2_s cn61xx; + struct cvmx_lmcx_dll_ctl2_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t dll_bringup:1; + uint64_t dreset:1; + uint64_t quad_dll_ena:1; + uint64_t byp_sel:4; + uint64_t byp_setting:8; +#else + uint64_t byp_setting:8; + uint64_t byp_sel:4; + uint64_t quad_dll_ena:1; + uint64_t dreset:1; + uint64_t dll_bringup:1; + uint64_t reserved_15_63:49; +#endif + } cn63xx; + struct cvmx_lmcx_dll_ctl2_cn63xx cn63xxp1; + struct cvmx_lmcx_dll_ctl2_cn63xx cn66xx; + struct cvmx_lmcx_dll_ctl2_s cn68xx; + struct cvmx_lmcx_dll_ctl2_s cn68xxp1; + struct cvmx_lmcx_dll_ctl2_s cnf71xx; +}; + +union cvmx_lmcx_dll_ctl3 { + uint64_t u64; + struct cvmx_lmcx_dll_ctl3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_41_63:23; + uint64_t dclk90_fwd:1; + uint64_t ddr_90_dly_byp:1; + uint64_t dclk90_recal_dis:1; + uint64_t dclk90_byp_sel:1; + uint64_t dclk90_byp_setting:8; + uint64_t dll_fast:1; + uint64_t dll90_setting:8; + uint64_t fine_tune_mode:1; + uint64_t dll_mode:1; + uint64_t dll90_byte_sel:4; + uint64_t offset_ena:1; + uint64_t load_offset:1; + uint64_t mode_sel:2; + uint64_t byte_sel:4; + uint64_t offset:6; +#else + uint64_t offset:6; + uint64_t byte_sel:4; + uint64_t mode_sel:2; + uint64_t load_offset:1; + uint64_t offset_ena:1; + uint64_t dll90_byte_sel:4; + uint64_t dll_mode:1; + uint64_t fine_tune_mode:1; + uint64_t dll90_setting:8; + uint64_t dll_fast:1; + uint64_t dclk90_byp_setting:8; + uint64_t dclk90_byp_sel:1; + uint64_t dclk90_recal_dis:1; + uint64_t ddr_90_dly_byp:1; + uint64_t dclk90_fwd:1; + uint64_t reserved_41_63:23; +#endif + } s; + struct cvmx_lmcx_dll_ctl3_s cn61xx; + struct cvmx_lmcx_dll_ctl3_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t dll_fast:1; + uint64_t dll90_setting:8; + uint64_t fine_tune_mode:1; + uint64_t dll_mode:1; + uint64_t dll90_byte_sel:4; + uint64_t offset_ena:1; + uint64_t load_offset:1; + uint64_t mode_sel:2; + uint64_t byte_sel:4; + uint64_t offset:6; +#else + uint64_t offset:6; + uint64_t byte_sel:4; + uint64_t mode_sel:2; + uint64_t load_offset:1; + uint64_t offset_ena:1; + uint64_t dll90_byte_sel:4; + uint64_t dll_mode:1; + uint64_t fine_tune_mode:1; + uint64_t dll90_setting:8; + uint64_t dll_fast:1; + uint64_t reserved_29_63:35; +#endif + } cn63xx; + struct cvmx_lmcx_dll_ctl3_cn63xx cn63xxp1; + struct cvmx_lmcx_dll_ctl3_cn63xx cn66xx; + struct cvmx_lmcx_dll_ctl3_s cn68xx; + struct cvmx_lmcx_dll_ctl3_s cn68xxp1; + struct cvmx_lmcx_dll_ctl3_s cnf71xx; +}; + +union cvmx_lmcx_dual_memcfg { + uint64_t u64; + struct cvmx_lmcx_dual_memcfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t bank8:1; + uint64_t row_lsb:3; + uint64_t reserved_8_15:8; + uint64_t cs_mask:8; +#else + uint64_t cs_mask:8; + uint64_t reserved_8_15:8; + uint64_t row_lsb:3; + uint64_t bank8:1; + uint64_t reserved_20_63:44; +#endif + } s; + struct cvmx_lmcx_dual_memcfg_s cn50xx; + struct cvmx_lmcx_dual_memcfg_s cn52xx; + struct cvmx_lmcx_dual_memcfg_s cn52xxp1; + struct cvmx_lmcx_dual_memcfg_s cn56xx; + struct cvmx_lmcx_dual_memcfg_s cn56xxp1; + struct cvmx_lmcx_dual_memcfg_s cn58xx; + struct cvmx_lmcx_dual_memcfg_s cn58xxp1; + struct cvmx_lmcx_dual_memcfg_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_19_63:45; + uint64_t row_lsb:3; + uint64_t reserved_8_15:8; + uint64_t cs_mask:8; +#else + uint64_t cs_mask:8; + uint64_t reserved_8_15:8; + uint64_t row_lsb:3; + uint64_t reserved_19_63:45; +#endif + } cn61xx; + struct cvmx_lmcx_dual_memcfg_cn61xx cn63xx; + struct cvmx_lmcx_dual_memcfg_cn61xx cn63xxp1; + struct cvmx_lmcx_dual_memcfg_cn61xx cn66xx; + struct cvmx_lmcx_dual_memcfg_cn61xx cn68xx; + struct cvmx_lmcx_dual_memcfg_cn61xx cn68xxp1; + struct cvmx_lmcx_dual_memcfg_cn61xx cnf71xx; +}; + +union cvmx_lmcx_ecc_synd { + uint64_t u64; + struct cvmx_lmcx_ecc_synd_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t mrdsyn3:8; + uint64_t mrdsyn2:8; + uint64_t mrdsyn1:8; + uint64_t mrdsyn0:8; +#else + uint64_t mrdsyn0:8; + uint64_t mrdsyn1:8; + uint64_t mrdsyn2:8; + uint64_t mrdsyn3:8; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_ecc_synd_s cn30xx; + struct cvmx_lmcx_ecc_synd_s cn31xx; + struct cvmx_lmcx_ecc_synd_s cn38xx; + struct cvmx_lmcx_ecc_synd_s cn38xxp2; + struct cvmx_lmcx_ecc_synd_s cn50xx; + struct cvmx_lmcx_ecc_synd_s cn52xx; + struct cvmx_lmcx_ecc_synd_s cn52xxp1; + struct cvmx_lmcx_ecc_synd_s cn56xx; + struct cvmx_lmcx_ecc_synd_s cn56xxp1; + struct cvmx_lmcx_ecc_synd_s cn58xx; + struct cvmx_lmcx_ecc_synd_s cn58xxp1; + struct cvmx_lmcx_ecc_synd_s cn61xx; + struct cvmx_lmcx_ecc_synd_s cn63xx; + struct cvmx_lmcx_ecc_synd_s cn63xxp1; + struct cvmx_lmcx_ecc_synd_s cn66xx; + struct cvmx_lmcx_ecc_synd_s cn68xx; + struct cvmx_lmcx_ecc_synd_s cn68xxp1; + struct cvmx_lmcx_ecc_synd_s cnf71xx; +}; + +union cvmx_lmcx_fadr { + uint64_t u64; + struct cvmx_lmcx_fadr_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif + } s; + struct cvmx_lmcx_fadr_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t fdimm:2; + uint64_t fbunk:1; + uint64_t fbank:3; + uint64_t frow:14; + uint64_t fcol:12; +#else + uint64_t fcol:12; + uint64_t frow:14; + uint64_t fbank:3; + uint64_t fbunk:1; + uint64_t fdimm:2; + uint64_t reserved_32_63:32; +#endif + } cn30xx; + struct cvmx_lmcx_fadr_cn30xx cn31xx; + struct cvmx_lmcx_fadr_cn30xx cn38xx; + struct cvmx_lmcx_fadr_cn30xx cn38xxp2; + struct cvmx_lmcx_fadr_cn30xx cn50xx; + struct cvmx_lmcx_fadr_cn30xx cn52xx; + struct cvmx_lmcx_fadr_cn30xx cn52xxp1; + struct cvmx_lmcx_fadr_cn30xx cn56xx; + struct cvmx_lmcx_fadr_cn30xx cn56xxp1; + struct cvmx_lmcx_fadr_cn30xx cn58xx; + struct cvmx_lmcx_fadr_cn30xx cn58xxp1; + struct cvmx_lmcx_fadr_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_36_63:28; + uint64_t fdimm:2; + uint64_t fbunk:1; + uint64_t fbank:3; + uint64_t frow:16; + uint64_t fcol:14; +#else + uint64_t fcol:14; + uint64_t frow:16; + uint64_t fbank:3; + uint64_t fbunk:1; + uint64_t fdimm:2; + uint64_t reserved_36_63:28; +#endif + } cn61xx; + struct cvmx_lmcx_fadr_cn61xx cn63xx; + struct cvmx_lmcx_fadr_cn61xx cn63xxp1; + struct cvmx_lmcx_fadr_cn61xx cn66xx; + struct cvmx_lmcx_fadr_cn61xx cn68xx; + struct cvmx_lmcx_fadr_cn61xx cn68xxp1; + struct cvmx_lmcx_fadr_cn61xx cnf71xx; +}; + +union cvmx_lmcx_ifb_cnt { + uint64_t u64; + struct cvmx_lmcx_ifb_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t ifbcnt:64; +#else + uint64_t ifbcnt:64; +#endif + } s; + struct cvmx_lmcx_ifb_cnt_s cn61xx; + struct cvmx_lmcx_ifb_cnt_s cn63xx; + struct cvmx_lmcx_ifb_cnt_s cn63xxp1; + struct cvmx_lmcx_ifb_cnt_s cn66xx; + struct cvmx_lmcx_ifb_cnt_s cn68xx; + struct cvmx_lmcx_ifb_cnt_s cn68xxp1; + struct cvmx_lmcx_ifb_cnt_s cnf71xx; +}; + +union cvmx_lmcx_ifb_cnt_hi { + uint64_t u64; + struct cvmx_lmcx_ifb_cnt_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t ifbcnt_hi:32; +#else + uint64_t ifbcnt_hi:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_ifb_cnt_hi_s cn30xx; + struct cvmx_lmcx_ifb_cnt_hi_s cn31xx; + struct cvmx_lmcx_ifb_cnt_hi_s cn38xx; + struct cvmx_lmcx_ifb_cnt_hi_s cn38xxp2; + struct cvmx_lmcx_ifb_cnt_hi_s cn50xx; + struct cvmx_lmcx_ifb_cnt_hi_s cn52xx; + struct cvmx_lmcx_ifb_cnt_hi_s cn52xxp1; + struct cvmx_lmcx_ifb_cnt_hi_s cn56xx; + struct cvmx_lmcx_ifb_cnt_hi_s cn56xxp1; + struct cvmx_lmcx_ifb_cnt_hi_s cn58xx; + struct cvmx_lmcx_ifb_cnt_hi_s cn58xxp1; +}; + +union cvmx_lmcx_ifb_cnt_lo { + uint64_t u64; + struct cvmx_lmcx_ifb_cnt_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t ifbcnt_lo:32; +#else + uint64_t ifbcnt_lo:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_ifb_cnt_lo_s cn30xx; + struct cvmx_lmcx_ifb_cnt_lo_s cn31xx; + struct cvmx_lmcx_ifb_cnt_lo_s cn38xx; + struct cvmx_lmcx_ifb_cnt_lo_s cn38xxp2; + struct cvmx_lmcx_ifb_cnt_lo_s cn50xx; + struct cvmx_lmcx_ifb_cnt_lo_s cn52xx; + struct cvmx_lmcx_ifb_cnt_lo_s cn52xxp1; + struct cvmx_lmcx_ifb_cnt_lo_s cn56xx; + struct cvmx_lmcx_ifb_cnt_lo_s cn56xxp1; + struct cvmx_lmcx_ifb_cnt_lo_s cn58xx; + struct cvmx_lmcx_ifb_cnt_lo_s cn58xxp1; +}; + +union cvmx_lmcx_int { + uint64_t u64; + struct cvmx_lmcx_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_9_63:55; + uint64_t ded_err:4; + uint64_t sec_err:4; + uint64_t nxm_wr_err:1; +#else + uint64_t nxm_wr_err:1; + uint64_t sec_err:4; + uint64_t ded_err:4; + uint64_t reserved_9_63:55; +#endif + } s; + struct cvmx_lmcx_int_s cn61xx; + struct cvmx_lmcx_int_s cn63xx; + struct cvmx_lmcx_int_s cn63xxp1; + struct cvmx_lmcx_int_s cn66xx; + struct cvmx_lmcx_int_s cn68xx; + struct cvmx_lmcx_int_s cn68xxp1; + struct cvmx_lmcx_int_s cnf71xx; +}; + +union cvmx_lmcx_int_en { + uint64_t u64; + struct cvmx_lmcx_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_3_63:61; + uint64_t intr_ded_ena:1; + uint64_t intr_sec_ena:1; + uint64_t intr_nxm_wr_ena:1; +#else + uint64_t intr_nxm_wr_ena:1; + uint64_t intr_sec_ena:1; + uint64_t intr_ded_ena:1; + uint64_t reserved_3_63:61; +#endif + } s; + struct cvmx_lmcx_int_en_s cn61xx; + struct cvmx_lmcx_int_en_s cn63xx; + struct cvmx_lmcx_int_en_s cn63xxp1; + struct cvmx_lmcx_int_en_s cn66xx; + struct cvmx_lmcx_int_en_s cn68xx; + struct cvmx_lmcx_int_en_s cn68xxp1; + struct cvmx_lmcx_int_en_s cnf71xx; +}; + +union cvmx_lmcx_mem_cfg0 { + uint64_t u64; + struct cvmx_lmcx_mem_cfg0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t reset:1; + uint64_t silo_qc:1; + uint64_t bunk_ena:1; + uint64_t ded_err:4; + uint64_t sec_err:4; + uint64_t intr_ded_ena:1; + uint64_t intr_sec_ena:1; + uint64_t tcl:4; + uint64_t ref_int:6; + uint64_t pbank_lsb:4; + uint64_t row_lsb:3; + uint64_t ecc_ena:1; + uint64_t init_start:1; +#else + uint64_t init_start:1; + uint64_t ecc_ena:1; + uint64_t row_lsb:3; + uint64_t pbank_lsb:4; + uint64_t ref_int:6; + uint64_t tcl:4; + uint64_t intr_sec_ena:1; + uint64_t intr_ded_ena:1; + uint64_t sec_err:4; + uint64_t ded_err:4; + uint64_t bunk_ena:1; + uint64_t silo_qc:1; + uint64_t reset:1; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_mem_cfg0_s cn30xx; + struct cvmx_lmcx_mem_cfg0_s cn31xx; + struct cvmx_lmcx_mem_cfg0_s cn38xx; + struct cvmx_lmcx_mem_cfg0_s cn38xxp2; + struct cvmx_lmcx_mem_cfg0_s cn50xx; + struct cvmx_lmcx_mem_cfg0_s cn52xx; + struct cvmx_lmcx_mem_cfg0_s cn52xxp1; + struct cvmx_lmcx_mem_cfg0_s cn56xx; + struct cvmx_lmcx_mem_cfg0_s cn56xxp1; + struct cvmx_lmcx_mem_cfg0_s cn58xx; + struct cvmx_lmcx_mem_cfg0_s cn58xxp1; +}; + +union cvmx_lmcx_mem_cfg1 { + uint64_t u64; + struct cvmx_lmcx_mem_cfg1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t comp_bypass:1; + uint64_t trrd:3; + uint64_t caslat:3; + uint64_t tmrd:3; + uint64_t trfc:5; + uint64_t trp:4; + uint64_t twtr:4; + uint64_t trcd:4; + uint64_t tras:5; +#else + uint64_t tras:5; + uint64_t trcd:4; + uint64_t twtr:4; + uint64_t trp:4; + uint64_t trfc:5; + uint64_t tmrd:3; + uint64_t caslat:3; + uint64_t trrd:3; + uint64_t comp_bypass:1; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_mem_cfg1_s cn30xx; + struct cvmx_lmcx_mem_cfg1_s cn31xx; + struct cvmx_lmcx_mem_cfg1_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_31_63:33; + uint64_t trrd:3; + uint64_t caslat:3; + uint64_t tmrd:3; + uint64_t trfc:5; + uint64_t trp:4; + uint64_t twtr:4; + uint64_t trcd:4; + uint64_t tras:5; +#else + uint64_t tras:5; + uint64_t trcd:4; + uint64_t twtr:4; + uint64_t trp:4; + uint64_t trfc:5; + uint64_t tmrd:3; + uint64_t caslat:3; + uint64_t trrd:3; + uint64_t reserved_31_63:33; +#endif + } cn38xx; + struct cvmx_lmcx_mem_cfg1_cn38xx cn38xxp2; + struct cvmx_lmcx_mem_cfg1_s cn50xx; + struct cvmx_lmcx_mem_cfg1_cn38xx cn52xx; + struct cvmx_lmcx_mem_cfg1_cn38xx cn52xxp1; + struct cvmx_lmcx_mem_cfg1_cn38xx cn56xx; + struct cvmx_lmcx_mem_cfg1_cn38xx cn56xxp1; + struct cvmx_lmcx_mem_cfg1_cn38xx cn58xx; + struct cvmx_lmcx_mem_cfg1_cn38xx cn58xxp1; +}; + +union cvmx_lmcx_modereg_params0 { + uint64_t u64; + struct cvmx_lmcx_modereg_params0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_25_63:39; + uint64_t ppd:1; + uint64_t wrp:3; + uint64_t dllr:1; + uint64_t tm:1; + uint64_t rbt:1; + uint64_t cl:4; + uint64_t bl:2; + uint64_t qoff:1; + uint64_t tdqs:1; + uint64_t wlev:1; + uint64_t al:2; + uint64_t dll:1; + uint64_t mpr:1; + uint64_t mprloc:2; + uint64_t cwl:3; +#else + uint64_t cwl:3; + uint64_t mprloc:2; + uint64_t mpr:1; + uint64_t dll:1; + uint64_t al:2; + uint64_t wlev:1; + uint64_t tdqs:1; + uint64_t qoff:1; + uint64_t bl:2; + uint64_t cl:4; + uint64_t rbt:1; + uint64_t tm:1; + uint64_t dllr:1; + uint64_t wrp:3; + uint64_t ppd:1; + uint64_t reserved_25_63:39; +#endif + } s; + struct cvmx_lmcx_modereg_params0_s cn61xx; + struct cvmx_lmcx_modereg_params0_s cn63xx; + struct cvmx_lmcx_modereg_params0_s cn63xxp1; + struct cvmx_lmcx_modereg_params0_s cn66xx; + struct cvmx_lmcx_modereg_params0_s cn68xx; + struct cvmx_lmcx_modereg_params0_s cn68xxp1; + struct cvmx_lmcx_modereg_params0_s cnf71xx; +}; + +union cvmx_lmcx_modereg_params1 { + uint64_t u64; + struct cvmx_lmcx_modereg_params1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t rtt_nom_11:3; + uint64_t dic_11:2; + uint64_t rtt_wr_11:2; + uint64_t srt_11:1; + uint64_t asr_11:1; + uint64_t pasr_11:3; + uint64_t rtt_nom_10:3; + uint64_t dic_10:2; + uint64_t rtt_wr_10:2; + uint64_t srt_10:1; + uint64_t asr_10:1; + uint64_t pasr_10:3; + uint64_t rtt_nom_01:3; + uint64_t dic_01:2; + uint64_t rtt_wr_01:2; + uint64_t srt_01:1; + uint64_t asr_01:1; + uint64_t pasr_01:3; + uint64_t rtt_nom_00:3; + uint64_t dic_00:2; + uint64_t rtt_wr_00:2; + uint64_t srt_00:1; + uint64_t asr_00:1; + uint64_t pasr_00:3; +#else + uint64_t pasr_00:3; + uint64_t asr_00:1; + uint64_t srt_00:1; + uint64_t rtt_wr_00:2; + uint64_t dic_00:2; + uint64_t rtt_nom_00:3; + uint64_t pasr_01:3; + uint64_t asr_01:1; + uint64_t srt_01:1; + uint64_t rtt_wr_01:2; + uint64_t dic_01:2; + uint64_t rtt_nom_01:3; + uint64_t pasr_10:3; + uint64_t asr_10:1; + uint64_t srt_10:1; + uint64_t rtt_wr_10:2; + uint64_t dic_10:2; + uint64_t rtt_nom_10:3; + uint64_t pasr_11:3; + uint64_t asr_11:1; + uint64_t srt_11:1; + uint64_t rtt_wr_11:2; + uint64_t dic_11:2; + uint64_t rtt_nom_11:3; + uint64_t reserved_48_63:16; +#endif + } s; + struct cvmx_lmcx_modereg_params1_s cn61xx; + struct cvmx_lmcx_modereg_params1_s cn63xx; + struct cvmx_lmcx_modereg_params1_s cn63xxp1; + struct cvmx_lmcx_modereg_params1_s cn66xx; + struct cvmx_lmcx_modereg_params1_s cn68xx; + struct cvmx_lmcx_modereg_params1_s cn68xxp1; + struct cvmx_lmcx_modereg_params1_s cnf71xx; +}; + +union cvmx_lmcx_nxm { + uint64_t u64; + struct cvmx_lmcx_nxm_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_40_63:24; + uint64_t mem_msb_d3_r1:4; + uint64_t mem_msb_d3_r0:4; + uint64_t mem_msb_d2_r1:4; + uint64_t mem_msb_d2_r0:4; + uint64_t mem_msb_d1_r1:4; + uint64_t mem_msb_d1_r0:4; + uint64_t mem_msb_d0_r1:4; + uint64_t mem_msb_d0_r0:4; + uint64_t cs_mask:8; +#else + uint64_t cs_mask:8; + uint64_t mem_msb_d0_r0:4; + uint64_t mem_msb_d0_r1:4; + uint64_t mem_msb_d1_r0:4; + uint64_t mem_msb_d1_r1:4; + uint64_t mem_msb_d2_r0:4; + uint64_t mem_msb_d2_r1:4; + uint64_t mem_msb_d3_r0:4; + uint64_t mem_msb_d3_r1:4; + uint64_t reserved_40_63:24; +#endif + } s; + struct cvmx_lmcx_nxm_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_8_63:56; + uint64_t cs_mask:8; +#else + uint64_t cs_mask:8; + uint64_t reserved_8_63:56; +#endif + } cn52xx; + struct cvmx_lmcx_nxm_cn52xx cn56xx; + struct cvmx_lmcx_nxm_cn52xx cn58xx; + struct cvmx_lmcx_nxm_s cn61xx; + struct cvmx_lmcx_nxm_s cn63xx; + struct cvmx_lmcx_nxm_s cn63xxp1; + struct cvmx_lmcx_nxm_s cn66xx; + struct cvmx_lmcx_nxm_s cn68xx; + struct cvmx_lmcx_nxm_s cn68xxp1; + struct cvmx_lmcx_nxm_s cnf71xx; +}; + +union cvmx_lmcx_ops_cnt { + uint64_t u64; + struct cvmx_lmcx_ops_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t opscnt:64; +#else + uint64_t opscnt:64; +#endif + } s; + struct cvmx_lmcx_ops_cnt_s cn61xx; + struct cvmx_lmcx_ops_cnt_s cn63xx; + struct cvmx_lmcx_ops_cnt_s cn63xxp1; + struct cvmx_lmcx_ops_cnt_s cn66xx; + struct cvmx_lmcx_ops_cnt_s cn68xx; + struct cvmx_lmcx_ops_cnt_s cn68xxp1; + struct cvmx_lmcx_ops_cnt_s cnf71xx; +}; + +union cvmx_lmcx_ops_cnt_hi { + uint64_t u64; + struct cvmx_lmcx_ops_cnt_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t opscnt_hi:32; +#else + uint64_t opscnt_hi:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_ops_cnt_hi_s cn30xx; + struct cvmx_lmcx_ops_cnt_hi_s cn31xx; + struct cvmx_lmcx_ops_cnt_hi_s cn38xx; + struct cvmx_lmcx_ops_cnt_hi_s cn38xxp2; + struct cvmx_lmcx_ops_cnt_hi_s cn50xx; + struct cvmx_lmcx_ops_cnt_hi_s cn52xx; + struct cvmx_lmcx_ops_cnt_hi_s cn52xxp1; + struct cvmx_lmcx_ops_cnt_hi_s cn56xx; + struct cvmx_lmcx_ops_cnt_hi_s cn56xxp1; + struct cvmx_lmcx_ops_cnt_hi_s cn58xx; + struct cvmx_lmcx_ops_cnt_hi_s cn58xxp1; +}; + +union cvmx_lmcx_ops_cnt_lo { + uint64_t u64; + struct cvmx_lmcx_ops_cnt_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t opscnt_lo:32; +#else + uint64_t opscnt_lo:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_ops_cnt_lo_s cn30xx; + struct cvmx_lmcx_ops_cnt_lo_s cn31xx; + struct cvmx_lmcx_ops_cnt_lo_s cn38xx; + struct cvmx_lmcx_ops_cnt_lo_s cn38xxp2; + struct cvmx_lmcx_ops_cnt_lo_s cn50xx; + struct cvmx_lmcx_ops_cnt_lo_s cn52xx; + struct cvmx_lmcx_ops_cnt_lo_s cn52xxp1; + struct cvmx_lmcx_ops_cnt_lo_s cn56xx; + struct cvmx_lmcx_ops_cnt_lo_s cn56xxp1; + struct cvmx_lmcx_ops_cnt_lo_s cn58xx; + struct cvmx_lmcx_ops_cnt_lo_s cn58xxp1; +}; + +union cvmx_lmcx_phy_ctl { + uint64_t u64; + struct cvmx_lmcx_phy_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t rx_always_on:1; + uint64_t lv_mode:1; + uint64_t ck_tune1:1; + uint64_t ck_dlyout1:4; + uint64_t ck_tune0:1; + uint64_t ck_dlyout0:4; + uint64_t loopback:1; + uint64_t loopback_pos:1; + uint64_t ts_stagger:1; +#else + uint64_t ts_stagger:1; + uint64_t loopback_pos:1; + uint64_t loopback:1; + uint64_t ck_dlyout0:4; + uint64_t ck_tune0:1; + uint64_t ck_dlyout1:4; + uint64_t ck_tune1:1; + uint64_t lv_mode:1; + uint64_t rx_always_on:1; + uint64_t reserved_15_63:49; +#endif + } s; + struct cvmx_lmcx_phy_ctl_s cn61xx; + struct cvmx_lmcx_phy_ctl_s cn63xx; + struct cvmx_lmcx_phy_ctl_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_14_63:50; + uint64_t lv_mode:1; + uint64_t ck_tune1:1; + uint64_t ck_dlyout1:4; + uint64_t ck_tune0:1; + uint64_t ck_dlyout0:4; + uint64_t loopback:1; + uint64_t loopback_pos:1; + uint64_t ts_stagger:1; +#else + uint64_t ts_stagger:1; + uint64_t loopback_pos:1; + uint64_t loopback:1; + uint64_t ck_dlyout0:4; + uint64_t ck_tune0:1; + uint64_t ck_dlyout1:4; + uint64_t ck_tune1:1; + uint64_t lv_mode:1; + uint64_t reserved_14_63:50; +#endif + } cn63xxp1; + struct cvmx_lmcx_phy_ctl_s cn66xx; + struct cvmx_lmcx_phy_ctl_s cn68xx; + struct cvmx_lmcx_phy_ctl_s cn68xxp1; + struct cvmx_lmcx_phy_ctl_s cnf71xx; +}; + +union cvmx_lmcx_pll_bwctl { + uint64_t u64; + struct cvmx_lmcx_pll_bwctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_5_63:59; + uint64_t bwupd:1; + uint64_t bwctl:4; +#else + uint64_t bwctl:4; + uint64_t bwupd:1; + uint64_t reserved_5_63:59; +#endif + } s; + struct cvmx_lmcx_pll_bwctl_s cn30xx; + struct cvmx_lmcx_pll_bwctl_s cn31xx; + struct cvmx_lmcx_pll_bwctl_s cn38xx; + struct cvmx_lmcx_pll_bwctl_s cn38xxp2; +}; + +union cvmx_lmcx_pll_ctl { + uint64_t u64; + struct cvmx_lmcx_pll_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_30_63:34; + uint64_t bypass:1; + uint64_t fasten_n:1; + uint64_t div_reset:1; + uint64_t reset_n:1; + uint64_t clkf:12; + uint64_t clkr:6; + uint64_t reserved_6_7:2; + uint64_t en16:1; + uint64_t en12:1; + uint64_t en8:1; + uint64_t en6:1; + uint64_t en4:1; + uint64_t en2:1; +#else + uint64_t en2:1; + uint64_t en4:1; + uint64_t en6:1; + uint64_t en8:1; + uint64_t en12:1; + uint64_t en16:1; + uint64_t reserved_6_7:2; + uint64_t clkr:6; + uint64_t clkf:12; + uint64_t reset_n:1; + uint64_t div_reset:1; + uint64_t fasten_n:1; + uint64_t bypass:1; + uint64_t reserved_30_63:34; +#endif + } s; + struct cvmx_lmcx_pll_ctl_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t fasten_n:1; + uint64_t div_reset:1; + uint64_t reset_n:1; + uint64_t clkf:12; + uint64_t clkr:6; + uint64_t reserved_6_7:2; + uint64_t en16:1; + uint64_t en12:1; + uint64_t en8:1; + uint64_t en6:1; + uint64_t en4:1; + uint64_t en2:1; +#else + uint64_t en2:1; + uint64_t en4:1; + uint64_t en6:1; + uint64_t en8:1; + uint64_t en12:1; + uint64_t en16:1; + uint64_t reserved_6_7:2; + uint64_t clkr:6; + uint64_t clkf:12; + uint64_t reset_n:1; + uint64_t div_reset:1; + uint64_t fasten_n:1; + uint64_t reserved_29_63:35; +#endif + } cn50xx; + struct cvmx_lmcx_pll_ctl_s cn52xx; + struct cvmx_lmcx_pll_ctl_s cn52xxp1; + struct cvmx_lmcx_pll_ctl_cn50xx cn56xx; + struct cvmx_lmcx_pll_ctl_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_28_63:36; + uint64_t div_reset:1; + uint64_t reset_n:1; + uint64_t clkf:12; + uint64_t clkr:6; + uint64_t reserved_6_7:2; + uint64_t en16:1; + uint64_t en12:1; + uint64_t en8:1; + uint64_t en6:1; + uint64_t en4:1; + uint64_t en2:1; +#else + uint64_t en2:1; + uint64_t en4:1; + uint64_t en6:1; + uint64_t en8:1; + uint64_t en12:1; + uint64_t en16:1; + uint64_t reserved_6_7:2; + uint64_t clkr:6; + uint64_t clkf:12; + uint64_t reset_n:1; + uint64_t div_reset:1; + uint64_t reserved_28_63:36; +#endif + } cn56xxp1; + struct cvmx_lmcx_pll_ctl_cn56xxp1 cn58xx; + struct cvmx_lmcx_pll_ctl_cn56xxp1 cn58xxp1; +}; + +union cvmx_lmcx_pll_status { + uint64_t u64; + struct cvmx_lmcx_pll_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t ddr__nctl:5; + uint64_t ddr__pctl:5; + uint64_t reserved_2_21:20; + uint64_t rfslip:1; + uint64_t fbslip:1; +#else + uint64_t fbslip:1; + uint64_t rfslip:1; + uint64_t reserved_2_21:20; + uint64_t ddr__pctl:5; + uint64_t ddr__nctl:5; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_pll_status_s cn50xx; + struct cvmx_lmcx_pll_status_s cn52xx; + struct cvmx_lmcx_pll_status_s cn52xxp1; + struct cvmx_lmcx_pll_status_s cn56xx; + struct cvmx_lmcx_pll_status_s cn56xxp1; + struct cvmx_lmcx_pll_status_s cn58xx; + struct cvmx_lmcx_pll_status_cn58xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_2_63:62; + uint64_t rfslip:1; + uint64_t fbslip:1; +#else + uint64_t fbslip:1; + uint64_t rfslip:1; + uint64_t reserved_2_63:62; +#endif + } cn58xxp1; +}; + +union cvmx_lmcx_read_level_ctl { + uint64_t u64; + struct cvmx_lmcx_read_level_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_44_63:20; + uint64_t rankmask:4; + uint64_t pattern:8; + uint64_t row:16; + uint64_t col:12; + uint64_t reserved_3_3:1; + uint64_t bnk:3; +#else + uint64_t bnk:3; + uint64_t reserved_3_3:1; + uint64_t col:12; + uint64_t row:16; + uint64_t pattern:8; + uint64_t rankmask:4; + uint64_t reserved_44_63:20; +#endif + } s; + struct cvmx_lmcx_read_level_ctl_s cn52xx; + struct cvmx_lmcx_read_level_ctl_s cn52xxp1; + struct cvmx_lmcx_read_level_ctl_s cn56xx; + struct cvmx_lmcx_read_level_ctl_s cn56xxp1; +}; + +union cvmx_lmcx_read_level_dbg { + uint64_t u64; + struct cvmx_lmcx_read_level_dbg_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t bitmask:16; + uint64_t reserved_4_15:12; + uint64_t byte:4; +#else + uint64_t byte:4; + uint64_t reserved_4_15:12; + uint64_t bitmask:16; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_read_level_dbg_s cn52xx; + struct cvmx_lmcx_read_level_dbg_s cn52xxp1; + struct cvmx_lmcx_read_level_dbg_s cn56xx; + struct cvmx_lmcx_read_level_dbg_s cn56xxp1; +}; + +union cvmx_lmcx_read_level_rankx { + uint64_t u64; + struct cvmx_lmcx_read_level_rankx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_38_63:26; + uint64_t status:2; + uint64_t byte8:4; + uint64_t byte7:4; + uint64_t byte6:4; + uint64_t byte5:4; + uint64_t byte4:4; + uint64_t byte3:4; + uint64_t byte2:4; + uint64_t byte1:4; + uint64_t byte0:4; +#else + uint64_t byte0:4; + uint64_t byte1:4; + uint64_t byte2:4; + uint64_t byte3:4; + uint64_t byte4:4; + uint64_t byte5:4; + uint64_t byte6:4; + uint64_t byte7:4; + uint64_t byte8:4; + uint64_t status:2; + uint64_t reserved_38_63:26; +#endif + } s; + struct cvmx_lmcx_read_level_rankx_s cn52xx; + struct cvmx_lmcx_read_level_rankx_s cn52xxp1; + struct cvmx_lmcx_read_level_rankx_s cn56xx; + struct cvmx_lmcx_read_level_rankx_s cn56xxp1; +}; + +union cvmx_lmcx_reset_ctl { + uint64_t u64; + struct cvmx_lmcx_reset_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t ddr3psv:1; + uint64_t ddr3psoft:1; + uint64_t ddr3pwarm:1; + uint64_t ddr3rst:1; +#else + uint64_t ddr3rst:1; + uint64_t ddr3pwarm:1; + uint64_t ddr3psoft:1; + uint64_t ddr3psv:1; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_lmcx_reset_ctl_s cn61xx; + struct cvmx_lmcx_reset_ctl_s cn63xx; + struct cvmx_lmcx_reset_ctl_s cn63xxp1; + struct cvmx_lmcx_reset_ctl_s cn66xx; + struct cvmx_lmcx_reset_ctl_s cn68xx; + struct cvmx_lmcx_reset_ctl_s cn68xxp1; + struct cvmx_lmcx_reset_ctl_s cnf71xx; +}; + +union cvmx_lmcx_rlevel_ctl { + uint64_t u64; + struct cvmx_lmcx_rlevel_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_22_63:42; + uint64_t delay_unload_3:1; + uint64_t delay_unload_2:1; + uint64_t delay_unload_1:1; + uint64_t delay_unload_0:1; + uint64_t bitmask:8; + uint64_t or_dis:1; + uint64_t offset_en:1; + uint64_t offset:4; + uint64_t byte:4; +#else + uint64_t byte:4; + uint64_t offset:4; + uint64_t offset_en:1; + uint64_t or_dis:1; + uint64_t bitmask:8; + uint64_t delay_unload_0:1; + uint64_t delay_unload_1:1; + uint64_t delay_unload_2:1; + uint64_t delay_unload_3:1; + uint64_t reserved_22_63:42; +#endif + } s; + struct cvmx_lmcx_rlevel_ctl_s cn61xx; + struct cvmx_lmcx_rlevel_ctl_s cn63xx; + struct cvmx_lmcx_rlevel_ctl_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_9_63:55; + uint64_t offset_en:1; + uint64_t offset:4; + uint64_t byte:4; +#else + uint64_t byte:4; + uint64_t offset:4; + uint64_t offset_en:1; + uint64_t reserved_9_63:55; +#endif + } cn63xxp1; + struct cvmx_lmcx_rlevel_ctl_s cn66xx; + struct cvmx_lmcx_rlevel_ctl_s cn68xx; + struct cvmx_lmcx_rlevel_ctl_s cn68xxp1; + struct cvmx_lmcx_rlevel_ctl_s cnf71xx; +}; + +union cvmx_lmcx_rlevel_dbg { + uint64_t u64; + struct cvmx_lmcx_rlevel_dbg_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bitmask:64; +#else + uint64_t bitmask:64; +#endif + } s; + struct cvmx_lmcx_rlevel_dbg_s cn61xx; + struct cvmx_lmcx_rlevel_dbg_s cn63xx; + struct cvmx_lmcx_rlevel_dbg_s cn63xxp1; + struct cvmx_lmcx_rlevel_dbg_s cn66xx; + struct cvmx_lmcx_rlevel_dbg_s cn68xx; + struct cvmx_lmcx_rlevel_dbg_s cn68xxp1; + struct cvmx_lmcx_rlevel_dbg_s cnf71xx; +}; + +union cvmx_lmcx_rlevel_rankx { + uint64_t u64; + struct cvmx_lmcx_rlevel_rankx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t status:2; + uint64_t byte8:6; + uint64_t byte7:6; + uint64_t byte6:6; + uint64_t byte5:6; + uint64_t byte4:6; + uint64_t byte3:6; + uint64_t byte2:6; + uint64_t byte1:6; + uint64_t byte0:6; +#else + uint64_t byte0:6; + uint64_t byte1:6; + uint64_t byte2:6; + uint64_t byte3:6; + uint64_t byte4:6; + uint64_t byte5:6; + uint64_t byte6:6; + uint64_t byte7:6; + uint64_t byte8:6; + uint64_t status:2; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_lmcx_rlevel_rankx_s cn61xx; + struct cvmx_lmcx_rlevel_rankx_s cn63xx; + struct cvmx_lmcx_rlevel_rankx_s cn63xxp1; + struct cvmx_lmcx_rlevel_rankx_s cn66xx; + struct cvmx_lmcx_rlevel_rankx_s cn68xx; + struct cvmx_lmcx_rlevel_rankx_s cn68xxp1; + struct cvmx_lmcx_rlevel_rankx_s cnf71xx; +}; + +union cvmx_lmcx_rodt_comp_ctl { + uint64_t u64; + struct cvmx_lmcx_rodt_comp_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_17_63:47; + uint64_t enable:1; + uint64_t reserved_12_15:4; + uint64_t nctl:4; + uint64_t reserved_5_7:3; + uint64_t pctl:5; +#else + uint64_t pctl:5; + uint64_t reserved_5_7:3; + uint64_t nctl:4; + uint64_t reserved_12_15:4; + uint64_t enable:1; + uint64_t reserved_17_63:47; +#endif + } s; + struct cvmx_lmcx_rodt_comp_ctl_s cn50xx; + struct cvmx_lmcx_rodt_comp_ctl_s cn52xx; + struct cvmx_lmcx_rodt_comp_ctl_s cn52xxp1; + struct cvmx_lmcx_rodt_comp_ctl_s cn56xx; + struct cvmx_lmcx_rodt_comp_ctl_s cn56xxp1; + struct cvmx_lmcx_rodt_comp_ctl_s cn58xx; + struct cvmx_lmcx_rodt_comp_ctl_s cn58xxp1; +}; + +union cvmx_lmcx_rodt_ctl { + uint64_t u64; + struct cvmx_lmcx_rodt_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t rodt_hi3:4; + uint64_t rodt_hi2:4; + uint64_t rodt_hi1:4; + uint64_t rodt_hi0:4; + uint64_t rodt_lo3:4; + uint64_t rodt_lo2:4; + uint64_t rodt_lo1:4; + uint64_t rodt_lo0:4; +#else + uint64_t rodt_lo0:4; + uint64_t rodt_lo1:4; + uint64_t rodt_lo2:4; + uint64_t rodt_lo3:4; + uint64_t rodt_hi0:4; + uint64_t rodt_hi1:4; + uint64_t rodt_hi2:4; + uint64_t rodt_hi3:4; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_rodt_ctl_s cn30xx; + struct cvmx_lmcx_rodt_ctl_s cn31xx; + struct cvmx_lmcx_rodt_ctl_s cn38xx; + struct cvmx_lmcx_rodt_ctl_s cn38xxp2; + struct cvmx_lmcx_rodt_ctl_s cn50xx; + struct cvmx_lmcx_rodt_ctl_s cn52xx; + struct cvmx_lmcx_rodt_ctl_s cn52xxp1; + struct cvmx_lmcx_rodt_ctl_s cn56xx; + struct cvmx_lmcx_rodt_ctl_s cn56xxp1; + struct cvmx_lmcx_rodt_ctl_s cn58xx; + struct cvmx_lmcx_rodt_ctl_s cn58xxp1; +}; + +union cvmx_lmcx_rodt_mask { + uint64_t u64; + struct cvmx_lmcx_rodt_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rodt_d3_r1:8; + uint64_t rodt_d3_r0:8; + uint64_t rodt_d2_r1:8; + uint64_t rodt_d2_r0:8; + uint64_t rodt_d1_r1:8; + uint64_t rodt_d1_r0:8; + uint64_t rodt_d0_r1:8; + uint64_t rodt_d0_r0:8; +#else + uint64_t rodt_d0_r0:8; + uint64_t rodt_d0_r1:8; + uint64_t rodt_d1_r0:8; + uint64_t rodt_d1_r1:8; + uint64_t rodt_d2_r0:8; + uint64_t rodt_d2_r1:8; + uint64_t rodt_d3_r0:8; + uint64_t rodt_d3_r1:8; +#endif + } s; + struct cvmx_lmcx_rodt_mask_s cn61xx; + struct cvmx_lmcx_rodt_mask_s cn63xx; + struct cvmx_lmcx_rodt_mask_s cn63xxp1; + struct cvmx_lmcx_rodt_mask_s cn66xx; + struct cvmx_lmcx_rodt_mask_s cn68xx; + struct cvmx_lmcx_rodt_mask_s cn68xxp1; + struct cvmx_lmcx_rodt_mask_s cnf71xx; +}; + +union cvmx_lmcx_scramble_cfg0 { + uint64_t u64; + struct cvmx_lmcx_scramble_cfg0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t key:64; +#else + uint64_t key:64; +#endif + } s; + struct cvmx_lmcx_scramble_cfg0_s cn61xx; + struct cvmx_lmcx_scramble_cfg0_s cn66xx; + struct cvmx_lmcx_scramble_cfg0_s cnf71xx; +}; + +union cvmx_lmcx_scramble_cfg1 { + uint64_t u64; + struct cvmx_lmcx_scramble_cfg1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t key:64; +#else + uint64_t key:64; +#endif + } s; + struct cvmx_lmcx_scramble_cfg1_s cn61xx; + struct cvmx_lmcx_scramble_cfg1_s cn66xx; + struct cvmx_lmcx_scramble_cfg1_s cnf71xx; +}; + +union cvmx_lmcx_scrambled_fadr { + uint64_t u64; + struct cvmx_lmcx_scrambled_fadr_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_36_63:28; + uint64_t fdimm:2; + uint64_t fbunk:1; + uint64_t fbank:3; + uint64_t frow:16; + uint64_t fcol:14; +#else + uint64_t fcol:14; + uint64_t frow:16; + uint64_t fbank:3; + uint64_t fbunk:1; + uint64_t fdimm:2; + uint64_t reserved_36_63:28; +#endif + } s; + struct cvmx_lmcx_scrambled_fadr_s cn61xx; + struct cvmx_lmcx_scrambled_fadr_s cn66xx; + struct cvmx_lmcx_scrambled_fadr_s cnf71xx; +}; + +union cvmx_lmcx_slot_ctl0 { + uint64_t u64; + struct cvmx_lmcx_slot_ctl0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_24_63:40; + uint64_t w2w_init:6; + uint64_t w2r_init:6; + uint64_t r2w_init:6; + uint64_t r2r_init:6; +#else + uint64_t r2r_init:6; + uint64_t r2w_init:6; + uint64_t w2r_init:6; + uint64_t w2w_init:6; + uint64_t reserved_24_63:40; +#endif + } s; + struct cvmx_lmcx_slot_ctl0_s cn61xx; + struct cvmx_lmcx_slot_ctl0_s cn63xx; + struct cvmx_lmcx_slot_ctl0_s cn63xxp1; + struct cvmx_lmcx_slot_ctl0_s cn66xx; + struct cvmx_lmcx_slot_ctl0_s cn68xx; + struct cvmx_lmcx_slot_ctl0_s cn68xxp1; + struct cvmx_lmcx_slot_ctl0_s cnf71xx; +}; + +union cvmx_lmcx_slot_ctl1 { + uint64_t u64; + struct cvmx_lmcx_slot_ctl1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_24_63:40; + uint64_t w2w_xrank_init:6; + uint64_t w2r_xrank_init:6; + uint64_t r2w_xrank_init:6; + uint64_t r2r_xrank_init:6; +#else + uint64_t r2r_xrank_init:6; + uint64_t r2w_xrank_init:6; + uint64_t w2r_xrank_init:6; + uint64_t w2w_xrank_init:6; + uint64_t reserved_24_63:40; +#endif + } s; + struct cvmx_lmcx_slot_ctl1_s cn61xx; + struct cvmx_lmcx_slot_ctl1_s cn63xx; + struct cvmx_lmcx_slot_ctl1_s cn63xxp1; + struct cvmx_lmcx_slot_ctl1_s cn66xx; + struct cvmx_lmcx_slot_ctl1_s cn68xx; + struct cvmx_lmcx_slot_ctl1_s cn68xxp1; + struct cvmx_lmcx_slot_ctl1_s cnf71xx; +}; + +union cvmx_lmcx_slot_ctl2 { + uint64_t u64; + struct cvmx_lmcx_slot_ctl2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_24_63:40; + uint64_t w2w_xdimm_init:6; + uint64_t w2r_xdimm_init:6; + uint64_t r2w_xdimm_init:6; + uint64_t r2r_xdimm_init:6; +#else + uint64_t r2r_xdimm_init:6; + uint64_t r2w_xdimm_init:6; + uint64_t w2r_xdimm_init:6; + uint64_t w2w_xdimm_init:6; + uint64_t reserved_24_63:40; +#endif + } s; + struct cvmx_lmcx_slot_ctl2_s cn61xx; + struct cvmx_lmcx_slot_ctl2_s cn63xx; + struct cvmx_lmcx_slot_ctl2_s cn63xxp1; + struct cvmx_lmcx_slot_ctl2_s cn66xx; + struct cvmx_lmcx_slot_ctl2_s cn68xx; + struct cvmx_lmcx_slot_ctl2_s cn68xxp1; + struct cvmx_lmcx_slot_ctl2_s cnf71xx; +}; + +union cvmx_lmcx_timing_params0 { + uint64_t u64; + struct cvmx_lmcx_timing_params0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_47_63:17; + uint64_t trp_ext:1; + uint64_t tcksre:4; + uint64_t trp:4; + uint64_t tzqinit:4; + uint64_t tdllk:4; + uint64_t tmod:4; + uint64_t tmrd:4; + uint64_t txpr:4; + uint64_t tcke:4; + uint64_t tzqcs:4; + uint64_t tckeon:10; +#else + uint64_t tckeon:10; + uint64_t tzqcs:4; + uint64_t tcke:4; + uint64_t txpr:4; + uint64_t tmrd:4; + uint64_t tmod:4; + uint64_t tdllk:4; + uint64_t tzqinit:4; + uint64_t trp:4; + uint64_t tcksre:4; + uint64_t trp_ext:1; + uint64_t reserved_47_63:17; +#endif + } s; + struct cvmx_lmcx_timing_params0_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_47_63:17; + uint64_t trp_ext:1; + uint64_t tcksre:4; + uint64_t trp:4; + uint64_t tzqinit:4; + uint64_t tdllk:4; + uint64_t tmod:4; + uint64_t tmrd:4; + uint64_t txpr:4; + uint64_t tcke:4; + uint64_t tzqcs:4; + uint64_t reserved_0_9:10; +#else + uint64_t reserved_0_9:10; + uint64_t tzqcs:4; + uint64_t tcke:4; + uint64_t txpr:4; + uint64_t tmrd:4; + uint64_t tmod:4; + uint64_t tdllk:4; + uint64_t tzqinit:4; + uint64_t trp:4; + uint64_t tcksre:4; + uint64_t trp_ext:1; + uint64_t reserved_47_63:17; +#endif + } cn61xx; + struct cvmx_lmcx_timing_params0_cn61xx cn63xx; + struct cvmx_lmcx_timing_params0_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_46_63:18; + uint64_t tcksre:4; + uint64_t trp:4; + uint64_t tzqinit:4; + uint64_t tdllk:4; + uint64_t tmod:4; + uint64_t tmrd:4; + uint64_t txpr:4; + uint64_t tcke:4; + uint64_t tzqcs:4; + uint64_t tckeon:10; +#else + uint64_t tckeon:10; + uint64_t tzqcs:4; + uint64_t tcke:4; + uint64_t txpr:4; + uint64_t tmrd:4; + uint64_t tmod:4; + uint64_t tdllk:4; + uint64_t tzqinit:4; + uint64_t trp:4; + uint64_t tcksre:4; + uint64_t reserved_46_63:18; +#endif + } cn63xxp1; + struct cvmx_lmcx_timing_params0_cn61xx cn66xx; + struct cvmx_lmcx_timing_params0_cn61xx cn68xx; + struct cvmx_lmcx_timing_params0_cn61xx cn68xxp1; + struct cvmx_lmcx_timing_params0_cn61xx cnf71xx; +}; + +union cvmx_lmcx_timing_params1 { + uint64_t u64; + struct cvmx_lmcx_timing_params1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_47_63:17; + uint64_t tras_ext:1; + uint64_t txpdll:5; + uint64_t tfaw:5; + uint64_t twldqsen:4; + uint64_t twlmrd:4; + uint64_t txp:3; + uint64_t trrd:3; + uint64_t trfc:5; + uint64_t twtr:4; + uint64_t trcd:4; + uint64_t tras:5; + uint64_t tmprr:4; +#else + uint64_t tmprr:4; + uint64_t tras:5; + uint64_t trcd:4; + uint64_t twtr:4; + uint64_t trfc:5; + uint64_t trrd:3; + uint64_t txp:3; + uint64_t twlmrd:4; + uint64_t twldqsen:4; + uint64_t tfaw:5; + uint64_t txpdll:5; + uint64_t tras_ext:1; + uint64_t reserved_47_63:17; +#endif + } s; + struct cvmx_lmcx_timing_params1_s cn61xx; + struct cvmx_lmcx_timing_params1_s cn63xx; + struct cvmx_lmcx_timing_params1_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_46_63:18; + uint64_t txpdll:5; + uint64_t tfaw:5; + uint64_t twldqsen:4; + uint64_t twlmrd:4; + uint64_t txp:3; + uint64_t trrd:3; + uint64_t trfc:5; + uint64_t twtr:4; + uint64_t trcd:4; + uint64_t tras:5; + uint64_t tmprr:4; +#else + uint64_t tmprr:4; + uint64_t tras:5; + uint64_t trcd:4; + uint64_t twtr:4; + uint64_t trfc:5; + uint64_t trrd:3; + uint64_t txp:3; + uint64_t twlmrd:4; + uint64_t twldqsen:4; + uint64_t tfaw:5; + uint64_t txpdll:5; + uint64_t reserved_46_63:18; +#endif + } cn63xxp1; + struct cvmx_lmcx_timing_params1_s cn66xx; + struct cvmx_lmcx_timing_params1_s cn68xx; + struct cvmx_lmcx_timing_params1_s cn68xxp1; + struct cvmx_lmcx_timing_params1_s cnf71xx; +}; + +union cvmx_lmcx_tro_ctl { + uint64_t u64; + struct cvmx_lmcx_tro_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_33_63:31; + uint64_t rclk_cnt:32; + uint64_t treset:1; +#else + uint64_t treset:1; + uint64_t rclk_cnt:32; + uint64_t reserved_33_63:31; +#endif + } s; + struct cvmx_lmcx_tro_ctl_s cn61xx; + struct cvmx_lmcx_tro_ctl_s cn63xx; + struct cvmx_lmcx_tro_ctl_s cn63xxp1; + struct cvmx_lmcx_tro_ctl_s cn66xx; + struct cvmx_lmcx_tro_ctl_s cn68xx; + struct cvmx_lmcx_tro_ctl_s cn68xxp1; + struct cvmx_lmcx_tro_ctl_s cnf71xx; +}; + +union cvmx_lmcx_tro_stat { + uint64_t u64; + struct cvmx_lmcx_tro_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t ring_cnt:32; +#else + uint64_t ring_cnt:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_tro_stat_s cn61xx; + struct cvmx_lmcx_tro_stat_s cn63xx; + struct cvmx_lmcx_tro_stat_s cn63xxp1; + struct cvmx_lmcx_tro_stat_s cn66xx; + struct cvmx_lmcx_tro_stat_s cn68xx; + struct cvmx_lmcx_tro_stat_s cn68xxp1; + struct cvmx_lmcx_tro_stat_s cnf71xx; +}; + +union cvmx_lmcx_wlevel_ctl { + uint64_t u64; + struct cvmx_lmcx_wlevel_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_22_63:42; + uint64_t rtt_nom:3; + uint64_t bitmask:8; + uint64_t or_dis:1; + uint64_t sset:1; + uint64_t lanemask:9; +#else + uint64_t lanemask:9; + uint64_t sset:1; + uint64_t or_dis:1; + uint64_t bitmask:8; + uint64_t rtt_nom:3; + uint64_t reserved_22_63:42; +#endif + } s; + struct cvmx_lmcx_wlevel_ctl_s cn61xx; + struct cvmx_lmcx_wlevel_ctl_s cn63xx; + struct cvmx_lmcx_wlevel_ctl_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_10_63:54; + uint64_t sset:1; + uint64_t lanemask:9; +#else + uint64_t lanemask:9; + uint64_t sset:1; + uint64_t reserved_10_63:54; +#endif + } cn63xxp1; + struct cvmx_lmcx_wlevel_ctl_s cn66xx; + struct cvmx_lmcx_wlevel_ctl_s cn68xx; + struct cvmx_lmcx_wlevel_ctl_s cn68xxp1; + struct cvmx_lmcx_wlevel_ctl_s cnf71xx; +}; + +union cvmx_lmcx_wlevel_dbg { + uint64_t u64; + struct cvmx_lmcx_wlevel_dbg_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t bitmask:8; + uint64_t byte:4; +#else + uint64_t byte:4; + uint64_t bitmask:8; + uint64_t reserved_12_63:52; +#endif + } s; + struct cvmx_lmcx_wlevel_dbg_s cn61xx; + struct cvmx_lmcx_wlevel_dbg_s cn63xx; + struct cvmx_lmcx_wlevel_dbg_s cn63xxp1; + struct cvmx_lmcx_wlevel_dbg_s cn66xx; + struct cvmx_lmcx_wlevel_dbg_s cn68xx; + struct cvmx_lmcx_wlevel_dbg_s cn68xxp1; + struct cvmx_lmcx_wlevel_dbg_s cnf71xx; +}; + +union cvmx_lmcx_wlevel_rankx { + uint64_t u64; + struct cvmx_lmcx_wlevel_rankx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_47_63:17; + uint64_t status:2; + uint64_t byte8:5; + uint64_t byte7:5; + uint64_t byte6:5; + uint64_t byte5:5; + uint64_t byte4:5; + uint64_t byte3:5; + uint64_t byte2:5; + uint64_t byte1:5; + uint64_t byte0:5; +#else + uint64_t byte0:5; + uint64_t byte1:5; + uint64_t byte2:5; + uint64_t byte3:5; + uint64_t byte4:5; + uint64_t byte5:5; + uint64_t byte6:5; + uint64_t byte7:5; + uint64_t byte8:5; + uint64_t status:2; + uint64_t reserved_47_63:17; +#endif + } s; + struct cvmx_lmcx_wlevel_rankx_s cn61xx; + struct cvmx_lmcx_wlevel_rankx_s cn63xx; + struct cvmx_lmcx_wlevel_rankx_s cn63xxp1; + struct cvmx_lmcx_wlevel_rankx_s cn66xx; + struct cvmx_lmcx_wlevel_rankx_s cn68xx; + struct cvmx_lmcx_wlevel_rankx_s cn68xxp1; + struct cvmx_lmcx_wlevel_rankx_s cnf71xx; +}; + +union cvmx_lmcx_wodt_ctl0 { + uint64_t u64; + struct cvmx_lmcx_wodt_ctl0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif + } s; + struct cvmx_lmcx_wodt_ctl0_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wodt_d1_r1:8; + uint64_t wodt_d1_r0:8; + uint64_t wodt_d0_r1:8; + uint64_t wodt_d0_r0:8; +#else + uint64_t wodt_d0_r0:8; + uint64_t wodt_d0_r1:8; + uint64_t wodt_d1_r0:8; + uint64_t wodt_d1_r1:8; + uint64_t reserved_32_63:32; +#endif + } cn30xx; + struct cvmx_lmcx_wodt_ctl0_cn30xx cn31xx; + struct cvmx_lmcx_wodt_ctl0_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wodt_hi3:4; + uint64_t wodt_hi2:4; + uint64_t wodt_hi1:4; + uint64_t wodt_hi0:4; + uint64_t wodt_lo3:4; + uint64_t wodt_lo2:4; + uint64_t wodt_lo1:4; + uint64_t wodt_lo0:4; +#else + uint64_t wodt_lo0:4; + uint64_t wodt_lo1:4; + uint64_t wodt_lo2:4; + uint64_t wodt_lo3:4; + uint64_t wodt_hi0:4; + uint64_t wodt_hi1:4; + uint64_t wodt_hi2:4; + uint64_t wodt_hi3:4; + uint64_t reserved_32_63:32; +#endif + } cn38xx; + struct cvmx_lmcx_wodt_ctl0_cn38xx cn38xxp2; + struct cvmx_lmcx_wodt_ctl0_cn38xx cn50xx; + struct cvmx_lmcx_wodt_ctl0_cn30xx cn52xx; + struct cvmx_lmcx_wodt_ctl0_cn30xx cn52xxp1; + struct cvmx_lmcx_wodt_ctl0_cn30xx cn56xx; + struct cvmx_lmcx_wodt_ctl0_cn30xx cn56xxp1; + struct cvmx_lmcx_wodt_ctl0_cn38xx cn58xx; + struct cvmx_lmcx_wodt_ctl0_cn38xx cn58xxp1; +}; + +union cvmx_lmcx_wodt_ctl1 { + uint64_t u64; + struct cvmx_lmcx_wodt_ctl1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t wodt_d3_r1:8; + uint64_t wodt_d3_r0:8; + uint64_t wodt_d2_r1:8; + uint64_t wodt_d2_r0:8; +#else + uint64_t wodt_d2_r0:8; + uint64_t wodt_d2_r1:8; + uint64_t wodt_d3_r0:8; + uint64_t wodt_d3_r1:8; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_wodt_ctl1_s cn30xx; + struct cvmx_lmcx_wodt_ctl1_s cn31xx; + struct cvmx_lmcx_wodt_ctl1_s cn52xx; + struct cvmx_lmcx_wodt_ctl1_s cn52xxp1; + struct cvmx_lmcx_wodt_ctl1_s cn56xx; + struct cvmx_lmcx_wodt_ctl1_s cn56xxp1; +}; + +union cvmx_lmcx_wodt_mask { + uint64_t u64; + struct cvmx_lmcx_wodt_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t wodt_d3_r1:8; + uint64_t wodt_d3_r0:8; + uint64_t wodt_d2_r1:8; + uint64_t wodt_d2_r0:8; + uint64_t wodt_d1_r1:8; + uint64_t wodt_d1_r0:8; + uint64_t wodt_d0_r1:8; + uint64_t wodt_d0_r0:8; +#else + uint64_t wodt_d0_r0:8; + uint64_t wodt_d0_r1:8; + uint64_t wodt_d1_r0:8; + uint64_t wodt_d1_r1:8; + uint64_t wodt_d2_r0:8; + uint64_t wodt_d2_r1:8; + uint64_t wodt_d3_r0:8; + uint64_t wodt_d3_r1:8; +#endif + } s; + struct cvmx_lmcx_wodt_mask_s cn61xx; + struct cvmx_lmcx_wodt_mask_s cn63xx; + struct cvmx_lmcx_wodt_mask_s cn63xxp1; + struct cvmx_lmcx_wodt_mask_s cn66xx; + struct cvmx_lmcx_wodt_mask_s cn68xx; + struct cvmx_lmcx_wodt_mask_s cn68xxp1; + struct cvmx_lmcx_wodt_mask_s cnf71xx; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-mdio.h b/arch/mips/include/asm/octeon/cvmx-mdio.h index d88ab8d8e37..9f6a4f32a83 100644 --- a/arch/mips/include/asm/octeon/cvmx-mdio.h +++ b/arch/mips/include/asm/octeon/cvmx-mdio.h @@ -35,7 +35,7 @@ #ifndef __CVMX_MIO_H__ #define __CVMX_MIO_H__ -#include "cvmx-smix-defs.h" +#include <asm/octeon/cvmx-smix-defs.h> /** * PHY register 0 from the 802.3 spec @@ -246,21 +246,21 @@ typedef union { } cvmx_mdio_phy_reg_mmd_address_data_t; /* Operating request encodings. */ -#define MDIO_CLAUSE_22_WRITE 0 -#define MDIO_CLAUSE_22_READ 1 +#define MDIO_CLAUSE_22_WRITE 0 +#define MDIO_CLAUSE_22_READ 1 -#define MDIO_CLAUSE_45_ADDRESS 0 -#define MDIO_CLAUSE_45_WRITE 1 +#define MDIO_CLAUSE_45_ADDRESS 0 +#define MDIO_CLAUSE_45_WRITE 1 #define MDIO_CLAUSE_45_READ_INC 2 -#define MDIO_CLAUSE_45_READ 3 +#define MDIO_CLAUSE_45_READ 3 /* MMD identifiers, mostly for accessing devices within XENPAK modules. */ -#define CVMX_MMD_DEVICE_PMA_PMD 1 -#define CVMX_MMD_DEVICE_WIS 2 -#define CVMX_MMD_DEVICE_PCS 3 -#define CVMX_MMD_DEVICE_PHY_XS 4 -#define CVMX_MMD_DEVICE_DTS_XS 5 -#define CVMX_MMD_DEVICE_TC 6 +#define CVMX_MMD_DEVICE_PMA_PMD 1 +#define CVMX_MMD_DEVICE_WIS 2 +#define CVMX_MMD_DEVICE_PCS 3 +#define CVMX_MMD_DEVICE_PHY_XS 4 +#define CVMX_MMD_DEVICE_DTS_XS 5 +#define CVMX_MMD_DEVICE_TC 6 #define CVMX_MMD_DEVICE_CL22_EXT 29 #define CVMX_MMD_DEVICE_VENDOR_1 30 #define CVMX_MMD_DEVICE_VENDOR_2 31 @@ -291,7 +291,7 @@ static inline void __cvmx_mdio_set_clause22_mode(int bus_id) * registers controlling auto negotiation. * * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) - * support multiple busses. + * support multiple busses. * @phy_id: The MII phy id * @location: Register location to read * @@ -328,13 +328,13 @@ static inline int cvmx_mdio_read(int bus_id, int phy_id, int location) * registers controlling auto negotiation. * * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) - * support multiple busses. + * support multiple busses. * @phy_id: The MII phy id * @location: Register location to write * @val: Value to write * * Returns -1 on error - * 0 on success + * 0 on success */ static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val) { @@ -370,7 +370,7 @@ static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val) * read PHY registers controlling auto negotiation. * * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) - * support multiple busses. + * support multiple busses. * @phy_id: The MII phy id * @device: MDIO Managable Device (MMD) id * @location: Register location to read @@ -407,7 +407,7 @@ static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, } while (smi_wr.s.pending && --timeout); if (timeout <= 0) { cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " - "device %2d register %2d TIME OUT(address)\n", + "device %2d register %2d TIME OUT(address)\n", bus_id, phy_id, device, location); return -1; } @@ -425,7 +425,7 @@ static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, if (timeout <= 0) { cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " - "device %2d register %2d TIME OUT(data)\n", + "device %2d register %2d TIME OUT(data)\n", bus_id, phy_id, device, location); return -1; } @@ -434,7 +434,7 @@ static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, return smi_rd.s.dat; else { cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " - "device %2d register %2d INVALID READ\n", + "device %2d register %2d INVALID READ\n", bus_id, phy_id, device, location); return -1; } @@ -445,14 +445,14 @@ static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, * write PHY registers controlling auto negotiation. * * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) - * support multiple busses. + * support multiple busses. * @phy_id: The MII phy id * @device: MDIO Managable Device (MMD) id * @location: Register location to write * @val: Value to write * * Returns -1 on error - * 0 on success + * 0 on success */ static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device, int location, int val) diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h index b1774126736..bb0ae338a46 100644 --- a/arch/mips/include/asm/octeon/cvmx-mio-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -94,6 +94,7 @@ #define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull)) #define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull)) #define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull)) +#define CVMX_MIO_PTP_PHY_1PPS_IN (CVMX_ADD_IO_SEG(0x0001070000000F70ull)) #define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull)) #define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull)) #define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull)) @@ -166,24 +167,44 @@ union cvmx_mio_boot_bist_stat { uint64_t u64; struct cvmx_mio_boot_bist_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif } s; struct cvmx_mio_boot_bist_stat_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t ncbo_1:1; uint64_t ncbo_0:1; uint64_t loc:1; uint64_t ncbi:1; +#else + uint64_t ncbi:1; + uint64_t loc:1; + uint64_t ncbo_0:1; + uint64_t ncbo_1:1; + uint64_t reserved_4_63:60; +#endif } cn30xx; struct cvmx_mio_boot_bist_stat_cn30xx cn31xx; struct cvmx_mio_boot_bist_stat_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t ncbo_0:1; uint64_t loc:1; uint64_t ncbi:1; +#else + uint64_t ncbi:1; + uint64_t loc:1; + uint64_t ncbo_0:1; + uint64_t reserved_3_63:61; +#endif } cn38xx; struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2; struct cvmx_mio_boot_bist_stat_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t pcm_1:1; uint64_t pcm_0:1; @@ -191,72 +212,132 @@ union cvmx_mio_boot_bist_stat { uint64_t ncbo_0:1; uint64_t loc:1; uint64_t ncbi:1; +#else + uint64_t ncbi:1; + uint64_t loc:1; + uint64_t ncbo_0:1; + uint64_t ncbo_1:1; + uint64_t pcm_0:1; + uint64_t pcm_1:1; + uint64_t reserved_6_63:58; +#endif } cn50xx; struct cvmx_mio_boot_bist_stat_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t ndf:2; uint64_t ncbo_0:1; uint64_t dma:1; uint64_t loc:1; uint64_t ncbi:1; +#else + uint64_t ncbi:1; + uint64_t loc:1; + uint64_t dma:1; + uint64_t ncbo_0:1; + uint64_t ndf:2; + uint64_t reserved_6_63:58; +#endif } cn52xx; struct cvmx_mio_boot_bist_stat_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t ncbo_0:1; uint64_t dma:1; uint64_t loc:1; uint64_t ncbi:1; +#else + uint64_t ncbi:1; + uint64_t loc:1; + uint64_t dma:1; + uint64_t ncbo_0:1; + uint64_t reserved_4_63:60; +#endif } cn52xxp1; struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx; struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1; struct cvmx_mio_boot_bist_stat_cn38xx cn58xx; struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1; struct cvmx_mio_boot_bist_stat_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t stat:12; +#else + uint64_t stat:12; + uint64_t reserved_12_63:52; +#endif } cn61xx; struct cvmx_mio_boot_bist_stat_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t stat:9; +#else + uint64_t stat:9; + uint64_t reserved_9_63:55; +#endif } cn63xx; struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1; struct cvmx_mio_boot_bist_stat_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t stat:10; +#else + uint64_t stat:10; + uint64_t reserved_10_63:54; +#endif } cn66xx; struct cvmx_mio_boot_bist_stat_cn66xx cn68xx; struct cvmx_mio_boot_bist_stat_cn66xx cn68xxp1; + struct cvmx_mio_boot_bist_stat_cn61xx cnf71xx; }; union cvmx_mio_boot_comp { uint64_t u64; struct cvmx_mio_boot_comp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif } s; struct cvmx_mio_boot_comp_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pctl:5; uint64_t nctl:5; +#else + uint64_t nctl:5; + uint64_t pctl:5; + uint64_t reserved_10_63:54; +#endif } cn50xx; struct cvmx_mio_boot_comp_cn50xx cn52xx; struct cvmx_mio_boot_comp_cn50xx cn52xxp1; struct cvmx_mio_boot_comp_cn50xx cn56xx; struct cvmx_mio_boot_comp_cn50xx cn56xxp1; struct cvmx_mio_boot_comp_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t pctl:6; uint64_t nctl:6; +#else + uint64_t nctl:6; + uint64_t pctl:6; + uint64_t reserved_12_63:52; +#endif } cn61xx; struct cvmx_mio_boot_comp_cn61xx cn63xx; struct cvmx_mio_boot_comp_cn61xx cn63xxp1; struct cvmx_mio_boot_comp_cn61xx cn66xx; struct cvmx_mio_boot_comp_cn61xx cn68xx; struct cvmx_mio_boot_comp_cn61xx cn68xxp1; + struct cvmx_mio_boot_comp_cn61xx cnf71xx; }; union cvmx_mio_boot_dma_cfgx { uint64_t u64; struct cvmx_mio_boot_dma_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t en:1; uint64_t rw:1; uint64_t clr:1; @@ -267,6 +348,18 @@ union cvmx_mio_boot_dma_cfgx { uint64_t endian:1; uint64_t size:20; uint64_t adr:36; +#else + uint64_t adr:36; + uint64_t size:20; + uint64_t endian:1; + uint64_t swap8:1; + uint64_t swap16:1; + uint64_t swap32:1; + uint64_t reserved_60_60:1; + uint64_t clr:1; + uint64_t rw:1; + uint64_t en:1; +#endif } s; struct cvmx_mio_boot_dma_cfgx_s cn52xx; struct cvmx_mio_boot_dma_cfgx_s cn52xxp1; @@ -278,14 +371,21 @@ union cvmx_mio_boot_dma_cfgx { struct cvmx_mio_boot_dma_cfgx_s cn66xx; struct cvmx_mio_boot_dma_cfgx_s cn68xx; struct cvmx_mio_boot_dma_cfgx_s cn68xxp1; + struct cvmx_mio_boot_dma_cfgx_s cnf71xx; }; union cvmx_mio_boot_dma_intx { uint64_t u64; struct cvmx_mio_boot_dma_intx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dmarq:1; uint64_t done:1; +#else + uint64_t done:1; + uint64_t dmarq:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_boot_dma_intx_s cn52xx; struct cvmx_mio_boot_dma_intx_s cn52xxp1; @@ -297,14 +397,21 @@ union cvmx_mio_boot_dma_intx { struct cvmx_mio_boot_dma_intx_s cn66xx; struct cvmx_mio_boot_dma_intx_s cn68xx; struct cvmx_mio_boot_dma_intx_s cn68xxp1; + struct cvmx_mio_boot_dma_intx_s cnf71xx; }; union cvmx_mio_boot_dma_int_enx { uint64_t u64; struct cvmx_mio_boot_dma_int_enx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dmarq:1; uint64_t done:1; +#else + uint64_t done:1; + uint64_t dmarq:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_boot_dma_int_enx_s cn52xx; struct cvmx_mio_boot_dma_int_enx_s cn52xxp1; @@ -316,11 +423,13 @@ union cvmx_mio_boot_dma_int_enx { struct cvmx_mio_boot_dma_int_enx_s cn66xx; struct cvmx_mio_boot_dma_int_enx_s cn68xx; struct cvmx_mio_boot_dma_int_enx_s cn68xxp1; + struct cvmx_mio_boot_dma_int_enx_s cnf71xx; }; union cvmx_mio_boot_dma_timx { uint64_t u64; struct cvmx_mio_boot_dma_timx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dmack_pi:1; uint64_t dmarq_pi:1; uint64_t tim_mult:2; @@ -336,6 +445,23 @@ union cvmx_mio_boot_dma_timx { uint64_t oe_a:6; uint64_t dmack_s:6; uint64_t dmarq:6; +#else + uint64_t dmarq:6; + uint64_t dmack_s:6; + uint64_t oe_a:6; + uint64_t oe_n:6; + uint64_t we_a:6; + uint64_t we_n:6; + uint64_t dmack_h:6; + uint64_t pause:6; + uint64_t reserved_48_54:7; + uint64_t width:1; + uint64_t ddr:1; + uint64_t rd_dly:3; + uint64_t tim_mult:2; + uint64_t dmarq_pi:1; + uint64_t dmack_pi:1; +#endif } s; struct cvmx_mio_boot_dma_timx_s cn52xx; struct cvmx_mio_boot_dma_timx_s cn52xxp1; @@ -347,14 +473,21 @@ union cvmx_mio_boot_dma_timx { struct cvmx_mio_boot_dma_timx_s cn66xx; struct cvmx_mio_boot_dma_timx_s cn68xx; struct cvmx_mio_boot_dma_timx_s cn68xxp1; + struct cvmx_mio_boot_dma_timx_s cnf71xx; }; union cvmx_mio_boot_err { uint64_t u64; struct cvmx_mio_boot_err_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t wait_err:1; uint64_t adr_err:1; +#else + uint64_t adr_err:1; + uint64_t wait_err:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_boot_err_s cn30xx; struct cvmx_mio_boot_err_s cn31xx; @@ -373,14 +506,21 @@ union cvmx_mio_boot_err { struct cvmx_mio_boot_err_s cn66xx; struct cvmx_mio_boot_err_s cn68xx; struct cvmx_mio_boot_err_s cn68xxp1; + struct cvmx_mio_boot_err_s cnf71xx; }; union cvmx_mio_boot_int { uint64_t u64; struct cvmx_mio_boot_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t wait_int:1; uint64_t adr_int:1; +#else + uint64_t adr_int:1; + uint64_t wait_int:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_boot_int_s cn30xx; struct cvmx_mio_boot_int_s cn31xx; @@ -399,14 +539,21 @@ union cvmx_mio_boot_int { struct cvmx_mio_boot_int_s cn66xx; struct cvmx_mio_boot_int_s cn68xx; struct cvmx_mio_boot_int_s cn68xxp1; + struct cvmx_mio_boot_int_s cnf71xx; }; union cvmx_mio_boot_loc_adr { uint64_t u64; struct cvmx_mio_boot_loc_adr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t adr:5; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t adr:5; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_boot_loc_adr_s cn30xx; struct cvmx_mio_boot_loc_adr_s cn31xx; @@ -425,16 +572,25 @@ union cvmx_mio_boot_loc_adr { struct cvmx_mio_boot_loc_adr_s cn66xx; struct cvmx_mio_boot_loc_adr_s cn68xx; struct cvmx_mio_boot_loc_adr_s cn68xxp1; + struct cvmx_mio_boot_loc_adr_s cnf71xx; }; union cvmx_mio_boot_loc_cfgx { uint64_t u64; struct cvmx_mio_boot_loc_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t en:1; uint64_t reserved_28_30:3; uint64_t base:25; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t base:25; + uint64_t reserved_28_30:3; + uint64_t en:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_boot_loc_cfgx_s cn30xx; struct cvmx_mio_boot_loc_cfgx_s cn31xx; @@ -453,12 +609,17 @@ union cvmx_mio_boot_loc_cfgx { struct cvmx_mio_boot_loc_cfgx_s cn66xx; struct cvmx_mio_boot_loc_cfgx_s cn68xx; struct cvmx_mio_boot_loc_cfgx_s cn68xxp1; + struct cvmx_mio_boot_loc_cfgx_s cnf71xx; }; union cvmx_mio_boot_loc_dat { uint64_t u64; struct cvmx_mio_boot_loc_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; +#else + uint64_t data:64; +#endif } s; struct cvmx_mio_boot_loc_dat_s cn30xx; struct cvmx_mio_boot_loc_dat_s cn31xx; @@ -477,11 +638,13 @@ union cvmx_mio_boot_loc_dat { struct cvmx_mio_boot_loc_dat_s cn66xx; struct cvmx_mio_boot_loc_dat_s cn68xx; struct cvmx_mio_boot_loc_dat_s cn68xxp1; + struct cvmx_mio_boot_loc_dat_s cnf71xx; }; union cvmx_mio_boot_pin_defs { uint64_t u64; struct cvmx_mio_boot_pin_defs_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t user1:16; uint64_t ale:1; @@ -492,8 +655,21 @@ union cvmx_mio_boot_pin_defs { uint64_t term:2; uint64_t nand:1; uint64_t user0:8; +#else + uint64_t user0:8; + uint64_t nand:1; + uint64_t term:2; + uint64_t dmack_p0:1; + uint64_t dmack_p1:1; + uint64_t dmack_p2:1; + uint64_t width:1; + uint64_t ale:1; + uint64_t user1:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_boot_pin_defs_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ale:1; uint64_t width:1; @@ -503,8 +679,20 @@ union cvmx_mio_boot_pin_defs { uint64_t term:2; uint64_t nand:1; uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t nand:1; + uint64_t term:2; + uint64_t dmack_p0:1; + uint64_t dmack_p1:1; + uint64_t reserved_13_13:1; + uint64_t width:1; + uint64_t ale:1; + uint64_t reserved_16_63:48; +#endif } cn52xx; struct cvmx_mio_boot_pin_defs_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ale:1; uint64_t width:1; @@ -513,8 +701,19 @@ union cvmx_mio_boot_pin_defs { uint64_t dmack_p0:1; uint64_t term:2; uint64_t reserved_0_8:9; +#else + uint64_t reserved_0_8:9; + uint64_t term:2; + uint64_t dmack_p0:1; + uint64_t dmack_p1:1; + uint64_t dmack_p2:1; + uint64_t width:1; + uint64_t ale:1; + uint64_t reserved_16_63:48; +#endif } cn56xx; struct cvmx_mio_boot_pin_defs_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t user1:16; uint64_t ale:1; @@ -525,17 +724,31 @@ union cvmx_mio_boot_pin_defs { uint64_t term:2; uint64_t nand:1; uint64_t user0:8; +#else + uint64_t user0:8; + uint64_t nand:1; + uint64_t term:2; + uint64_t dmack_p0:1; + uint64_t dmack_p1:1; + uint64_t reserved_13_13:1; + uint64_t width:1; + uint64_t ale:1; + uint64_t user1:16; + uint64_t reserved_32_63:32; +#endif } cn61xx; struct cvmx_mio_boot_pin_defs_cn52xx cn63xx; struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1; struct cvmx_mio_boot_pin_defs_cn52xx cn66xx; struct cvmx_mio_boot_pin_defs_cn52xx cn68xx; struct cvmx_mio_boot_pin_defs_cn52xx cn68xxp1; + struct cvmx_mio_boot_pin_defs_cn61xx cnf71xx; }; union cvmx_mio_boot_reg_cfgx { uint64_t u64; struct cvmx_mio_boot_reg_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t dmack:2; uint64_t tim_mult:2; @@ -549,8 +762,24 @@ union cvmx_mio_boot_reg_cfgx { uint64_t width:1; uint64_t size:12; uint64_t base:16; +#else + uint64_t base:16; + uint64_t size:12; + uint64_t width:1; + uint64_t ale:1; + uint64_t orbit:1; + uint64_t en:1; + uint64_t oe_ext:2; + uint64_t we_ext:2; + uint64_t sam:1; + uint64_t rd_dly:3; + uint64_t tim_mult:2; + uint64_t dmack:2; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_mio_boot_reg_cfgx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t sam:1; uint64_t we_ext:2; @@ -561,18 +790,40 @@ union cvmx_mio_boot_reg_cfgx { uint64_t width:1; uint64_t size:12; uint64_t base:16; +#else + uint64_t base:16; + uint64_t size:12; + uint64_t width:1; + uint64_t ale:1; + uint64_t orbit:1; + uint64_t en:1; + uint64_t oe_ext:2; + uint64_t we_ext:2; + uint64_t sam:1; + uint64_t reserved_37_63:27; +#endif } cn30xx; struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx; struct cvmx_mio_boot_reg_cfgx_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t en:1; uint64_t orbit:1; uint64_t reserved_28_29:2; uint64_t size:12; uint64_t base:16; +#else + uint64_t base:16; + uint64_t size:12; + uint64_t reserved_28_29:2; + uint64_t orbit:1; + uint64_t en:1; + uint64_t reserved_32_63:32; +#endif } cn38xx; struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2; struct cvmx_mio_boot_reg_cfgx_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t tim_mult:2; uint64_t rd_dly:3; @@ -585,6 +836,20 @@ union cvmx_mio_boot_reg_cfgx { uint64_t width:1; uint64_t size:12; uint64_t base:16; +#else + uint64_t base:16; + uint64_t size:12; + uint64_t width:1; + uint64_t ale:1; + uint64_t orbit:1; + uint64_t en:1; + uint64_t oe_ext:2; + uint64_t we_ext:2; + uint64_t sam:1; + uint64_t rd_dly:3; + uint64_t tim_mult:2; + uint64_t reserved_42_63:22; +#endif } cn50xx; struct cvmx_mio_boot_reg_cfgx_s cn52xx; struct cvmx_mio_boot_reg_cfgx_s cn52xxp1; @@ -598,11 +863,13 @@ union cvmx_mio_boot_reg_cfgx { struct cvmx_mio_boot_reg_cfgx_s cn66xx; struct cvmx_mio_boot_reg_cfgx_s cn68xx; struct cvmx_mio_boot_reg_cfgx_s cn68xxp1; + struct cvmx_mio_boot_reg_cfgx_s cnf71xx; }; union cvmx_mio_boot_reg_timx { uint64_t u64; struct cvmx_mio_boot_reg_timx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t pagem:1; uint64_t waitm:1; uint64_t pages:2; @@ -616,10 +883,26 @@ union cvmx_mio_boot_reg_timx { uint64_t oe:6; uint64_t ce:6; uint64_t adr:6; +#else + uint64_t adr:6; + uint64_t ce:6; + uint64_t oe:6; + uint64_t we:6; + uint64_t rd_hld:6; + uint64_t wr_hld:6; + uint64_t pause:6; + uint64_t wait:6; + uint64_t page:6; + uint64_t ale:6; + uint64_t pages:2; + uint64_t waitm:1; + uint64_t pagem:1; +#endif } s; struct cvmx_mio_boot_reg_timx_s cn30xx; struct cvmx_mio_boot_reg_timx_s cn31xx; struct cvmx_mio_boot_reg_timx_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t pagem:1; uint64_t waitm:1; uint64_t pages:2; @@ -633,6 +916,21 @@ union cvmx_mio_boot_reg_timx { uint64_t oe:6; uint64_t ce:6; uint64_t adr:6; +#else + uint64_t adr:6; + uint64_t ce:6; + uint64_t oe:6; + uint64_t we:6; + uint64_t rd_hld:6; + uint64_t wr_hld:6; + uint64_t pause:6; + uint64_t wait:6; + uint64_t page:6; + uint64_t reserved_54_59:6; + uint64_t pages:2; + uint64_t waitm:1; + uint64_t pagem:1; +#endif } cn38xx; struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2; struct cvmx_mio_boot_reg_timx_s cn50xx; @@ -648,23 +946,40 @@ union cvmx_mio_boot_reg_timx { struct cvmx_mio_boot_reg_timx_s cn66xx; struct cvmx_mio_boot_reg_timx_s cn68xx; struct cvmx_mio_boot_reg_timx_s cn68xxp1; + struct cvmx_mio_boot_reg_timx_s cnf71xx; }; union cvmx_mio_boot_thr { uint64_t u64; struct cvmx_mio_boot_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t dma_thr:6; uint64_t reserved_14_15:2; uint64_t fif_cnt:6; uint64_t reserved_6_7:2; uint64_t fif_thr:6; +#else + uint64_t fif_thr:6; + uint64_t reserved_6_7:2; + uint64_t fif_cnt:6; + uint64_t reserved_14_15:2; + uint64_t dma_thr:6; + uint64_t reserved_22_63:42; +#endif } s; struct cvmx_mio_boot_thr_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t fif_cnt:6; uint64_t reserved_6_7:2; uint64_t fif_thr:6; +#else + uint64_t fif_thr:6; + uint64_t reserved_6_7:2; + uint64_t fif_cnt:6; + uint64_t reserved_14_63:50; +#endif } cn30xx; struct cvmx_mio_boot_thr_cn30xx cn31xx; struct cvmx_mio_boot_thr_cn30xx cn38xx; @@ -682,42 +997,66 @@ union cvmx_mio_boot_thr { struct cvmx_mio_boot_thr_s cn66xx; struct cvmx_mio_boot_thr_s cn68xx; struct cvmx_mio_boot_thr_s cn68xxp1; + struct cvmx_mio_boot_thr_s cnf71xx; }; union cvmx_mio_emm_buf_dat { uint64_t u64; struct cvmx_mio_emm_buf_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dat:64; +#else + uint64_t dat:64; +#endif } s; struct cvmx_mio_emm_buf_dat_s cn61xx; + struct cvmx_mio_emm_buf_dat_s cnf71xx; }; union cvmx_mio_emm_buf_idx { uint64_t u64; struct cvmx_mio_emm_buf_idx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t inc:1; uint64_t reserved_7_15:9; uint64_t buf_num:1; uint64_t offset:6; +#else + uint64_t offset:6; + uint64_t buf_num:1; + uint64_t reserved_7_15:9; + uint64_t inc:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_mio_emm_buf_idx_s cn61xx; + struct cvmx_mio_emm_buf_idx_s cnf71xx; }; union cvmx_mio_emm_cfg { uint64_t u64; struct cvmx_mio_emm_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t boot_fail:1; uint64_t reserved_4_15:12; uint64_t bus_ena:4; +#else + uint64_t bus_ena:4; + uint64_t reserved_4_15:12; + uint64_t boot_fail:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_mio_emm_cfg_s cn61xx; + struct cvmx_mio_emm_cfg_s cnf71xx; }; union cvmx_mio_emm_cmd { uint64_t u64; struct cvmx_mio_emm_cmd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t bus_id:2; uint64_t cmd_val:1; @@ -729,13 +1068,28 @@ union cvmx_mio_emm_cmd { uint64_t rtype_xor:3; uint64_t cmd_idx:6; uint64_t arg:32; +#else + uint64_t arg:32; + uint64_t cmd_idx:6; + uint64_t rtype_xor:3; + uint64_t ctype_xor:2; + uint64_t reserved_43_48:6; + uint64_t offset:6; + uint64_t dbuf:1; + uint64_t reserved_56_58:3; + uint64_t cmd_val:1; + uint64_t bus_id:2; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_mio_emm_cmd_s cn61xx; + struct cvmx_mio_emm_cmd_s cnf71xx; }; union cvmx_mio_emm_dma { uint64_t u64; struct cvmx_mio_emm_dma_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t bus_id:2; uint64_t dma_val:1; @@ -747,13 +1101,28 @@ union cvmx_mio_emm_dma { uint64_t multi:1; uint64_t block_cnt:16; uint64_t card_addr:32; +#else + uint64_t card_addr:32; + uint64_t block_cnt:16; + uint64_t multi:1; + uint64_t rw:1; + uint64_t rel_wr:1; + uint64_t thres:6; + uint64_t dat_null:1; + uint64_t sector:1; + uint64_t dma_val:1; + uint64_t bus_id:2; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_mio_emm_dma_s cn61xx; + struct cvmx_mio_emm_dma_s cnf71xx; }; union cvmx_mio_emm_int { uint64_t u64; struct cvmx_mio_emm_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t switch_err:1; uint64_t switch_done:1; @@ -762,13 +1131,25 @@ union cvmx_mio_emm_int { uint64_t dma_done:1; uint64_t cmd_done:1; uint64_t buf_done:1; +#else + uint64_t buf_done:1; + uint64_t cmd_done:1; + uint64_t dma_done:1; + uint64_t cmd_err:1; + uint64_t dma_err:1; + uint64_t switch_done:1; + uint64_t switch_err:1; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_mio_emm_int_s cn61xx; + struct cvmx_mio_emm_int_s cnf71xx; }; union cvmx_mio_emm_int_en { uint64_t u64; struct cvmx_mio_emm_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t switch_err:1; uint64_t switch_done:1; @@ -777,13 +1158,25 @@ union cvmx_mio_emm_int_en { uint64_t dma_done:1; uint64_t cmd_done:1; uint64_t buf_done:1; +#else + uint64_t buf_done:1; + uint64_t cmd_done:1; + uint64_t dma_done:1; + uint64_t cmd_err:1; + uint64_t dma_err:1; + uint64_t switch_done:1; + uint64_t switch_err:1; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_mio_emm_int_en_s cn61xx; + struct cvmx_mio_emm_int_en_s cnf71xx; }; union cvmx_mio_emm_modex { uint64_t u64; struct cvmx_mio_emm_modex_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t hs_timing:1; uint64_t reserved_43_47:5; @@ -792,38 +1185,66 @@ union cvmx_mio_emm_modex { uint64_t power_class:4; uint64_t clk_hi:16; uint64_t clk_lo:16; +#else + uint64_t clk_lo:16; + uint64_t clk_hi:16; + uint64_t power_class:4; + uint64_t reserved_36_39:4; + uint64_t bus_width:3; + uint64_t reserved_43_47:5; + uint64_t hs_timing:1; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_mio_emm_modex_s cn61xx; + struct cvmx_mio_emm_modex_s cnf71xx; }; union cvmx_mio_emm_rca { uint64_t u64; struct cvmx_mio_emm_rca_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t card_rca:16; +#else + uint64_t card_rca:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_mio_emm_rca_s cn61xx; + struct cvmx_mio_emm_rca_s cnf71xx; }; union cvmx_mio_emm_rsp_hi { uint64_t u64; struct cvmx_mio_emm_rsp_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dat:64; +#else uint64_t dat:64; +#endif } s; struct cvmx_mio_emm_rsp_hi_s cn61xx; + struct cvmx_mio_emm_rsp_hi_s cnf71xx; }; union cvmx_mio_emm_rsp_lo { uint64_t u64; struct cvmx_mio_emm_rsp_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dat:64; +#else + uint64_t dat:64; +#endif } s; struct cvmx_mio_emm_rsp_lo_s cn61xx; + struct cvmx_mio_emm_rsp_lo_s cnf71xx; }; union cvmx_mio_emm_rsp_sts { uint64_t u64; struct cvmx_mio_emm_rsp_sts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t bus_id:2; uint64_t cmd_val:1; @@ -849,33 +1270,76 @@ union cvmx_mio_emm_rsp_sts { uint64_t cmd_type:2; uint64_t cmd_idx:6; uint64_t cmd_done:1; +#else + uint64_t cmd_done:1; + uint64_t cmd_idx:6; + uint64_t cmd_type:2; + uint64_t rsp_type:3; + uint64_t rsp_val:1; + uint64_t rsp_bad_sts:1; + uint64_t rsp_crc_err:1; + uint64_t rsp_timeout:1; + uint64_t stp_val:1; + uint64_t stp_bad_sts:1; + uint64_t stp_crc_err:1; + uint64_t stp_timeout:1; + uint64_t rsp_busybit:1; + uint64_t blk_crc_err:1; + uint64_t blk_timeout:1; + uint64_t dbuf:1; + uint64_t reserved_24_27:4; + uint64_t dbuf_err:1; + uint64_t reserved_29_55:27; + uint64_t dma_pend:1; + uint64_t dma_val:1; + uint64_t switch_val:1; + uint64_t cmd_val:1; + uint64_t bus_id:2; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_mio_emm_rsp_sts_s cn61xx; + struct cvmx_mio_emm_rsp_sts_s cnf71xx; }; union cvmx_mio_emm_sample { uint64_t u64; struct cvmx_mio_emm_sample_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t cmd_cnt:10; uint64_t reserved_10_15:6; uint64_t dat_cnt:10; +#else + uint64_t dat_cnt:10; + uint64_t reserved_10_15:6; + uint64_t cmd_cnt:10; + uint64_t reserved_26_63:38; +#endif } s; struct cvmx_mio_emm_sample_s cn61xx; + struct cvmx_mio_emm_sample_s cnf71xx; }; union cvmx_mio_emm_sts_mask { uint64_t u64; struct cvmx_mio_emm_sts_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t sts_msk:32; +#else + uint64_t sts_msk:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_emm_sts_mask_s cn61xx; + struct cvmx_mio_emm_sts_mask_s cnf71xx; }; union cvmx_mio_emm_switch { uint64_t u64; struct cvmx_mio_emm_switch_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t bus_id:2; uint64_t switch_exe:1; @@ -890,23 +1354,50 @@ union cvmx_mio_emm_switch { uint64_t power_class:4; uint64_t clk_hi:16; uint64_t clk_lo:16; +#else + uint64_t clk_lo:16; + uint64_t clk_hi:16; + uint64_t power_class:4; + uint64_t reserved_36_39:4; + uint64_t bus_width:3; + uint64_t reserved_43_47:5; + uint64_t hs_timing:1; + uint64_t reserved_49_55:7; + uint64_t switch_err2:1; + uint64_t switch_err1:1; + uint64_t switch_err0:1; + uint64_t switch_exe:1; + uint64_t bus_id:2; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_mio_emm_switch_s cn61xx; + struct cvmx_mio_emm_switch_s cnf71xx; }; union cvmx_mio_emm_wdog { uint64_t u64; struct cvmx_mio_emm_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t clk_cnt:26; +#else + uint64_t clk_cnt:26; + uint64_t reserved_26_63:38; +#endif } s; struct cvmx_mio_emm_wdog_s cn61xx; + struct cvmx_mio_emm_wdog_s cnf71xx; }; union cvmx_mio_fus_bnk_datx { uint64_t u64; struct cvmx_mio_fus_bnk_datx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dat:64; +#else uint64_t dat:64; +#endif } s; struct cvmx_mio_fus_bnk_datx_s cn50xx; struct cvmx_mio_fus_bnk_datx_s cn52xx; @@ -921,13 +1412,19 @@ union cvmx_mio_fus_bnk_datx { struct cvmx_mio_fus_bnk_datx_s cn66xx; struct cvmx_mio_fus_bnk_datx_s cn68xx; struct cvmx_mio_fus_bnk_datx_s cn68xxp1; + struct cvmx_mio_fus_bnk_datx_s cnf71xx; }; union cvmx_mio_fus_dat0 { uint64_t u64; struct cvmx_mio_fus_dat0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t man_info:32; +#else + uint64_t man_info:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_fus_dat0_s cn30xx; struct cvmx_mio_fus_dat0_s cn31xx; @@ -946,13 +1443,19 @@ union cvmx_mio_fus_dat0 { struct cvmx_mio_fus_dat0_s cn66xx; struct cvmx_mio_fus_dat0_s cn68xx; struct cvmx_mio_fus_dat0_s cn68xxp1; + struct cvmx_mio_fus_dat0_s cnf71xx; }; union cvmx_mio_fus_dat1 { uint64_t u64; struct cvmx_mio_fus_dat1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t man_info:32; +#else + uint64_t man_info:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_fus_dat1_s cn30xx; struct cvmx_mio_fus_dat1_s cn31xx; @@ -971,11 +1474,13 @@ union cvmx_mio_fus_dat1 { struct cvmx_mio_fus_dat1_s cn66xx; struct cvmx_mio_fus_dat1_s cn68xx; struct cvmx_mio_fus_dat1_s cn68xxp1; + struct cvmx_mio_fus_dat1_s cnf71xx; }; union cvmx_mio_fus_dat2 { uint64_t u64; struct cvmx_mio_fus_dat2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t fus118:1; uint64_t rom_info:10; @@ -992,8 +1497,27 @@ union cvmx_mio_fus_dat2 { uint64_t bist_dis:1; uint64_t chip_id:8; uint64_t reserved_0_15:16; +#else + uint64_t reserved_0_15:16; + uint64_t chip_id:8; + uint64_t bist_dis:1; + uint64_t rst_sht:1; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t nokasu:1; + uint64_t reserved_30_31:2; + uint64_t raid_en:1; + uint64_t fus318:1; + uint64_t dorm_crypto:1; + uint64_t power_limit:2; + uint64_t rom_info:10; + uint64_t fus118:1; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_mio_fus_dat2_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t nodfa_cp2:1; uint64_t nomul:1; @@ -1004,8 +1528,21 @@ union cvmx_mio_fus_dat2 { uint64_t pll_off:4; uint64_t reserved_1_11:11; uint64_t pp_dis:1; +#else + uint64_t pp_dis:1; + uint64_t reserved_1_11:11; + uint64_t pll_off:4; + uint64_t chip_id:8; + uint64_t bist_dis:1; + uint64_t rst_sht:1; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t reserved_29_63:35; +#endif } cn30xx; struct cvmx_mio_fus_dat2_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t nodfa_cp2:1; uint64_t nomul:1; @@ -1016,8 +1553,21 @@ union cvmx_mio_fus_dat2 { uint64_t pll_off:4; uint64_t reserved_2_11:10; uint64_t pp_dis:2; +#else + uint64_t pp_dis:2; + uint64_t reserved_2_11:10; + uint64_t pll_off:4; + uint64_t chip_id:8; + uint64_t bist_dis:1; + uint64_t rst_sht:1; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t reserved_29_63:35; +#endif } cn31xx; struct cvmx_mio_fus_dat2_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t nodfa_cp2:1; uint64_t nomul:1; @@ -1026,9 +1576,20 @@ union cvmx_mio_fus_dat2 { uint64_t bist_dis:1; uint64_t chip_id:8; uint64_t pp_dis:16; +#else + uint64_t pp_dis:16; + uint64_t chip_id:8; + uint64_t bist_dis:1; + uint64_t rst_sht:1; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t reserved_29_63:35; +#endif } cn38xx; struct cvmx_mio_fus_dat2_cn38xx cn38xxp2; struct cvmx_mio_fus_dat2_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t fus318:1; uint64_t raid_en:1; @@ -1042,8 +1603,24 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_2_15:14; uint64_t pp_dis:2; +#else + uint64_t pp_dis:2; + uint64_t reserved_2_15:14; + uint64_t chip_id:8; + uint64_t bist_dis:1; + uint64_t rst_sht:1; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t nokasu:1; + uint64_t reserved_30_31:2; + uint64_t raid_en:1; + uint64_t fus318:1; + uint64_t reserved_34_63:30; +#endif } cn50xx; struct cvmx_mio_fus_dat2_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t fus318:1; uint64_t raid_en:1; @@ -1057,9 +1634,25 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_4_15:12; uint64_t pp_dis:4; +#else + uint64_t pp_dis:4; + uint64_t reserved_4_15:12; + uint64_t chip_id:8; + uint64_t bist_dis:1; + uint64_t rst_sht:1; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t nokasu:1; + uint64_t reserved_30_31:2; + uint64_t raid_en:1; + uint64_t fus318:1; + uint64_t reserved_34_63:30; +#endif } cn52xx; struct cvmx_mio_fus_dat2_cn52xx cn52xxp1; struct cvmx_mio_fus_dat2_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t fus318:1; uint64_t raid_en:1; @@ -1073,9 +1666,25 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_12_15:4; uint64_t pp_dis:12; +#else + uint64_t pp_dis:12; + uint64_t reserved_12_15:4; + uint64_t chip_id:8; + uint64_t bist_dis:1; + uint64_t rst_sht:1; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t nokasu:1; + uint64_t reserved_30_31:2; + uint64_t raid_en:1; + uint64_t fus318:1; + uint64_t reserved_34_63:30; +#endif } cn56xx; struct cvmx_mio_fus_dat2_cn56xx cn56xxp1; struct cvmx_mio_fus_dat2_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_30_63:34; uint64_t nokasu:1; uint64_t nodfa_cp2:1; @@ -1085,9 +1694,21 @@ union cvmx_mio_fus_dat2 { uint64_t bist_dis:1; uint64_t chip_id:8; uint64_t pp_dis:16; +#else + uint64_t pp_dis:16; + uint64_t chip_id:8; + uint64_t bist_dis:1; + uint64_t rst_sht:1; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t nokasu:1; + uint64_t reserved_30_63:34; +#endif } cn58xx; struct cvmx_mio_fus_dat2_cn58xx cn58xxp1; struct cvmx_mio_fus_dat2_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t fus118:1; uint64_t rom_info:10; @@ -1103,8 +1724,26 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_4_15:12; uint64_t pp_dis:4; +#else + uint64_t pp_dis:4; + uint64_t reserved_4_15:12; + uint64_t chip_id:8; + uint64_t reserved_24_25:2; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t reserved_29_31:3; + uint64_t raid_en:1; + uint64_t fus318:1; + uint64_t dorm_crypto:1; + uint64_t power_limit:2; + uint64_t rom_info:10; + uint64_t fus118:1; + uint64_t reserved_48_63:16; +#endif } cn61xx; struct cvmx_mio_fus_dat2_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t dorm_crypto:1; uint64_t fus318:1; @@ -1117,9 +1756,24 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_6_15:10; uint64_t pp_dis:6; +#else + uint64_t pp_dis:6; + uint64_t reserved_6_15:10; + uint64_t chip_id:8; + uint64_t reserved_24_25:2; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t reserved_29_31:3; + uint64_t raid_en:1; + uint64_t fus318:1; + uint64_t dorm_crypto:1; + uint64_t reserved_35_63:29; +#endif } cn63xx; struct cvmx_mio_fus_dat2_cn63xx cn63xxp1; struct cvmx_mio_fus_dat2_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t fus118:1; uint64_t rom_info:10; @@ -1135,8 +1789,26 @@ union cvmx_mio_fus_dat2 { uint64_t chip_id:8; uint64_t reserved_10_15:6; uint64_t pp_dis:10; +#else + uint64_t pp_dis:10; + uint64_t reserved_10_15:6; + uint64_t chip_id:8; + uint64_t reserved_24_25:2; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t reserved_29_31:3; + uint64_t raid_en:1; + uint64_t fus318:1; + uint64_t dorm_crypto:1; + uint64_t power_limit:2; + uint64_t rom_info:10; + uint64_t fus118:1; + uint64_t reserved_48_63:16; +#endif } cn66xx; struct cvmx_mio_fus_dat2_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t power_limit:2; uint64_t dorm_crypto:1; @@ -1149,13 +1821,29 @@ union cvmx_mio_fus_dat2 { uint64_t reserved_24_25:2; uint64_t chip_id:8; uint64_t reserved_0_15:16; +#else + uint64_t reserved_0_15:16; + uint64_t chip_id:8; + uint64_t reserved_24_25:2; + uint64_t nocrypto:1; + uint64_t nomul:1; + uint64_t nodfa_cp2:1; + uint64_t reserved_29_31:3; + uint64_t raid_en:1; + uint64_t fus318:1; + uint64_t dorm_crypto:1; + uint64_t power_limit:2; + uint64_t reserved_37_63:27; +#endif } cn68xx; struct cvmx_mio_fus_dat2_cn68xx cn68xxp1; + struct cvmx_mio_fus_dat2_cn61xx cnf71xx; }; union cvmx_mio_fus_dat3 { uint64_t u64; struct cvmx_mio_fus_dat3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t pll_ctl:10; uint64_t dfa_info_dte:3; @@ -1174,8 +1862,29 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t icache:24; +#else + uint64_t icache:24; + uint64_t nodfa_dte:1; + uint64_t nozip:1; + uint64_t efus_ign:1; + uint64_t efus_lck:1; + uint64_t bar2_en:1; + uint64_t reserved_29_30:2; + uint64_t pll_div4:1; + uint64_t l2c_crip:3; + uint64_t pll_half_dis:1; + uint64_t efus_lck_man:1; + uint64_t efus_lck_rsv:1; + uint64_t ema:2; + uint64_t reserved_40_40:1; + uint64_t dfa_info_clm:4; + uint64_t dfa_info_dte:3; + uint64_t pll_ctl:10; + uint64_t reserved_58_63:6; +#endif } s; struct cvmx_mio_fus_dat3_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pll_div4:1; uint64_t reserved_29_30:2; @@ -1185,8 +1894,20 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t icache:24; +#else + uint64_t icache:24; + uint64_t nodfa_dte:1; + uint64_t nozip:1; + uint64_t efus_ign:1; + uint64_t efus_lck:1; + uint64_t bar2_en:1; + uint64_t reserved_29_30:2; + uint64_t pll_div4:1; + uint64_t reserved_32_63:32; +#endif } cn30xx; struct cvmx_mio_fus_dat3_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pll_div4:1; uint64_t zip_crip:2; @@ -1196,8 +1917,20 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t icache:24; +#else + uint64_t icache:24; + uint64_t nodfa_dte:1; + uint64_t nozip:1; + uint64_t efus_ign:1; + uint64_t efus_lck:1; + uint64_t bar2_en:1; + uint64_t zip_crip:2; + uint64_t pll_div4:1; + uint64_t reserved_32_63:32; +#endif } cn31xx; struct cvmx_mio_fus_dat3_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t zip_crip:2; uint64_t bar2_en:1; @@ -1206,8 +1939,19 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t icache:24; +#else + uint64_t icache:24; + uint64_t nodfa_dte:1; + uint64_t nozip:1; + uint64_t efus_ign:1; + uint64_t efus_lck:1; + uint64_t bar2_en:1; + uint64_t zip_crip:2; + uint64_t reserved_31_63:33; +#endif } cn38xx; struct cvmx_mio_fus_dat3_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t bar2_en:1; uint64_t efus_lck:1; @@ -1215,6 +1959,15 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t icache:24; +#else + uint64_t icache:24; + uint64_t nodfa_dte:1; + uint64_t nozip:1; + uint64_t efus_ign:1; + uint64_t efus_lck:1; + uint64_t bar2_en:1; + uint64_t reserved_29_63:35; +#endif } cn38xxp2; struct cvmx_mio_fus_dat3_cn38xx cn50xx; struct cvmx_mio_fus_dat3_cn38xx cn52xx; @@ -1224,6 +1977,7 @@ union cvmx_mio_fus_dat3 { struct cvmx_mio_fus_dat3_cn38xx cn58xx; struct cvmx_mio_fus_dat3_cn38xx cn58xxp1; struct cvmx_mio_fus_dat3_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t pll_ctl:10; uint64_t dfa_info_dte:3; @@ -1242,21 +1996,49 @@ union cvmx_mio_fus_dat3 { uint64_t nozip:1; uint64_t nodfa_dte:1; uint64_t reserved_0_23:24; +#else + uint64_t reserved_0_23:24; + uint64_t nodfa_dte:1; + uint64_t nozip:1; + uint64_t efus_ign:1; + uint64_t efus_lck:1; + uint64_t bar2_en:1; + uint64_t zip_info:2; + uint64_t reserved_31_31:1; + uint64_t l2c_crip:3; + uint64_t pll_half_dis:1; + uint64_t efus_lck_man:1; + uint64_t efus_lck_rsv:1; + uint64_t ema:2; + uint64_t reserved_40_40:1; + uint64_t dfa_info_clm:4; + uint64_t dfa_info_dte:3; + uint64_t pll_ctl:10; + uint64_t reserved_58_63:6; +#endif } cn61xx; struct cvmx_mio_fus_dat3_cn61xx cn63xx; struct cvmx_mio_fus_dat3_cn61xx cn63xxp1; struct cvmx_mio_fus_dat3_cn61xx cn66xx; struct cvmx_mio_fus_dat3_cn61xx cn68xx; struct cvmx_mio_fus_dat3_cn61xx cn68xxp1; + struct cvmx_mio_fus_dat3_cn61xx cnf71xx; }; union cvmx_mio_fus_ema { uint64_t u64; struct cvmx_mio_fus_ema_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t eff_ema:3; uint64_t reserved_3_3:1; uint64_t ema:3; +#else + uint64_t ema:3; + uint64_t reserved_3_3:1; + uint64_t eff_ema:3; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_mio_fus_ema_s cn50xx; struct cvmx_mio_fus_ema_s cn52xx; @@ -1264,8 +2046,13 @@ union cvmx_mio_fus_ema { struct cvmx_mio_fus_ema_s cn56xx; struct cvmx_mio_fus_ema_s cn56xxp1; struct cvmx_mio_fus_ema_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t ema:2; +#else + uint64_t ema:2; + uint64_t reserved_2_63:62; +#endif } cn58xx; struct cvmx_mio_fus_ema_cn58xx cn58xxp1; struct cvmx_mio_fus_ema_s cn61xx; @@ -1274,12 +2061,17 @@ union cvmx_mio_fus_ema { struct cvmx_mio_fus_ema_s cn66xx; struct cvmx_mio_fus_ema_s cn68xx; struct cvmx_mio_fus_ema_s cn68xxp1; + struct cvmx_mio_fus_ema_s cnf71xx; }; union cvmx_mio_fus_pdf { uint64_t u64; struct cvmx_mio_fus_pdf_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t pdf:64; +#else uint64_t pdf:64; +#endif } s; struct cvmx_mio_fus_pdf_s cn50xx; struct cvmx_mio_fus_pdf_s cn52xx; @@ -1293,11 +2085,13 @@ union cvmx_mio_fus_pdf { struct cvmx_mio_fus_pdf_s cn66xx; struct cvmx_mio_fus_pdf_s cn68xx; struct cvmx_mio_fus_pdf_s cn68xxp1; + struct cvmx_mio_fus_pdf_s cnf71xx; }; union cvmx_mio_fus_pll { uint64_t u64; struct cvmx_mio_fus_pll_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t rclk_align_r:8; uint64_t rclk_align_l:8; @@ -1308,11 +2102,29 @@ union cvmx_mio_fus_pll { uint64_t pnr_cout_sel:2; uint64_t rfslip:1; uint64_t fbslip:1; +#else + uint64_t fbslip:1; + uint64_t rfslip:1; + uint64_t pnr_cout_sel:2; + uint64_t pnr_cout_rst:1; + uint64_t c_cout_sel:2; + uint64_t c_cout_rst:1; + uint64_t reserved_8_31:24; + uint64_t rclk_align_l:8; + uint64_t rclk_align_r:8; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_mio_fus_pll_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t rfslip:1; uint64_t fbslip:1; +#else + uint64_t fbslip:1; + uint64_t rfslip:1; + uint64_t reserved_2_63:62; +#endif } cn50xx; struct cvmx_mio_fus_pll_cn50xx cn52xx; struct cvmx_mio_fus_pll_cn50xx cn52xxp1; @@ -1321,6 +2133,7 @@ union cvmx_mio_fus_pll { struct cvmx_mio_fus_pll_cn50xx cn58xx; struct cvmx_mio_fus_pll_cn50xx cn58xxp1; struct cvmx_mio_fus_pll_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t c_cout_rst:1; uint64_t c_cout_sel:2; @@ -1328,24 +2141,45 @@ union cvmx_mio_fus_pll { uint64_t pnr_cout_sel:2; uint64_t rfslip:1; uint64_t fbslip:1; +#else + uint64_t fbslip:1; + uint64_t rfslip:1; + uint64_t pnr_cout_sel:2; + uint64_t pnr_cout_rst:1; + uint64_t c_cout_sel:2; + uint64_t c_cout_rst:1; + uint64_t reserved_8_63:56; +#endif } cn61xx; struct cvmx_mio_fus_pll_cn61xx cn63xx; struct cvmx_mio_fus_pll_cn61xx cn63xxp1; struct cvmx_mio_fus_pll_cn61xx cn66xx; struct cvmx_mio_fus_pll_s cn68xx; struct cvmx_mio_fus_pll_s cn68xxp1; + struct cvmx_mio_fus_pll_cn61xx cnf71xx; }; union cvmx_mio_fus_prog { uint64_t u64; struct cvmx_mio_fus_prog_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t soft:1; uint64_t prog:1; +#else + uint64_t prog:1; + uint64_t soft:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_fus_prog_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t prog:1; +#else + uint64_t prog:1; + uint64_t reserved_1_63:63; +#endif } cn30xx; struct cvmx_mio_fus_prog_cn30xx cn31xx; struct cvmx_mio_fus_prog_cn30xx cn38xx; @@ -1363,25 +2197,44 @@ union cvmx_mio_fus_prog { struct cvmx_mio_fus_prog_s cn66xx; struct cvmx_mio_fus_prog_s cn68xx; struct cvmx_mio_fus_prog_s cn68xxp1; + struct cvmx_mio_fus_prog_s cnf71xx; }; union cvmx_mio_fus_prog_times { uint64_t u64; struct cvmx_mio_fus_prog_times_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t vgate_pin:1; uint64_t fsrc_pin:1; uint64_t prog_pin:1; uint64_t reserved_6_31:26; uint64_t setup:6; +#else + uint64_t setup:6; + uint64_t reserved_6_31:26; + uint64_t prog_pin:1; + uint64_t fsrc_pin:1; + uint64_t vgate_pin:1; + uint64_t reserved_35_63:29; +#endif } s; struct cvmx_mio_fus_prog_times_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_33_63:31; uint64_t prog_pin:1; uint64_t out:8; uint64_t sclk_lo:4; uint64_t sclk_hi:12; uint64_t setup:8; +#else + uint64_t setup:8; + uint64_t sclk_hi:12; + uint64_t sclk_lo:4; + uint64_t out:8; + uint64_t prog_pin:1; + uint64_t reserved_33_63:31; +#endif } cn50xx; struct cvmx_mio_fus_prog_times_cn50xx cn52xx; struct cvmx_mio_fus_prog_times_cn50xx cn52xxp1; @@ -1390,6 +2243,7 @@ union cvmx_mio_fus_prog_times { struct cvmx_mio_fus_prog_times_cn50xx cn58xx; struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1; struct cvmx_mio_fus_prog_times_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t vgate_pin:1; uint64_t fsrc_pin:1; @@ -1398,17 +2252,29 @@ union cvmx_mio_fus_prog_times { uint64_t sclk_lo:4; uint64_t sclk_hi:15; uint64_t setup:6; +#else + uint64_t setup:6; + uint64_t sclk_hi:15; + uint64_t sclk_lo:4; + uint64_t out:7; + uint64_t prog_pin:1; + uint64_t fsrc_pin:1; + uint64_t vgate_pin:1; + uint64_t reserved_35_63:29; +#endif } cn61xx; struct cvmx_mio_fus_prog_times_cn61xx cn63xx; struct cvmx_mio_fus_prog_times_cn61xx cn63xxp1; struct cvmx_mio_fus_prog_times_cn61xx cn66xx; struct cvmx_mio_fus_prog_times_cn61xx cn68xx; struct cvmx_mio_fus_prog_times_cn61xx cn68xxp1; + struct cvmx_mio_fus_prog_times_cn61xx cnf71xx; }; union cvmx_mio_fus_rcmd { uint64_t u64; struct cvmx_mio_fus_rcmd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t dat:8; uint64_t reserved_13_15:3; @@ -1416,8 +2282,18 @@ union cvmx_mio_fus_rcmd { uint64_t reserved_9_11:3; uint64_t efuse:1; uint64_t addr:8; +#else + uint64_t addr:8; + uint64_t efuse:1; + uint64_t reserved_9_11:3; + uint64_t pend:1; + uint64_t reserved_13_15:3; + uint64_t dat:8; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_mio_fus_rcmd_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t dat:8; uint64_t reserved_13_15:3; @@ -1426,6 +2302,16 @@ union cvmx_mio_fus_rcmd { uint64_t efuse:1; uint64_t reserved_7_7:1; uint64_t addr:7; +#else + uint64_t addr:7; + uint64_t reserved_7_7:1; + uint64_t efuse:1; + uint64_t reserved_9_11:3; + uint64_t pend:1; + uint64_t reserved_13_15:3; + uint64_t dat:8; + uint64_t reserved_24_63:40; +#endif } cn30xx; struct cvmx_mio_fus_rcmd_cn30xx cn31xx; struct cvmx_mio_fus_rcmd_cn30xx cn38xx; @@ -1443,17 +2329,27 @@ union cvmx_mio_fus_rcmd { struct cvmx_mio_fus_rcmd_s cn66xx; struct cvmx_mio_fus_rcmd_s cn68xx; struct cvmx_mio_fus_rcmd_s cn68xxp1; + struct cvmx_mio_fus_rcmd_s cnf71xx; }; union cvmx_mio_fus_read_times { uint64_t u64; struct cvmx_mio_fus_read_times_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_26_63:38; uint64_t sch:4; uint64_t fsh:4; uint64_t prh:4; uint64_t sdh:4; uint64_t setup:10; +#else + uint64_t setup:10; + uint64_t sdh:4; + uint64_t prh:4; + uint64_t fsh:4; + uint64_t sch:4; + uint64_t reserved_26_63:38; +#endif } s; struct cvmx_mio_fus_read_times_s cn61xx; struct cvmx_mio_fus_read_times_s cn63xx; @@ -1461,16 +2357,25 @@ union cvmx_mio_fus_read_times { struct cvmx_mio_fus_read_times_s cn66xx; struct cvmx_mio_fus_read_times_s cn68xx; struct cvmx_mio_fus_read_times_s cn68xxp1; + struct cvmx_mio_fus_read_times_s cnf71xx; }; union cvmx_mio_fus_repair_res0 { uint64_t u64; struct cvmx_mio_fus_repair_res0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_55_63:9; uint64_t too_many:1; uint64_t repair2:18; uint64_t repair1:18; uint64_t repair0:18; +#else + uint64_t repair0:18; + uint64_t repair1:18; + uint64_t repair2:18; + uint64_t too_many:1; + uint64_t reserved_55_63:9; +#endif } s; struct cvmx_mio_fus_repair_res0_s cn61xx; struct cvmx_mio_fus_repair_res0_s cn63xx; @@ -1478,15 +2383,23 @@ union cvmx_mio_fus_repair_res0 { struct cvmx_mio_fus_repair_res0_s cn66xx; struct cvmx_mio_fus_repair_res0_s cn68xx; struct cvmx_mio_fus_repair_res0_s cn68xxp1; + struct cvmx_mio_fus_repair_res0_s cnf71xx; }; union cvmx_mio_fus_repair_res1 { uint64_t u64; struct cvmx_mio_fus_repair_res1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t repair5:18; uint64_t repair4:18; uint64_t repair3:18; +#else + uint64_t repair3:18; + uint64_t repair4:18; + uint64_t repair5:18; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_mio_fus_repair_res1_s cn61xx; struct cvmx_mio_fus_repair_res1_s cn63xx; @@ -1494,13 +2407,19 @@ union cvmx_mio_fus_repair_res1 { struct cvmx_mio_fus_repair_res1_s cn66xx; struct cvmx_mio_fus_repair_res1_s cn68xx; struct cvmx_mio_fus_repair_res1_s cn68xxp1; + struct cvmx_mio_fus_repair_res1_s cnf71xx; }; union cvmx_mio_fus_repair_res2 { uint64_t u64; struct cvmx_mio_fus_repair_res2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t repair6:18; +#else + uint64_t repair6:18; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_mio_fus_repair_res2_s cn61xx; struct cvmx_mio_fus_repair_res2_s cn63xx; @@ -1508,15 +2427,23 @@ union cvmx_mio_fus_repair_res2 { struct cvmx_mio_fus_repair_res2_s cn66xx; struct cvmx_mio_fus_repair_res2_s cn68xx; struct cvmx_mio_fus_repair_res2_s cn68xxp1; + struct cvmx_mio_fus_repair_res2_s cnf71xx; }; union cvmx_mio_fus_spr_repair_res { uint64_t u64; struct cvmx_mio_fus_spr_repair_res_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t repair2:14; uint64_t repair1:14; uint64_t repair0:14; +#else + uint64_t repair0:14; + uint64_t repair1:14; + uint64_t repair2:14; + uint64_t reserved_42_63:22; +#endif } s; struct cvmx_mio_fus_spr_repair_res_s cn30xx; struct cvmx_mio_fus_spr_repair_res_s cn31xx; @@ -1534,13 +2461,19 @@ union cvmx_mio_fus_spr_repair_res { struct cvmx_mio_fus_spr_repair_res_s cn66xx; struct cvmx_mio_fus_spr_repair_res_s cn68xx; struct cvmx_mio_fus_spr_repair_res_s cn68xxp1; + struct cvmx_mio_fus_spr_repair_res_s cnf71xx; }; union cvmx_mio_fus_spr_repair_sum { uint64_t u64; struct cvmx_mio_fus_spr_repair_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t too_many:1; +#else + uint64_t too_many:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_fus_spr_repair_sum_s cn30xx; struct cvmx_mio_fus_spr_repair_sum_s cn31xx; @@ -1558,23 +2491,35 @@ union cvmx_mio_fus_spr_repair_sum { struct cvmx_mio_fus_spr_repair_sum_s cn66xx; struct cvmx_mio_fus_spr_repair_sum_s cn68xx; struct cvmx_mio_fus_spr_repair_sum_s cn68xxp1; + struct cvmx_mio_fus_spr_repair_sum_s cnf71xx; }; union cvmx_mio_fus_tgg { uint64_t u64; struct cvmx_mio_fus_tgg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t val:1; uint64_t dat:63; +#else + uint64_t dat:63; + uint64_t val:1; +#endif } s; struct cvmx_mio_fus_tgg_s cn61xx; struct cvmx_mio_fus_tgg_s cn66xx; + struct cvmx_mio_fus_tgg_s cnf71xx; }; union cvmx_mio_fus_unlock { uint64_t u64; struct cvmx_mio_fus_unlock_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t key:24; +#else + uint64_t key:24; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_mio_fus_unlock_s cn30xx; struct cvmx_mio_fus_unlock_s cn31xx; @@ -1583,20 +2528,35 @@ union cvmx_mio_fus_unlock { union cvmx_mio_fus_wadr { uint64_t u64; struct cvmx_mio_fus_wadr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t addr:10; +#else + uint64_t addr:10; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_mio_fus_wadr_s cn30xx; struct cvmx_mio_fus_wadr_s cn31xx; struct cvmx_mio_fus_wadr_s cn38xx; struct cvmx_mio_fus_wadr_s cn38xxp2; struct cvmx_mio_fus_wadr_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t addr:2; +#else + uint64_t addr:2; + uint64_t reserved_2_63:62; +#endif } cn50xx; struct cvmx_mio_fus_wadr_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t addr:3; +#else + uint64_t addr:3; + uint64_t reserved_3_63:61; +#endif } cn52xx; struct cvmx_mio_fus_wadr_cn52xx cn52xxp1; struct cvmx_mio_fus_wadr_cn52xx cn56xx; @@ -1604,22 +2564,34 @@ union cvmx_mio_fus_wadr { struct cvmx_mio_fus_wadr_cn50xx cn58xx; struct cvmx_mio_fus_wadr_cn50xx cn58xxp1; struct cvmx_mio_fus_wadr_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t addr:4; +#else + uint64_t addr:4; + uint64_t reserved_4_63:60; +#endif } cn61xx; struct cvmx_mio_fus_wadr_cn61xx cn63xx; struct cvmx_mio_fus_wadr_cn61xx cn63xxp1; struct cvmx_mio_fus_wadr_cn61xx cn66xx; struct cvmx_mio_fus_wadr_cn61xx cn68xx; struct cvmx_mio_fus_wadr_cn61xx cn68xxp1; + struct cvmx_mio_fus_wadr_cn61xx cnf71xx; }; union cvmx_mio_gpio_comp { uint64_t u64; struct cvmx_mio_gpio_comp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t pctl:6; uint64_t nctl:6; +#else + uint64_t nctl:6; + uint64_t pctl:6; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_mio_gpio_comp_s cn61xx; struct cvmx_mio_gpio_comp_s cn63xx; @@ -1627,11 +2599,13 @@ union cvmx_mio_gpio_comp { struct cvmx_mio_gpio_comp_s cn66xx; struct cvmx_mio_gpio_comp_s cn68xx; struct cvmx_mio_gpio_comp_s cn68xxp1; + struct cvmx_mio_gpio_comp_s cnf71xx; }; union cvmx_mio_ndf_dma_cfg { uint64_t u64; struct cvmx_mio_ndf_dma_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t en:1; uint64_t rw:1; uint64_t clr:1; @@ -1642,6 +2616,18 @@ union cvmx_mio_ndf_dma_cfg { uint64_t endian:1; uint64_t size:20; uint64_t adr:36; +#else + uint64_t adr:36; + uint64_t size:20; + uint64_t endian:1; + uint64_t swap8:1; + uint64_t swap16:1; + uint64_t swap32:1; + uint64_t reserved_60_60:1; + uint64_t clr:1; + uint64_t rw:1; + uint64_t en:1; +#endif } s; struct cvmx_mio_ndf_dma_cfg_s cn52xx; struct cvmx_mio_ndf_dma_cfg_s cn61xx; @@ -1650,13 +2636,19 @@ union cvmx_mio_ndf_dma_cfg { struct cvmx_mio_ndf_dma_cfg_s cn66xx; struct cvmx_mio_ndf_dma_cfg_s cn68xx; struct cvmx_mio_ndf_dma_cfg_s cn68xxp1; + struct cvmx_mio_ndf_dma_cfg_s cnf71xx; }; union cvmx_mio_ndf_dma_int { uint64_t u64; struct cvmx_mio_ndf_dma_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t done:1; +#else + uint64_t done:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_ndf_dma_int_s cn52xx; struct cvmx_mio_ndf_dma_int_s cn61xx; @@ -1665,13 +2657,19 @@ union cvmx_mio_ndf_dma_int { struct cvmx_mio_ndf_dma_int_s cn66xx; struct cvmx_mio_ndf_dma_int_s cn68xx; struct cvmx_mio_ndf_dma_int_s cn68xxp1; + struct cvmx_mio_ndf_dma_int_s cnf71xx; }; union cvmx_mio_ndf_dma_int_en { uint64_t u64; struct cvmx_mio_ndf_dma_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t done:1; +#else + uint64_t done:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_ndf_dma_int_en_s cn52xx; struct cvmx_mio_ndf_dma_int_en_s cn61xx; @@ -1680,13 +2678,19 @@ union cvmx_mio_ndf_dma_int_en { struct cvmx_mio_ndf_dma_int_en_s cn66xx; struct cvmx_mio_ndf_dma_int_en_s cn68xx; struct cvmx_mio_ndf_dma_int_en_s cn68xxp1; + struct cvmx_mio_ndf_dma_int_en_s cnf71xx; }; union cvmx_mio_pll_ctl { uint64_t u64; struct cvmx_mio_pll_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t bw_ctl:5; +#else + uint64_t bw_ctl:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_mio_pll_ctl_s cn30xx; struct cvmx_mio_pll_ctl_s cn31xx; @@ -1695,8 +2699,13 @@ union cvmx_mio_pll_ctl { union cvmx_mio_pll_setting { uint64_t u64; struct cvmx_mio_pll_setting_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t setting:17; +#else + uint64_t setting:17; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_mio_pll_setting_s cn30xx; struct cvmx_mio_pll_setting_s cn31xx; @@ -1705,49 +2714,73 @@ union cvmx_mio_pll_setting { union cvmx_mio_ptp_ckout_hi_incr { uint64_t u64; struct cvmx_mio_ptp_ckout_hi_incr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:32; uint64_t frnanosec:32; +#else + uint64_t frnanosec:32; + uint64_t nanosec:32; +#endif } s; struct cvmx_mio_ptp_ckout_hi_incr_s cn61xx; struct cvmx_mio_ptp_ckout_hi_incr_s cn66xx; struct cvmx_mio_ptp_ckout_hi_incr_s cn68xx; + struct cvmx_mio_ptp_ckout_hi_incr_s cnf71xx; }; union cvmx_mio_ptp_ckout_lo_incr { uint64_t u64; struct cvmx_mio_ptp_ckout_lo_incr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:32; uint64_t frnanosec:32; +#else + uint64_t frnanosec:32; + uint64_t nanosec:32; +#endif } s; struct cvmx_mio_ptp_ckout_lo_incr_s cn61xx; struct cvmx_mio_ptp_ckout_lo_incr_s cn66xx; struct cvmx_mio_ptp_ckout_lo_incr_s cn68xx; + struct cvmx_mio_ptp_ckout_lo_incr_s cnf71xx; }; union cvmx_mio_ptp_ckout_thresh_hi { uint64_t u64; struct cvmx_mio_ptp_ckout_thresh_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t nanosec:64; +#else uint64_t nanosec:64; +#endif } s; struct cvmx_mio_ptp_ckout_thresh_hi_s cn61xx; struct cvmx_mio_ptp_ckout_thresh_hi_s cn66xx; struct cvmx_mio_ptp_ckout_thresh_hi_s cn68xx; + struct cvmx_mio_ptp_ckout_thresh_hi_s cnf71xx; }; union cvmx_mio_ptp_ckout_thresh_lo { uint64_t u64; struct cvmx_mio_ptp_ckout_thresh_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t frnanosec:32; +#else + uint64_t frnanosec:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_ptp_ckout_thresh_lo_s cn61xx; struct cvmx_mio_ptp_ckout_thresh_lo_s cn66xx; struct cvmx_mio_ptp_ckout_thresh_lo_s cn68xx; + struct cvmx_mio_ptp_ckout_thresh_lo_s cnf71xx; }; union cvmx_mio_ptp_clock_cfg { uint64_t u64; struct cvmx_mio_ptp_clock_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t pps:1; uint64_t ckout:1; @@ -1768,9 +2801,32 @@ union cvmx_mio_ptp_clock_cfg { uint64_t ext_clk_in:6; uint64_t ext_clk_en:1; uint64_t ptp_en:1; +#else + uint64_t ptp_en:1; + uint64_t ext_clk_en:1; + uint64_t ext_clk_in:6; + uint64_t tstmp_en:1; + uint64_t tstmp_edge:1; + uint64_t tstmp_in:6; + uint64_t evcnt_en:1; + uint64_t evcnt_edge:1; + uint64_t evcnt_in:6; + uint64_t ckout_en:1; + uint64_t ckout_inv:1; + uint64_t ckout_out:4; + uint64_t pps_en:1; + uint64_t pps_inv:1; + uint64_t pps_out:5; + uint64_t ckout_out4:1; + uint64_t ext_clk_edge:2; + uint64_t ckout:1; + uint64_t pps:1; + uint64_t reserved_42_63:22; +#endif } s; struct cvmx_mio_ptp_clock_cfg_s cn61xx; struct cvmx_mio_ptp_clock_cfg_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t evcnt_in:6; uint64_t evcnt_edge:1; @@ -1781,9 +2837,22 @@ union cvmx_mio_ptp_clock_cfg { uint64_t ext_clk_in:6; uint64_t ext_clk_en:1; uint64_t ptp_en:1; +#else + uint64_t ptp_en:1; + uint64_t ext_clk_en:1; + uint64_t ext_clk_in:6; + uint64_t tstmp_en:1; + uint64_t tstmp_edge:1; + uint64_t tstmp_in:6; + uint64_t evcnt_en:1; + uint64_t evcnt_edge:1; + uint64_t evcnt_in:6; + uint64_t reserved_24_63:40; +#endif } cn63xx; struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1; struct cvmx_mio_ptp_clock_cfg_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ext_clk_edge:2; uint64_t ckout_out4:1; @@ -1802,16 +2871,42 @@ union cvmx_mio_ptp_clock_cfg { uint64_t ext_clk_in:6; uint64_t ext_clk_en:1; uint64_t ptp_en:1; +#else + uint64_t ptp_en:1; + uint64_t ext_clk_en:1; + uint64_t ext_clk_in:6; + uint64_t tstmp_en:1; + uint64_t tstmp_edge:1; + uint64_t tstmp_in:6; + uint64_t evcnt_en:1; + uint64_t evcnt_edge:1; + uint64_t evcnt_in:6; + uint64_t ckout_en:1; + uint64_t ckout_inv:1; + uint64_t ckout_out:4; + uint64_t pps_en:1; + uint64_t pps_inv:1; + uint64_t pps_out:5; + uint64_t ckout_out4:1; + uint64_t ext_clk_edge:2; + uint64_t reserved_40_63:24; +#endif } cn66xx; struct cvmx_mio_ptp_clock_cfg_s cn68xx; struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1; + struct cvmx_mio_ptp_clock_cfg_s cnf71xx; }; union cvmx_mio_ptp_clock_comp { uint64_t u64; struct cvmx_mio_ptp_clock_comp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:32; uint64_t frnanosec:32; +#else + uint64_t frnanosec:32; + uint64_t nanosec:32; +#endif } s; struct cvmx_mio_ptp_clock_comp_s cn61xx; struct cvmx_mio_ptp_clock_comp_s cn63xx; @@ -1819,12 +2914,17 @@ union cvmx_mio_ptp_clock_comp { struct cvmx_mio_ptp_clock_comp_s cn66xx; struct cvmx_mio_ptp_clock_comp_s cn68xx; struct cvmx_mio_ptp_clock_comp_s cn68xxp1; + struct cvmx_mio_ptp_clock_comp_s cnf71xx; }; union cvmx_mio_ptp_clock_hi { uint64_t u64; struct cvmx_mio_ptp_clock_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t nanosec:64; +#else uint64_t nanosec:64; +#endif } s; struct cvmx_mio_ptp_clock_hi_s cn61xx; struct cvmx_mio_ptp_clock_hi_s cn63xx; @@ -1832,13 +2932,19 @@ union cvmx_mio_ptp_clock_hi { struct cvmx_mio_ptp_clock_hi_s cn66xx; struct cvmx_mio_ptp_clock_hi_s cn68xx; struct cvmx_mio_ptp_clock_hi_s cn68xxp1; + struct cvmx_mio_ptp_clock_hi_s cnf71xx; }; union cvmx_mio_ptp_clock_lo { uint64_t u64; struct cvmx_mio_ptp_clock_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t frnanosec:32; +#else + uint64_t frnanosec:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_ptp_clock_lo_s cn61xx; struct cvmx_mio_ptp_clock_lo_s cn63xx; @@ -1846,12 +2952,17 @@ union cvmx_mio_ptp_clock_lo { struct cvmx_mio_ptp_clock_lo_s cn66xx; struct cvmx_mio_ptp_clock_lo_s cn68xx; struct cvmx_mio_ptp_clock_lo_s cn68xxp1; + struct cvmx_mio_ptp_clock_lo_s cnf71xx; }; union cvmx_mio_ptp_evt_cnt { uint64_t u64; struct cvmx_mio_ptp_evt_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t cntr:64; +#else uint64_t cntr:64; +#endif } s; struct cvmx_mio_ptp_evt_cnt_s cn61xx; struct cvmx_mio_ptp_evt_cnt_s cn63xx; @@ -1859,55 +2970,97 @@ union cvmx_mio_ptp_evt_cnt { struct cvmx_mio_ptp_evt_cnt_s cn66xx; struct cvmx_mio_ptp_evt_cnt_s cn68xx; struct cvmx_mio_ptp_evt_cnt_s cn68xxp1; + struct cvmx_mio_ptp_evt_cnt_s cnf71xx; +}; + +union cvmx_mio_ptp_phy_1pps_in { + uint64_t u64; + struct cvmx_mio_ptp_phy_1pps_in_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_5_63:59; + uint64_t sel:5; +#else + uint64_t sel:5; + uint64_t reserved_5_63:59; +#endif + } s; + struct cvmx_mio_ptp_phy_1pps_in_s cnf71xx; }; union cvmx_mio_ptp_pps_hi_incr { uint64_t u64; struct cvmx_mio_ptp_pps_hi_incr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:32; uint64_t frnanosec:32; +#else + uint64_t frnanosec:32; + uint64_t nanosec:32; +#endif } s; struct cvmx_mio_ptp_pps_hi_incr_s cn61xx; struct cvmx_mio_ptp_pps_hi_incr_s cn66xx; struct cvmx_mio_ptp_pps_hi_incr_s cn68xx; + struct cvmx_mio_ptp_pps_hi_incr_s cnf71xx; }; union cvmx_mio_ptp_pps_lo_incr { uint64_t u64; struct cvmx_mio_ptp_pps_lo_incr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:32; uint64_t frnanosec:32; +#else + uint64_t frnanosec:32; + uint64_t nanosec:32; +#endif } s; struct cvmx_mio_ptp_pps_lo_incr_s cn61xx; struct cvmx_mio_ptp_pps_lo_incr_s cn66xx; struct cvmx_mio_ptp_pps_lo_incr_s cn68xx; + struct cvmx_mio_ptp_pps_lo_incr_s cnf71xx; }; union cvmx_mio_ptp_pps_thresh_hi { uint64_t u64; struct cvmx_mio_ptp_pps_thresh_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t nanosec:64; +#else uint64_t nanosec:64; +#endif } s; struct cvmx_mio_ptp_pps_thresh_hi_s cn61xx; struct cvmx_mio_ptp_pps_thresh_hi_s cn66xx; struct cvmx_mio_ptp_pps_thresh_hi_s cn68xx; + struct cvmx_mio_ptp_pps_thresh_hi_s cnf71xx; }; union cvmx_mio_ptp_pps_thresh_lo { uint64_t u64; struct cvmx_mio_ptp_pps_thresh_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t frnanosec:32; +#else + uint64_t frnanosec:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_ptp_pps_thresh_lo_s cn61xx; struct cvmx_mio_ptp_pps_thresh_lo_s cn66xx; struct cvmx_mio_ptp_pps_thresh_lo_s cn68xx; + struct cvmx_mio_ptp_pps_thresh_lo_s cnf71xx; }; union cvmx_mio_ptp_timestamp { uint64_t u64; struct cvmx_mio_ptp_timestamp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t nanosec:64; +#else + uint64_t nanosec:64; +#endif } s; struct cvmx_mio_ptp_timestamp_s cn61xx; struct cvmx_mio_ptp_timestamp_s cn63xx; @@ -1915,35 +3068,79 @@ union cvmx_mio_ptp_timestamp { struct cvmx_mio_ptp_timestamp_s cn66xx; struct cvmx_mio_ptp_timestamp_s cn68xx; struct cvmx_mio_ptp_timestamp_s cn68xxp1; + struct cvmx_mio_ptp_timestamp_s cnf71xx; }; union cvmx_mio_qlmx_cfg { uint64_t u64; struct cvmx_mio_qlmx_cfg_s { - uint64_t reserved_12_63:52; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t prtmode:1; + uint64_t reserved_12_13:2; uint64_t qlm_spd:4; uint64_t reserved_4_7:4; uint64_t qlm_cfg:4; +#else + uint64_t qlm_cfg:4; + uint64_t reserved_4_7:4; + uint64_t qlm_spd:4; + uint64_t reserved_12_13:2; + uint64_t prtmode:1; + uint64_t reserved_15_63:49; +#endif } s; struct cvmx_mio_qlmx_cfg_cn61xx { - uint64_t reserved_12_63:52; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_15_63:49; + uint64_t prtmode:1; + uint64_t reserved_12_13:2; uint64_t qlm_spd:4; uint64_t reserved_2_7:6; uint64_t qlm_cfg:2; +#else + uint64_t qlm_cfg:2; + uint64_t reserved_2_7:6; + uint64_t qlm_spd:4; + uint64_t reserved_12_13:2; + uint64_t prtmode:1; + uint64_t reserved_15_63:49; +#endif } cn61xx; - struct cvmx_mio_qlmx_cfg_s cn66xx; + struct cvmx_mio_qlmx_cfg_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t qlm_spd:4; + uint64_t reserved_4_7:4; + uint64_t qlm_cfg:4; +#else + uint64_t qlm_cfg:4; + uint64_t reserved_4_7:4; + uint64_t qlm_spd:4; + uint64_t reserved_12_63:52; +#endif + } cn66xx; struct cvmx_mio_qlmx_cfg_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t qlm_spd:4; uint64_t reserved_3_7:5; uint64_t qlm_cfg:3; +#else + uint64_t qlm_cfg:3; + uint64_t reserved_3_7:5; + uint64_t qlm_spd:4; + uint64_t reserved_12_63:52; +#endif } cn68xx; struct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1; + struct cvmx_mio_qlmx_cfg_cn61xx cnf71xx; }; union cvmx_mio_rst_boot { uint64_t u64; struct cvmx_mio_rst_boot_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t chipkill:1; uint64_t jtcsrdis:1; uint64_t ejtagdis:1; @@ -1963,8 +3160,30 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; +#else + uint64_t rboot_pin:1; + uint64_t rboot:1; + uint64_t lboot:10; + uint64_t qlm0_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm2_spd:4; + uint64_t pnr_mul:6; + uint64_t c_mul:6; + uint64_t qlm3_spd:4; + uint64_t qlm4_spd:4; + uint64_t reserved_44_47:4; + uint64_t lboot_ext:2; + uint64_t reserved_50_57:8; + uint64_t jt_tstmode:1; + uint64_t ckill_ppdis:1; + uint64_t romen:1; + uint64_t ejtagdis:1; + uint64_t jtcsrdis:1; + uint64_t chipkill:1; +#endif } s; struct cvmx_mio_rst_boot_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t chipkill:1; uint64_t jtcsrdis:1; uint64_t ejtagdis:1; @@ -1982,8 +3201,28 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; +#else + uint64_t rboot_pin:1; + uint64_t rboot:1; + uint64_t lboot:10; + uint64_t qlm0_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm2_spd:4; + uint64_t pnr_mul:6; + uint64_t c_mul:6; + uint64_t reserved_36_47:12; + uint64_t lboot_ext:2; + uint64_t reserved_50_57:8; + uint64_t jt_tstmode:1; + uint64_t ckill_ppdis:1; + uint64_t romen:1; + uint64_t ejtagdis:1; + uint64_t jtcsrdis:1; + uint64_t chipkill:1; +#endif } cn61xx; struct cvmx_mio_rst_boot_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t c_mul:6; uint64_t pnr_mul:6; @@ -1993,9 +3232,21 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; +#else + uint64_t rboot_pin:1; + uint64_t rboot:1; + uint64_t lboot:10; + uint64_t qlm0_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm2_spd:4; + uint64_t pnr_mul:6; + uint64_t c_mul:6; + uint64_t reserved_36_63:28; +#endif } cn63xx; struct cvmx_mio_rst_boot_cn63xx cn63xxp1; struct cvmx_mio_rst_boot_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t chipkill:1; uint64_t jtcsrdis:1; uint64_t ejtagdis:1; @@ -2012,8 +3263,27 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; +#else + uint64_t rboot_pin:1; + uint64_t rboot:1; + uint64_t lboot:10; + uint64_t qlm0_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm2_spd:4; + uint64_t pnr_mul:6; + uint64_t c_mul:6; + uint64_t reserved_36_47:12; + uint64_t lboot_ext:2; + uint64_t reserved_50_58:9; + uint64_t ckill_ppdis:1; + uint64_t romen:1; + uint64_t ejtagdis:1; + uint64_t jtcsrdis:1; + uint64_t chipkill:1; +#endif } cn66xx; struct cvmx_mio_rst_boot_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t jt_tstmode:1; uint64_t reserved_44_57:14; @@ -2027,8 +3297,24 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; +#else + uint64_t rboot_pin:1; + uint64_t rboot:1; + uint64_t lboot:10; + uint64_t qlm0_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm2_spd:4; + uint64_t pnr_mul:6; + uint64_t c_mul:6; + uint64_t qlm3_spd:4; + uint64_t qlm4_spd:4; + uint64_t reserved_44_57:14; + uint64_t jt_tstmode:1; + uint64_t reserved_59_63:5; +#endif } cn68xx; struct cvmx_mio_rst_boot_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t qlm4_spd:4; uint64_t qlm3_spd:4; @@ -2040,55 +3326,107 @@ union cvmx_mio_rst_boot { uint64_t lboot:10; uint64_t rboot:1; uint64_t rboot_pin:1; +#else + uint64_t rboot_pin:1; + uint64_t rboot:1; + uint64_t lboot:10; + uint64_t qlm0_spd:4; + uint64_t qlm1_spd:4; + uint64_t qlm2_spd:4; + uint64_t pnr_mul:6; + uint64_t c_mul:6; + uint64_t qlm3_spd:4; + uint64_t qlm4_spd:4; + uint64_t reserved_44_63:20; +#endif } cn68xxp1; + struct cvmx_mio_rst_boot_cn61xx cnf71xx; }; union cvmx_mio_rst_cfg { uint64_t u64; struct cvmx_mio_rst_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t cntl_clr_bist:1; uint64_t warm_clr_bist:1; uint64_t soft_clr_bist:1; +#else + uint64_t soft_clr_bist:1; + uint64_t warm_clr_bist:1; + uint64_t cntl_clr_bist:1; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_mio_rst_cfg_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bist_delay:58; uint64_t reserved_3_5:3; uint64_t cntl_clr_bist:1; uint64_t warm_clr_bist:1; uint64_t soft_clr_bist:1; +#else + uint64_t soft_clr_bist:1; + uint64_t warm_clr_bist:1; + uint64_t cntl_clr_bist:1; + uint64_t reserved_3_5:3; + uint64_t bist_delay:58; +#endif } cn61xx; struct cvmx_mio_rst_cfg_cn61xx cn63xx; struct cvmx_mio_rst_cfg_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bist_delay:58; uint64_t reserved_2_5:4; uint64_t warm_clr_bist:1; uint64_t soft_clr_bist:1; +#else + uint64_t soft_clr_bist:1; + uint64_t warm_clr_bist:1; + uint64_t reserved_2_5:4; + uint64_t bist_delay:58; +#endif } cn63xxp1; struct cvmx_mio_rst_cfg_cn61xx cn66xx; struct cvmx_mio_rst_cfg_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bist_delay:56; uint64_t reserved_3_7:5; uint64_t cntl_clr_bist:1; uint64_t warm_clr_bist:1; uint64_t soft_clr_bist:1; +#else + uint64_t soft_clr_bist:1; + uint64_t warm_clr_bist:1; + uint64_t cntl_clr_bist:1; + uint64_t reserved_3_7:5; + uint64_t bist_delay:56; +#endif } cn68xx; struct cvmx_mio_rst_cfg_cn68xx cn68xxp1; + struct cvmx_mio_rst_cfg_cn61xx cnf71xx; }; union cvmx_mio_rst_ckill { uint64_t u64; struct cvmx_mio_rst_ckill_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_47_63:17; uint64_t timer:47; +#else + uint64_t timer:47; + uint64_t reserved_47_63:17; +#endif } s; struct cvmx_mio_rst_ckill_s cn61xx; struct cvmx_mio_rst_ckill_s cn66xx; + struct cvmx_mio_rst_ckill_s cnf71xx; }; union cvmx_mio_rst_cntlx { uint64_t u64; struct cvmx_mio_rst_cntlx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t in_rev_ln:1; uint64_t rev_lanes:1; @@ -2102,9 +3440,25 @@ union cvmx_mio_rst_cntlx { uint64_t rst_rcv:1; uint64_t rst_chip:1; uint64_t rst_val:1; +#else + uint64_t rst_val:1; + uint64_t rst_chip:1; + uint64_t rst_rcv:1; + uint64_t rst_drv:1; + uint64_t prtmode:2; + uint64_t host_mode:1; + uint64_t rst_link:1; + uint64_t rst_done:1; + uint64_t prst_link:1; + uint64_t gen1_only:1; + uint64_t rev_lanes:1; + uint64_t in_rev_ln:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_mio_rst_cntlx_s cn61xx; struct cvmx_mio_rst_cntlx_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t prst_link:1; uint64_t rst_done:1; @@ -2115,13 +3469,27 @@ union cvmx_mio_rst_cntlx { uint64_t rst_rcv:1; uint64_t rst_chip:1; uint64_t rst_val:1; +#else + uint64_t rst_val:1; + uint64_t rst_chip:1; + uint64_t rst_rcv:1; + uint64_t rst_drv:1; + uint64_t prtmode:2; + uint64_t host_mode:1; + uint64_t rst_link:1; + uint64_t rst_done:1; + uint64_t prst_link:1; + uint64_t reserved_10_63:54; +#endif } cn66xx; struct cvmx_mio_rst_cntlx_cn66xx cn68xx; + struct cvmx_mio_rst_cntlx_s cnf71xx; }; union cvmx_mio_rst_ctlx { uint64_t u64; struct cvmx_mio_rst_ctlx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t in_rev_ln:1; uint64_t rev_lanes:1; @@ -2135,9 +3503,25 @@ union cvmx_mio_rst_ctlx { uint64_t rst_rcv:1; uint64_t rst_chip:1; uint64_t rst_val:1; +#else + uint64_t rst_val:1; + uint64_t rst_chip:1; + uint64_t rst_rcv:1; + uint64_t rst_drv:1; + uint64_t prtmode:2; + uint64_t host_mode:1; + uint64_t rst_link:1; + uint64_t rst_done:1; + uint64_t prst_link:1; + uint64_t gen1_only:1; + uint64_t rev_lanes:1; + uint64_t in_rev_ln:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_mio_rst_ctlx_s cn61xx; struct cvmx_mio_rst_ctlx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t prst_link:1; uint64_t rst_done:1; @@ -2148,8 +3532,21 @@ union cvmx_mio_rst_ctlx { uint64_t rst_rcv:1; uint64_t rst_chip:1; uint64_t rst_val:1; +#else + uint64_t rst_val:1; + uint64_t rst_chip:1; + uint64_t rst_rcv:1; + uint64_t rst_drv:1; + uint64_t prtmode:2; + uint64_t host_mode:1; + uint64_t rst_link:1; + uint64_t rst_done:1; + uint64_t prst_link:1; + uint64_t reserved_10_63:54; +#endif } cn63xx; struct cvmx_mio_rst_ctlx_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t rst_done:1; uint64_t rst_link:1; @@ -2159,18 +3556,36 @@ union cvmx_mio_rst_ctlx { uint64_t rst_rcv:1; uint64_t rst_chip:1; uint64_t rst_val:1; +#else + uint64_t rst_val:1; + uint64_t rst_chip:1; + uint64_t rst_rcv:1; + uint64_t rst_drv:1; + uint64_t prtmode:2; + uint64_t host_mode:1; + uint64_t rst_link:1; + uint64_t rst_done:1; + uint64_t reserved_9_63:55; +#endif } cn63xxp1; struct cvmx_mio_rst_ctlx_cn63xx cn66xx; struct cvmx_mio_rst_ctlx_cn63xx cn68xx; struct cvmx_mio_rst_ctlx_cn63xx cn68xxp1; + struct cvmx_mio_rst_ctlx_s cnf71xx; }; union cvmx_mio_rst_delay { uint64_t u64; struct cvmx_mio_rst_delay_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t warm_rst_dly:16; uint64_t soft_rst_dly:16; +#else + uint64_t soft_rst_dly:16; + uint64_t warm_rst_dly:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_mio_rst_delay_s cn61xx; struct cvmx_mio_rst_delay_s cn63xx; @@ -2178,11 +3593,13 @@ union cvmx_mio_rst_delay { struct cvmx_mio_rst_delay_s cn66xx; struct cvmx_mio_rst_delay_s cn68xx; struct cvmx_mio_rst_delay_s cn68xxp1; + struct cvmx_mio_rst_delay_s cnf71xx; }; union cvmx_mio_rst_int { uint64_t u64; struct cvmx_mio_rst_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t perst1:1; uint64_t perst0:1; @@ -2191,25 +3608,46 @@ union cvmx_mio_rst_int { uint64_t rst_link2:1; uint64_t rst_link1:1; uint64_t rst_link0:1; +#else + uint64_t rst_link0:1; + uint64_t rst_link1:1; + uint64_t rst_link2:1; + uint64_t rst_link3:1; + uint64_t reserved_4_7:4; + uint64_t perst0:1; + uint64_t perst1:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_mio_rst_int_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t perst1:1; uint64_t perst0:1; uint64_t reserved_2_7:6; uint64_t rst_link1:1; uint64_t rst_link0:1; +#else + uint64_t rst_link0:1; + uint64_t rst_link1:1; + uint64_t reserved_2_7:6; + uint64_t perst0:1; + uint64_t perst1:1; + uint64_t reserved_10_63:54; +#endif } cn61xx; struct cvmx_mio_rst_int_cn61xx cn63xx; struct cvmx_mio_rst_int_cn61xx cn63xxp1; struct cvmx_mio_rst_int_s cn66xx; struct cvmx_mio_rst_int_cn61xx cn68xx; struct cvmx_mio_rst_int_cn61xx cn68xxp1; + struct cvmx_mio_rst_int_cn61xx cnf71xx; }; union cvmx_mio_rst_int_en { uint64_t u64; struct cvmx_mio_rst_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t perst1:1; uint64_t perst0:1; @@ -2218,25 +3656,46 @@ union cvmx_mio_rst_int_en { uint64_t rst_link2:1; uint64_t rst_link1:1; uint64_t rst_link0:1; +#else + uint64_t rst_link0:1; + uint64_t rst_link1:1; + uint64_t rst_link2:1; + uint64_t rst_link3:1; + uint64_t reserved_4_7:4; + uint64_t perst0:1; + uint64_t perst1:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_mio_rst_int_en_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t perst1:1; uint64_t perst0:1; uint64_t reserved_2_7:6; uint64_t rst_link1:1; uint64_t rst_link0:1; +#else + uint64_t rst_link0:1; + uint64_t rst_link1:1; + uint64_t reserved_2_7:6; + uint64_t perst0:1; + uint64_t perst1:1; + uint64_t reserved_10_63:54; +#endif } cn61xx; struct cvmx_mio_rst_int_en_cn61xx cn63xx; struct cvmx_mio_rst_int_en_cn61xx cn63xxp1; struct cvmx_mio_rst_int_en_s cn66xx; struct cvmx_mio_rst_int_en_cn61xx cn68xx; struct cvmx_mio_rst_int_en_cn61xx cn68xxp1; + struct cvmx_mio_rst_int_en_cn61xx cnf71xx; }; union cvmx_mio_twsx_int { uint64_t u64; struct cvmx_mio_twsx_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t scl:1; uint64_t sda:1; @@ -2250,11 +3709,27 @@ union cvmx_mio_twsx_int { uint64_t core_int:1; uint64_t ts_int:1; uint64_t st_int:1; +#else + uint64_t st_int:1; + uint64_t ts_int:1; + uint64_t core_int:1; + uint64_t reserved_3_3:1; + uint64_t st_en:1; + uint64_t ts_en:1; + uint64_t core_en:1; + uint64_t reserved_7_7:1; + uint64_t sda_ovr:1; + uint64_t scl_ovr:1; + uint64_t sda:1; + uint64_t scl:1; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_mio_twsx_int_s cn30xx; struct cvmx_mio_twsx_int_s cn31xx; struct cvmx_mio_twsx_int_s cn38xx; struct cvmx_mio_twsx_int_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t core_en:1; uint64_t ts_en:1; @@ -2263,6 +3738,16 @@ union cvmx_mio_twsx_int { uint64_t core_int:1; uint64_t ts_int:1; uint64_t st_int:1; +#else + uint64_t st_int:1; + uint64_t ts_int:1; + uint64_t core_int:1; + uint64_t reserved_3_3:1; + uint64_t st_en:1; + uint64_t ts_en:1; + uint64_t core_en:1; + uint64_t reserved_7_63:57; +#endif } cn38xxp2; struct cvmx_mio_twsx_int_s cn50xx; struct cvmx_mio_twsx_int_s cn52xx; @@ -2277,11 +3762,13 @@ union cvmx_mio_twsx_int { struct cvmx_mio_twsx_int_s cn66xx; struct cvmx_mio_twsx_int_s cn68xx; struct cvmx_mio_twsx_int_s cn68xxp1; + struct cvmx_mio_twsx_int_s cnf71xx; }; union cvmx_mio_twsx_sw_twsi { uint64_t u64; struct cvmx_mio_twsx_sw_twsi_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t v:1; uint64_t slonly:1; uint64_t eia:1; @@ -2294,6 +3781,20 @@ union cvmx_mio_twsx_sw_twsi { uint64_t ia:5; uint64_t eop_ia:3; uint64_t d:32; +#else + uint64_t d:32; + uint64_t eop_ia:3; + uint64_t ia:5; + uint64_t a:10; + uint64_t scr:2; + uint64_t size:3; + uint64_t sovr:1; + uint64_t r:1; + uint64_t op:4; + uint64_t eia:1; + uint64_t slonly:1; + uint64_t v:1; +#endif } s; struct cvmx_mio_twsx_sw_twsi_s cn30xx; struct cvmx_mio_twsx_sw_twsi_s cn31xx; @@ -2312,14 +3813,21 @@ union cvmx_mio_twsx_sw_twsi { struct cvmx_mio_twsx_sw_twsi_s cn66xx; struct cvmx_mio_twsx_sw_twsi_s cn68xx; struct cvmx_mio_twsx_sw_twsi_s cn68xxp1; + struct cvmx_mio_twsx_sw_twsi_s cnf71xx; }; union cvmx_mio_twsx_sw_twsi_ext { uint64_t u64; struct cvmx_mio_twsx_sw_twsi_ext_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ia:8; uint64_t d:32; +#else + uint64_t d:32; + uint64_t ia:8; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx; struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx; @@ -2338,14 +3846,21 @@ union cvmx_mio_twsx_sw_twsi_ext { struct cvmx_mio_twsx_sw_twsi_ext_s cn66xx; struct cvmx_mio_twsx_sw_twsi_ext_s cn68xx; struct cvmx_mio_twsx_sw_twsi_ext_s cn68xxp1; + struct cvmx_mio_twsx_sw_twsi_ext_s cnf71xx; }; union cvmx_mio_twsx_twsi_sw { uint64_t u64; struct cvmx_mio_twsx_twsi_sw_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t v:2; uint64_t reserved_32_61:30; uint64_t d:32; +#else + uint64_t d:32; + uint64_t reserved_32_61:30; + uint64_t v:2; +#endif } s; struct cvmx_mio_twsx_twsi_sw_s cn30xx; struct cvmx_mio_twsx_twsi_sw_s cn31xx; @@ -2364,13 +3879,19 @@ union cvmx_mio_twsx_twsi_sw { struct cvmx_mio_twsx_twsi_sw_s cn66xx; struct cvmx_mio_twsx_twsi_sw_s cn68xx; struct cvmx_mio_twsx_twsi_sw_s cn68xxp1; + struct cvmx_mio_twsx_twsi_sw_s cnf71xx; }; union cvmx_mio_uartx_dlh { uint64_t u64; struct cvmx_mio_uartx_dlh_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dlh:8; +#else + uint64_t dlh:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_dlh_s cn30xx; struct cvmx_mio_uartx_dlh_s cn31xx; @@ -2389,13 +3910,19 @@ union cvmx_mio_uartx_dlh { struct cvmx_mio_uartx_dlh_s cn66xx; struct cvmx_mio_uartx_dlh_s cn68xx; struct cvmx_mio_uartx_dlh_s cn68xxp1; + struct cvmx_mio_uartx_dlh_s cnf71xx; }; union cvmx_mio_uartx_dll { uint64_t u64; struct cvmx_mio_uartx_dll_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dll:8; +#else + uint64_t dll:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_dll_s cn30xx; struct cvmx_mio_uartx_dll_s cn31xx; @@ -2414,13 +3941,19 @@ union cvmx_mio_uartx_dll { struct cvmx_mio_uartx_dll_s cn66xx; struct cvmx_mio_uartx_dll_s cn68xx; struct cvmx_mio_uartx_dll_s cn68xxp1; + struct cvmx_mio_uartx_dll_s cnf71xx; }; union cvmx_mio_uartx_far { uint64_t u64; struct cvmx_mio_uartx_far_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t far:1; +#else + uint64_t far:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uartx_far_s cn30xx; struct cvmx_mio_uartx_far_s cn31xx; @@ -2439,11 +3972,13 @@ union cvmx_mio_uartx_far { struct cvmx_mio_uartx_far_s cn66xx; struct cvmx_mio_uartx_far_s cn68xx; struct cvmx_mio_uartx_far_s cn68xxp1; + struct cvmx_mio_uartx_far_s cnf71xx; }; union cvmx_mio_uartx_fcr { uint64_t u64; struct cvmx_mio_uartx_fcr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rxtrig:2; uint64_t txtrig:2; @@ -2451,6 +3986,15 @@ union cvmx_mio_uartx_fcr { uint64_t txfr:1; uint64_t rxfr:1; uint64_t en:1; +#else + uint64_t en:1; + uint64_t rxfr:1; + uint64_t txfr:1; + uint64_t reserved_3_3:1; + uint64_t txtrig:2; + uint64_t rxtrig:2; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_fcr_s cn30xx; struct cvmx_mio_uartx_fcr_s cn31xx; @@ -2469,13 +4013,19 @@ union cvmx_mio_uartx_fcr { struct cvmx_mio_uartx_fcr_s cn66xx; struct cvmx_mio_uartx_fcr_s cn68xx; struct cvmx_mio_uartx_fcr_s cn68xxp1; + struct cvmx_mio_uartx_fcr_s cnf71xx; }; union cvmx_mio_uartx_htx { uint64_t u64; struct cvmx_mio_uartx_htx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t htx:1; +#else + uint64_t htx:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uartx_htx_s cn30xx; struct cvmx_mio_uartx_htx_s cn31xx; @@ -2494,11 +4044,13 @@ union cvmx_mio_uartx_htx { struct cvmx_mio_uartx_htx_s cn66xx; struct cvmx_mio_uartx_htx_s cn68xx; struct cvmx_mio_uartx_htx_s cn68xxp1; + struct cvmx_mio_uartx_htx_s cnf71xx; }; union cvmx_mio_uartx_ier { uint64_t u64; struct cvmx_mio_uartx_ier_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ptime:1; uint64_t reserved_4_6:3; @@ -2506,6 +4058,15 @@ union cvmx_mio_uartx_ier { uint64_t elsi:1; uint64_t etbei:1; uint64_t erbfi:1; +#else + uint64_t erbfi:1; + uint64_t etbei:1; + uint64_t elsi:1; + uint64_t edssi:1; + uint64_t reserved_4_6:3; + uint64_t ptime:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_ier_s cn30xx; struct cvmx_mio_uartx_ier_s cn31xx; @@ -2524,15 +4085,23 @@ union cvmx_mio_uartx_ier { struct cvmx_mio_uartx_ier_s cn66xx; struct cvmx_mio_uartx_ier_s cn68xx; struct cvmx_mio_uartx_ier_s cn68xxp1; + struct cvmx_mio_uartx_ier_s cnf71xx; }; union cvmx_mio_uartx_iir { uint64_t u64; struct cvmx_mio_uartx_iir_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t fen:2; uint64_t reserved_4_5:2; uint64_t iid:4; +#else + uint64_t iid:4; + uint64_t reserved_4_5:2; + uint64_t fen:2; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_iir_s cn30xx; struct cvmx_mio_uartx_iir_s cn31xx; @@ -2551,11 +4120,13 @@ union cvmx_mio_uartx_iir { struct cvmx_mio_uartx_iir_s cn66xx; struct cvmx_mio_uartx_iir_s cn68xx; struct cvmx_mio_uartx_iir_s cn68xxp1; + struct cvmx_mio_uartx_iir_s cnf71xx; }; union cvmx_mio_uartx_lcr { uint64_t u64; struct cvmx_mio_uartx_lcr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dlab:1; uint64_t brk:1; @@ -2564,6 +4135,16 @@ union cvmx_mio_uartx_lcr { uint64_t pen:1; uint64_t stop:1; uint64_t cls:2; +#else + uint64_t cls:2; + uint64_t stop:1; + uint64_t pen:1; + uint64_t eps:1; + uint64_t reserved_5_5:1; + uint64_t brk:1; + uint64_t dlab:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_lcr_s cn30xx; struct cvmx_mio_uartx_lcr_s cn31xx; @@ -2582,11 +4163,13 @@ union cvmx_mio_uartx_lcr { struct cvmx_mio_uartx_lcr_s cn66xx; struct cvmx_mio_uartx_lcr_s cn68xx; struct cvmx_mio_uartx_lcr_s cn68xxp1; + struct cvmx_mio_uartx_lcr_s cnf71xx; }; union cvmx_mio_uartx_lsr { uint64_t u64; struct cvmx_mio_uartx_lsr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ferr:1; uint64_t temt:1; @@ -2596,6 +4179,17 @@ union cvmx_mio_uartx_lsr { uint64_t pe:1; uint64_t oe:1; uint64_t dr:1; +#else + uint64_t dr:1; + uint64_t oe:1; + uint64_t pe:1; + uint64_t fe:1; + uint64_t bi:1; + uint64_t thre:1; + uint64_t temt:1; + uint64_t ferr:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_lsr_s cn30xx; struct cvmx_mio_uartx_lsr_s cn31xx; @@ -2614,11 +4208,13 @@ union cvmx_mio_uartx_lsr { struct cvmx_mio_uartx_lsr_s cn66xx; struct cvmx_mio_uartx_lsr_s cn68xx; struct cvmx_mio_uartx_lsr_s cn68xxp1; + struct cvmx_mio_uartx_lsr_s cnf71xx; }; union cvmx_mio_uartx_mcr { uint64_t u64; struct cvmx_mio_uartx_mcr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t afce:1; uint64_t loop:1; @@ -2626,6 +4222,15 @@ union cvmx_mio_uartx_mcr { uint64_t out1:1; uint64_t rts:1; uint64_t dtr:1; +#else + uint64_t dtr:1; + uint64_t rts:1; + uint64_t out1:1; + uint64_t out2:1; + uint64_t loop:1; + uint64_t afce:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_mio_uartx_mcr_s cn30xx; struct cvmx_mio_uartx_mcr_s cn31xx; @@ -2644,11 +4249,13 @@ union cvmx_mio_uartx_mcr { struct cvmx_mio_uartx_mcr_s cn66xx; struct cvmx_mio_uartx_mcr_s cn68xx; struct cvmx_mio_uartx_mcr_s cn68xxp1; + struct cvmx_mio_uartx_mcr_s cnf71xx; }; union cvmx_mio_uartx_msr { uint64_t u64; struct cvmx_mio_uartx_msr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dcd:1; uint64_t ri:1; @@ -2658,6 +4265,17 @@ union cvmx_mio_uartx_msr { uint64_t teri:1; uint64_t ddsr:1; uint64_t dcts:1; +#else + uint64_t dcts:1; + uint64_t ddsr:1; + uint64_t teri:1; + uint64_t ddcd:1; + uint64_t cts:1; + uint64_t dsr:1; + uint64_t ri:1; + uint64_t dcd:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_msr_s cn30xx; struct cvmx_mio_uartx_msr_s cn31xx; @@ -2676,13 +4294,19 @@ union cvmx_mio_uartx_msr { struct cvmx_mio_uartx_msr_s cn66xx; struct cvmx_mio_uartx_msr_s cn68xx; struct cvmx_mio_uartx_msr_s cn68xxp1; + struct cvmx_mio_uartx_msr_s cnf71xx; }; union cvmx_mio_uartx_rbr { uint64_t u64; struct cvmx_mio_uartx_rbr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rbr:8; +#else + uint64_t rbr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_rbr_s cn30xx; struct cvmx_mio_uartx_rbr_s cn31xx; @@ -2701,13 +4325,19 @@ union cvmx_mio_uartx_rbr { struct cvmx_mio_uartx_rbr_s cn66xx; struct cvmx_mio_uartx_rbr_s cn68xx; struct cvmx_mio_uartx_rbr_s cn68xxp1; + struct cvmx_mio_uartx_rbr_s cnf71xx; }; union cvmx_mio_uartx_rfl { uint64_t u64; struct cvmx_mio_uartx_rfl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t rfl:7; +#else + uint64_t rfl:7; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_mio_uartx_rfl_s cn30xx; struct cvmx_mio_uartx_rfl_s cn31xx; @@ -2726,15 +4356,23 @@ union cvmx_mio_uartx_rfl { struct cvmx_mio_uartx_rfl_s cn66xx; struct cvmx_mio_uartx_rfl_s cn68xx; struct cvmx_mio_uartx_rfl_s cn68xxp1; + struct cvmx_mio_uartx_rfl_s cnf71xx; }; union cvmx_mio_uartx_rfw { uint64_t u64; struct cvmx_mio_uartx_rfw_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t rffe:1; uint64_t rfpe:1; uint64_t rfwd:8; +#else + uint64_t rfwd:8; + uint64_t rfpe:1; + uint64_t rffe:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_mio_uartx_rfw_s cn30xx; struct cvmx_mio_uartx_rfw_s cn31xx; @@ -2753,13 +4391,19 @@ union cvmx_mio_uartx_rfw { struct cvmx_mio_uartx_rfw_s cn66xx; struct cvmx_mio_uartx_rfw_s cn68xx; struct cvmx_mio_uartx_rfw_s cn68xxp1; + struct cvmx_mio_uartx_rfw_s cnf71xx; }; union cvmx_mio_uartx_sbcr { uint64_t u64; struct cvmx_mio_uartx_sbcr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t sbcr:1; +#else + uint64_t sbcr:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uartx_sbcr_s cn30xx; struct cvmx_mio_uartx_sbcr_s cn31xx; @@ -2778,13 +4422,19 @@ union cvmx_mio_uartx_sbcr { struct cvmx_mio_uartx_sbcr_s cn66xx; struct cvmx_mio_uartx_sbcr_s cn68xx; struct cvmx_mio_uartx_sbcr_s cn68xxp1; + struct cvmx_mio_uartx_sbcr_s cnf71xx; }; union cvmx_mio_uartx_scr { uint64_t u64; struct cvmx_mio_uartx_scr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t scr:8; +#else + uint64_t scr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_scr_s cn30xx; struct cvmx_mio_uartx_scr_s cn31xx; @@ -2803,13 +4453,19 @@ union cvmx_mio_uartx_scr { struct cvmx_mio_uartx_scr_s cn66xx; struct cvmx_mio_uartx_scr_s cn68xx; struct cvmx_mio_uartx_scr_s cn68xxp1; + struct cvmx_mio_uartx_scr_s cnf71xx; }; union cvmx_mio_uartx_sfe { uint64_t u64; struct cvmx_mio_uartx_sfe_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t sfe:1; +#else + uint64_t sfe:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uartx_sfe_s cn30xx; struct cvmx_mio_uartx_sfe_s cn31xx; @@ -2828,15 +4484,23 @@ union cvmx_mio_uartx_sfe { struct cvmx_mio_uartx_sfe_s cn66xx; struct cvmx_mio_uartx_sfe_s cn68xx; struct cvmx_mio_uartx_sfe_s cn68xxp1; + struct cvmx_mio_uartx_sfe_s cnf71xx; }; union cvmx_mio_uartx_srr { uint64_t u64; struct cvmx_mio_uartx_srr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t stfr:1; uint64_t srfr:1; uint64_t usr:1; +#else + uint64_t usr:1; + uint64_t srfr:1; + uint64_t stfr:1; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_mio_uartx_srr_s cn30xx; struct cvmx_mio_uartx_srr_s cn31xx; @@ -2855,13 +4519,19 @@ union cvmx_mio_uartx_srr { struct cvmx_mio_uartx_srr_s cn66xx; struct cvmx_mio_uartx_srr_s cn68xx; struct cvmx_mio_uartx_srr_s cn68xxp1; + struct cvmx_mio_uartx_srr_s cnf71xx; }; union cvmx_mio_uartx_srt { uint64_t u64; struct cvmx_mio_uartx_srt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t srt:2; +#else + uint64_t srt:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_uartx_srt_s cn30xx; struct cvmx_mio_uartx_srt_s cn31xx; @@ -2880,13 +4550,19 @@ union cvmx_mio_uartx_srt { struct cvmx_mio_uartx_srt_s cn66xx; struct cvmx_mio_uartx_srt_s cn68xx; struct cvmx_mio_uartx_srt_s cn68xxp1; + struct cvmx_mio_uartx_srt_s cnf71xx; }; union cvmx_mio_uartx_srts { uint64_t u64; struct cvmx_mio_uartx_srts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t srts:1; +#else + uint64_t srts:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uartx_srts_s cn30xx; struct cvmx_mio_uartx_srts_s cn31xx; @@ -2905,13 +4581,19 @@ union cvmx_mio_uartx_srts { struct cvmx_mio_uartx_srts_s cn66xx; struct cvmx_mio_uartx_srts_s cn68xx; struct cvmx_mio_uartx_srts_s cn68xxp1; + struct cvmx_mio_uartx_srts_s cnf71xx; }; union cvmx_mio_uartx_stt { uint64_t u64; struct cvmx_mio_uartx_stt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t stt:2; +#else + uint64_t stt:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_uartx_stt_s cn30xx; struct cvmx_mio_uartx_stt_s cn31xx; @@ -2930,13 +4612,19 @@ union cvmx_mio_uartx_stt { struct cvmx_mio_uartx_stt_s cn66xx; struct cvmx_mio_uartx_stt_s cn68xx; struct cvmx_mio_uartx_stt_s cn68xxp1; + struct cvmx_mio_uartx_stt_s cnf71xx; }; union cvmx_mio_uartx_tfl { uint64_t u64; struct cvmx_mio_uartx_tfl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t tfl:7; +#else + uint64_t tfl:7; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_mio_uartx_tfl_s cn30xx; struct cvmx_mio_uartx_tfl_s cn31xx; @@ -2955,13 +4643,19 @@ union cvmx_mio_uartx_tfl { struct cvmx_mio_uartx_tfl_s cn66xx; struct cvmx_mio_uartx_tfl_s cn68xx; struct cvmx_mio_uartx_tfl_s cn68xxp1; + struct cvmx_mio_uartx_tfl_s cnf71xx; }; union cvmx_mio_uartx_tfr { uint64_t u64; struct cvmx_mio_uartx_tfr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t tfr:8; +#else + uint64_t tfr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_tfr_s cn30xx; struct cvmx_mio_uartx_tfr_s cn31xx; @@ -2980,13 +4674,19 @@ union cvmx_mio_uartx_tfr { struct cvmx_mio_uartx_tfr_s cn66xx; struct cvmx_mio_uartx_tfr_s cn68xx; struct cvmx_mio_uartx_tfr_s cn68xxp1; + struct cvmx_mio_uartx_tfr_s cnf71xx; }; union cvmx_mio_uartx_thr { uint64_t u64; struct cvmx_mio_uartx_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t thr:8; +#else + uint64_t thr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uartx_thr_s cn30xx; struct cvmx_mio_uartx_thr_s cn31xx; @@ -3005,17 +4705,27 @@ union cvmx_mio_uartx_thr { struct cvmx_mio_uartx_thr_s cn66xx; struct cvmx_mio_uartx_thr_s cn68xx; struct cvmx_mio_uartx_thr_s cn68xxp1; + struct cvmx_mio_uartx_thr_s cnf71xx; }; union cvmx_mio_uartx_usr { uint64_t u64; struct cvmx_mio_uartx_usr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t rff:1; uint64_t rfne:1; uint64_t tfe:1; uint64_t tfnf:1; uint64_t busy:1; +#else + uint64_t busy:1; + uint64_t tfnf:1; + uint64_t tfe:1; + uint64_t rfne:1; + uint64_t rff:1; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_mio_uartx_usr_s cn30xx; struct cvmx_mio_uartx_usr_s cn31xx; @@ -3034,13 +4744,19 @@ union cvmx_mio_uartx_usr { struct cvmx_mio_uartx_usr_s cn66xx; struct cvmx_mio_uartx_usr_s cn68xx; struct cvmx_mio_uartx_usr_s cn68xxp1; + struct cvmx_mio_uartx_usr_s cnf71xx; }; union cvmx_mio_uart2_dlh { uint64_t u64; struct cvmx_mio_uart2_dlh_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dlh:8; +#else + uint64_t dlh:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_dlh_s cn52xx; struct cvmx_mio_uart2_dlh_s cn52xxp1; @@ -3049,8 +4765,13 @@ union cvmx_mio_uart2_dlh { union cvmx_mio_uart2_dll { uint64_t u64; struct cvmx_mio_uart2_dll_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dll:8; +#else + uint64_t dll:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_dll_s cn52xx; struct cvmx_mio_uart2_dll_s cn52xxp1; @@ -3059,8 +4780,13 @@ union cvmx_mio_uart2_dll { union cvmx_mio_uart2_far { uint64_t u64; struct cvmx_mio_uart2_far_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t far:1; +#else + uint64_t far:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uart2_far_s cn52xx; struct cvmx_mio_uart2_far_s cn52xxp1; @@ -3069,6 +4795,7 @@ union cvmx_mio_uart2_far { union cvmx_mio_uart2_fcr { uint64_t u64; struct cvmx_mio_uart2_fcr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rxtrig:2; uint64_t txtrig:2; @@ -3076,6 +4803,15 @@ union cvmx_mio_uart2_fcr { uint64_t txfr:1; uint64_t rxfr:1; uint64_t en:1; +#else + uint64_t en:1; + uint64_t rxfr:1; + uint64_t txfr:1; + uint64_t reserved_3_3:1; + uint64_t txtrig:2; + uint64_t rxtrig:2; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_fcr_s cn52xx; struct cvmx_mio_uart2_fcr_s cn52xxp1; @@ -3084,8 +4820,13 @@ union cvmx_mio_uart2_fcr { union cvmx_mio_uart2_htx { uint64_t u64; struct cvmx_mio_uart2_htx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t htx:1; +#else + uint64_t htx:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uart2_htx_s cn52xx; struct cvmx_mio_uart2_htx_s cn52xxp1; @@ -3094,6 +4835,7 @@ union cvmx_mio_uart2_htx { union cvmx_mio_uart2_ier { uint64_t u64; struct cvmx_mio_uart2_ier_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ptime:1; uint64_t reserved_4_6:3; @@ -3101,6 +4843,15 @@ union cvmx_mio_uart2_ier { uint64_t elsi:1; uint64_t etbei:1; uint64_t erbfi:1; +#else + uint64_t erbfi:1; + uint64_t etbei:1; + uint64_t elsi:1; + uint64_t edssi:1; + uint64_t reserved_4_6:3; + uint64_t ptime:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_ier_s cn52xx; struct cvmx_mio_uart2_ier_s cn52xxp1; @@ -3109,10 +4860,17 @@ union cvmx_mio_uart2_ier { union cvmx_mio_uart2_iir { uint64_t u64; struct cvmx_mio_uart2_iir_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t fen:2; uint64_t reserved_4_5:2; uint64_t iid:4; +#else + uint64_t iid:4; + uint64_t reserved_4_5:2; + uint64_t fen:2; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_iir_s cn52xx; struct cvmx_mio_uart2_iir_s cn52xxp1; @@ -3121,6 +4879,7 @@ union cvmx_mio_uart2_iir { union cvmx_mio_uart2_lcr { uint64_t u64; struct cvmx_mio_uart2_lcr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dlab:1; uint64_t brk:1; @@ -3129,6 +4888,16 @@ union cvmx_mio_uart2_lcr { uint64_t pen:1; uint64_t stop:1; uint64_t cls:2; +#else + uint64_t cls:2; + uint64_t stop:1; + uint64_t pen:1; + uint64_t eps:1; + uint64_t reserved_5_5:1; + uint64_t brk:1; + uint64_t dlab:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_lcr_s cn52xx; struct cvmx_mio_uart2_lcr_s cn52xxp1; @@ -3137,6 +4906,7 @@ union cvmx_mio_uart2_lcr { union cvmx_mio_uart2_lsr { uint64_t u64; struct cvmx_mio_uart2_lsr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ferr:1; uint64_t temt:1; @@ -3146,6 +4916,17 @@ union cvmx_mio_uart2_lsr { uint64_t pe:1; uint64_t oe:1; uint64_t dr:1; +#else + uint64_t dr:1; + uint64_t oe:1; + uint64_t pe:1; + uint64_t fe:1; + uint64_t bi:1; + uint64_t thre:1; + uint64_t temt:1; + uint64_t ferr:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_lsr_s cn52xx; struct cvmx_mio_uart2_lsr_s cn52xxp1; @@ -3154,6 +4935,7 @@ union cvmx_mio_uart2_lsr { union cvmx_mio_uart2_mcr { uint64_t u64; struct cvmx_mio_uart2_mcr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t afce:1; uint64_t loop:1; @@ -3161,6 +4943,15 @@ union cvmx_mio_uart2_mcr { uint64_t out1:1; uint64_t rts:1; uint64_t dtr:1; +#else + uint64_t dtr:1; + uint64_t rts:1; + uint64_t out1:1; + uint64_t out2:1; + uint64_t loop:1; + uint64_t afce:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_mio_uart2_mcr_s cn52xx; struct cvmx_mio_uart2_mcr_s cn52xxp1; @@ -3169,6 +4960,7 @@ union cvmx_mio_uart2_mcr { union cvmx_mio_uart2_msr { uint64_t u64; struct cvmx_mio_uart2_msr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t dcd:1; uint64_t ri:1; @@ -3178,6 +4970,17 @@ union cvmx_mio_uart2_msr { uint64_t teri:1; uint64_t ddsr:1; uint64_t dcts:1; +#else + uint64_t dcts:1; + uint64_t ddsr:1; + uint64_t teri:1; + uint64_t ddcd:1; + uint64_t cts:1; + uint64_t dsr:1; + uint64_t ri:1; + uint64_t dcd:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_msr_s cn52xx; struct cvmx_mio_uart2_msr_s cn52xxp1; @@ -3186,8 +4989,13 @@ union cvmx_mio_uart2_msr { union cvmx_mio_uart2_rbr { uint64_t u64; struct cvmx_mio_uart2_rbr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rbr:8; +#else + uint64_t rbr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_rbr_s cn52xx; struct cvmx_mio_uart2_rbr_s cn52xxp1; @@ -3196,8 +5004,13 @@ union cvmx_mio_uart2_rbr { union cvmx_mio_uart2_rfl { uint64_t u64; struct cvmx_mio_uart2_rfl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t rfl:7; +#else + uint64_t rfl:7; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_mio_uart2_rfl_s cn52xx; struct cvmx_mio_uart2_rfl_s cn52xxp1; @@ -3206,10 +5019,17 @@ union cvmx_mio_uart2_rfl { union cvmx_mio_uart2_rfw { uint64_t u64; struct cvmx_mio_uart2_rfw_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t rffe:1; uint64_t rfpe:1; uint64_t rfwd:8; +#else + uint64_t rfwd:8; + uint64_t rfpe:1; + uint64_t rffe:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_mio_uart2_rfw_s cn52xx; struct cvmx_mio_uart2_rfw_s cn52xxp1; @@ -3218,8 +5038,13 @@ union cvmx_mio_uart2_rfw { union cvmx_mio_uart2_sbcr { uint64_t u64; struct cvmx_mio_uart2_sbcr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t sbcr:1; +#else + uint64_t sbcr:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uart2_sbcr_s cn52xx; struct cvmx_mio_uart2_sbcr_s cn52xxp1; @@ -3228,8 +5053,13 @@ union cvmx_mio_uart2_sbcr { union cvmx_mio_uart2_scr { uint64_t u64; struct cvmx_mio_uart2_scr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t scr:8; +#else + uint64_t scr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_scr_s cn52xx; struct cvmx_mio_uart2_scr_s cn52xxp1; @@ -3238,8 +5068,13 @@ union cvmx_mio_uart2_scr { union cvmx_mio_uart2_sfe { uint64_t u64; struct cvmx_mio_uart2_sfe_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t sfe:1; +#else + uint64_t sfe:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uart2_sfe_s cn52xx; struct cvmx_mio_uart2_sfe_s cn52xxp1; @@ -3248,10 +5083,17 @@ union cvmx_mio_uart2_sfe { union cvmx_mio_uart2_srr { uint64_t u64; struct cvmx_mio_uart2_srr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t stfr:1; uint64_t srfr:1; uint64_t usr:1; +#else + uint64_t usr:1; + uint64_t srfr:1; + uint64_t stfr:1; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_mio_uart2_srr_s cn52xx; struct cvmx_mio_uart2_srr_s cn52xxp1; @@ -3260,8 +5102,13 @@ union cvmx_mio_uart2_srr { union cvmx_mio_uart2_srt { uint64_t u64; struct cvmx_mio_uart2_srt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t srt:2; +#else + uint64_t srt:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_uart2_srt_s cn52xx; struct cvmx_mio_uart2_srt_s cn52xxp1; @@ -3270,8 +5117,13 @@ union cvmx_mio_uart2_srt { union cvmx_mio_uart2_srts { uint64_t u64; struct cvmx_mio_uart2_srts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t srts:1; +#else + uint64_t srts:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_mio_uart2_srts_s cn52xx; struct cvmx_mio_uart2_srts_s cn52xxp1; @@ -3280,8 +5132,13 @@ union cvmx_mio_uart2_srts { union cvmx_mio_uart2_stt { uint64_t u64; struct cvmx_mio_uart2_stt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t stt:2; +#else + uint64_t stt:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_mio_uart2_stt_s cn52xx; struct cvmx_mio_uart2_stt_s cn52xxp1; @@ -3290,8 +5147,13 @@ union cvmx_mio_uart2_stt { union cvmx_mio_uart2_tfl { uint64_t u64; struct cvmx_mio_uart2_tfl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t tfl:7; +#else + uint64_t tfl:7; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_mio_uart2_tfl_s cn52xx; struct cvmx_mio_uart2_tfl_s cn52xxp1; @@ -3300,8 +5162,13 @@ union cvmx_mio_uart2_tfl { union cvmx_mio_uart2_tfr { uint64_t u64; struct cvmx_mio_uart2_tfr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t tfr:8; +#else + uint64_t tfr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_tfr_s cn52xx; struct cvmx_mio_uart2_tfr_s cn52xxp1; @@ -3310,8 +5177,13 @@ union cvmx_mio_uart2_tfr { union cvmx_mio_uart2_thr { uint64_t u64; struct cvmx_mio_uart2_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t thr:8; +#else + uint64_t thr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mio_uart2_thr_s cn52xx; struct cvmx_mio_uart2_thr_s cn52xxp1; @@ -3320,12 +5192,21 @@ union cvmx_mio_uart2_thr { union cvmx_mio_uart2_usr { uint64_t u64; struct cvmx_mio_uart2_usr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t rff:1; uint64_t rfne:1; uint64_t tfe:1; uint64_t tfnf:1; uint64_t busy:1; +#else + uint64_t busy:1; + uint64_t tfnf:1; + uint64_t tfe:1; + uint64_t rfne:1; + uint64_t rff:1; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_mio_uart2_usr_s cn52xx; struct cvmx_mio_uart2_usr_s cn52xxp1; diff --git a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h index 7057c447e69..3155e6019dc 100644 --- a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -47,6 +47,7 @@ union cvmx_mixx_bist { uint64_t u64; struct cvmx_mixx_bist_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t opfdat:1; uint64_t mrgdat:1; @@ -54,24 +55,46 @@ union cvmx_mixx_bist { uint64_t ipfdat:1; uint64_t irfdat:1; uint64_t orfdat:1; +#else + uint64_t orfdat:1; + uint64_t irfdat:1; + uint64_t ipfdat:1; + uint64_t mrqdat:1; + uint64_t mrgdat:1; + uint64_t opfdat:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_mixx_bist_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t mrqdat:1; uint64_t ipfdat:1; uint64_t irfdat:1; uint64_t orfdat:1; +#else + uint64_t orfdat:1; + uint64_t irfdat:1; + uint64_t ipfdat:1; + uint64_t mrqdat:1; + uint64_t reserved_4_63:60; +#endif } cn52xx; struct cvmx_mixx_bist_cn52xx cn52xxp1; struct cvmx_mixx_bist_cn52xx cn56xx; struct cvmx_mixx_bist_cn52xx cn56xxp1; + struct cvmx_mixx_bist_s cn61xx; struct cvmx_mixx_bist_s cn63xx; struct cvmx_mixx_bist_s cn63xxp1; + struct cvmx_mixx_bist_s cn66xx; + struct cvmx_mixx_bist_s cn68xx; + struct cvmx_mixx_bist_s cn68xxp1; }; union cvmx_mixx_ctl { uint64_t u64; struct cvmx_mixx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t ts_thresh:4; uint64_t crc_strip:1; @@ -81,8 +104,20 @@ union cvmx_mixx_ctl { uint64_t lendian:1; uint64_t nbtarb:1; uint64_t mrq_hwm:2; +#else + uint64_t mrq_hwm:2; + uint64_t nbtarb:1; + uint64_t lendian:1; + uint64_t reset:1; + uint64_t en:1; + uint64_t busy:1; + uint64_t crc_strip:1; + uint64_t ts_thresh:4; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_mixx_ctl_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t crc_strip:1; uint64_t busy:1; @@ -91,17 +126,32 @@ union cvmx_mixx_ctl { uint64_t lendian:1; uint64_t nbtarb:1; uint64_t mrq_hwm:2; +#else + uint64_t mrq_hwm:2; + uint64_t nbtarb:1; + uint64_t lendian:1; + uint64_t reset:1; + uint64_t en:1; + uint64_t busy:1; + uint64_t crc_strip:1; + uint64_t reserved_8_63:56; +#endif } cn52xx; struct cvmx_mixx_ctl_cn52xx cn52xxp1; struct cvmx_mixx_ctl_cn52xx cn56xx; struct cvmx_mixx_ctl_cn52xx cn56xxp1; + struct cvmx_mixx_ctl_s cn61xx; struct cvmx_mixx_ctl_s cn63xx; struct cvmx_mixx_ctl_s cn63xxp1; + struct cvmx_mixx_ctl_s cn66xx; + struct cvmx_mixx_ctl_s cn68xx; + struct cvmx_mixx_ctl_s cn68xxp1; }; union cvmx_mixx_intena { uint64_t u64; struct cvmx_mixx_intena_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t tsena:1; uint64_t orunena:1; @@ -111,8 +161,20 @@ union cvmx_mixx_intena { uint64_t othena:1; uint64_t ivfena:1; uint64_t ovfena:1; +#else + uint64_t ovfena:1; + uint64_t ivfena:1; + uint64_t othena:1; + uint64_t ithena:1; + uint64_t data_drpena:1; + uint64_t irunena:1; + uint64_t orunena:1; + uint64_t tsena:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mixx_intena_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t orunena:1; uint64_t irunena:1; @@ -121,84 +183,148 @@ union cvmx_mixx_intena { uint64_t othena:1; uint64_t ivfena:1; uint64_t ovfena:1; +#else + uint64_t ovfena:1; + uint64_t ivfena:1; + uint64_t othena:1; + uint64_t ithena:1; + uint64_t data_drpena:1; + uint64_t irunena:1; + uint64_t orunena:1; + uint64_t reserved_7_63:57; +#endif } cn52xx; struct cvmx_mixx_intena_cn52xx cn52xxp1; struct cvmx_mixx_intena_cn52xx cn56xx; struct cvmx_mixx_intena_cn52xx cn56xxp1; + struct cvmx_mixx_intena_s cn61xx; struct cvmx_mixx_intena_s cn63xx; struct cvmx_mixx_intena_s cn63xxp1; + struct cvmx_mixx_intena_s cn66xx; + struct cvmx_mixx_intena_s cn68xx; + struct cvmx_mixx_intena_s cn68xxp1; }; union cvmx_mixx_ircnt { uint64_t u64; struct cvmx_mixx_ircnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t ircnt:20; +#else + uint64_t ircnt:20; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_mixx_ircnt_s cn52xx; struct cvmx_mixx_ircnt_s cn52xxp1; struct cvmx_mixx_ircnt_s cn56xx; struct cvmx_mixx_ircnt_s cn56xxp1; + struct cvmx_mixx_ircnt_s cn61xx; struct cvmx_mixx_ircnt_s cn63xx; struct cvmx_mixx_ircnt_s cn63xxp1; + struct cvmx_mixx_ircnt_s cn66xx; + struct cvmx_mixx_ircnt_s cn68xx; + struct cvmx_mixx_ircnt_s cn68xxp1; }; union cvmx_mixx_irhwm { uint64_t u64; struct cvmx_mixx_irhwm_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t ibplwm:20; uint64_t irhwm:20; +#else + uint64_t irhwm:20; + uint64_t ibplwm:20; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_mixx_irhwm_s cn52xx; struct cvmx_mixx_irhwm_s cn52xxp1; struct cvmx_mixx_irhwm_s cn56xx; struct cvmx_mixx_irhwm_s cn56xxp1; + struct cvmx_mixx_irhwm_s cn61xx; struct cvmx_mixx_irhwm_s cn63xx; struct cvmx_mixx_irhwm_s cn63xxp1; + struct cvmx_mixx_irhwm_s cn66xx; + struct cvmx_mixx_irhwm_s cn68xx; + struct cvmx_mixx_irhwm_s cn68xxp1; }; union cvmx_mixx_iring1 { uint64_t u64; struct cvmx_mixx_iring1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t isize:20; uint64_t ibase:37; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t ibase:37; + uint64_t isize:20; + uint64_t reserved_60_63:4; +#endif } s; struct cvmx_mixx_iring1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t isize:20; uint64_t reserved_36_39:4; uint64_t ibase:33; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t ibase:33; + uint64_t reserved_36_39:4; + uint64_t isize:20; + uint64_t reserved_60_63:4; +#endif } cn52xx; struct cvmx_mixx_iring1_cn52xx cn52xxp1; struct cvmx_mixx_iring1_cn52xx cn56xx; struct cvmx_mixx_iring1_cn52xx cn56xxp1; + struct cvmx_mixx_iring1_s cn61xx; struct cvmx_mixx_iring1_s cn63xx; struct cvmx_mixx_iring1_s cn63xxp1; + struct cvmx_mixx_iring1_s cn66xx; + struct cvmx_mixx_iring1_s cn68xx; + struct cvmx_mixx_iring1_s cn68xxp1; }; union cvmx_mixx_iring2 { uint64_t u64; struct cvmx_mixx_iring2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_52_63:12; uint64_t itlptr:20; uint64_t reserved_20_31:12; uint64_t idbell:20; +#else + uint64_t idbell:20; + uint64_t reserved_20_31:12; + uint64_t itlptr:20; + uint64_t reserved_52_63:12; +#endif } s; struct cvmx_mixx_iring2_s cn52xx; struct cvmx_mixx_iring2_s cn52xxp1; struct cvmx_mixx_iring2_s cn56xx; struct cvmx_mixx_iring2_s cn56xxp1; + struct cvmx_mixx_iring2_s cn61xx; struct cvmx_mixx_iring2_s cn63xx; struct cvmx_mixx_iring2_s cn63xxp1; + struct cvmx_mixx_iring2_s cn66xx; + struct cvmx_mixx_iring2_s cn68xx; + struct cvmx_mixx_iring2_s cn68xxp1; }; union cvmx_mixx_isr { uint64_t u64; struct cvmx_mixx_isr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ts:1; uint64_t orun:1; @@ -208,8 +334,20 @@ union cvmx_mixx_isr { uint64_t orthresh:1; uint64_t idblovf:1; uint64_t odblovf:1; +#else + uint64_t odblovf:1; + uint64_t idblovf:1; + uint64_t orthresh:1; + uint64_t irthresh:1; + uint64_t data_drp:1; + uint64_t irun:1; + uint64_t orun:1; + uint64_t ts:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_mixx_isr_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t orun:1; uint64_t irun:1; @@ -218,117 +356,211 @@ union cvmx_mixx_isr { uint64_t orthresh:1; uint64_t idblovf:1; uint64_t odblovf:1; +#else + uint64_t odblovf:1; + uint64_t idblovf:1; + uint64_t orthresh:1; + uint64_t irthresh:1; + uint64_t data_drp:1; + uint64_t irun:1; + uint64_t orun:1; + uint64_t reserved_7_63:57; +#endif } cn52xx; struct cvmx_mixx_isr_cn52xx cn52xxp1; struct cvmx_mixx_isr_cn52xx cn56xx; struct cvmx_mixx_isr_cn52xx cn56xxp1; + struct cvmx_mixx_isr_s cn61xx; struct cvmx_mixx_isr_s cn63xx; struct cvmx_mixx_isr_s cn63xxp1; + struct cvmx_mixx_isr_s cn66xx; + struct cvmx_mixx_isr_s cn68xx; + struct cvmx_mixx_isr_s cn68xxp1; }; union cvmx_mixx_orcnt { uint64_t u64; struct cvmx_mixx_orcnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t orcnt:20; +#else + uint64_t orcnt:20; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_mixx_orcnt_s cn52xx; struct cvmx_mixx_orcnt_s cn52xxp1; struct cvmx_mixx_orcnt_s cn56xx; struct cvmx_mixx_orcnt_s cn56xxp1; + struct cvmx_mixx_orcnt_s cn61xx; struct cvmx_mixx_orcnt_s cn63xx; struct cvmx_mixx_orcnt_s cn63xxp1; + struct cvmx_mixx_orcnt_s cn66xx; + struct cvmx_mixx_orcnt_s cn68xx; + struct cvmx_mixx_orcnt_s cn68xxp1; }; union cvmx_mixx_orhwm { uint64_t u64; struct cvmx_mixx_orhwm_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t orhwm:20; +#else + uint64_t orhwm:20; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_mixx_orhwm_s cn52xx; struct cvmx_mixx_orhwm_s cn52xxp1; struct cvmx_mixx_orhwm_s cn56xx; struct cvmx_mixx_orhwm_s cn56xxp1; + struct cvmx_mixx_orhwm_s cn61xx; struct cvmx_mixx_orhwm_s cn63xx; struct cvmx_mixx_orhwm_s cn63xxp1; + struct cvmx_mixx_orhwm_s cn66xx; + struct cvmx_mixx_orhwm_s cn68xx; + struct cvmx_mixx_orhwm_s cn68xxp1; }; union cvmx_mixx_oring1 { uint64_t u64; struct cvmx_mixx_oring1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t osize:20; uint64_t obase:37; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t obase:37; + uint64_t osize:20; + uint64_t reserved_60_63:4; +#endif } s; struct cvmx_mixx_oring1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t osize:20; uint64_t reserved_36_39:4; uint64_t obase:33; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t obase:33; + uint64_t reserved_36_39:4; + uint64_t osize:20; + uint64_t reserved_60_63:4; +#endif } cn52xx; struct cvmx_mixx_oring1_cn52xx cn52xxp1; struct cvmx_mixx_oring1_cn52xx cn56xx; struct cvmx_mixx_oring1_cn52xx cn56xxp1; + struct cvmx_mixx_oring1_s cn61xx; struct cvmx_mixx_oring1_s cn63xx; struct cvmx_mixx_oring1_s cn63xxp1; + struct cvmx_mixx_oring1_s cn66xx; + struct cvmx_mixx_oring1_s cn68xx; + struct cvmx_mixx_oring1_s cn68xxp1; }; union cvmx_mixx_oring2 { uint64_t u64; struct cvmx_mixx_oring2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_52_63:12; uint64_t otlptr:20; uint64_t reserved_20_31:12; uint64_t odbell:20; +#else + uint64_t odbell:20; + uint64_t reserved_20_31:12; + uint64_t otlptr:20; + uint64_t reserved_52_63:12; +#endif } s; struct cvmx_mixx_oring2_s cn52xx; struct cvmx_mixx_oring2_s cn52xxp1; struct cvmx_mixx_oring2_s cn56xx; struct cvmx_mixx_oring2_s cn56xxp1; + struct cvmx_mixx_oring2_s cn61xx; struct cvmx_mixx_oring2_s cn63xx; struct cvmx_mixx_oring2_s cn63xxp1; + struct cvmx_mixx_oring2_s cn66xx; + struct cvmx_mixx_oring2_s cn68xx; + struct cvmx_mixx_oring2_s cn68xxp1; }; union cvmx_mixx_remcnt { uint64_t u64; struct cvmx_mixx_remcnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_52_63:12; uint64_t iremcnt:20; uint64_t reserved_20_31:12; uint64_t oremcnt:20; +#else + uint64_t oremcnt:20; + uint64_t reserved_20_31:12; + uint64_t iremcnt:20; + uint64_t reserved_52_63:12; +#endif } s; struct cvmx_mixx_remcnt_s cn52xx; struct cvmx_mixx_remcnt_s cn52xxp1; struct cvmx_mixx_remcnt_s cn56xx; struct cvmx_mixx_remcnt_s cn56xxp1; + struct cvmx_mixx_remcnt_s cn61xx; struct cvmx_mixx_remcnt_s cn63xx; struct cvmx_mixx_remcnt_s cn63xxp1; + struct cvmx_mixx_remcnt_s cn66xx; + struct cvmx_mixx_remcnt_s cn68xx; + struct cvmx_mixx_remcnt_s cn68xxp1; }; union cvmx_mixx_tsctl { uint64_t u64; struct cvmx_mixx_tsctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t tsavl:5; uint64_t reserved_13_15:3; uint64_t tstot:5; uint64_t reserved_5_7:3; uint64_t tscnt:5; +#else + uint64_t tscnt:5; + uint64_t reserved_5_7:3; + uint64_t tstot:5; + uint64_t reserved_13_15:3; + uint64_t tsavl:5; + uint64_t reserved_21_63:43; +#endif } s; + struct cvmx_mixx_tsctl_s cn61xx; struct cvmx_mixx_tsctl_s cn63xx; struct cvmx_mixx_tsctl_s cn63xxp1; + struct cvmx_mixx_tsctl_s cn66xx; + struct cvmx_mixx_tsctl_s cn68xx; + struct cvmx_mixx_tsctl_s cn68xxp1; }; union cvmx_mixx_tstamp { uint64_t u64; struct cvmx_mixx_tstamp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t tstamp:64; +#else + uint64_t tstamp:64; +#endif } s; + struct cvmx_mixx_tstamp_s cn61xx; struct cvmx_mixx_tstamp_s cn63xx; struct cvmx_mixx_tstamp_s cn63xxp1; + struct cvmx_mixx_tstamp_s cn66xx; + struct cvmx_mixx_tstamp_s cn68xx; + struct cvmx_mixx_tstamp_s cn68xxp1; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-mpi-defs.h b/arch/mips/include/asm/octeon/cvmx-mpi-defs.h new file mode 100644 index 00000000000..4615b102625 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-mpi-defs.h @@ -0,0 +1,328 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_MPI_DEFS_H__ +#define __CVMX_MPI_DEFS_H__ + +#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull)) +#define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8) +#define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull)) +#define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull)) + +union cvmx_mpi_cfg { + uint64_t u64; + struct cvmx_mpi_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t clkdiv:13; + uint64_t csena3:1; + uint64_t csena2:1; + uint64_t csena1:1; + uint64_t csena0:1; + uint64_t cslate:1; + uint64_t tritx:1; + uint64_t idleclks:2; + uint64_t cshi:1; + uint64_t csena:1; + uint64_t int_ena:1; + uint64_t lsbfirst:1; + uint64_t wireor:1; + uint64_t clk_cont:1; + uint64_t idlelo:1; + uint64_t enable:1; +#else + uint64_t enable:1; + uint64_t idlelo:1; + uint64_t clk_cont:1; + uint64_t wireor:1; + uint64_t lsbfirst:1; + uint64_t int_ena:1; + uint64_t csena:1; + uint64_t cshi:1; + uint64_t idleclks:2; + uint64_t tritx:1; + uint64_t cslate:1; + uint64_t csena0:1; + uint64_t csena1:1; + uint64_t csena2:1; + uint64_t csena3:1; + uint64_t clkdiv:13; + uint64_t reserved_29_63:35; +#endif + } s; + struct cvmx_mpi_cfg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t clkdiv:13; + uint64_t reserved_12_15:4; + uint64_t cslate:1; + uint64_t tritx:1; + uint64_t idleclks:2; + uint64_t cshi:1; + uint64_t csena:1; + uint64_t int_ena:1; + uint64_t lsbfirst:1; + uint64_t wireor:1; + uint64_t clk_cont:1; + uint64_t idlelo:1; + uint64_t enable:1; +#else + uint64_t enable:1; + uint64_t idlelo:1; + uint64_t clk_cont:1; + uint64_t wireor:1; + uint64_t lsbfirst:1; + uint64_t int_ena:1; + uint64_t csena:1; + uint64_t cshi:1; + uint64_t idleclks:2; + uint64_t tritx:1; + uint64_t cslate:1; + uint64_t reserved_12_15:4; + uint64_t clkdiv:13; + uint64_t reserved_29_63:35; +#endif + } cn30xx; + struct cvmx_mpi_cfg_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t clkdiv:13; + uint64_t reserved_11_15:5; + uint64_t tritx:1; + uint64_t idleclks:2; + uint64_t cshi:1; + uint64_t csena:1; + uint64_t int_ena:1; + uint64_t lsbfirst:1; + uint64_t wireor:1; + uint64_t clk_cont:1; + uint64_t idlelo:1; + uint64_t enable:1; +#else + uint64_t enable:1; + uint64_t idlelo:1; + uint64_t clk_cont:1; + uint64_t wireor:1; + uint64_t lsbfirst:1; + uint64_t int_ena:1; + uint64_t csena:1; + uint64_t cshi:1; + uint64_t idleclks:2; + uint64_t tritx:1; + uint64_t reserved_11_15:5; + uint64_t clkdiv:13; + uint64_t reserved_29_63:35; +#endif + } cn31xx; + struct cvmx_mpi_cfg_cn30xx cn50xx; + struct cvmx_mpi_cfg_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t clkdiv:13; + uint64_t reserved_14_15:2; + uint64_t csena1:1; + uint64_t csena0:1; + uint64_t cslate:1; + uint64_t tritx:1; + uint64_t idleclks:2; + uint64_t cshi:1; + uint64_t reserved_6_6:1; + uint64_t int_ena:1; + uint64_t lsbfirst:1; + uint64_t wireor:1; + uint64_t clk_cont:1; + uint64_t idlelo:1; + uint64_t enable:1; +#else + uint64_t enable:1; + uint64_t idlelo:1; + uint64_t clk_cont:1; + uint64_t wireor:1; + uint64_t lsbfirst:1; + uint64_t int_ena:1; + uint64_t reserved_6_6:1; + uint64_t cshi:1; + uint64_t idleclks:2; + uint64_t tritx:1; + uint64_t cslate:1; + uint64_t csena0:1; + uint64_t csena1:1; + uint64_t reserved_14_15:2; + uint64_t clkdiv:13; + uint64_t reserved_29_63:35; +#endif + } cn61xx; + struct cvmx_mpi_cfg_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t clkdiv:13; + uint64_t csena3:1; + uint64_t csena2:1; + uint64_t reserved_12_13:2; + uint64_t cslate:1; + uint64_t tritx:1; + uint64_t idleclks:2; + uint64_t cshi:1; + uint64_t reserved_6_6:1; + uint64_t int_ena:1; + uint64_t lsbfirst:1; + uint64_t wireor:1; + uint64_t clk_cont:1; + uint64_t idlelo:1; + uint64_t enable:1; +#else + uint64_t enable:1; + uint64_t idlelo:1; + uint64_t clk_cont:1; + uint64_t wireor:1; + uint64_t lsbfirst:1; + uint64_t int_ena:1; + uint64_t reserved_6_6:1; + uint64_t cshi:1; + uint64_t idleclks:2; + uint64_t tritx:1; + uint64_t cslate:1; + uint64_t reserved_12_13:2; + uint64_t csena2:1; + uint64_t csena3:1; + uint64_t clkdiv:13; + uint64_t reserved_29_63:35; +#endif + } cn66xx; + struct cvmx_mpi_cfg_cn61xx cnf71xx; +}; + +union cvmx_mpi_datx { + uint64_t u64; + struct cvmx_mpi_datx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_8_63:56; + uint64_t data:8; +#else + uint64_t data:8; + uint64_t reserved_8_63:56; +#endif + } s; + struct cvmx_mpi_datx_s cn30xx; + struct cvmx_mpi_datx_s cn31xx; + struct cvmx_mpi_datx_s cn50xx; + struct cvmx_mpi_datx_s cn61xx; + struct cvmx_mpi_datx_s cn66xx; + struct cvmx_mpi_datx_s cnf71xx; +}; + +union cvmx_mpi_sts { + uint64_t u64; + struct cvmx_mpi_sts_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_13_63:51; + uint64_t rxnum:5; + uint64_t reserved_1_7:7; + uint64_t busy:1; +#else + uint64_t busy:1; + uint64_t reserved_1_7:7; + uint64_t rxnum:5; + uint64_t reserved_13_63:51; +#endif + } s; + struct cvmx_mpi_sts_s cn30xx; + struct cvmx_mpi_sts_s cn31xx; + struct cvmx_mpi_sts_s cn50xx; + struct cvmx_mpi_sts_s cn61xx; + struct cvmx_mpi_sts_s cn66xx; + struct cvmx_mpi_sts_s cnf71xx; +}; + +union cvmx_mpi_tx { + uint64_t u64; + struct cvmx_mpi_tx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_22_63:42; + uint64_t csid:2; + uint64_t reserved_17_19:3; + uint64_t leavecs:1; + uint64_t reserved_13_15:3; + uint64_t txnum:5; + uint64_t reserved_5_7:3; + uint64_t totnum:5; +#else + uint64_t totnum:5; + uint64_t reserved_5_7:3; + uint64_t txnum:5; + uint64_t reserved_13_15:3; + uint64_t leavecs:1; + uint64_t reserved_17_19:3; + uint64_t csid:2; + uint64_t reserved_22_63:42; +#endif + } s; + struct cvmx_mpi_tx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_17_63:47; + uint64_t leavecs:1; + uint64_t reserved_13_15:3; + uint64_t txnum:5; + uint64_t reserved_5_7:3; + uint64_t totnum:5; +#else + uint64_t totnum:5; + uint64_t reserved_5_7:3; + uint64_t txnum:5; + uint64_t reserved_13_15:3; + uint64_t leavecs:1; + uint64_t reserved_17_63:47; +#endif + } cn30xx; + struct cvmx_mpi_tx_cn30xx cn31xx; + struct cvmx_mpi_tx_cn30xx cn50xx; + struct cvmx_mpi_tx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_21_63:43; + uint64_t csid:1; + uint64_t reserved_17_19:3; + uint64_t leavecs:1; + uint64_t reserved_13_15:3; + uint64_t txnum:5; + uint64_t reserved_5_7:3; + uint64_t totnum:5; +#else + uint64_t totnum:5; + uint64_t reserved_5_7:3; + uint64_t txnum:5; + uint64_t reserved_13_15:3; + uint64_t leavecs:1; + uint64_t reserved_17_19:3; + uint64_t csid:1; + uint64_t reserved_21_63:43; +#endif + } cn61xx; + struct cvmx_mpi_tx_s cn66xx; + struct cvmx_mpi_tx_cn61xx cnf71xx; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h index a3075f733ca..58114d41435 100644 --- a/arch/mips/include/asm/octeon/cvmx-npei-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2011 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -140,11 +140,19 @@ union cvmx_npei_bar1_indexx { uint32_t u32; struct cvmx_npei_bar1_indexx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_18_31:14; uint32_t addr_idx:14; uint32_t ca:1; uint32_t end_swp:2; uint32_t addr_v:1; +#else + uint32_t addr_v:1; + uint32_t end_swp:2; + uint32_t ca:1; + uint32_t addr_idx:14; + uint32_t reserved_18_31:14; +#endif } s; struct cvmx_npei_bar1_indexx_s cn52xx; struct cvmx_npei_bar1_indexx_s cn52xxp1; @@ -155,6 +163,7 @@ union cvmx_npei_bar1_indexx { union cvmx_npei_bist_status { uint64_t u64; struct cvmx_npei_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t pkt_rdf:1; uint64_t reserved_60_62:3; uint64_t pcr_gim:1; @@ -204,8 +213,60 @@ union cvmx_npei_bist_status { uint64_t reserved_2_2:1; uint64_t msi:1; uint64_t ncb_cmd:1; +#else + uint64_t ncb_cmd:1; + uint64_t msi:1; + uint64_t reserved_2_2:1; + uint64_t dif3:1; + uint64_t dif2:1; + uint64_t dif1:1; + uint64_t dif0:1; + uint64_t csm1:1; + uint64_t csm0:1; + uint64_t p2n1_p1:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_n:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_c0:1; + uint64_t p2n0_p1:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_n:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_c0:1; + uint64_t p2n0_co:1; + uint64_t p2n0_no:1; + uint64_t p2n0_po:1; + uint64_t p2n1_co:1; + uint64_t p2n1_no:1; + uint64_t p2n1_po:1; + uint64_t cpl_p1:1; + uint64_t cpl_p0:1; + uint64_t n2p1_o:1; + uint64_t n2p1_c:1; + uint64_t n2p0_o:1; + uint64_t n2p0_c:1; + uint64_t reserved_31_31:1; + uint64_t d3_pst:1; + uint64_t d2_pst:1; + uint64_t d1_pst:1; + uint64_t d0_pst:1; + uint64_t reserved_36_47:12; + uint64_t pkt_slm:1; + uint64_t pkt_ind:1; + uint64_t reserved_50_52:3; + uint64_t pcsr_sl:1; + uint64_t pcsr_id:1; + uint64_t pcsr_cnt:1; + uint64_t pcsr_im:1; + uint64_t pcsr_int:1; + uint64_t pkt_pif:1; + uint64_t pcr_gim:1; + uint64_t reserved_60_62:3; + uint64_t pkt_rdf:1; +#endif } s; struct cvmx_npei_bist_status_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t pkt_rdf:1; uint64_t reserved_60_62:3; uint64_t pcr_gim:1; @@ -264,8 +325,69 @@ union cvmx_npei_bist_status { uint64_t dif4:1; uint64_t msi:1; uint64_t ncb_cmd:1; +#else + uint64_t ncb_cmd:1; + uint64_t msi:1; + uint64_t dif4:1; + uint64_t dif3:1; + uint64_t dif2:1; + uint64_t dif1:1; + uint64_t dif0:1; + uint64_t csm1:1; + uint64_t csm0:1; + uint64_t p2n1_p1:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_n:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_c0:1; + uint64_t p2n0_p1:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_n:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_c0:1; + uint64_t p2n0_co:1; + uint64_t p2n0_no:1; + uint64_t p2n0_po:1; + uint64_t p2n1_co:1; + uint64_t p2n1_no:1; + uint64_t p2n1_po:1; + uint64_t cpl_p1:1; + uint64_t cpl_p0:1; + uint64_t n2p1_o:1; + uint64_t n2p1_c:1; + uint64_t n2p0_o:1; + uint64_t n2p0_c:1; + uint64_t d4_pst:1; + uint64_t d3_pst:1; + uint64_t d2_pst:1; + uint64_t d1_pst:1; + uint64_t d0_pst:1; + uint64_t reserved_36_39:4; + uint64_t ds_mem:1; + uint64_t d4_mem:1; + uint64_t d3_mem:1; + uint64_t d2_mem:1; + uint64_t d1_mem:1; + uint64_t d0_mem:1; + uint64_t pkt_pop1:1; + uint64_t pkt_pop0:1; + uint64_t reserved_48_49:2; + uint64_t pkt_pof:1; + uint64_t pkt_pfm:1; + uint64_t pkt_imem:1; + uint64_t pcsr_sl:1; + uint64_t pcsr_id:1; + uint64_t pcsr_cnt:1; + uint64_t pcsr_im:1; + uint64_t pcsr_int:1; + uint64_t pkt_pif:1; + uint64_t pcr_gim:1; + uint64_t reserved_60_62:3; + uint64_t pkt_rdf:1; +#endif } cn52xx; struct cvmx_npei_bist_status_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_46_63:18; uint64_t d0_mem0:1; uint64_t d1_mem1:1; @@ -313,9 +435,59 @@ union cvmx_npei_bist_status { uint64_t dr3_mem:1; uint64_t msi:1; uint64_t ncb_cmd:1; +#else + uint64_t ncb_cmd:1; + uint64_t msi:1; + uint64_t dr3_mem:1; + uint64_t dif3:1; + uint64_t dif2:1; + uint64_t dif1:1; + uint64_t dif0:1; + uint64_t csm1:1; + uint64_t csm0:1; + uint64_t p2n1_p1:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_n:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_c0:1; + uint64_t p2n0_p1:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_n:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_c0:1; + uint64_t p2n0_co:1; + uint64_t p2n0_no:1; + uint64_t p2n0_po:1; + uint64_t p2n1_co:1; + uint64_t p2n1_no:1; + uint64_t p2n1_po:1; + uint64_t cpl_p1:1; + uint64_t cpl_p0:1; + uint64_t n2p1_o:1; + uint64_t n2p1_c:1; + uint64_t n2p0_o:1; + uint64_t n2p0_c:1; + uint64_t dr2_mem:1; + uint64_t d3_pst:1; + uint64_t d2_pst:1; + uint64_t d1_pst:1; + uint64_t d0_pst:1; + uint64_t dr1_mem:1; + uint64_t d3_mem:1; + uint64_t d2_mem:1; + uint64_t d1_mem:1; + uint64_t d0_mem:1; + uint64_t dr0_mem:1; + uint64_t d3_mem3:1; + uint64_t d2_mem2:1; + uint64_t d1_mem1:1; + uint64_t d0_mem0:1; + uint64_t reserved_46_63:18; +#endif } cn52xxp1; struct cvmx_npei_bist_status_cn52xx cn56xx; struct cvmx_npei_bist_status_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t pcsr_int:1; uint64_t pcsr_im:1; @@ -375,12 +547,74 @@ union cvmx_npei_bist_status { uint64_t dif4:1; uint64_t msi:1; uint64_t ncb_cmd:1; +#else + uint64_t ncb_cmd:1; + uint64_t msi:1; + uint64_t dif4:1; + uint64_t dif3:1; + uint64_t dif2:1; + uint64_t dif1:1; + uint64_t dif0:1; + uint64_t csm1:1; + uint64_t csm0:1; + uint64_t p2n1_p1:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_n:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_c0:1; + uint64_t p2n0_p1:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_n:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_c0:1; + uint64_t p2n0_co:1; + uint64_t p2n0_no:1; + uint64_t p2n0_po:1; + uint64_t p2n1_co:1; + uint64_t p2n1_no:1; + uint64_t p2n1_po:1; + uint64_t cpl_p1:1; + uint64_t cpl_p0:1; + uint64_t n2p1_o:1; + uint64_t n2p1_c:1; + uint64_t n2p0_o:1; + uint64_t n2p0_c:1; + uint64_t d4_pst:1; + uint64_t d3_pst:1; + uint64_t d2_pst:1; + uint64_t d1_pst:1; + uint64_t d0_pst:1; + uint64_t d4_mem:1; + uint64_t d3_mem:1; + uint64_t d2_mem:1; + uint64_t d1_mem:1; + uint64_t d0_mem:1; + uint64_t pkt_s1:1; + uint64_t pkt_s0:1; + uint64_t pkt_i1:1; + uint64_t pkt_i0:1; + uint64_t pkt_out:1; + uint64_t pkt_oif:1; + uint64_t pkt_odf:1; + uint64_t pkt_slm:1; + uint64_t pkt_ind:1; + uint64_t pkt_cntm:1; + uint64_t pkt_imem:1; + uint64_t pkt_pout:1; + uint64_t pcsr_sl:1; + uint64_t pcsr_id:1; + uint64_t pcsr_cnt:1; + uint64_t pcsr_im:1; + uint64_t pcsr_int:1; + uint64_t reserved_58_63:6; +#endif } cn56xxp1; }; union cvmx_npei_bist_status2 { uint64_t u64; struct cvmx_npei_bist_status2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t prd_tag:1; uint64_t prd_st0:1; @@ -396,6 +630,23 @@ union cvmx_npei_bist_status2 { uint64_t pkt_gd:1; uint64_t pkt_gl:1; uint64_t pkt_blk:1; +#else + uint64_t pkt_blk:1; + uint64_t pkt_gl:1; + uint64_t pkt_gd:1; + uint64_t psc_p1:1; + uint64_t psc_p0:1; + uint64_t pkt_rd:1; + uint64_t nwe_wr1:1; + uint64_t nwe_wr0:1; + uint64_t nwe_st:1; + uint64_t nrd_st:1; + uint64_t prd_err:1; + uint64_t prd_st1:1; + uint64_t prd_st0:1; + uint64_t prd_tag:1; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_npei_bist_status2_s cn52xx; struct cvmx_npei_bist_status2_s cn56xx; @@ -404,6 +655,7 @@ union cvmx_npei_bist_status2 { union cvmx_npei_ctl_port0 { uint64_t u64; struct cvmx_npei_ctl_port0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t waitl_com:1; uint64_t intd:1; @@ -421,6 +673,25 @@ union cvmx_npei_ctl_port0 { uint64_t bar2_esx:2; uint64_t bar2_cax:1; uint64_t wait_com:1; +#else + uint64_t wait_com:1; + uint64_t bar2_cax:1; + uint64_t bar2_esx:2; + uint64_t bar2_enb:1; + uint64_t ptlp_ro:1; + uint64_t reserved_6_6:1; + uint64_t ctlp_ro:1; + uint64_t inta_map:2; + uint64_t intb_map:2; + uint64_t intc_map:2; + uint64_t intd_map:2; + uint64_t inta:1; + uint64_t intb:1; + uint64_t intc:1; + uint64_t intd:1; + uint64_t waitl_com:1; + uint64_t reserved_21_63:43; +#endif } s; struct cvmx_npei_ctl_port0_s cn52xx; struct cvmx_npei_ctl_port0_s cn52xxp1; @@ -431,6 +702,7 @@ union cvmx_npei_ctl_port0 { union cvmx_npei_ctl_port1 { uint64_t u64; struct cvmx_npei_ctl_port1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t waitl_com:1; uint64_t intd:1; @@ -448,6 +720,25 @@ union cvmx_npei_ctl_port1 { uint64_t bar2_esx:2; uint64_t bar2_cax:1; uint64_t wait_com:1; +#else + uint64_t wait_com:1; + uint64_t bar2_cax:1; + uint64_t bar2_esx:2; + uint64_t bar2_enb:1; + uint64_t ptlp_ro:1; + uint64_t reserved_6_6:1; + uint64_t ctlp_ro:1; + uint64_t inta_map:2; + uint64_t intb_map:2; + uint64_t intc_map:2; + uint64_t intd_map:2; + uint64_t inta:1; + uint64_t intb:1; + uint64_t intc:1; + uint64_t intd:1; + uint64_t waitl_com:1; + uint64_t reserved_21_63:43; +#endif } s; struct cvmx_npei_ctl_port1_s cn52xx; struct cvmx_npei_ctl_port1_s cn52xxp1; @@ -458,6 +749,7 @@ union cvmx_npei_ctl_port1 { union cvmx_npei_ctl_status { uint64_t u64; struct cvmx_npei_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t p1_ntags:6; uint64_t p0_ntags:6; @@ -468,9 +760,22 @@ union cvmx_npei_ctl_status { uint64_t pkt_bp:4; uint64_t host_mode:1; uint64_t chip_rev:8; +#else + uint64_t chip_rev:8; + uint64_t host_mode:1; + uint64_t pkt_bp:4; + uint64_t arb:1; + uint64_t lnk_rst:1; + uint64_t ring_en:1; + uint64_t cfg_rtry:16; + uint64_t p0_ntags:6; + uint64_t p1_ntags:6; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_npei_ctl_status_s cn52xx; struct cvmx_npei_ctl_status_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t p1_ntags:6; uint64_t p0_ntags:6; @@ -481,21 +786,43 @@ union cvmx_npei_ctl_status { uint64_t reserved_9_12:4; uint64_t host_mode:1; uint64_t chip_rev:8; +#else + uint64_t chip_rev:8; + uint64_t host_mode:1; + uint64_t reserved_9_12:4; + uint64_t arb:1; + uint64_t lnk_rst:1; + uint64_t reserved_15_15:1; + uint64_t cfg_rtry:16; + uint64_t p0_ntags:6; + uint64_t p1_ntags:6; + uint64_t reserved_44_63:20; +#endif } cn52xxp1; struct cvmx_npei_ctl_status_s cn56xx; struct cvmx_npei_ctl_status_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t lnk_rst:1; uint64_t arb:1; uint64_t pkt_bp:4; uint64_t host_mode:1; uint64_t chip_rev:8; +#else + uint64_t chip_rev:8; + uint64_t host_mode:1; + uint64_t pkt_bp:4; + uint64_t arb:1; + uint64_t lnk_rst:1; + uint64_t reserved_15_63:49; +#endif } cn56xxp1; }; union cvmx_npei_ctl_status2 { uint64_t u64; struct cvmx_npei_ctl_status2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mps:1; uint64_t mrrs:3; @@ -507,6 +834,19 @@ union cvmx_npei_ctl_status2 { uint64_t c1_b0_d:1; uint64_t c0_wi_d:1; uint64_t c0_b0_d:1; +#else + uint64_t c0_b0_d:1; + uint64_t c0_wi_d:1; + uint64_t c1_b0_d:1; + uint64_t c1_wi_d:1; + uint64_t c0_b1_s:3; + uint64_t c1_b1_s:3; + uint64_t c0_w_flt:1; + uint64_t c1_w_flt:1; + uint64_t mrrs:3; + uint64_t mps:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_npei_ctl_status2_s cn52xx; struct cvmx_npei_ctl_status2_s cn52xxp1; @@ -517,11 +857,19 @@ union cvmx_npei_ctl_status2 { union cvmx_npei_data_out_cnt { uint64_t u64; struct cvmx_npei_data_out_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t p1_ucnt:16; uint64_t p1_fcnt:6; uint64_t p0_ucnt:16; uint64_t p0_fcnt:6; +#else + uint64_t p0_fcnt:6; + uint64_t p0_ucnt:16; + uint64_t p1_fcnt:6; + uint64_t p1_ucnt:16; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_npei_data_out_cnt_s cn52xx; struct cvmx_npei_data_out_cnt_s cn52xxp1; @@ -532,6 +880,7 @@ union cvmx_npei_data_out_cnt { union cvmx_npei_dbg_data { uint64_t u64; struct cvmx_npei_dbg_data_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t qlm0_rev_lanes:1; uint64_t reserved_25_26:2; @@ -539,8 +888,18 @@ union cvmx_npei_dbg_data { uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; +#else + uint64_t data:17; + uint64_t dsel_ext:1; + uint64_t c_mul:5; + uint64_t qlm1_spd:2; + uint64_t reserved_25_26:2; + uint64_t qlm0_rev_lanes:1; + uint64_t reserved_28_63:36; +#endif } s; struct cvmx_npei_dbg_data_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t qlm0_link_width:1; uint64_t qlm0_rev_lanes:1; @@ -549,9 +908,20 @@ union cvmx_npei_dbg_data { uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; +#else + uint64_t data:17; + uint64_t dsel_ext:1; + uint64_t c_mul:5; + uint64_t qlm1_spd:2; + uint64_t qlm1_mode:2; + uint64_t qlm0_rev_lanes:1; + uint64_t qlm0_link_width:1; + uint64_t reserved_29_63:35; +#endif } cn52xx; struct cvmx_npei_dbg_data_cn52xx cn52xxp1; struct cvmx_npei_dbg_data_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t qlm2_rev_lanes:1; uint64_t qlm0_rev_lanes:1; @@ -560,6 +930,16 @@ union cvmx_npei_dbg_data { uint64_t c_mul:5; uint64_t dsel_ext:1; uint64_t data:17; +#else + uint64_t data:17; + uint64_t dsel_ext:1; + uint64_t c_mul:5; + uint64_t qlm1_spd:2; + uint64_t qlm3_spd:2; + uint64_t qlm0_rev_lanes:1; + uint64_t qlm2_rev_lanes:1; + uint64_t reserved_29_63:35; +#endif } cn56xx; struct cvmx_npei_dbg_data_cn56xx cn56xxp1; }; @@ -567,8 +947,13 @@ union cvmx_npei_dbg_data { union cvmx_npei_dbg_select { uint64_t u64; struct cvmx_npei_dbg_select_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dbg_sel:16; +#else + uint64_t dbg_sel:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_npei_dbg_select_s cn52xx; struct cvmx_npei_dbg_select_s cn52xxp1; @@ -579,9 +964,15 @@ union cvmx_npei_dbg_select { union cvmx_npei_dmax_counts { uint64_t u64; struct cvmx_npei_dmax_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t fcnt:7; uint64_t dbell:32; +#else + uint64_t dbell:32; + uint64_t fcnt:7; + uint64_t reserved_39_63:25; +#endif } s; struct cvmx_npei_dmax_counts_s cn52xx; struct cvmx_npei_dmax_counts_s cn52xxp1; @@ -592,8 +983,13 @@ union cvmx_npei_dmax_counts { union cvmx_npei_dmax_dbell { uint32_t u32; struct cvmx_npei_dmax_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_16_31:16; uint32_t dbell:16; +#else + uint32_t dbell:16; + uint32_t reserved_16_31:16; +#endif } s; struct cvmx_npei_dmax_dbell_s cn52xx; struct cvmx_npei_dmax_dbell_s cn52xxp1; @@ -604,16 +1000,29 @@ union cvmx_npei_dmax_dbell { union cvmx_npei_dmax_ibuff_saddr { uint64_t u64; struct cvmx_npei_dmax_ibuff_saddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t idle:1; uint64_t saddr:29; uint64_t reserved_0_6:7; +#else + uint64_t reserved_0_6:7; + uint64_t saddr:29; + uint64_t idle:1; + uint64_t reserved_37_63:27; +#endif } s; struct cvmx_npei_dmax_ibuff_saddr_s cn52xx; struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t saddr:29; uint64_t reserved_0_6:7; +#else + uint64_t reserved_0_6:7; + uint64_t saddr:29; + uint64_t reserved_36_63:28; +#endif } cn52xxp1; struct cvmx_npei_dmax_ibuff_saddr_s cn56xx; struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1; @@ -622,8 +1031,13 @@ union cvmx_npei_dmax_ibuff_saddr { union cvmx_npei_dmax_naddr { uint64_t u64; struct cvmx_npei_dmax_naddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t addr:36; +#else + uint64_t addr:36; + uint64_t reserved_36_63:28; +#endif } s; struct cvmx_npei_dmax_naddr_s cn52xx; struct cvmx_npei_dmax_naddr_s cn52xxp1; @@ -634,8 +1048,13 @@ union cvmx_npei_dmax_naddr { union cvmx_npei_dma0_int_level { uint64_t u64; struct cvmx_npei_dma0_int_level_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t time:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t time:32; +#endif } s; struct cvmx_npei_dma0_int_level_s cn52xx; struct cvmx_npei_dma0_int_level_s cn52xxp1; @@ -646,8 +1065,13 @@ union cvmx_npei_dma0_int_level { union cvmx_npei_dma1_int_level { uint64_t u64; struct cvmx_npei_dma1_int_level_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t time:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t time:32; +#endif } s; struct cvmx_npei_dma1_int_level_s cn52xx; struct cvmx_npei_dma1_int_level_s cn52xxp1; @@ -658,8 +1082,13 @@ union cvmx_npei_dma1_int_level { union cvmx_npei_dma_cnts { uint64_t u64; struct cvmx_npei_dma_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dma1:32; uint64_t dma0:32; +#else + uint64_t dma0:32; + uint64_t dma1:32; +#endif } s; struct cvmx_npei_dma_cnts_s cn52xx; struct cvmx_npei_dma_cnts_s cn52xxp1; @@ -670,6 +1099,7 @@ union cvmx_npei_dma_cnts { union cvmx_npei_dma_control { uint64_t u64; struct cvmx_npei_dma_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t p_32b_m:1; uint64_t dma4_enb:1; @@ -687,9 +1117,29 @@ union cvmx_npei_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t csize:14; +#else + uint64_t csize:14; + uint64_t o_mode:1; + uint64_t o_es:2; + uint64_t o_ns:1; + uint64_t o_ro:1; + uint64_t o_add1:1; + uint64_t fpa_que:3; + uint64_t dwb_ichk:9; + uint64_t dwb_denb:1; + uint64_t b0_lend:1; + uint64_t dma0_enb:1; + uint64_t dma1_enb:1; + uint64_t dma2_enb:1; + uint64_t dma3_enb:1; + uint64_t dma4_enb:1; + uint64_t p_32b_m:1; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_npei_dma_control_s cn52xx; struct cvmx_npei_dma_control_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t dma3_enb:1; uint64_t dma2_enb:1; @@ -705,9 +1155,27 @@ union cvmx_npei_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t csize:14; +#else + uint64_t csize:14; + uint64_t o_mode:1; + uint64_t o_es:2; + uint64_t o_ns:1; + uint64_t o_ro:1; + uint64_t o_add1:1; + uint64_t fpa_que:3; + uint64_t dwb_ichk:9; + uint64_t dwb_denb:1; + uint64_t b0_lend:1; + uint64_t dma0_enb:1; + uint64_t dma1_enb:1; + uint64_t dma2_enb:1; + uint64_t dma3_enb:1; + uint64_t reserved_38_63:26; +#endif } cn52xxp1; struct cvmx_npei_dma_control_s cn56xx; struct cvmx_npei_dma_control_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t dma4_enb:1; uint64_t dma3_enb:1; @@ -724,12 +1192,31 @@ union cvmx_npei_dma_control { uint64_t o_es:2; uint64_t o_mode:1; uint64_t csize:14; +#else + uint64_t csize:14; + uint64_t o_mode:1; + uint64_t o_es:2; + uint64_t o_ns:1; + uint64_t o_ro:1; + uint64_t o_add1:1; + uint64_t fpa_que:3; + uint64_t dwb_ichk:9; + uint64_t dwb_denb:1; + uint64_t b0_lend:1; + uint64_t dma0_enb:1; + uint64_t dma1_enb:1; + uint64_t dma2_enb:1; + uint64_t dma3_enb:1; + uint64_t dma4_enb:1; + uint64_t reserved_39_63:25; +#endif } cn56xxp1; }; union cvmx_npei_dma_pcie_req_num { uint64_t u64; struct cvmx_npei_dma_pcie_req_num_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dma_arb:1; uint64_t reserved_53_62:10; uint64_t pkt_cnt:5; @@ -745,6 +1232,23 @@ union cvmx_npei_dma_pcie_req_num { uint64_t dma0_cnt:5; uint64_t reserved_5_7:3; uint64_t dma_cnt:5; +#else + uint64_t dma_cnt:5; + uint64_t reserved_5_7:3; + uint64_t dma0_cnt:5; + uint64_t reserved_13_15:3; + uint64_t dma1_cnt:5; + uint64_t reserved_21_23:3; + uint64_t dma2_cnt:5; + uint64_t reserved_29_31:3; + uint64_t dma3_cnt:5; + uint64_t reserved_37_39:3; + uint64_t dma4_cnt:5; + uint64_t reserved_45_47:3; + uint64_t pkt_cnt:5; + uint64_t reserved_53_62:10; + uint64_t dma_arb:1; +#endif } s; struct cvmx_npei_dma_pcie_req_num_s cn52xx; struct cvmx_npei_dma_pcie_req_num_s cn56xx; @@ -753,12 +1257,21 @@ union cvmx_npei_dma_pcie_req_num { union cvmx_npei_dma_state1 { uint64_t u64; struct cvmx_npei_dma_state1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t d4_dwe:8; uint64_t d3_dwe:8; uint64_t d2_dwe:8; uint64_t d1_dwe:8; uint64_t d0_dwe:8; +#else + uint64_t d0_dwe:8; + uint64_t d1_dwe:8; + uint64_t d2_dwe:8; + uint64_t d3_dwe:8; + uint64_t d4_dwe:8; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_npei_dma_state1_s cn52xx; }; @@ -766,6 +1279,7 @@ union cvmx_npei_dma_state1 { union cvmx_npei_dma_state1_p1 { uint64_t u64; struct cvmx_npei_dma_state1_p1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t d0_difst:7; uint64_t d1_difst:7; @@ -777,8 +1291,22 @@ union cvmx_npei_dma_state1_p1 { uint64_t d2_reqst:5; uint64_t d3_reqst:5; uint64_t d4_reqst:5; +#else + uint64_t d4_reqst:5; + uint64_t d3_reqst:5; + uint64_t d2_reqst:5; + uint64_t d1_reqst:5; + uint64_t d0_reqst:5; + uint64_t d4_difst:7; + uint64_t d3_difst:7; + uint64_t d2_difst:7; + uint64_t d1_difst:7; + uint64_t d0_difst:7; + uint64_t reserved_60_63:4; +#endif } s; struct cvmx_npei_dma_state1_p1_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t d0_difst:7; uint64_t d1_difst:7; @@ -790,6 +1318,19 @@ union cvmx_npei_dma_state1_p1 { uint64_t d2_reqst:5; uint64_t d3_reqst:5; uint64_t reserved_0_4:5; +#else + uint64_t reserved_0_4:5; + uint64_t d3_reqst:5; + uint64_t d2_reqst:5; + uint64_t d1_reqst:5; + uint64_t d0_reqst:5; + uint64_t reserved_25_31:7; + uint64_t d3_difst:7; + uint64_t d2_difst:7; + uint64_t d1_difst:7; + uint64_t d0_difst:7; + uint64_t reserved_60_63:4; +#endif } cn52xxp1; struct cvmx_npei_dma_state1_p1_s cn56xxp1; }; @@ -797,12 +1338,21 @@ union cvmx_npei_dma_state1_p1 { union cvmx_npei_dma_state2 { uint64_t u64; struct cvmx_npei_dma_state2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t ndwe:4; uint64_t reserved_21_23:3; uint64_t ndre:5; uint64_t reserved_10_15:6; uint64_t prd:10; +#else + uint64_t prd:10; + uint64_t reserved_10_15:6; + uint64_t ndre:5; + uint64_t reserved_21_23:3; + uint64_t ndwe:4; + uint64_t reserved_28_63:36; +#endif } s; struct cvmx_npei_dma_state2_s cn52xx; }; @@ -810,20 +1360,38 @@ union cvmx_npei_dma_state2 { union cvmx_npei_dma_state2_p1 { uint64_t u64; struct cvmx_npei_dma_state2_p1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t d0_dffst:9; uint64_t d1_dffst:9; uint64_t d2_dffst:9; uint64_t d3_dffst:9; uint64_t d4_dffst:9; +#else + uint64_t d4_dffst:9; + uint64_t d3_dffst:9; + uint64_t d2_dffst:9; + uint64_t d1_dffst:9; + uint64_t d0_dffst:9; + uint64_t reserved_45_63:19; +#endif } s; struct cvmx_npei_dma_state2_p1_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t d0_dffst:9; uint64_t d1_dffst:9; uint64_t d2_dffst:9; uint64_t d3_dffst:9; uint64_t reserved_0_8:9; +#else + uint64_t reserved_0_8:9; + uint64_t d3_dffst:9; + uint64_t d2_dffst:9; + uint64_t d1_dffst:9; + uint64_t d0_dffst:9; + uint64_t reserved_45_63:19; +#endif } cn52xxp1; struct cvmx_npei_dma_state2_p1_s cn56xxp1; }; @@ -831,11 +1399,19 @@ union cvmx_npei_dma_state2_p1 { union cvmx_npei_dma_state3_p1 { uint64_t u64; struct cvmx_npei_dma_state3_p1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t d0_drest:15; uint64_t d1_drest:15; uint64_t d2_drest:15; uint64_t d3_drest:15; +#else + uint64_t d3_drest:15; + uint64_t d2_drest:15; + uint64_t d1_drest:15; + uint64_t d0_drest:15; + uint64_t reserved_60_63:4; +#endif } s; struct cvmx_npei_dma_state3_p1_s cn52xxp1; struct cvmx_npei_dma_state3_p1_s cn56xxp1; @@ -844,11 +1420,19 @@ union cvmx_npei_dma_state3_p1 { union cvmx_npei_dma_state4_p1 { uint64_t u64; struct cvmx_npei_dma_state4_p1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_52_63:12; uint64_t d0_dwest:13; uint64_t d1_dwest:13; uint64_t d2_dwest:13; uint64_t d3_dwest:13; +#else + uint64_t d3_dwest:13; + uint64_t d2_dwest:13; + uint64_t d1_dwest:13; + uint64_t d0_dwest:13; + uint64_t reserved_52_63:12; +#endif } s; struct cvmx_npei_dma_state4_p1_s cn52xxp1; struct cvmx_npei_dma_state4_p1_s cn56xxp1; @@ -857,9 +1441,15 @@ union cvmx_npei_dma_state4_p1 { union cvmx_npei_dma_state5_p1 { uint64_t u64; struct cvmx_npei_dma_state5_p1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t d4_drest:15; uint64_t d4_dwest:13; +#else + uint64_t d4_dwest:13; + uint64_t d4_drest:15; + uint64_t reserved_28_63:36; +#endif } s; struct cvmx_npei_dma_state5_p1_s cn56xxp1; }; @@ -867,6 +1457,7 @@ union cvmx_npei_dma_state5_p1 { union cvmx_npei_int_a_enb { uint64_t u64; struct cvmx_npei_int_a_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pout_err:1; uint64_t pin_bp:1; @@ -878,12 +1469,31 @@ union cvmx_npei_int_a_enb { uint64_t pins_err:1; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; +#else + uint64_t dma0_cpl:1; + uint64_t dma1_cpl:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t p0_rdlk:1; + uint64_t p1_rdlk:1; + uint64_t pin_bp:1; + uint64_t pout_err:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_npei_int_a_enb_s cn52xx; struct cvmx_npei_int_a_enb_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; +#else + uint64_t dma0_cpl:1; + uint64_t dma1_cpl:1; + uint64_t reserved_2_63:62; +#endif } cn52xxp1; struct cvmx_npei_int_a_enb_s cn56xx; }; @@ -891,6 +1501,7 @@ union cvmx_npei_int_a_enb { union cvmx_npei_int_a_enb2 { uint64_t u64; struct cvmx_npei_int_a_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pout_err:1; uint64_t pin_bp:1; @@ -902,12 +1513,31 @@ union cvmx_npei_int_a_enb2 { uint64_t pins_err:1; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; +#else + uint64_t dma0_cpl:1; + uint64_t dma1_cpl:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t p0_rdlk:1; + uint64_t p1_rdlk:1; + uint64_t pin_bp:1; + uint64_t pout_err:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_npei_int_a_enb2_s cn52xx; struct cvmx_npei_int_a_enb2_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; +#else + uint64_t dma0_cpl:1; + uint64_t dma1_cpl:1; + uint64_t reserved_2_63:62; +#endif } cn52xxp1; struct cvmx_npei_int_a_enb2_s cn56xx; }; @@ -915,6 +1545,7 @@ union cvmx_npei_int_a_enb2 { union cvmx_npei_int_a_sum { uint64_t u64; struct cvmx_npei_int_a_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pout_err:1; uint64_t pin_bp:1; @@ -926,12 +1557,31 @@ union cvmx_npei_int_a_sum { uint64_t pins_err:1; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; +#else + uint64_t dma0_cpl:1; + uint64_t dma1_cpl:1; + uint64_t pins_err:1; + uint64_t pop_err:1; + uint64_t pdi_err:1; + uint64_t pgl_err:1; + uint64_t p0_rdlk:1; + uint64_t p1_rdlk:1; + uint64_t pin_bp:1; + uint64_t pout_err:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_npei_int_a_sum_s cn52xx; struct cvmx_npei_int_a_sum_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t dma1_cpl:1; uint64_t dma0_cpl:1; +#else + uint64_t dma0_cpl:1; + uint64_t dma1_cpl:1; + uint64_t reserved_2_63:62; +#endif } cn52xxp1; struct cvmx_npei_int_a_sum_s cn56xx; }; @@ -939,6 +1589,7 @@ union cvmx_npei_int_a_sum { union cvmx_npei_int_enb { uint64_t u64; struct cvmx_npei_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_62_62:1; uint64_t int_a:1; @@ -1003,9 +1654,76 @@ union cvmx_npei_int_enb { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t dma4dbo:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t c0_aeri:1; + uint64_t crs0_er:1; + uint64_t c0_se:1; + uint64_t crs0_dr:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t crs1_er:1; + uint64_t c1_se:1; + uint64_t crs1_dr:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t int_a:1; + uint64_t reserved_62_62:1; + uint64_t mio_inta:1; +#endif } s; struct cvmx_npei_int_enb_s cn52xx; struct cvmx_npei_int_enb_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_62_62:1; uint64_t int_a:1; @@ -1070,9 +1788,76 @@ union cvmx_npei_int_enb { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t reserved_8_8:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t c0_aeri:1; + uint64_t crs0_er:1; + uint64_t c0_se:1; + uint64_t crs0_dr:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t crs1_er:1; + uint64_t c1_se:1; + uint64_t crs1_dr:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t int_a:1; + uint64_t reserved_62_62:1; + uint64_t mio_inta:1; +#endif } cn52xxp1; struct cvmx_npei_int_enb_s cn56xx; struct cvmx_npei_int_enb_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_61_62:2; uint64_t c1_ldwn:1; @@ -1136,12 +1921,78 @@ union cvmx_npei_int_enb { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t dma4dbo:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t c0_aeri:1; + uint64_t reserved_20_20:1; + uint64_t c0_se:1; + uint64_t reserved_22_22:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t reserved_27_27:1; + uint64_t c1_se:1; + uint64_t reserved_29_29:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t reserved_61_62:2; + uint64_t mio_inta:1; +#endif } cn56xxp1; }; union cvmx_npei_int_enb2 { uint64_t u64; struct cvmx_npei_int_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t int_a:1; uint64_t c1_ldwn:1; @@ -1205,9 +2056,75 @@ union cvmx_npei_int_enb2 { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t dma4dbo:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t c0_aeri:1; + uint64_t crs0_er:1; + uint64_t c0_se:1; + uint64_t crs0_dr:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t crs1_er:1; + uint64_t c1_se:1; + uint64_t crs1_dr:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t int_a:1; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_npei_int_enb2_s cn52xx; struct cvmx_npei_int_enb2_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t int_a:1; uint64_t c1_ldwn:1; @@ -1271,9 +2188,75 @@ union cvmx_npei_int_enb2 { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t reserved_8_8:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t c0_aeri:1; + uint64_t crs0_er:1; + uint64_t c0_se:1; + uint64_t crs0_dr:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t crs1_er:1; + uint64_t c1_se:1; + uint64_t crs1_dr:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t int_a:1; + uint64_t reserved_62_63:2; +#endif } cn52xxp1; struct cvmx_npei_int_enb2_s cn56xx; struct cvmx_npei_int_enb2_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t c1_ldwn:1; uint64_t c0_ldwn:1; @@ -1336,15 +2319,85 @@ union cvmx_npei_int_enb2 { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t dma4dbo:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t c0_aeri:1; + uint64_t reserved_20_20:1; + uint64_t c0_se:1; + uint64_t reserved_22_22:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t reserved_27_27:1; + uint64_t c1_se:1; + uint64_t reserved_29_29:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t reserved_61_63:3; +#endif } cn56xxp1; }; union cvmx_npei_int_info { uint64_t u64; struct cvmx_npei_int_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t pidbof:6; uint64_t psldbof:6; +#else + uint64_t psldbof:6; + uint64_t pidbof:6; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_npei_int_info_s cn52xx; struct cvmx_npei_int_info_s cn56xx; @@ -1354,6 +2407,7 @@ union cvmx_npei_int_info { union cvmx_npei_int_sum { uint64_t u64; struct cvmx_npei_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_62_62:1; uint64_t int_a:1; @@ -1418,9 +2472,76 @@ union cvmx_npei_int_sum { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t dma4dbo:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t psldbof:1; + uint64_t pidbof:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t c0_aeri:1; + uint64_t crs0_er:1; + uint64_t c0_se:1; + uint64_t crs0_dr:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t crs1_er:1; + uint64_t c1_se:1; + uint64_t crs1_dr:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t int_a:1; + uint64_t reserved_62_62:1; + uint64_t mio_inta:1; +#endif } s; struct cvmx_npei_int_sum_s cn52xx; struct cvmx_npei_int_sum_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_62_62:1; uint64_t int_a:1; @@ -1482,9 +2603,73 @@ union cvmx_npei_int_sum { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t reserved_8_8:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t reserved_15_18:4; + uint64_t c0_aeri:1; + uint64_t crs0_er:1; + uint64_t c0_se:1; + uint64_t crs0_dr:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t crs1_er:1; + uint64_t c1_se:1; + uint64_t crs1_dr:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t int_a:1; + uint64_t reserved_62_62:1; + uint64_t mio_inta:1; +#endif } cn52xxp1; struct cvmx_npei_int_sum_s cn56xx; struct cvmx_npei_int_sum_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_61_62:2; uint64_t c1_ldwn:1; @@ -1545,12 +2730,75 @@ union cvmx_npei_int_sum { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t dma4dbo:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t reserved_15_18:4; + uint64_t c0_aeri:1; + uint64_t reserved_20_20:1; + uint64_t c0_se:1; + uint64_t reserved_22_22:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t reserved_27_27:1; + uint64_t c1_se:1; + uint64_t reserved_29_29:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t reserved_61_62:2; + uint64_t mio_inta:1; +#endif } cn56xxp1; }; union cvmx_npei_int_sum2 { uint64_t u64; struct cvmx_npei_int_sum2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t mio_inta:1; uint64_t reserved_62_62:1; uint64_t int_a:1; @@ -1612,6 +2860,69 @@ union cvmx_npei_int_sum2 { uint64_t bar0_to:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t dma0dbo:1; + uint64_t dma1dbo:1; + uint64_t dma2dbo:1; + uint64_t dma3dbo:1; + uint64_t reserved_8_8:1; + uint64_t dma0fi:1; + uint64_t dma1fi:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t reserved_15_18:4; + uint64_t c0_aeri:1; + uint64_t crs0_er:1; + uint64_t c0_se:1; + uint64_t crs0_dr:1; + uint64_t c0_wake:1; + uint64_t c0_pmei:1; + uint64_t c0_hpint:1; + uint64_t c1_aeri:1; + uint64_t crs1_er:1; + uint64_t c1_se:1; + uint64_t crs1_dr:1; + uint64_t c1_wake:1; + uint64_t c1_pmei:1; + uint64_t c1_hpint:1; + uint64_t c0_up_b0:1; + uint64_t c0_up_b1:1; + uint64_t c0_up_b2:1; + uint64_t c0_up_wi:1; + uint64_t c0_up_bx:1; + uint64_t c0_un_b0:1; + uint64_t c0_un_b1:1; + uint64_t c0_un_b2:1; + uint64_t c0_un_wi:1; + uint64_t c0_un_bx:1; + uint64_t c1_up_b0:1; + uint64_t c1_up_b1:1; + uint64_t c1_up_b2:1; + uint64_t c1_up_wi:1; + uint64_t c1_up_bx:1; + uint64_t c1_un_b0:1; + uint64_t c1_un_b1:1; + uint64_t c1_un_b2:1; + uint64_t c1_un_wi:1; + uint64_t c1_un_bx:1; + uint64_t c0_un_wf:1; + uint64_t c1_un_wf:1; + uint64_t c0_up_wf:1; + uint64_t c1_up_wf:1; + uint64_t c0_exc:1; + uint64_t c1_exc:1; + uint64_t c0_ldwn:1; + uint64_t c1_ldwn:1; + uint64_t int_a:1; + uint64_t reserved_62_62:1; + uint64_t mio_inta:1; +#endif } s; struct cvmx_npei_int_sum2_s cn52xx; struct cvmx_npei_int_sum2_s cn52xxp1; @@ -1621,7 +2932,11 @@ union cvmx_npei_int_sum2 { union cvmx_npei_last_win_rdata0 { uint64_t u64; struct cvmx_npei_last_win_rdata0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; +#else + uint64_t data:64; +#endif } s; struct cvmx_npei_last_win_rdata0_s cn52xx; struct cvmx_npei_last_win_rdata0_s cn52xxp1; @@ -1632,7 +2947,11 @@ union cvmx_npei_last_win_rdata0 { union cvmx_npei_last_win_rdata1 { uint64_t u64; struct cvmx_npei_last_win_rdata1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_npei_last_win_rdata1_s cn52xx; struct cvmx_npei_last_win_rdata1_s cn52xxp1; @@ -1643,9 +2962,15 @@ union cvmx_npei_last_win_rdata1 { union cvmx_npei_mem_access_ctl { uint64_t u64; struct cvmx_npei_mem_access_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t max_word:4; uint64_t timer:10; +#else + uint64_t timer:10; + uint64_t max_word:4; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_npei_mem_access_ctl_s cn52xx; struct cvmx_npei_mem_access_ctl_s cn52xxp1; @@ -1656,6 +2981,7 @@ union cvmx_npei_mem_access_ctl { union cvmx_npei_mem_access_subidx { uint64_t u64; struct cvmx_npei_mem_access_subidx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t zero:1; uint64_t port:2; @@ -1667,6 +2993,19 @@ union cvmx_npei_mem_access_subidx { uint64_t ror:1; uint64_t row:1; uint64_t ba:30; +#else + uint64_t ba:30; + uint64_t row:1; + uint64_t ror:1; + uint64_t nsw:1; + uint64_t nsr:1; + uint64_t esw:2; + uint64_t esr:2; + uint64_t nmerge:1; + uint64_t port:2; + uint64_t zero:1; + uint64_t reserved_42_63:22; +#endif } s; struct cvmx_npei_mem_access_subidx_s cn52xx; struct cvmx_npei_mem_access_subidx_s cn52xxp1; @@ -1677,7 +3016,11 @@ union cvmx_npei_mem_access_subidx { union cvmx_npei_msi_enb0 { uint64_t u64; struct cvmx_npei_msi_enb0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t enb:64; +#else + uint64_t enb:64; +#endif } s; struct cvmx_npei_msi_enb0_s cn52xx; struct cvmx_npei_msi_enb0_s cn52xxp1; @@ -1688,7 +3031,11 @@ union cvmx_npei_msi_enb0 { union cvmx_npei_msi_enb1 { uint64_t u64; struct cvmx_npei_msi_enb1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t enb:64; +#else uint64_t enb:64; +#endif } s; struct cvmx_npei_msi_enb1_s cn52xx; struct cvmx_npei_msi_enb1_s cn52xxp1; @@ -1699,7 +3046,11 @@ union cvmx_npei_msi_enb1 { union cvmx_npei_msi_enb2 { uint64_t u64; struct cvmx_npei_msi_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t enb:64; +#else uint64_t enb:64; +#endif } s; struct cvmx_npei_msi_enb2_s cn52xx; struct cvmx_npei_msi_enb2_s cn52xxp1; @@ -1710,7 +3061,11 @@ union cvmx_npei_msi_enb2 { union cvmx_npei_msi_enb3 { uint64_t u64; struct cvmx_npei_msi_enb3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t enb:64; +#else + uint64_t enb:64; +#endif } s; struct cvmx_npei_msi_enb3_s cn52xx; struct cvmx_npei_msi_enb3_s cn52xxp1; @@ -1721,7 +3076,11 @@ union cvmx_npei_msi_enb3 { union cvmx_npei_msi_rcv0 { uint64_t u64; struct cvmx_npei_msi_rcv0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t intr:64; +#else + uint64_t intr:64; +#endif } s; struct cvmx_npei_msi_rcv0_s cn52xx; struct cvmx_npei_msi_rcv0_s cn52xxp1; @@ -1732,7 +3091,11 @@ union cvmx_npei_msi_rcv0 { union cvmx_npei_msi_rcv1 { uint64_t u64; struct cvmx_npei_msi_rcv1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t intr:64; +#else uint64_t intr:64; +#endif } s; struct cvmx_npei_msi_rcv1_s cn52xx; struct cvmx_npei_msi_rcv1_s cn52xxp1; @@ -1743,7 +3106,11 @@ union cvmx_npei_msi_rcv1 { union cvmx_npei_msi_rcv2 { uint64_t u64; struct cvmx_npei_msi_rcv2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t intr:64; +#else uint64_t intr:64; +#endif } s; struct cvmx_npei_msi_rcv2_s cn52xx; struct cvmx_npei_msi_rcv2_s cn52xxp1; @@ -1754,7 +3121,11 @@ union cvmx_npei_msi_rcv2 { union cvmx_npei_msi_rcv3 { uint64_t u64; struct cvmx_npei_msi_rcv3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t intr:64; +#else + uint64_t intr:64; +#endif } s; struct cvmx_npei_msi_rcv3_s cn52xx; struct cvmx_npei_msi_rcv3_s cn52xxp1; @@ -1765,9 +3136,15 @@ union cvmx_npei_msi_rcv3 { union cvmx_npei_msi_rd_map { uint64_t u64; struct cvmx_npei_msi_rd_map_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t rd_int:8; uint64_t msi_int:8; +#else + uint64_t msi_int:8; + uint64_t rd_int:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_npei_msi_rd_map_s cn52xx; struct cvmx_npei_msi_rd_map_s cn52xxp1; @@ -1778,7 +3155,11 @@ union cvmx_npei_msi_rd_map { union cvmx_npei_msi_w1c_enb0 { uint64_t u64; struct cvmx_npei_msi_w1c_enb0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t clr:64; +#else + uint64_t clr:64; +#endif } s; struct cvmx_npei_msi_w1c_enb0_s cn52xx; struct cvmx_npei_msi_w1c_enb0_s cn56xx; @@ -1787,7 +3168,11 @@ union cvmx_npei_msi_w1c_enb0 { union cvmx_npei_msi_w1c_enb1 { uint64_t u64; struct cvmx_npei_msi_w1c_enb1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t clr:64; +#else uint64_t clr:64; +#endif } s; struct cvmx_npei_msi_w1c_enb1_s cn52xx; struct cvmx_npei_msi_w1c_enb1_s cn56xx; @@ -1796,7 +3181,11 @@ union cvmx_npei_msi_w1c_enb1 { union cvmx_npei_msi_w1c_enb2 { uint64_t u64; struct cvmx_npei_msi_w1c_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t clr:64; +#else uint64_t clr:64; +#endif } s; struct cvmx_npei_msi_w1c_enb2_s cn52xx; struct cvmx_npei_msi_w1c_enb2_s cn56xx; @@ -1805,7 +3194,11 @@ union cvmx_npei_msi_w1c_enb2 { union cvmx_npei_msi_w1c_enb3 { uint64_t u64; struct cvmx_npei_msi_w1c_enb3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t clr:64; +#else + uint64_t clr:64; +#endif } s; struct cvmx_npei_msi_w1c_enb3_s cn52xx; struct cvmx_npei_msi_w1c_enb3_s cn56xx; @@ -1814,7 +3207,11 @@ union cvmx_npei_msi_w1c_enb3 { union cvmx_npei_msi_w1s_enb0 { uint64_t u64; struct cvmx_npei_msi_w1s_enb0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t set:64; +#else uint64_t set:64; +#endif } s; struct cvmx_npei_msi_w1s_enb0_s cn52xx; struct cvmx_npei_msi_w1s_enb0_s cn56xx; @@ -1823,7 +3220,11 @@ union cvmx_npei_msi_w1s_enb0 { union cvmx_npei_msi_w1s_enb1 { uint64_t u64; struct cvmx_npei_msi_w1s_enb1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t set:64; +#else uint64_t set:64; +#endif } s; struct cvmx_npei_msi_w1s_enb1_s cn52xx; struct cvmx_npei_msi_w1s_enb1_s cn56xx; @@ -1832,7 +3233,11 @@ union cvmx_npei_msi_w1s_enb1 { union cvmx_npei_msi_w1s_enb2 { uint64_t u64; struct cvmx_npei_msi_w1s_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t set:64; +#else uint64_t set:64; +#endif } s; struct cvmx_npei_msi_w1s_enb2_s cn52xx; struct cvmx_npei_msi_w1s_enb2_s cn56xx; @@ -1841,7 +3246,11 @@ union cvmx_npei_msi_w1s_enb2 { union cvmx_npei_msi_w1s_enb3 { uint64_t u64; struct cvmx_npei_msi_w1s_enb3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t set:64; +#else + uint64_t set:64; +#endif } s; struct cvmx_npei_msi_w1s_enb3_s cn52xx; struct cvmx_npei_msi_w1s_enb3_s cn56xx; @@ -1850,9 +3259,15 @@ union cvmx_npei_msi_w1s_enb3 { union cvmx_npei_msi_wr_map { uint64_t u64; struct cvmx_npei_msi_wr_map_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ciu_int:8; uint64_t msi_int:8; +#else + uint64_t msi_int:8; + uint64_t ciu_int:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_npei_msi_wr_map_s cn52xx; struct cvmx_npei_msi_wr_map_s cn52xxp1; @@ -1863,6 +3278,7 @@ union cvmx_npei_msi_wr_map { union cvmx_npei_pcie_credit_cnt { uint64_t u64; struct cvmx_npei_pcie_credit_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t p1_ccnt:8; uint64_t p1_ncnt:8; @@ -1870,6 +3286,15 @@ union cvmx_npei_pcie_credit_cnt { uint64_t p0_ccnt:8; uint64_t p0_ncnt:8; uint64_t p0_pcnt:8; +#else + uint64_t p0_pcnt:8; + uint64_t p0_ncnt:8; + uint64_t p0_ccnt:8; + uint64_t p1_pcnt:8; + uint64_t p1_ncnt:8; + uint64_t p1_ccnt:8; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_npei_pcie_credit_cnt_s cn52xx; struct cvmx_npei_pcie_credit_cnt_s cn56xx; @@ -1878,8 +3303,13 @@ union cvmx_npei_pcie_credit_cnt { union cvmx_npei_pcie_msi_rcv { uint64_t u64; struct cvmx_npei_pcie_msi_rcv_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t intr:8; +#else + uint64_t intr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_npei_pcie_msi_rcv_s cn52xx; struct cvmx_npei_pcie_msi_rcv_s cn52xxp1; @@ -1890,9 +3320,15 @@ union cvmx_npei_pcie_msi_rcv { union cvmx_npei_pcie_msi_rcv_b1 { uint64_t u64; struct cvmx_npei_pcie_msi_rcv_b1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t intr:8; uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t intr:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx; struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1; @@ -1903,9 +3339,15 @@ union cvmx_npei_pcie_msi_rcv_b1 { union cvmx_npei_pcie_msi_rcv_b2 { uint64_t u64; struct cvmx_npei_pcie_msi_rcv_b2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t intr:8; uint64_t reserved_0_15:16; +#else + uint64_t reserved_0_15:16; + uint64_t intr:8; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx; struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1; @@ -1916,9 +3358,15 @@ union cvmx_npei_pcie_msi_rcv_b2 { union cvmx_npei_pcie_msi_rcv_b3 { uint64_t u64; struct cvmx_npei_pcie_msi_rcv_b3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t intr:8; uint64_t reserved_0_23:24; +#else + uint64_t reserved_0_23:24; + uint64_t intr:8; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx; struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1; @@ -1929,9 +3377,15 @@ union cvmx_npei_pcie_msi_rcv_b3 { union cvmx_npei_pktx_cnts { uint64_t u64; struct cvmx_npei_pktx_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t timer:22; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t timer:22; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_npei_pktx_cnts_s cn52xx; struct cvmx_npei_pktx_cnts_s cn56xx; @@ -1940,8 +3394,13 @@ union cvmx_npei_pktx_cnts { union cvmx_npei_pktx_in_bp { uint64_t u64; struct cvmx_npei_pktx_in_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wmark:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t wmark:32; +#endif } s; struct cvmx_npei_pktx_in_bp_s cn52xx; struct cvmx_npei_pktx_in_bp_s cn56xx; @@ -1950,8 +3409,13 @@ union cvmx_npei_pktx_in_bp { union cvmx_npei_pktx_instr_baddr { uint64_t u64; struct cvmx_npei_pktx_instr_baddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:61; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t addr:61; +#endif } s; struct cvmx_npei_pktx_instr_baddr_s cn52xx; struct cvmx_npei_pktx_instr_baddr_s cn56xx; @@ -1960,8 +3424,13 @@ union cvmx_npei_pktx_instr_baddr { union cvmx_npei_pktx_instr_baoff_dbell { uint64_t u64; struct cvmx_npei_pktx_instr_baoff_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t aoff:32; uint64_t dbell:32; +#else + uint64_t dbell:32; + uint64_t aoff:32; +#endif } s; struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx; struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx; @@ -1970,11 +3439,19 @@ union cvmx_npei_pktx_instr_baoff_dbell { union cvmx_npei_pktx_instr_fifo_rsize { uint64_t u64; struct cvmx_npei_pktx_instr_fifo_rsize_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t max:9; uint64_t rrp:9; uint64_t wrp:9; uint64_t fcnt:5; uint64_t rsize:32; +#else + uint64_t rsize:32; + uint64_t fcnt:5; + uint64_t wrp:9; + uint64_t rrp:9; + uint64_t max:9; +#endif } s; struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx; struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx; @@ -1983,6 +3460,7 @@ union cvmx_npei_pktx_instr_fifo_rsize { union cvmx_npei_pktx_instr_header { uint64_t u64; struct cvmx_npei_pktx_instr_header_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t reserved_38_42:5; @@ -1996,6 +3474,21 @@ union cvmx_npei_pktx_instr_header { uint64_t reserved_13_13:1; uint64_t skp_len:7; uint64_t reserved_0_5:6; +#else + uint64_t reserved_0_5:6; + uint64_t skp_len:7; + uint64_t reserved_13_13:1; + uint64_t par_mode:2; + uint64_t reserved_16_20:5; + uint64_t use_ihdr:1; + uint64_t reserved_22_27:6; + uint64_t rskp_len:7; + uint64_t reserved_35_35:1; + uint64_t rparmode:2; + uint64_t reserved_38_42:5; + uint64_t pbp:1; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_npei_pktx_instr_header_s cn52xx; struct cvmx_npei_pktx_instr_header_s cn56xx; @@ -2004,8 +3497,13 @@ union cvmx_npei_pktx_instr_header { union cvmx_npei_pktx_slist_baddr { uint64_t u64; struct cvmx_npei_pktx_slist_baddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:60; uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t addr:60; +#endif } s; struct cvmx_npei_pktx_slist_baddr_s cn52xx; struct cvmx_npei_pktx_slist_baddr_s cn56xx; @@ -2014,8 +3512,13 @@ union cvmx_npei_pktx_slist_baddr { union cvmx_npei_pktx_slist_baoff_dbell { uint64_t u64; struct cvmx_npei_pktx_slist_baoff_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t aoff:32; uint64_t dbell:32; +#else + uint64_t dbell:32; + uint64_t aoff:32; +#endif } s; struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx; struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx; @@ -2024,8 +3527,13 @@ union cvmx_npei_pktx_slist_baoff_dbell { union cvmx_npei_pktx_slist_fifo_rsize { uint64_t u64; struct cvmx_npei_pktx_slist_fifo_rsize_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rsize:32; +#else + uint64_t rsize:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx; struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx; @@ -2034,8 +3542,13 @@ union cvmx_npei_pktx_slist_fifo_rsize { union cvmx_npei_pkt_cnt_int { uint64_t u64; struct cvmx_npei_pkt_cnt_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; +#else + uint64_t port:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_cnt_int_s cn52xx; struct cvmx_npei_pkt_cnt_int_s cn56xx; @@ -2044,8 +3557,13 @@ union cvmx_npei_pkt_cnt_int { union cvmx_npei_pkt_cnt_int_enb { uint64_t u64; struct cvmx_npei_pkt_cnt_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; +#else + uint64_t port:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_cnt_int_enb_s cn52xx; struct cvmx_npei_pkt_cnt_int_enb_s cn56xx; @@ -2054,7 +3572,11 @@ union cvmx_npei_pkt_cnt_int_enb { union cvmx_npei_pkt_data_out_es { uint64_t u64; struct cvmx_npei_pkt_data_out_es_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t es:64; +#else uint64_t es:64; +#endif } s; struct cvmx_npei_pkt_data_out_es_s cn52xx; struct cvmx_npei_pkt_data_out_es_s cn56xx; @@ -2063,8 +3585,13 @@ union cvmx_npei_pkt_data_out_es { union cvmx_npei_pkt_data_out_ns { uint64_t u64; struct cvmx_npei_pkt_data_out_ns_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t nsr:32; +#else + uint64_t nsr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_data_out_ns_s cn52xx; struct cvmx_npei_pkt_data_out_ns_s cn56xx; @@ -2073,8 +3600,13 @@ union cvmx_npei_pkt_data_out_ns { union cvmx_npei_pkt_data_out_ror { uint64_t u64; struct cvmx_npei_pkt_data_out_ror_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ror:32; +#else + uint64_t ror:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_data_out_ror_s cn52xx; struct cvmx_npei_pkt_data_out_ror_s cn56xx; @@ -2083,8 +3615,13 @@ union cvmx_npei_pkt_data_out_ror { union cvmx_npei_pkt_dpaddr { uint64_t u64; struct cvmx_npei_pkt_dpaddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t dptr:32; +#else + uint64_t dptr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_dpaddr_s cn52xx; struct cvmx_npei_pkt_dpaddr_s cn56xx; @@ -2093,8 +3630,13 @@ union cvmx_npei_pkt_dpaddr { union cvmx_npei_pkt_in_bp { uint64_t u64; struct cvmx_npei_pkt_in_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bp:32; +#else + uint64_t bp:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_in_bp_s cn52xx; struct cvmx_npei_pkt_in_bp_s cn56xx; @@ -2103,8 +3645,13 @@ union cvmx_npei_pkt_in_bp { union cvmx_npei_pkt_in_donex_cnts { uint64_t u64; struct cvmx_npei_pkt_in_donex_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_in_donex_cnts_s cn52xx; struct cvmx_npei_pkt_in_donex_cnts_s cn56xx; @@ -2113,8 +3660,13 @@ union cvmx_npei_pkt_in_donex_cnts { union cvmx_npei_pkt_in_instr_counts { uint64_t u64; struct cvmx_npei_pkt_in_instr_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_cnt:32; uint64_t rd_cnt:32; +#else + uint64_t rd_cnt:32; + uint64_t wr_cnt:32; +#endif } s; struct cvmx_npei_pkt_in_instr_counts_s cn52xx; struct cvmx_npei_pkt_in_instr_counts_s cn56xx; @@ -2123,7 +3675,11 @@ union cvmx_npei_pkt_in_instr_counts { union cvmx_npei_pkt_in_pcie_port { uint64_t u64; struct cvmx_npei_pkt_in_pcie_port_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t pp:64; +#else uint64_t pp:64; +#endif } s; struct cvmx_npei_pkt_in_pcie_port_s cn52xx; struct cvmx_npei_pkt_in_pcie_port_s cn56xx; @@ -2132,6 +3688,7 @@ union cvmx_npei_pkt_in_pcie_port { union cvmx_npei_pkt_input_control { uint64_t u64; struct cvmx_npei_pkt_input_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t pkt_rr:1; uint64_t pbp_dhi:13; @@ -2142,6 +3699,18 @@ union cvmx_npei_pkt_input_control { uint64_t nsr:1; uint64_t esr:2; uint64_t ror:1; +#else + uint64_t ror:1; + uint64_t esr:2; + uint64_t nsr:1; + uint64_t use_csr:1; + uint64_t d_ror:1; + uint64_t d_esr:2; + uint64_t d_nsr:1; + uint64_t pbp_dhi:13; + uint64_t pkt_rr:1; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_npei_pkt_input_control_s cn52xx; struct cvmx_npei_pkt_input_control_s cn56xx; @@ -2150,8 +3719,13 @@ union cvmx_npei_pkt_input_control { union cvmx_npei_pkt_instr_enb { uint64_t u64; struct cvmx_npei_pkt_instr_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enb:32; +#else + uint64_t enb:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_instr_enb_s cn52xx; struct cvmx_npei_pkt_instr_enb_s cn56xx; @@ -2160,7 +3734,11 @@ union cvmx_npei_pkt_instr_enb { union cvmx_npei_pkt_instr_rd_size { uint64_t u64; struct cvmx_npei_pkt_instr_rd_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rdsize:64; +#else + uint64_t rdsize:64; +#endif } s; struct cvmx_npei_pkt_instr_rd_size_s cn52xx; struct cvmx_npei_pkt_instr_rd_size_s cn56xx; @@ -2169,8 +3747,13 @@ union cvmx_npei_pkt_instr_rd_size { union cvmx_npei_pkt_instr_size { uint64_t u64; struct cvmx_npei_pkt_instr_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t is_64b:32; +#else + uint64_t is_64b:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_instr_size_s cn52xx; struct cvmx_npei_pkt_instr_size_s cn56xx; @@ -2179,9 +3762,15 @@ union cvmx_npei_pkt_instr_size { union cvmx_npei_pkt_int_levels { uint64_t u64; struct cvmx_npei_pkt_int_levels_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t time:22; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t time:22; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_npei_pkt_int_levels_s cn52xx; struct cvmx_npei_pkt_int_levels_s cn56xx; @@ -2190,8 +3779,13 @@ union cvmx_npei_pkt_int_levels { union cvmx_npei_pkt_iptr { uint64_t u64; struct cvmx_npei_pkt_iptr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iptr:32; +#else + uint64_t iptr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_iptr_s cn52xx; struct cvmx_npei_pkt_iptr_s cn56xx; @@ -2200,8 +3794,13 @@ union cvmx_npei_pkt_iptr { union cvmx_npei_pkt_out_bmode { uint64_t u64; struct cvmx_npei_pkt_out_bmode_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bmode:32; +#else + uint64_t bmode:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_out_bmode_s cn52xx; struct cvmx_npei_pkt_out_bmode_s cn56xx; @@ -2210,8 +3809,13 @@ union cvmx_npei_pkt_out_bmode { union cvmx_npei_pkt_out_enb { uint64_t u64; struct cvmx_npei_pkt_out_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enb:32; +#else + uint64_t enb:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_out_enb_s cn52xx; struct cvmx_npei_pkt_out_enb_s cn56xx; @@ -2220,8 +3824,13 @@ union cvmx_npei_pkt_out_enb { union cvmx_npei_pkt_output_wmark { uint64_t u64; struct cvmx_npei_pkt_output_wmark_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t wmark:32; +#else + uint64_t wmark:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_output_wmark_s cn52xx; struct cvmx_npei_pkt_output_wmark_s cn56xx; @@ -2230,7 +3839,11 @@ union cvmx_npei_pkt_output_wmark { union cvmx_npei_pkt_pcie_port { uint64_t u64; struct cvmx_npei_pkt_pcie_port_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t pp:64; +#else + uint64_t pp:64; +#endif } s; struct cvmx_npei_pkt_pcie_port_s cn52xx; struct cvmx_npei_pkt_pcie_port_s cn56xx; @@ -2239,8 +3852,13 @@ union cvmx_npei_pkt_pcie_port { union cvmx_npei_pkt_port_in_rst { uint64_t u64; struct cvmx_npei_pkt_port_in_rst_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t in_rst:32; uint64_t out_rst:32; +#else + uint64_t out_rst:32; + uint64_t in_rst:32; +#endif } s; struct cvmx_npei_pkt_port_in_rst_s cn52xx; struct cvmx_npei_pkt_port_in_rst_s cn56xx; @@ -2249,7 +3867,11 @@ union cvmx_npei_pkt_port_in_rst { union cvmx_npei_pkt_slist_es { uint64_t u64; struct cvmx_npei_pkt_slist_es_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t es:64; +#else + uint64_t es:64; +#endif } s; struct cvmx_npei_pkt_slist_es_s cn52xx; struct cvmx_npei_pkt_slist_es_s cn56xx; @@ -2258,9 +3880,15 @@ union cvmx_npei_pkt_slist_es { union cvmx_npei_pkt_slist_id_size { uint64_t u64; struct cvmx_npei_pkt_slist_id_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t isize:7; uint64_t bsize:16; +#else + uint64_t bsize:16; + uint64_t isize:7; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_npei_pkt_slist_id_size_s cn52xx; struct cvmx_npei_pkt_slist_id_size_s cn56xx; @@ -2269,8 +3897,13 @@ union cvmx_npei_pkt_slist_id_size { union cvmx_npei_pkt_slist_ns { uint64_t u64; struct cvmx_npei_pkt_slist_ns_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t nsr:32; +#else + uint64_t nsr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_slist_ns_s cn52xx; struct cvmx_npei_pkt_slist_ns_s cn56xx; @@ -2279,8 +3912,13 @@ union cvmx_npei_pkt_slist_ns { union cvmx_npei_pkt_slist_ror { uint64_t u64; struct cvmx_npei_pkt_slist_ror_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ror:32; +#else + uint64_t ror:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_slist_ror_s cn52xx; struct cvmx_npei_pkt_slist_ror_s cn56xx; @@ -2289,8 +3927,13 @@ union cvmx_npei_pkt_slist_ror { union cvmx_npei_pkt_time_int { uint64_t u64; struct cvmx_npei_pkt_time_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; +#else + uint64_t port:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_time_int_s cn52xx; struct cvmx_npei_pkt_time_int_s cn56xx; @@ -2299,8 +3942,13 @@ union cvmx_npei_pkt_time_int { union cvmx_npei_pkt_time_int_enb { uint64_t u64; struct cvmx_npei_pkt_time_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; +#else + uint64_t port:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_pkt_time_int_enb_s cn52xx; struct cvmx_npei_pkt_time_int_enb_s cn56xx; @@ -2309,6 +3957,7 @@ union cvmx_npei_pkt_time_int_enb { union cvmx_npei_rsl_int_blocks { uint64_t u64; struct cvmx_npei_rsl_int_blocks_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t iob:1; uint64_t lmc1:1; @@ -2338,6 +3987,37 @@ union cvmx_npei_rsl_int_blocks { uint64_t gmx1:1; uint64_t gmx0:1; uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t gmx1:1; + uint64_t npei:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t reserved_8_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t usb:1; + uint64_t rad:1; + uint64_t usb1:1; + uint64_t l2c:1; + uint64_t lmc0:1; + uint64_t spx0:1; + uint64_t spx1:1; + uint64_t pip:1; + uint64_t reserved_21_21:1; + uint64_t asxpcs0:1; + uint64_t asxpcs1:1; + uint64_t reserved_24_27:4; + uint64_t agl:1; + uint64_t lmc1:1; + uint64_t iob:1; + uint64_t reserved_31_63:33; +#endif } s; struct cvmx_npei_rsl_int_blocks_s cn52xx; struct cvmx_npei_rsl_int_blocks_s cn52xxp1; @@ -2348,7 +4028,11 @@ union cvmx_npei_rsl_int_blocks { union cvmx_npei_scratch_1 { uint64_t u64; struct cvmx_npei_scratch_1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_npei_scratch_1_s cn52xx; struct cvmx_npei_scratch_1_s cn52xxp1; @@ -2359,10 +4043,17 @@ union cvmx_npei_scratch_1 { union cvmx_npei_state1 { uint64_t u64; struct cvmx_npei_state1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t cpl1:12; uint64_t cpl0:12; uint64_t arb:1; uint64_t csr:39; +#else + uint64_t csr:39; + uint64_t arb:1; + uint64_t cpl0:12; + uint64_t cpl1:12; +#endif } s; struct cvmx_npei_state1_s cn52xx; struct cvmx_npei_state1_s cn52xxp1; @@ -2373,6 +4064,7 @@ union cvmx_npei_state1 { union cvmx_npei_state2 { uint64_t u64; struct cvmx_npei_state2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t npei:1; uint64_t rac:1; @@ -2380,6 +4072,15 @@ union cvmx_npei_state2 { uint64_t csm0:15; uint64_t nnp0:8; uint64_t nnd:8; +#else + uint64_t nnd:8; + uint64_t nnp0:8; + uint64_t csm0:15; + uint64_t csm1:15; + uint64_t rac:1; + uint64_t npei:1; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_npei_state2_s cn52xx; struct cvmx_npei_state2_s cn52xxp1; @@ -2390,11 +4091,19 @@ union cvmx_npei_state2 { union cvmx_npei_state3 { uint64_t u64; struct cvmx_npei_state3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t psm1:15; uint64_t psm0:15; uint64_t nsm1:13; uint64_t nsm0:13; +#else + uint64_t nsm0:13; + uint64_t nsm1:13; + uint64_t psm0:15; + uint64_t psm1:15; + uint64_t reserved_56_63:8; +#endif } s; struct cvmx_npei_state3_s cn52xx; struct cvmx_npei_state3_s cn52xxp1; @@ -2405,10 +4114,17 @@ union cvmx_npei_state3 { union cvmx_npei_win_rd_addr { uint64_t u64; struct cvmx_npei_win_rd_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_51_63:13; uint64_t ld_cmd:2; uint64_t iobit:1; uint64_t rd_addr:48; +#else + uint64_t rd_addr:48; + uint64_t iobit:1; + uint64_t ld_cmd:2; + uint64_t reserved_51_63:13; +#endif } s; struct cvmx_npei_win_rd_addr_s cn52xx; struct cvmx_npei_win_rd_addr_s cn52xxp1; @@ -2419,7 +4135,11 @@ union cvmx_npei_win_rd_addr { union cvmx_npei_win_rd_data { uint64_t u64; struct cvmx_npei_win_rd_data_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rd_data:64; +#else uint64_t rd_data:64; +#endif } s; struct cvmx_npei_win_rd_data_s cn52xx; struct cvmx_npei_win_rd_data_s cn52xxp1; @@ -2430,10 +4150,17 @@ union cvmx_npei_win_rd_data { union cvmx_npei_win_wr_addr { uint64_t u64; struct cvmx_npei_win_wr_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t wr_addr:46; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t wr_addr:46; + uint64_t iobit:1; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_npei_win_wr_addr_s cn52xx; struct cvmx_npei_win_wr_addr_s cn52xxp1; @@ -2444,7 +4171,11 @@ union cvmx_npei_win_wr_addr { union cvmx_npei_win_wr_data { uint64_t u64; struct cvmx_npei_win_wr_data_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_data:64; +#else + uint64_t wr_data:64; +#endif } s; struct cvmx_npei_win_wr_data_s cn52xx; struct cvmx_npei_win_wr_data_s cn52xxp1; @@ -2455,8 +4186,13 @@ union cvmx_npei_win_wr_data { union cvmx_npei_win_wr_mask { uint64_t u64; struct cvmx_npei_win_wr_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t wr_mask:8; +#else + uint64_t wr_mask:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_npei_win_wr_mask_s cn52xx; struct cvmx_npei_win_wr_mask_s cn52xxp1; @@ -2467,8 +4203,13 @@ union cvmx_npei_win_wr_mask { union cvmx_npei_window_ctl { uint64_t u64; struct cvmx_npei_window_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t time:32; +#else + uint64_t time:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npei_window_ctl_s cn52xx; struct cvmx_npei_window_ctl_s cn52xxp1; diff --git a/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/arch/mips/include/asm/octeon/cvmx-npi-defs.h index f089c780060..129bb250e53 100644 --- a/arch/mips/include/asm/octeon/cvmx-npi-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -152,8 +152,13 @@ union cvmx_npi_base_addr_inputx { uint64_t u64; struct cvmx_npi_base_addr_inputx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t baddr:61; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t baddr:61; +#endif } s; struct cvmx_npi_base_addr_inputx_s cn30xx; struct cvmx_npi_base_addr_inputx_s cn31xx; @@ -167,8 +172,13 @@ union cvmx_npi_base_addr_inputx { union cvmx_npi_base_addr_outputx { uint64_t u64; struct cvmx_npi_base_addr_outputx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t baddr:61; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t baddr:61; +#endif } s; struct cvmx_npi_base_addr_outputx_s cn30xx; struct cvmx_npi_base_addr_outputx_s cn31xx; @@ -182,6 +192,7 @@ union cvmx_npi_base_addr_outputx { union cvmx_npi_bist_status { uint64_t u64; struct cvmx_npi_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t csr_bs:1; uint64_t dif_bs:1; @@ -203,8 +214,32 @@ union cvmx_npi_bist_status { uint64_t dob_bs:1; uint64_t pdf_bs:1; uint64_t dpi_bs:1; +#else + uint64_t dpi_bs:1; + uint64_t pdf_bs:1; + uint64_t dob_bs:1; + uint64_t nus_bs:1; + uint64_t pos_bs:1; + uint64_t pof3_bs:1; + uint64_t pof2_bs:1; + uint64_t pof1_bs:1; + uint64_t pof0_bs:1; + uint64_t pig_bs:1; + uint64_t pgf_bs:1; + uint64_t rdnl_bs:1; + uint64_t pcad_bs:1; + uint64_t pcac_bs:1; + uint64_t rdn_bs:1; + uint64_t pcn_bs:1; + uint64_t pcnc_bs:1; + uint64_t rdp_bs:1; + uint64_t dif_bs:1; + uint64_t csr_bs:1; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_npi_bist_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t csr_bs:1; uint64_t dif_bs:1; @@ -224,11 +259,33 @@ union cvmx_npi_bist_status { uint64_t dob_bs:1; uint64_t pdf_bs:1; uint64_t dpi_bs:1; +#else + uint64_t dpi_bs:1; + uint64_t pdf_bs:1; + uint64_t dob_bs:1; + uint64_t nus_bs:1; + uint64_t pos_bs:1; + uint64_t reserved_5_7:3; + uint64_t pof0_bs:1; + uint64_t pig_bs:1; + uint64_t pgf_bs:1; + uint64_t rdnl_bs:1; + uint64_t pcad_bs:1; + uint64_t pcac_bs:1; + uint64_t rdn_bs:1; + uint64_t pcn_bs:1; + uint64_t pcnc_bs:1; + uint64_t rdp_bs:1; + uint64_t dif_bs:1; + uint64_t csr_bs:1; + uint64_t reserved_20_63:44; +#endif } cn30xx; struct cvmx_npi_bist_status_s cn31xx; struct cvmx_npi_bist_status_s cn38xx; struct cvmx_npi_bist_status_s cn38xxp2; struct cvmx_npi_bist_status_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t csr_bs:1; uint64_t dif_bs:1; @@ -249,6 +306,28 @@ union cvmx_npi_bist_status { uint64_t dob_bs:1; uint64_t pdf_bs:1; uint64_t dpi_bs:1; +#else + uint64_t dpi_bs:1; + uint64_t pdf_bs:1; + uint64_t dob_bs:1; + uint64_t nus_bs:1; + uint64_t pos_bs:1; + uint64_t reserved_5_6:2; + uint64_t pof1_bs:1; + uint64_t pof0_bs:1; + uint64_t pig_bs:1; + uint64_t pgf_bs:1; + uint64_t rdnl_bs:1; + uint64_t pcad_bs:1; + uint64_t pcac_bs:1; + uint64_t rdn_bs:1; + uint64_t pcn_bs:1; + uint64_t pcnc_bs:1; + uint64_t rdp_bs:1; + uint64_t dif_bs:1; + uint64_t csr_bs:1; + uint64_t reserved_20_63:44; +#endif } cn50xx; struct cvmx_npi_bist_status_s cn58xx; struct cvmx_npi_bist_status_s cn58xxp1; @@ -257,9 +336,15 @@ union cvmx_npi_bist_status { union cvmx_npi_buff_size_outputx { uint64_t u64; struct cvmx_npi_buff_size_outputx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t isize:7; uint64_t bsize:16; +#else + uint64_t bsize:16; + uint64_t isize:7; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_npi_buff_size_outputx_s cn30xx; struct cvmx_npi_buff_size_outputx_s cn31xx; @@ -273,9 +358,15 @@ union cvmx_npi_buff_size_outputx { union cvmx_npi_comp_ctl { uint64_t u64; struct cvmx_npi_comp_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t pctl:5; uint64_t nctl:5; +#else + uint64_t nctl:5; + uint64_t pctl:5; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_npi_comp_ctl_s cn50xx; struct cvmx_npi_comp_ctl_s cn58xx; @@ -285,6 +376,7 @@ union cvmx_npi_comp_ctl { union cvmx_npi_ctl_status { uint64_t u64; struct cvmx_npi_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_63_63:1; uint64_t chip_rev:8; uint64_t dis_pniw:1; @@ -306,8 +398,32 @@ union cvmx_npi_ctl_status { uint64_t max_word:5; uint64_t reserved_10_31:22; uint64_t timer:10; +#else + uint64_t timer:10; + uint64_t reserved_10_31:22; + uint64_t max_word:5; + uint64_t reserved_37_39:3; + uint64_t wait_com:1; + uint64_t pci_wdis:1; + uint64_t ins0_64b:1; + uint64_t ins1_64b:1; + uint64_t ins2_64b:1; + uint64_t ins3_64b:1; + uint64_t ins0_enb:1; + uint64_t ins1_enb:1; + uint64_t ins2_enb:1; + uint64_t ins3_enb:1; + uint64_t out0_enb:1; + uint64_t out1_enb:1; + uint64_t out2_enb:1; + uint64_t out3_enb:1; + uint64_t dis_pniw:1; + uint64_t chip_rev:8; + uint64_t reserved_63_63:1; +#endif } s; struct cvmx_npi_ctl_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_63_63:1; uint64_t chip_rev:8; uint64_t dis_pniw:1; @@ -323,8 +439,26 @@ union cvmx_npi_ctl_status { uint64_t max_word:5; uint64_t reserved_10_31:22; uint64_t timer:10; +#else + uint64_t timer:10; + uint64_t reserved_10_31:22; + uint64_t max_word:5; + uint64_t reserved_37_39:3; + uint64_t wait_com:1; + uint64_t pci_wdis:1; + uint64_t ins0_64b:1; + uint64_t reserved_43_45:3; + uint64_t ins0_enb:1; + uint64_t reserved_47_49:3; + uint64_t out0_enb:1; + uint64_t reserved_51_53:3; + uint64_t dis_pniw:1; + uint64_t chip_rev:8; + uint64_t reserved_63_63:1; +#endif } cn30xx; struct cvmx_npi_ctl_status_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_63_63:1; uint64_t chip_rev:8; uint64_t dis_pniw:1; @@ -343,6 +477,26 @@ union cvmx_npi_ctl_status { uint64_t max_word:5; uint64_t reserved_10_31:22; uint64_t timer:10; +#else + uint64_t timer:10; + uint64_t reserved_10_31:22; + uint64_t max_word:5; + uint64_t reserved_37_39:3; + uint64_t wait_com:1; + uint64_t pci_wdis:1; + uint64_t ins0_64b:1; + uint64_t ins1_64b:1; + uint64_t reserved_44_45:2; + uint64_t ins0_enb:1; + uint64_t ins1_enb:1; + uint64_t reserved_48_49:2; + uint64_t out0_enb:1; + uint64_t out1_enb:1; + uint64_t reserved_52_53:2; + uint64_t dis_pniw:1; + uint64_t chip_rev:8; + uint64_t reserved_63_63:1; +#endif } cn31xx; struct cvmx_npi_ctl_status_s cn38xx; struct cvmx_npi_ctl_status_s cn38xxp2; @@ -354,8 +508,13 @@ union cvmx_npi_ctl_status { union cvmx_npi_dbg_select { uint64_t u64; struct cvmx_npi_dbg_select_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dbg_sel:16; +#else + uint64_t dbg_sel:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_npi_dbg_select_s cn30xx; struct cvmx_npi_dbg_select_s cn31xx; @@ -369,6 +528,7 @@ union cvmx_npi_dbg_select { union cvmx_npi_dma_control { uint64_t u64; struct cvmx_npi_dma_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t b0_lend:1; uint64_t dwb_denb:1; @@ -382,6 +542,21 @@ union cvmx_npi_dma_control { uint64_t hp_enb:1; uint64_t lp_enb:1; uint64_t csize:14; +#else + uint64_t csize:14; + uint64_t lp_enb:1; + uint64_t hp_enb:1; + uint64_t o_mode:1; + uint64_t o_es:2; + uint64_t o_ns:1; + uint64_t o_ro:1; + uint64_t o_add1:1; + uint64_t fpa_que:3; + uint64_t dwb_ichk:9; + uint64_t dwb_denb:1; + uint64_t b0_lend:1; + uint64_t reserved_36_63:28; +#endif } s; struct cvmx_npi_dma_control_s cn30xx; struct cvmx_npi_dma_control_s cn31xx; @@ -395,9 +570,15 @@ union cvmx_npi_dma_control { union cvmx_npi_dma_highp_counts { uint64_t u64; struct cvmx_npi_dma_highp_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t fcnt:7; uint64_t dbell:32; +#else + uint64_t dbell:32; + uint64_t fcnt:7; + uint64_t reserved_39_63:25; +#endif } s; struct cvmx_npi_dma_highp_counts_s cn30xx; struct cvmx_npi_dma_highp_counts_s cn31xx; @@ -411,9 +592,15 @@ union cvmx_npi_dma_highp_counts { union cvmx_npi_dma_highp_naddr { uint64_t u64; struct cvmx_npi_dma_highp_naddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t state:4; uint64_t addr:36; +#else + uint64_t addr:36; + uint64_t state:4; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_npi_dma_highp_naddr_s cn30xx; struct cvmx_npi_dma_highp_naddr_s cn31xx; @@ -427,9 +614,15 @@ union cvmx_npi_dma_highp_naddr { union cvmx_npi_dma_lowp_counts { uint64_t u64; struct cvmx_npi_dma_lowp_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_39_63:25; uint64_t fcnt:7; uint64_t dbell:32; +#else + uint64_t dbell:32; + uint64_t fcnt:7; + uint64_t reserved_39_63:25; +#endif } s; struct cvmx_npi_dma_lowp_counts_s cn30xx; struct cvmx_npi_dma_lowp_counts_s cn31xx; @@ -443,9 +636,15 @@ union cvmx_npi_dma_lowp_counts { union cvmx_npi_dma_lowp_naddr { uint64_t u64; struct cvmx_npi_dma_lowp_naddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t state:4; uint64_t addr:36; +#else + uint64_t addr:36; + uint64_t state:4; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_npi_dma_lowp_naddr_s cn30xx; struct cvmx_npi_dma_lowp_naddr_s cn31xx; @@ -459,8 +658,13 @@ union cvmx_npi_dma_lowp_naddr { union cvmx_npi_highp_dbell { uint64_t u64; struct cvmx_npi_highp_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dbell:16; +#else + uint64_t dbell:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_npi_highp_dbell_s cn30xx; struct cvmx_npi_highp_dbell_s cn31xx; @@ -474,8 +678,13 @@ union cvmx_npi_highp_dbell { union cvmx_npi_highp_ibuff_saddr { uint64_t u64; struct cvmx_npi_highp_ibuff_saddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t saddr:36; +#else + uint64_t saddr:36; + uint64_t reserved_36_63:28; +#endif } s; struct cvmx_npi_highp_ibuff_saddr_s cn30xx; struct cvmx_npi_highp_ibuff_saddr_s cn31xx; @@ -489,6 +698,7 @@ union cvmx_npi_highp_ibuff_saddr { union cvmx_npi_input_control { uint64_t u64; struct cvmx_npi_input_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t pkt_rr:1; uint64_t pbp_dhi:13; @@ -499,8 +709,21 @@ union cvmx_npi_input_control { uint64_t nsr:1; uint64_t esr:2; uint64_t ror:1; +#else + uint64_t ror:1; + uint64_t esr:2; + uint64_t nsr:1; + uint64_t use_csr:1; + uint64_t d_ror:1; + uint64_t d_esr:2; + uint64_t d_nsr:1; + uint64_t pbp_dhi:13; + uint64_t pkt_rr:1; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_npi_input_control_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t pbp_dhi:13; uint64_t d_nsr:1; @@ -510,6 +733,17 @@ union cvmx_npi_input_control { uint64_t nsr:1; uint64_t esr:2; uint64_t ror:1; +#else + uint64_t ror:1; + uint64_t esr:2; + uint64_t nsr:1; + uint64_t use_csr:1; + uint64_t d_ror:1; + uint64_t d_esr:2; + uint64_t d_nsr:1; + uint64_t pbp_dhi:13; + uint64_t reserved_22_63:42; +#endif } cn30xx; struct cvmx_npi_input_control_cn30xx cn31xx; struct cvmx_npi_input_control_s cn38xx; @@ -522,6 +756,7 @@ union cvmx_npi_input_control { union cvmx_npi_int_enb { uint64_t u64; struct cvmx_npi_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -585,8 +820,74 @@ union cvmx_npi_int_enb { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t pci_rsl:1; + uint64_t po0_2sml:1; + uint64_t po1_2sml:1; + uint64_t po2_2sml:1; + uint64_t po3_2sml:1; + uint64_t i0_rtout:1; + uint64_t i1_rtout:1; + uint64_t i2_rtout:1; + uint64_t i3_rtout:1; + uint64_t i0_overf:1; + uint64_t i1_overf:1; + uint64_t i2_overf:1; + uint64_t i3_overf:1; + uint64_t p0_rtout:1; + uint64_t p1_rtout:1; + uint64_t p2_rtout:1; + uint64_t p3_rtout:1; + uint64_t p0_perr:1; + uint64_t p1_perr:1; + uint64_t p2_perr:1; + uint64_t p3_perr:1; + uint64_t g0_rtout:1; + uint64_t g1_rtout:1; + uint64_t g2_rtout:1; + uint64_t g3_rtout:1; + uint64_t p0_pperr:1; + uint64_t p1_pperr:1; + uint64_t p2_pperr:1; + uint64_t p3_pperr:1; + uint64_t p0_ptout:1; + uint64_t p1_ptout:1; + uint64_t p2_ptout:1; + uint64_t p3_ptout:1; + uint64_t i0_pperr:1; + uint64_t i1_pperr:1; + uint64_t i2_pperr:1; + uint64_t i3_pperr:1; + uint64_t win_rto:1; + uint64_t p_dperr:1; + uint64_t iobdma:1; + uint64_t fcr_s_e:1; + uint64_t fcr_a_f:1; + uint64_t pcr_s_e:1; + uint64_t pcr_a_f:1; + uint64_t q2_s_e:1; + uint64_t q2_a_f:1; + uint64_t q3_s_e:1; + uint64_t q3_a_f:1; + uint64_t com_s_e:1; + uint64_t com_a_f:1; + uint64_t pnc_s_e:1; + uint64_t pnc_a_f:1; + uint64_t rwx_s_e:1; + uint64_t rdx_s_e:1; + uint64_t pcf_p_e:1; + uint64_t pcf_p_f:1; + uint64_t pdf_p_e:1; + uint64_t pdf_p_f:1; + uint64_t q1_s_e:1; + uint64_t q1_a_f:1; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_npi_int_enb_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -632,8 +933,56 @@ union cvmx_npi_int_enb { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t pci_rsl:1; + uint64_t po0_2sml:1; + uint64_t reserved_4_6:3; + uint64_t i0_rtout:1; + uint64_t reserved_8_10:3; + uint64_t i0_overf:1; + uint64_t reserved_12_14:3; + uint64_t p0_rtout:1; + uint64_t reserved_16_18:3; + uint64_t p0_perr:1; + uint64_t reserved_20_22:3; + uint64_t g0_rtout:1; + uint64_t reserved_24_26:3; + uint64_t p0_pperr:1; + uint64_t reserved_28_30:3; + uint64_t p0_ptout:1; + uint64_t reserved_32_34:3; + uint64_t i0_pperr:1; + uint64_t reserved_36_38:3; + uint64_t win_rto:1; + uint64_t p_dperr:1; + uint64_t iobdma:1; + uint64_t fcr_s_e:1; + uint64_t fcr_a_f:1; + uint64_t pcr_s_e:1; + uint64_t pcr_a_f:1; + uint64_t q2_s_e:1; + uint64_t q2_a_f:1; + uint64_t q3_s_e:1; + uint64_t q3_a_f:1; + uint64_t com_s_e:1; + uint64_t com_a_f:1; + uint64_t pnc_s_e:1; + uint64_t pnc_a_f:1; + uint64_t rwx_s_e:1; + uint64_t rdx_s_e:1; + uint64_t pcf_p_e:1; + uint64_t pcf_p_f:1; + uint64_t pdf_p_e:1; + uint64_t pdf_p_f:1; + uint64_t q1_s_e:1; + uint64_t q1_a_f:1; + uint64_t reserved_62_63:2; +#endif } cn30xx; struct cvmx_npi_int_enb_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -688,9 +1037,66 @@ union cvmx_npi_int_enb { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t pci_rsl:1; + uint64_t po0_2sml:1; + uint64_t po1_2sml:1; + uint64_t reserved_5_6:2; + uint64_t i0_rtout:1; + uint64_t i1_rtout:1; + uint64_t reserved_9_10:2; + uint64_t i0_overf:1; + uint64_t i1_overf:1; + uint64_t reserved_13_14:2; + uint64_t p0_rtout:1; + uint64_t p1_rtout:1; + uint64_t reserved_17_18:2; + uint64_t p0_perr:1; + uint64_t p1_perr:1; + uint64_t reserved_21_22:2; + uint64_t g0_rtout:1; + uint64_t g1_rtout:1; + uint64_t reserved_25_26:2; + uint64_t p0_pperr:1; + uint64_t p1_pperr:1; + uint64_t reserved_29_30:2; + uint64_t p0_ptout:1; + uint64_t p1_ptout:1; + uint64_t reserved_33_34:2; + uint64_t i0_pperr:1; + uint64_t i1_pperr:1; + uint64_t reserved_37_38:2; + uint64_t win_rto:1; + uint64_t p_dperr:1; + uint64_t iobdma:1; + uint64_t fcr_s_e:1; + uint64_t fcr_a_f:1; + uint64_t pcr_s_e:1; + uint64_t pcr_a_f:1; + uint64_t q2_s_e:1; + uint64_t q2_a_f:1; + uint64_t q3_s_e:1; + uint64_t q3_a_f:1; + uint64_t com_s_e:1; + uint64_t com_a_f:1; + uint64_t pnc_s_e:1; + uint64_t pnc_a_f:1; + uint64_t rwx_s_e:1; + uint64_t rdx_s_e:1; + uint64_t pcf_p_e:1; + uint64_t pcf_p_f:1; + uint64_t pdf_p_e:1; + uint64_t pdf_p_f:1; + uint64_t q1_s_e:1; + uint64_t q1_a_f:1; + uint64_t reserved_62_63:2; +#endif } cn31xx; struct cvmx_npi_int_enb_s cn38xx; struct cvmx_npi_int_enb_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t iobdma:1; uint64_t p_dperr:1; @@ -734,6 +1140,51 @@ union cvmx_npi_int_enb { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t pci_rsl:1; + uint64_t po0_2sml:1; + uint64_t po1_2sml:1; + uint64_t po2_2sml:1; + uint64_t po3_2sml:1; + uint64_t i0_rtout:1; + uint64_t i1_rtout:1; + uint64_t i2_rtout:1; + uint64_t i3_rtout:1; + uint64_t i0_overf:1; + uint64_t i1_overf:1; + uint64_t i2_overf:1; + uint64_t i3_overf:1; + uint64_t p0_rtout:1; + uint64_t p1_rtout:1; + uint64_t p2_rtout:1; + uint64_t p3_rtout:1; + uint64_t p0_perr:1; + uint64_t p1_perr:1; + uint64_t p2_perr:1; + uint64_t p3_perr:1; + uint64_t g0_rtout:1; + uint64_t g1_rtout:1; + uint64_t g2_rtout:1; + uint64_t g3_rtout:1; + uint64_t p0_pperr:1; + uint64_t p1_pperr:1; + uint64_t p2_pperr:1; + uint64_t p3_pperr:1; + uint64_t p0_ptout:1; + uint64_t p1_ptout:1; + uint64_t p2_ptout:1; + uint64_t p3_ptout:1; + uint64_t i0_pperr:1; + uint64_t i1_pperr:1; + uint64_t i2_pperr:1; + uint64_t i3_pperr:1; + uint64_t win_rto:1; + uint64_t p_dperr:1; + uint64_t iobdma:1; + uint64_t reserved_42_63:22; +#endif } cn38xxp2; struct cvmx_npi_int_enb_cn31xx cn50xx; struct cvmx_npi_int_enb_s cn58xx; @@ -743,6 +1194,7 @@ union cvmx_npi_int_enb { union cvmx_npi_int_sum { uint64_t u64; struct cvmx_npi_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -806,8 +1258,74 @@ union cvmx_npi_int_sum { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t pci_rsl:1; + uint64_t po0_2sml:1; + uint64_t po1_2sml:1; + uint64_t po2_2sml:1; + uint64_t po3_2sml:1; + uint64_t i0_rtout:1; + uint64_t i1_rtout:1; + uint64_t i2_rtout:1; + uint64_t i3_rtout:1; + uint64_t i0_overf:1; + uint64_t i1_overf:1; + uint64_t i2_overf:1; + uint64_t i3_overf:1; + uint64_t p0_rtout:1; + uint64_t p1_rtout:1; + uint64_t p2_rtout:1; + uint64_t p3_rtout:1; + uint64_t p0_perr:1; + uint64_t p1_perr:1; + uint64_t p2_perr:1; + uint64_t p3_perr:1; + uint64_t g0_rtout:1; + uint64_t g1_rtout:1; + uint64_t g2_rtout:1; + uint64_t g3_rtout:1; + uint64_t p0_pperr:1; + uint64_t p1_pperr:1; + uint64_t p2_pperr:1; + uint64_t p3_pperr:1; + uint64_t p0_ptout:1; + uint64_t p1_ptout:1; + uint64_t p2_ptout:1; + uint64_t p3_ptout:1; + uint64_t i0_pperr:1; + uint64_t i1_pperr:1; + uint64_t i2_pperr:1; + uint64_t i3_pperr:1; + uint64_t win_rto:1; + uint64_t p_dperr:1; + uint64_t iobdma:1; + uint64_t fcr_s_e:1; + uint64_t fcr_a_f:1; + uint64_t pcr_s_e:1; + uint64_t pcr_a_f:1; + uint64_t q2_s_e:1; + uint64_t q2_a_f:1; + uint64_t q3_s_e:1; + uint64_t q3_a_f:1; + uint64_t com_s_e:1; + uint64_t com_a_f:1; + uint64_t pnc_s_e:1; + uint64_t pnc_a_f:1; + uint64_t rwx_s_e:1; + uint64_t rdx_s_e:1; + uint64_t pcf_p_e:1; + uint64_t pcf_p_f:1; + uint64_t pdf_p_e:1; + uint64_t pdf_p_f:1; + uint64_t q1_s_e:1; + uint64_t q1_a_f:1; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_npi_int_sum_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -853,8 +1371,56 @@ union cvmx_npi_int_sum { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t pci_rsl:1; + uint64_t po0_2sml:1; + uint64_t reserved_4_6:3; + uint64_t i0_rtout:1; + uint64_t reserved_8_10:3; + uint64_t i0_overf:1; + uint64_t reserved_12_14:3; + uint64_t p0_rtout:1; + uint64_t reserved_16_18:3; + uint64_t p0_perr:1; + uint64_t reserved_20_22:3; + uint64_t g0_rtout:1; + uint64_t reserved_24_26:3; + uint64_t p0_pperr:1; + uint64_t reserved_28_30:3; + uint64_t p0_ptout:1; + uint64_t reserved_32_34:3; + uint64_t i0_pperr:1; + uint64_t reserved_36_38:3; + uint64_t win_rto:1; + uint64_t p_dperr:1; + uint64_t iobdma:1; + uint64_t fcr_s_e:1; + uint64_t fcr_a_f:1; + uint64_t pcr_s_e:1; + uint64_t pcr_a_f:1; + uint64_t q2_s_e:1; + uint64_t q2_a_f:1; + uint64_t q3_s_e:1; + uint64_t q3_a_f:1; + uint64_t com_s_e:1; + uint64_t com_a_f:1; + uint64_t pnc_s_e:1; + uint64_t pnc_a_f:1; + uint64_t rwx_s_e:1; + uint64_t rdx_s_e:1; + uint64_t pcf_p_e:1; + uint64_t pcf_p_f:1; + uint64_t pdf_p_e:1; + uint64_t pdf_p_f:1; + uint64_t q1_s_e:1; + uint64_t q1_a_f:1; + uint64_t reserved_62_63:2; +#endif } cn30xx; struct cvmx_npi_int_sum_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t q1_a_f:1; uint64_t q1_s_e:1; @@ -909,9 +1475,66 @@ union cvmx_npi_int_sum { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t pci_rsl:1; + uint64_t po0_2sml:1; + uint64_t po1_2sml:1; + uint64_t reserved_5_6:2; + uint64_t i0_rtout:1; + uint64_t i1_rtout:1; + uint64_t reserved_9_10:2; + uint64_t i0_overf:1; + uint64_t i1_overf:1; + uint64_t reserved_13_14:2; + uint64_t p0_rtout:1; + uint64_t p1_rtout:1; + uint64_t reserved_17_18:2; + uint64_t p0_perr:1; + uint64_t p1_perr:1; + uint64_t reserved_21_22:2; + uint64_t g0_rtout:1; + uint64_t g1_rtout:1; + uint64_t reserved_25_26:2; + uint64_t p0_pperr:1; + uint64_t p1_pperr:1; + uint64_t reserved_29_30:2; + uint64_t p0_ptout:1; + uint64_t p1_ptout:1; + uint64_t reserved_33_34:2; + uint64_t i0_pperr:1; + uint64_t i1_pperr:1; + uint64_t reserved_37_38:2; + uint64_t win_rto:1; + uint64_t p_dperr:1; + uint64_t iobdma:1; + uint64_t fcr_s_e:1; + uint64_t fcr_a_f:1; + uint64_t pcr_s_e:1; + uint64_t pcr_a_f:1; + uint64_t q2_s_e:1; + uint64_t q2_a_f:1; + uint64_t q3_s_e:1; + uint64_t q3_a_f:1; + uint64_t com_s_e:1; + uint64_t com_a_f:1; + uint64_t pnc_s_e:1; + uint64_t pnc_a_f:1; + uint64_t rwx_s_e:1; + uint64_t rdx_s_e:1; + uint64_t pcf_p_e:1; + uint64_t pcf_p_f:1; + uint64_t pdf_p_e:1; + uint64_t pdf_p_f:1; + uint64_t q1_s_e:1; + uint64_t q1_a_f:1; + uint64_t reserved_62_63:2; +#endif } cn31xx; struct cvmx_npi_int_sum_s cn38xx; struct cvmx_npi_int_sum_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_42_63:22; uint64_t iobdma:1; uint64_t p_dperr:1; @@ -955,6 +1578,51 @@ union cvmx_npi_int_sum { uint64_t pci_rsl:1; uint64_t rml_wto:1; uint64_t rml_rto:1; +#else + uint64_t rml_rto:1; + uint64_t rml_wto:1; + uint64_t pci_rsl:1; + uint64_t po0_2sml:1; + uint64_t po1_2sml:1; + uint64_t po2_2sml:1; + uint64_t po3_2sml:1; + uint64_t i0_rtout:1; + uint64_t i1_rtout:1; + uint64_t i2_rtout:1; + uint64_t i3_rtout:1; + uint64_t i0_overf:1; + uint64_t i1_overf:1; + uint64_t i2_overf:1; + uint64_t i3_overf:1; + uint64_t p0_rtout:1; + uint64_t p1_rtout:1; + uint64_t p2_rtout:1; + uint64_t p3_rtout:1; + uint64_t p0_perr:1; + uint64_t p1_perr:1; + uint64_t p2_perr:1; + uint64_t p3_perr:1; + uint64_t g0_rtout:1; + uint64_t g1_rtout:1; + uint64_t g2_rtout:1; + uint64_t g3_rtout:1; + uint64_t p0_pperr:1; + uint64_t p1_pperr:1; + uint64_t p2_pperr:1; + uint64_t p3_pperr:1; + uint64_t p0_ptout:1; + uint64_t p1_ptout:1; + uint64_t p2_ptout:1; + uint64_t p3_ptout:1; + uint64_t i0_pperr:1; + uint64_t i1_pperr:1; + uint64_t i2_pperr:1; + uint64_t i3_pperr:1; + uint64_t win_rto:1; + uint64_t p_dperr:1; + uint64_t iobdma:1; + uint64_t reserved_42_63:22; +#endif } cn38xxp2; struct cvmx_npi_int_sum_cn31xx cn50xx; struct cvmx_npi_int_sum_s cn58xx; @@ -964,8 +1632,13 @@ union cvmx_npi_int_sum { union cvmx_npi_lowp_dbell { uint64_t u64; struct cvmx_npi_lowp_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dbell:16; +#else + uint64_t dbell:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_npi_lowp_dbell_s cn30xx; struct cvmx_npi_lowp_dbell_s cn31xx; @@ -979,8 +1652,13 @@ union cvmx_npi_lowp_dbell { union cvmx_npi_lowp_ibuff_saddr { uint64_t u64; struct cvmx_npi_lowp_ibuff_saddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t saddr:36; +#else + uint64_t saddr:36; + uint64_t reserved_36_63:28; +#endif } s; struct cvmx_npi_lowp_ibuff_saddr_s cn30xx; struct cvmx_npi_lowp_ibuff_saddr_s cn31xx; @@ -994,6 +1672,7 @@ union cvmx_npi_lowp_ibuff_saddr { union cvmx_npi_mem_access_subidx { uint64_t u64; struct cvmx_npi_mem_access_subidx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t shortl:1; uint64_t nmerge:1; @@ -1004,9 +1683,22 @@ union cvmx_npi_mem_access_subidx { uint64_t ror:1; uint64_t row:1; uint64_t ba:28; +#else + uint64_t ba:28; + uint64_t row:1; + uint64_t ror:1; + uint64_t nsw:1; + uint64_t nsr:1; + uint64_t esw:2; + uint64_t esr:2; + uint64_t nmerge:1; + uint64_t shortl:1; + uint64_t reserved_38_63:26; +#endif } s; struct cvmx_npi_mem_access_subidx_s cn30xx; struct cvmx_npi_mem_access_subidx_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t esr:2; uint64_t esw:2; @@ -1015,6 +1707,16 @@ union cvmx_npi_mem_access_subidx { uint64_t ror:1; uint64_t row:1; uint64_t ba:28; +#else + uint64_t ba:28; + uint64_t row:1; + uint64_t ror:1; + uint64_t nsw:1; + uint64_t nsr:1; + uint64_t esw:2; + uint64_t esr:2; + uint64_t reserved_36_63:28; +#endif } cn31xx; struct cvmx_npi_mem_access_subidx_s cn38xx; struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2; @@ -1026,7 +1728,11 @@ union cvmx_npi_mem_access_subidx { union cvmx_npi_msi_rcv { uint64_t u64; struct cvmx_npi_msi_rcv_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t int_vec:64; +#else uint64_t int_vec:64; +#endif } s; struct cvmx_npi_msi_rcv_s cn30xx; struct cvmx_npi_msi_rcv_s cn31xx; @@ -1040,8 +1746,13 @@ union cvmx_npi_msi_rcv { union cvmx_npi_num_desc_outputx { uint64_t u64; struct cvmx_npi_num_desc_outputx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t size:32; +#else + uint64_t size:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npi_num_desc_outputx_s cn30xx; struct cvmx_npi_num_desc_outputx_s cn31xx; @@ -1055,6 +1766,7 @@ union cvmx_npi_num_desc_outputx { union cvmx_npi_output_control { uint64_t u64; struct cvmx_npi_output_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t pkt_rr:1; uint64_t p3_bmode:1; @@ -1094,8 +1806,50 @@ union cvmx_npi_output_control { uint64_t esr_sl0:2; uint64_t nsr_sl0:1; uint64_t ror_sl0:1; +#else + uint64_t ror_sl0:1; + uint64_t nsr_sl0:1; + uint64_t esr_sl0:2; + uint64_t ror_sl1:1; + uint64_t nsr_sl1:1; + uint64_t esr_sl1:2; + uint64_t ror_sl2:1; + uint64_t nsr_sl2:1; + uint64_t esr_sl2:2; + uint64_t ror_sl3:1; + uint64_t nsr_sl3:1; + uint64_t esr_sl3:2; + uint64_t iptr_o0:1; + uint64_t iptr_o1:1; + uint64_t iptr_o2:1; + uint64_t iptr_o3:1; + uint64_t reserved_20_23:4; + uint64_t o0_csrm:1; + uint64_t o1_csrm:1; + uint64_t o2_csrm:1; + uint64_t o3_csrm:1; + uint64_t o0_ro:1; + uint64_t o0_ns:1; + uint64_t o0_es:2; + uint64_t o1_ro:1; + uint64_t o1_ns:1; + uint64_t o1_es:2; + uint64_t o2_ro:1; + uint64_t o2_ns:1; + uint64_t o2_es:2; + uint64_t o3_ro:1; + uint64_t o3_ns:1; + uint64_t o3_es:2; + uint64_t p0_bmode:1; + uint64_t p1_bmode:1; + uint64_t p2_bmode:1; + uint64_t p3_bmode:1; + uint64_t pkt_rr:1; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_npi_output_control_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t p0_bmode:1; uint64_t reserved_32_43:12; @@ -1110,8 +1864,25 @@ union cvmx_npi_output_control { uint64_t esr_sl0:2; uint64_t nsr_sl0:1; uint64_t ror_sl0:1; +#else + uint64_t ror_sl0:1; + uint64_t nsr_sl0:1; + uint64_t esr_sl0:2; + uint64_t reserved_4_15:12; + uint64_t iptr_o0:1; + uint64_t reserved_17_23:7; + uint64_t o0_csrm:1; + uint64_t reserved_25_27:3; + uint64_t o0_ro:1; + uint64_t o0_ns:1; + uint64_t o0_es:2; + uint64_t reserved_32_43:12; + uint64_t p0_bmode:1; + uint64_t reserved_45_63:19; +#endif } cn30xx; struct cvmx_npi_output_control_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_46_63:18; uint64_t p1_bmode:1; uint64_t p0_bmode:1; @@ -1135,9 +1906,35 @@ union cvmx_npi_output_control { uint64_t esr_sl0:2; uint64_t nsr_sl0:1; uint64_t ror_sl0:1; +#else + uint64_t ror_sl0:1; + uint64_t nsr_sl0:1; + uint64_t esr_sl0:2; + uint64_t ror_sl1:1; + uint64_t nsr_sl1:1; + uint64_t esr_sl1:2; + uint64_t reserved_8_15:8; + uint64_t iptr_o0:1; + uint64_t iptr_o1:1; + uint64_t reserved_18_23:6; + uint64_t o0_csrm:1; + uint64_t o1_csrm:1; + uint64_t reserved_26_27:2; + uint64_t o0_ro:1; + uint64_t o0_ns:1; + uint64_t o0_es:2; + uint64_t o1_ro:1; + uint64_t o1_ns:1; + uint64_t o1_es:2; + uint64_t reserved_36_43:8; + uint64_t p0_bmode:1; + uint64_t p1_bmode:1; + uint64_t reserved_46_63:18; +#endif } cn31xx; struct cvmx_npi_output_control_s cn38xx; struct cvmx_npi_output_control_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t p3_bmode:1; uint64_t p2_bmode:1; @@ -1176,8 +1973,49 @@ union cvmx_npi_output_control { uint64_t esr_sl0:2; uint64_t nsr_sl0:1; uint64_t ror_sl0:1; +#else + uint64_t ror_sl0:1; + uint64_t nsr_sl0:1; + uint64_t esr_sl0:2; + uint64_t ror_sl1:1; + uint64_t nsr_sl1:1; + uint64_t esr_sl1:2; + uint64_t ror_sl2:1; + uint64_t nsr_sl2:1; + uint64_t esr_sl2:2; + uint64_t ror_sl3:1; + uint64_t nsr_sl3:1; + uint64_t esr_sl3:2; + uint64_t iptr_o0:1; + uint64_t iptr_o1:1; + uint64_t iptr_o2:1; + uint64_t iptr_o3:1; + uint64_t reserved_20_23:4; + uint64_t o0_csrm:1; + uint64_t o1_csrm:1; + uint64_t o2_csrm:1; + uint64_t o3_csrm:1; + uint64_t o0_ro:1; + uint64_t o0_ns:1; + uint64_t o0_es:2; + uint64_t o1_ro:1; + uint64_t o1_ns:1; + uint64_t o1_es:2; + uint64_t o2_ro:1; + uint64_t o2_ns:1; + uint64_t o2_es:2; + uint64_t o3_ro:1; + uint64_t o3_ns:1; + uint64_t o3_es:2; + uint64_t p0_bmode:1; + uint64_t p1_bmode:1; + uint64_t p2_bmode:1; + uint64_t p3_bmode:1; + uint64_t reserved_48_63:16; +#endif } cn38xxp2; struct cvmx_npi_output_control_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t pkt_rr:1; uint64_t reserved_46_47:2; @@ -1203,6 +2041,33 @@ union cvmx_npi_output_control { uint64_t esr_sl0:2; uint64_t nsr_sl0:1; uint64_t ror_sl0:1; +#else + uint64_t ror_sl0:1; + uint64_t nsr_sl0:1; + uint64_t esr_sl0:2; + uint64_t ror_sl1:1; + uint64_t nsr_sl1:1; + uint64_t esr_sl1:2; + uint64_t reserved_8_15:8; + uint64_t iptr_o0:1; + uint64_t iptr_o1:1; + uint64_t reserved_18_23:6; + uint64_t o0_csrm:1; + uint64_t o1_csrm:1; + uint64_t reserved_26_27:2; + uint64_t o0_ro:1; + uint64_t o0_ns:1; + uint64_t o0_es:2; + uint64_t o1_ro:1; + uint64_t o1_ns:1; + uint64_t o1_es:2; + uint64_t reserved_36_43:8; + uint64_t p0_bmode:1; + uint64_t p1_bmode:1; + uint64_t reserved_46_47:2; + uint64_t pkt_rr:1; + uint64_t reserved_49_63:15; +#endif } cn50xx; struct cvmx_npi_output_control_s cn58xx; struct cvmx_npi_output_control_s cn58xxp1; @@ -1211,9 +2076,15 @@ union cvmx_npi_output_control { union cvmx_npi_px_dbpair_addr { uint64_t u64; struct cvmx_npi_px_dbpair_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_63_63:1; uint64_t state:2; uint64_t naddr:61; +#else + uint64_t naddr:61; + uint64_t state:2; + uint64_t reserved_63_63:1; +#endif } s; struct cvmx_npi_px_dbpair_addr_s cn30xx; struct cvmx_npi_px_dbpair_addr_s cn31xx; @@ -1227,8 +2098,13 @@ union cvmx_npi_px_dbpair_addr { union cvmx_npi_px_instr_addr { uint64_t u64; struct cvmx_npi_px_instr_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t state:3; uint64_t naddr:61; +#else + uint64_t naddr:61; + uint64_t state:3; +#endif } s; struct cvmx_npi_px_instr_addr_s cn30xx; struct cvmx_npi_px_instr_addr_s cn31xx; @@ -1242,9 +2118,15 @@ union cvmx_npi_px_instr_addr { union cvmx_npi_px_instr_cnts { uint64_t u64; struct cvmx_npi_px_instr_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t fcnt:6; uint64_t avail:32; +#else + uint64_t avail:32; + uint64_t fcnt:6; + uint64_t reserved_38_63:26; +#endif } s; struct cvmx_npi_px_instr_cnts_s cn30xx; struct cvmx_npi_px_instr_cnts_s cn31xx; @@ -1258,9 +2140,15 @@ union cvmx_npi_px_instr_cnts { union cvmx_npi_px_pair_cnts { uint64_t u64; struct cvmx_npi_px_pair_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t fcnt:5; uint64_t avail:32; +#else + uint64_t avail:32; + uint64_t fcnt:5; + uint64_t reserved_37_63:27; +#endif } s; struct cvmx_npi_px_pair_cnts_s cn30xx; struct cvmx_npi_px_pair_cnts_s cn31xx; @@ -1274,9 +2162,15 @@ union cvmx_npi_px_pair_cnts { union cvmx_npi_pci_burst_size { uint64_t u64; struct cvmx_npi_pci_burst_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t wr_brst:7; uint64_t rd_brst:7; +#else + uint64_t rd_brst:7; + uint64_t wr_brst:7; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_npi_pci_burst_size_s cn30xx; struct cvmx_npi_pci_burst_size_s cn31xx; @@ -1290,6 +2184,7 @@ union cvmx_npi_pci_burst_size { union cvmx_npi_pci_int_arb_cfg { uint64_t u64; struct cvmx_npi_pci_int_arb_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t hostmode:1; uint64_t pci_ovr:4; @@ -1297,12 +2192,28 @@ union cvmx_npi_pci_int_arb_cfg { uint64_t en:1; uint64_t park_mod:1; uint64_t park_dev:3; +#else + uint64_t park_dev:3; + uint64_t park_mod:1; + uint64_t en:1; + uint64_t reserved_5_7:3; + uint64_t pci_ovr:4; + uint64_t hostmode:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_npi_pci_int_arb_cfg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t en:1; uint64_t park_mod:1; uint64_t park_dev:3; +#else + uint64_t park_dev:3; + uint64_t park_mod:1; + uint64_t en:1; + uint64_t reserved_5_63:59; +#endif } cn30xx; struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx; struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx; @@ -1315,8 +2226,13 @@ union cvmx_npi_pci_int_arb_cfg { union cvmx_npi_pci_read_cmd { uint64_t u64; struct cvmx_npi_pci_read_cmd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t cmd_size:11; +#else + uint64_t cmd_size:11; + uint64_t reserved_11_63:53; +#endif } s; struct cvmx_npi_pci_read_cmd_s cn30xx; struct cvmx_npi_pci_read_cmd_s cn31xx; @@ -1330,6 +2246,7 @@ union cvmx_npi_pci_read_cmd { union cvmx_npi_port32_instr_hdr { uint64_t u64; struct cvmx_npi_port32_instr_hdr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t rsv_f:5; @@ -1343,6 +2260,21 @@ union cvmx_npi_port32_instr_hdr { uint64_t rsv_b:1; uint64_t skp_len:7; uint64_t rsv_a:6; +#else + uint64_t rsv_a:6; + uint64_t skp_len:7; + uint64_t rsv_b:1; + uint64_t par_mode:2; + uint64_t rsv_c:5; + uint64_t use_ihdr:1; + uint64_t rsv_d:6; + uint64_t rskp_len:7; + uint64_t rsv_e:1; + uint64_t rparmode:2; + uint64_t rsv_f:5; + uint64_t pbp:1; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_npi_port32_instr_hdr_s cn30xx; struct cvmx_npi_port32_instr_hdr_s cn31xx; @@ -1356,6 +2288,7 @@ union cvmx_npi_port32_instr_hdr { union cvmx_npi_port33_instr_hdr { uint64_t u64; struct cvmx_npi_port33_instr_hdr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t rsv_f:5; @@ -1369,6 +2302,21 @@ union cvmx_npi_port33_instr_hdr { uint64_t rsv_b:1; uint64_t skp_len:7; uint64_t rsv_a:6; +#else + uint64_t rsv_a:6; + uint64_t skp_len:7; + uint64_t rsv_b:1; + uint64_t par_mode:2; + uint64_t rsv_c:5; + uint64_t use_ihdr:1; + uint64_t rsv_d:6; + uint64_t rskp_len:7; + uint64_t rsv_e:1; + uint64_t rparmode:2; + uint64_t rsv_f:5; + uint64_t pbp:1; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_npi_port33_instr_hdr_s cn31xx; struct cvmx_npi_port33_instr_hdr_s cn38xx; @@ -1381,6 +2329,7 @@ union cvmx_npi_port33_instr_hdr { union cvmx_npi_port34_instr_hdr { uint64_t u64; struct cvmx_npi_port34_instr_hdr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t rsv_f:5; @@ -1394,6 +2343,21 @@ union cvmx_npi_port34_instr_hdr { uint64_t rsv_b:1; uint64_t skp_len:7; uint64_t rsv_a:6; +#else + uint64_t rsv_a:6; + uint64_t skp_len:7; + uint64_t rsv_b:1; + uint64_t par_mode:2; + uint64_t rsv_c:5; + uint64_t use_ihdr:1; + uint64_t rsv_d:6; + uint64_t rskp_len:7; + uint64_t rsv_e:1; + uint64_t rparmode:2; + uint64_t rsv_f:5; + uint64_t pbp:1; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_npi_port34_instr_hdr_s cn38xx; struct cvmx_npi_port34_instr_hdr_s cn38xxp2; @@ -1404,6 +2368,7 @@ union cvmx_npi_port34_instr_hdr { union cvmx_npi_port35_instr_hdr { uint64_t u64; struct cvmx_npi_port35_instr_hdr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t rsv_f:5; @@ -1417,6 +2382,21 @@ union cvmx_npi_port35_instr_hdr { uint64_t rsv_b:1; uint64_t skp_len:7; uint64_t rsv_a:6; +#else + uint64_t rsv_a:6; + uint64_t skp_len:7; + uint64_t rsv_b:1; + uint64_t par_mode:2; + uint64_t rsv_c:5; + uint64_t use_ihdr:1; + uint64_t rsv_d:6; + uint64_t rskp_len:7; + uint64_t rsv_e:1; + uint64_t rparmode:2; + uint64_t rsv_f:5; + uint64_t pbp:1; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_npi_port35_instr_hdr_s cn38xx; struct cvmx_npi_port35_instr_hdr_s cn38xxp2; @@ -1427,9 +2407,15 @@ union cvmx_npi_port35_instr_hdr { union cvmx_npi_port_bp_control { uint64_t u64; struct cvmx_npi_port_bp_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t bp_on:4; uint64_t enb:4; +#else + uint64_t enb:4; + uint64_t bp_on:4; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_npi_port_bp_control_s cn30xx; struct cvmx_npi_port_bp_control_s cn31xx; @@ -1443,6 +2429,7 @@ union cvmx_npi_port_bp_control { union cvmx_npi_rsl_int_blocks { uint64_t u64; struct cvmx_npi_rsl_int_blocks_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rint_31:1; uint64_t iob:1; @@ -1474,8 +2461,42 @@ union cvmx_npi_rsl_int_blocks { uint64_t gmx1:1; uint64_t gmx0:1; uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t gmx1:1; + uint64_t npi:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t rint_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t reserved_13_14:2; + uint64_t rint_15:1; + uint64_t l2c:1; + uint64_t lmc:1; + uint64_t spx0:1; + uint64_t spx1:1; + uint64_t pip:1; + uint64_t rint_21:1; + uint64_t asx0:1; + uint64_t asx1:1; + uint64_t rint_24:1; + uint64_t rint_25:1; + uint64_t rint_26:1; + uint64_t rint_27:1; + uint64_t reserved_28_29:2; + uint64_t iob:1; + uint64_t rint_31:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npi_rsl_int_blocks_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rint_31:1; uint64_t iob:1; @@ -1509,9 +2530,45 @@ union cvmx_npi_rsl_int_blocks { uint64_t gmx1:1; uint64_t gmx0:1; uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t gmx1:1; + uint64_t npi:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t rint_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t usb:1; + uint64_t rint_14:1; + uint64_t rint_15:1; + uint64_t l2c:1; + uint64_t lmc:1; + uint64_t spx0:1; + uint64_t spx1:1; + uint64_t pip:1; + uint64_t rint_21:1; + uint64_t asx0:1; + uint64_t asx1:1; + uint64_t rint_24:1; + uint64_t rint_25:1; + uint64_t rint_26:1; + uint64_t rint_27:1; + uint64_t rint_28:1; + uint64_t rint_29:1; + uint64_t iob:1; + uint64_t rint_31:1; + uint64_t reserved_32_63:32; +#endif } cn30xx; struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx; struct cvmx_npi_rsl_int_blocks_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rint_31:1; uint64_t iob:1; @@ -1545,9 +2602,45 @@ union cvmx_npi_rsl_int_blocks { uint64_t gmx1:1; uint64_t gmx0:1; uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t gmx1:1; + uint64_t npi:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t rint_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t rint_13:1; + uint64_t rint_14:1; + uint64_t rint_15:1; + uint64_t l2c:1; + uint64_t lmc:1; + uint64_t spx0:1; + uint64_t spx1:1; + uint64_t pip:1; + uint64_t rint_21:1; + uint64_t asx0:1; + uint64_t asx1:1; + uint64_t rint_24:1; + uint64_t rint_25:1; + uint64_t rint_26:1; + uint64_t rint_27:1; + uint64_t rint_28:1; + uint64_t rint_29:1; + uint64_t iob:1; + uint64_t rint_31:1; + uint64_t reserved_32_63:32; +#endif } cn38xx; struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2; struct cvmx_npi_rsl_int_blocks_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t iob:1; uint64_t lmc1:1; @@ -1577,6 +2670,37 @@ union cvmx_npi_rsl_int_blocks { uint64_t gmx1:1; uint64_t gmx0:1; uint64_t mio:1; +#else + uint64_t mio:1; + uint64_t gmx0:1; + uint64_t gmx1:1; + uint64_t npi:1; + uint64_t key:1; + uint64_t fpa:1; + uint64_t dfa:1; + uint64_t zip:1; + uint64_t reserved_8_8:1; + uint64_t ipd:1; + uint64_t pko:1; + uint64_t tim:1; + uint64_t pow:1; + uint64_t usb:1; + uint64_t rad:1; + uint64_t reserved_15_15:1; + uint64_t l2c:1; + uint64_t lmc:1; + uint64_t spx0:1; + uint64_t spx1:1; + uint64_t pip:1; + uint64_t reserved_21_21:1; + uint64_t asx0:1; + uint64_t asx1:1; + uint64_t reserved_24_27:4; + uint64_t agl:1; + uint64_t lmc1:1; + uint64_t iob:1; + uint64_t reserved_31_63:33; +#endif } cn50xx; struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx; struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1; @@ -1585,8 +2709,13 @@ union cvmx_npi_rsl_int_blocks { union cvmx_npi_size_inputx { uint64_t u64; struct cvmx_npi_size_inputx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t size:32; +#else + uint64_t size:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npi_size_inputx_s cn30xx; struct cvmx_npi_size_inputx_s cn31xx; @@ -1600,8 +2729,13 @@ union cvmx_npi_size_inputx { union cvmx_npi_win_read_to { uint64_t u64; struct cvmx_npi_win_read_to_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t time:32; +#else + uint64_t time:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_npi_win_read_to_s cn30xx; struct cvmx_npi_win_read_to_s cn31xx; diff --git a/arch/mips/include/asm/octeon/cvmx-pci-defs.h b/arch/mips/include/asm/octeon/cvmx-pci-defs.h index 6ff6d9d357b..25d603f1829 100644 --- a/arch/mips/include/asm/octeon/cvmx-pci-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pci-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -117,11 +117,19 @@ union cvmx_pci_bar1_indexx { uint32_t u32; struct cvmx_pci_bar1_indexx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_18_31:14; uint32_t addr_idx:14; uint32_t ca:1; uint32_t end_swp:2; uint32_t addr_v:1; +#else + uint32_t addr_v:1; + uint32_t end_swp:2; + uint32_t ca:1; + uint32_t addr_idx:14; + uint32_t reserved_18_31:14; +#endif } s; struct cvmx_pci_bar1_indexx_s cn30xx; struct cvmx_pci_bar1_indexx_s cn31xx; @@ -135,6 +143,7 @@ union cvmx_pci_bar1_indexx { union cvmx_pci_bist_reg { uint64_t u64; struct cvmx_pci_bist_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t rsp_bs:1; uint64_t dma0_bs:1; @@ -146,6 +155,19 @@ union cvmx_pci_bist_reg { uint64_t csr2n_bs:1; uint64_t dat2n_bs:1; uint64_t dbg2n_bs:1; +#else + uint64_t dbg2n_bs:1; + uint64_t dat2n_bs:1; + uint64_t csr2n_bs:1; + uint64_t rsp2p_bs:1; + uint64_t csrr_bs:1; + uint64_t csr2p_bs:1; + uint64_t cmd_bs:1; + uint64_t cmd0_bs:1; + uint64_t dma0_bs:1; + uint64_t rsp_bs:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_pci_bist_reg_s cn50xx; }; @@ -153,8 +175,13 @@ union cvmx_pci_bist_reg { union cvmx_pci_cfg00 { uint32_t u32; struct cvmx_pci_cfg00_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t devid:16; uint32_t vendid:16; +#else + uint32_t vendid:16; + uint32_t devid:16; +#endif } s; struct cvmx_pci_cfg00_s cn30xx; struct cvmx_pci_cfg00_s cn31xx; @@ -168,6 +195,7 @@ union cvmx_pci_cfg00 { union cvmx_pci_cfg01 { uint32_t u32; struct cvmx_pci_cfg01_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t dpe:1; uint32_t sse:1; uint32_t rma:1; @@ -192,6 +220,32 @@ union cvmx_pci_cfg01 { uint32_t me:1; uint32_t msae:1; uint32_t isae:1; +#else + uint32_t isae:1; + uint32_t msae:1; + uint32_t me:1; + uint32_t scse:1; + uint32_t mwice:1; + uint32_t vps:1; + uint32_t pee:1; + uint32_t ads:1; + uint32_t see:1; + uint32_t fbbe:1; + uint32_t i_dis:1; + uint32_t reserved_11_18:8; + uint32_t i_stat:1; + uint32_t cle:1; + uint32_t m66:1; + uint32_t reserved_22_22:1; + uint32_t fbb:1; + uint32_t mdpe:1; + uint32_t devt:2; + uint32_t sta:1; + uint32_t rta:1; + uint32_t rma:1; + uint32_t sse:1; + uint32_t dpe:1; +#endif } s; struct cvmx_pci_cfg01_s cn30xx; struct cvmx_pci_cfg01_s cn31xx; @@ -205,8 +259,13 @@ union cvmx_pci_cfg01 { union cvmx_pci_cfg02 { uint32_t u32; struct cvmx_pci_cfg02_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t cc:24; uint32_t rid:8; +#else + uint32_t rid:8; + uint32_t cc:24; +#endif } s; struct cvmx_pci_cfg02_s cn30xx; struct cvmx_pci_cfg02_s cn31xx; @@ -220,6 +279,7 @@ union cvmx_pci_cfg02 { union cvmx_pci_cfg03 { uint32_t u32; struct cvmx_pci_cfg03_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t bcap:1; uint32_t brb:1; uint32_t reserved_28_29:2; @@ -227,6 +287,15 @@ union cvmx_pci_cfg03 { uint32_t ht:8; uint32_t lt:8; uint32_t cls:8; +#else + uint32_t cls:8; + uint32_t lt:8; + uint32_t ht:8; + uint32_t bcod:4; + uint32_t reserved_28_29:2; + uint32_t brb:1; + uint32_t bcap:1; +#endif } s; struct cvmx_pci_cfg03_s cn30xx; struct cvmx_pci_cfg03_s cn31xx; @@ -240,11 +309,19 @@ union cvmx_pci_cfg03 { union cvmx_pci_cfg04 { uint32_t u32; struct cvmx_pci_cfg04_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t lbase:20; uint32_t lbasez:8; uint32_t pf:1; uint32_t typ:2; uint32_t mspc:1; +#else + uint32_t mspc:1; + uint32_t typ:2; + uint32_t pf:1; + uint32_t lbasez:8; + uint32_t lbase:20; +#endif } s; struct cvmx_pci_cfg04_s cn30xx; struct cvmx_pci_cfg04_s cn31xx; @@ -258,7 +335,11 @@ union cvmx_pci_cfg04 { union cvmx_pci_cfg05 { uint32_t u32; struct cvmx_pci_cfg05_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t hbase:32; +#else uint32_t hbase:32; +#endif } s; struct cvmx_pci_cfg05_s cn30xx; struct cvmx_pci_cfg05_s cn31xx; @@ -272,11 +353,19 @@ union cvmx_pci_cfg05 { union cvmx_pci_cfg06 { uint32_t u32; struct cvmx_pci_cfg06_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t lbase:5; uint32_t lbasez:23; uint32_t pf:1; uint32_t typ:2; uint32_t mspc:1; +#else + uint32_t mspc:1; + uint32_t typ:2; + uint32_t pf:1; + uint32_t lbasez:23; + uint32_t lbase:5; +#endif } s; struct cvmx_pci_cfg06_s cn30xx; struct cvmx_pci_cfg06_s cn31xx; @@ -290,7 +379,11 @@ union cvmx_pci_cfg06 { union cvmx_pci_cfg07 { uint32_t u32; struct cvmx_pci_cfg07_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t hbase:32; +#else uint32_t hbase:32; +#endif } s; struct cvmx_pci_cfg07_s cn30xx; struct cvmx_pci_cfg07_s cn31xx; @@ -304,10 +397,17 @@ union cvmx_pci_cfg07 { union cvmx_pci_cfg08 { uint32_t u32; struct cvmx_pci_cfg08_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t lbasez:28; uint32_t pf:1; uint32_t typ:2; uint32_t mspc:1; +#else + uint32_t mspc:1; + uint32_t typ:2; + uint32_t pf:1; + uint32_t lbasez:28; +#endif } s; struct cvmx_pci_cfg08_s cn30xx; struct cvmx_pci_cfg08_s cn31xx; @@ -321,8 +421,13 @@ union cvmx_pci_cfg08 { union cvmx_pci_cfg09 { uint32_t u32; struct cvmx_pci_cfg09_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t hbase:25; uint32_t hbasez:7; +#else + uint32_t hbasez:7; + uint32_t hbase:25; +#endif } s; struct cvmx_pci_cfg09_s cn30xx; struct cvmx_pci_cfg09_s cn31xx; @@ -336,7 +441,11 @@ union cvmx_pci_cfg09 { union cvmx_pci_cfg10 { uint32_t u32; struct cvmx_pci_cfg10_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t cisp:32; +#else uint32_t cisp:32; +#endif } s; struct cvmx_pci_cfg10_s cn30xx; struct cvmx_pci_cfg10_s cn31xx; @@ -350,8 +459,13 @@ union cvmx_pci_cfg10 { union cvmx_pci_cfg11 { uint32_t u32; struct cvmx_pci_cfg11_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t ssid:16; uint32_t ssvid:16; +#else + uint32_t ssvid:16; + uint32_t ssid:16; +#endif } s; struct cvmx_pci_cfg11_s cn30xx; struct cvmx_pci_cfg11_s cn31xx; @@ -365,10 +479,17 @@ union cvmx_pci_cfg11 { union cvmx_pci_cfg12 { uint32_t u32; struct cvmx_pci_cfg12_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t erbar:16; uint32_t erbarz:5; uint32_t reserved_1_10:10; uint32_t erbar_en:1; +#else + uint32_t erbar_en:1; + uint32_t reserved_1_10:10; + uint32_t erbarz:5; + uint32_t erbar:16; +#endif } s; struct cvmx_pci_cfg12_s cn30xx; struct cvmx_pci_cfg12_s cn31xx; @@ -382,8 +503,13 @@ union cvmx_pci_cfg12 { union cvmx_pci_cfg13 { uint32_t u32; struct cvmx_pci_cfg13_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_8_31:24; uint32_t cp:8; +#else + uint32_t cp:8; + uint32_t reserved_8_31:24; +#endif } s; struct cvmx_pci_cfg13_s cn30xx; struct cvmx_pci_cfg13_s cn31xx; @@ -397,10 +523,17 @@ union cvmx_pci_cfg13 { union cvmx_pci_cfg15 { uint32_t u32; struct cvmx_pci_cfg15_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t ml:8; uint32_t mg:8; uint32_t inta:8; uint32_t il:8; +#else + uint32_t il:8; + uint32_t inta:8; + uint32_t mg:8; + uint32_t ml:8; +#endif } s; struct cvmx_pci_cfg15_s cn30xx; struct cvmx_pci_cfg15_s cn31xx; @@ -414,6 +547,7 @@ union cvmx_pci_cfg15 { union cvmx_pci_cfg16 { uint32_t u32; struct cvmx_pci_cfg16_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t trdnpr:1; uint32_t trdard:1; uint32_t rdsati:1; @@ -430,6 +564,24 @@ union cvmx_pci_cfg16 { uint32_t reserved_2_2:1; uint32_t tswc:1; uint32_t mltd:1; +#else + uint32_t mltd:1; + uint32_t tswc:1; + uint32_t reserved_2_2:1; + uint32_t dppmr:1; + uint32_t pbe:12; + uint32_t tilt:4; + uint32_t tslte:3; + uint32_t tmae:1; + uint32_t twtae:1; + uint32_t twsen:1; + uint32_t twsei:1; + uint32_t trtae:1; + uint32_t trdrs:1; + uint32_t rdsati:1; + uint32_t trdard:1; + uint32_t trdnpr:1; +#endif } s; struct cvmx_pci_cfg16_s cn30xx; struct cvmx_pci_cfg16_s cn31xx; @@ -443,7 +595,11 @@ union cvmx_pci_cfg16 { union cvmx_pci_cfg17 { uint32_t u32; struct cvmx_pci_cfg17_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t tscme:32; +#else + uint32_t tscme:32; +#endif } s; struct cvmx_pci_cfg17_s cn30xx; struct cvmx_pci_cfg17_s cn31xx; @@ -457,7 +613,11 @@ union cvmx_pci_cfg17 { union cvmx_pci_cfg18 { uint32_t u32; struct cvmx_pci_cfg18_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t tdsrps:32; +#else uint32_t tdsrps:32; +#endif } s; struct cvmx_pci_cfg18_s cn30xx; struct cvmx_pci_cfg18_s cn31xx; @@ -471,6 +631,7 @@ union cvmx_pci_cfg18 { union cvmx_pci_cfg19 { uint32_t u32; struct cvmx_pci_cfg19_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t mrbcm:1; uint32_t mrbci:1; uint32_t mdwe:1; @@ -489,6 +650,26 @@ union cvmx_pci_cfg19 { uint32_t reserved_6_6:1; uint32_t tidomc:1; uint32_t tdomc:5; +#else + uint32_t tdomc:5; + uint32_t tidomc:1; + uint32_t reserved_6_6:1; + uint32_t tibde:1; + uint32_t tibcd:1; + uint32_t reserved_9_10:2; + uint32_t tmapes:1; + uint32_t tmdpes:1; + uint32_t tmse:1; + uint32_t tmei:1; + uint32_t teci:1; + uint32_t tmes:8; + uint32_t mdrrmc:3; + uint32_t mdrimc:1; + uint32_t mdre:1; + uint32_t mdwe:1; + uint32_t mrbci:1; + uint32_t mrbcm:1; +#endif } s; struct cvmx_pci_cfg19_s cn30xx; struct cvmx_pci_cfg19_s cn31xx; @@ -502,7 +683,11 @@ union cvmx_pci_cfg19 { union cvmx_pci_cfg20 { uint32_t u32; struct cvmx_pci_cfg20_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t mdsp:32; +#else + uint32_t mdsp:32; +#endif } s; struct cvmx_pci_cfg20_s cn30xx; struct cvmx_pci_cfg20_s cn31xx; @@ -516,7 +701,11 @@ union cvmx_pci_cfg20 { union cvmx_pci_cfg21 { uint32_t u32; struct cvmx_pci_cfg21_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t scmre:32; +#else uint32_t scmre:32; +#endif } s; struct cvmx_pci_cfg21_s cn30xx; struct cvmx_pci_cfg21_s cn31xx; @@ -530,6 +719,7 @@ union cvmx_pci_cfg21 { union cvmx_pci_cfg22 { uint32_t u32; struct cvmx_pci_cfg22_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t mac:7; uint32_t reserved_19_24:6; uint32_t flush:1; @@ -537,6 +727,15 @@ union cvmx_pci_cfg22 { uint32_t mtta:1; uint32_t mrv:8; uint32_t mttv:8; +#else + uint32_t mttv:8; + uint32_t mrv:8; + uint32_t mtta:1; + uint32_t mra:1; + uint32_t flush:1; + uint32_t reserved_19_24:6; + uint32_t mac:7; +#endif } s; struct cvmx_pci_cfg22_s cn30xx; struct cvmx_pci_cfg22_s cn31xx; @@ -550,6 +749,7 @@ union cvmx_pci_cfg22 { union cvmx_pci_cfg56 { uint32_t u32; struct cvmx_pci_cfg56_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_23_31:9; uint32_t most:3; uint32_t mmbc:2; @@ -557,6 +757,15 @@ union cvmx_pci_cfg56 { uint32_t dpere:1; uint32_t ncp:8; uint32_t pxcid:8; +#else + uint32_t pxcid:8; + uint32_t ncp:8; + uint32_t dpere:1; + uint32_t roe:1; + uint32_t mmbc:2; + uint32_t most:3; + uint32_t reserved_23_31:9; +#endif } s; struct cvmx_pci_cfg56_s cn30xx; struct cvmx_pci_cfg56_s cn31xx; @@ -570,6 +779,7 @@ union cvmx_pci_cfg56 { union cvmx_pci_cfg57 { uint32_t u32; struct cvmx_pci_cfg57_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_30_31:2; uint32_t scemr:1; uint32_t mcrsd:3; @@ -583,6 +793,21 @@ union cvmx_pci_cfg57 { uint32_t bn:8; uint32_t dn:5; uint32_t fn:3; +#else + uint32_t fn:3; + uint32_t dn:5; + uint32_t bn:8; + uint32_t w64:1; + uint32_t m133:1; + uint32_t scd:1; + uint32_t usc:1; + uint32_t dc:1; + uint32_t mmrbcd:2; + uint32_t mostd:3; + uint32_t mcrsd:3; + uint32_t scemr:1; + uint32_t reserved_30_31:2; +#endif } s; struct cvmx_pci_cfg57_s cn30xx; struct cvmx_pci_cfg57_s cn31xx; @@ -596,6 +821,7 @@ union cvmx_pci_cfg57 { union cvmx_pci_cfg58 { uint32_t u32; struct cvmx_pci_cfg58_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pmes:5; uint32_t d2s:1; uint32_t d1s:1; @@ -606,6 +832,18 @@ union cvmx_pci_cfg58 { uint32_t pcimiv:3; uint32_t ncp:8; uint32_t pmcid:8; +#else + uint32_t pmcid:8; + uint32_t ncp:8; + uint32_t pcimiv:3; + uint32_t pmec:1; + uint32_t reserved_20_20:1; + uint32_t dsi:1; + uint32_t auxc:3; + uint32_t d1s:1; + uint32_t d2s:1; + uint32_t pmes:5; +#endif } s; struct cvmx_pci_cfg58_s cn30xx; struct cvmx_pci_cfg58_s cn31xx; @@ -619,6 +857,7 @@ union cvmx_pci_cfg58 { union cvmx_pci_cfg59 { uint32_t u32; struct cvmx_pci_cfg59_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pmdia:8; uint32_t bpccen:1; uint32_t bd3h:1; @@ -629,6 +868,18 @@ union cvmx_pci_cfg59 { uint32_t pmeens:1; uint32_t reserved_2_7:6; uint32_t ps:2; +#else + uint32_t ps:2; + uint32_t reserved_2_7:6; + uint32_t pmeens:1; + uint32_t pmds:4; + uint32_t pmedsia:2; + uint32_t pmess:1; + uint32_t reserved_16_21:6; + uint32_t bd3h:1; + uint32_t bpccen:1; + uint32_t pmdia:8; +#endif } s; struct cvmx_pci_cfg59_s cn30xx; struct cvmx_pci_cfg59_s cn31xx; @@ -642,6 +893,7 @@ union cvmx_pci_cfg59 { union cvmx_pci_cfg60 { uint32_t u32; struct cvmx_pci_cfg60_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_24_31:8; uint32_t m64:1; uint32_t mme:3; @@ -649,6 +901,15 @@ union cvmx_pci_cfg60 { uint32_t msien:1; uint32_t ncp:8; uint32_t msicid:8; +#else + uint32_t msicid:8; + uint32_t ncp:8; + uint32_t msien:1; + uint32_t mmc:3; + uint32_t mme:3; + uint32_t m64:1; + uint32_t reserved_24_31:8; +#endif } s; struct cvmx_pci_cfg60_s cn30xx; struct cvmx_pci_cfg60_s cn31xx; @@ -662,8 +923,13 @@ union cvmx_pci_cfg60 { union cvmx_pci_cfg61 { uint32_t u32; struct cvmx_pci_cfg61_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t msi31t2:30; uint32_t reserved_0_1:2; +#else + uint32_t reserved_0_1:2; + uint32_t msi31t2:30; +#endif } s; struct cvmx_pci_cfg61_s cn30xx; struct cvmx_pci_cfg61_s cn31xx; @@ -677,7 +943,11 @@ union cvmx_pci_cfg61 { union cvmx_pci_cfg62 { uint32_t u32; struct cvmx_pci_cfg62_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t msi:32; +#else + uint32_t msi:32; +#endif } s; struct cvmx_pci_cfg62_s cn30xx; struct cvmx_pci_cfg62_s cn31xx; @@ -691,8 +961,13 @@ union cvmx_pci_cfg62 { union cvmx_pci_cfg63 { uint32_t u32; struct cvmx_pci_cfg63_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_16_31:16; uint32_t msimd:16; +#else + uint32_t msimd:16; + uint32_t reserved_16_31:16; +#endif } s; struct cvmx_pci_cfg63_s cn30xx; struct cvmx_pci_cfg63_s cn31xx; @@ -706,12 +981,21 @@ union cvmx_pci_cfg63 { union cvmx_pci_cnt_reg { uint64_t u64; struct cvmx_pci_cnt_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t hm_pcix:1; uint64_t hm_speed:2; uint64_t ap_pcix:1; uint64_t ap_speed:2; uint64_t pcicnt:32; +#else + uint64_t pcicnt:32; + uint64_t ap_speed:2; + uint64_t ap_pcix:1; + uint64_t hm_speed:2; + uint64_t hm_pcix:1; + uint64_t reserved_38_63:26; +#endif } s; struct cvmx_pci_cnt_reg_s cn50xx; struct cvmx_pci_cnt_reg_s cn58xx; @@ -721,6 +1005,7 @@ union cvmx_pci_cnt_reg { union cvmx_pci_ctl_status_2 { uint32_t u32; struct cvmx_pci_ctl_status_2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_29_31:3; uint32_t bb1_hole:3; uint32_t bb1_siz:1; @@ -743,9 +1028,34 @@ union cvmx_pci_ctl_status_2 { uint32_t bar2_enb:1; uint32_t bar2_esx:2; uint32_t bar2_cax:1; +#else + uint32_t bar2_cax:1; + uint32_t bar2_esx:2; + uint32_t bar2_enb:1; + uint32_t tsr_hwm:3; + uint32_t pmo_fpc:3; + uint32_t pmo_amod:1; + uint32_t b12_bist:1; + uint32_t ap_64ad:1; + uint32_t ap_pcix:1; + uint32_t reserved_14_14:1; + uint32_t en_wfilt:1; + uint32_t scm:1; + uint32_t scmtyp:1; + uint32_t bar2pres:1; + uint32_t erst_n:1; + uint32_t bb0:1; + uint32_t bb1:1; + uint32_t bb_es:2; + uint32_t bb_ca:1; + uint32_t bb1_siz:1; + uint32_t bb1_hole:3; + uint32_t reserved_29_31:3; +#endif } s; struct cvmx_pci_ctl_status_2_s cn30xx; struct cvmx_pci_ctl_status_2_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_20_31:12; uint32_t erst_n:1; uint32_t bar2pres:1; @@ -762,6 +1072,24 @@ union cvmx_pci_ctl_status_2 { uint32_t bar2_enb:1; uint32_t bar2_esx:2; uint32_t bar2_cax:1; +#else + uint32_t bar2_cax:1; + uint32_t bar2_esx:2; + uint32_t bar2_enb:1; + uint32_t tsr_hwm:3; + uint32_t pmo_fpc:3; + uint32_t pmo_amod:1; + uint32_t b12_bist:1; + uint32_t ap_64ad:1; + uint32_t ap_pcix:1; + uint32_t reserved_14_14:1; + uint32_t en_wfilt:1; + uint32_t scm:1; + uint32_t scmtyp:1; + uint32_t bar2pres:1; + uint32_t erst_n:1; + uint32_t reserved_20_31:12; +#endif } cn31xx; struct cvmx_pci_ctl_status_2_s cn38xx; struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2; @@ -773,8 +1101,13 @@ union cvmx_pci_ctl_status_2 { union cvmx_pci_dbellx { uint32_t u32; struct cvmx_pci_dbellx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_16_31:16; uint32_t inc_val:16; +#else + uint32_t inc_val:16; + uint32_t reserved_16_31:16; +#endif } s; struct cvmx_pci_dbellx_s cn30xx; struct cvmx_pci_dbellx_s cn31xx; @@ -788,7 +1121,11 @@ union cvmx_pci_dbellx { union cvmx_pci_dma_cntx { uint32_t u32; struct cvmx_pci_dma_cntx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t dma_cnt:32; +#else uint32_t dma_cnt:32; +#endif } s; struct cvmx_pci_dma_cntx_s cn30xx; struct cvmx_pci_dma_cntx_s cn31xx; @@ -802,7 +1139,11 @@ union cvmx_pci_dma_cntx { union cvmx_pci_dma_int_levx { uint32_t u32; struct cvmx_pci_dma_int_levx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pkt_cnt:32; +#else + uint32_t pkt_cnt:32; +#endif } s; struct cvmx_pci_dma_int_levx_s cn30xx; struct cvmx_pci_dma_int_levx_s cn31xx; @@ -816,7 +1157,11 @@ union cvmx_pci_dma_int_levx { union cvmx_pci_dma_timex { uint32_t u32; struct cvmx_pci_dma_timex_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t dma_time:32; +#else uint32_t dma_time:32; +#endif } s; struct cvmx_pci_dma_timex_s cn30xx; struct cvmx_pci_dma_timex_s cn31xx; @@ -830,7 +1175,11 @@ union cvmx_pci_dma_timex { union cvmx_pci_instr_countx { uint32_t u32; struct cvmx_pci_instr_countx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t icnt:32; +#else uint32_t icnt:32; +#endif } s; struct cvmx_pci_instr_countx_s cn30xx; struct cvmx_pci_instr_countx_s cn31xx; @@ -844,6 +1193,7 @@ union cvmx_pci_instr_countx { union cvmx_pci_int_enb { uint64_t u64; struct cvmx_pci_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -879,8 +1229,46 @@ union cvmx_pci_int_enb { uint64_t imr_wtto:1; uint64_t imr_wabt:1; uint64_t itr_wabt:1; +#else + uint64_t itr_wabt:1; + uint64_t imr_wabt:1; + uint64_t imr_wtto:1; + uint64_t itr_abt:1; + uint64_t imr_abt:1; + uint64_t imr_tto:1; + uint64_t imsi_per:1; + uint64_t imsi_tabt:1; + uint64_t imsi_mabt:1; + uint64_t imsc_msg:1; + uint64_t itsr_abt:1; + uint64_t iserr:1; + uint64_t iaperr:1; + uint64_t idperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t irsl_int:1; + uint64_t ipcnt0:1; + uint64_t ipcnt1:1; + uint64_t ipcnt2:1; + uint64_t ipcnt3:1; + uint64_t iptime0:1; + uint64_t iptime1:1; + uint64_t iptime2:1; + uint64_t iptime3:1; + uint64_t idcnt0:1; + uint64_t idcnt1:1; + uint64_t idtime0:1; + uint64_t idtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_pci_int_enb_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -912,8 +1300,42 @@ union cvmx_pci_int_enb { uint64_t imr_wtto:1; uint64_t imr_wabt:1; uint64_t itr_wabt:1; +#else + uint64_t itr_wabt:1; + uint64_t imr_wabt:1; + uint64_t imr_wtto:1; + uint64_t itr_abt:1; + uint64_t imr_abt:1; + uint64_t imr_tto:1; + uint64_t imsi_per:1; + uint64_t imsi_tabt:1; + uint64_t imsi_mabt:1; + uint64_t imsc_msg:1; + uint64_t itsr_abt:1; + uint64_t iserr:1; + uint64_t iaperr:1; + uint64_t idperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t irsl_int:1; + uint64_t ipcnt0:1; + uint64_t reserved_18_20:3; + uint64_t iptime0:1; + uint64_t reserved_22_24:3; + uint64_t idcnt0:1; + uint64_t idcnt1:1; + uint64_t idtime0:1; + uint64_t idtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } cn30xx; struct cvmx_pci_int_enb_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -947,6 +1369,41 @@ union cvmx_pci_int_enb { uint64_t imr_wtto:1; uint64_t imr_wabt:1; uint64_t itr_wabt:1; +#else + uint64_t itr_wabt:1; + uint64_t imr_wabt:1; + uint64_t imr_wtto:1; + uint64_t itr_abt:1; + uint64_t imr_abt:1; + uint64_t imr_tto:1; + uint64_t imsi_per:1; + uint64_t imsi_tabt:1; + uint64_t imsi_mabt:1; + uint64_t imsc_msg:1; + uint64_t itsr_abt:1; + uint64_t iserr:1; + uint64_t iaperr:1; + uint64_t idperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t irsl_int:1; + uint64_t ipcnt0:1; + uint64_t ipcnt1:1; + uint64_t reserved_19_20:2; + uint64_t iptime0:1; + uint64_t iptime1:1; + uint64_t reserved_23_24:2; + uint64_t idcnt0:1; + uint64_t idcnt1:1; + uint64_t idtime0:1; + uint64_t idtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } cn31xx; struct cvmx_pci_int_enb_s cn38xx; struct cvmx_pci_int_enb_s cn38xxp2; @@ -958,6 +1415,7 @@ union cvmx_pci_int_enb { union cvmx_pci_int_enb2 { uint64_t u64; struct cvmx_pci_int_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -993,8 +1451,46 @@ union cvmx_pci_int_enb2 { uint64_t rmr_wtto:1; uint64_t rmr_wabt:1; uint64_t rtr_wabt:1; +#else + uint64_t rtr_wabt:1; + uint64_t rmr_wabt:1; + uint64_t rmr_wtto:1; + uint64_t rtr_abt:1; + uint64_t rmr_abt:1; + uint64_t rmr_tto:1; + uint64_t rmsi_per:1; + uint64_t rmsi_tabt:1; + uint64_t rmsi_mabt:1; + uint64_t rmsc_msg:1; + uint64_t rtsr_abt:1; + uint64_t rserr:1; + uint64_t raperr:1; + uint64_t rdperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rrsl_int:1; + uint64_t rpcnt0:1; + uint64_t rpcnt1:1; + uint64_t rpcnt2:1; + uint64_t rpcnt3:1; + uint64_t rptime0:1; + uint64_t rptime1:1; + uint64_t rptime2:1; + uint64_t rptime3:1; + uint64_t rdcnt0:1; + uint64_t rdcnt1:1; + uint64_t rdtime0:1; + uint64_t rdtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_pci_int_enb2_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1026,8 +1522,42 @@ union cvmx_pci_int_enb2 { uint64_t rmr_wtto:1; uint64_t rmr_wabt:1; uint64_t rtr_wabt:1; +#else + uint64_t rtr_wabt:1; + uint64_t rmr_wabt:1; + uint64_t rmr_wtto:1; + uint64_t rtr_abt:1; + uint64_t rmr_abt:1; + uint64_t rmr_tto:1; + uint64_t rmsi_per:1; + uint64_t rmsi_tabt:1; + uint64_t rmsi_mabt:1; + uint64_t rmsc_msg:1; + uint64_t rtsr_abt:1; + uint64_t rserr:1; + uint64_t raperr:1; + uint64_t rdperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rrsl_int:1; + uint64_t rpcnt0:1; + uint64_t reserved_18_20:3; + uint64_t rptime0:1; + uint64_t reserved_22_24:3; + uint64_t rdcnt0:1; + uint64_t rdcnt1:1; + uint64_t rdtime0:1; + uint64_t rdtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } cn30xx; struct cvmx_pci_int_enb2_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1061,6 +1591,41 @@ union cvmx_pci_int_enb2 { uint64_t rmr_wtto:1; uint64_t rmr_wabt:1; uint64_t rtr_wabt:1; +#else + uint64_t rtr_wabt:1; + uint64_t rmr_wabt:1; + uint64_t rmr_wtto:1; + uint64_t rtr_abt:1; + uint64_t rmr_abt:1; + uint64_t rmr_tto:1; + uint64_t rmsi_per:1; + uint64_t rmsi_tabt:1; + uint64_t rmsi_mabt:1; + uint64_t rmsc_msg:1; + uint64_t rtsr_abt:1; + uint64_t rserr:1; + uint64_t raperr:1; + uint64_t rdperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rrsl_int:1; + uint64_t rpcnt0:1; + uint64_t rpcnt1:1; + uint64_t reserved_19_20:2; + uint64_t rptime0:1; + uint64_t rptime1:1; + uint64_t reserved_23_24:2; + uint64_t rdcnt0:1; + uint64_t rdcnt1:1; + uint64_t rdtime0:1; + uint64_t rdtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } cn31xx; struct cvmx_pci_int_enb2_s cn38xx; struct cvmx_pci_int_enb2_s cn38xxp2; @@ -1072,6 +1637,7 @@ union cvmx_pci_int_enb2 { union cvmx_pci_int_sum { uint64_t u64; struct cvmx_pci_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1107,8 +1673,46 @@ union cvmx_pci_int_sum { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; +#else + uint64_t tr_wabt:1; + uint64_t mr_wabt:1; + uint64_t mr_wtto:1; + uint64_t tr_abt:1; + uint64_t mr_abt:1; + uint64_t mr_tto:1; + uint64_t msi_per:1; + uint64_t msi_tabt:1; + uint64_t msi_mabt:1; + uint64_t msc_msg:1; + uint64_t tsr_abt:1; + uint64_t serr:1; + uint64_t aperr:1; + uint64_t dperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rsl_int:1; + uint64_t pcnt0:1; + uint64_t pcnt1:1; + uint64_t pcnt2:1; + uint64_t pcnt3:1; + uint64_t ptime0:1; + uint64_t ptime1:1; + uint64_t ptime2:1; + uint64_t ptime3:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_pci_int_sum_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1140,8 +1744,42 @@ union cvmx_pci_int_sum { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; +#else + uint64_t tr_wabt:1; + uint64_t mr_wabt:1; + uint64_t mr_wtto:1; + uint64_t tr_abt:1; + uint64_t mr_abt:1; + uint64_t mr_tto:1; + uint64_t msi_per:1; + uint64_t msi_tabt:1; + uint64_t msi_mabt:1; + uint64_t msc_msg:1; + uint64_t tsr_abt:1; + uint64_t serr:1; + uint64_t aperr:1; + uint64_t dperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rsl_int:1; + uint64_t pcnt0:1; + uint64_t reserved_18_20:3; + uint64_t ptime0:1; + uint64_t reserved_22_24:3; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } cn30xx; struct cvmx_pci_int_sum_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1175,6 +1813,41 @@ union cvmx_pci_int_sum { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; +#else + uint64_t tr_wabt:1; + uint64_t mr_wabt:1; + uint64_t mr_wtto:1; + uint64_t tr_abt:1; + uint64_t mr_abt:1; + uint64_t mr_tto:1; + uint64_t msi_per:1; + uint64_t msi_tabt:1; + uint64_t msi_mabt:1; + uint64_t msc_msg:1; + uint64_t tsr_abt:1; + uint64_t serr:1; + uint64_t aperr:1; + uint64_t dperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rsl_int:1; + uint64_t pcnt0:1; + uint64_t pcnt1:1; + uint64_t reserved_19_20:2; + uint64_t ptime0:1; + uint64_t ptime1:1; + uint64_t reserved_23_24:2; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } cn31xx; struct cvmx_pci_int_sum_s cn38xx; struct cvmx_pci_int_sum_s cn38xxp2; @@ -1186,6 +1859,7 @@ union cvmx_pci_int_sum { union cvmx_pci_int_sum2 { uint64_t u64; struct cvmx_pci_int_sum2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1221,8 +1895,46 @@ union cvmx_pci_int_sum2 { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; +#else + uint64_t tr_wabt:1; + uint64_t mr_wabt:1; + uint64_t mr_wtto:1; + uint64_t tr_abt:1; + uint64_t mr_abt:1; + uint64_t mr_tto:1; + uint64_t msi_per:1; + uint64_t msi_tabt:1; + uint64_t msi_mabt:1; + uint64_t msc_msg:1; + uint64_t tsr_abt:1; + uint64_t serr:1; + uint64_t aperr:1; + uint64_t dperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rsl_int:1; + uint64_t pcnt0:1; + uint64_t pcnt1:1; + uint64_t pcnt2:1; + uint64_t pcnt3:1; + uint64_t ptime0:1; + uint64_t ptime1:1; + uint64_t ptime2:1; + uint64_t ptime3:1; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } s; struct cvmx_pci_int_sum2_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1254,8 +1966,42 @@ union cvmx_pci_int_sum2 { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; +#else + uint64_t tr_wabt:1; + uint64_t mr_wabt:1; + uint64_t mr_wtto:1; + uint64_t tr_abt:1; + uint64_t mr_abt:1; + uint64_t mr_tto:1; + uint64_t msi_per:1; + uint64_t msi_tabt:1; + uint64_t msi_mabt:1; + uint64_t msc_msg:1; + uint64_t tsr_abt:1; + uint64_t serr:1; + uint64_t aperr:1; + uint64_t dperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rsl_int:1; + uint64_t pcnt0:1; + uint64_t reserved_18_20:3; + uint64_t ptime0:1; + uint64_t reserved_22_24:3; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } cn30xx; struct cvmx_pci_int_sum2_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_34_63:30; uint64_t ill_rd:1; uint64_t ill_wr:1; @@ -1289,6 +2035,41 @@ union cvmx_pci_int_sum2 { uint64_t mr_wtto:1; uint64_t mr_wabt:1; uint64_t tr_wabt:1; +#else + uint64_t tr_wabt:1; + uint64_t mr_wabt:1; + uint64_t mr_wtto:1; + uint64_t tr_abt:1; + uint64_t mr_abt:1; + uint64_t mr_tto:1; + uint64_t msi_per:1; + uint64_t msi_tabt:1; + uint64_t msi_mabt:1; + uint64_t msc_msg:1; + uint64_t tsr_abt:1; + uint64_t serr:1; + uint64_t aperr:1; + uint64_t dperr:1; + uint64_t ill_rwr:1; + uint64_t ill_rrd:1; + uint64_t rsl_int:1; + uint64_t pcnt0:1; + uint64_t pcnt1:1; + uint64_t reserved_19_20:2; + uint64_t ptime0:1; + uint64_t ptime1:1; + uint64_t reserved_23_24:2; + uint64_t dcnt0:1; + uint64_t dcnt1:1; + uint64_t dtime0:1; + uint64_t dtime1:1; + uint64_t dma0_fi:1; + uint64_t dma1_fi:1; + uint64_t win_wr:1; + uint64_t ill_wr:1; + uint64_t ill_rd:1; + uint64_t reserved_34_63:30; +#endif } cn31xx; struct cvmx_pci_int_sum2_s cn38xx; struct cvmx_pci_int_sum2_s cn38xxp2; @@ -1300,8 +2081,13 @@ union cvmx_pci_int_sum2 { union cvmx_pci_msi_rcv { uint32_t u32; struct cvmx_pci_msi_rcv_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_6_31:26; uint32_t intr:6; +#else + uint32_t intr:6; + uint32_t reserved_6_31:26; +#endif } s; struct cvmx_pci_msi_rcv_s cn30xx; struct cvmx_pci_msi_rcv_s cn31xx; @@ -1315,8 +2101,13 @@ union cvmx_pci_msi_rcv { union cvmx_pci_pkt_creditsx { uint32_t u32; struct cvmx_pci_pkt_creditsx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pkt_cnt:16; uint32_t ptr_cnt:16; +#else + uint32_t ptr_cnt:16; + uint32_t pkt_cnt:16; +#endif } s; struct cvmx_pci_pkt_creditsx_s cn30xx; struct cvmx_pci_pkt_creditsx_s cn31xx; @@ -1330,7 +2121,11 @@ union cvmx_pci_pkt_creditsx { union cvmx_pci_pkts_sentx { uint32_t u32; struct cvmx_pci_pkts_sentx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pkt_cnt:32; +#else + uint32_t pkt_cnt:32; +#endif } s; struct cvmx_pci_pkts_sentx_s cn30xx; struct cvmx_pci_pkts_sentx_s cn31xx; @@ -1344,7 +2139,11 @@ union cvmx_pci_pkts_sentx { union cvmx_pci_pkts_sent_int_levx { uint32_t u32; struct cvmx_pci_pkts_sent_int_levx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t pkt_cnt:32; +#else uint32_t pkt_cnt:32; +#endif } s; struct cvmx_pci_pkts_sent_int_levx_s cn30xx; struct cvmx_pci_pkts_sent_int_levx_s cn31xx; @@ -1358,7 +2157,11 @@ union cvmx_pci_pkts_sent_int_levx { union cvmx_pci_pkts_sent_timex { uint32_t u32; struct cvmx_pci_pkts_sent_timex_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t pkt_time:32; +#else uint32_t pkt_time:32; +#endif } s; struct cvmx_pci_pkts_sent_timex_s cn30xx; struct cvmx_pci_pkts_sent_timex_s cn31xx; @@ -1372,9 +2175,15 @@ union cvmx_pci_pkts_sent_timex { union cvmx_pci_read_cmd_6 { uint32_t u32; struct cvmx_pci_read_cmd_6_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_9_31:23; uint32_t min_data:6; uint32_t prefetch:3; +#else + uint32_t prefetch:3; + uint32_t min_data:6; + uint32_t reserved_9_31:23; +#endif } s; struct cvmx_pci_read_cmd_6_s cn30xx; struct cvmx_pci_read_cmd_6_s cn31xx; @@ -1388,9 +2197,15 @@ union cvmx_pci_read_cmd_6 { union cvmx_pci_read_cmd_c { uint32_t u32; struct cvmx_pci_read_cmd_c_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_9_31:23; uint32_t min_data:6; uint32_t prefetch:3; +#else + uint32_t prefetch:3; + uint32_t min_data:6; + uint32_t reserved_9_31:23; +#endif } s; struct cvmx_pci_read_cmd_c_s cn30xx; struct cvmx_pci_read_cmd_c_s cn31xx; @@ -1404,9 +2219,15 @@ union cvmx_pci_read_cmd_c { union cvmx_pci_read_cmd_e { uint32_t u32; struct cvmx_pci_read_cmd_e_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_9_31:23; uint32_t min_data:6; uint32_t prefetch:3; +#else + uint32_t prefetch:3; + uint32_t min_data:6; + uint32_t reserved_9_31:23; +#endif } s; struct cvmx_pci_read_cmd_e_s cn30xx; struct cvmx_pci_read_cmd_e_s cn31xx; @@ -1420,9 +2241,15 @@ union cvmx_pci_read_cmd_e { union cvmx_pci_read_timeout { uint64_t u64; struct cvmx_pci_read_timeout_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enb:1; uint64_t cnt:31; +#else + uint64_t cnt:31; + uint64_t enb:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pci_read_timeout_s cn30xx; struct cvmx_pci_read_timeout_s cn31xx; @@ -1436,8 +2263,13 @@ union cvmx_pci_read_timeout { union cvmx_pci_scm_reg { uint64_t u64; struct cvmx_pci_scm_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t scm:32; +#else + uint64_t scm:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pci_scm_reg_s cn30xx; struct cvmx_pci_scm_reg_s cn31xx; @@ -1451,8 +2283,13 @@ union cvmx_pci_scm_reg { union cvmx_pci_tsr_reg { uint64_t u64; struct cvmx_pci_tsr_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_36_63:28; uint64_t tsr:36; +#else + uint64_t tsr:36; + uint64_t reserved_36_63:28; +#endif } s; struct cvmx_pci_tsr_reg_s cn30xx; struct cvmx_pci_tsr_reg_s cn31xx; @@ -1466,22 +2303,42 @@ union cvmx_pci_tsr_reg { union cvmx_pci_win_rd_addr { uint64_t u64; struct cvmx_pci_win_rd_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t reserved_0_47:48; +#else + uint64_t reserved_0_47:48; + uint64_t iobit:1; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_pci_win_rd_addr_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t rd_addr:46; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t rd_addr:46; + uint64_t iobit:1; + uint64_t reserved_49_63:15; +#endif } cn30xx; struct cvmx_pci_win_rd_addr_cn30xx cn31xx; struct cvmx_pci_win_rd_addr_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t rd_addr:45; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t rd_addr:45; + uint64_t iobit:1; + uint64_t reserved_49_63:15; +#endif } cn38xx; struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2; struct cvmx_pci_win_rd_addr_cn30xx cn50xx; @@ -1492,7 +2349,11 @@ union cvmx_pci_win_rd_addr { union cvmx_pci_win_rd_data { uint64_t u64; struct cvmx_pci_win_rd_data_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rd_data:64; +#else uint64_t rd_data:64; +#endif } s; struct cvmx_pci_win_rd_data_s cn30xx; struct cvmx_pci_win_rd_data_s cn31xx; @@ -1506,10 +2367,17 @@ union cvmx_pci_win_rd_data { union cvmx_pci_win_wr_addr { uint64_t u64; struct cvmx_pci_win_wr_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t wr_addr:45; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t wr_addr:45; + uint64_t iobit:1; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_pci_win_wr_addr_s cn30xx; struct cvmx_pci_win_wr_addr_s cn31xx; @@ -1523,7 +2391,11 @@ union cvmx_pci_win_wr_addr { union cvmx_pci_win_wr_data { uint64_t u64; struct cvmx_pci_win_wr_data_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_data:64; +#else + uint64_t wr_data:64; +#endif } s; struct cvmx_pci_win_wr_data_s cn30xx; struct cvmx_pci_win_wr_data_s cn31xx; @@ -1537,8 +2409,13 @@ union cvmx_pci_win_wr_data { union cvmx_pci_win_wr_mask { uint64_t u64; struct cvmx_pci_win_wr_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t wr_mask:8; +#else + uint64_t wr_mask:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_pci_win_wr_mask_s cn30xx; struct cvmx_pci_win_wr_mask_s cn31xx; diff --git a/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h b/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h deleted file mode 100644 index d553f8e88df..00000000000 --- a/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h +++ /dev/null @@ -1,1365 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_PCIEEP_DEFS_H__ -#define __CVMX_PCIEEP_DEFS_H__ - -#define CVMX_PCIEEP_CFG000 \ - (0x0000000000000000ull) -#define CVMX_PCIEEP_CFG001 \ - (0x0000000000000004ull) -#define CVMX_PCIEEP_CFG002 \ - (0x0000000000000008ull) -#define CVMX_PCIEEP_CFG003 \ - (0x000000000000000Cull) -#define CVMX_PCIEEP_CFG004 \ - (0x0000000000000010ull) -#define CVMX_PCIEEP_CFG004_MASK \ - (0x0000000080000010ull) -#define CVMX_PCIEEP_CFG005 \ - (0x0000000000000014ull) -#define CVMX_PCIEEP_CFG005_MASK \ - (0x0000000080000014ull) -#define CVMX_PCIEEP_CFG006 \ - (0x0000000000000018ull) -#define CVMX_PCIEEP_CFG006_MASK \ - (0x0000000080000018ull) -#define CVMX_PCIEEP_CFG007 \ - (0x000000000000001Cull) -#define CVMX_PCIEEP_CFG007_MASK \ - (0x000000008000001Cull) -#define CVMX_PCIEEP_CFG008 \ - (0x0000000000000020ull) -#define CVMX_PCIEEP_CFG008_MASK \ - (0x0000000080000020ull) -#define CVMX_PCIEEP_CFG009 \ - (0x0000000000000024ull) -#define CVMX_PCIEEP_CFG009_MASK \ - (0x0000000080000024ull) -#define CVMX_PCIEEP_CFG010 \ - (0x0000000000000028ull) -#define CVMX_PCIEEP_CFG011 \ - (0x000000000000002Cull) -#define CVMX_PCIEEP_CFG012 \ - (0x0000000000000030ull) -#define CVMX_PCIEEP_CFG012_MASK \ - (0x0000000080000030ull) -#define CVMX_PCIEEP_CFG013 \ - (0x0000000000000034ull) -#define CVMX_PCIEEP_CFG015 \ - (0x000000000000003Cull) -#define CVMX_PCIEEP_CFG016 \ - (0x0000000000000040ull) -#define CVMX_PCIEEP_CFG017 \ - (0x0000000000000044ull) -#define CVMX_PCIEEP_CFG020 \ - (0x0000000000000050ull) -#define CVMX_PCIEEP_CFG021 \ - (0x0000000000000054ull) -#define CVMX_PCIEEP_CFG022 \ - (0x0000000000000058ull) -#define CVMX_PCIEEP_CFG023 \ - (0x000000000000005Cull) -#define CVMX_PCIEEP_CFG028 \ - (0x0000000000000070ull) -#define CVMX_PCIEEP_CFG029 \ - (0x0000000000000074ull) -#define CVMX_PCIEEP_CFG030 \ - (0x0000000000000078ull) -#define CVMX_PCIEEP_CFG031 \ - (0x000000000000007Cull) -#define CVMX_PCIEEP_CFG032 \ - (0x0000000000000080ull) -#define CVMX_PCIEEP_CFG033 \ - (0x0000000000000084ull) -#define CVMX_PCIEEP_CFG034 \ - (0x0000000000000088ull) -#define CVMX_PCIEEP_CFG037 \ - (0x0000000000000094ull) -#define CVMX_PCIEEP_CFG038 \ - (0x0000000000000098ull) -#define CVMX_PCIEEP_CFG039 \ - (0x000000000000009Cull) -#define CVMX_PCIEEP_CFG040 \ - (0x00000000000000A0ull) -#define CVMX_PCIEEP_CFG041 \ - (0x00000000000000A4ull) -#define CVMX_PCIEEP_CFG042 \ - (0x00000000000000A8ull) -#define CVMX_PCIEEP_CFG064 \ - (0x0000000000000100ull) -#define CVMX_PCIEEP_CFG065 \ - (0x0000000000000104ull) -#define CVMX_PCIEEP_CFG066 \ - (0x0000000000000108ull) -#define CVMX_PCIEEP_CFG067 \ - (0x000000000000010Cull) -#define CVMX_PCIEEP_CFG068 \ - (0x0000000000000110ull) -#define CVMX_PCIEEP_CFG069 \ - (0x0000000000000114ull) -#define CVMX_PCIEEP_CFG070 \ - (0x0000000000000118ull) -#define CVMX_PCIEEP_CFG071 \ - (0x000000000000011Cull) -#define CVMX_PCIEEP_CFG072 \ - (0x0000000000000120ull) -#define CVMX_PCIEEP_CFG073 \ - (0x0000000000000124ull) -#define CVMX_PCIEEP_CFG074 \ - (0x0000000000000128ull) -#define CVMX_PCIEEP_CFG448 \ - (0x0000000000000700ull) -#define CVMX_PCIEEP_CFG449 \ - (0x0000000000000704ull) -#define CVMX_PCIEEP_CFG450 \ - (0x0000000000000708ull) -#define CVMX_PCIEEP_CFG451 \ - (0x000000000000070Cull) -#define CVMX_PCIEEP_CFG452 \ - (0x0000000000000710ull) -#define CVMX_PCIEEP_CFG453 \ - (0x0000000000000714ull) -#define CVMX_PCIEEP_CFG454 \ - (0x0000000000000718ull) -#define CVMX_PCIEEP_CFG455 \ - (0x000000000000071Cull) -#define CVMX_PCIEEP_CFG456 \ - (0x0000000000000720ull) -#define CVMX_PCIEEP_CFG458 \ - (0x0000000000000728ull) -#define CVMX_PCIEEP_CFG459 \ - (0x000000000000072Cull) -#define CVMX_PCIEEP_CFG460 \ - (0x0000000000000730ull) -#define CVMX_PCIEEP_CFG461 \ - (0x0000000000000734ull) -#define CVMX_PCIEEP_CFG462 \ - (0x0000000000000738ull) -#define CVMX_PCIEEP_CFG463 \ - (0x000000000000073Cull) -#define CVMX_PCIEEP_CFG464 \ - (0x0000000000000740ull) -#define CVMX_PCIEEP_CFG465 \ - (0x0000000000000744ull) -#define CVMX_PCIEEP_CFG466 \ - (0x0000000000000748ull) -#define CVMX_PCIEEP_CFG467 \ - (0x000000000000074Cull) -#define CVMX_PCIEEP_CFG468 \ - (0x0000000000000750ull) -#define CVMX_PCIEEP_CFG490 \ - (0x00000000000007A8ull) -#define CVMX_PCIEEP_CFG491 \ - (0x00000000000007ACull) -#define CVMX_PCIEEP_CFG492 \ - (0x00000000000007B0ull) -#define CVMX_PCIEEP_CFG516 \ - (0x0000000000000810ull) -#define CVMX_PCIEEP_CFG517 \ - (0x0000000000000814ull) - -union cvmx_pcieep_cfg000 { - uint32_t u32; - struct cvmx_pcieep_cfg000_s { - uint32_t devid:16; - uint32_t vendid:16; - } s; - struct cvmx_pcieep_cfg000_s cn52xx; - struct cvmx_pcieep_cfg000_s cn52xxp1; - struct cvmx_pcieep_cfg000_s cn56xx; - struct cvmx_pcieep_cfg000_s cn56xxp1; -}; - -union cvmx_pcieep_cfg001 { - uint32_t u32; - struct cvmx_pcieep_cfg001_s { - uint32_t dpe:1; - uint32_t sse:1; - uint32_t rma:1; - uint32_t rta:1; - uint32_t sta:1; - uint32_t devt:2; - uint32_t mdpe:1; - uint32_t fbb:1; - uint32_t reserved_22_22:1; - uint32_t m66:1; - uint32_t cl:1; - uint32_t i_stat:1; - uint32_t reserved_11_18:8; - uint32_t i_dis:1; - uint32_t fbbe:1; - uint32_t see:1; - uint32_t ids_wcc:1; - uint32_t per:1; - uint32_t vps:1; - uint32_t mwice:1; - uint32_t scse:1; - uint32_t me:1; - uint32_t msae:1; - uint32_t isae:1; - } s; - struct cvmx_pcieep_cfg001_s cn52xx; - struct cvmx_pcieep_cfg001_s cn52xxp1; - struct cvmx_pcieep_cfg001_s cn56xx; - struct cvmx_pcieep_cfg001_s cn56xxp1; -}; - -union cvmx_pcieep_cfg002 { - uint32_t u32; - struct cvmx_pcieep_cfg002_s { - uint32_t bcc:8; - uint32_t sc:8; - uint32_t pi:8; - uint32_t rid:8; - } s; - struct cvmx_pcieep_cfg002_s cn52xx; - struct cvmx_pcieep_cfg002_s cn52xxp1; - struct cvmx_pcieep_cfg002_s cn56xx; - struct cvmx_pcieep_cfg002_s cn56xxp1; -}; - -union cvmx_pcieep_cfg003 { - uint32_t u32; - struct cvmx_pcieep_cfg003_s { - uint32_t bist:8; - uint32_t mfd:1; - uint32_t chf:7; - uint32_t lt:8; - uint32_t cls:8; - } s; - struct cvmx_pcieep_cfg003_s cn52xx; - struct cvmx_pcieep_cfg003_s cn52xxp1; - struct cvmx_pcieep_cfg003_s cn56xx; - struct cvmx_pcieep_cfg003_s cn56xxp1; -}; - -union cvmx_pcieep_cfg004 { - uint32_t u32; - struct cvmx_pcieep_cfg004_s { - uint32_t lbab:18; - uint32_t reserved_4_13:10; - uint32_t pf:1; - uint32_t typ:2; - uint32_t mspc:1; - } s; - struct cvmx_pcieep_cfg004_s cn52xx; - struct cvmx_pcieep_cfg004_s cn52xxp1; - struct cvmx_pcieep_cfg004_s cn56xx; - struct cvmx_pcieep_cfg004_s cn56xxp1; -}; - -union cvmx_pcieep_cfg004_mask { - uint32_t u32; - struct cvmx_pcieep_cfg004_mask_s { - uint32_t lmask:31; - uint32_t enb:1; - } s; - struct cvmx_pcieep_cfg004_mask_s cn52xx; - struct cvmx_pcieep_cfg004_mask_s cn52xxp1; - struct cvmx_pcieep_cfg004_mask_s cn56xx; - struct cvmx_pcieep_cfg004_mask_s cn56xxp1; -}; - -union cvmx_pcieep_cfg005 { - uint32_t u32; - struct cvmx_pcieep_cfg005_s { - uint32_t ubab:32; - } s; - struct cvmx_pcieep_cfg005_s cn52xx; - struct cvmx_pcieep_cfg005_s cn52xxp1; - struct cvmx_pcieep_cfg005_s cn56xx; - struct cvmx_pcieep_cfg005_s cn56xxp1; -}; - -union cvmx_pcieep_cfg005_mask { - uint32_t u32; - struct cvmx_pcieep_cfg005_mask_s { - uint32_t umask:32; - } s; - struct cvmx_pcieep_cfg005_mask_s cn52xx; - struct cvmx_pcieep_cfg005_mask_s cn52xxp1; - struct cvmx_pcieep_cfg005_mask_s cn56xx; - struct cvmx_pcieep_cfg005_mask_s cn56xxp1; -}; - -union cvmx_pcieep_cfg006 { - uint32_t u32; - struct cvmx_pcieep_cfg006_s { - uint32_t lbab:6; - uint32_t reserved_4_25:22; - uint32_t pf:1; - uint32_t typ:2; - uint32_t mspc:1; - } s; - struct cvmx_pcieep_cfg006_s cn52xx; - struct cvmx_pcieep_cfg006_s cn52xxp1; - struct cvmx_pcieep_cfg006_s cn56xx; - struct cvmx_pcieep_cfg006_s cn56xxp1; -}; - -union cvmx_pcieep_cfg006_mask { - uint32_t u32; - struct cvmx_pcieep_cfg006_mask_s { - uint32_t lmask:31; - uint32_t enb:1; - } s; - struct cvmx_pcieep_cfg006_mask_s cn52xx; - struct cvmx_pcieep_cfg006_mask_s cn52xxp1; - struct cvmx_pcieep_cfg006_mask_s cn56xx; - struct cvmx_pcieep_cfg006_mask_s cn56xxp1; -}; - -union cvmx_pcieep_cfg007 { - uint32_t u32; - struct cvmx_pcieep_cfg007_s { - uint32_t ubab:32; - } s; - struct cvmx_pcieep_cfg007_s cn52xx; - struct cvmx_pcieep_cfg007_s cn52xxp1; - struct cvmx_pcieep_cfg007_s cn56xx; - struct cvmx_pcieep_cfg007_s cn56xxp1; -}; - -union cvmx_pcieep_cfg007_mask { - uint32_t u32; - struct cvmx_pcieep_cfg007_mask_s { - uint32_t umask:32; - } s; - struct cvmx_pcieep_cfg007_mask_s cn52xx; - struct cvmx_pcieep_cfg007_mask_s cn52xxp1; - struct cvmx_pcieep_cfg007_mask_s cn56xx; - struct cvmx_pcieep_cfg007_mask_s cn56xxp1; -}; - -union cvmx_pcieep_cfg008 { - uint32_t u32; - struct cvmx_pcieep_cfg008_s { - uint32_t reserved_4_31:28; - uint32_t pf:1; - uint32_t typ:2; - uint32_t mspc:1; - } s; - struct cvmx_pcieep_cfg008_s cn52xx; - struct cvmx_pcieep_cfg008_s cn52xxp1; - struct cvmx_pcieep_cfg008_s cn56xx; - struct cvmx_pcieep_cfg008_s cn56xxp1; -}; - -union cvmx_pcieep_cfg008_mask { - uint32_t u32; - struct cvmx_pcieep_cfg008_mask_s { - uint32_t lmask:31; - uint32_t enb:1; - } s; - struct cvmx_pcieep_cfg008_mask_s cn52xx; - struct cvmx_pcieep_cfg008_mask_s cn52xxp1; - struct cvmx_pcieep_cfg008_mask_s cn56xx; - struct cvmx_pcieep_cfg008_mask_s cn56xxp1; -}; - -union cvmx_pcieep_cfg009 { - uint32_t u32; - struct cvmx_pcieep_cfg009_s { - uint32_t ubab:25; - uint32_t reserved_0_6:7; - } s; - struct cvmx_pcieep_cfg009_s cn52xx; - struct cvmx_pcieep_cfg009_s cn52xxp1; - struct cvmx_pcieep_cfg009_s cn56xx; - struct cvmx_pcieep_cfg009_s cn56xxp1; -}; - -union cvmx_pcieep_cfg009_mask { - uint32_t u32; - struct cvmx_pcieep_cfg009_mask_s { - uint32_t umask:32; - } s; - struct cvmx_pcieep_cfg009_mask_s cn52xx; - struct cvmx_pcieep_cfg009_mask_s cn52xxp1; - struct cvmx_pcieep_cfg009_mask_s cn56xx; - struct cvmx_pcieep_cfg009_mask_s cn56xxp1; -}; - -union cvmx_pcieep_cfg010 { - uint32_t u32; - struct cvmx_pcieep_cfg010_s { - uint32_t cisp:32; - } s; - struct cvmx_pcieep_cfg010_s cn52xx; - struct cvmx_pcieep_cfg010_s cn52xxp1; - struct cvmx_pcieep_cfg010_s cn56xx; - struct cvmx_pcieep_cfg010_s cn56xxp1; -}; - -union cvmx_pcieep_cfg011 { - uint32_t u32; - struct cvmx_pcieep_cfg011_s { - uint32_t ssid:16; - uint32_t ssvid:16; - } s; - struct cvmx_pcieep_cfg011_s cn52xx; - struct cvmx_pcieep_cfg011_s cn52xxp1; - struct cvmx_pcieep_cfg011_s cn56xx; - struct cvmx_pcieep_cfg011_s cn56xxp1; -}; - -union cvmx_pcieep_cfg012 { - uint32_t u32; - struct cvmx_pcieep_cfg012_s { - uint32_t eraddr:16; - uint32_t reserved_1_15:15; - uint32_t er_en:1; - } s; - struct cvmx_pcieep_cfg012_s cn52xx; - struct cvmx_pcieep_cfg012_s cn52xxp1; - struct cvmx_pcieep_cfg012_s cn56xx; - struct cvmx_pcieep_cfg012_s cn56xxp1; -}; - -union cvmx_pcieep_cfg012_mask { - uint32_t u32; - struct cvmx_pcieep_cfg012_mask_s { - uint32_t mask:31; - uint32_t enb:1; - } s; - struct cvmx_pcieep_cfg012_mask_s cn52xx; - struct cvmx_pcieep_cfg012_mask_s cn52xxp1; - struct cvmx_pcieep_cfg012_mask_s cn56xx; - struct cvmx_pcieep_cfg012_mask_s cn56xxp1; -}; - -union cvmx_pcieep_cfg013 { - uint32_t u32; - struct cvmx_pcieep_cfg013_s { - uint32_t reserved_8_31:24; - uint32_t cp:8; - } s; - struct cvmx_pcieep_cfg013_s cn52xx; - struct cvmx_pcieep_cfg013_s cn52xxp1; - struct cvmx_pcieep_cfg013_s cn56xx; - struct cvmx_pcieep_cfg013_s cn56xxp1; -}; - -union cvmx_pcieep_cfg015 { - uint32_t u32; - struct cvmx_pcieep_cfg015_s { - uint32_t ml:8; - uint32_t mg:8; - uint32_t inta:8; - uint32_t il:8; - } s; - struct cvmx_pcieep_cfg015_s cn52xx; - struct cvmx_pcieep_cfg015_s cn52xxp1; - struct cvmx_pcieep_cfg015_s cn56xx; - struct cvmx_pcieep_cfg015_s cn56xxp1; -}; - -union cvmx_pcieep_cfg016 { - uint32_t u32; - struct cvmx_pcieep_cfg016_s { - uint32_t pmes:5; - uint32_t d2s:1; - uint32_t d1s:1; - uint32_t auxc:3; - uint32_t dsi:1; - uint32_t reserved_20_20:1; - uint32_t pme_clock:1; - uint32_t pmsv:3; - uint32_t ncp:8; - uint32_t pmcid:8; - } s; - struct cvmx_pcieep_cfg016_s cn52xx; - struct cvmx_pcieep_cfg016_s cn52xxp1; - struct cvmx_pcieep_cfg016_s cn56xx; - struct cvmx_pcieep_cfg016_s cn56xxp1; -}; - -union cvmx_pcieep_cfg017 { - uint32_t u32; - struct cvmx_pcieep_cfg017_s { - uint32_t pmdia:8; - uint32_t bpccee:1; - uint32_t bd3h:1; - uint32_t reserved_16_21:6; - uint32_t pmess:1; - uint32_t pmedsia:2; - uint32_t pmds:4; - uint32_t pmeens:1; - uint32_t reserved_4_7:4; - uint32_t nsr:1; - uint32_t reserved_2_2:1; - uint32_t ps:2; - } s; - struct cvmx_pcieep_cfg017_s cn52xx; - struct cvmx_pcieep_cfg017_s cn52xxp1; - struct cvmx_pcieep_cfg017_s cn56xx; - struct cvmx_pcieep_cfg017_s cn56xxp1; -}; - -union cvmx_pcieep_cfg020 { - uint32_t u32; - struct cvmx_pcieep_cfg020_s { - uint32_t reserved_24_31:8; - uint32_t m64:1; - uint32_t mme:3; - uint32_t mmc:3; - uint32_t msien:1; - uint32_t ncp:8; - uint32_t msicid:8; - } s; - struct cvmx_pcieep_cfg020_s cn52xx; - struct cvmx_pcieep_cfg020_s cn52xxp1; - struct cvmx_pcieep_cfg020_s cn56xx; - struct cvmx_pcieep_cfg020_s cn56xxp1; -}; - -union cvmx_pcieep_cfg021 { - uint32_t u32; - struct cvmx_pcieep_cfg021_s { - uint32_t lmsi:30; - uint32_t reserved_0_1:2; - } s; - struct cvmx_pcieep_cfg021_s cn52xx; - struct cvmx_pcieep_cfg021_s cn52xxp1; - struct cvmx_pcieep_cfg021_s cn56xx; - struct cvmx_pcieep_cfg021_s cn56xxp1; -}; - -union cvmx_pcieep_cfg022 { - uint32_t u32; - struct cvmx_pcieep_cfg022_s { - uint32_t umsi:32; - } s; - struct cvmx_pcieep_cfg022_s cn52xx; - struct cvmx_pcieep_cfg022_s cn52xxp1; - struct cvmx_pcieep_cfg022_s cn56xx; - struct cvmx_pcieep_cfg022_s cn56xxp1; -}; - -union cvmx_pcieep_cfg023 { - uint32_t u32; - struct cvmx_pcieep_cfg023_s { - uint32_t reserved_16_31:16; - uint32_t msimd:16; - } s; - struct cvmx_pcieep_cfg023_s cn52xx; - struct cvmx_pcieep_cfg023_s cn52xxp1; - struct cvmx_pcieep_cfg023_s cn56xx; - struct cvmx_pcieep_cfg023_s cn56xxp1; -}; - -union cvmx_pcieep_cfg028 { - uint32_t u32; - struct cvmx_pcieep_cfg028_s { - uint32_t reserved_30_31:2; - uint32_t imn:5; - uint32_t si:1; - uint32_t dpt:4; - uint32_t pciecv:4; - uint32_t ncp:8; - uint32_t pcieid:8; - } s; - struct cvmx_pcieep_cfg028_s cn52xx; - struct cvmx_pcieep_cfg028_s cn52xxp1; - struct cvmx_pcieep_cfg028_s cn56xx; - struct cvmx_pcieep_cfg028_s cn56xxp1; -}; - -union cvmx_pcieep_cfg029 { - uint32_t u32; - struct cvmx_pcieep_cfg029_s { - uint32_t reserved_28_31:4; - uint32_t cspls:2; - uint32_t csplv:8; - uint32_t reserved_16_17:2; - uint32_t rber:1; - uint32_t reserved_12_14:3; - uint32_t el1al:3; - uint32_t el0al:3; - uint32_t etfs:1; - uint32_t pfs:2; - uint32_t mpss:3; - } s; - struct cvmx_pcieep_cfg029_s cn52xx; - struct cvmx_pcieep_cfg029_s cn52xxp1; - struct cvmx_pcieep_cfg029_s cn56xx; - struct cvmx_pcieep_cfg029_s cn56xxp1; -}; - -union cvmx_pcieep_cfg030 { - uint32_t u32; - struct cvmx_pcieep_cfg030_s { - uint32_t reserved_22_31:10; - uint32_t tp:1; - uint32_t ap_d:1; - uint32_t ur_d:1; - uint32_t fe_d:1; - uint32_t nfe_d:1; - uint32_t ce_d:1; - uint32_t reserved_15_15:1; - uint32_t mrrs:3; - uint32_t ns_en:1; - uint32_t ap_en:1; - uint32_t pf_en:1; - uint32_t etf_en:1; - uint32_t mps:3; - uint32_t ro_en:1; - uint32_t ur_en:1; - uint32_t fe_en:1; - uint32_t nfe_en:1; - uint32_t ce_en:1; - } s; - struct cvmx_pcieep_cfg030_s cn52xx; - struct cvmx_pcieep_cfg030_s cn52xxp1; - struct cvmx_pcieep_cfg030_s cn56xx; - struct cvmx_pcieep_cfg030_s cn56xxp1; -}; - -union cvmx_pcieep_cfg031 { - uint32_t u32; - struct cvmx_pcieep_cfg031_s { - uint32_t pnum:8; - uint32_t reserved_22_23:2; - uint32_t lbnc:1; - uint32_t dllarc:1; - uint32_t sderc:1; - uint32_t cpm:1; - uint32_t l1el:3; - uint32_t l0el:3; - uint32_t aslpms:2; - uint32_t mlw:6; - uint32_t mls:4; - } s; - struct cvmx_pcieep_cfg031_s cn52xx; - struct cvmx_pcieep_cfg031_s cn52xxp1; - struct cvmx_pcieep_cfg031_s cn56xx; - struct cvmx_pcieep_cfg031_s cn56xxp1; -}; - -union cvmx_pcieep_cfg032 { - uint32_t u32; - struct cvmx_pcieep_cfg032_s { - uint32_t reserved_30_31:2; - uint32_t dlla:1; - uint32_t scc:1; - uint32_t lt:1; - uint32_t reserved_26_26:1; - uint32_t nlw:6; - uint32_t ls:4; - uint32_t reserved_10_15:6; - uint32_t hawd:1; - uint32_t ecpm:1; - uint32_t es:1; - uint32_t ccc:1; - uint32_t rl:1; - uint32_t ld:1; - uint32_t rcb:1; - uint32_t reserved_2_2:1; - uint32_t aslpc:2; - } s; - struct cvmx_pcieep_cfg032_s cn52xx; - struct cvmx_pcieep_cfg032_s cn52xxp1; - struct cvmx_pcieep_cfg032_s cn56xx; - struct cvmx_pcieep_cfg032_s cn56xxp1; -}; - -union cvmx_pcieep_cfg033 { - uint32_t u32; - struct cvmx_pcieep_cfg033_s { - uint32_t ps_num:13; - uint32_t nccs:1; - uint32_t emip:1; - uint32_t sp_ls:2; - uint32_t sp_lv:8; - uint32_t hp_c:1; - uint32_t hp_s:1; - uint32_t pip:1; - uint32_t aip:1; - uint32_t mrlsp:1; - uint32_t pcp:1; - uint32_t abp:1; - } s; - struct cvmx_pcieep_cfg033_s cn52xx; - struct cvmx_pcieep_cfg033_s cn52xxp1; - struct cvmx_pcieep_cfg033_s cn56xx; - struct cvmx_pcieep_cfg033_s cn56xxp1; -}; - -union cvmx_pcieep_cfg034 { - uint32_t u32; - struct cvmx_pcieep_cfg034_s { - uint32_t reserved_25_31:7; - uint32_t dlls_c:1; - uint32_t emis:1; - uint32_t pds:1; - uint32_t mrlss:1; - uint32_t ccint_d:1; - uint32_t pd_c:1; - uint32_t mrls_c:1; - uint32_t pf_d:1; - uint32_t abp_d:1; - uint32_t reserved_13_15:3; - uint32_t dlls_en:1; - uint32_t emic:1; - uint32_t pcc:1; - uint32_t pic:2; - uint32_t aic:2; - uint32_t hpint_en:1; - uint32_t ccint_en:1; - uint32_t pd_en:1; - uint32_t mrls_en:1; - uint32_t pf_en:1; - uint32_t abp_en:1; - } s; - struct cvmx_pcieep_cfg034_s cn52xx; - struct cvmx_pcieep_cfg034_s cn52xxp1; - struct cvmx_pcieep_cfg034_s cn56xx; - struct cvmx_pcieep_cfg034_s cn56xxp1; -}; - -union cvmx_pcieep_cfg037 { - uint32_t u32; - struct cvmx_pcieep_cfg037_s { - uint32_t reserved_5_31:27; - uint32_t ctds:1; - uint32_t ctrs:4; - } s; - struct cvmx_pcieep_cfg037_s cn52xx; - struct cvmx_pcieep_cfg037_s cn52xxp1; - struct cvmx_pcieep_cfg037_s cn56xx; - struct cvmx_pcieep_cfg037_s cn56xxp1; -}; - -union cvmx_pcieep_cfg038 { - uint32_t u32; - struct cvmx_pcieep_cfg038_s { - uint32_t reserved_5_31:27; - uint32_t ctd:1; - uint32_t ctv:4; - } s; - struct cvmx_pcieep_cfg038_s cn52xx; - struct cvmx_pcieep_cfg038_s cn52xxp1; - struct cvmx_pcieep_cfg038_s cn56xx; - struct cvmx_pcieep_cfg038_s cn56xxp1; -}; - -union cvmx_pcieep_cfg039 { - uint32_t u32; - struct cvmx_pcieep_cfg039_s { - uint32_t reserved_0_31:32; - } s; - struct cvmx_pcieep_cfg039_s cn52xx; - struct cvmx_pcieep_cfg039_s cn52xxp1; - struct cvmx_pcieep_cfg039_s cn56xx; - struct cvmx_pcieep_cfg039_s cn56xxp1; -}; - -union cvmx_pcieep_cfg040 { - uint32_t u32; - struct cvmx_pcieep_cfg040_s { - uint32_t reserved_0_31:32; - } s; - struct cvmx_pcieep_cfg040_s cn52xx; - struct cvmx_pcieep_cfg040_s cn52xxp1; - struct cvmx_pcieep_cfg040_s cn56xx; - struct cvmx_pcieep_cfg040_s cn56xxp1; -}; - -union cvmx_pcieep_cfg041 { - uint32_t u32; - struct cvmx_pcieep_cfg041_s { - uint32_t reserved_0_31:32; - } s; - struct cvmx_pcieep_cfg041_s cn52xx; - struct cvmx_pcieep_cfg041_s cn52xxp1; - struct cvmx_pcieep_cfg041_s cn56xx; - struct cvmx_pcieep_cfg041_s cn56xxp1; -}; - -union cvmx_pcieep_cfg042 { - uint32_t u32; - struct cvmx_pcieep_cfg042_s { - uint32_t reserved_0_31:32; - } s; - struct cvmx_pcieep_cfg042_s cn52xx; - struct cvmx_pcieep_cfg042_s cn52xxp1; - struct cvmx_pcieep_cfg042_s cn56xx; - struct cvmx_pcieep_cfg042_s cn56xxp1; -}; - -union cvmx_pcieep_cfg064 { - uint32_t u32; - struct cvmx_pcieep_cfg064_s { - uint32_t nco:12; - uint32_t cv:4; - uint32_t pcieec:16; - } s; - struct cvmx_pcieep_cfg064_s cn52xx; - struct cvmx_pcieep_cfg064_s cn52xxp1; - struct cvmx_pcieep_cfg064_s cn56xx; - struct cvmx_pcieep_cfg064_s cn56xxp1; -}; - -union cvmx_pcieep_cfg065 { - uint32_t u32; - struct cvmx_pcieep_cfg065_s { - uint32_t reserved_21_31:11; - uint32_t ures:1; - uint32_t ecrces:1; - uint32_t mtlps:1; - uint32_t ros:1; - uint32_t ucs:1; - uint32_t cas:1; - uint32_t cts:1; - uint32_t fcpes:1; - uint32_t ptlps:1; - uint32_t reserved_6_11:6; - uint32_t sdes:1; - uint32_t dlpes:1; - uint32_t reserved_0_3:4; - } s; - struct cvmx_pcieep_cfg065_s cn52xx; - struct cvmx_pcieep_cfg065_s cn52xxp1; - struct cvmx_pcieep_cfg065_s cn56xx; - struct cvmx_pcieep_cfg065_s cn56xxp1; -}; - -union cvmx_pcieep_cfg066 { - uint32_t u32; - struct cvmx_pcieep_cfg066_s { - uint32_t reserved_21_31:11; - uint32_t urem:1; - uint32_t ecrcem:1; - uint32_t mtlpm:1; - uint32_t rom:1; - uint32_t ucm:1; - uint32_t cam:1; - uint32_t ctm:1; - uint32_t fcpem:1; - uint32_t ptlpm:1; - uint32_t reserved_6_11:6; - uint32_t sdem:1; - uint32_t dlpem:1; - uint32_t reserved_0_3:4; - } s; - struct cvmx_pcieep_cfg066_s cn52xx; - struct cvmx_pcieep_cfg066_s cn52xxp1; - struct cvmx_pcieep_cfg066_s cn56xx; - struct cvmx_pcieep_cfg066_s cn56xxp1; -}; - -union cvmx_pcieep_cfg067 { - uint32_t u32; - struct cvmx_pcieep_cfg067_s { - uint32_t reserved_21_31:11; - uint32_t ures:1; - uint32_t ecrces:1; - uint32_t mtlps:1; - uint32_t ros:1; - uint32_t ucs:1; - uint32_t cas:1; - uint32_t cts:1; - uint32_t fcpes:1; - uint32_t ptlps:1; - uint32_t reserved_6_11:6; - uint32_t sdes:1; - uint32_t dlpes:1; - uint32_t reserved_0_3:4; - } s; - struct cvmx_pcieep_cfg067_s cn52xx; - struct cvmx_pcieep_cfg067_s cn52xxp1; - struct cvmx_pcieep_cfg067_s cn56xx; - struct cvmx_pcieep_cfg067_s cn56xxp1; -}; - -union cvmx_pcieep_cfg068 { - uint32_t u32; - struct cvmx_pcieep_cfg068_s { - uint32_t reserved_14_31:18; - uint32_t anfes:1; - uint32_t rtts:1; - uint32_t reserved_9_11:3; - uint32_t rnrs:1; - uint32_t bdllps:1; - uint32_t btlps:1; - uint32_t reserved_1_5:5; - uint32_t res:1; - } s; - struct cvmx_pcieep_cfg068_s cn52xx; - struct cvmx_pcieep_cfg068_s cn52xxp1; - struct cvmx_pcieep_cfg068_s cn56xx; - struct cvmx_pcieep_cfg068_s cn56xxp1; -}; - -union cvmx_pcieep_cfg069 { - uint32_t u32; - struct cvmx_pcieep_cfg069_s { - uint32_t reserved_14_31:18; - uint32_t anfem:1; - uint32_t rttm:1; - uint32_t reserved_9_11:3; - uint32_t rnrm:1; - uint32_t bdllpm:1; - uint32_t btlpm:1; - uint32_t reserved_1_5:5; - uint32_t rem:1; - } s; - struct cvmx_pcieep_cfg069_s cn52xx; - struct cvmx_pcieep_cfg069_s cn52xxp1; - struct cvmx_pcieep_cfg069_s cn56xx; - struct cvmx_pcieep_cfg069_s cn56xxp1; -}; - -union cvmx_pcieep_cfg070 { - uint32_t u32; - struct cvmx_pcieep_cfg070_s { - uint32_t reserved_9_31:23; - uint32_t ce:1; - uint32_t cc:1; - uint32_t ge:1; - uint32_t gc:1; - uint32_t fep:5; - } s; - struct cvmx_pcieep_cfg070_s cn52xx; - struct cvmx_pcieep_cfg070_s cn52xxp1; - struct cvmx_pcieep_cfg070_s cn56xx; - struct cvmx_pcieep_cfg070_s cn56xxp1; -}; - -union cvmx_pcieep_cfg071 { - uint32_t u32; - struct cvmx_pcieep_cfg071_s { - uint32_t dword1:32; - } s; - struct cvmx_pcieep_cfg071_s cn52xx; - struct cvmx_pcieep_cfg071_s cn52xxp1; - struct cvmx_pcieep_cfg071_s cn56xx; - struct cvmx_pcieep_cfg071_s cn56xxp1; -}; - -union cvmx_pcieep_cfg072 { - uint32_t u32; - struct cvmx_pcieep_cfg072_s { - uint32_t dword2:32; - } s; - struct cvmx_pcieep_cfg072_s cn52xx; - struct cvmx_pcieep_cfg072_s cn52xxp1; - struct cvmx_pcieep_cfg072_s cn56xx; - struct cvmx_pcieep_cfg072_s cn56xxp1; -}; - -union cvmx_pcieep_cfg073 { - uint32_t u32; - struct cvmx_pcieep_cfg073_s { - uint32_t dword3:32; - } s; - struct cvmx_pcieep_cfg073_s cn52xx; - struct cvmx_pcieep_cfg073_s cn52xxp1; - struct cvmx_pcieep_cfg073_s cn56xx; - struct cvmx_pcieep_cfg073_s cn56xxp1; -}; - -union cvmx_pcieep_cfg074 { - uint32_t u32; - struct cvmx_pcieep_cfg074_s { - uint32_t dword4:32; - } s; - struct cvmx_pcieep_cfg074_s cn52xx; - struct cvmx_pcieep_cfg074_s cn52xxp1; - struct cvmx_pcieep_cfg074_s cn56xx; - struct cvmx_pcieep_cfg074_s cn56xxp1; -}; - -union cvmx_pcieep_cfg448 { - uint32_t u32; - struct cvmx_pcieep_cfg448_s { - uint32_t rtl:16; - uint32_t rtltl:16; - } s; - struct cvmx_pcieep_cfg448_s cn52xx; - struct cvmx_pcieep_cfg448_s cn52xxp1; - struct cvmx_pcieep_cfg448_s cn56xx; - struct cvmx_pcieep_cfg448_s cn56xxp1; -}; - -union cvmx_pcieep_cfg449 { - uint32_t u32; - struct cvmx_pcieep_cfg449_s { - uint32_t omr:32; - } s; - struct cvmx_pcieep_cfg449_s cn52xx; - struct cvmx_pcieep_cfg449_s cn52xxp1; - struct cvmx_pcieep_cfg449_s cn56xx; - struct cvmx_pcieep_cfg449_s cn56xxp1; -}; - -union cvmx_pcieep_cfg450 { - uint32_t u32; - struct cvmx_pcieep_cfg450_s { - uint32_t lpec:8; - uint32_t reserved_22_23:2; - uint32_t link_state:6; - uint32_t force_link:1; - uint32_t reserved_8_14:7; - uint32_t link_num:8; - } s; - struct cvmx_pcieep_cfg450_s cn52xx; - struct cvmx_pcieep_cfg450_s cn52xxp1; - struct cvmx_pcieep_cfg450_s cn56xx; - struct cvmx_pcieep_cfg450_s cn56xxp1; -}; - -union cvmx_pcieep_cfg451 { - uint32_t u32; - struct cvmx_pcieep_cfg451_s { - uint32_t reserved_30_31:2; - uint32_t l1el:3; - uint32_t l0el:3; - uint32_t n_fts_cc:8; - uint32_t n_fts:8; - uint32_t ack_freq:8; - } s; - struct cvmx_pcieep_cfg451_s cn52xx; - struct cvmx_pcieep_cfg451_s cn52xxp1; - struct cvmx_pcieep_cfg451_s cn56xx; - struct cvmx_pcieep_cfg451_s cn56xxp1; -}; - -union cvmx_pcieep_cfg452 { - uint32_t u32; - struct cvmx_pcieep_cfg452_s { - uint32_t reserved_26_31:6; - uint32_t eccrc:1; - uint32_t reserved_22_24:3; - uint32_t lme:6; - uint32_t reserved_8_15:8; - uint32_t flm:1; - uint32_t reserved_6_6:1; - uint32_t dllle:1; - uint32_t reserved_4_4:1; - uint32_t ra:1; - uint32_t le:1; - uint32_t sd:1; - uint32_t omr:1; - } s; - struct cvmx_pcieep_cfg452_s cn52xx; - struct cvmx_pcieep_cfg452_s cn52xxp1; - struct cvmx_pcieep_cfg452_s cn56xx; - struct cvmx_pcieep_cfg452_s cn56xxp1; -}; - -union cvmx_pcieep_cfg453 { - uint32_t u32; - struct cvmx_pcieep_cfg453_s { - uint32_t dlld:1; - uint32_t reserved_26_30:5; - uint32_t ack_nak:1; - uint32_t fcd:1; - uint32_t ilst:24; - } s; - struct cvmx_pcieep_cfg453_s cn52xx; - struct cvmx_pcieep_cfg453_s cn52xxp1; - struct cvmx_pcieep_cfg453_s cn56xx; - struct cvmx_pcieep_cfg453_s cn56xxp1; -}; - -union cvmx_pcieep_cfg454 { - uint32_t u32; - struct cvmx_pcieep_cfg454_s { - uint32_t reserved_29_31:3; - uint32_t tmfcwt:5; - uint32_t tmanlt:5; - uint32_t tmrt:5; - uint32_t reserved_11_13:3; - uint32_t nskps:3; - uint32_t reserved_4_7:4; - uint32_t ntss:4; - } s; - struct cvmx_pcieep_cfg454_s cn52xx; - struct cvmx_pcieep_cfg454_s cn52xxp1; - struct cvmx_pcieep_cfg454_s cn56xx; - struct cvmx_pcieep_cfg454_s cn56xxp1; -}; - -union cvmx_pcieep_cfg455 { - uint32_t u32; - struct cvmx_pcieep_cfg455_s { - uint32_t m_cfg0_filt:1; - uint32_t m_io_filt:1; - uint32_t msg_ctrl:1; - uint32_t m_cpl_ecrc_filt:1; - uint32_t m_ecrc_filt:1; - uint32_t m_cpl_len_err:1; - uint32_t m_cpl_attr_err:1; - uint32_t m_cpl_tc_err:1; - uint32_t m_cpl_fun_err:1; - uint32_t m_cpl_rid_err:1; - uint32_t m_cpl_tag_err:1; - uint32_t m_lk_filt:1; - uint32_t m_cfg1_filt:1; - uint32_t m_bar_match:1; - uint32_t m_pois_filt:1; - uint32_t m_fun:1; - uint32_t dfcwt:1; - uint32_t reserved_11_14:4; - uint32_t skpiv:11; - } s; - struct cvmx_pcieep_cfg455_s cn52xx; - struct cvmx_pcieep_cfg455_s cn52xxp1; - struct cvmx_pcieep_cfg455_s cn56xx; - struct cvmx_pcieep_cfg455_s cn56xxp1; -}; - -union cvmx_pcieep_cfg456 { - uint32_t u32; - struct cvmx_pcieep_cfg456_s { - uint32_t reserved_2_31:30; - uint32_t m_vend1_drp:1; - uint32_t m_vend0_drp:1; - } s; - struct cvmx_pcieep_cfg456_s cn52xx; - struct cvmx_pcieep_cfg456_s cn52xxp1; - struct cvmx_pcieep_cfg456_s cn56xx; - struct cvmx_pcieep_cfg456_s cn56xxp1; -}; - -union cvmx_pcieep_cfg458 { - uint32_t u32; - struct cvmx_pcieep_cfg458_s { - uint32_t dbg_info_l32:32; - } s; - struct cvmx_pcieep_cfg458_s cn52xx; - struct cvmx_pcieep_cfg458_s cn52xxp1; - struct cvmx_pcieep_cfg458_s cn56xx; - struct cvmx_pcieep_cfg458_s cn56xxp1; -}; - -union cvmx_pcieep_cfg459 { - uint32_t u32; - struct cvmx_pcieep_cfg459_s { - uint32_t dbg_info_u32:32; - } s; - struct cvmx_pcieep_cfg459_s cn52xx; - struct cvmx_pcieep_cfg459_s cn52xxp1; - struct cvmx_pcieep_cfg459_s cn56xx; - struct cvmx_pcieep_cfg459_s cn56xxp1; -}; - -union cvmx_pcieep_cfg460 { - uint32_t u32; - struct cvmx_pcieep_cfg460_s { - uint32_t reserved_20_31:12; - uint32_t tphfcc:8; - uint32_t tpdfcc:12; - } s; - struct cvmx_pcieep_cfg460_s cn52xx; - struct cvmx_pcieep_cfg460_s cn52xxp1; - struct cvmx_pcieep_cfg460_s cn56xx; - struct cvmx_pcieep_cfg460_s cn56xxp1; -}; - -union cvmx_pcieep_cfg461 { - uint32_t u32; - struct cvmx_pcieep_cfg461_s { - uint32_t reserved_20_31:12; - uint32_t tchfcc:8; - uint32_t tcdfcc:12; - } s; - struct cvmx_pcieep_cfg461_s cn52xx; - struct cvmx_pcieep_cfg461_s cn52xxp1; - struct cvmx_pcieep_cfg461_s cn56xx; - struct cvmx_pcieep_cfg461_s cn56xxp1; -}; - -union cvmx_pcieep_cfg462 { - uint32_t u32; - struct cvmx_pcieep_cfg462_s { - uint32_t reserved_20_31:12; - uint32_t tchfcc:8; - uint32_t tcdfcc:12; - } s; - struct cvmx_pcieep_cfg462_s cn52xx; - struct cvmx_pcieep_cfg462_s cn52xxp1; - struct cvmx_pcieep_cfg462_s cn56xx; - struct cvmx_pcieep_cfg462_s cn56xxp1; -}; - -union cvmx_pcieep_cfg463 { - uint32_t u32; - struct cvmx_pcieep_cfg463_s { - uint32_t reserved_3_31:29; - uint32_t rqne:1; - uint32_t trbne:1; - uint32_t rtlpfccnr:1; - } s; - struct cvmx_pcieep_cfg463_s cn52xx; - struct cvmx_pcieep_cfg463_s cn52xxp1; - struct cvmx_pcieep_cfg463_s cn56xx; - struct cvmx_pcieep_cfg463_s cn56xxp1; -}; - -union cvmx_pcieep_cfg464 { - uint32_t u32; - struct cvmx_pcieep_cfg464_s { - uint32_t wrr_vc3:8; - uint32_t wrr_vc2:8; - uint32_t wrr_vc1:8; - uint32_t wrr_vc0:8; - } s; - struct cvmx_pcieep_cfg464_s cn52xx; - struct cvmx_pcieep_cfg464_s cn52xxp1; - struct cvmx_pcieep_cfg464_s cn56xx; - struct cvmx_pcieep_cfg464_s cn56xxp1; -}; - -union cvmx_pcieep_cfg465 { - uint32_t u32; - struct cvmx_pcieep_cfg465_s { - uint32_t wrr_vc7:8; - uint32_t wrr_vc6:8; - uint32_t wrr_vc5:8; - uint32_t wrr_vc4:8; - } s; - struct cvmx_pcieep_cfg465_s cn52xx; - struct cvmx_pcieep_cfg465_s cn52xxp1; - struct cvmx_pcieep_cfg465_s cn56xx; - struct cvmx_pcieep_cfg465_s cn56xxp1; -}; - -union cvmx_pcieep_cfg466 { - uint32_t u32; - struct cvmx_pcieep_cfg466_s { - uint32_t rx_queue_order:1; - uint32_t type_ordering:1; - uint32_t reserved_24_29:6; - uint32_t queue_mode:3; - uint32_t reserved_20_20:1; - uint32_t header_credits:8; - uint32_t data_credits:12; - } s; - struct cvmx_pcieep_cfg466_s cn52xx; - struct cvmx_pcieep_cfg466_s cn52xxp1; - struct cvmx_pcieep_cfg466_s cn56xx; - struct cvmx_pcieep_cfg466_s cn56xxp1; -}; - -union cvmx_pcieep_cfg467 { - uint32_t u32; - struct cvmx_pcieep_cfg467_s { - uint32_t reserved_24_31:8; - uint32_t queue_mode:3; - uint32_t reserved_20_20:1; - uint32_t header_credits:8; - uint32_t data_credits:12; - } s; - struct cvmx_pcieep_cfg467_s cn52xx; - struct cvmx_pcieep_cfg467_s cn52xxp1; - struct cvmx_pcieep_cfg467_s cn56xx; - struct cvmx_pcieep_cfg467_s cn56xxp1; -}; - -union cvmx_pcieep_cfg468 { - uint32_t u32; - struct cvmx_pcieep_cfg468_s { - uint32_t reserved_24_31:8; - uint32_t queue_mode:3; - uint32_t reserved_20_20:1; - uint32_t header_credits:8; - uint32_t data_credits:12; - } s; - struct cvmx_pcieep_cfg468_s cn52xx; - struct cvmx_pcieep_cfg468_s cn52xxp1; - struct cvmx_pcieep_cfg468_s cn56xx; - struct cvmx_pcieep_cfg468_s cn56xxp1; -}; - -union cvmx_pcieep_cfg490 { - uint32_t u32; - struct cvmx_pcieep_cfg490_s { - uint32_t reserved_26_31:6; - uint32_t header_depth:10; - uint32_t reserved_14_15:2; - uint32_t data_depth:14; - } s; - struct cvmx_pcieep_cfg490_s cn52xx; - struct cvmx_pcieep_cfg490_s cn52xxp1; - struct cvmx_pcieep_cfg490_s cn56xx; - struct cvmx_pcieep_cfg490_s cn56xxp1; -}; - -union cvmx_pcieep_cfg491 { - uint32_t u32; - struct cvmx_pcieep_cfg491_s { - uint32_t reserved_26_31:6; - uint32_t header_depth:10; - uint32_t reserved_14_15:2; - uint32_t data_depth:14; - } s; - struct cvmx_pcieep_cfg491_s cn52xx; - struct cvmx_pcieep_cfg491_s cn52xxp1; - struct cvmx_pcieep_cfg491_s cn56xx; - struct cvmx_pcieep_cfg491_s cn56xxp1; -}; - -union cvmx_pcieep_cfg492 { - uint32_t u32; - struct cvmx_pcieep_cfg492_s { - uint32_t reserved_26_31:6; - uint32_t header_depth:10; - uint32_t reserved_14_15:2; - uint32_t data_depth:14; - } s; - struct cvmx_pcieep_cfg492_s cn52xx; - struct cvmx_pcieep_cfg492_s cn52xxp1; - struct cvmx_pcieep_cfg492_s cn56xx; - struct cvmx_pcieep_cfg492_s cn56xxp1; -}; - -union cvmx_pcieep_cfg516 { - uint32_t u32; - struct cvmx_pcieep_cfg516_s { - uint32_t phy_stat:32; - } s; - struct cvmx_pcieep_cfg516_s cn52xx; - struct cvmx_pcieep_cfg516_s cn52xxp1; - struct cvmx_pcieep_cfg516_s cn56xx; - struct cvmx_pcieep_cfg516_s cn56xxp1; -}; - -union cvmx_pcieep_cfg517 { - uint32_t u32; - struct cvmx_pcieep_cfg517_s { - uint32_t phy_ctrl:32; - } s; - struct cvmx_pcieep_cfg517_s cn52xx; - struct cvmx_pcieep_cfg517_s cn52xxp1; - struct cvmx_pcieep_cfg517_s cn56xx; - struct cvmx_pcieep_cfg517_s cn56xxp1; -}; - -#endif diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h index 7b1dc8b74e5..4bce393391e 100644 --- a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2011 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -109,8 +109,13 @@ union cvmx_pciercx_cfg000 { uint32_t u32; struct cvmx_pciercx_cfg000_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t devid:16; uint32_t vendid:16; +#else + uint32_t vendid:16; + uint32_t devid:16; +#endif } s; struct cvmx_pciercx_cfg000_s cn52xx; struct cvmx_pciercx_cfg000_s cn52xxp1; @@ -122,11 +127,13 @@ union cvmx_pciercx_cfg000 { struct cvmx_pciercx_cfg000_s cn66xx; struct cvmx_pciercx_cfg000_s cn68xx; struct cvmx_pciercx_cfg000_s cn68xxp1; + struct cvmx_pciercx_cfg000_s cnf71xx; }; union cvmx_pciercx_cfg001 { uint32_t u32; struct cvmx_pciercx_cfg001_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t dpe:1; uint32_t sse:1; uint32_t rma:1; @@ -151,6 +158,32 @@ union cvmx_pciercx_cfg001 { uint32_t me:1; uint32_t msae:1; uint32_t isae:1; +#else + uint32_t isae:1; + uint32_t msae:1; + uint32_t me:1; + uint32_t scse:1; + uint32_t mwice:1; + uint32_t vps:1; + uint32_t per:1; + uint32_t ids_wcc:1; + uint32_t see:1; + uint32_t fbbe:1; + uint32_t i_dis:1; + uint32_t reserved_11_18:8; + uint32_t i_stat:1; + uint32_t cl:1; + uint32_t m66:1; + uint32_t reserved_22_22:1; + uint32_t fbb:1; + uint32_t mdpe:1; + uint32_t devt:2; + uint32_t sta:1; + uint32_t rta:1; + uint32_t rma:1; + uint32_t sse:1; + uint32_t dpe:1; +#endif } s; struct cvmx_pciercx_cfg001_s cn52xx; struct cvmx_pciercx_cfg001_s cn52xxp1; @@ -162,15 +195,23 @@ union cvmx_pciercx_cfg001 { struct cvmx_pciercx_cfg001_s cn66xx; struct cvmx_pciercx_cfg001_s cn68xx; struct cvmx_pciercx_cfg001_s cn68xxp1; + struct cvmx_pciercx_cfg001_s cnf71xx; }; union cvmx_pciercx_cfg002 { uint32_t u32; struct cvmx_pciercx_cfg002_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t bcc:8; uint32_t sc:8; uint32_t pi:8; uint32_t rid:8; +#else + uint32_t rid:8; + uint32_t pi:8; + uint32_t sc:8; + uint32_t bcc:8; +#endif } s; struct cvmx_pciercx_cfg002_s cn52xx; struct cvmx_pciercx_cfg002_s cn52xxp1; @@ -182,16 +223,25 @@ union cvmx_pciercx_cfg002 { struct cvmx_pciercx_cfg002_s cn66xx; struct cvmx_pciercx_cfg002_s cn68xx; struct cvmx_pciercx_cfg002_s cn68xxp1; + struct cvmx_pciercx_cfg002_s cnf71xx; }; union cvmx_pciercx_cfg003 { uint32_t u32; struct cvmx_pciercx_cfg003_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t bist:8; uint32_t mfd:1; uint32_t chf:7; uint32_t lt:8; uint32_t cls:8; +#else + uint32_t cls:8; + uint32_t lt:8; + uint32_t chf:7; + uint32_t mfd:1; + uint32_t bist:8; +#endif } s; struct cvmx_pciercx_cfg003_s cn52xx; struct cvmx_pciercx_cfg003_s cn52xxp1; @@ -203,12 +253,17 @@ union cvmx_pciercx_cfg003 { struct cvmx_pciercx_cfg003_s cn66xx; struct cvmx_pciercx_cfg003_s cn68xx; struct cvmx_pciercx_cfg003_s cn68xxp1; + struct cvmx_pciercx_cfg003_s cnf71xx; }; union cvmx_pciercx_cfg004 { uint32_t u32; struct cvmx_pciercx_cfg004_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_0_31:32; +#else uint32_t reserved_0_31:32; +#endif } s; struct cvmx_pciercx_cfg004_s cn52xx; struct cvmx_pciercx_cfg004_s cn52xxp1; @@ -220,12 +275,17 @@ union cvmx_pciercx_cfg004 { struct cvmx_pciercx_cfg004_s cn66xx; struct cvmx_pciercx_cfg004_s cn68xx; struct cvmx_pciercx_cfg004_s cn68xxp1; + struct cvmx_pciercx_cfg004_s cnf71xx; }; union cvmx_pciercx_cfg005 { uint32_t u32; struct cvmx_pciercx_cfg005_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_0_31:32; +#else uint32_t reserved_0_31:32; +#endif } s; struct cvmx_pciercx_cfg005_s cn52xx; struct cvmx_pciercx_cfg005_s cn52xxp1; @@ -237,15 +297,23 @@ union cvmx_pciercx_cfg005 { struct cvmx_pciercx_cfg005_s cn66xx; struct cvmx_pciercx_cfg005_s cn68xx; struct cvmx_pciercx_cfg005_s cn68xxp1; + struct cvmx_pciercx_cfg005_s cnf71xx; }; union cvmx_pciercx_cfg006 { uint32_t u32; struct cvmx_pciercx_cfg006_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t slt:8; uint32_t subbnum:8; uint32_t sbnum:8; uint32_t pbnum:8; +#else + uint32_t pbnum:8; + uint32_t sbnum:8; + uint32_t subbnum:8; + uint32_t slt:8; +#endif } s; struct cvmx_pciercx_cfg006_s cn52xx; struct cvmx_pciercx_cfg006_s cn52xxp1; @@ -257,11 +325,13 @@ union cvmx_pciercx_cfg006 { struct cvmx_pciercx_cfg006_s cn66xx; struct cvmx_pciercx_cfg006_s cn68xx; struct cvmx_pciercx_cfg006_s cn68xxp1; + struct cvmx_pciercx_cfg006_s cnf71xx; }; union cvmx_pciercx_cfg007 { uint32_t u32; struct cvmx_pciercx_cfg007_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t dpe:1; uint32_t sse:1; uint32_t rma:1; @@ -279,6 +349,25 @@ union cvmx_pciercx_cfg007 { uint32_t lio_base:4; uint32_t reserved_1_3:3; uint32_t io32a:1; +#else + uint32_t io32a:1; + uint32_t reserved_1_3:3; + uint32_t lio_base:4; + uint32_t io32b:1; + uint32_t reserved_9_11:3; + uint32_t lio_limi:4; + uint32_t reserved_16_20:5; + uint32_t m66:1; + uint32_t reserved_22_22:1; + uint32_t fbb:1; + uint32_t mdpe:1; + uint32_t devt:2; + uint32_t sta:1; + uint32_t rta:1; + uint32_t rma:1; + uint32_t sse:1; + uint32_t dpe:1; +#endif } s; struct cvmx_pciercx_cfg007_s cn52xx; struct cvmx_pciercx_cfg007_s cn52xxp1; @@ -290,15 +379,23 @@ union cvmx_pciercx_cfg007 { struct cvmx_pciercx_cfg007_s cn66xx; struct cvmx_pciercx_cfg007_s cn68xx; struct cvmx_pciercx_cfg007_s cn68xxp1; + struct cvmx_pciercx_cfg007_s cnf71xx; }; union cvmx_pciercx_cfg008 { uint32_t u32; struct cvmx_pciercx_cfg008_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t ml_addr:12; uint32_t reserved_16_19:4; uint32_t mb_addr:12; uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t mb_addr:12; + uint32_t reserved_16_19:4; + uint32_t ml_addr:12; +#endif } s; struct cvmx_pciercx_cfg008_s cn52xx; struct cvmx_pciercx_cfg008_s cn52xxp1; @@ -310,17 +407,27 @@ union cvmx_pciercx_cfg008 { struct cvmx_pciercx_cfg008_s cn66xx; struct cvmx_pciercx_cfg008_s cn68xx; struct cvmx_pciercx_cfg008_s cn68xxp1; + struct cvmx_pciercx_cfg008_s cnf71xx; }; union cvmx_pciercx_cfg009 { uint32_t u32; struct cvmx_pciercx_cfg009_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t lmem_limit:12; uint32_t reserved_17_19:3; uint32_t mem64b:1; uint32_t lmem_base:12; uint32_t reserved_1_3:3; uint32_t mem64a:1; +#else + uint32_t mem64a:1; + uint32_t reserved_1_3:3; + uint32_t lmem_base:12; + uint32_t mem64b:1; + uint32_t reserved_17_19:3; + uint32_t lmem_limit:12; +#endif } s; struct cvmx_pciercx_cfg009_s cn52xx; struct cvmx_pciercx_cfg009_s cn52xxp1; @@ -332,12 +439,17 @@ union cvmx_pciercx_cfg009 { struct cvmx_pciercx_cfg009_s cn66xx; struct cvmx_pciercx_cfg009_s cn68xx; struct cvmx_pciercx_cfg009_s cn68xxp1; + struct cvmx_pciercx_cfg009_s cnf71xx; }; union cvmx_pciercx_cfg010 { uint32_t u32; struct cvmx_pciercx_cfg010_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t umem_base:32; +#else + uint32_t umem_base:32; +#endif } s; struct cvmx_pciercx_cfg010_s cn52xx; struct cvmx_pciercx_cfg010_s cn52xxp1; @@ -349,12 +461,17 @@ union cvmx_pciercx_cfg010 { struct cvmx_pciercx_cfg010_s cn66xx; struct cvmx_pciercx_cfg010_s cn68xx; struct cvmx_pciercx_cfg010_s cn68xxp1; + struct cvmx_pciercx_cfg010_s cnf71xx; }; union cvmx_pciercx_cfg011 { uint32_t u32; struct cvmx_pciercx_cfg011_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t umem_limit:32; +#else + uint32_t umem_limit:32; +#endif } s; struct cvmx_pciercx_cfg011_s cn52xx; struct cvmx_pciercx_cfg011_s cn52xxp1; @@ -366,13 +483,19 @@ union cvmx_pciercx_cfg011 { struct cvmx_pciercx_cfg011_s cn66xx; struct cvmx_pciercx_cfg011_s cn68xx; struct cvmx_pciercx_cfg011_s cn68xxp1; + struct cvmx_pciercx_cfg011_s cnf71xx; }; union cvmx_pciercx_cfg012 { uint32_t u32; struct cvmx_pciercx_cfg012_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t uio_limit:16; uint32_t uio_base:16; +#else + uint32_t uio_base:16; + uint32_t uio_limit:16; +#endif } s; struct cvmx_pciercx_cfg012_s cn52xx; struct cvmx_pciercx_cfg012_s cn52xxp1; @@ -384,13 +507,19 @@ union cvmx_pciercx_cfg012 { struct cvmx_pciercx_cfg012_s cn66xx; struct cvmx_pciercx_cfg012_s cn68xx; struct cvmx_pciercx_cfg012_s cn68xxp1; + struct cvmx_pciercx_cfg012_s cnf71xx; }; union cvmx_pciercx_cfg013 { uint32_t u32; struct cvmx_pciercx_cfg013_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_8_31:24; uint32_t cp:8; +#else + uint32_t cp:8; + uint32_t reserved_8_31:24; +#endif } s; struct cvmx_pciercx_cfg013_s cn52xx; struct cvmx_pciercx_cfg013_s cn52xxp1; @@ -402,12 +531,17 @@ union cvmx_pciercx_cfg013 { struct cvmx_pciercx_cfg013_s cn66xx; struct cvmx_pciercx_cfg013_s cn68xx; struct cvmx_pciercx_cfg013_s cn68xxp1; + struct cvmx_pciercx_cfg013_s cnf71xx; }; union cvmx_pciercx_cfg014 { uint32_t u32; struct cvmx_pciercx_cfg014_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_0_31:32; +#else uint32_t reserved_0_31:32; +#endif } s; struct cvmx_pciercx_cfg014_s cn52xx; struct cvmx_pciercx_cfg014_s cn52xxp1; @@ -419,11 +553,13 @@ union cvmx_pciercx_cfg014 { struct cvmx_pciercx_cfg014_s cn66xx; struct cvmx_pciercx_cfg014_s cn68xx; struct cvmx_pciercx_cfg014_s cn68xxp1; + struct cvmx_pciercx_cfg014_s cnf71xx; }; union cvmx_pciercx_cfg015 { uint32_t u32; struct cvmx_pciercx_cfg015_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_28_31:4; uint32_t dtsees:1; uint32_t dts:1; @@ -439,6 +575,23 @@ union cvmx_pciercx_cfg015 { uint32_t pere:1; uint32_t inta:8; uint32_t il:8; +#else + uint32_t il:8; + uint32_t inta:8; + uint32_t pere:1; + uint32_t see:1; + uint32_t isae:1; + uint32_t vgae:1; + uint32_t vga16d:1; + uint32_t mam:1; + uint32_t sbrst:1; + uint32_t fbbe:1; + uint32_t pdt:1; + uint32_t sdt:1; + uint32_t dts:1; + uint32_t dtsees:1; + uint32_t reserved_28_31:4; +#endif } s; struct cvmx_pciercx_cfg015_s cn52xx; struct cvmx_pciercx_cfg015_s cn52xxp1; @@ -450,11 +603,13 @@ union cvmx_pciercx_cfg015 { struct cvmx_pciercx_cfg015_s cn66xx; struct cvmx_pciercx_cfg015_s cn68xx; struct cvmx_pciercx_cfg015_s cn68xxp1; + struct cvmx_pciercx_cfg015_s cnf71xx; }; union cvmx_pciercx_cfg016 { uint32_t u32; struct cvmx_pciercx_cfg016_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pmes:5; uint32_t d2s:1; uint32_t d1s:1; @@ -465,6 +620,18 @@ union cvmx_pciercx_cfg016 { uint32_t pmsv:3; uint32_t ncp:8; uint32_t pmcid:8; +#else + uint32_t pmcid:8; + uint32_t ncp:8; + uint32_t pmsv:3; + uint32_t pme_clock:1; + uint32_t reserved_20_20:1; + uint32_t dsi:1; + uint32_t auxc:3; + uint32_t d1s:1; + uint32_t d2s:1; + uint32_t pmes:5; +#endif } s; struct cvmx_pciercx_cfg016_s cn52xx; struct cvmx_pciercx_cfg016_s cn52xxp1; @@ -476,11 +643,13 @@ union cvmx_pciercx_cfg016 { struct cvmx_pciercx_cfg016_s cn66xx; struct cvmx_pciercx_cfg016_s cn68xx; struct cvmx_pciercx_cfg016_s cn68xxp1; + struct cvmx_pciercx_cfg016_s cnf71xx; }; union cvmx_pciercx_cfg017 { uint32_t u32; struct cvmx_pciercx_cfg017_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pmdia:8; uint32_t bpccee:1; uint32_t bd3h:1; @@ -493,6 +662,20 @@ union cvmx_pciercx_cfg017 { uint32_t nsr:1; uint32_t reserved_2_2:1; uint32_t ps:2; +#else + uint32_t ps:2; + uint32_t reserved_2_2:1; + uint32_t nsr:1; + uint32_t reserved_4_7:4; + uint32_t pmeens:1; + uint32_t pmds:4; + uint32_t pmedsia:2; + uint32_t pmess:1; + uint32_t reserved_16_21:6; + uint32_t bd3h:1; + uint32_t bpccee:1; + uint32_t pmdia:8; +#endif } s; struct cvmx_pciercx_cfg017_s cn52xx; struct cvmx_pciercx_cfg017_s cn52xxp1; @@ -504,11 +687,13 @@ union cvmx_pciercx_cfg017 { struct cvmx_pciercx_cfg017_s cn66xx; struct cvmx_pciercx_cfg017_s cn68xx; struct cvmx_pciercx_cfg017_s cn68xxp1; + struct cvmx_pciercx_cfg017_s cnf71xx; }; union cvmx_pciercx_cfg020 { uint32_t u32; struct cvmx_pciercx_cfg020_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_25_31:7; uint32_t pvm:1; uint32_t m64:1; @@ -517,8 +702,19 @@ union cvmx_pciercx_cfg020 { uint32_t msien:1; uint32_t ncp:8; uint32_t msicid:8; +#else + uint32_t msicid:8; + uint32_t ncp:8; + uint32_t msien:1; + uint32_t mmc:3; + uint32_t mme:3; + uint32_t m64:1; + uint32_t pvm:1; + uint32_t reserved_25_31:7; +#endif } s; struct cvmx_pciercx_cfg020_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_24_31:8; uint32_t m64:1; uint32_t mme:3; @@ -526,6 +722,15 @@ union cvmx_pciercx_cfg020 { uint32_t msien:1; uint32_t ncp:8; uint32_t msicid:8; +#else + uint32_t msicid:8; + uint32_t ncp:8; + uint32_t msien:1; + uint32_t mmc:3; + uint32_t mme:3; + uint32_t m64:1; + uint32_t reserved_24_31:8; +#endif } cn52xx; struct cvmx_pciercx_cfg020_cn52xx cn52xxp1; struct cvmx_pciercx_cfg020_cn52xx cn56xx; @@ -536,13 +741,19 @@ union cvmx_pciercx_cfg020 { struct cvmx_pciercx_cfg020_cn52xx cn66xx; struct cvmx_pciercx_cfg020_cn52xx cn68xx; struct cvmx_pciercx_cfg020_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg020_s cnf71xx; }; union cvmx_pciercx_cfg021 { uint32_t u32; struct cvmx_pciercx_cfg021_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t lmsi:30; uint32_t reserved_0_1:2; +#else + uint32_t reserved_0_1:2; + uint32_t lmsi:30; +#endif } s; struct cvmx_pciercx_cfg021_s cn52xx; struct cvmx_pciercx_cfg021_s cn52xxp1; @@ -554,12 +765,17 @@ union cvmx_pciercx_cfg021 { struct cvmx_pciercx_cfg021_s cn66xx; struct cvmx_pciercx_cfg021_s cn68xx; struct cvmx_pciercx_cfg021_s cn68xxp1; + struct cvmx_pciercx_cfg021_s cnf71xx; }; union cvmx_pciercx_cfg022 { uint32_t u32; struct cvmx_pciercx_cfg022_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t umsi:32; +#else + uint32_t umsi:32; +#endif } s; struct cvmx_pciercx_cfg022_s cn52xx; struct cvmx_pciercx_cfg022_s cn52xxp1; @@ -571,13 +787,19 @@ union cvmx_pciercx_cfg022 { struct cvmx_pciercx_cfg022_s cn66xx; struct cvmx_pciercx_cfg022_s cn68xx; struct cvmx_pciercx_cfg022_s cn68xxp1; + struct cvmx_pciercx_cfg022_s cnf71xx; }; union cvmx_pciercx_cfg023 { uint32_t u32; struct cvmx_pciercx_cfg023_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_16_31:16; uint32_t msimd:16; +#else + uint32_t msimd:16; + uint32_t reserved_16_31:16; +#endif } s; struct cvmx_pciercx_cfg023_s cn52xx; struct cvmx_pciercx_cfg023_s cn52xxp1; @@ -589,11 +811,13 @@ union cvmx_pciercx_cfg023 { struct cvmx_pciercx_cfg023_s cn66xx; struct cvmx_pciercx_cfg023_s cn68xx; struct cvmx_pciercx_cfg023_s cn68xxp1; + struct cvmx_pciercx_cfg023_s cnf71xx; }; union cvmx_pciercx_cfg028 { uint32_t u32; struct cvmx_pciercx_cfg028_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_30_31:2; uint32_t imn:5; uint32_t si:1; @@ -601,6 +825,15 @@ union cvmx_pciercx_cfg028 { uint32_t pciecv:4; uint32_t ncp:8; uint32_t pcieid:8; +#else + uint32_t pcieid:8; + uint32_t ncp:8; + uint32_t pciecv:4; + uint32_t dpt:4; + uint32_t si:1; + uint32_t imn:5; + uint32_t reserved_30_31:2; +#endif } s; struct cvmx_pciercx_cfg028_s cn52xx; struct cvmx_pciercx_cfg028_s cn52xxp1; @@ -612,11 +845,13 @@ union cvmx_pciercx_cfg028 { struct cvmx_pciercx_cfg028_s cn66xx; struct cvmx_pciercx_cfg028_s cn68xx; struct cvmx_pciercx_cfg028_s cn68xxp1; + struct cvmx_pciercx_cfg028_s cnf71xx; }; union cvmx_pciercx_cfg029 { uint32_t u32; struct cvmx_pciercx_cfg029_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_28_31:4; uint32_t cspls:2; uint32_t csplv:8; @@ -628,6 +863,19 @@ union cvmx_pciercx_cfg029 { uint32_t etfs:1; uint32_t pfs:2; uint32_t mpss:3; +#else + uint32_t mpss:3; + uint32_t pfs:2; + uint32_t etfs:1; + uint32_t el0al:3; + uint32_t el1al:3; + uint32_t reserved_12_14:3; + uint32_t rber:1; + uint32_t reserved_16_17:2; + uint32_t csplv:8; + uint32_t cspls:2; + uint32_t reserved_28_31:4; +#endif } s; struct cvmx_pciercx_cfg029_s cn52xx; struct cvmx_pciercx_cfg029_s cn52xxp1; @@ -639,11 +887,13 @@ union cvmx_pciercx_cfg029 { struct cvmx_pciercx_cfg029_s cn66xx; struct cvmx_pciercx_cfg029_s cn68xx; struct cvmx_pciercx_cfg029_s cn68xxp1; + struct cvmx_pciercx_cfg029_s cnf71xx; }; union cvmx_pciercx_cfg030 { uint32_t u32; struct cvmx_pciercx_cfg030_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_22_31:10; uint32_t tp:1; uint32_t ap_d:1; @@ -663,6 +913,27 @@ union cvmx_pciercx_cfg030 { uint32_t fe_en:1; uint32_t nfe_en:1; uint32_t ce_en:1; +#else + uint32_t ce_en:1; + uint32_t nfe_en:1; + uint32_t fe_en:1; + uint32_t ur_en:1; + uint32_t ro_en:1; + uint32_t mps:3; + uint32_t etf_en:1; + uint32_t pf_en:1; + uint32_t ap_en:1; + uint32_t ns_en:1; + uint32_t mrrs:3; + uint32_t reserved_15_15:1; + uint32_t ce_d:1; + uint32_t nfe_d:1; + uint32_t fe_d:1; + uint32_t ur_d:1; + uint32_t ap_d:1; + uint32_t tp:1; + uint32_t reserved_22_31:10; +#endif } s; struct cvmx_pciercx_cfg030_s cn52xx; struct cvmx_pciercx_cfg030_s cn52xxp1; @@ -674,11 +945,13 @@ union cvmx_pciercx_cfg030 { struct cvmx_pciercx_cfg030_s cn66xx; struct cvmx_pciercx_cfg030_s cn68xx; struct cvmx_pciercx_cfg030_s cn68xxp1; + struct cvmx_pciercx_cfg030_s cnf71xx; }; union cvmx_pciercx_cfg031 { uint32_t u32; struct cvmx_pciercx_cfg031_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pnum:8; uint32_t reserved_23_23:1; uint32_t aspm:1; @@ -691,8 +964,23 @@ union cvmx_pciercx_cfg031 { uint32_t aslpms:2; uint32_t mlw:6; uint32_t mls:4; +#else + uint32_t mls:4; + uint32_t mlw:6; + uint32_t aslpms:2; + uint32_t l0el:3; + uint32_t l1el:3; + uint32_t cpm:1; + uint32_t sderc:1; + uint32_t dllarc:1; + uint32_t lbnc:1; + uint32_t aspm:1; + uint32_t reserved_23_23:1; + uint32_t pnum:8; +#endif } s; struct cvmx_pciercx_cfg031_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pnum:8; uint32_t reserved_22_23:2; uint32_t lbnc:1; @@ -704,6 +992,19 @@ union cvmx_pciercx_cfg031 { uint32_t aslpms:2; uint32_t mlw:6; uint32_t mls:4; +#else + uint32_t mls:4; + uint32_t mlw:6; + uint32_t aslpms:2; + uint32_t l0el:3; + uint32_t l1el:3; + uint32_t cpm:1; + uint32_t sderc:1; + uint32_t dllarc:1; + uint32_t lbnc:1; + uint32_t reserved_22_23:2; + uint32_t pnum:8; +#endif } cn52xx; struct cvmx_pciercx_cfg031_cn52xx cn52xxp1; struct cvmx_pciercx_cfg031_cn52xx cn56xx; @@ -714,11 +1015,13 @@ union cvmx_pciercx_cfg031 { struct cvmx_pciercx_cfg031_s cn66xx; struct cvmx_pciercx_cfg031_s cn68xx; struct cvmx_pciercx_cfg031_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg031_s cnf71xx; }; union cvmx_pciercx_cfg032 { uint32_t u32; struct cvmx_pciercx_cfg032_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t lab:1; uint32_t lbm:1; uint32_t dlla:1; @@ -739,6 +1042,28 @@ union cvmx_pciercx_cfg032 { uint32_t rcb:1; uint32_t reserved_2_2:1; uint32_t aslpc:2; +#else + uint32_t aslpc:2; + uint32_t reserved_2_2:1; + uint32_t rcb:1; + uint32_t ld:1; + uint32_t rl:1; + uint32_t ccc:1; + uint32_t es:1; + uint32_t ecpm:1; + uint32_t hawd:1; + uint32_t lbm_int_enb:1; + uint32_t lab_int_enb:1; + uint32_t reserved_12_15:4; + uint32_t ls:4; + uint32_t nlw:6; + uint32_t reserved_26_26:1; + uint32_t lt:1; + uint32_t scc:1; + uint32_t dlla:1; + uint32_t lbm:1; + uint32_t lab:1; +#endif } s; struct cvmx_pciercx_cfg032_s cn52xx; struct cvmx_pciercx_cfg032_s cn52xxp1; @@ -750,11 +1075,13 @@ union cvmx_pciercx_cfg032 { struct cvmx_pciercx_cfg032_s cn66xx; struct cvmx_pciercx_cfg032_s cn68xx; struct cvmx_pciercx_cfg032_s cn68xxp1; + struct cvmx_pciercx_cfg032_s cnf71xx; }; union cvmx_pciercx_cfg033 { uint32_t u32; struct cvmx_pciercx_cfg033_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t ps_num:13; uint32_t nccs:1; uint32_t emip:1; @@ -767,6 +1094,20 @@ union cvmx_pciercx_cfg033 { uint32_t mrlsp:1; uint32_t pcp:1; uint32_t abp:1; +#else + uint32_t abp:1; + uint32_t pcp:1; + uint32_t mrlsp:1; + uint32_t aip:1; + uint32_t pip:1; + uint32_t hp_s:1; + uint32_t hp_c:1; + uint32_t sp_lv:8; + uint32_t sp_ls:2; + uint32_t emip:1; + uint32_t nccs:1; + uint32_t ps_num:13; +#endif } s; struct cvmx_pciercx_cfg033_s cn52xx; struct cvmx_pciercx_cfg033_s cn52xxp1; @@ -778,11 +1119,13 @@ union cvmx_pciercx_cfg033 { struct cvmx_pciercx_cfg033_s cn66xx; struct cvmx_pciercx_cfg033_s cn68xx; struct cvmx_pciercx_cfg033_s cn68xxp1; + struct cvmx_pciercx_cfg033_s cnf71xx; }; union cvmx_pciercx_cfg034 { uint32_t u32; struct cvmx_pciercx_cfg034_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_25_31:7; uint32_t dlls_c:1; uint32_t emis:1; @@ -805,6 +1148,30 @@ union cvmx_pciercx_cfg034 { uint32_t mrls_en:1; uint32_t pf_en:1; uint32_t abp_en:1; +#else + uint32_t abp_en:1; + uint32_t pf_en:1; + uint32_t mrls_en:1; + uint32_t pd_en:1; + uint32_t ccint_en:1; + uint32_t hpint_en:1; + uint32_t aic:2; + uint32_t pic:2; + uint32_t pcc:1; + uint32_t emic:1; + uint32_t dlls_en:1; + uint32_t reserved_13_15:3; + uint32_t abp_d:1; + uint32_t pf_d:1; + uint32_t mrls_c:1; + uint32_t pd_c:1; + uint32_t ccint_d:1; + uint32_t mrlss:1; + uint32_t pds:1; + uint32_t emis:1; + uint32_t dlls_c:1; + uint32_t reserved_25_31:7; +#endif } s; struct cvmx_pciercx_cfg034_s cn52xx; struct cvmx_pciercx_cfg034_s cn52xxp1; @@ -816,11 +1183,13 @@ union cvmx_pciercx_cfg034 { struct cvmx_pciercx_cfg034_s cn66xx; struct cvmx_pciercx_cfg034_s cn68xx; struct cvmx_pciercx_cfg034_s cn68xxp1; + struct cvmx_pciercx_cfg034_s cnf71xx; }; union cvmx_pciercx_cfg035 { uint32_t u32; struct cvmx_pciercx_cfg035_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_17_31:15; uint32_t crssv:1; uint32_t reserved_5_15:11; @@ -829,6 +1198,16 @@ union cvmx_pciercx_cfg035 { uint32_t sefee:1; uint32_t senfee:1; uint32_t secee:1; +#else + uint32_t secee:1; + uint32_t senfee:1; + uint32_t sefee:1; + uint32_t pmeie:1; + uint32_t crssve:1; + uint32_t reserved_5_15:11; + uint32_t crssv:1; + uint32_t reserved_17_31:15; +#endif } s; struct cvmx_pciercx_cfg035_s cn52xx; struct cvmx_pciercx_cfg035_s cn52xxp1; @@ -840,15 +1219,23 @@ union cvmx_pciercx_cfg035 { struct cvmx_pciercx_cfg035_s cn66xx; struct cvmx_pciercx_cfg035_s cn68xx; struct cvmx_pciercx_cfg035_s cn68xxp1; + struct cvmx_pciercx_cfg035_s cnf71xx; }; union cvmx_pciercx_cfg036 { uint32_t u32; struct cvmx_pciercx_cfg036_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_18_31:14; uint32_t pme_pend:1; uint32_t pme_stat:1; uint32_t pme_rid:16; +#else + uint32_t pme_rid:16; + uint32_t pme_stat:1; + uint32_t pme_pend:1; + uint32_t reserved_18_31:14; +#endif } s; struct cvmx_pciercx_cfg036_s cn52xx; struct cvmx_pciercx_cfg036_s cn52xxp1; @@ -860,14 +1247,17 @@ union cvmx_pciercx_cfg036 { struct cvmx_pciercx_cfg036_s cn66xx; struct cvmx_pciercx_cfg036_s cn68xx; struct cvmx_pciercx_cfg036_s cn68xxp1; + struct cvmx_pciercx_cfg036_s cnf71xx; }; union cvmx_pciercx_cfg037 { uint32_t u32; struct cvmx_pciercx_cfg037_s { - uint32_t reserved_14_31:18; - uint32_t tph:2; - uint32_t reserved_11_11:1; +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_20_31:12; + uint32_t obffs:2; + uint32_t reserved_12_17:6; + uint32_t ltrs:1; uint32_t noroprpr:1; uint32_t atom128s:1; uint32_t atom64s:1; @@ -876,16 +1266,37 @@ union cvmx_pciercx_cfg037 { uint32_t reserved_5_5:1; uint32_t ctds:1; uint32_t ctrs:4; +#else + uint32_t ctrs:4; + uint32_t ctds:1; + uint32_t reserved_5_5:1; + uint32_t atom_ops:1; + uint32_t atom32s:1; + uint32_t atom64s:1; + uint32_t atom128s:1; + uint32_t noroprpr:1; + uint32_t ltrs:1; + uint32_t reserved_12_17:6; + uint32_t obffs:2; + uint32_t reserved_20_31:12; +#endif } s; struct cvmx_pciercx_cfg037_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_5_31:27; uint32_t ctds:1; uint32_t ctrs:4; +#else + uint32_t ctrs:4; + uint32_t ctds:1; + uint32_t reserved_5_31:27; +#endif } cn52xx; struct cvmx_pciercx_cfg037_cn52xx cn52xxp1; struct cvmx_pciercx_cfg037_cn52xx cn56xx; struct cvmx_pciercx_cfg037_cn52xx cn56xxp1; struct cvmx_pciercx_cfg037_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_14_31:18; uint32_t tph:2; uint32_t reserved_11_11:1; @@ -897,10 +1308,24 @@ union cvmx_pciercx_cfg037 { uint32_t ari_fw:1; uint32_t ctds:1; uint32_t ctrs:4; +#else + uint32_t ctrs:4; + uint32_t ctds:1; + uint32_t ari_fw:1; + uint32_t atom_ops:1; + uint32_t atom32s:1; + uint32_t atom64s:1; + uint32_t atom128s:1; + uint32_t noroprpr:1; + uint32_t reserved_11_11:1; + uint32_t tph:2; + uint32_t reserved_14_31:18; +#endif } cn61xx; struct cvmx_pciercx_cfg037_cn52xx cn63xx; struct cvmx_pciercx_cfg037_cn52xx cn63xxp1; struct cvmx_pciercx_cfg037_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_14_31:18; uint32_t tph:2; uint32_t reserved_11_11:1; @@ -912,15 +1337,63 @@ union cvmx_pciercx_cfg037 { uint32_t ari:1; uint32_t ctds:1; uint32_t ctrs:4; +#else + uint32_t ctrs:4; + uint32_t ctds:1; + uint32_t ari:1; + uint32_t atom_ops:1; + uint32_t atom32s:1; + uint32_t atom64s:1; + uint32_t atom128s:1; + uint32_t noroprpr:1; + uint32_t reserved_11_11:1; + uint32_t tph:2; + uint32_t reserved_14_31:18; +#endif } cn66xx; struct cvmx_pciercx_cfg037_cn66xx cn68xx; struct cvmx_pciercx_cfg037_cn66xx cn68xxp1; + struct cvmx_pciercx_cfg037_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_20_31:12; + uint32_t obffs:2; + uint32_t reserved_14_17:4; + uint32_t tphs:2; + uint32_t ltrs:1; + uint32_t noroprpr:1; + uint32_t atom128s:1; + uint32_t atom64s:1; + uint32_t atom32s:1; + uint32_t atom_ops:1; + uint32_t ari_fw:1; + uint32_t ctds:1; + uint32_t ctrs:4; +#else + uint32_t ctrs:4; + uint32_t ctds:1; + uint32_t ari_fw:1; + uint32_t atom_ops:1; + uint32_t atom32s:1; + uint32_t atom64s:1; + uint32_t atom128s:1; + uint32_t noroprpr:1; + uint32_t ltrs:1; + uint32_t tphs:2; + uint32_t reserved_14_17:4; + uint32_t obffs:2; + uint32_t reserved_20_31:12; +#endif + } cnf71xx; }; union cvmx_pciercx_cfg038 { uint32_t u32; struct cvmx_pciercx_cfg038_s { - uint32_t reserved_10_31:22; +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_15_31:17; + uint32_t obffe:2; + uint32_t reserved_11_12:2; + uint32_t ltre:1; uint32_t id0_cp:1; uint32_t id0_rq:1; uint32_t atom_op_eb:1; @@ -928,33 +1401,84 @@ union cvmx_pciercx_cfg038 { uint32_t ari:1; uint32_t ctd:1; uint32_t ctv:4; +#else + uint32_t ctv:4; + uint32_t ctd:1; + uint32_t ari:1; + uint32_t atom_op:1; + uint32_t atom_op_eb:1; + uint32_t id0_rq:1; + uint32_t id0_cp:1; + uint32_t ltre:1; + uint32_t reserved_11_12:2; + uint32_t obffe:2; + uint32_t reserved_15_31:17; +#endif } s; struct cvmx_pciercx_cfg038_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_5_31:27; uint32_t ctd:1; uint32_t ctv:4; +#else + uint32_t ctv:4; + uint32_t ctd:1; + uint32_t reserved_5_31:27; +#endif } cn52xx; struct cvmx_pciercx_cfg038_cn52xx cn52xxp1; struct cvmx_pciercx_cfg038_cn52xx cn56xx; struct cvmx_pciercx_cfg038_cn52xx cn56xxp1; - struct cvmx_pciercx_cfg038_s cn61xx; + struct cvmx_pciercx_cfg038_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_10_31:22; + uint32_t id0_cp:1; + uint32_t id0_rq:1; + uint32_t atom_op_eb:1; + uint32_t atom_op:1; + uint32_t ari:1; + uint32_t ctd:1; + uint32_t ctv:4; +#else + uint32_t ctv:4; + uint32_t ctd:1; + uint32_t ari:1; + uint32_t atom_op:1; + uint32_t atom_op_eb:1; + uint32_t id0_rq:1; + uint32_t id0_cp:1; + uint32_t reserved_10_31:22; +#endif + } cn61xx; struct cvmx_pciercx_cfg038_cn52xx cn63xx; struct cvmx_pciercx_cfg038_cn52xx cn63xxp1; - struct cvmx_pciercx_cfg038_s cn66xx; - struct cvmx_pciercx_cfg038_s cn68xx; - struct cvmx_pciercx_cfg038_s cn68xxp1; + struct cvmx_pciercx_cfg038_cn61xx cn66xx; + struct cvmx_pciercx_cfg038_cn61xx cn68xx; + struct cvmx_pciercx_cfg038_cn61xx cn68xxp1; + struct cvmx_pciercx_cfg038_s cnf71xx; }; union cvmx_pciercx_cfg039 { uint32_t u32; struct cvmx_pciercx_cfg039_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_9_31:23; uint32_t cls:1; uint32_t slsv:7; uint32_t reserved_0_0:1; +#else + uint32_t reserved_0_0:1; + uint32_t slsv:7; + uint32_t cls:1; + uint32_t reserved_9_31:23; +#endif } s; struct cvmx_pciercx_cfg039_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_0_31:32; +#else uint32_t reserved_0_31:32; +#endif } cn52xx; struct cvmx_pciercx_cfg039_cn52xx cn52xxp1; struct cvmx_pciercx_cfg039_cn52xx cn56xx; @@ -965,11 +1489,13 @@ union cvmx_pciercx_cfg039 { struct cvmx_pciercx_cfg039_s cn66xx; struct cvmx_pciercx_cfg039_s cn68xx; struct cvmx_pciercx_cfg039_s cn68xxp1; + struct cvmx_pciercx_cfg039_s cnf71xx; }; union cvmx_pciercx_cfg040 { uint32_t u32; struct cvmx_pciercx_cfg040_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_17_31:15; uint32_t cdl:1; uint32_t reserved_13_15:3; @@ -981,9 +1507,26 @@ union cvmx_pciercx_cfg040 { uint32_t hasd:1; uint32_t ec:1; uint32_t tls:4; +#else + uint32_t tls:4; + uint32_t ec:1; + uint32_t hasd:1; + uint32_t sde:1; + uint32_t tm:3; + uint32_t emc:1; + uint32_t csos:1; + uint32_t cde:1; + uint32_t reserved_13_15:3; + uint32_t cdl:1; + uint32_t reserved_17_31:15; +#endif } s; struct cvmx_pciercx_cfg040_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_0_31:32; +#else uint32_t reserved_0_31:32; +#endif } cn52xx; struct cvmx_pciercx_cfg040_cn52xx cn52xxp1; struct cvmx_pciercx_cfg040_cn52xx cn56xx; @@ -994,12 +1537,17 @@ union cvmx_pciercx_cfg040 { struct cvmx_pciercx_cfg040_s cn66xx; struct cvmx_pciercx_cfg040_s cn68xx; struct cvmx_pciercx_cfg040_s cn68xxp1; + struct cvmx_pciercx_cfg040_s cnf71xx; }; union cvmx_pciercx_cfg041 { uint32_t u32; struct cvmx_pciercx_cfg041_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_0_31:32; +#else uint32_t reserved_0_31:32; +#endif } s; struct cvmx_pciercx_cfg041_s cn52xx; struct cvmx_pciercx_cfg041_s cn52xxp1; @@ -1011,12 +1559,17 @@ union cvmx_pciercx_cfg041 { struct cvmx_pciercx_cfg041_s cn66xx; struct cvmx_pciercx_cfg041_s cn68xx; struct cvmx_pciercx_cfg041_s cn68xxp1; + struct cvmx_pciercx_cfg041_s cnf71xx; }; union cvmx_pciercx_cfg042 { uint32_t u32; struct cvmx_pciercx_cfg042_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_0_31:32; +#else uint32_t reserved_0_31:32; +#endif } s; struct cvmx_pciercx_cfg042_s cn52xx; struct cvmx_pciercx_cfg042_s cn52xxp1; @@ -1028,14 +1581,21 @@ union cvmx_pciercx_cfg042 { struct cvmx_pciercx_cfg042_s cn66xx; struct cvmx_pciercx_cfg042_s cn68xx; struct cvmx_pciercx_cfg042_s cn68xxp1; + struct cvmx_pciercx_cfg042_s cnf71xx; }; union cvmx_pciercx_cfg064 { uint32_t u32; struct cvmx_pciercx_cfg064_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t nco:12; uint32_t cv:4; uint32_t pcieec:16; +#else + uint32_t pcieec:16; + uint32_t cv:4; + uint32_t nco:12; +#endif } s; struct cvmx_pciercx_cfg064_s cn52xx; struct cvmx_pciercx_cfg064_s cn52xxp1; @@ -1047,14 +1607,18 @@ union cvmx_pciercx_cfg064 { struct cvmx_pciercx_cfg064_s cn66xx; struct cvmx_pciercx_cfg064_s cn68xx; struct cvmx_pciercx_cfg064_s cn68xxp1; + struct cvmx_pciercx_cfg064_s cnf71xx; }; union cvmx_pciercx_cfg065 { uint32_t u32; struct cvmx_pciercx_cfg065_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_25_31:7; uint32_t uatombs:1; - uint32_t reserved_21_23:3; + uint32_t reserved_23_23:1; + uint32_t ucies:1; + uint32_t reserved_21_21:1; uint32_t ures:1; uint32_t ecrces:1; uint32_t mtlps:1; @@ -1068,8 +1632,29 @@ union cvmx_pciercx_cfg065 { uint32_t sdes:1; uint32_t dlpes:1; uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpes:1; + uint32_t sdes:1; + uint32_t reserved_6_11:6; + uint32_t ptlps:1; + uint32_t fcpes:1; + uint32_t cts:1; + uint32_t cas:1; + uint32_t ucs:1; + uint32_t ros:1; + uint32_t mtlps:1; + uint32_t ecrces:1; + uint32_t ures:1; + uint32_t reserved_21_21:1; + uint32_t ucies:1; + uint32_t reserved_23_23:1; + uint32_t uatombs:1; + uint32_t reserved_25_31:7; +#endif } s; struct cvmx_pciercx_cfg065_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_21_31:11; uint32_t ures:1; uint32_t ecrces:1; @@ -1084,24 +1669,80 @@ union cvmx_pciercx_cfg065 { uint32_t sdes:1; uint32_t dlpes:1; uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpes:1; + uint32_t sdes:1; + uint32_t reserved_6_11:6; + uint32_t ptlps:1; + uint32_t fcpes:1; + uint32_t cts:1; + uint32_t cas:1; + uint32_t ucs:1; + uint32_t ros:1; + uint32_t mtlps:1; + uint32_t ecrces:1; + uint32_t ures:1; + uint32_t reserved_21_31:11; +#endif } cn52xx; struct cvmx_pciercx_cfg065_cn52xx cn52xxp1; struct cvmx_pciercx_cfg065_cn52xx cn56xx; struct cvmx_pciercx_cfg065_cn52xx cn56xxp1; - struct cvmx_pciercx_cfg065_s cn61xx; + struct cvmx_pciercx_cfg065_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_25_31:7; + uint32_t uatombs:1; + uint32_t reserved_21_23:3; + uint32_t ures:1; + uint32_t ecrces:1; + uint32_t mtlps:1; + uint32_t ros:1; + uint32_t ucs:1; + uint32_t cas:1; + uint32_t cts:1; + uint32_t fcpes:1; + uint32_t ptlps:1; + uint32_t reserved_6_11:6; + uint32_t sdes:1; + uint32_t dlpes:1; + uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpes:1; + uint32_t sdes:1; + uint32_t reserved_6_11:6; + uint32_t ptlps:1; + uint32_t fcpes:1; + uint32_t cts:1; + uint32_t cas:1; + uint32_t ucs:1; + uint32_t ros:1; + uint32_t mtlps:1; + uint32_t ecrces:1; + uint32_t ures:1; + uint32_t reserved_21_23:3; + uint32_t uatombs:1; + uint32_t reserved_25_31:7; +#endif + } cn61xx; struct cvmx_pciercx_cfg065_cn52xx cn63xx; struct cvmx_pciercx_cfg065_cn52xx cn63xxp1; - struct cvmx_pciercx_cfg065_s cn66xx; - struct cvmx_pciercx_cfg065_s cn68xx; + struct cvmx_pciercx_cfg065_cn61xx cn66xx; + struct cvmx_pciercx_cfg065_cn61xx cn68xx; struct cvmx_pciercx_cfg065_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg065_s cnf71xx; }; union cvmx_pciercx_cfg066 { uint32_t u32; struct cvmx_pciercx_cfg066_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_25_31:7; uint32_t uatombm:1; - uint32_t reserved_21_23:3; + uint32_t reserved_23_23:1; + uint32_t uciem:1; + uint32_t reserved_21_21:1; uint32_t urem:1; uint32_t ecrcem:1; uint32_t mtlpm:1; @@ -1115,8 +1756,29 @@ union cvmx_pciercx_cfg066 { uint32_t sdem:1; uint32_t dlpem:1; uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpem:1; + uint32_t sdem:1; + uint32_t reserved_6_11:6; + uint32_t ptlpm:1; + uint32_t fcpem:1; + uint32_t ctm:1; + uint32_t cam:1; + uint32_t ucm:1; + uint32_t rom:1; + uint32_t mtlpm:1; + uint32_t ecrcem:1; + uint32_t urem:1; + uint32_t reserved_21_21:1; + uint32_t uciem:1; + uint32_t reserved_23_23:1; + uint32_t uatombm:1; + uint32_t reserved_25_31:7; +#endif } s; struct cvmx_pciercx_cfg066_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_21_31:11; uint32_t urem:1; uint32_t ecrcem:1; @@ -1131,24 +1793,80 @@ union cvmx_pciercx_cfg066 { uint32_t sdem:1; uint32_t dlpem:1; uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpem:1; + uint32_t sdem:1; + uint32_t reserved_6_11:6; + uint32_t ptlpm:1; + uint32_t fcpem:1; + uint32_t ctm:1; + uint32_t cam:1; + uint32_t ucm:1; + uint32_t rom:1; + uint32_t mtlpm:1; + uint32_t ecrcem:1; + uint32_t urem:1; + uint32_t reserved_21_31:11; +#endif } cn52xx; struct cvmx_pciercx_cfg066_cn52xx cn52xxp1; struct cvmx_pciercx_cfg066_cn52xx cn56xx; struct cvmx_pciercx_cfg066_cn52xx cn56xxp1; - struct cvmx_pciercx_cfg066_s cn61xx; + struct cvmx_pciercx_cfg066_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_25_31:7; + uint32_t uatombm:1; + uint32_t reserved_21_23:3; + uint32_t urem:1; + uint32_t ecrcem:1; + uint32_t mtlpm:1; + uint32_t rom:1; + uint32_t ucm:1; + uint32_t cam:1; + uint32_t ctm:1; + uint32_t fcpem:1; + uint32_t ptlpm:1; + uint32_t reserved_6_11:6; + uint32_t sdem:1; + uint32_t dlpem:1; + uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpem:1; + uint32_t sdem:1; + uint32_t reserved_6_11:6; + uint32_t ptlpm:1; + uint32_t fcpem:1; + uint32_t ctm:1; + uint32_t cam:1; + uint32_t ucm:1; + uint32_t rom:1; + uint32_t mtlpm:1; + uint32_t ecrcem:1; + uint32_t urem:1; + uint32_t reserved_21_23:3; + uint32_t uatombm:1; + uint32_t reserved_25_31:7; +#endif + } cn61xx; struct cvmx_pciercx_cfg066_cn52xx cn63xx; struct cvmx_pciercx_cfg066_cn52xx cn63xxp1; - struct cvmx_pciercx_cfg066_s cn66xx; - struct cvmx_pciercx_cfg066_s cn68xx; + struct cvmx_pciercx_cfg066_cn61xx cn66xx; + struct cvmx_pciercx_cfg066_cn61xx cn68xx; struct cvmx_pciercx_cfg066_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg066_s cnf71xx; }; union cvmx_pciercx_cfg067 { uint32_t u32; struct cvmx_pciercx_cfg067_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_25_31:7; uint32_t uatombs:1; - uint32_t reserved_21_23:3; + uint32_t reserved_23_23:1; + uint32_t ucies:1; + uint32_t reserved_21_21:1; uint32_t ures:1; uint32_t ecrces:1; uint32_t mtlps:1; @@ -1162,8 +1880,29 @@ union cvmx_pciercx_cfg067 { uint32_t sdes:1; uint32_t dlpes:1; uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpes:1; + uint32_t sdes:1; + uint32_t reserved_6_11:6; + uint32_t ptlps:1; + uint32_t fcpes:1; + uint32_t cts:1; + uint32_t cas:1; + uint32_t ucs:1; + uint32_t ros:1; + uint32_t mtlps:1; + uint32_t ecrces:1; + uint32_t ures:1; + uint32_t reserved_21_21:1; + uint32_t ucies:1; + uint32_t reserved_23_23:1; + uint32_t uatombs:1; + uint32_t reserved_25_31:7; +#endif } s; struct cvmx_pciercx_cfg067_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_21_31:11; uint32_t ures:1; uint32_t ecrces:1; @@ -1178,22 +1917,77 @@ union cvmx_pciercx_cfg067 { uint32_t sdes:1; uint32_t dlpes:1; uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpes:1; + uint32_t sdes:1; + uint32_t reserved_6_11:6; + uint32_t ptlps:1; + uint32_t fcpes:1; + uint32_t cts:1; + uint32_t cas:1; + uint32_t ucs:1; + uint32_t ros:1; + uint32_t mtlps:1; + uint32_t ecrces:1; + uint32_t ures:1; + uint32_t reserved_21_31:11; +#endif } cn52xx; struct cvmx_pciercx_cfg067_cn52xx cn52xxp1; struct cvmx_pciercx_cfg067_cn52xx cn56xx; struct cvmx_pciercx_cfg067_cn52xx cn56xxp1; - struct cvmx_pciercx_cfg067_s cn61xx; + struct cvmx_pciercx_cfg067_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_25_31:7; + uint32_t uatombs:1; + uint32_t reserved_21_23:3; + uint32_t ures:1; + uint32_t ecrces:1; + uint32_t mtlps:1; + uint32_t ros:1; + uint32_t ucs:1; + uint32_t cas:1; + uint32_t cts:1; + uint32_t fcpes:1; + uint32_t ptlps:1; + uint32_t reserved_6_11:6; + uint32_t sdes:1; + uint32_t dlpes:1; + uint32_t reserved_0_3:4; +#else + uint32_t reserved_0_3:4; + uint32_t dlpes:1; + uint32_t sdes:1; + uint32_t reserved_6_11:6; + uint32_t ptlps:1; + uint32_t fcpes:1; + uint32_t cts:1; + uint32_t cas:1; + uint32_t ucs:1; + uint32_t ros:1; + uint32_t mtlps:1; + uint32_t ecrces:1; + uint32_t ures:1; + uint32_t reserved_21_23:3; + uint32_t uatombs:1; + uint32_t reserved_25_31:7; +#endif + } cn61xx; struct cvmx_pciercx_cfg067_cn52xx cn63xx; struct cvmx_pciercx_cfg067_cn52xx cn63xxp1; - struct cvmx_pciercx_cfg067_s cn66xx; - struct cvmx_pciercx_cfg067_s cn68xx; + struct cvmx_pciercx_cfg067_cn61xx cn66xx; + struct cvmx_pciercx_cfg067_cn61xx cn68xx; struct cvmx_pciercx_cfg067_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg067_s cnf71xx; }; union cvmx_pciercx_cfg068 { uint32_t u32; struct cvmx_pciercx_cfg068_s { - uint32_t reserved_14_31:18; +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_15_31:17; + uint32_t cies:1; uint32_t anfes:1; uint32_t rtts:1; uint32_t reserved_9_11:3; @@ -1202,23 +1996,60 @@ union cvmx_pciercx_cfg068 { uint32_t btlps:1; uint32_t reserved_1_5:5; uint32_t res:1; +#else + uint32_t res:1; + uint32_t reserved_1_5:5; + uint32_t btlps:1; + uint32_t bdllps:1; + uint32_t rnrs:1; + uint32_t reserved_9_11:3; + uint32_t rtts:1; + uint32_t anfes:1; + uint32_t cies:1; + uint32_t reserved_15_31:17; +#endif } s; - struct cvmx_pciercx_cfg068_s cn52xx; - struct cvmx_pciercx_cfg068_s cn52xxp1; - struct cvmx_pciercx_cfg068_s cn56xx; - struct cvmx_pciercx_cfg068_s cn56xxp1; - struct cvmx_pciercx_cfg068_s cn61xx; - struct cvmx_pciercx_cfg068_s cn63xx; - struct cvmx_pciercx_cfg068_s cn63xxp1; - struct cvmx_pciercx_cfg068_s cn66xx; - struct cvmx_pciercx_cfg068_s cn68xx; - struct cvmx_pciercx_cfg068_s cn68xxp1; + struct cvmx_pciercx_cfg068_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_14_31:18; + uint32_t anfes:1; + uint32_t rtts:1; + uint32_t reserved_9_11:3; + uint32_t rnrs:1; + uint32_t bdllps:1; + uint32_t btlps:1; + uint32_t reserved_1_5:5; + uint32_t res:1; +#else + uint32_t res:1; + uint32_t reserved_1_5:5; + uint32_t btlps:1; + uint32_t bdllps:1; + uint32_t rnrs:1; + uint32_t reserved_9_11:3; + uint32_t rtts:1; + uint32_t anfes:1; + uint32_t reserved_14_31:18; +#endif + } cn52xx; + struct cvmx_pciercx_cfg068_cn52xx cn52xxp1; + struct cvmx_pciercx_cfg068_cn52xx cn56xx; + struct cvmx_pciercx_cfg068_cn52xx cn56xxp1; + struct cvmx_pciercx_cfg068_cn52xx cn61xx; + struct cvmx_pciercx_cfg068_cn52xx cn63xx; + struct cvmx_pciercx_cfg068_cn52xx cn63xxp1; + struct cvmx_pciercx_cfg068_cn52xx cn66xx; + struct cvmx_pciercx_cfg068_cn52xx cn68xx; + struct cvmx_pciercx_cfg068_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg068_s cnf71xx; }; union cvmx_pciercx_cfg069 { uint32_t u32; struct cvmx_pciercx_cfg069_s { - uint32_t reserved_14_31:18; +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_15_31:17; + uint32_t ciem:1; uint32_t anfem:1; uint32_t rttm:1; uint32_t reserved_9_11:3; @@ -1227,28 +2058,72 @@ union cvmx_pciercx_cfg069 { uint32_t btlpm:1; uint32_t reserved_1_5:5; uint32_t rem:1; +#else + uint32_t rem:1; + uint32_t reserved_1_5:5; + uint32_t btlpm:1; + uint32_t bdllpm:1; + uint32_t rnrm:1; + uint32_t reserved_9_11:3; + uint32_t rttm:1; + uint32_t anfem:1; + uint32_t ciem:1; + uint32_t reserved_15_31:17; +#endif } s; - struct cvmx_pciercx_cfg069_s cn52xx; - struct cvmx_pciercx_cfg069_s cn52xxp1; - struct cvmx_pciercx_cfg069_s cn56xx; - struct cvmx_pciercx_cfg069_s cn56xxp1; - struct cvmx_pciercx_cfg069_s cn61xx; - struct cvmx_pciercx_cfg069_s cn63xx; - struct cvmx_pciercx_cfg069_s cn63xxp1; - struct cvmx_pciercx_cfg069_s cn66xx; - struct cvmx_pciercx_cfg069_s cn68xx; - struct cvmx_pciercx_cfg069_s cn68xxp1; + struct cvmx_pciercx_cfg069_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_14_31:18; + uint32_t anfem:1; + uint32_t rttm:1; + uint32_t reserved_9_11:3; + uint32_t rnrm:1; + uint32_t bdllpm:1; + uint32_t btlpm:1; + uint32_t reserved_1_5:5; + uint32_t rem:1; +#else + uint32_t rem:1; + uint32_t reserved_1_5:5; + uint32_t btlpm:1; + uint32_t bdllpm:1; + uint32_t rnrm:1; + uint32_t reserved_9_11:3; + uint32_t rttm:1; + uint32_t anfem:1; + uint32_t reserved_14_31:18; +#endif + } cn52xx; + struct cvmx_pciercx_cfg069_cn52xx cn52xxp1; + struct cvmx_pciercx_cfg069_cn52xx cn56xx; + struct cvmx_pciercx_cfg069_cn52xx cn56xxp1; + struct cvmx_pciercx_cfg069_cn52xx cn61xx; + struct cvmx_pciercx_cfg069_cn52xx cn63xx; + struct cvmx_pciercx_cfg069_cn52xx cn63xxp1; + struct cvmx_pciercx_cfg069_cn52xx cn66xx; + struct cvmx_pciercx_cfg069_cn52xx cn68xx; + struct cvmx_pciercx_cfg069_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg069_s cnf71xx; }; union cvmx_pciercx_cfg070 { uint32_t u32; struct cvmx_pciercx_cfg070_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_9_31:23; uint32_t ce:1; uint32_t cc:1; uint32_t ge:1; uint32_t gc:1; uint32_t fep:5; +#else + uint32_t fep:5; + uint32_t gc:1; + uint32_t ge:1; + uint32_t cc:1; + uint32_t ce:1; + uint32_t reserved_9_31:23; +#endif } s; struct cvmx_pciercx_cfg070_s cn52xx; struct cvmx_pciercx_cfg070_s cn52xxp1; @@ -1260,12 +2135,17 @@ union cvmx_pciercx_cfg070 { struct cvmx_pciercx_cfg070_s cn66xx; struct cvmx_pciercx_cfg070_s cn68xx; struct cvmx_pciercx_cfg070_s cn68xxp1; + struct cvmx_pciercx_cfg070_s cnf71xx; }; union cvmx_pciercx_cfg071 { uint32_t u32; struct cvmx_pciercx_cfg071_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t dword1:32; +#else + uint32_t dword1:32; +#endif } s; struct cvmx_pciercx_cfg071_s cn52xx; struct cvmx_pciercx_cfg071_s cn52xxp1; @@ -1277,12 +2157,17 @@ union cvmx_pciercx_cfg071 { struct cvmx_pciercx_cfg071_s cn66xx; struct cvmx_pciercx_cfg071_s cn68xx; struct cvmx_pciercx_cfg071_s cn68xxp1; + struct cvmx_pciercx_cfg071_s cnf71xx; }; union cvmx_pciercx_cfg072 { uint32_t u32; struct cvmx_pciercx_cfg072_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t dword2:32; +#else + uint32_t dword2:32; +#endif } s; struct cvmx_pciercx_cfg072_s cn52xx; struct cvmx_pciercx_cfg072_s cn52xxp1; @@ -1294,12 +2179,17 @@ union cvmx_pciercx_cfg072 { struct cvmx_pciercx_cfg072_s cn66xx; struct cvmx_pciercx_cfg072_s cn68xx; struct cvmx_pciercx_cfg072_s cn68xxp1; + struct cvmx_pciercx_cfg072_s cnf71xx; }; union cvmx_pciercx_cfg073 { uint32_t u32; struct cvmx_pciercx_cfg073_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t dword3:32; +#else + uint32_t dword3:32; +#endif } s; struct cvmx_pciercx_cfg073_s cn52xx; struct cvmx_pciercx_cfg073_s cn52xxp1; @@ -1311,12 +2201,17 @@ union cvmx_pciercx_cfg073 { struct cvmx_pciercx_cfg073_s cn66xx; struct cvmx_pciercx_cfg073_s cn68xx; struct cvmx_pciercx_cfg073_s cn68xxp1; + struct cvmx_pciercx_cfg073_s cnf71xx; }; union cvmx_pciercx_cfg074 { uint32_t u32; struct cvmx_pciercx_cfg074_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t dword4:32; +#else uint32_t dword4:32; +#endif } s; struct cvmx_pciercx_cfg074_s cn52xx; struct cvmx_pciercx_cfg074_s cn52xxp1; @@ -1328,15 +2223,23 @@ union cvmx_pciercx_cfg074 { struct cvmx_pciercx_cfg074_s cn66xx; struct cvmx_pciercx_cfg074_s cn68xx; struct cvmx_pciercx_cfg074_s cn68xxp1; + struct cvmx_pciercx_cfg074_s cnf71xx; }; union cvmx_pciercx_cfg075 { uint32_t u32; struct cvmx_pciercx_cfg075_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_3_31:29; uint32_t fere:1; uint32_t nfere:1; uint32_t cere:1; +#else + uint32_t cere:1; + uint32_t nfere:1; + uint32_t fere:1; + uint32_t reserved_3_31:29; +#endif } s; struct cvmx_pciercx_cfg075_s cn52xx; struct cvmx_pciercx_cfg075_s cn52xxp1; @@ -1348,11 +2251,13 @@ union cvmx_pciercx_cfg075 { struct cvmx_pciercx_cfg075_s cn66xx; struct cvmx_pciercx_cfg075_s cn68xx; struct cvmx_pciercx_cfg075_s cn68xxp1; + struct cvmx_pciercx_cfg075_s cnf71xx; }; union cvmx_pciercx_cfg076 { uint32_t u32; struct cvmx_pciercx_cfg076_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t aeimn:5; uint32_t reserved_7_26:20; uint32_t femr:1; @@ -1362,6 +2267,17 @@ union cvmx_pciercx_cfg076 { uint32_t efnfr:1; uint32_t multi_ecr:1; uint32_t ecr:1; +#else + uint32_t ecr:1; + uint32_t multi_ecr:1; + uint32_t efnfr:1; + uint32_t multi_efnfr:1; + uint32_t fuf:1; + uint32_t nfemr:1; + uint32_t femr:1; + uint32_t reserved_7_26:20; + uint32_t aeimn:5; +#endif } s; struct cvmx_pciercx_cfg076_s cn52xx; struct cvmx_pciercx_cfg076_s cn52xxp1; @@ -1373,13 +2289,19 @@ union cvmx_pciercx_cfg076 { struct cvmx_pciercx_cfg076_s cn66xx; struct cvmx_pciercx_cfg076_s cn68xx; struct cvmx_pciercx_cfg076_s cn68xxp1; + struct cvmx_pciercx_cfg076_s cnf71xx; }; union cvmx_pciercx_cfg077 { uint32_t u32; struct cvmx_pciercx_cfg077_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t efnfsi:16; uint32_t ecsi:16; +#else + uint32_t ecsi:16; + uint32_t efnfsi:16; +#endif } s; struct cvmx_pciercx_cfg077_s cn52xx; struct cvmx_pciercx_cfg077_s cn52xxp1; @@ -1391,13 +2313,19 @@ union cvmx_pciercx_cfg077 { struct cvmx_pciercx_cfg077_s cn66xx; struct cvmx_pciercx_cfg077_s cn68xx; struct cvmx_pciercx_cfg077_s cn68xxp1; + struct cvmx_pciercx_cfg077_s cnf71xx; }; union cvmx_pciercx_cfg448 { uint32_t u32; struct cvmx_pciercx_cfg448_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t rtl:16; uint32_t rtltl:16; +#else + uint32_t rtltl:16; + uint32_t rtl:16; +#endif } s; struct cvmx_pciercx_cfg448_s cn52xx; struct cvmx_pciercx_cfg448_s cn52xxp1; @@ -1409,12 +2337,17 @@ union cvmx_pciercx_cfg448 { struct cvmx_pciercx_cfg448_s cn66xx; struct cvmx_pciercx_cfg448_s cn68xx; struct cvmx_pciercx_cfg448_s cn68xxp1; + struct cvmx_pciercx_cfg448_s cnf71xx; }; union cvmx_pciercx_cfg449 { uint32_t u32; struct cvmx_pciercx_cfg449_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t omr:32; +#else uint32_t omr:32; +#endif } s; struct cvmx_pciercx_cfg449_s cn52xx; struct cvmx_pciercx_cfg449_s cn52xxp1; @@ -1426,17 +2359,27 @@ union cvmx_pciercx_cfg449 { struct cvmx_pciercx_cfg449_s cn66xx; struct cvmx_pciercx_cfg449_s cn68xx; struct cvmx_pciercx_cfg449_s cn68xxp1; + struct cvmx_pciercx_cfg449_s cnf71xx; }; union cvmx_pciercx_cfg450 { uint32_t u32; struct cvmx_pciercx_cfg450_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t lpec:8; uint32_t reserved_22_23:2; uint32_t link_state:6; uint32_t force_link:1; uint32_t reserved_8_14:7; uint32_t link_num:8; +#else + uint32_t link_num:8; + uint32_t reserved_8_14:7; + uint32_t force_link:1; + uint32_t link_state:6; + uint32_t reserved_22_23:2; + uint32_t lpec:8; +#endif } s; struct cvmx_pciercx_cfg450_s cn52xx; struct cvmx_pciercx_cfg450_s cn52xxp1; @@ -1448,11 +2391,13 @@ union cvmx_pciercx_cfg450 { struct cvmx_pciercx_cfg450_s cn66xx; struct cvmx_pciercx_cfg450_s cn68xx; struct cvmx_pciercx_cfg450_s cn68xxp1; + struct cvmx_pciercx_cfg450_s cnf71xx; }; union cvmx_pciercx_cfg451 { uint32_t u32; struct cvmx_pciercx_cfg451_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_31_31:1; uint32_t easpml1:1; uint32_t l1el:3; @@ -1460,14 +2405,32 @@ union cvmx_pciercx_cfg451 { uint32_t n_fts_cc:8; uint32_t n_fts:8; uint32_t ack_freq:8; +#else + uint32_t ack_freq:8; + uint32_t n_fts:8; + uint32_t n_fts_cc:8; + uint32_t l0el:3; + uint32_t l1el:3; + uint32_t easpml1:1; + uint32_t reserved_31_31:1; +#endif } s; struct cvmx_pciercx_cfg451_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_30_31:2; uint32_t l1el:3; uint32_t l0el:3; uint32_t n_fts_cc:8; uint32_t n_fts:8; uint32_t ack_freq:8; +#else + uint32_t ack_freq:8; + uint32_t n_fts:8; + uint32_t n_fts_cc:8; + uint32_t l0el:3; + uint32_t l1el:3; + uint32_t reserved_30_31:2; +#endif } cn52xx; struct cvmx_pciercx_cfg451_cn52xx cn52xxp1; struct cvmx_pciercx_cfg451_cn52xx cn56xx; @@ -1478,11 +2441,13 @@ union cvmx_pciercx_cfg451 { struct cvmx_pciercx_cfg451_s cn66xx; struct cvmx_pciercx_cfg451_s cn68xx; struct cvmx_pciercx_cfg451_s cn68xxp1; + struct cvmx_pciercx_cfg451_s cnf71xx; }; union cvmx_pciercx_cfg452 { uint32_t u32; struct cvmx_pciercx_cfg452_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_26_31:6; uint32_t eccrc:1; uint32_t reserved_22_24:3; @@ -1496,12 +2461,28 @@ union cvmx_pciercx_cfg452 { uint32_t le:1; uint32_t sd:1; uint32_t omr:1; +#else + uint32_t omr:1; + uint32_t sd:1; + uint32_t le:1; + uint32_t ra:1; + uint32_t reserved_4_4:1; + uint32_t dllle:1; + uint32_t reserved_6_6:1; + uint32_t flm:1; + uint32_t reserved_8_15:8; + uint32_t lme:6; + uint32_t reserved_22_24:3; + uint32_t eccrc:1; + uint32_t reserved_26_31:6; +#endif } s; struct cvmx_pciercx_cfg452_s cn52xx; struct cvmx_pciercx_cfg452_s cn52xxp1; struct cvmx_pciercx_cfg452_s cn56xx; struct cvmx_pciercx_cfg452_s cn56xxp1; struct cvmx_pciercx_cfg452_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_22_31:10; uint32_t lme:6; uint32_t reserved_8_15:8; @@ -1513,22 +2494,44 @@ union cvmx_pciercx_cfg452 { uint32_t le:1; uint32_t sd:1; uint32_t omr:1; +#else + uint32_t omr:1; + uint32_t sd:1; + uint32_t le:1; + uint32_t ra:1; + uint32_t reserved_4_4:1; + uint32_t dllle:1; + uint32_t reserved_6_6:1; + uint32_t flm:1; + uint32_t reserved_8_15:8; + uint32_t lme:6; + uint32_t reserved_22_31:10; +#endif } cn61xx; struct cvmx_pciercx_cfg452_s cn63xx; struct cvmx_pciercx_cfg452_s cn63xxp1; struct cvmx_pciercx_cfg452_cn61xx cn66xx; struct cvmx_pciercx_cfg452_cn61xx cn68xx; struct cvmx_pciercx_cfg452_cn61xx cn68xxp1; + struct cvmx_pciercx_cfg452_cn61xx cnf71xx; }; union cvmx_pciercx_cfg453 { uint32_t u32; struct cvmx_pciercx_cfg453_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t dlld:1; uint32_t reserved_26_30:5; uint32_t ack_nak:1; uint32_t fcd:1; uint32_t ilst:24; +#else + uint32_t ilst:24; + uint32_t fcd:1; + uint32_t ack_nak:1; + uint32_t reserved_26_30:5; + uint32_t dlld:1; +#endif } s; struct cvmx_pciercx_cfg453_s cn52xx; struct cvmx_pciercx_cfg453_s cn52xxp1; @@ -1540,11 +2543,13 @@ union cvmx_pciercx_cfg453 { struct cvmx_pciercx_cfg453_s cn66xx; struct cvmx_pciercx_cfg453_s cn68xx; struct cvmx_pciercx_cfg453_s cn68xxp1; + struct cvmx_pciercx_cfg453_s cnf71xx; }; union cvmx_pciercx_cfg454 { uint32_t u32; struct cvmx_pciercx_cfg454_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t cx_nfunc:3; uint32_t tmfcwt:5; uint32_t tmanlt:5; @@ -1552,8 +2557,18 @@ union cvmx_pciercx_cfg454 { uint32_t reserved_11_13:3; uint32_t nskps:3; uint32_t reserved_0_7:8; +#else + uint32_t reserved_0_7:8; + uint32_t nskps:3; + uint32_t reserved_11_13:3; + uint32_t tmrt:5; + uint32_t tmanlt:5; + uint32_t tmfcwt:5; + uint32_t cx_nfunc:3; +#endif } s; struct cvmx_pciercx_cfg454_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_29_31:3; uint32_t tmfcwt:5; uint32_t tmanlt:5; @@ -1562,28 +2577,49 @@ union cvmx_pciercx_cfg454 { uint32_t nskps:3; uint32_t reserved_4_7:4; uint32_t ntss:4; +#else + uint32_t ntss:4; + uint32_t reserved_4_7:4; + uint32_t nskps:3; + uint32_t reserved_11_13:3; + uint32_t tmrt:5; + uint32_t tmanlt:5; + uint32_t tmfcwt:5; + uint32_t reserved_29_31:3; +#endif } cn52xx; struct cvmx_pciercx_cfg454_cn52xx cn52xxp1; struct cvmx_pciercx_cfg454_cn52xx cn56xx; struct cvmx_pciercx_cfg454_cn52xx cn56xxp1; struct cvmx_pciercx_cfg454_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t cx_nfunc:3; uint32_t tmfcwt:5; uint32_t tmanlt:5; uint32_t tmrt:5; uint32_t reserved_8_13:6; uint32_t mfuncn:8; +#else + uint32_t mfuncn:8; + uint32_t reserved_8_13:6; + uint32_t tmrt:5; + uint32_t tmanlt:5; + uint32_t tmfcwt:5; + uint32_t cx_nfunc:3; +#endif } cn61xx; struct cvmx_pciercx_cfg454_cn52xx cn63xx; struct cvmx_pciercx_cfg454_cn52xx cn63xxp1; struct cvmx_pciercx_cfg454_cn61xx cn66xx; struct cvmx_pciercx_cfg454_cn61xx cn68xx; struct cvmx_pciercx_cfg454_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg454_cn61xx cnf71xx; }; union cvmx_pciercx_cfg455 { uint32_t u32; struct cvmx_pciercx_cfg455_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t m_cfg0_filt:1; uint32_t m_io_filt:1; uint32_t msg_ctrl:1; @@ -1603,6 +2639,27 @@ union cvmx_pciercx_cfg455 { uint32_t dfcwt:1; uint32_t reserved_11_14:4; uint32_t skpiv:11; +#else + uint32_t skpiv:11; + uint32_t reserved_11_14:4; + uint32_t dfcwt:1; + uint32_t m_fun:1; + uint32_t m_pois_filt:1; + uint32_t m_bar_match:1; + uint32_t m_cfg1_filt:1; + uint32_t m_lk_filt:1; + uint32_t m_cpl_tag_err:1; + uint32_t m_cpl_rid_err:1; + uint32_t m_cpl_fun_err:1; + uint32_t m_cpl_tc_err:1; + uint32_t m_cpl_attr_err:1; + uint32_t m_cpl_len_err:1; + uint32_t m_ecrc_filt:1; + uint32_t m_cpl_ecrc_filt:1; + uint32_t msg_ctrl:1; + uint32_t m_io_filt:1; + uint32_t m_cfg0_filt:1; +#endif } s; struct cvmx_pciercx_cfg455_s cn52xx; struct cvmx_pciercx_cfg455_s cn52xxp1; @@ -1614,21 +2671,36 @@ union cvmx_pciercx_cfg455 { struct cvmx_pciercx_cfg455_s cn66xx; struct cvmx_pciercx_cfg455_s cn68xx; struct cvmx_pciercx_cfg455_s cn68xxp1; + struct cvmx_pciercx_cfg455_s cnf71xx; }; union cvmx_pciercx_cfg456 { uint32_t u32; struct cvmx_pciercx_cfg456_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_4_31:28; uint32_t m_handle_flush:1; uint32_t m_dabort_4ucpl:1; uint32_t m_vend1_drp:1; uint32_t m_vend0_drp:1; +#else + uint32_t m_vend0_drp:1; + uint32_t m_vend1_drp:1; + uint32_t m_dabort_4ucpl:1; + uint32_t m_handle_flush:1; + uint32_t reserved_4_31:28; +#endif } s; struct cvmx_pciercx_cfg456_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_2_31:30; uint32_t m_vend1_drp:1; uint32_t m_vend0_drp:1; +#else + uint32_t m_vend0_drp:1; + uint32_t m_vend1_drp:1; + uint32_t reserved_2_31:30; +#endif } cn52xx; struct cvmx_pciercx_cfg456_cn52xx cn52xxp1; struct cvmx_pciercx_cfg456_cn52xx cn56xx; @@ -1639,12 +2711,17 @@ union cvmx_pciercx_cfg456 { struct cvmx_pciercx_cfg456_s cn66xx; struct cvmx_pciercx_cfg456_s cn68xx; struct cvmx_pciercx_cfg456_cn52xx cn68xxp1; + struct cvmx_pciercx_cfg456_s cnf71xx; }; union cvmx_pciercx_cfg458 { uint32_t u32; struct cvmx_pciercx_cfg458_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t dbg_info_l32:32; +#else uint32_t dbg_info_l32:32; +#endif } s; struct cvmx_pciercx_cfg458_s cn52xx; struct cvmx_pciercx_cfg458_s cn52xxp1; @@ -1656,12 +2733,17 @@ union cvmx_pciercx_cfg458 { struct cvmx_pciercx_cfg458_s cn66xx; struct cvmx_pciercx_cfg458_s cn68xx; struct cvmx_pciercx_cfg458_s cn68xxp1; + struct cvmx_pciercx_cfg458_s cnf71xx; }; union cvmx_pciercx_cfg459 { uint32_t u32; struct cvmx_pciercx_cfg459_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t dbg_info_u32:32; +#else uint32_t dbg_info_u32:32; +#endif } s; struct cvmx_pciercx_cfg459_s cn52xx; struct cvmx_pciercx_cfg459_s cn52xxp1; @@ -1673,14 +2755,21 @@ union cvmx_pciercx_cfg459 { struct cvmx_pciercx_cfg459_s cn66xx; struct cvmx_pciercx_cfg459_s cn68xx; struct cvmx_pciercx_cfg459_s cn68xxp1; + struct cvmx_pciercx_cfg459_s cnf71xx; }; union cvmx_pciercx_cfg460 { uint32_t u32; struct cvmx_pciercx_cfg460_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_20_31:12; uint32_t tphfcc:8; uint32_t tpdfcc:12; +#else + uint32_t tpdfcc:12; + uint32_t tphfcc:8; + uint32_t reserved_20_31:12; +#endif } s; struct cvmx_pciercx_cfg460_s cn52xx; struct cvmx_pciercx_cfg460_s cn52xxp1; @@ -1692,14 +2781,21 @@ union cvmx_pciercx_cfg460 { struct cvmx_pciercx_cfg460_s cn66xx; struct cvmx_pciercx_cfg460_s cn68xx; struct cvmx_pciercx_cfg460_s cn68xxp1; + struct cvmx_pciercx_cfg460_s cnf71xx; }; union cvmx_pciercx_cfg461 { uint32_t u32; struct cvmx_pciercx_cfg461_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_20_31:12; uint32_t tchfcc:8; uint32_t tcdfcc:12; +#else + uint32_t tcdfcc:12; + uint32_t tchfcc:8; + uint32_t reserved_20_31:12; +#endif } s; struct cvmx_pciercx_cfg461_s cn52xx; struct cvmx_pciercx_cfg461_s cn52xxp1; @@ -1711,14 +2807,21 @@ union cvmx_pciercx_cfg461 { struct cvmx_pciercx_cfg461_s cn66xx; struct cvmx_pciercx_cfg461_s cn68xx; struct cvmx_pciercx_cfg461_s cn68xxp1; + struct cvmx_pciercx_cfg461_s cnf71xx; }; union cvmx_pciercx_cfg462 { uint32_t u32; struct cvmx_pciercx_cfg462_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_20_31:12; uint32_t tchfcc:8; uint32_t tcdfcc:12; +#else + uint32_t tcdfcc:12; + uint32_t tchfcc:8; + uint32_t reserved_20_31:12; +#endif } s; struct cvmx_pciercx_cfg462_s cn52xx; struct cvmx_pciercx_cfg462_s cn52xxp1; @@ -1730,15 +2833,23 @@ union cvmx_pciercx_cfg462 { struct cvmx_pciercx_cfg462_s cn66xx; struct cvmx_pciercx_cfg462_s cn68xx; struct cvmx_pciercx_cfg462_s cn68xxp1; + struct cvmx_pciercx_cfg462_s cnf71xx; }; union cvmx_pciercx_cfg463 { uint32_t u32; struct cvmx_pciercx_cfg463_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_3_31:29; uint32_t rqne:1; uint32_t trbne:1; uint32_t rtlpfccnr:1; +#else + uint32_t rtlpfccnr:1; + uint32_t trbne:1; + uint32_t rqne:1; + uint32_t reserved_3_31:29; +#endif } s; struct cvmx_pciercx_cfg463_s cn52xx; struct cvmx_pciercx_cfg463_s cn52xxp1; @@ -1750,15 +2861,23 @@ union cvmx_pciercx_cfg463 { struct cvmx_pciercx_cfg463_s cn66xx; struct cvmx_pciercx_cfg463_s cn68xx; struct cvmx_pciercx_cfg463_s cn68xxp1; + struct cvmx_pciercx_cfg463_s cnf71xx; }; union cvmx_pciercx_cfg464 { uint32_t u32; struct cvmx_pciercx_cfg464_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t wrr_vc3:8; uint32_t wrr_vc2:8; uint32_t wrr_vc1:8; uint32_t wrr_vc0:8; +#else + uint32_t wrr_vc0:8; + uint32_t wrr_vc1:8; + uint32_t wrr_vc2:8; + uint32_t wrr_vc3:8; +#endif } s; struct cvmx_pciercx_cfg464_s cn52xx; struct cvmx_pciercx_cfg464_s cn52xxp1; @@ -1770,15 +2889,23 @@ union cvmx_pciercx_cfg464 { struct cvmx_pciercx_cfg464_s cn66xx; struct cvmx_pciercx_cfg464_s cn68xx; struct cvmx_pciercx_cfg464_s cn68xxp1; + struct cvmx_pciercx_cfg464_s cnf71xx; }; union cvmx_pciercx_cfg465 { uint32_t u32; struct cvmx_pciercx_cfg465_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t wrr_vc7:8; uint32_t wrr_vc6:8; uint32_t wrr_vc5:8; uint32_t wrr_vc4:8; +#else + uint32_t wrr_vc4:8; + uint32_t wrr_vc5:8; + uint32_t wrr_vc6:8; + uint32_t wrr_vc7:8; +#endif } s; struct cvmx_pciercx_cfg465_s cn52xx; struct cvmx_pciercx_cfg465_s cn52xxp1; @@ -1790,11 +2917,13 @@ union cvmx_pciercx_cfg465 { struct cvmx_pciercx_cfg465_s cn66xx; struct cvmx_pciercx_cfg465_s cn68xx; struct cvmx_pciercx_cfg465_s cn68xxp1; + struct cvmx_pciercx_cfg465_s cnf71xx; }; union cvmx_pciercx_cfg466 { uint32_t u32; struct cvmx_pciercx_cfg466_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t rx_queue_order:1; uint32_t type_ordering:1; uint32_t reserved_24_29:6; @@ -1802,6 +2931,15 @@ union cvmx_pciercx_cfg466 { uint32_t reserved_20_20:1; uint32_t header_credits:8; uint32_t data_credits:12; +#else + uint32_t data_credits:12; + uint32_t header_credits:8; + uint32_t reserved_20_20:1; + uint32_t queue_mode:3; + uint32_t reserved_24_29:6; + uint32_t type_ordering:1; + uint32_t rx_queue_order:1; +#endif } s; struct cvmx_pciercx_cfg466_s cn52xx; struct cvmx_pciercx_cfg466_s cn52xxp1; @@ -1813,16 +2951,25 @@ union cvmx_pciercx_cfg466 { struct cvmx_pciercx_cfg466_s cn66xx; struct cvmx_pciercx_cfg466_s cn68xx; struct cvmx_pciercx_cfg466_s cn68xxp1; + struct cvmx_pciercx_cfg466_s cnf71xx; }; union cvmx_pciercx_cfg467 { uint32_t u32; struct cvmx_pciercx_cfg467_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_24_31:8; uint32_t queue_mode:3; uint32_t reserved_20_20:1; uint32_t header_credits:8; uint32_t data_credits:12; +#else + uint32_t data_credits:12; + uint32_t header_credits:8; + uint32_t reserved_20_20:1; + uint32_t queue_mode:3; + uint32_t reserved_24_31:8; +#endif } s; struct cvmx_pciercx_cfg467_s cn52xx; struct cvmx_pciercx_cfg467_s cn52xxp1; @@ -1834,16 +2981,25 @@ union cvmx_pciercx_cfg467 { struct cvmx_pciercx_cfg467_s cn66xx; struct cvmx_pciercx_cfg467_s cn68xx; struct cvmx_pciercx_cfg467_s cn68xxp1; + struct cvmx_pciercx_cfg467_s cnf71xx; }; union cvmx_pciercx_cfg468 { uint32_t u32; struct cvmx_pciercx_cfg468_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_24_31:8; uint32_t queue_mode:3; uint32_t reserved_20_20:1; uint32_t header_credits:8; uint32_t data_credits:12; +#else + uint32_t data_credits:12; + uint32_t header_credits:8; + uint32_t reserved_20_20:1; + uint32_t queue_mode:3; + uint32_t reserved_24_31:8; +#endif } s; struct cvmx_pciercx_cfg468_s cn52xx; struct cvmx_pciercx_cfg468_s cn52xxp1; @@ -1855,15 +3011,23 @@ union cvmx_pciercx_cfg468 { struct cvmx_pciercx_cfg468_s cn66xx; struct cvmx_pciercx_cfg468_s cn68xx; struct cvmx_pciercx_cfg468_s cn68xxp1; + struct cvmx_pciercx_cfg468_s cnf71xx; }; union cvmx_pciercx_cfg490 { uint32_t u32; struct cvmx_pciercx_cfg490_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_26_31:6; uint32_t header_depth:10; uint32_t reserved_14_15:2; uint32_t data_depth:14; +#else + uint32_t data_depth:14; + uint32_t reserved_14_15:2; + uint32_t header_depth:10; + uint32_t reserved_26_31:6; +#endif } s; struct cvmx_pciercx_cfg490_s cn52xx; struct cvmx_pciercx_cfg490_s cn52xxp1; @@ -1875,15 +3039,23 @@ union cvmx_pciercx_cfg490 { struct cvmx_pciercx_cfg490_s cn66xx; struct cvmx_pciercx_cfg490_s cn68xx; struct cvmx_pciercx_cfg490_s cn68xxp1; + struct cvmx_pciercx_cfg490_s cnf71xx; }; union cvmx_pciercx_cfg491 { uint32_t u32; struct cvmx_pciercx_cfg491_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_26_31:6; uint32_t header_depth:10; uint32_t reserved_14_15:2; uint32_t data_depth:14; +#else + uint32_t data_depth:14; + uint32_t reserved_14_15:2; + uint32_t header_depth:10; + uint32_t reserved_26_31:6; +#endif } s; struct cvmx_pciercx_cfg491_s cn52xx; struct cvmx_pciercx_cfg491_s cn52xxp1; @@ -1895,15 +3067,23 @@ union cvmx_pciercx_cfg491 { struct cvmx_pciercx_cfg491_s cn66xx; struct cvmx_pciercx_cfg491_s cn68xx; struct cvmx_pciercx_cfg491_s cn68xxp1; + struct cvmx_pciercx_cfg491_s cnf71xx; }; union cvmx_pciercx_cfg492 { uint32_t u32; struct cvmx_pciercx_cfg492_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_26_31:6; uint32_t header_depth:10; uint32_t reserved_14_15:2; uint32_t data_depth:14; +#else + uint32_t data_depth:14; + uint32_t reserved_14_15:2; + uint32_t header_depth:10; + uint32_t reserved_26_31:6; +#endif } s; struct cvmx_pciercx_cfg492_s cn52xx; struct cvmx_pciercx_cfg492_s cn52xxp1; @@ -1915,11 +3095,13 @@ union cvmx_pciercx_cfg492 { struct cvmx_pciercx_cfg492_s cn66xx; struct cvmx_pciercx_cfg492_s cn68xx; struct cvmx_pciercx_cfg492_s cn68xxp1; + struct cvmx_pciercx_cfg492_s cnf71xx; }; union cvmx_pciercx_cfg515 { uint32_t u32; struct cvmx_pciercx_cfg515_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_21_31:11; uint32_t s_d_e:1; uint32_t ctcrb:1; @@ -1927,6 +3109,15 @@ union cvmx_pciercx_cfg515 { uint32_t dsc:1; uint32_t le:9; uint32_t n_fts:8; +#else + uint32_t n_fts:8; + uint32_t le:9; + uint32_t dsc:1; + uint32_t cpyts:1; + uint32_t ctcrb:1; + uint32_t s_d_e:1; + uint32_t reserved_21_31:11; +#endif } s; struct cvmx_pciercx_cfg515_s cn61xx; struct cvmx_pciercx_cfg515_s cn63xx; @@ -1934,12 +3125,17 @@ union cvmx_pciercx_cfg515 { struct cvmx_pciercx_cfg515_s cn66xx; struct cvmx_pciercx_cfg515_s cn68xx; struct cvmx_pciercx_cfg515_s cn68xxp1; + struct cvmx_pciercx_cfg515_s cnf71xx; }; union cvmx_pciercx_cfg516 { uint32_t u32; struct cvmx_pciercx_cfg516_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t phy_stat:32; +#else uint32_t phy_stat:32; +#endif } s; struct cvmx_pciercx_cfg516_s cn52xx; struct cvmx_pciercx_cfg516_s cn52xxp1; @@ -1951,12 +3147,17 @@ union cvmx_pciercx_cfg516 { struct cvmx_pciercx_cfg516_s cn66xx; struct cvmx_pciercx_cfg516_s cn68xx; struct cvmx_pciercx_cfg516_s cn68xxp1; + struct cvmx_pciercx_cfg516_s cnf71xx; }; union cvmx_pciercx_cfg517 { uint32_t u32; struct cvmx_pciercx_cfg517_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t phy_ctrl:32; +#else uint32_t phy_ctrl:32; +#endif } s; struct cvmx_pciercx_cfg517_s cn52xx; struct cvmx_pciercx_cfg517_s cn52xxp1; @@ -1968,6 +3169,7 @@ union cvmx_pciercx_cfg517 { struct cvmx_pciercx_cfg517_s cn66xx; struct cvmx_pciercx_cfg517_s cn68xx; struct cvmx_pciercx_cfg517_s cn68xxp1; + struct cvmx_pciercx_cfg517_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h index d45952df5f5..a5e8fd861c3 100644 --- a/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,44 +28,316 @@ #ifndef __CVMX_PCSX_DEFS_H__ #define __CVMX_PCSX_DEFS_H__ -#define CVMX_PCSX_ANX_ADV_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001010ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_ANX_EXT_ST_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001028ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_ANX_LP_ABIL_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001018ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_ANX_RESULTS_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001020ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_INTX_EN_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001088ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_INTX_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001080ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_LINKX_TIMER_COUNT_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001040ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_LOG_ANLX_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001090ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_MISCX_CTL_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001078ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_MRX_CONTROL_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001000ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_MRX_STATUS_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001008ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_RXX_STATES_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001058ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_RXX_SYNC_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001050ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_SGMX_AN_ADV_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001068ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_SGMX_LP_ADV_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001070ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_TXX_STATES_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001060ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_TX_RXX_POLARITY_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001048ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} union cvmx_pcsx_anx_adv_reg { uint64_t u64; struct cvmx_pcsx_anx_adv_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t np:1; uint64_t reserved_14_14:1; @@ -75,32 +347,67 @@ union cvmx_pcsx_anx_adv_reg { uint64_t hfd:1; uint64_t fd:1; uint64_t reserved_0_4:5; +#else + uint64_t reserved_0_4:5; + uint64_t fd:1; + uint64_t hfd:1; + uint64_t pause:2; + uint64_t reserved_9_11:3; + uint64_t rem_flt:2; + uint64_t reserved_14_14:1; + uint64_t np:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_anx_adv_reg_s cn52xx; struct cvmx_pcsx_anx_adv_reg_s cn52xxp1; struct cvmx_pcsx_anx_adv_reg_s cn56xx; struct cvmx_pcsx_anx_adv_reg_s cn56xxp1; + struct cvmx_pcsx_anx_adv_reg_s cn61xx; + struct cvmx_pcsx_anx_adv_reg_s cn63xx; + struct cvmx_pcsx_anx_adv_reg_s cn63xxp1; + struct cvmx_pcsx_anx_adv_reg_s cn66xx; + struct cvmx_pcsx_anx_adv_reg_s cn68xx; + struct cvmx_pcsx_anx_adv_reg_s cn68xxp1; + struct cvmx_pcsx_anx_adv_reg_s cnf71xx; }; union cvmx_pcsx_anx_ext_st_reg { uint64_t u64; struct cvmx_pcsx_anx_ext_st_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t thou_xfd:1; uint64_t thou_xhd:1; uint64_t thou_tfd:1; uint64_t thou_thd:1; uint64_t reserved_0_11:12; +#else + uint64_t reserved_0_11:12; + uint64_t thou_thd:1; + uint64_t thou_tfd:1; + uint64_t thou_xhd:1; + uint64_t thou_xfd:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_anx_ext_st_reg_s cn52xx; struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1; struct cvmx_pcsx_anx_ext_st_reg_s cn56xx; struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1; + struct cvmx_pcsx_anx_ext_st_reg_s cn61xx; + struct cvmx_pcsx_anx_ext_st_reg_s cn63xx; + struct cvmx_pcsx_anx_ext_st_reg_s cn63xxp1; + struct cvmx_pcsx_anx_ext_st_reg_s cn66xx; + struct cvmx_pcsx_anx_ext_st_reg_s cn68xx; + struct cvmx_pcsx_anx_ext_st_reg_s cn68xxp1; + struct cvmx_pcsx_anx_ext_st_reg_s cnf71xx; }; union cvmx_pcsx_anx_lp_abil_reg { uint64_t u64; struct cvmx_pcsx_anx_lp_abil_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t np:1; uint64_t ack:1; @@ -110,33 +417,69 @@ union cvmx_pcsx_anx_lp_abil_reg { uint64_t hfd:1; uint64_t fd:1; uint64_t reserved_0_4:5; +#else + uint64_t reserved_0_4:5; + uint64_t fd:1; + uint64_t hfd:1; + uint64_t pause:2; + uint64_t reserved_9_11:3; + uint64_t rem_flt:2; + uint64_t ack:1; + uint64_t np:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx; struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1; struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx; struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1; + struct cvmx_pcsx_anx_lp_abil_reg_s cn61xx; + struct cvmx_pcsx_anx_lp_abil_reg_s cn63xx; + struct cvmx_pcsx_anx_lp_abil_reg_s cn63xxp1; + struct cvmx_pcsx_anx_lp_abil_reg_s cn66xx; + struct cvmx_pcsx_anx_lp_abil_reg_s cn68xx; + struct cvmx_pcsx_anx_lp_abil_reg_s cn68xxp1; + struct cvmx_pcsx_anx_lp_abil_reg_s cnf71xx; }; union cvmx_pcsx_anx_results_reg { uint64_t u64; struct cvmx_pcsx_anx_results_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t pause:2; uint64_t spd:2; uint64_t an_cpt:1; uint64_t dup:1; uint64_t link_ok:1; +#else + uint64_t link_ok:1; + uint64_t dup:1; + uint64_t an_cpt:1; + uint64_t spd:2; + uint64_t pause:2; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_pcsx_anx_results_reg_s cn52xx; struct cvmx_pcsx_anx_results_reg_s cn52xxp1; struct cvmx_pcsx_anx_results_reg_s cn56xx; struct cvmx_pcsx_anx_results_reg_s cn56xxp1; + struct cvmx_pcsx_anx_results_reg_s cn61xx; + struct cvmx_pcsx_anx_results_reg_s cn63xx; + struct cvmx_pcsx_anx_results_reg_s cn63xxp1; + struct cvmx_pcsx_anx_results_reg_s cn66xx; + struct cvmx_pcsx_anx_results_reg_s cn68xx; + struct cvmx_pcsx_anx_results_reg_s cn68xxp1; + struct cvmx_pcsx_anx_results_reg_s cnf71xx; }; union cvmx_pcsx_intx_en_reg { uint64_t u64; struct cvmx_pcsx_intx_en_reg_s { - uint64_t reserved_12_63:52; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_13_63:51; + uint64_t dbg_sync_en:1; uint64_t dup:1; uint64_t sync_bad_en:1; uint64_t an_bad_en:1; @@ -149,17 +492,72 @@ union cvmx_pcsx_intx_en_reg { uint64_t an_err_en:1; uint64_t xmit_en:1; uint64_t lnkspd_en:1; +#else + uint64_t lnkspd_en:1; + uint64_t xmit_en:1; + uint64_t an_err_en:1; + uint64_t txfifu_en:1; + uint64_t txfifo_en:1; + uint64_t txbad_en:1; + uint64_t rxerr_en:1; + uint64_t rxbad_en:1; + uint64_t rxlock_en:1; + uint64_t an_bad_en:1; + uint64_t sync_bad_en:1; + uint64_t dup:1; + uint64_t dbg_sync_en:1; + uint64_t reserved_13_63:51; +#endif } s; - struct cvmx_pcsx_intx_en_reg_s cn52xx; - struct cvmx_pcsx_intx_en_reg_s cn52xxp1; - struct cvmx_pcsx_intx_en_reg_s cn56xx; - struct cvmx_pcsx_intx_en_reg_s cn56xxp1; + struct cvmx_pcsx_intx_en_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t dup:1; + uint64_t sync_bad_en:1; + uint64_t an_bad_en:1; + uint64_t rxlock_en:1; + uint64_t rxbad_en:1; + uint64_t rxerr_en:1; + uint64_t txbad_en:1; + uint64_t txfifo_en:1; + uint64_t txfifu_en:1; + uint64_t an_err_en:1; + uint64_t xmit_en:1; + uint64_t lnkspd_en:1; +#else + uint64_t lnkspd_en:1; + uint64_t xmit_en:1; + uint64_t an_err_en:1; + uint64_t txfifu_en:1; + uint64_t txfifo_en:1; + uint64_t txbad_en:1; + uint64_t rxerr_en:1; + uint64_t rxbad_en:1; + uint64_t rxlock_en:1; + uint64_t an_bad_en:1; + uint64_t sync_bad_en:1; + uint64_t dup:1; + uint64_t reserved_12_63:52; +#endif + } cn52xx; + struct cvmx_pcsx_intx_en_reg_cn52xx cn52xxp1; + struct cvmx_pcsx_intx_en_reg_cn52xx cn56xx; + struct cvmx_pcsx_intx_en_reg_cn52xx cn56xxp1; + struct cvmx_pcsx_intx_en_reg_s cn61xx; + struct cvmx_pcsx_intx_en_reg_s cn63xx; + struct cvmx_pcsx_intx_en_reg_s cn63xxp1; + struct cvmx_pcsx_intx_en_reg_s cn66xx; + struct cvmx_pcsx_intx_en_reg_s cn68xx; + struct cvmx_pcsx_intx_en_reg_s cn68xxp1; + struct cvmx_pcsx_intx_en_reg_s cnf71xx; }; union cvmx_pcsx_intx_reg { uint64_t u64; struct cvmx_pcsx_intx_reg_s { - uint64_t reserved_12_63:52; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_13_63:51; + uint64_t dbg_sync:1; uint64_t dup:1; uint64_t sync_bad:1; uint64_t an_bad:1; @@ -172,42 +570,122 @@ union cvmx_pcsx_intx_reg { uint64_t an_err:1; uint64_t xmit:1; uint64_t lnkspd:1; +#else + uint64_t lnkspd:1; + uint64_t xmit:1; + uint64_t an_err:1; + uint64_t txfifu:1; + uint64_t txfifo:1; + uint64_t txbad:1; + uint64_t rxerr:1; + uint64_t rxbad:1; + uint64_t rxlock:1; + uint64_t an_bad:1; + uint64_t sync_bad:1; + uint64_t dup:1; + uint64_t dbg_sync:1; + uint64_t reserved_13_63:51; +#endif } s; - struct cvmx_pcsx_intx_reg_s cn52xx; - struct cvmx_pcsx_intx_reg_s cn52xxp1; - struct cvmx_pcsx_intx_reg_s cn56xx; - struct cvmx_pcsx_intx_reg_s cn56xxp1; + struct cvmx_pcsx_intx_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t dup:1; + uint64_t sync_bad:1; + uint64_t an_bad:1; + uint64_t rxlock:1; + uint64_t rxbad:1; + uint64_t rxerr:1; + uint64_t txbad:1; + uint64_t txfifo:1; + uint64_t txfifu:1; + uint64_t an_err:1; + uint64_t xmit:1; + uint64_t lnkspd:1; +#else + uint64_t lnkspd:1; + uint64_t xmit:1; + uint64_t an_err:1; + uint64_t txfifu:1; + uint64_t txfifo:1; + uint64_t txbad:1; + uint64_t rxerr:1; + uint64_t rxbad:1; + uint64_t rxlock:1; + uint64_t an_bad:1; + uint64_t sync_bad:1; + uint64_t dup:1; + uint64_t reserved_12_63:52; +#endif + } cn52xx; + struct cvmx_pcsx_intx_reg_cn52xx cn52xxp1; + struct cvmx_pcsx_intx_reg_cn52xx cn56xx; + struct cvmx_pcsx_intx_reg_cn52xx cn56xxp1; + struct cvmx_pcsx_intx_reg_s cn61xx; + struct cvmx_pcsx_intx_reg_s cn63xx; + struct cvmx_pcsx_intx_reg_s cn63xxp1; + struct cvmx_pcsx_intx_reg_s cn66xx; + struct cvmx_pcsx_intx_reg_s cn68xx; + struct cvmx_pcsx_intx_reg_s cn68xxp1; + struct cvmx_pcsx_intx_reg_s cnf71xx; }; union cvmx_pcsx_linkx_timer_count_reg { uint64_t u64; struct cvmx_pcsx_linkx_timer_count_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t count:16; +#else + uint64_t count:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx; struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1; struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx; struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1; + struct cvmx_pcsx_linkx_timer_count_reg_s cn61xx; + struct cvmx_pcsx_linkx_timer_count_reg_s cn63xx; + struct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1; + struct cvmx_pcsx_linkx_timer_count_reg_s cn66xx; + struct cvmx_pcsx_linkx_timer_count_reg_s cn68xx; + struct cvmx_pcsx_linkx_timer_count_reg_s cn68xxp1; + struct cvmx_pcsx_linkx_timer_count_reg_s cnf71xx; }; union cvmx_pcsx_log_anlx_reg { uint64_t u64; struct cvmx_pcsx_log_anlx_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t lafifovfl:1; uint64_t la_en:1; uint64_t pkt_sz:2; +#else + uint64_t pkt_sz:2; + uint64_t la_en:1; + uint64_t lafifovfl:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_pcsx_log_anlx_reg_s cn52xx; struct cvmx_pcsx_log_anlx_reg_s cn52xxp1; struct cvmx_pcsx_log_anlx_reg_s cn56xx; struct cvmx_pcsx_log_anlx_reg_s cn56xxp1; + struct cvmx_pcsx_log_anlx_reg_s cn61xx; + struct cvmx_pcsx_log_anlx_reg_s cn63xx; + struct cvmx_pcsx_log_anlx_reg_s cn63xxp1; + struct cvmx_pcsx_log_anlx_reg_s cn66xx; + struct cvmx_pcsx_log_anlx_reg_s cn68xx; + struct cvmx_pcsx_log_anlx_reg_s cn68xxp1; + struct cvmx_pcsx_log_anlx_reg_s cnf71xx; }; union cvmx_pcsx_miscx_ctl_reg { uint64_t u64; struct cvmx_pcsx_miscx_ctl_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t sgmii:1; uint64_t gmxeno:1; @@ -216,16 +694,34 @@ union cvmx_pcsx_miscx_ctl_reg { uint64_t mode:1; uint64_t an_ovrd:1; uint64_t samp_pt:7; +#else + uint64_t samp_pt:7; + uint64_t an_ovrd:1; + uint64_t mode:1; + uint64_t mac_phy:1; + uint64_t loopbck2:1; + uint64_t gmxeno:1; + uint64_t sgmii:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_pcsx_miscx_ctl_reg_s cn52xx; struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1; struct cvmx_pcsx_miscx_ctl_reg_s cn56xx; struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1; + struct cvmx_pcsx_miscx_ctl_reg_s cn61xx; + struct cvmx_pcsx_miscx_ctl_reg_s cn63xx; + struct cvmx_pcsx_miscx_ctl_reg_s cn63xxp1; + struct cvmx_pcsx_miscx_ctl_reg_s cn66xx; + struct cvmx_pcsx_miscx_ctl_reg_s cn68xx; + struct cvmx_pcsx_miscx_ctl_reg_s cn68xxp1; + struct cvmx_pcsx_miscx_ctl_reg_s cnf71xx; }; union cvmx_pcsx_mrx_control_reg { uint64_t u64; struct cvmx_pcsx_mrx_control_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t reset:1; uint64_t loopbck1:1; @@ -239,16 +735,39 @@ union cvmx_pcsx_mrx_control_reg { uint64_t spdmsb:1; uint64_t uni:1; uint64_t reserved_0_4:5; +#else + uint64_t reserved_0_4:5; + uint64_t uni:1; + uint64_t spdmsb:1; + uint64_t coltst:1; + uint64_t dup:1; + uint64_t rst_an:1; + uint64_t reserved_10_10:1; + uint64_t pwr_dn:1; + uint64_t an_en:1; + uint64_t spdlsb:1; + uint64_t loopbck1:1; + uint64_t reset:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_mrx_control_reg_s cn52xx; struct cvmx_pcsx_mrx_control_reg_s cn52xxp1; struct cvmx_pcsx_mrx_control_reg_s cn56xx; struct cvmx_pcsx_mrx_control_reg_s cn56xxp1; + struct cvmx_pcsx_mrx_control_reg_s cn61xx; + struct cvmx_pcsx_mrx_control_reg_s cn63xx; + struct cvmx_pcsx_mrx_control_reg_s cn63xxp1; + struct cvmx_pcsx_mrx_control_reg_s cn66xx; + struct cvmx_pcsx_mrx_control_reg_s cn68xx; + struct cvmx_pcsx_mrx_control_reg_s cn68xxp1; + struct cvmx_pcsx_mrx_control_reg_s cnf71xx; }; union cvmx_pcsx_mrx_status_reg { uint64_t u64; struct cvmx_pcsx_mrx_status_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t hun_t4:1; uint64_t hun_xfd:1; @@ -266,16 +785,43 @@ union cvmx_pcsx_mrx_status_reg { uint64_t lnk_st:1; uint64_t reserved_1_1:1; uint64_t extnd:1; +#else + uint64_t extnd:1; + uint64_t reserved_1_1:1; + uint64_t lnk_st:1; + uint64_t an_abil:1; + uint64_t rm_flt:1; + uint64_t an_cpt:1; + uint64_t prb_sup:1; + uint64_t reserved_7_7:1; + uint64_t ext_st:1; + uint64_t hun_t2hd:1; + uint64_t hun_t2fd:1; + uint64_t ten_hd:1; + uint64_t ten_fd:1; + uint64_t hun_xhd:1; + uint64_t hun_xfd:1; + uint64_t hun_t4:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_mrx_status_reg_s cn52xx; struct cvmx_pcsx_mrx_status_reg_s cn52xxp1; struct cvmx_pcsx_mrx_status_reg_s cn56xx; struct cvmx_pcsx_mrx_status_reg_s cn56xxp1; + struct cvmx_pcsx_mrx_status_reg_s cn61xx; + struct cvmx_pcsx_mrx_status_reg_s cn63xx; + struct cvmx_pcsx_mrx_status_reg_s cn63xxp1; + struct cvmx_pcsx_mrx_status_reg_s cn66xx; + struct cvmx_pcsx_mrx_status_reg_s cn68xx; + struct cvmx_pcsx_mrx_status_reg_s cn68xxp1; + struct cvmx_pcsx_mrx_status_reg_s cnf71xx; }; union cvmx_pcsx_rxx_states_reg { uint64_t u64; struct cvmx_pcsx_rxx_states_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t rx_bad:1; uint64_t rx_st:5; @@ -283,29 +829,59 @@ union cvmx_pcsx_rxx_states_reg { uint64_t sync:4; uint64_t an_bad:1; uint64_t an_st:4; +#else + uint64_t an_st:4; + uint64_t an_bad:1; + uint64_t sync:4; + uint64_t sync_bad:1; + uint64_t rx_st:5; + uint64_t rx_bad:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_rxx_states_reg_s cn52xx; struct cvmx_pcsx_rxx_states_reg_s cn52xxp1; struct cvmx_pcsx_rxx_states_reg_s cn56xx; struct cvmx_pcsx_rxx_states_reg_s cn56xxp1; + struct cvmx_pcsx_rxx_states_reg_s cn61xx; + struct cvmx_pcsx_rxx_states_reg_s cn63xx; + struct cvmx_pcsx_rxx_states_reg_s cn63xxp1; + struct cvmx_pcsx_rxx_states_reg_s cn66xx; + struct cvmx_pcsx_rxx_states_reg_s cn68xx; + struct cvmx_pcsx_rxx_states_reg_s cn68xxp1; + struct cvmx_pcsx_rxx_states_reg_s cnf71xx; }; union cvmx_pcsx_rxx_sync_reg { uint64_t u64; struct cvmx_pcsx_rxx_sync_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t sync:1; uint64_t bit_lock:1; +#else + uint64_t bit_lock:1; + uint64_t sync:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_pcsx_rxx_sync_reg_s cn52xx; struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1; struct cvmx_pcsx_rxx_sync_reg_s cn56xx; struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1; + struct cvmx_pcsx_rxx_sync_reg_s cn61xx; + struct cvmx_pcsx_rxx_sync_reg_s cn63xx; + struct cvmx_pcsx_rxx_sync_reg_s cn63xxp1; + struct cvmx_pcsx_rxx_sync_reg_s cn66xx; + struct cvmx_pcsx_rxx_sync_reg_s cn68xx; + struct cvmx_pcsx_rxx_sync_reg_s cn68xxp1; + struct cvmx_pcsx_rxx_sync_reg_s cnf71xx; }; union cvmx_pcsx_sgmx_an_adv_reg { uint64_t u64; struct cvmx_pcsx_sgmx_an_adv_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t link:1; uint64_t ack:1; @@ -314,16 +890,34 @@ union cvmx_pcsx_sgmx_an_adv_reg { uint64_t speed:2; uint64_t reserved_1_9:9; uint64_t one:1; +#else + uint64_t one:1; + uint64_t reserved_1_9:9; + uint64_t speed:2; + uint64_t dup:1; + uint64_t reserved_13_13:1; + uint64_t ack:1; + uint64_t link:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx; struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1; struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx; struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn61xx; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xx; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xxp1; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn66xx; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xx; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xxp1; + struct cvmx_pcsx_sgmx_an_adv_reg_s cnf71xx; }; union cvmx_pcsx_sgmx_lp_adv_reg { uint64_t u64; struct cvmx_pcsx_sgmx_lp_adv_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t link:1; uint64_t reserved_13_14:2; @@ -331,40 +925,85 @@ union cvmx_pcsx_sgmx_lp_adv_reg { uint64_t speed:2; uint64_t reserved_1_9:9; uint64_t one:1; +#else + uint64_t one:1; + uint64_t reserved_1_9:9; + uint64_t speed:2; + uint64_t dup:1; + uint64_t reserved_13_14:2; + uint64_t link:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx; struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1; struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx; struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn61xx; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xx; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xxp1; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn66xx; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xx; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xxp1; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cnf71xx; }; union cvmx_pcsx_txx_states_reg { uint64_t u64; struct cvmx_pcsx_txx_states_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t xmit:2; uint64_t tx_bad:1; uint64_t ord_st:4; +#else + uint64_t ord_st:4; + uint64_t tx_bad:1; + uint64_t xmit:2; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_pcsx_txx_states_reg_s cn52xx; struct cvmx_pcsx_txx_states_reg_s cn52xxp1; struct cvmx_pcsx_txx_states_reg_s cn56xx; struct cvmx_pcsx_txx_states_reg_s cn56xxp1; + struct cvmx_pcsx_txx_states_reg_s cn61xx; + struct cvmx_pcsx_txx_states_reg_s cn63xx; + struct cvmx_pcsx_txx_states_reg_s cn63xxp1; + struct cvmx_pcsx_txx_states_reg_s cn66xx; + struct cvmx_pcsx_txx_states_reg_s cn68xx; + struct cvmx_pcsx_txx_states_reg_s cn68xxp1; + struct cvmx_pcsx_txx_states_reg_s cnf71xx; }; union cvmx_pcsx_tx_rxx_polarity_reg { uint64_t u64; struct cvmx_pcsx_tx_rxx_polarity_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t rxovrd:1; uint64_t autorxpl:1; uint64_t rxplrt:1; uint64_t txplrt:1; +#else + uint64_t txplrt:1; + uint64_t rxplrt:1; + uint64_t autorxpl:1; + uint64_t rxovrd:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx; struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1; struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx; struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn61xx; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn66xx; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xx; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xxp1; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h index 55d120fe8ae..b5b45d26f1c 100644 --- a/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,40 +28,250 @@ #ifndef __CVMX_PCSXX_DEFS_H__ #define __CVMX_PCSXX_DEFS_H__ -#define CVMX_PCSXX_10GBX_STATUS_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000828ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_BIST_STATUS_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000870ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000850ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_CONTROL1_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000800ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_CONTROL2_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000818ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_INT_EN_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000860ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_INT_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000858ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_LOG_ANL_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000868ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_MISC_CTL_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000848ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000838ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_SPD_ABIL_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000810ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_STATUS1_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000808ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_STATUS2_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000820ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000840ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_TX_RX_STATES_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000830ull + (((block_id) & 1) * 0x8000000ull)) +static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull; +} + +static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull; +} union cvmx_pcsxx_10gbx_status_reg { uint64_t u64; struct cvmx_pcsxx_10gbx_status_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t alignd:1; uint64_t pattst:1; @@ -70,43 +280,85 @@ union cvmx_pcsxx_10gbx_status_reg { uint64_t l2sync:1; uint64_t l1sync:1; uint64_t l0sync:1; +#else + uint64_t l0sync:1; + uint64_t l1sync:1; + uint64_t l2sync:1; + uint64_t l3sync:1; + uint64_t reserved_4_10:7; + uint64_t pattst:1; + uint64_t alignd:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_pcsxx_10gbx_status_reg_s cn52xx; struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1; struct cvmx_pcsxx_10gbx_status_reg_s cn56xx; struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1; + struct cvmx_pcsxx_10gbx_status_reg_s cn61xx; + struct cvmx_pcsxx_10gbx_status_reg_s cn63xx; + struct cvmx_pcsxx_10gbx_status_reg_s cn63xxp1; + struct cvmx_pcsxx_10gbx_status_reg_s cn66xx; + struct cvmx_pcsxx_10gbx_status_reg_s cn68xx; + struct cvmx_pcsxx_10gbx_status_reg_s cn68xxp1; }; union cvmx_pcsxx_bist_status_reg { uint64_t u64; struct cvmx_pcsxx_bist_status_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t bist_status:1; +#else + uint64_t bist_status:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_pcsxx_bist_status_reg_s cn52xx; struct cvmx_pcsxx_bist_status_reg_s cn52xxp1; struct cvmx_pcsxx_bist_status_reg_s cn56xx; struct cvmx_pcsxx_bist_status_reg_s cn56xxp1; + struct cvmx_pcsxx_bist_status_reg_s cn61xx; + struct cvmx_pcsxx_bist_status_reg_s cn63xx; + struct cvmx_pcsxx_bist_status_reg_s cn63xxp1; + struct cvmx_pcsxx_bist_status_reg_s cn66xx; + struct cvmx_pcsxx_bist_status_reg_s cn68xx; + struct cvmx_pcsxx_bist_status_reg_s cn68xxp1; }; union cvmx_pcsxx_bit_lock_status_reg { uint64_t u64; struct cvmx_pcsxx_bit_lock_status_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t bitlck3:1; uint64_t bitlck2:1; uint64_t bitlck1:1; uint64_t bitlck0:1; +#else + uint64_t bitlck0:1; + uint64_t bitlck1:1; + uint64_t bitlck2:1; + uint64_t bitlck3:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx; struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1; struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx; struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1; + struct cvmx_pcsxx_bit_lock_status_reg_s cn61xx; + struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx; + struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1; + struct cvmx_pcsxx_bit_lock_status_reg_s cn66xx; + struct cvmx_pcsxx_bit_lock_status_reg_s cn68xx; + struct cvmx_pcsxx_bit_lock_status_reg_s cn68xxp1; }; union cvmx_pcsxx_control1_reg { uint64_t u64; struct cvmx_pcsxx_control1_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t reset:1; uint64_t loopbck1:1; @@ -117,137 +369,309 @@ union cvmx_pcsxx_control1_reg { uint64_t spdsel0:1; uint64_t spd:4; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t spd:4; + uint64_t spdsel0:1; + uint64_t reserved_7_10:4; + uint64_t lo_pwr:1; + uint64_t reserved_12_12:1; + uint64_t spdsel1:1; + uint64_t loopbck1:1; + uint64_t reset:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsxx_control1_reg_s cn52xx; struct cvmx_pcsxx_control1_reg_s cn52xxp1; struct cvmx_pcsxx_control1_reg_s cn56xx; struct cvmx_pcsxx_control1_reg_s cn56xxp1; + struct cvmx_pcsxx_control1_reg_s cn61xx; + struct cvmx_pcsxx_control1_reg_s cn63xx; + struct cvmx_pcsxx_control1_reg_s cn63xxp1; + struct cvmx_pcsxx_control1_reg_s cn66xx; + struct cvmx_pcsxx_control1_reg_s cn68xx; + struct cvmx_pcsxx_control1_reg_s cn68xxp1; }; union cvmx_pcsxx_control2_reg { uint64_t u64; struct cvmx_pcsxx_control2_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t type:2; +#else + uint64_t type:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_pcsxx_control2_reg_s cn52xx; struct cvmx_pcsxx_control2_reg_s cn52xxp1; struct cvmx_pcsxx_control2_reg_s cn56xx; struct cvmx_pcsxx_control2_reg_s cn56xxp1; + struct cvmx_pcsxx_control2_reg_s cn61xx; + struct cvmx_pcsxx_control2_reg_s cn63xx; + struct cvmx_pcsxx_control2_reg_s cn63xxp1; + struct cvmx_pcsxx_control2_reg_s cn66xx; + struct cvmx_pcsxx_control2_reg_s cn68xx; + struct cvmx_pcsxx_control2_reg_s cn68xxp1; }; union cvmx_pcsxx_int_en_reg { uint64_t u64; struct cvmx_pcsxx_int_en_reg_s { - uint64_t reserved_6_63:58; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t dbg_sync_en:1; uint64_t algnlos_en:1; uint64_t synlos_en:1; uint64_t bitlckls_en:1; uint64_t rxsynbad_en:1; uint64_t rxbad_en:1; uint64_t txflt_en:1; +#else + uint64_t txflt_en:1; + uint64_t rxbad_en:1; + uint64_t rxsynbad_en:1; + uint64_t bitlckls_en:1; + uint64_t synlos_en:1; + uint64_t algnlos_en:1; + uint64_t dbg_sync_en:1; + uint64_t reserved_7_63:57; +#endif } s; - struct cvmx_pcsxx_int_en_reg_s cn52xx; - struct cvmx_pcsxx_int_en_reg_s cn52xxp1; - struct cvmx_pcsxx_int_en_reg_s cn56xx; - struct cvmx_pcsxx_int_en_reg_s cn56xxp1; + struct cvmx_pcsxx_int_en_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_6_63:58; + uint64_t algnlos_en:1; + uint64_t synlos_en:1; + uint64_t bitlckls_en:1; + uint64_t rxsynbad_en:1; + uint64_t rxbad_en:1; + uint64_t txflt_en:1; +#else + uint64_t txflt_en:1; + uint64_t rxbad_en:1; + uint64_t rxsynbad_en:1; + uint64_t bitlckls_en:1; + uint64_t synlos_en:1; + uint64_t algnlos_en:1; + uint64_t reserved_6_63:58; +#endif + } cn52xx; + struct cvmx_pcsxx_int_en_reg_cn52xx cn52xxp1; + struct cvmx_pcsxx_int_en_reg_cn52xx cn56xx; + struct cvmx_pcsxx_int_en_reg_cn52xx cn56xxp1; + struct cvmx_pcsxx_int_en_reg_s cn61xx; + struct cvmx_pcsxx_int_en_reg_s cn63xx; + struct cvmx_pcsxx_int_en_reg_s cn63xxp1; + struct cvmx_pcsxx_int_en_reg_s cn66xx; + struct cvmx_pcsxx_int_en_reg_s cn68xx; + struct cvmx_pcsxx_int_en_reg_s cn68xxp1; }; union cvmx_pcsxx_int_reg { uint64_t u64; struct cvmx_pcsxx_int_reg_s { - uint64_t reserved_6_63:58; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t dbg_sync:1; uint64_t algnlos:1; uint64_t synlos:1; uint64_t bitlckls:1; uint64_t rxsynbad:1; uint64_t rxbad:1; uint64_t txflt:1; +#else + uint64_t txflt:1; + uint64_t rxbad:1; + uint64_t rxsynbad:1; + uint64_t bitlckls:1; + uint64_t synlos:1; + uint64_t algnlos:1; + uint64_t dbg_sync:1; + uint64_t reserved_7_63:57; +#endif } s; - struct cvmx_pcsxx_int_reg_s cn52xx; - struct cvmx_pcsxx_int_reg_s cn52xxp1; - struct cvmx_pcsxx_int_reg_s cn56xx; - struct cvmx_pcsxx_int_reg_s cn56xxp1; + struct cvmx_pcsxx_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_6_63:58; + uint64_t algnlos:1; + uint64_t synlos:1; + uint64_t bitlckls:1; + uint64_t rxsynbad:1; + uint64_t rxbad:1; + uint64_t txflt:1; +#else + uint64_t txflt:1; + uint64_t rxbad:1; + uint64_t rxsynbad:1; + uint64_t bitlckls:1; + uint64_t synlos:1; + uint64_t algnlos:1; + uint64_t reserved_6_63:58; +#endif + } cn52xx; + struct cvmx_pcsxx_int_reg_cn52xx cn52xxp1; + struct cvmx_pcsxx_int_reg_cn52xx cn56xx; + struct cvmx_pcsxx_int_reg_cn52xx cn56xxp1; + struct cvmx_pcsxx_int_reg_s cn61xx; + struct cvmx_pcsxx_int_reg_s cn63xx; + struct cvmx_pcsxx_int_reg_s cn63xxp1; + struct cvmx_pcsxx_int_reg_s cn66xx; + struct cvmx_pcsxx_int_reg_s cn68xx; + struct cvmx_pcsxx_int_reg_s cn68xxp1; }; union cvmx_pcsxx_log_anl_reg { uint64_t u64; struct cvmx_pcsxx_log_anl_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t enc_mode:1; uint64_t drop_ln:2; uint64_t lafifovfl:1; uint64_t la_en:1; uint64_t pkt_sz:2; +#else + uint64_t pkt_sz:2; + uint64_t la_en:1; + uint64_t lafifovfl:1; + uint64_t drop_ln:2; + uint64_t enc_mode:1; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_pcsxx_log_anl_reg_s cn52xx; struct cvmx_pcsxx_log_anl_reg_s cn52xxp1; struct cvmx_pcsxx_log_anl_reg_s cn56xx; struct cvmx_pcsxx_log_anl_reg_s cn56xxp1; + struct cvmx_pcsxx_log_anl_reg_s cn61xx; + struct cvmx_pcsxx_log_anl_reg_s cn63xx; + struct cvmx_pcsxx_log_anl_reg_s cn63xxp1; + struct cvmx_pcsxx_log_anl_reg_s cn66xx; + struct cvmx_pcsxx_log_anl_reg_s cn68xx; + struct cvmx_pcsxx_log_anl_reg_s cn68xxp1; }; union cvmx_pcsxx_misc_ctl_reg { uint64_t u64; struct cvmx_pcsxx_misc_ctl_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t tx_swap:1; uint64_t rx_swap:1; uint64_t xaui:1; uint64_t gmxeno:1; +#else + uint64_t gmxeno:1; + uint64_t xaui:1; + uint64_t rx_swap:1; + uint64_t tx_swap:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_pcsxx_misc_ctl_reg_s cn52xx; struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1; struct cvmx_pcsxx_misc_ctl_reg_s cn56xx; struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1; + struct cvmx_pcsxx_misc_ctl_reg_s cn61xx; + struct cvmx_pcsxx_misc_ctl_reg_s cn63xx; + struct cvmx_pcsxx_misc_ctl_reg_s cn63xxp1; + struct cvmx_pcsxx_misc_ctl_reg_s cn66xx; + struct cvmx_pcsxx_misc_ctl_reg_s cn68xx; + struct cvmx_pcsxx_misc_ctl_reg_s cn68xxp1; }; union cvmx_pcsxx_rx_sync_states_reg { uint64_t u64; struct cvmx_pcsxx_rx_sync_states_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t sync3st:4; uint64_t sync2st:4; uint64_t sync1st:4; uint64_t sync0st:4; +#else + uint64_t sync0st:4; + uint64_t sync1st:4; + uint64_t sync2st:4; + uint64_t sync3st:4; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx; struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1; struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx; struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1; + struct cvmx_pcsxx_rx_sync_states_reg_s cn61xx; + struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx; + struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1; + struct cvmx_pcsxx_rx_sync_states_reg_s cn66xx; + struct cvmx_pcsxx_rx_sync_states_reg_s cn68xx; + struct cvmx_pcsxx_rx_sync_states_reg_s cn68xxp1; }; union cvmx_pcsxx_spd_abil_reg { uint64_t u64; struct cvmx_pcsxx_spd_abil_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t tenpasst:1; uint64_t tengb:1; +#else + uint64_t tengb:1; + uint64_t tenpasst:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_pcsxx_spd_abil_reg_s cn52xx; struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1; struct cvmx_pcsxx_spd_abil_reg_s cn56xx; struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1; + struct cvmx_pcsxx_spd_abil_reg_s cn61xx; + struct cvmx_pcsxx_spd_abil_reg_s cn63xx; + struct cvmx_pcsxx_spd_abil_reg_s cn63xxp1; + struct cvmx_pcsxx_spd_abil_reg_s cn66xx; + struct cvmx_pcsxx_spd_abil_reg_s cn68xx; + struct cvmx_pcsxx_spd_abil_reg_s cn68xxp1; }; union cvmx_pcsxx_status1_reg { uint64_t u64; struct cvmx_pcsxx_status1_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t flt:1; uint64_t reserved_3_6:4; uint64_t rcv_lnk:1; uint64_t lpable:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t lpable:1; + uint64_t rcv_lnk:1; + uint64_t reserved_3_6:4; + uint64_t flt:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_pcsxx_status1_reg_s cn52xx; struct cvmx_pcsxx_status1_reg_s cn52xxp1; struct cvmx_pcsxx_status1_reg_s cn56xx; struct cvmx_pcsxx_status1_reg_s cn56xxp1; + struct cvmx_pcsxx_status1_reg_s cn61xx; + struct cvmx_pcsxx_status1_reg_s cn63xx; + struct cvmx_pcsxx_status1_reg_s cn63xxp1; + struct cvmx_pcsxx_status1_reg_s cn66xx; + struct cvmx_pcsxx_status1_reg_s cn68xx; + struct cvmx_pcsxx_status1_reg_s cn68xxp1; }; union cvmx_pcsxx_status2_reg { uint64_t u64; struct cvmx_pcsxx_status2_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t dev:2; uint64_t reserved_12_13:2; @@ -257,35 +681,73 @@ union cvmx_pcsxx_status2_reg { uint64_t tengb_w:1; uint64_t tengb_x:1; uint64_t tengb_r:1; +#else + uint64_t tengb_r:1; + uint64_t tengb_x:1; + uint64_t tengb_w:1; + uint64_t reserved_3_9:7; + uint64_t rcvflt:1; + uint64_t xmtflt:1; + uint64_t reserved_12_13:2; + uint64_t dev:2; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pcsxx_status2_reg_s cn52xx; struct cvmx_pcsxx_status2_reg_s cn52xxp1; struct cvmx_pcsxx_status2_reg_s cn56xx; struct cvmx_pcsxx_status2_reg_s cn56xxp1; + struct cvmx_pcsxx_status2_reg_s cn61xx; + struct cvmx_pcsxx_status2_reg_s cn63xx; + struct cvmx_pcsxx_status2_reg_s cn63xxp1; + struct cvmx_pcsxx_status2_reg_s cn66xx; + struct cvmx_pcsxx_status2_reg_s cn68xx; + struct cvmx_pcsxx_status2_reg_s cn68xxp1; }; union cvmx_pcsxx_tx_rx_polarity_reg { uint64_t u64; struct cvmx_pcsxx_tx_rx_polarity_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t xor_rxplrt:4; uint64_t xor_txplrt:4; uint64_t rxplrt:1; uint64_t txplrt:1; +#else + uint64_t txplrt:1; + uint64_t rxplrt:1; + uint64_t xor_txplrt:4; + uint64_t xor_rxplrt:4; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx; struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t rxplrt:1; uint64_t txplrt:1; +#else + uint64_t txplrt:1; + uint64_t rxplrt:1; + uint64_t reserved_2_63:62; +#endif } cn52xxp1; struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx; struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1; + struct cvmx_pcsxx_tx_rx_polarity_reg_s cn61xx; + struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx; + struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1; + struct cvmx_pcsxx_tx_rx_polarity_reg_s cn66xx; + struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xx; + struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xxp1; }; union cvmx_pcsxx_tx_rx_states_reg { uint64_t u64; struct cvmx_pcsxx_tx_rx_states_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t term_err:1; uint64_t syn3bad:1; @@ -296,9 +758,22 @@ union cvmx_pcsxx_tx_rx_states_reg { uint64_t algn_st:3; uint64_t rx_st:2; uint64_t tx_st:3; +#else + uint64_t tx_st:3; + uint64_t rx_st:2; + uint64_t algn_st:3; + uint64_t rxbad:1; + uint64_t syn0bad:1; + uint64_t syn1bad:1; + uint64_t syn2bad:1; + uint64_t syn3bad:1; + uint64_t term_err:1; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx; struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t syn3bad:1; uint64_t syn2bad:1; @@ -308,9 +783,26 @@ union cvmx_pcsxx_tx_rx_states_reg { uint64_t algn_st:3; uint64_t rx_st:2; uint64_t tx_st:3; +#else + uint64_t tx_st:3; + uint64_t rx_st:2; + uint64_t algn_st:3; + uint64_t rxbad:1; + uint64_t syn0bad:1; + uint64_t syn1bad:1; + uint64_t syn2bad:1; + uint64_t syn3bad:1; + uint64_t reserved_13_63:51; +#endif } cn52xxp1; struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx; struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1; + struct cvmx_pcsxx_tx_rx_states_reg_s cn61xx; + struct cvmx_pcsxx_tx_rx_states_reg_s cn63xx; + struct cvmx_pcsxx_tx_rx_states_reg_s cn63xxp1; + struct cvmx_pcsxx_tx_rx_states_reg_s cn66xx; + struct cvmx_pcsxx_tx_rx_states_reg_s cn68xx; + struct cvmx_pcsxx_tx_rx_states_reg_s cn68xxp1; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-pemx-defs.h b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h index be189a2585e..50a916f892f 100644 --- a/arch/mips/include/asm/octeon/cvmx-pemx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2011 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -54,11 +54,19 @@ union cvmx_pemx_bar1_indexx { uint64_t u64; struct cvmx_pemx_bar1_indexx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t addr_idx:16; uint64_t ca:1; uint64_t end_swp:2; uint64_t addr_v:1; +#else + uint64_t addr_v:1; + uint64_t end_swp:2; + uint64_t ca:1; + uint64_t addr_idx:16; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_pemx_bar1_indexx_s cn61xx; struct cvmx_pemx_bar1_indexx_s cn63xx; @@ -66,29 +74,45 @@ union cvmx_pemx_bar1_indexx { struct cvmx_pemx_bar1_indexx_s cn66xx; struct cvmx_pemx_bar1_indexx_s cn68xx; struct cvmx_pemx_bar1_indexx_s cn68xxp1; + struct cvmx_pemx_bar1_indexx_s cnf71xx; }; union cvmx_pemx_bar2_mask { uint64_t u64; struct cvmx_pemx_bar2_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t mask:35; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t mask:35; + uint64_t reserved_38_63:26; +#endif } s; struct cvmx_pemx_bar2_mask_s cn61xx; struct cvmx_pemx_bar2_mask_s cn66xx; struct cvmx_pemx_bar2_mask_s cn68xx; struct cvmx_pemx_bar2_mask_s cn68xxp1; + struct cvmx_pemx_bar2_mask_s cnf71xx; }; union cvmx_pemx_bar_ctl { uint64_t u64; struct cvmx_pemx_bar_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t bar1_siz:3; uint64_t bar2_enb:1; uint64_t bar2_esx:2; uint64_t bar2_cax:1; +#else + uint64_t bar2_cax:1; + uint64_t bar2_esx:2; + uint64_t bar2_enb:1; + uint64_t bar1_siz:3; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_pemx_bar_ctl_s cn61xx; struct cvmx_pemx_bar_ctl_s cn63xx; @@ -96,11 +120,13 @@ union cvmx_pemx_bar_ctl { struct cvmx_pemx_bar_ctl_s cn66xx; struct cvmx_pemx_bar_ctl_s cn68xx; struct cvmx_pemx_bar_ctl_s cn68xxp1; + struct cvmx_pemx_bar_ctl_s cnf71xx; }; union cvmx_pemx_bist_status { uint64_t u64; struct cvmx_pemx_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t retry:1; uint64_t rqdata0:1; @@ -110,6 +136,17 @@ union cvmx_pemx_bist_status { uint64_t rqhdr1:1; uint64_t rqhdr0:1; uint64_t sot:1; +#else + uint64_t sot:1; + uint64_t rqhdr0:1; + uint64_t rqhdr1:1; + uint64_t rqdata3:1; + uint64_t rqdata2:1; + uint64_t rqdata1:1; + uint64_t rqdata0:1; + uint64_t retry:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_pemx_bist_status_s cn61xx; struct cvmx_pemx_bist_status_s cn63xx; @@ -117,11 +154,13 @@ union cvmx_pemx_bist_status { struct cvmx_pemx_bist_status_s cn66xx; struct cvmx_pemx_bist_status_s cn68xx; struct cvmx_pemx_bist_status_s cn68xxp1; + struct cvmx_pemx_bist_status_s cnf71xx; }; union cvmx_pemx_bist_status2 { uint64_t u64; struct cvmx_pemx_bist_status2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t e2p_cpl:1; uint64_t e2p_n:1; @@ -133,6 +172,19 @@ union cvmx_pemx_bist_status2 { uint64_t pef_tcf1:1; uint64_t pef_tc0:1; uint64_t ppf:1; +#else + uint64_t ppf:1; + uint64_t pef_tc0:1; + uint64_t pef_tcf1:1; + uint64_t pef_tnf:1; + uint64_t pef_tpf0:1; + uint64_t pef_tpf1:1; + uint64_t peai_p2e:1; + uint64_t e2p_p:1; + uint64_t e2p_n:1; + uint64_t e2p_cpl:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_pemx_bist_status2_s cn61xx; struct cvmx_pemx_bist_status2_s cn63xx; @@ -140,13 +192,19 @@ union cvmx_pemx_bist_status2 { struct cvmx_pemx_bist_status2_s cn66xx; struct cvmx_pemx_bist_status2_s cn68xx; struct cvmx_pemx_bist_status2_s cn68xxp1; + struct cvmx_pemx_bist_status2_s cnf71xx; }; union cvmx_pemx_cfg_rd { uint64_t u64; struct cvmx_pemx_cfg_rd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:32; uint64_t addr:32; +#else + uint64_t addr:32; + uint64_t data:32; +#endif } s; struct cvmx_pemx_cfg_rd_s cn61xx; struct cvmx_pemx_cfg_rd_s cn63xx; @@ -154,13 +212,19 @@ union cvmx_pemx_cfg_rd { struct cvmx_pemx_cfg_rd_s cn66xx; struct cvmx_pemx_cfg_rd_s cn68xx; struct cvmx_pemx_cfg_rd_s cn68xxp1; + struct cvmx_pemx_cfg_rd_s cnf71xx; }; union cvmx_pemx_cfg_wr { uint64_t u64; struct cvmx_pemx_cfg_wr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:32; uint64_t addr:32; +#else + uint64_t addr:32; + uint64_t data:32; +#endif } s; struct cvmx_pemx_cfg_wr_s cn61xx; struct cvmx_pemx_cfg_wr_s cn63xx; @@ -168,13 +232,19 @@ union cvmx_pemx_cfg_wr { struct cvmx_pemx_cfg_wr_s cn66xx; struct cvmx_pemx_cfg_wr_s cn68xx; struct cvmx_pemx_cfg_wr_s cn68xxp1; + struct cvmx_pemx_cfg_wr_s cnf71xx; }; union cvmx_pemx_cpl_lut_valid { uint64_t u64; struct cvmx_pemx_cpl_lut_valid_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t tag:32; +#else + uint64_t tag:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pemx_cpl_lut_valid_s cn61xx; struct cvmx_pemx_cpl_lut_valid_s cn63xx; @@ -182,11 +252,13 @@ union cvmx_pemx_cpl_lut_valid { struct cvmx_pemx_cpl_lut_valid_s cn66xx; struct cvmx_pemx_cpl_lut_valid_s cn68xx; struct cvmx_pemx_cpl_lut_valid_s cn68xxp1; + struct cvmx_pemx_cpl_lut_valid_s cnf71xx; }; union cvmx_pemx_ctl_status { uint64_t u64; struct cvmx_pemx_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t auto_sd:1; uint64_t dnum:5; @@ -205,6 +277,26 @@ union cvmx_pemx_ctl_status { uint64_t fast_lm:1; uint64_t inv_ecrc:1; uint64_t inv_lcrc:1; +#else + uint64_t inv_lcrc:1; + uint64_t inv_ecrc:1; + uint64_t fast_lm:1; + uint64_t ro_ctlp:1; + uint64_t lnk_enb:1; + uint64_t dly_one:1; + uint64_t nf_ecrc:1; + uint64_t reserved_7_8:2; + uint64_t ob_p_cmd:1; + uint64_t pm_xpme:1; + uint64_t pm_xtoff:1; + uint64_t reserved_12_15:4; + uint64_t cfg_rtry:16; + uint64_t reserved_32_33:2; + uint64_t pbus:8; + uint64_t dnum:5; + uint64_t auto_sd:1; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_pemx_ctl_status_s cn61xx; struct cvmx_pemx_ctl_status_s cn63xx; @@ -212,11 +304,13 @@ union cvmx_pemx_ctl_status { struct cvmx_pemx_ctl_status_s cn66xx; struct cvmx_pemx_ctl_status_s cn68xx; struct cvmx_pemx_ctl_status_s cn68xxp1; + struct cvmx_pemx_ctl_status_s cnf71xx; }; union cvmx_pemx_dbg_info { uint64_t u64; struct cvmx_pemx_dbg_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t ecrc_e:1; uint64_t rawwpp:1; @@ -249,6 +343,40 @@ union cvmx_pemx_dbg_info { uint64_t rtlplle:1; uint64_t rtlpmal:1; uint64_t spoison:1; +#else + uint64_t spoison:1; + uint64_t rtlpmal:1; + uint64_t rtlplle:1; + uint64_t recrce:1; + uint64_t rpoison:1; + uint64_t rcemrc:1; + uint64_t rnfemrc:1; + uint64_t rfemrc:1; + uint64_t rpmerc:1; + uint64_t rptamrc:1; + uint64_t rumep:1; + uint64_t rvdm:1; + uint64_t acto:1; + uint64_t rte:1; + uint64_t mre:1; + uint64_t rdwdle:1; + uint64_t rtwdle:1; + uint64_t dpeoosd:1; + uint64_t fcpvwt:1; + uint64_t rpe:1; + uint64_t fcuv:1; + uint64_t rqo:1; + uint64_t rauc:1; + uint64_t racur:1; + uint64_t racca:1; + uint64_t caar:1; + uint64_t rarwdns:1; + uint64_t ramtlp:1; + uint64_t racpp:1; + uint64_t rawwpp:1; + uint64_t ecrc_e:1; + uint64_t reserved_31_63:33; +#endif } s; struct cvmx_pemx_dbg_info_s cn61xx; struct cvmx_pemx_dbg_info_s cn63xx; @@ -256,11 +384,13 @@ union cvmx_pemx_dbg_info { struct cvmx_pemx_dbg_info_s cn66xx; struct cvmx_pemx_dbg_info_s cn68xx; struct cvmx_pemx_dbg_info_s cn68xxp1; + struct cvmx_pemx_dbg_info_s cnf71xx; }; union cvmx_pemx_dbg_info_en { uint64_t u64; struct cvmx_pemx_dbg_info_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t ecrc_e:1; uint64_t rawwpp:1; @@ -293,6 +423,40 @@ union cvmx_pemx_dbg_info_en { uint64_t rtlplle:1; uint64_t rtlpmal:1; uint64_t spoison:1; +#else + uint64_t spoison:1; + uint64_t rtlpmal:1; + uint64_t rtlplle:1; + uint64_t recrce:1; + uint64_t rpoison:1; + uint64_t rcemrc:1; + uint64_t rnfemrc:1; + uint64_t rfemrc:1; + uint64_t rpmerc:1; + uint64_t rptamrc:1; + uint64_t rumep:1; + uint64_t rvdm:1; + uint64_t acto:1; + uint64_t rte:1; + uint64_t mre:1; + uint64_t rdwdle:1; + uint64_t rtwdle:1; + uint64_t dpeoosd:1; + uint64_t fcpvwt:1; + uint64_t rpe:1; + uint64_t fcuv:1; + uint64_t rqo:1; + uint64_t rauc:1; + uint64_t racur:1; + uint64_t racca:1; + uint64_t caar:1; + uint64_t rarwdns:1; + uint64_t ramtlp:1; + uint64_t racpp:1; + uint64_t rawwpp:1; + uint64_t ecrc_e:1; + uint64_t reserved_31_63:33; +#endif } s; struct cvmx_pemx_dbg_info_en_s cn61xx; struct cvmx_pemx_dbg_info_en_s cn63xx; @@ -300,16 +464,25 @@ union cvmx_pemx_dbg_info_en { struct cvmx_pemx_dbg_info_en_s cn66xx; struct cvmx_pemx_dbg_info_en_s cn68xx; struct cvmx_pemx_dbg_info_en_s cn68xxp1; + struct cvmx_pemx_dbg_info_en_s cnf71xx; }; union cvmx_pemx_diag_status { uint64_t u64; struct cvmx_pemx_diag_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t pm_dst:1; uint64_t pm_stat:1; uint64_t pm_en:1; uint64_t aux_en:1; +#else + uint64_t aux_en:1; + uint64_t pm_en:1; + uint64_t pm_stat:1; + uint64_t pm_dst:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_pemx_diag_status_s cn61xx; struct cvmx_pemx_diag_status_s cn63xx; @@ -317,22 +490,30 @@ union cvmx_pemx_diag_status { struct cvmx_pemx_diag_status_s cn66xx; struct cvmx_pemx_diag_status_s cn68xx; struct cvmx_pemx_diag_status_s cn68xxp1; + struct cvmx_pemx_diag_status_s cnf71xx; }; union cvmx_pemx_inb_read_credits { uint64_t u64; struct cvmx_pemx_inb_read_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t num:6; +#else + uint64_t num:6; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_pemx_inb_read_credits_s cn61xx; struct cvmx_pemx_inb_read_credits_s cn66xx; struct cvmx_pemx_inb_read_credits_s cn68xx; + struct cvmx_pemx_inb_read_credits_s cnf71xx; }; union cvmx_pemx_int_enb { uint64_t u64; struct cvmx_pemx_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t crs_dr:1; uint64_t crs_er:1; @@ -348,6 +529,23 @@ union cvmx_pemx_int_enb { uint64_t pmei:1; uint64_t se:1; uint64_t aeri:1; +#else + uint64_t aeri:1; + uint64_t se:1; + uint64_t pmei:1; + uint64_t pmem:1; + uint64_t up_b1:1; + uint64_t up_b2:1; + uint64_t up_bx:1; + uint64_t un_b1:1; + uint64_t un_b2:1; + uint64_t un_bx:1; + uint64_t exc:1; + uint64_t rdlk:1; + uint64_t crs_er:1; + uint64_t crs_dr:1; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_pemx_int_enb_s cn61xx; struct cvmx_pemx_int_enb_s cn63xx; @@ -355,11 +553,13 @@ union cvmx_pemx_int_enb { struct cvmx_pemx_int_enb_s cn66xx; struct cvmx_pemx_int_enb_s cn68xx; struct cvmx_pemx_int_enb_s cn68xxp1; + struct cvmx_pemx_int_enb_s cnf71xx; }; union cvmx_pemx_int_enb_int { uint64_t u64; struct cvmx_pemx_int_enb_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t crs_dr:1; uint64_t crs_er:1; @@ -375,6 +575,23 @@ union cvmx_pemx_int_enb_int { uint64_t pmei:1; uint64_t se:1; uint64_t aeri:1; +#else + uint64_t aeri:1; + uint64_t se:1; + uint64_t pmei:1; + uint64_t pmem:1; + uint64_t up_b1:1; + uint64_t up_b2:1; + uint64_t up_bx:1; + uint64_t un_b1:1; + uint64_t un_b2:1; + uint64_t un_bx:1; + uint64_t exc:1; + uint64_t rdlk:1; + uint64_t crs_er:1; + uint64_t crs_dr:1; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_pemx_int_enb_int_s cn61xx; struct cvmx_pemx_int_enb_int_s cn63xx; @@ -382,11 +599,13 @@ union cvmx_pemx_int_enb_int { struct cvmx_pemx_int_enb_int_s cn66xx; struct cvmx_pemx_int_enb_int_s cn68xx; struct cvmx_pemx_int_enb_int_s cn68xxp1; + struct cvmx_pemx_int_enb_int_s cnf71xx; }; union cvmx_pemx_int_sum { uint64_t u64; struct cvmx_pemx_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t crs_dr:1; uint64_t crs_er:1; @@ -402,6 +621,23 @@ union cvmx_pemx_int_sum { uint64_t pmei:1; uint64_t se:1; uint64_t aeri:1; +#else + uint64_t aeri:1; + uint64_t se:1; + uint64_t pmei:1; + uint64_t pmem:1; + uint64_t up_b1:1; + uint64_t up_b2:1; + uint64_t up_bx:1; + uint64_t un_b1:1; + uint64_t un_b2:1; + uint64_t un_bx:1; + uint64_t exc:1; + uint64_t rdlk:1; + uint64_t crs_er:1; + uint64_t crs_dr:1; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_pemx_int_sum_s cn61xx; struct cvmx_pemx_int_sum_s cn63xx; @@ -409,13 +645,19 @@ union cvmx_pemx_int_sum { struct cvmx_pemx_int_sum_s cn66xx; struct cvmx_pemx_int_sum_s cn68xx; struct cvmx_pemx_int_sum_s cn68xxp1; + struct cvmx_pemx_int_sum_s cnf71xx; }; union cvmx_pemx_p2n_bar0_start { uint64_t u64; struct cvmx_pemx_p2n_bar0_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:50; uint64_t reserved_0_13:14; +#else + uint64_t reserved_0_13:14; + uint64_t addr:50; +#endif } s; struct cvmx_pemx_p2n_bar0_start_s cn61xx; struct cvmx_pemx_p2n_bar0_start_s cn63xx; @@ -423,13 +665,19 @@ union cvmx_pemx_p2n_bar0_start { struct cvmx_pemx_p2n_bar0_start_s cn66xx; struct cvmx_pemx_p2n_bar0_start_s cn68xx; struct cvmx_pemx_p2n_bar0_start_s cn68xxp1; + struct cvmx_pemx_p2n_bar0_start_s cnf71xx; }; union cvmx_pemx_p2n_bar1_start { uint64_t u64; struct cvmx_pemx_p2n_bar1_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:38; uint64_t reserved_0_25:26; +#else + uint64_t reserved_0_25:26; + uint64_t addr:38; +#endif } s; struct cvmx_pemx_p2n_bar1_start_s cn61xx; struct cvmx_pemx_p2n_bar1_start_s cn63xx; @@ -437,13 +685,19 @@ union cvmx_pemx_p2n_bar1_start { struct cvmx_pemx_p2n_bar1_start_s cn66xx; struct cvmx_pemx_p2n_bar1_start_s cn68xx; struct cvmx_pemx_p2n_bar1_start_s cn68xxp1; + struct cvmx_pemx_p2n_bar1_start_s cnf71xx; }; union cvmx_pemx_p2n_bar2_start { uint64_t u64; struct cvmx_pemx_p2n_bar2_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:23; uint64_t reserved_0_40:41; +#else + uint64_t reserved_0_40:41; + uint64_t addr:23; +#endif } s; struct cvmx_pemx_p2n_bar2_start_s cn61xx; struct cvmx_pemx_p2n_bar2_start_s cn63xx; @@ -451,13 +705,19 @@ union cvmx_pemx_p2n_bar2_start { struct cvmx_pemx_p2n_bar2_start_s cn66xx; struct cvmx_pemx_p2n_bar2_start_s cn68xx; struct cvmx_pemx_p2n_bar2_start_s cn68xxp1; + struct cvmx_pemx_p2n_bar2_start_s cnf71xx; }; union cvmx_pemx_p2p_barx_end { uint64_t u64; struct cvmx_pemx_p2p_barx_end_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:52; uint64_t reserved_0_11:12; +#else + uint64_t reserved_0_11:12; + uint64_t addr:52; +#endif } s; struct cvmx_pemx_p2p_barx_end_s cn63xx; struct cvmx_pemx_p2p_barx_end_s cn63xxp1; @@ -469,8 +729,13 @@ union cvmx_pemx_p2p_barx_end { union cvmx_pemx_p2p_barx_start { uint64_t u64; struct cvmx_pemx_p2p_barx_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:52; uint64_t reserved_0_11:12; +#else + uint64_t reserved_0_11:12; + uint64_t addr:52; +#endif } s; struct cvmx_pemx_p2p_barx_start_s cn63xx; struct cvmx_pemx_p2p_barx_start_s cn63xxp1; @@ -482,6 +747,7 @@ union cvmx_pemx_p2p_barx_start { union cvmx_pemx_tlp_credits { uint64_t u64; struct cvmx_pemx_tlp_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t peai_ppf:8; uint64_t pem_cpl:8; @@ -490,20 +756,40 @@ union cvmx_pemx_tlp_credits { uint64_t sli_cpl:8; uint64_t sli_np:8; uint64_t sli_p:8; +#else + uint64_t sli_p:8; + uint64_t sli_np:8; + uint64_t sli_cpl:8; + uint64_t pem_p:8; + uint64_t pem_np:8; + uint64_t pem_cpl:8; + uint64_t peai_ppf:8; + uint64_t reserved_56_63:8; +#endif } s; struct cvmx_pemx_tlp_credits_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t peai_ppf:8; uint64_t reserved_24_47:24; uint64_t sli_cpl:8; uint64_t sli_np:8; uint64_t sli_p:8; +#else + uint64_t sli_p:8; + uint64_t sli_np:8; + uint64_t sli_cpl:8; + uint64_t reserved_24_47:24; + uint64_t peai_ppf:8; + uint64_t reserved_56_63:8; +#endif } cn61xx; struct cvmx_pemx_tlp_credits_s cn63xx; struct cvmx_pemx_tlp_credits_s cn63xxp1; struct cvmx_pemx_tlp_credits_s cn66xx; struct cvmx_pemx_tlp_credits_s cn68xx; struct cvmx_pemx_tlp_credits_s cn68xxp1; + struct cvmx_pemx_tlp_credits_cn61xx cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h index aef84851a94..59b3dc56544 100644 --- a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -48,6 +48,7 @@ union cvmx_pescx_bist_status { uint64_t u64; struct cvmx_pescx_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t rqdata5:1; uint64_t ctlp_or:1; @@ -62,9 +63,26 @@ union cvmx_pescx_bist_status { uint64_t rqhdr1:1; uint64_t rqhdr0:1; uint64_t sot:1; +#else + uint64_t sot:1; + uint64_t rqhdr0:1; + uint64_t rqhdr1:1; + uint64_t rqdata4:1; + uint64_t rqdata3:1; + uint64_t rqdata2:1; + uint64_t rqdata1:1; + uint64_t rqdata0:1; + uint64_t retry:1; + uint64_t ptlp_or:1; + uint64_t ntlp_or:1; + uint64_t ctlp_or:1; + uint64_t rqdata5:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_pescx_bist_status_s cn52xx; struct cvmx_pescx_bist_status_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t ctlp_or:1; uint64_t ntlp_or:1; @@ -78,6 +96,21 @@ union cvmx_pescx_bist_status { uint64_t rqhdr1:1; uint64_t rqhdr0:1; uint64_t sot:1; +#else + uint64_t sot:1; + uint64_t rqhdr0:1; + uint64_t rqhdr1:1; + uint64_t rqdata4:1; + uint64_t rqdata3:1; + uint64_t rqdata2:1; + uint64_t rqdata1:1; + uint64_t rqdata0:1; + uint64_t retry:1; + uint64_t ptlp_or:1; + uint64_t ntlp_or:1; + uint64_t ctlp_or:1; + uint64_t reserved_12_63:52; +#endif } cn52xxp1; struct cvmx_pescx_bist_status_s cn56xx; struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1; @@ -86,6 +119,7 @@ union cvmx_pescx_bist_status { union cvmx_pescx_bist_status2 { uint64_t u64; struct cvmx_pescx_bist_status2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t cto_p2e:1; uint64_t e2p_cpl:1; @@ -101,6 +135,23 @@ union cvmx_pescx_bist_status2 { uint64_t pef_tcf1:1; uint64_t pef_tc0:1; uint64_t ppf:1; +#else + uint64_t ppf:1; + uint64_t pef_tc0:1; + uint64_t pef_tcf1:1; + uint64_t pef_tnf:1; + uint64_t pef_tpf0:1; + uint64_t pef_tpf1:1; + uint64_t rsl_p2e:1; + uint64_t peai_p2e:1; + uint64_t dbg_p2e:1; + uint64_t e2p_rsl:1; + uint64_t e2p_p:1; + uint64_t e2p_n:1; + uint64_t e2p_cpl:1; + uint64_t cto_p2e:1; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_pescx_bist_status2_s cn52xx; struct cvmx_pescx_bist_status2_s cn52xxp1; @@ -111,8 +162,13 @@ union cvmx_pescx_bist_status2 { union cvmx_pescx_cfg_rd { uint64_t u64; struct cvmx_pescx_cfg_rd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:32; uint64_t addr:32; +#else + uint64_t addr:32; + uint64_t data:32; +#endif } s; struct cvmx_pescx_cfg_rd_s cn52xx; struct cvmx_pescx_cfg_rd_s cn52xxp1; @@ -123,8 +179,13 @@ union cvmx_pescx_cfg_rd { union cvmx_pescx_cfg_wr { uint64_t u64; struct cvmx_pescx_cfg_wr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:32; uint64_t addr:32; +#else + uint64_t addr:32; + uint64_t data:32; +#endif } s; struct cvmx_pescx_cfg_wr_s cn52xx; struct cvmx_pescx_cfg_wr_s cn52xxp1; @@ -135,8 +196,13 @@ union cvmx_pescx_cfg_wr { union cvmx_pescx_cpl_lut_valid { uint64_t u64; struct cvmx_pescx_cpl_lut_valid_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t tag:32; +#else + uint64_t tag:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pescx_cpl_lut_valid_s cn52xx; struct cvmx_pescx_cpl_lut_valid_s cn52xxp1; @@ -147,6 +213,7 @@ union cvmx_pescx_cpl_lut_valid { union cvmx_pescx_ctl_status { uint64_t u64; struct cvmx_pescx_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t dnum:5; uint64_t pbus:8; @@ -163,10 +230,29 @@ union cvmx_pescx_ctl_status { uint64_t reserved_2_2:1; uint64_t inv_ecrc:1; uint64_t inv_lcrc:1; +#else + uint64_t inv_lcrc:1; + uint64_t inv_ecrc:1; + uint64_t reserved_2_2:1; + uint64_t ro_ctlp:1; + uint64_t lnk_enb:1; + uint64_t dly_one:1; + uint64_t nf_ecrc:1; + uint64_t reserved_7_8:2; + uint64_t ob_p_cmd:1; + uint64_t pm_xpme:1; + uint64_t pm_xtoff:1; + uint64_t lane_swp:1; + uint64_t qlm_cfg:2; + uint64_t pbus:8; + uint64_t dnum:5; + uint64_t reserved_28_63:36; +#endif } s; struct cvmx_pescx_ctl_status_s cn52xx; struct cvmx_pescx_ctl_status_s cn52xxp1; struct cvmx_pescx_ctl_status_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t dnum:5; uint64_t pbus:8; @@ -183,6 +269,24 @@ union cvmx_pescx_ctl_status { uint64_t reserved_2_2:1; uint64_t inv_ecrc:1; uint64_t inv_lcrc:1; +#else + uint64_t inv_lcrc:1; + uint64_t inv_ecrc:1; + uint64_t reserved_2_2:1; + uint64_t ro_ctlp:1; + uint64_t lnk_enb:1; + uint64_t dly_one:1; + uint64_t nf_ecrc:1; + uint64_t reserved_7_8:2; + uint64_t ob_p_cmd:1; + uint64_t pm_xpme:1; + uint64_t pm_xtoff:1; + uint64_t reserved_12_12:1; + uint64_t qlm_cfg:2; + uint64_t pbus:8; + uint64_t dnum:5; + uint64_t reserved_28_63:36; +#endif } cn56xx; struct cvmx_pescx_ctl_status_cn56xx cn56xxp1; }; @@ -190,14 +294,25 @@ union cvmx_pescx_ctl_status { union cvmx_pescx_ctl_status2 { uint64_t u64; struct cvmx_pescx_ctl_status2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t pclk_run:1; uint64_t pcierst:1; +#else + uint64_t pcierst:1; + uint64_t pclk_run:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_pescx_ctl_status2_s cn52xx; struct cvmx_pescx_ctl_status2_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t pcierst:1; +#else + uint64_t pcierst:1; + uint64_t reserved_1_63:63; +#endif } cn52xxp1; struct cvmx_pescx_ctl_status2_s cn56xx; struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1; @@ -206,6 +321,7 @@ union cvmx_pescx_ctl_status2 { union cvmx_pescx_dbg_info { uint64_t u64; struct cvmx_pescx_dbg_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t ecrc_e:1; uint64_t rawwpp:1; @@ -238,6 +354,40 @@ union cvmx_pescx_dbg_info { uint64_t rtlplle:1; uint64_t rtlpmal:1; uint64_t spoison:1; +#else + uint64_t spoison:1; + uint64_t rtlpmal:1; + uint64_t rtlplle:1; + uint64_t recrce:1; + uint64_t rpoison:1; + uint64_t rcemrc:1; + uint64_t rnfemrc:1; + uint64_t rfemrc:1; + uint64_t rpmerc:1; + uint64_t rptamrc:1; + uint64_t rumep:1; + uint64_t rvdm:1; + uint64_t acto:1; + uint64_t rte:1; + uint64_t mre:1; + uint64_t rdwdle:1; + uint64_t rtwdle:1; + uint64_t dpeoosd:1; + uint64_t fcpvwt:1; + uint64_t rpe:1; + uint64_t fcuv:1; + uint64_t rqo:1; + uint64_t rauc:1; + uint64_t racur:1; + uint64_t racca:1; + uint64_t caar:1; + uint64_t rarwdns:1; + uint64_t ramtlp:1; + uint64_t racpp:1; + uint64_t rawwpp:1; + uint64_t ecrc_e:1; + uint64_t reserved_31_63:33; +#endif } s; struct cvmx_pescx_dbg_info_s cn52xx; struct cvmx_pescx_dbg_info_s cn52xxp1; @@ -248,6 +398,7 @@ union cvmx_pescx_dbg_info { union cvmx_pescx_dbg_info_en { uint64_t u64; struct cvmx_pescx_dbg_info_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t ecrc_e:1; uint64_t rawwpp:1; @@ -280,6 +431,40 @@ union cvmx_pescx_dbg_info_en { uint64_t rtlplle:1; uint64_t rtlpmal:1; uint64_t spoison:1; +#else + uint64_t spoison:1; + uint64_t rtlpmal:1; + uint64_t rtlplle:1; + uint64_t recrce:1; + uint64_t rpoison:1; + uint64_t rcemrc:1; + uint64_t rnfemrc:1; + uint64_t rfemrc:1; + uint64_t rpmerc:1; + uint64_t rptamrc:1; + uint64_t rumep:1; + uint64_t rvdm:1; + uint64_t acto:1; + uint64_t rte:1; + uint64_t mre:1; + uint64_t rdwdle:1; + uint64_t rtwdle:1; + uint64_t dpeoosd:1; + uint64_t fcpvwt:1; + uint64_t rpe:1; + uint64_t fcuv:1; + uint64_t rqo:1; + uint64_t rauc:1; + uint64_t racur:1; + uint64_t racca:1; + uint64_t caar:1; + uint64_t rarwdns:1; + uint64_t ramtlp:1; + uint64_t racpp:1; + uint64_t rawwpp:1; + uint64_t ecrc_e:1; + uint64_t reserved_31_63:33; +#endif } s; struct cvmx_pescx_dbg_info_en_s cn52xx; struct cvmx_pescx_dbg_info_en_s cn52xxp1; @@ -290,11 +475,19 @@ union cvmx_pescx_dbg_info_en { union cvmx_pescx_diag_status { uint64_t u64; struct cvmx_pescx_diag_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t pm_dst:1; uint64_t pm_stat:1; uint64_t pm_en:1; uint64_t aux_en:1; +#else + uint64_t aux_en:1; + uint64_t pm_en:1; + uint64_t pm_stat:1; + uint64_t pm_dst:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_pescx_diag_status_s cn52xx; struct cvmx_pescx_diag_status_s cn52xxp1; @@ -305,8 +498,13 @@ union cvmx_pescx_diag_status { union cvmx_pescx_p2n_bar0_start { uint64_t u64; struct cvmx_pescx_p2n_bar0_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:50; uint64_t reserved_0_13:14; +#else + uint64_t reserved_0_13:14; + uint64_t addr:50; +#endif } s; struct cvmx_pescx_p2n_bar0_start_s cn52xx; struct cvmx_pescx_p2n_bar0_start_s cn52xxp1; @@ -317,8 +515,13 @@ union cvmx_pescx_p2n_bar0_start { union cvmx_pescx_p2n_bar1_start { uint64_t u64; struct cvmx_pescx_p2n_bar1_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:38; uint64_t reserved_0_25:26; +#else + uint64_t reserved_0_25:26; + uint64_t addr:38; +#endif } s; struct cvmx_pescx_p2n_bar1_start_s cn52xx; struct cvmx_pescx_p2n_bar1_start_s cn52xxp1; @@ -329,8 +532,13 @@ union cvmx_pescx_p2n_bar1_start { union cvmx_pescx_p2n_bar2_start { uint64_t u64; struct cvmx_pescx_p2n_bar2_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:25; uint64_t reserved_0_38:39; +#else + uint64_t reserved_0_38:39; + uint64_t addr:25; +#endif } s; struct cvmx_pescx_p2n_bar2_start_s cn52xx; struct cvmx_pescx_p2n_bar2_start_s cn52xxp1; @@ -341,8 +549,13 @@ union cvmx_pescx_p2n_bar2_start { union cvmx_pescx_p2p_barx_end { uint64_t u64; struct cvmx_pescx_p2p_barx_end_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:52; uint64_t reserved_0_11:12; +#else + uint64_t reserved_0_11:12; + uint64_t addr:52; +#endif } s; struct cvmx_pescx_p2p_barx_end_s cn52xx; struct cvmx_pescx_p2p_barx_end_s cn52xxp1; @@ -353,8 +566,13 @@ union cvmx_pescx_p2p_barx_end { union cvmx_pescx_p2p_barx_start { uint64_t u64; struct cvmx_pescx_p2p_barx_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:52; uint64_t reserved_0_11:12; +#else + uint64_t reserved_0_11:12; + uint64_t addr:52; +#endif } s; struct cvmx_pescx_p2p_barx_start_s cn52xx; struct cvmx_pescx_p2p_barx_start_s cn52xxp1; @@ -365,9 +583,14 @@ union cvmx_pescx_p2p_barx_start { union cvmx_pescx_tlp_credits { uint64_t u64; struct cvmx_pescx_tlp_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pescx_tlp_credits_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t peai_ppf:8; uint64_t pesc_cpl:8; @@ -376,8 +599,19 @@ union cvmx_pescx_tlp_credits { uint64_t npei_cpl:8; uint64_t npei_np:8; uint64_t npei_p:8; +#else + uint64_t npei_p:8; + uint64_t npei_np:8; + uint64_t npei_cpl:8; + uint64_t pesc_p:8; + uint64_t pesc_np:8; + uint64_t pesc_cpl:8; + uint64_t peai_ppf:8; + uint64_t reserved_56_63:8; +#endif } cn52xx; struct cvmx_pescx_tlp_credits_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_38_63:26; uint64_t peai_ppf:8; uint64_t pesc_cpl:5; @@ -386,6 +620,16 @@ union cvmx_pescx_tlp_credits { uint64_t npei_cpl:5; uint64_t npei_np:5; uint64_t npei_p:5; +#else + uint64_t npei_p:5; + uint64_t npei_np:5; + uint64_t npei_cpl:5; + uint64_t pesc_p:5; + uint64_t pesc_np:5; + uint64_t pesc_cpl:5; + uint64_t peai_ppf:8; + uint64_t reserved_38_63:26; +#endif } cn52xxp1; struct cvmx_pescx_tlp_credits_cn52xx cn56xx; struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1; diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h index 4438d211988..eb673f3514d 100644 --- a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2011 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as diff --git a/arch/mips/include/asm/octeon/cvmx-pip-defs.h b/arch/mips/include/asm/octeon/cvmx-pip-defs.h index 5a369100ca6..e975c7d2e48 100644 --- a/arch/mips/include/asm/octeon/cvmx-pip-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pip-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -44,100 +44,144 @@ enum cvmx_pip_port_parse_mode { */ CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull, /* - * Input packets are assumed to be IP. Results from non IP + * Input packets are assumed to be IP. Results from non IP * packets is undefined. Pointers reference the beginning of * the IP header. */ CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull }; -#define CVMX_PIP_BCK_PRS \ - CVMX_ADD_IO_SEG(0x00011800A0000038ull) -#define CVMX_PIP_BIST_STATUS \ - CVMX_ADD_IO_SEG(0x00011800A0000000ull) -#define CVMX_PIP_CRC_CTLX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000040ull + (((offset) & 1) * 8)) -#define CVMX_PIP_CRC_IVX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000050ull + (((offset) & 1) * 8)) -#define CVMX_PIP_DEC_IPSECX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000080ull + (((offset) & 3) * 8)) -#define CVMX_PIP_DSA_SRC_GRP \ - CVMX_ADD_IO_SEG(0x00011800A0000190ull) -#define CVMX_PIP_DSA_VID_GRP \ - CVMX_ADD_IO_SEG(0x00011800A0000198ull) -#define CVMX_PIP_FRM_LEN_CHKX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000180ull + (((offset) & 1) * 8)) -#define CVMX_PIP_GBL_CFG \ - CVMX_ADD_IO_SEG(0x00011800A0000028ull) -#define CVMX_PIP_GBL_CTL \ - CVMX_ADD_IO_SEG(0x00011800A0000020ull) -#define CVMX_PIP_HG_PRI_QOS \ - CVMX_ADD_IO_SEG(0x00011800A00001A0ull) -#define CVMX_PIP_INT_EN \ - CVMX_ADD_IO_SEG(0x00011800A0000010ull) -#define CVMX_PIP_INT_REG \ - CVMX_ADD_IO_SEG(0x00011800A0000008ull) -#define CVMX_PIP_IP_OFFSET \ - CVMX_ADD_IO_SEG(0x00011800A0000060ull) -#define CVMX_PIP_PRT_CFGX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000200ull + (((offset) & 63) * 8)) -#define CVMX_PIP_PRT_TAGX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000400ull + (((offset) & 63) * 8)) -#define CVMX_PIP_QOS_DIFFX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000600ull + (((offset) & 63) * 8)) -#define CVMX_PIP_QOS_VLANX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A00000C0ull + (((offset) & 7) * 8)) -#define CVMX_PIP_QOS_WATCHX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000100ull + (((offset) & 7) * 8)) -#define CVMX_PIP_RAW_WORD \ - CVMX_ADD_IO_SEG(0x00011800A00000B0ull) -#define CVMX_PIP_SFT_RST \ - CVMX_ADD_IO_SEG(0x00011800A0000030ull) -#define CVMX_PIP_STAT0_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000800ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT1_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000808ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT2_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000810ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT3_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000818ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT4_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000820ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT5_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000828ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT6_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000830ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT7_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000838ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT8_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000840ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT9_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000848ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT_CTL \ - CVMX_ADD_IO_SEG(0x00011800A0000018ull) -#define CVMX_PIP_STAT_INB_ERRSX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0001A10ull + (((offset) & 63) * 32)) -#define CVMX_PIP_STAT_INB_OCTSX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0001A08ull + (((offset) & 63) * 32)) -#define CVMX_PIP_STAT_INB_PKTSX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0001A00ull + (((offset) & 63) * 32)) -#define CVMX_PIP_TAG_INCX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0001800ull + (((offset) & 63) * 8)) -#define CVMX_PIP_TAG_MASK \ - CVMX_ADD_IO_SEG(0x00011800A0000070ull) -#define CVMX_PIP_TAG_SECRET \ - CVMX_ADD_IO_SEG(0x00011800A0000068ull) -#define CVMX_PIP_TODO_ENTRY \ - CVMX_ADD_IO_SEG(0x00011800A0000078ull) +#define CVMX_PIP_ALT_SKIP_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8) +#define CVMX_PIP_BCK_PRS (CVMX_ADD_IO_SEG(0x00011800A0000038ull)) +#define CVMX_PIP_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A0000000ull)) +#define CVMX_PIP_BSEL_EXT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16) +#define CVMX_PIP_BSEL_EXT_POSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16) +#define CVMX_PIP_BSEL_TBL_ENTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8) +#define CVMX_PIP_CLKEN (CVMX_ADD_IO_SEG(0x00011800A0000040ull)) +#define CVMX_PIP_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8) +#define CVMX_PIP_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8) +#define CVMX_PIP_DEC_IPSECX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8) +#define CVMX_PIP_DSA_SRC_GRP (CVMX_ADD_IO_SEG(0x00011800A0000190ull)) +#define CVMX_PIP_DSA_VID_GRP (CVMX_ADD_IO_SEG(0x00011800A0000198ull)) +#define CVMX_PIP_FRM_LEN_CHKX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8) +#define CVMX_PIP_GBL_CFG (CVMX_ADD_IO_SEG(0x00011800A0000028ull)) +#define CVMX_PIP_GBL_CTL (CVMX_ADD_IO_SEG(0x00011800A0000020ull)) +#define CVMX_PIP_HG_PRI_QOS (CVMX_ADD_IO_SEG(0x00011800A00001A0ull)) +#define CVMX_PIP_INT_EN (CVMX_ADD_IO_SEG(0x00011800A0000010ull)) +#define CVMX_PIP_INT_REG (CVMX_ADD_IO_SEG(0x00011800A0000008ull)) +#define CVMX_PIP_IP_OFFSET (CVMX_ADD_IO_SEG(0x00011800A0000060ull)) +#define CVMX_PIP_PRI_TBLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8) +#define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8) +#define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8) +#define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8) +#define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8) +#define CVMX_PIP_QOS_VLANX(offset) (CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8) +#define CVMX_PIP_QOS_WATCHX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8) +#define CVMX_PIP_RAW_WORD (CVMX_ADD_IO_SEG(0x00011800A00000B0ull)) +#define CVMX_PIP_SFT_RST (CVMX_ADD_IO_SEG(0x00011800A0000030ull)) +#define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16) +#define CVMX_PIP_STAT10_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16) +#define CVMX_PIP_STAT11_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT1_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT2_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT3_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT4_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT5_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT6_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT7_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT8_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT9_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT_CTL (CVMX_ADD_IO_SEG(0x00011800A0000018ull)) +#define CVMX_PIP_STAT_INB_ERRSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32) +#define CVMX_PIP_STAT_INB_ERRS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32) +#define CVMX_PIP_STAT_INB_OCTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32) +#define CVMX_PIP_STAT_INB_OCTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32) +#define CVMX_PIP_STAT_INB_PKTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32) +#define CVMX_PIP_STAT_INB_PKTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32) +#define CVMX_PIP_SUB_PKIND_FCSX(block_id) (CVMX_ADD_IO_SEG(0x00011800A0080000ull)) +#define CVMX_PIP_TAG_INCX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8) +#define CVMX_PIP_TAG_MASK (CVMX_ADD_IO_SEG(0x00011800A0000070ull)) +#define CVMX_PIP_TAG_SECRET (CVMX_ADD_IO_SEG(0x00011800A0000068ull)) +#define CVMX_PIP_TODO_ENTRY (CVMX_ADD_IO_SEG(0x00011800A0000078ull)) +#define CVMX_PIP_VLAN_ETYPESX(offset) (CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8) +#define CVMX_PIP_XSTAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40) +#define CVMX_PIP_XSTAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40) +#define CVMX_PIP_XSTAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40) +#define CVMX_PIP_XSTAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40) + +union cvmx_pip_alt_skip_cfgx { + uint64_t u64; + struct cvmx_pip_alt_skip_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_57_63:7; + uint64_t len:1; + uint64_t reserved_46_55:10; + uint64_t bit1:6; + uint64_t reserved_38_39:2; + uint64_t bit0:6; + uint64_t reserved_23_31:9; + uint64_t skip3:7; + uint64_t reserved_15_15:1; + uint64_t skip2:7; + uint64_t reserved_7_7:1; + uint64_t skip1:7; +#else + uint64_t skip1:7; + uint64_t reserved_7_7:1; + uint64_t skip2:7; + uint64_t reserved_15_15:1; + uint64_t skip3:7; + uint64_t reserved_23_31:9; + uint64_t bit0:6; + uint64_t reserved_38_39:2; + uint64_t bit1:6; + uint64_t reserved_46_55:10; + uint64_t len:1; + uint64_t reserved_57_63:7; +#endif + } s; + struct cvmx_pip_alt_skip_cfgx_s cn61xx; + struct cvmx_pip_alt_skip_cfgx_s cn66xx; + struct cvmx_pip_alt_skip_cfgx_s cn68xx; + struct cvmx_pip_alt_skip_cfgx_s cnf71xx; +}; union cvmx_pip_bck_prs { uint64_t u64; struct cvmx_pip_bck_prs_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bckprs:1; uint64_t reserved_13_62:50; uint64_t hiwater:5; uint64_t reserved_5_7:3; uint64_t lowater:5; +#else + uint64_t lowater:5; + uint64_t reserved_5_7:3; + uint64_t hiwater:5; + uint64_t reserved_13_62:50; + uint64_t bckprs:1; +#endif } s; struct cvmx_pip_bck_prs_s cn38xx; struct cvmx_pip_bck_prs_s cn38xxp2; @@ -145,36 +189,236 @@ union cvmx_pip_bck_prs { struct cvmx_pip_bck_prs_s cn56xxp1; struct cvmx_pip_bck_prs_s cn58xx; struct cvmx_pip_bck_prs_s cn58xxp1; + struct cvmx_pip_bck_prs_s cn61xx; + struct cvmx_pip_bck_prs_s cn63xx; + struct cvmx_pip_bck_prs_s cn63xxp1; + struct cvmx_pip_bck_prs_s cn66xx; + struct cvmx_pip_bck_prs_s cn68xx; + struct cvmx_pip_bck_prs_s cn68xxp1; + struct cvmx_pip_bck_prs_s cnf71xx; }; union cvmx_pip_bist_status { uint64_t u64; struct cvmx_pip_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_22_63:42; + uint64_t bist:22; +#else + uint64_t bist:22; + uint64_t reserved_22_63:42; +#endif + } s; + struct cvmx_pip_bist_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t bist:18; - } s; - struct cvmx_pip_bist_status_s cn30xx; - struct cvmx_pip_bist_status_s cn31xx; - struct cvmx_pip_bist_status_s cn38xx; - struct cvmx_pip_bist_status_s cn38xxp2; +#else + uint64_t bist:18; + uint64_t reserved_18_63:46; +#endif + } cn30xx; + struct cvmx_pip_bist_status_cn30xx cn31xx; + struct cvmx_pip_bist_status_cn30xx cn38xx; + struct cvmx_pip_bist_status_cn30xx cn38xxp2; struct cvmx_pip_bist_status_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t bist:17; +#else + uint64_t bist:17; + uint64_t reserved_17_63:47; +#endif } cn50xx; - struct cvmx_pip_bist_status_s cn52xx; - struct cvmx_pip_bist_status_s cn52xxp1; - struct cvmx_pip_bist_status_s cn56xx; - struct cvmx_pip_bist_status_s cn56xxp1; - struct cvmx_pip_bist_status_s cn58xx; - struct cvmx_pip_bist_status_s cn58xxp1; + struct cvmx_pip_bist_status_cn30xx cn52xx; + struct cvmx_pip_bist_status_cn30xx cn52xxp1; + struct cvmx_pip_bist_status_cn30xx cn56xx; + struct cvmx_pip_bist_status_cn30xx cn56xxp1; + struct cvmx_pip_bist_status_cn30xx cn58xx; + struct cvmx_pip_bist_status_cn30xx cn58xxp1; + struct cvmx_pip_bist_status_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t bist:20; +#else + uint64_t bist:20; + uint64_t reserved_20_63:44; +#endif + } cn61xx; + struct cvmx_pip_bist_status_cn30xx cn63xx; + struct cvmx_pip_bist_status_cn30xx cn63xxp1; + struct cvmx_pip_bist_status_cn61xx cn66xx; + struct cvmx_pip_bist_status_s cn68xx; + struct cvmx_pip_bist_status_cn61xx cn68xxp1; + struct cvmx_pip_bist_status_cn61xx cnf71xx; +}; + +union cvmx_pip_bsel_ext_cfgx { + uint64_t u64; + struct cvmx_pip_bsel_ext_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t upper_tag:16; + uint64_t tag:8; + uint64_t reserved_25_31:7; + uint64_t offset:9; + uint64_t reserved_7_15:9; + uint64_t skip:7; +#else + uint64_t skip:7; + uint64_t reserved_7_15:9; + uint64_t offset:9; + uint64_t reserved_25_31:7; + uint64_t tag:8; + uint64_t upper_tag:16; + uint64_t reserved_56_63:8; +#endif + } s; + struct cvmx_pip_bsel_ext_cfgx_s cn61xx; + struct cvmx_pip_bsel_ext_cfgx_s cn68xx; + struct cvmx_pip_bsel_ext_cfgx_s cnf71xx; +}; + +union cvmx_pip_bsel_ext_posx { + uint64_t u64; + struct cvmx_pip_bsel_ext_posx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t pos7_val:1; + uint64_t pos7:7; + uint64_t pos6_val:1; + uint64_t pos6:7; + uint64_t pos5_val:1; + uint64_t pos5:7; + uint64_t pos4_val:1; + uint64_t pos4:7; + uint64_t pos3_val:1; + uint64_t pos3:7; + uint64_t pos2_val:1; + uint64_t pos2:7; + uint64_t pos1_val:1; + uint64_t pos1:7; + uint64_t pos0_val:1; + uint64_t pos0:7; +#else + uint64_t pos0:7; + uint64_t pos0_val:1; + uint64_t pos1:7; + uint64_t pos1_val:1; + uint64_t pos2:7; + uint64_t pos2_val:1; + uint64_t pos3:7; + uint64_t pos3_val:1; + uint64_t pos4:7; + uint64_t pos4_val:1; + uint64_t pos5:7; + uint64_t pos5_val:1; + uint64_t pos6:7; + uint64_t pos6_val:1; + uint64_t pos7:7; + uint64_t pos7_val:1; +#endif + } s; + struct cvmx_pip_bsel_ext_posx_s cn61xx; + struct cvmx_pip_bsel_ext_posx_s cn68xx; + struct cvmx_pip_bsel_ext_posx_s cnf71xx; +}; + +union cvmx_pip_bsel_tbl_entx { + uint64_t u64; + struct cvmx_pip_bsel_tbl_entx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t tag_en:1; + uint64_t grp_en:1; + uint64_t tt_en:1; + uint64_t qos_en:1; + uint64_t reserved_40_59:20; + uint64_t tag:8; + uint64_t reserved_22_31:10; + uint64_t grp:6; + uint64_t reserved_10_15:6; + uint64_t tt:2; + uint64_t reserved_3_7:5; + uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t reserved_3_7:5; + uint64_t tt:2; + uint64_t reserved_10_15:6; + uint64_t grp:6; + uint64_t reserved_22_31:10; + uint64_t tag:8; + uint64_t reserved_40_59:20; + uint64_t qos_en:1; + uint64_t tt_en:1; + uint64_t grp_en:1; + uint64_t tag_en:1; +#endif + } s; + struct cvmx_pip_bsel_tbl_entx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t tag_en:1; + uint64_t grp_en:1; + uint64_t tt_en:1; + uint64_t qos_en:1; + uint64_t reserved_40_59:20; + uint64_t tag:8; + uint64_t reserved_20_31:12; + uint64_t grp:4; + uint64_t reserved_10_15:6; + uint64_t tt:2; + uint64_t reserved_3_7:5; + uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t reserved_3_7:5; + uint64_t tt:2; + uint64_t reserved_10_15:6; + uint64_t grp:4; + uint64_t reserved_20_31:12; + uint64_t tag:8; + uint64_t reserved_40_59:20; + uint64_t qos_en:1; + uint64_t tt_en:1; + uint64_t grp_en:1; + uint64_t tag_en:1; +#endif + } cn61xx; + struct cvmx_pip_bsel_tbl_entx_s cn68xx; + struct cvmx_pip_bsel_tbl_entx_cn61xx cnf71xx; +}; + +union cvmx_pip_clken { + uint64_t u64; + struct cvmx_pip_clken_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t clken:1; +#else + uint64_t clken:1; + uint64_t reserved_1_63:63; +#endif + } s; + struct cvmx_pip_clken_s cn61xx; + struct cvmx_pip_clken_s cn63xx; + struct cvmx_pip_clken_s cn63xxp1; + struct cvmx_pip_clken_s cn66xx; + struct cvmx_pip_clken_s cn68xx; + struct cvmx_pip_clken_s cn68xxp1; + struct cvmx_pip_clken_s cnf71xx; }; union cvmx_pip_crc_ctlx { uint64_t u64; struct cvmx_pip_crc_ctlx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t invres:1; uint64_t reflect:1; +#else + uint64_t reflect:1; + uint64_t invres:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_pip_crc_ctlx_s cn38xx; struct cvmx_pip_crc_ctlx_s cn38xxp2; @@ -185,8 +429,13 @@ union cvmx_pip_crc_ctlx { union cvmx_pip_crc_ivx { uint64_t u64; struct cvmx_pip_crc_ivx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iv:32; +#else + uint64_t iv:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pip_crc_ivx_s cn38xx; struct cvmx_pip_crc_ivx_s cn38xxp2; @@ -197,10 +446,17 @@ union cvmx_pip_crc_ivx { union cvmx_pip_dec_ipsecx { uint64_t u64; struct cvmx_pip_dec_ipsecx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t tcp:1; uint64_t udp:1; uint64_t dprt:16; +#else + uint64_t dprt:16; + uint64_t udp:1; + uint64_t tcp:1; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_pip_dec_ipsecx_s cn30xx; struct cvmx_pip_dec_ipsecx_s cn31xx; @@ -213,11 +469,19 @@ union cvmx_pip_dec_ipsecx { struct cvmx_pip_dec_ipsecx_s cn56xxp1; struct cvmx_pip_dec_ipsecx_s cn58xx; struct cvmx_pip_dec_ipsecx_s cn58xxp1; + struct cvmx_pip_dec_ipsecx_s cn61xx; + struct cvmx_pip_dec_ipsecx_s cn63xx; + struct cvmx_pip_dec_ipsecx_s cn63xxp1; + struct cvmx_pip_dec_ipsecx_s cn66xx; + struct cvmx_pip_dec_ipsecx_s cn68xx; + struct cvmx_pip_dec_ipsecx_s cn68xxp1; + struct cvmx_pip_dec_ipsecx_s cnf71xx; }; union cvmx_pip_dsa_src_grp { uint64_t u64; struct cvmx_pip_dsa_src_grp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t map15:4; uint64_t map14:4; uint64_t map13:4; @@ -234,15 +498,41 @@ union cvmx_pip_dsa_src_grp { uint64_t map2:4; uint64_t map1:4; uint64_t map0:4; +#else + uint64_t map0:4; + uint64_t map1:4; + uint64_t map2:4; + uint64_t map3:4; + uint64_t map4:4; + uint64_t map5:4; + uint64_t map6:4; + uint64_t map7:4; + uint64_t map8:4; + uint64_t map9:4; + uint64_t map10:4; + uint64_t map11:4; + uint64_t map12:4; + uint64_t map13:4; + uint64_t map14:4; + uint64_t map15:4; +#endif } s; struct cvmx_pip_dsa_src_grp_s cn52xx; struct cvmx_pip_dsa_src_grp_s cn52xxp1; struct cvmx_pip_dsa_src_grp_s cn56xx; + struct cvmx_pip_dsa_src_grp_s cn61xx; + struct cvmx_pip_dsa_src_grp_s cn63xx; + struct cvmx_pip_dsa_src_grp_s cn63xxp1; + struct cvmx_pip_dsa_src_grp_s cn66xx; + struct cvmx_pip_dsa_src_grp_s cn68xx; + struct cvmx_pip_dsa_src_grp_s cn68xxp1; + struct cvmx_pip_dsa_src_grp_s cnf71xx; }; union cvmx_pip_dsa_vid_grp { uint64_t u64; struct cvmx_pip_dsa_vid_grp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t map15:4; uint64_t map14:4; uint64_t map13:4; @@ -259,29 +549,68 @@ union cvmx_pip_dsa_vid_grp { uint64_t map2:4; uint64_t map1:4; uint64_t map0:4; +#else + uint64_t map0:4; + uint64_t map1:4; + uint64_t map2:4; + uint64_t map3:4; + uint64_t map4:4; + uint64_t map5:4; + uint64_t map6:4; + uint64_t map7:4; + uint64_t map8:4; + uint64_t map9:4; + uint64_t map10:4; + uint64_t map11:4; + uint64_t map12:4; + uint64_t map13:4; + uint64_t map14:4; + uint64_t map15:4; +#endif } s; struct cvmx_pip_dsa_vid_grp_s cn52xx; struct cvmx_pip_dsa_vid_grp_s cn52xxp1; struct cvmx_pip_dsa_vid_grp_s cn56xx; + struct cvmx_pip_dsa_vid_grp_s cn61xx; + struct cvmx_pip_dsa_vid_grp_s cn63xx; + struct cvmx_pip_dsa_vid_grp_s cn63xxp1; + struct cvmx_pip_dsa_vid_grp_s cn66xx; + struct cvmx_pip_dsa_vid_grp_s cn68xx; + struct cvmx_pip_dsa_vid_grp_s cn68xxp1; + struct cvmx_pip_dsa_vid_grp_s cnf71xx; }; union cvmx_pip_frm_len_chkx { uint64_t u64; struct cvmx_pip_frm_len_chkx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t maxlen:16; uint64_t minlen:16; +#else + uint64_t minlen:16; + uint64_t maxlen:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pip_frm_len_chkx_s cn50xx; struct cvmx_pip_frm_len_chkx_s cn52xx; struct cvmx_pip_frm_len_chkx_s cn52xxp1; struct cvmx_pip_frm_len_chkx_s cn56xx; struct cvmx_pip_frm_len_chkx_s cn56xxp1; + struct cvmx_pip_frm_len_chkx_s cn61xx; + struct cvmx_pip_frm_len_chkx_s cn63xx; + struct cvmx_pip_frm_len_chkx_s cn63xxp1; + struct cvmx_pip_frm_len_chkx_s cn66xx; + struct cvmx_pip_frm_len_chkx_s cn68xx; + struct cvmx_pip_frm_len_chkx_s cn68xxp1; + struct cvmx_pip_frm_len_chkx_s cnf71xx; }; union cvmx_pip_gbl_cfg { uint64_t u64; struct cvmx_pip_gbl_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t tag_syn:1; uint64_t ip6_udp:1; @@ -290,6 +619,16 @@ union cvmx_pip_gbl_cfg { uint64_t raw_shf:3; uint64_t reserved_3_7:5; uint64_t nip_shf:3; +#else + uint64_t nip_shf:3; + uint64_t reserved_3_7:5; + uint64_t raw_shf:3; + uint64_t reserved_11_15:5; + uint64_t max_l2:1; + uint64_t ip6_udp:1; + uint64_t tag_syn:1; + uint64_t reserved_19_63:45; +#endif } s; struct cvmx_pip_gbl_cfg_s cn30xx; struct cvmx_pip_gbl_cfg_s cn31xx; @@ -302,12 +641,22 @@ union cvmx_pip_gbl_cfg { struct cvmx_pip_gbl_cfg_s cn56xxp1; struct cvmx_pip_gbl_cfg_s cn58xx; struct cvmx_pip_gbl_cfg_s cn58xxp1; + struct cvmx_pip_gbl_cfg_s cn61xx; + struct cvmx_pip_gbl_cfg_s cn63xx; + struct cvmx_pip_gbl_cfg_s cn63xxp1; + struct cvmx_pip_gbl_cfg_s cn66xx; + struct cvmx_pip_gbl_cfg_s cn68xx; + struct cvmx_pip_gbl_cfg_s cn68xxp1; + struct cvmx_pip_gbl_cfg_s cnf71xx; }; union cvmx_pip_gbl_ctl { uint64_t u64; struct cvmx_pip_gbl_ctl_s { - uint64_t reserved_27_63:37; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t egrp_dis:1; + uint64_t ihmsk_dis:1; uint64_t dsa_grp_tvid:1; uint64_t dsa_grp_scmd:1; uint64_t dsa_grp_sid:1; @@ -329,8 +678,35 @@ union cvmx_pip_gbl_ctl { uint64_t ip_hop:1; uint64_t ip_mal:1; uint64_t ip_chk:1; +#else + uint64_t ip_chk:1; + uint64_t ip_mal:1; + uint64_t ip_hop:1; + uint64_t ip4_opts:1; + uint64_t ip6_eext:2; + uint64_t reserved_6_7:2; + uint64_t l4_mal:1; + uint64_t l4_prt:1; + uint64_t l4_chk:1; + uint64_t l4_len:1; + uint64_t tcp_flag:1; + uint64_t l2_mal:1; + uint64_t vs_qos:1; + uint64_t vs_wqe:1; + uint64_t ignrs:1; + uint64_t reserved_17_19:3; + uint64_t ring_en:1; + uint64_t reserved_21_23:3; + uint64_t dsa_grp_sid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_tvid:1; + uint64_t ihmsk_dis:1; + uint64_t egrp_dis:1; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_pip_gbl_ctl_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t ignrs:1; uint64_t vs_wqe:1; @@ -347,15 +723,82 @@ union cvmx_pip_gbl_ctl { uint64_t ip_hop:1; uint64_t ip_mal:1; uint64_t ip_chk:1; +#else + uint64_t ip_chk:1; + uint64_t ip_mal:1; + uint64_t ip_hop:1; + uint64_t ip4_opts:1; + uint64_t ip6_eext:2; + uint64_t reserved_6_7:2; + uint64_t l4_mal:1; + uint64_t l4_prt:1; + uint64_t l4_chk:1; + uint64_t l4_len:1; + uint64_t tcp_flag:1; + uint64_t l2_mal:1; + uint64_t vs_qos:1; + uint64_t vs_wqe:1; + uint64_t ignrs:1; + uint64_t reserved_17_63:47; +#endif } cn30xx; struct cvmx_pip_gbl_ctl_cn30xx cn31xx; struct cvmx_pip_gbl_ctl_cn30xx cn38xx; struct cvmx_pip_gbl_ctl_cn30xx cn38xxp2; struct cvmx_pip_gbl_ctl_cn30xx cn50xx; - struct cvmx_pip_gbl_ctl_s cn52xx; - struct cvmx_pip_gbl_ctl_s cn52xxp1; - struct cvmx_pip_gbl_ctl_s cn56xx; + struct cvmx_pip_gbl_ctl_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_27_63:37; + uint64_t dsa_grp_tvid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_sid:1; + uint64_t reserved_21_23:3; + uint64_t ring_en:1; + uint64_t reserved_17_19:3; + uint64_t ignrs:1; + uint64_t vs_wqe:1; + uint64_t vs_qos:1; + uint64_t l2_mal:1; + uint64_t tcp_flag:1; + uint64_t l4_len:1; + uint64_t l4_chk:1; + uint64_t l4_prt:1; + uint64_t l4_mal:1; + uint64_t reserved_6_7:2; + uint64_t ip6_eext:2; + uint64_t ip4_opts:1; + uint64_t ip_hop:1; + uint64_t ip_mal:1; + uint64_t ip_chk:1; +#else + uint64_t ip_chk:1; + uint64_t ip_mal:1; + uint64_t ip_hop:1; + uint64_t ip4_opts:1; + uint64_t ip6_eext:2; + uint64_t reserved_6_7:2; + uint64_t l4_mal:1; + uint64_t l4_prt:1; + uint64_t l4_chk:1; + uint64_t l4_len:1; + uint64_t tcp_flag:1; + uint64_t l2_mal:1; + uint64_t vs_qos:1; + uint64_t vs_wqe:1; + uint64_t ignrs:1; + uint64_t reserved_17_19:3; + uint64_t ring_en:1; + uint64_t reserved_21_23:3; + uint64_t dsa_grp_sid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_tvid:1; + uint64_t reserved_27_63:37; +#endif + } cn52xx; + struct cvmx_pip_gbl_ctl_cn52xx cn52xxp1; + struct cvmx_pip_gbl_ctl_cn52xx cn56xx; struct cvmx_pip_gbl_ctl_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t ring_en:1; uint64_t reserved_17_19:3; @@ -374,27 +817,215 @@ union cvmx_pip_gbl_ctl { uint64_t ip_hop:1; uint64_t ip_mal:1; uint64_t ip_chk:1; +#else + uint64_t ip_chk:1; + uint64_t ip_mal:1; + uint64_t ip_hop:1; + uint64_t ip4_opts:1; + uint64_t ip6_eext:2; + uint64_t reserved_6_7:2; + uint64_t l4_mal:1; + uint64_t l4_prt:1; + uint64_t l4_chk:1; + uint64_t l4_len:1; + uint64_t tcp_flag:1; + uint64_t l2_mal:1; + uint64_t vs_qos:1; + uint64_t vs_wqe:1; + uint64_t ignrs:1; + uint64_t reserved_17_19:3; + uint64_t ring_en:1; + uint64_t reserved_21_63:43; +#endif } cn56xxp1; struct cvmx_pip_gbl_ctl_cn30xx cn58xx; struct cvmx_pip_gbl_ctl_cn30xx cn58xxp1; + struct cvmx_pip_gbl_ctl_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_28_63:36; + uint64_t ihmsk_dis:1; + uint64_t dsa_grp_tvid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_sid:1; + uint64_t reserved_21_23:3; + uint64_t ring_en:1; + uint64_t reserved_17_19:3; + uint64_t ignrs:1; + uint64_t vs_wqe:1; + uint64_t vs_qos:1; + uint64_t l2_mal:1; + uint64_t tcp_flag:1; + uint64_t l4_len:1; + uint64_t l4_chk:1; + uint64_t l4_prt:1; + uint64_t l4_mal:1; + uint64_t reserved_6_7:2; + uint64_t ip6_eext:2; + uint64_t ip4_opts:1; + uint64_t ip_hop:1; + uint64_t ip_mal:1; + uint64_t ip_chk:1; +#else + uint64_t ip_chk:1; + uint64_t ip_mal:1; + uint64_t ip_hop:1; + uint64_t ip4_opts:1; + uint64_t ip6_eext:2; + uint64_t reserved_6_7:2; + uint64_t l4_mal:1; + uint64_t l4_prt:1; + uint64_t l4_chk:1; + uint64_t l4_len:1; + uint64_t tcp_flag:1; + uint64_t l2_mal:1; + uint64_t vs_qos:1; + uint64_t vs_wqe:1; + uint64_t ignrs:1; + uint64_t reserved_17_19:3; + uint64_t ring_en:1; + uint64_t reserved_21_23:3; + uint64_t dsa_grp_sid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_tvid:1; + uint64_t ihmsk_dis:1; + uint64_t reserved_28_63:36; +#endif + } cn61xx; + struct cvmx_pip_gbl_ctl_cn61xx cn63xx; + struct cvmx_pip_gbl_ctl_cn61xx cn63xxp1; + struct cvmx_pip_gbl_ctl_cn61xx cn66xx; + struct cvmx_pip_gbl_ctl_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_29_63:35; + uint64_t egrp_dis:1; + uint64_t ihmsk_dis:1; + uint64_t dsa_grp_tvid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_sid:1; + uint64_t reserved_17_23:7; + uint64_t ignrs:1; + uint64_t vs_wqe:1; + uint64_t vs_qos:1; + uint64_t l2_mal:1; + uint64_t tcp_flag:1; + uint64_t l4_len:1; + uint64_t l4_chk:1; + uint64_t l4_prt:1; + uint64_t l4_mal:1; + uint64_t reserved_6_7:2; + uint64_t ip6_eext:2; + uint64_t ip4_opts:1; + uint64_t ip_hop:1; + uint64_t ip_mal:1; + uint64_t ip_chk:1; +#else + uint64_t ip_chk:1; + uint64_t ip_mal:1; + uint64_t ip_hop:1; + uint64_t ip4_opts:1; + uint64_t ip6_eext:2; + uint64_t reserved_6_7:2; + uint64_t l4_mal:1; + uint64_t l4_prt:1; + uint64_t l4_chk:1; + uint64_t l4_len:1; + uint64_t tcp_flag:1; + uint64_t l2_mal:1; + uint64_t vs_qos:1; + uint64_t vs_wqe:1; + uint64_t ignrs:1; + uint64_t reserved_17_23:7; + uint64_t dsa_grp_sid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_tvid:1; + uint64_t ihmsk_dis:1; + uint64_t egrp_dis:1; + uint64_t reserved_29_63:35; +#endif + } cn68xx; + struct cvmx_pip_gbl_ctl_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_28_63:36; + uint64_t ihmsk_dis:1; + uint64_t dsa_grp_tvid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_sid:1; + uint64_t reserved_17_23:7; + uint64_t ignrs:1; + uint64_t vs_wqe:1; + uint64_t vs_qos:1; + uint64_t l2_mal:1; + uint64_t tcp_flag:1; + uint64_t l4_len:1; + uint64_t l4_chk:1; + uint64_t l4_prt:1; + uint64_t l4_mal:1; + uint64_t reserved_6_7:2; + uint64_t ip6_eext:2; + uint64_t ip4_opts:1; + uint64_t ip_hop:1; + uint64_t ip_mal:1; + uint64_t ip_chk:1; +#else + uint64_t ip_chk:1; + uint64_t ip_mal:1; + uint64_t ip_hop:1; + uint64_t ip4_opts:1; + uint64_t ip6_eext:2; + uint64_t reserved_6_7:2; + uint64_t l4_mal:1; + uint64_t l4_prt:1; + uint64_t l4_chk:1; + uint64_t l4_len:1; + uint64_t tcp_flag:1; + uint64_t l2_mal:1; + uint64_t vs_qos:1; + uint64_t vs_wqe:1; + uint64_t ignrs:1; + uint64_t reserved_17_23:7; + uint64_t dsa_grp_sid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_tvid:1; + uint64_t ihmsk_dis:1; + uint64_t reserved_28_63:36; +#endif + } cn68xxp1; + struct cvmx_pip_gbl_ctl_cn61xx cnf71xx; }; union cvmx_pip_hg_pri_qos { uint64_t u64; struct cvmx_pip_hg_pri_qos_s { - uint64_t reserved_11_63:53; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_13_63:51; + uint64_t up_qos:1; + uint64_t reserved_11_11:1; uint64_t qos:3; uint64_t reserved_6_7:2; uint64_t pri:6; +#else + uint64_t pri:6; + uint64_t reserved_6_7:2; + uint64_t qos:3; + uint64_t reserved_11_11:1; + uint64_t up_qos:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_pip_hg_pri_qos_s cn52xx; struct cvmx_pip_hg_pri_qos_s cn52xxp1; struct cvmx_pip_hg_pri_qos_s cn56xx; + struct cvmx_pip_hg_pri_qos_s cn61xx; + struct cvmx_pip_hg_pri_qos_s cn63xx; + struct cvmx_pip_hg_pri_qos_s cn63xxp1; + struct cvmx_pip_hg_pri_qos_s cn66xx; + struct cvmx_pip_hg_pri_qos_s cnf71xx; }; union cvmx_pip_int_en { uint64_t u64; struct cvmx_pip_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t lenerr:1; @@ -409,8 +1040,25 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t crcerr:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t minerr:1; + uint64_t maxerr:1; + uint64_t lenerr:1; + uint64_t punyerr:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_pip_int_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t beperr:1; uint64_t feperr:1; @@ -421,11 +1069,24 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t crcerr:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t reserved_9_63:55; +#endif } cn30xx; struct cvmx_pip_int_en_cn30xx cn31xx; struct cvmx_pip_int_en_cn30xx cn38xx; struct cvmx_pip_int_en_cn30xx cn38xxp2; struct cvmx_pip_int_en_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t lenerr:1; uint64_t maxerr:1; @@ -439,8 +1100,24 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t reserved_1_1:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t reserved_1_1:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t minerr:1; + uint64_t maxerr:1; + uint64_t lenerr:1; + uint64_t reserved_12_63:52; +#endif } cn50xx; struct cvmx_pip_int_en_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t lenerr:1; @@ -455,10 +1132,27 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t reserved_1_1:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t reserved_1_1:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t minerr:1; + uint64_t maxerr:1; + uint64_t lenerr:1; + uint64_t punyerr:1; + uint64_t reserved_13_63:51; +#endif } cn52xx; struct cvmx_pip_int_en_cn52xx cn52xxp1; struct cvmx_pip_int_en_s cn56xx; struct cvmx_pip_int_en_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t lenerr:1; uint64_t maxerr:1; @@ -472,8 +1166,24 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t crcerr:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t minerr:1; + uint64_t maxerr:1; + uint64_t lenerr:1; + uint64_t reserved_12_63:52; +#endif } cn56xxp1; struct cvmx_pip_int_en_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t reserved_9_11:3; @@ -486,13 +1196,35 @@ union cvmx_pip_int_en { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t crcerr:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t reserved_9_11:3; + uint64_t punyerr:1; + uint64_t reserved_13_63:51; +#endif } cn58xx; struct cvmx_pip_int_en_cn30xx cn58xxp1; + struct cvmx_pip_int_en_s cn61xx; + struct cvmx_pip_int_en_s cn63xx; + struct cvmx_pip_int_en_s cn63xxp1; + struct cvmx_pip_int_en_s cn66xx; + struct cvmx_pip_int_en_s cn68xx; + struct cvmx_pip_int_en_s cn68xxp1; + struct cvmx_pip_int_en_s cnf71xx; }; union cvmx_pip_int_reg { uint64_t u64; struct cvmx_pip_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t lenerr:1; @@ -507,8 +1239,25 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t crcerr:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t minerr:1; + uint64_t maxerr:1; + uint64_t lenerr:1; + uint64_t punyerr:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_pip_int_reg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t beperr:1; uint64_t feperr:1; @@ -519,11 +1268,24 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t crcerr:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t reserved_9_63:55; +#endif } cn30xx; struct cvmx_pip_int_reg_cn30xx cn31xx; struct cvmx_pip_int_reg_cn30xx cn38xx; struct cvmx_pip_int_reg_cn30xx cn38xxp2; struct cvmx_pip_int_reg_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t lenerr:1; uint64_t maxerr:1; @@ -537,8 +1299,24 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t reserved_1_1:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t reserved_1_1:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t minerr:1; + uint64_t maxerr:1; + uint64_t lenerr:1; + uint64_t reserved_12_63:52; +#endif } cn50xx; struct cvmx_pip_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t lenerr:1; @@ -553,10 +1331,27 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t reserved_1_1:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t reserved_1_1:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t minerr:1; + uint64_t maxerr:1; + uint64_t lenerr:1; + uint64_t punyerr:1; + uint64_t reserved_13_63:51; +#endif } cn52xx; struct cvmx_pip_int_reg_cn52xx cn52xxp1; struct cvmx_pip_int_reg_s cn56xx; struct cvmx_pip_int_reg_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t lenerr:1; uint64_t maxerr:1; @@ -570,8 +1365,24 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t crcerr:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t minerr:1; + uint64_t maxerr:1; + uint64_t lenerr:1; + uint64_t reserved_12_63:52; +#endif } cn56xxp1; struct cvmx_pip_int_reg_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t punyerr:1; uint64_t reserved_9_11:3; @@ -584,15 +1395,41 @@ union cvmx_pip_int_reg { uint64_t bckprs:1; uint64_t crcerr:1; uint64_t pktdrp:1; +#else + uint64_t pktdrp:1; + uint64_t crcerr:1; + uint64_t bckprs:1; + uint64_t prtnxa:1; + uint64_t badtag:1; + uint64_t skprunt:1; + uint64_t todoovr:1; + uint64_t feperr:1; + uint64_t beperr:1; + uint64_t reserved_9_11:3; + uint64_t punyerr:1; + uint64_t reserved_13_63:51; +#endif } cn58xx; struct cvmx_pip_int_reg_cn30xx cn58xxp1; + struct cvmx_pip_int_reg_s cn61xx; + struct cvmx_pip_int_reg_s cn63xx; + struct cvmx_pip_int_reg_s cn63xxp1; + struct cvmx_pip_int_reg_s cn66xx; + struct cvmx_pip_int_reg_s cn68xx; + struct cvmx_pip_int_reg_s cn68xxp1; + struct cvmx_pip_int_reg_s cnf71xx; }; union cvmx_pip_ip_offset { uint64_t u64; struct cvmx_pip_ip_offset_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t offset:3; +#else + uint64_t offset:3; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_pip_ip_offset_s cn30xx; struct cvmx_pip_ip_offset_s cn31xx; @@ -605,12 +1442,63 @@ union cvmx_pip_ip_offset { struct cvmx_pip_ip_offset_s cn56xxp1; struct cvmx_pip_ip_offset_s cn58xx; struct cvmx_pip_ip_offset_s cn58xxp1; + struct cvmx_pip_ip_offset_s cn61xx; + struct cvmx_pip_ip_offset_s cn63xx; + struct cvmx_pip_ip_offset_s cn63xxp1; + struct cvmx_pip_ip_offset_s cn66xx; + struct cvmx_pip_ip_offset_s cn68xx; + struct cvmx_pip_ip_offset_s cn68xxp1; + struct cvmx_pip_ip_offset_s cnf71xx; +}; + +union cvmx_pip_pri_tblx { + uint64_t u64; + struct cvmx_pip_pri_tblx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t diff2_padd:8; + uint64_t hg2_padd:8; + uint64_t vlan2_padd:8; + uint64_t reserved_38_39:2; + uint64_t diff2_bpid:6; + uint64_t reserved_30_31:2; + uint64_t hg2_bpid:6; + uint64_t reserved_22_23:2; + uint64_t vlan2_bpid:6; + uint64_t reserved_11_15:5; + uint64_t diff2_qos:3; + uint64_t reserved_7_7:1; + uint64_t hg2_qos:3; + uint64_t reserved_3_3:1; + uint64_t vlan2_qos:3; +#else + uint64_t vlan2_qos:3; + uint64_t reserved_3_3:1; + uint64_t hg2_qos:3; + uint64_t reserved_7_7:1; + uint64_t diff2_qos:3; + uint64_t reserved_11_15:5; + uint64_t vlan2_bpid:6; + uint64_t reserved_22_23:2; + uint64_t hg2_bpid:6; + uint64_t reserved_30_31:2; + uint64_t diff2_bpid:6; + uint64_t reserved_38_39:2; + uint64_t vlan2_padd:8; + uint64_t hg2_padd:8; + uint64_t diff2_padd:8; +#endif + } s; + struct cvmx_pip_pri_tblx_s cn68xx; + struct cvmx_pip_pri_tblx_s cn68xxp1; }; union cvmx_pip_prt_cfgx { uint64_t u64; struct cvmx_pip_prt_cfgx_s { - uint64_t reserved_53_63:11; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_55_63:9; + uint64_t ih_pri:1; + uint64_t len_chk_sel:1; uint64_t pad_len:1; uint64_t vlan_len:1; uint64_t lenerr_en:1; @@ -638,8 +1526,41 @@ union cvmx_pip_prt_cfgx { uint64_t mode:2; uint64_t reserved_7_7:1; uint64_t skip:7; +#else + uint64_t skip:7; + uint64_t reserved_7_7:1; + uint64_t mode:2; + uint64_t dsa_en:1; + uint64_t higig_en:1; + uint64_t crc_en:1; + uint64_t reserved_13_15:3; + uint64_t qos_vlan:1; + uint64_t qos_diff:1; + uint64_t qos_vod:1; + uint64_t qos_vsel:1; + uint64_t qos_wat:4; + uint64_t qos:3; + uint64_t hg_qos:1; + uint64_t grp_wat:4; + uint64_t inst_hdr:1; + uint64_t dyn_rs:1; + uint64_t tag_inc:2; + uint64_t rawdrp:1; + uint64_t reserved_37_39:3; + uint64_t qos_wat_47:4; + uint64_t grp_wat_47:4; + uint64_t minerr_en:1; + uint64_t maxerr_en:1; + uint64_t lenerr_en:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t len_chk_sel:1; + uint64_t ih_pri:1; + uint64_t reserved_55_63:9; +#endif } s; struct cvmx_pip_prt_cfgx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t rawdrp:1; uint64_t tag_inc:2; @@ -656,9 +1577,28 @@ union cvmx_pip_prt_cfgx { uint64_t mode:2; uint64_t reserved_7_7:1; uint64_t skip:7; +#else + uint64_t skip:7; + uint64_t reserved_7_7:1; + uint64_t mode:2; + uint64_t reserved_10_15:6; + uint64_t qos_vlan:1; + uint64_t qos_diff:1; + uint64_t reserved_18_19:2; + uint64_t qos_wat:4; + uint64_t qos:3; + uint64_t reserved_27_27:1; + uint64_t grp_wat:4; + uint64_t inst_hdr:1; + uint64_t dyn_rs:1; + uint64_t tag_inc:2; + uint64_t rawdrp:1; + uint64_t reserved_37_63:27; +#endif } cn30xx; struct cvmx_pip_prt_cfgx_cn30xx cn31xx; struct cvmx_pip_prt_cfgx_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t rawdrp:1; uint64_t tag_inc:2; @@ -677,9 +1617,30 @@ union cvmx_pip_prt_cfgx { uint64_t mode:2; uint64_t reserved_7_7:1; uint64_t skip:7; +#else + uint64_t skip:7; + uint64_t reserved_7_7:1; + uint64_t mode:2; + uint64_t reserved_10_11:2; + uint64_t crc_en:1; + uint64_t reserved_13_15:3; + uint64_t qos_vlan:1; + uint64_t qos_diff:1; + uint64_t reserved_18_19:2; + uint64_t qos_wat:4; + uint64_t qos:3; + uint64_t reserved_27_27:1; + uint64_t grp_wat:4; + uint64_t inst_hdr:1; + uint64_t dyn_rs:1; + uint64_t tag_inc:2; + uint64_t rawdrp:1; + uint64_t reserved_37_63:27; +#endif } cn38xx; struct cvmx_pip_prt_cfgx_cn38xx cn38xxp2; struct cvmx_pip_prt_cfgx_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_53_63:11; uint64_t pad_len:1; uint64_t vlan_len:1; @@ -707,12 +1668,102 @@ union cvmx_pip_prt_cfgx { uint64_t mode:2; uint64_t reserved_7_7:1; uint64_t skip:7; +#else + uint64_t skip:7; + uint64_t reserved_7_7:1; + uint64_t mode:2; + uint64_t reserved_10_11:2; + uint64_t crc_en:1; + uint64_t reserved_13_15:3; + uint64_t qos_vlan:1; + uint64_t qos_diff:1; + uint64_t qos_vod:1; + uint64_t reserved_19_19:1; + uint64_t qos_wat:4; + uint64_t qos:3; + uint64_t reserved_27_27:1; + uint64_t grp_wat:4; + uint64_t inst_hdr:1; + uint64_t dyn_rs:1; + uint64_t tag_inc:2; + uint64_t rawdrp:1; + uint64_t reserved_37_39:3; + uint64_t qos_wat_47:4; + uint64_t grp_wat_47:4; + uint64_t minerr_en:1; + uint64_t maxerr_en:1; + uint64_t lenerr_en:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t reserved_53_63:11; +#endif } cn50xx; - struct cvmx_pip_prt_cfgx_s cn52xx; - struct cvmx_pip_prt_cfgx_s cn52xxp1; - struct cvmx_pip_prt_cfgx_s cn56xx; + struct cvmx_pip_prt_cfgx_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_53_63:11; + uint64_t pad_len:1; + uint64_t vlan_len:1; + uint64_t lenerr_en:1; + uint64_t maxerr_en:1; + uint64_t minerr_en:1; + uint64_t grp_wat_47:4; + uint64_t qos_wat_47:4; + uint64_t reserved_37_39:3; + uint64_t rawdrp:1; + uint64_t tag_inc:2; + uint64_t dyn_rs:1; + uint64_t inst_hdr:1; + uint64_t grp_wat:4; + uint64_t hg_qos:1; + uint64_t qos:3; + uint64_t qos_wat:4; + uint64_t qos_vsel:1; + uint64_t qos_vod:1; + uint64_t qos_diff:1; + uint64_t qos_vlan:1; + uint64_t reserved_13_15:3; + uint64_t crc_en:1; + uint64_t higig_en:1; + uint64_t dsa_en:1; + uint64_t mode:2; + uint64_t reserved_7_7:1; + uint64_t skip:7; +#else + uint64_t skip:7; + uint64_t reserved_7_7:1; + uint64_t mode:2; + uint64_t dsa_en:1; + uint64_t higig_en:1; + uint64_t crc_en:1; + uint64_t reserved_13_15:3; + uint64_t qos_vlan:1; + uint64_t qos_diff:1; + uint64_t qos_vod:1; + uint64_t qos_vsel:1; + uint64_t qos_wat:4; + uint64_t qos:3; + uint64_t hg_qos:1; + uint64_t grp_wat:4; + uint64_t inst_hdr:1; + uint64_t dyn_rs:1; + uint64_t tag_inc:2; + uint64_t rawdrp:1; + uint64_t reserved_37_39:3; + uint64_t qos_wat_47:4; + uint64_t grp_wat_47:4; + uint64_t minerr_en:1; + uint64_t maxerr_en:1; + uint64_t lenerr_en:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t reserved_53_63:11; +#endif + } cn52xx; + struct cvmx_pip_prt_cfgx_cn52xx cn52xxp1; + struct cvmx_pip_prt_cfgx_cn52xx cn56xx; struct cvmx_pip_prt_cfgx_cn50xx cn56xxp1; struct cvmx_pip_prt_cfgx_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t rawdrp:1; uint64_t tag_inc:2; @@ -732,14 +1783,191 @@ union cvmx_pip_prt_cfgx { uint64_t mode:2; uint64_t reserved_7_7:1; uint64_t skip:7; +#else + uint64_t skip:7; + uint64_t reserved_7_7:1; + uint64_t mode:2; + uint64_t reserved_10_11:2; + uint64_t crc_en:1; + uint64_t reserved_13_15:3; + uint64_t qos_vlan:1; + uint64_t qos_diff:1; + uint64_t qos_vod:1; + uint64_t reserved_19_19:1; + uint64_t qos_wat:4; + uint64_t qos:3; + uint64_t reserved_27_27:1; + uint64_t grp_wat:4; + uint64_t inst_hdr:1; + uint64_t dyn_rs:1; + uint64_t tag_inc:2; + uint64_t rawdrp:1; + uint64_t reserved_37_63:27; +#endif } cn58xx; struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1; + struct cvmx_pip_prt_cfgx_cn52xx cn61xx; + struct cvmx_pip_prt_cfgx_cn52xx cn63xx; + struct cvmx_pip_prt_cfgx_cn52xx cn63xxp1; + struct cvmx_pip_prt_cfgx_cn52xx cn66xx; + struct cvmx_pip_prt_cfgx_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_55_63:9; + uint64_t ih_pri:1; + uint64_t len_chk_sel:1; + uint64_t pad_len:1; + uint64_t vlan_len:1; + uint64_t lenerr_en:1; + uint64_t maxerr_en:1; + uint64_t minerr_en:1; + uint64_t grp_wat_47:4; + uint64_t qos_wat_47:4; + uint64_t reserved_37_39:3; + uint64_t rawdrp:1; + uint64_t tag_inc:2; + uint64_t dyn_rs:1; + uint64_t inst_hdr:1; + uint64_t grp_wat:4; + uint64_t hg_qos:1; + uint64_t qos:3; + uint64_t qos_wat:4; + uint64_t reserved_19_19:1; + uint64_t qos_vod:1; + uint64_t qos_diff:1; + uint64_t qos_vlan:1; + uint64_t reserved_13_15:3; + uint64_t crc_en:1; + uint64_t higig_en:1; + uint64_t dsa_en:1; + uint64_t mode:2; + uint64_t reserved_7_7:1; + uint64_t skip:7; +#else + uint64_t skip:7; + uint64_t reserved_7_7:1; + uint64_t mode:2; + uint64_t dsa_en:1; + uint64_t higig_en:1; + uint64_t crc_en:1; + uint64_t reserved_13_15:3; + uint64_t qos_vlan:1; + uint64_t qos_diff:1; + uint64_t qos_vod:1; + uint64_t reserved_19_19:1; + uint64_t qos_wat:4; + uint64_t qos:3; + uint64_t hg_qos:1; + uint64_t grp_wat:4; + uint64_t inst_hdr:1; + uint64_t dyn_rs:1; + uint64_t tag_inc:2; + uint64_t rawdrp:1; + uint64_t reserved_37_39:3; + uint64_t qos_wat_47:4; + uint64_t grp_wat_47:4; + uint64_t minerr_en:1; + uint64_t maxerr_en:1; + uint64_t lenerr_en:1; + uint64_t vlan_len:1; + uint64_t pad_len:1; + uint64_t len_chk_sel:1; + uint64_t ih_pri:1; + uint64_t reserved_55_63:9; +#endif + } cn68xx; + struct cvmx_pip_prt_cfgx_cn68xx cn68xxp1; + struct cvmx_pip_prt_cfgx_cn52xx cnf71xx; +}; + +union cvmx_pip_prt_cfgbx { + uint64_t u64; + struct cvmx_pip_prt_cfgbx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_39_63:25; + uint64_t alt_skp_sel:2; + uint64_t alt_skp_en:1; + uint64_t reserved_35_35:1; + uint64_t bsel_num:2; + uint64_t bsel_en:1; + uint64_t reserved_24_31:8; + uint64_t base:8; + uint64_t reserved_6_15:10; + uint64_t bpid:6; +#else + uint64_t bpid:6; + uint64_t reserved_6_15:10; + uint64_t base:8; + uint64_t reserved_24_31:8; + uint64_t bsel_en:1; + uint64_t bsel_num:2; + uint64_t reserved_35_35:1; + uint64_t alt_skp_en:1; + uint64_t alt_skp_sel:2; + uint64_t reserved_39_63:25; +#endif + } s; + struct cvmx_pip_prt_cfgbx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_39_63:25; + uint64_t alt_skp_sel:2; + uint64_t alt_skp_en:1; + uint64_t reserved_35_35:1; + uint64_t bsel_num:2; + uint64_t bsel_en:1; + uint64_t reserved_0_31:32; +#else + uint64_t reserved_0_31:32; + uint64_t bsel_en:1; + uint64_t bsel_num:2; + uint64_t reserved_35_35:1; + uint64_t alt_skp_en:1; + uint64_t alt_skp_sel:2; + uint64_t reserved_39_63:25; +#endif + } cn61xx; + struct cvmx_pip_prt_cfgbx_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_39_63:25; + uint64_t alt_skp_sel:2; + uint64_t alt_skp_en:1; + uint64_t reserved_0_35:36; +#else + uint64_t reserved_0_35:36; + uint64_t alt_skp_en:1; + uint64_t alt_skp_sel:2; + uint64_t reserved_39_63:25; +#endif + } cn66xx; + struct cvmx_pip_prt_cfgbx_s cn68xx; + struct cvmx_pip_prt_cfgbx_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_24_63:40; + uint64_t base:8; + uint64_t reserved_6_15:10; + uint64_t bpid:6; +#else + uint64_t bpid:6; + uint64_t reserved_6_15:10; + uint64_t base:8; + uint64_t reserved_24_63:40; +#endif + } cn68xxp1; + struct cvmx_pip_prt_cfgbx_cn61xx cnf71xx; }; union cvmx_pip_prt_tagx { uint64_t u64; struct cvmx_pip_prt_tagx_s { - uint64_t reserved_40_63:24; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_54_63:10; + uint64_t portadd_en:1; + uint64_t inc_hwchk:1; + uint64_t reserved_50_51:2; + uint64_t grptagbase_msb:2; + uint64_t reserved_46_47:2; + uint64_t grptagmask_msb:2; + uint64_t reserved_42_43:2; + uint64_t grp_msb:2; uint64_t grptagbase:4; uint64_t grptagmask:4; uint64_t grptag:1; @@ -764,8 +1992,44 @@ union cvmx_pip_prt_tagx { uint64_t ip4_tag_type:2; uint64_t non_tag_type:2; uint64_t grp:4; +#else + uint64_t grp:4; + uint64_t non_tag_type:2; + uint64_t ip4_tag_type:2; + uint64_t ip6_tag_type:2; + uint64_t tcp4_tag_type:2; + uint64_t tcp6_tag_type:2; + uint64_t ip4_src_flag:1; + uint64_t ip6_src_flag:1; + uint64_t ip4_dst_flag:1; + uint64_t ip6_dst_flag:1; + uint64_t ip4_pctl_flag:1; + uint64_t ip6_nxth_flag:1; + uint64_t ip4_sprt_flag:1; + uint64_t ip6_sprt_flag:1; + uint64_t ip4_dprt_flag:1; + uint64_t ip6_dprt_flag:1; + uint64_t inc_prt_flag:1; + uint64_t inc_vlan:1; + uint64_t inc_vs:2; + uint64_t tag_mode:2; + uint64_t grptag_mskip:1; + uint64_t grptag:1; + uint64_t grptagmask:4; + uint64_t grptagbase:4; + uint64_t grp_msb:2; + uint64_t reserved_42_43:2; + uint64_t grptagmask_msb:2; + uint64_t reserved_46_47:2; + uint64_t grptagbase_msb:2; + uint64_t reserved_50_51:2; + uint64_t inc_hwchk:1; + uint64_t portadd_en:1; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_pip_prt_tagx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t grptagbase:4; uint64_t grptagmask:4; @@ -791,24 +2055,117 @@ union cvmx_pip_prt_tagx { uint64_t ip4_tag_type:2; uint64_t non_tag_type:2; uint64_t grp:4; +#else + uint64_t grp:4; + uint64_t non_tag_type:2; + uint64_t ip4_tag_type:2; + uint64_t ip6_tag_type:2; + uint64_t tcp4_tag_type:2; + uint64_t tcp6_tag_type:2; + uint64_t ip4_src_flag:1; + uint64_t ip6_src_flag:1; + uint64_t ip4_dst_flag:1; + uint64_t ip6_dst_flag:1; + uint64_t ip4_pctl_flag:1; + uint64_t ip6_nxth_flag:1; + uint64_t ip4_sprt_flag:1; + uint64_t ip6_sprt_flag:1; + uint64_t ip4_dprt_flag:1; + uint64_t ip6_dprt_flag:1; + uint64_t inc_prt_flag:1; + uint64_t inc_vlan:1; + uint64_t inc_vs:2; + uint64_t tag_mode:2; + uint64_t reserved_30_30:1; + uint64_t grptag:1; + uint64_t grptagmask:4; + uint64_t grptagbase:4; + uint64_t reserved_40_63:24; +#endif } cn30xx; struct cvmx_pip_prt_tagx_cn30xx cn31xx; struct cvmx_pip_prt_tagx_cn30xx cn38xx; struct cvmx_pip_prt_tagx_cn30xx cn38xxp2; - struct cvmx_pip_prt_tagx_s cn50xx; - struct cvmx_pip_prt_tagx_s cn52xx; - struct cvmx_pip_prt_tagx_s cn52xxp1; - struct cvmx_pip_prt_tagx_s cn56xx; - struct cvmx_pip_prt_tagx_s cn56xxp1; + struct cvmx_pip_prt_tagx_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_40_63:24; + uint64_t grptagbase:4; + uint64_t grptagmask:4; + uint64_t grptag:1; + uint64_t grptag_mskip:1; + uint64_t tag_mode:2; + uint64_t inc_vs:2; + uint64_t inc_vlan:1; + uint64_t inc_prt_flag:1; + uint64_t ip6_dprt_flag:1; + uint64_t ip4_dprt_flag:1; + uint64_t ip6_sprt_flag:1; + uint64_t ip4_sprt_flag:1; + uint64_t ip6_nxth_flag:1; + uint64_t ip4_pctl_flag:1; + uint64_t ip6_dst_flag:1; + uint64_t ip4_dst_flag:1; + uint64_t ip6_src_flag:1; + uint64_t ip4_src_flag:1; + uint64_t tcp6_tag_type:2; + uint64_t tcp4_tag_type:2; + uint64_t ip6_tag_type:2; + uint64_t ip4_tag_type:2; + uint64_t non_tag_type:2; + uint64_t grp:4; +#else + uint64_t grp:4; + uint64_t non_tag_type:2; + uint64_t ip4_tag_type:2; + uint64_t ip6_tag_type:2; + uint64_t tcp4_tag_type:2; + uint64_t tcp6_tag_type:2; + uint64_t ip4_src_flag:1; + uint64_t ip6_src_flag:1; + uint64_t ip4_dst_flag:1; + uint64_t ip6_dst_flag:1; + uint64_t ip4_pctl_flag:1; + uint64_t ip6_nxth_flag:1; + uint64_t ip4_sprt_flag:1; + uint64_t ip6_sprt_flag:1; + uint64_t ip4_dprt_flag:1; + uint64_t ip6_dprt_flag:1; + uint64_t inc_prt_flag:1; + uint64_t inc_vlan:1; + uint64_t inc_vs:2; + uint64_t tag_mode:2; + uint64_t grptag_mskip:1; + uint64_t grptag:1; + uint64_t grptagmask:4; + uint64_t grptagbase:4; + uint64_t reserved_40_63:24; +#endif + } cn50xx; + struct cvmx_pip_prt_tagx_cn50xx cn52xx; + struct cvmx_pip_prt_tagx_cn50xx cn52xxp1; + struct cvmx_pip_prt_tagx_cn50xx cn56xx; + struct cvmx_pip_prt_tagx_cn50xx cn56xxp1; struct cvmx_pip_prt_tagx_cn30xx cn58xx; struct cvmx_pip_prt_tagx_cn30xx cn58xxp1; + struct cvmx_pip_prt_tagx_cn50xx cn61xx; + struct cvmx_pip_prt_tagx_cn50xx cn63xx; + struct cvmx_pip_prt_tagx_cn50xx cn63xxp1; + struct cvmx_pip_prt_tagx_cn50xx cn66xx; + struct cvmx_pip_prt_tagx_s cn68xx; + struct cvmx_pip_prt_tagx_s cn68xxp1; + struct cvmx_pip_prt_tagx_cn50xx cnf71xx; }; union cvmx_pip_qos_diffx { uint64_t u64; struct cvmx_pip_qos_diffx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_pip_qos_diffx_s cn30xx; struct cvmx_pip_qos_diffx_s cn31xx; @@ -821,19 +2178,36 @@ union cvmx_pip_qos_diffx { struct cvmx_pip_qos_diffx_s cn56xxp1; struct cvmx_pip_qos_diffx_s cn58xx; struct cvmx_pip_qos_diffx_s cn58xxp1; + struct cvmx_pip_qos_diffx_s cn61xx; + struct cvmx_pip_qos_diffx_s cn63xx; + struct cvmx_pip_qos_diffx_s cn63xxp1; + struct cvmx_pip_qos_diffx_s cn66xx; + struct cvmx_pip_qos_diffx_s cnf71xx; }; union cvmx_pip_qos_vlanx { uint64_t u64; struct cvmx_pip_qos_vlanx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t qos1:3; uint64_t reserved_3_3:1; uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t reserved_3_3:1; + uint64_t qos1:3; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_pip_qos_vlanx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t reserved_3_63:61; +#endif } cn30xx; struct cvmx_pip_qos_vlanx_cn30xx cn31xx; struct cvmx_pip_qos_vlanx_cn30xx cn38xx; @@ -845,22 +2219,40 @@ union cvmx_pip_qos_vlanx { struct cvmx_pip_qos_vlanx_cn30xx cn56xxp1; struct cvmx_pip_qos_vlanx_cn30xx cn58xx; struct cvmx_pip_qos_vlanx_cn30xx cn58xxp1; + struct cvmx_pip_qos_vlanx_s cn61xx; + struct cvmx_pip_qos_vlanx_s cn63xx; + struct cvmx_pip_qos_vlanx_s cn63xxp1; + struct cvmx_pip_qos_vlanx_s cn66xx; + struct cvmx_pip_qos_vlanx_s cnf71xx; }; union cvmx_pip_qos_watchx { uint64_t u64; struct cvmx_pip_qos_watchx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t mask:16; - uint64_t reserved_28_31:4; - uint64_t grp:4; + uint64_t reserved_30_31:2; + uint64_t grp:6; uint64_t reserved_23_23:1; uint64_t qos:3; uint64_t reserved_19_19:1; uint64_t match_type:3; uint64_t match_value:16; +#else + uint64_t match_value:16; + uint64_t match_type:3; + uint64_t reserved_19_19:1; + uint64_t qos:3; + uint64_t reserved_23_23:1; + uint64_t grp:6; + uint64_t reserved_30_31:2; + uint64_t mask:16; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_pip_qos_watchx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t mask:16; uint64_t reserved_28_31:4; @@ -870,24 +2262,69 @@ union cvmx_pip_qos_watchx { uint64_t reserved_18_19:2; uint64_t match_type:2; uint64_t match_value:16; +#else + uint64_t match_value:16; + uint64_t match_type:2; + uint64_t reserved_18_19:2; + uint64_t qos:3; + uint64_t reserved_23_23:1; + uint64_t grp:4; + uint64_t reserved_28_31:4; + uint64_t mask:16; + uint64_t reserved_48_63:16; +#endif } cn30xx; struct cvmx_pip_qos_watchx_cn30xx cn31xx; struct cvmx_pip_qos_watchx_cn30xx cn38xx; struct cvmx_pip_qos_watchx_cn30xx cn38xxp2; - struct cvmx_pip_qos_watchx_s cn50xx; - struct cvmx_pip_qos_watchx_s cn52xx; - struct cvmx_pip_qos_watchx_s cn52xxp1; - struct cvmx_pip_qos_watchx_s cn56xx; - struct cvmx_pip_qos_watchx_s cn56xxp1; + struct cvmx_pip_qos_watchx_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t mask:16; + uint64_t reserved_28_31:4; + uint64_t grp:4; + uint64_t reserved_23_23:1; + uint64_t qos:3; + uint64_t reserved_19_19:1; + uint64_t match_type:3; + uint64_t match_value:16; +#else + uint64_t match_value:16; + uint64_t match_type:3; + uint64_t reserved_19_19:1; + uint64_t qos:3; + uint64_t reserved_23_23:1; + uint64_t grp:4; + uint64_t reserved_28_31:4; + uint64_t mask:16; + uint64_t reserved_48_63:16; +#endif + } cn50xx; + struct cvmx_pip_qos_watchx_cn50xx cn52xx; + struct cvmx_pip_qos_watchx_cn50xx cn52xxp1; + struct cvmx_pip_qos_watchx_cn50xx cn56xx; + struct cvmx_pip_qos_watchx_cn50xx cn56xxp1; struct cvmx_pip_qos_watchx_cn30xx cn58xx; struct cvmx_pip_qos_watchx_cn30xx cn58xxp1; + struct cvmx_pip_qos_watchx_cn50xx cn61xx; + struct cvmx_pip_qos_watchx_cn50xx cn63xx; + struct cvmx_pip_qos_watchx_cn50xx cn63xxp1; + struct cvmx_pip_qos_watchx_cn50xx cn66xx; + struct cvmx_pip_qos_watchx_s cn68xx; + struct cvmx_pip_qos_watchx_s cn68xxp1; + struct cvmx_pip_qos_watchx_cn50xx cnf71xx; }; union cvmx_pip_raw_word { uint64_t u64; struct cvmx_pip_raw_word_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t word:56; +#else + uint64_t word:56; + uint64_t reserved_56_63:8; +#endif } s; struct cvmx_pip_raw_word_s cn30xx; struct cvmx_pip_raw_word_s cn31xx; @@ -900,13 +2337,25 @@ union cvmx_pip_raw_word { struct cvmx_pip_raw_word_s cn56xxp1; struct cvmx_pip_raw_word_s cn58xx; struct cvmx_pip_raw_word_s cn58xxp1; + struct cvmx_pip_raw_word_s cn61xx; + struct cvmx_pip_raw_word_s cn63xx; + struct cvmx_pip_raw_word_s cn63xxp1; + struct cvmx_pip_raw_word_s cn66xx; + struct cvmx_pip_raw_word_s cn68xx; + struct cvmx_pip_raw_word_s cn68xxp1; + struct cvmx_pip_raw_word_s cnf71xx; }; union cvmx_pip_sft_rst { uint64_t u64; struct cvmx_pip_sft_rst_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t rst:1; +#else + uint64_t rst:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_pip_sft_rst_s cn30xx; struct cvmx_pip_sft_rst_s cn31xx; @@ -918,13 +2367,40 @@ union cvmx_pip_sft_rst { struct cvmx_pip_sft_rst_s cn56xxp1; struct cvmx_pip_sft_rst_s cn58xx; struct cvmx_pip_sft_rst_s cn58xxp1; + struct cvmx_pip_sft_rst_s cn61xx; + struct cvmx_pip_sft_rst_s cn63xx; + struct cvmx_pip_sft_rst_s cn63xxp1; + struct cvmx_pip_sft_rst_s cn66xx; + struct cvmx_pip_sft_rst_s cn68xx; + struct cvmx_pip_sft_rst_s cn68xxp1; + struct cvmx_pip_sft_rst_s cnf71xx; +}; + +union cvmx_pip_stat0_x { + uint64_t u64; + struct cvmx_pip_stat0_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t drp_pkts:32; + uint64_t drp_octs:32; +#else + uint64_t drp_octs:32; + uint64_t drp_pkts:32; +#endif + } s; + struct cvmx_pip_stat0_x_s cn68xx; + struct cvmx_pip_stat0_x_s cn68xxp1; }; union cvmx_pip_stat0_prtx { uint64_t u64; struct cvmx_pip_stat0_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t drp_pkts:32; uint64_t drp_octs:32; +#else + uint64_t drp_octs:32; + uint64_t drp_pkts:32; +#endif } s; struct cvmx_pip_stat0_prtx_s cn30xx; struct cvmx_pip_stat0_prtx_s cn31xx; @@ -937,13 +2413,112 @@ union cvmx_pip_stat0_prtx { struct cvmx_pip_stat0_prtx_s cn56xxp1; struct cvmx_pip_stat0_prtx_s cn58xx; struct cvmx_pip_stat0_prtx_s cn58xxp1; + struct cvmx_pip_stat0_prtx_s cn61xx; + struct cvmx_pip_stat0_prtx_s cn63xx; + struct cvmx_pip_stat0_prtx_s cn63xxp1; + struct cvmx_pip_stat0_prtx_s cn66xx; + struct cvmx_pip_stat0_prtx_s cnf71xx; +}; + +union cvmx_pip_stat10_x { + uint64_t u64; + struct cvmx_pip_stat10_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bcast:32; + uint64_t mcast:32; +#else + uint64_t mcast:32; + uint64_t bcast:32; +#endif + } s; + struct cvmx_pip_stat10_x_s cn68xx; + struct cvmx_pip_stat10_x_s cn68xxp1; +}; + +union cvmx_pip_stat10_prtx { + uint64_t u64; + struct cvmx_pip_stat10_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bcast:32; + uint64_t mcast:32; +#else + uint64_t mcast:32; + uint64_t bcast:32; +#endif + } s; + struct cvmx_pip_stat10_prtx_s cn52xx; + struct cvmx_pip_stat10_prtx_s cn52xxp1; + struct cvmx_pip_stat10_prtx_s cn56xx; + struct cvmx_pip_stat10_prtx_s cn56xxp1; + struct cvmx_pip_stat10_prtx_s cn61xx; + struct cvmx_pip_stat10_prtx_s cn63xx; + struct cvmx_pip_stat10_prtx_s cn63xxp1; + struct cvmx_pip_stat10_prtx_s cn66xx; + struct cvmx_pip_stat10_prtx_s cnf71xx; +}; + +union cvmx_pip_stat11_x { + uint64_t u64; + struct cvmx_pip_stat11_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bcast:32; + uint64_t mcast:32; +#else + uint64_t mcast:32; + uint64_t bcast:32; +#endif + } s; + struct cvmx_pip_stat11_x_s cn68xx; + struct cvmx_pip_stat11_x_s cn68xxp1; +}; + +union cvmx_pip_stat11_prtx { + uint64_t u64; + struct cvmx_pip_stat11_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bcast:32; + uint64_t mcast:32; +#else + uint64_t mcast:32; + uint64_t bcast:32; +#endif + } s; + struct cvmx_pip_stat11_prtx_s cn52xx; + struct cvmx_pip_stat11_prtx_s cn52xxp1; + struct cvmx_pip_stat11_prtx_s cn56xx; + struct cvmx_pip_stat11_prtx_s cn56xxp1; + struct cvmx_pip_stat11_prtx_s cn61xx; + struct cvmx_pip_stat11_prtx_s cn63xx; + struct cvmx_pip_stat11_prtx_s cn63xxp1; + struct cvmx_pip_stat11_prtx_s cn66xx; + struct cvmx_pip_stat11_prtx_s cnf71xx; +}; + +union cvmx_pip_stat1_x { + uint64_t u64; + struct cvmx_pip_stat1_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t octs:48; +#else + uint64_t octs:48; + uint64_t reserved_48_63:16; +#endif + } s; + struct cvmx_pip_stat1_x_s cn68xx; + struct cvmx_pip_stat1_x_s cn68xxp1; }; union cvmx_pip_stat1_prtx { uint64_t u64; struct cvmx_pip_stat1_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t octs:48; +#else + uint64_t octs:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_pip_stat1_prtx_s cn30xx; struct cvmx_pip_stat1_prtx_s cn31xx; @@ -956,13 +2531,38 @@ union cvmx_pip_stat1_prtx { struct cvmx_pip_stat1_prtx_s cn56xxp1; struct cvmx_pip_stat1_prtx_s cn58xx; struct cvmx_pip_stat1_prtx_s cn58xxp1; + struct cvmx_pip_stat1_prtx_s cn61xx; + struct cvmx_pip_stat1_prtx_s cn63xx; + struct cvmx_pip_stat1_prtx_s cn63xxp1; + struct cvmx_pip_stat1_prtx_s cn66xx; + struct cvmx_pip_stat1_prtx_s cnf71xx; +}; + +union cvmx_pip_stat2_x { + uint64_t u64; + struct cvmx_pip_stat2_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t pkts:32; + uint64_t raw:32; +#else + uint64_t raw:32; + uint64_t pkts:32; +#endif + } s; + struct cvmx_pip_stat2_x_s cn68xx; + struct cvmx_pip_stat2_x_s cn68xxp1; }; union cvmx_pip_stat2_prtx { uint64_t u64; struct cvmx_pip_stat2_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t pkts:32; uint64_t raw:32; +#else + uint64_t raw:32; + uint64_t pkts:32; +#endif } s; struct cvmx_pip_stat2_prtx_s cn30xx; struct cvmx_pip_stat2_prtx_s cn31xx; @@ -975,13 +2575,38 @@ union cvmx_pip_stat2_prtx { struct cvmx_pip_stat2_prtx_s cn56xxp1; struct cvmx_pip_stat2_prtx_s cn58xx; struct cvmx_pip_stat2_prtx_s cn58xxp1; + struct cvmx_pip_stat2_prtx_s cn61xx; + struct cvmx_pip_stat2_prtx_s cn63xx; + struct cvmx_pip_stat2_prtx_s cn63xxp1; + struct cvmx_pip_stat2_prtx_s cn66xx; + struct cvmx_pip_stat2_prtx_s cnf71xx; +}; + +union cvmx_pip_stat3_x { + uint64_t u64; + struct cvmx_pip_stat3_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bcst:32; + uint64_t mcst:32; +#else + uint64_t mcst:32; + uint64_t bcst:32; +#endif + } s; + struct cvmx_pip_stat3_x_s cn68xx; + struct cvmx_pip_stat3_x_s cn68xxp1; }; union cvmx_pip_stat3_prtx { uint64_t u64; struct cvmx_pip_stat3_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t bcst:32; uint64_t mcst:32; +#else + uint64_t mcst:32; + uint64_t bcst:32; +#endif } s; struct cvmx_pip_stat3_prtx_s cn30xx; struct cvmx_pip_stat3_prtx_s cn31xx; @@ -994,13 +2619,38 @@ union cvmx_pip_stat3_prtx { struct cvmx_pip_stat3_prtx_s cn56xxp1; struct cvmx_pip_stat3_prtx_s cn58xx; struct cvmx_pip_stat3_prtx_s cn58xxp1; + struct cvmx_pip_stat3_prtx_s cn61xx; + struct cvmx_pip_stat3_prtx_s cn63xx; + struct cvmx_pip_stat3_prtx_s cn63xxp1; + struct cvmx_pip_stat3_prtx_s cn66xx; + struct cvmx_pip_stat3_prtx_s cnf71xx; +}; + +union cvmx_pip_stat4_x { + uint64_t u64; + struct cvmx_pip_stat4_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t h65to127:32; + uint64_t h64:32; +#else + uint64_t h64:32; + uint64_t h65to127:32; +#endif + } s; + struct cvmx_pip_stat4_x_s cn68xx; + struct cvmx_pip_stat4_x_s cn68xxp1; }; union cvmx_pip_stat4_prtx { uint64_t u64; struct cvmx_pip_stat4_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t h65to127:32; uint64_t h64:32; +#else + uint64_t h64:32; + uint64_t h65to127:32; +#endif } s; struct cvmx_pip_stat4_prtx_s cn30xx; struct cvmx_pip_stat4_prtx_s cn31xx; @@ -1013,13 +2663,38 @@ union cvmx_pip_stat4_prtx { struct cvmx_pip_stat4_prtx_s cn56xxp1; struct cvmx_pip_stat4_prtx_s cn58xx; struct cvmx_pip_stat4_prtx_s cn58xxp1; + struct cvmx_pip_stat4_prtx_s cn61xx; + struct cvmx_pip_stat4_prtx_s cn63xx; + struct cvmx_pip_stat4_prtx_s cn63xxp1; + struct cvmx_pip_stat4_prtx_s cn66xx; + struct cvmx_pip_stat4_prtx_s cnf71xx; +}; + +union cvmx_pip_stat5_x { + uint64_t u64; + struct cvmx_pip_stat5_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t h256to511:32; + uint64_t h128to255:32; +#else + uint64_t h128to255:32; + uint64_t h256to511:32; +#endif + } s; + struct cvmx_pip_stat5_x_s cn68xx; + struct cvmx_pip_stat5_x_s cn68xxp1; }; union cvmx_pip_stat5_prtx { uint64_t u64; struct cvmx_pip_stat5_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t h256to511:32; uint64_t h128to255:32; +#else + uint64_t h128to255:32; + uint64_t h256to511:32; +#endif } s; struct cvmx_pip_stat5_prtx_s cn30xx; struct cvmx_pip_stat5_prtx_s cn31xx; @@ -1032,13 +2707,38 @@ union cvmx_pip_stat5_prtx { struct cvmx_pip_stat5_prtx_s cn56xxp1; struct cvmx_pip_stat5_prtx_s cn58xx; struct cvmx_pip_stat5_prtx_s cn58xxp1; + struct cvmx_pip_stat5_prtx_s cn61xx; + struct cvmx_pip_stat5_prtx_s cn63xx; + struct cvmx_pip_stat5_prtx_s cn63xxp1; + struct cvmx_pip_stat5_prtx_s cn66xx; + struct cvmx_pip_stat5_prtx_s cnf71xx; +}; + +union cvmx_pip_stat6_x { + uint64_t u64; + struct cvmx_pip_stat6_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t h1024to1518:32; + uint64_t h512to1023:32; +#else + uint64_t h512to1023:32; + uint64_t h1024to1518:32; +#endif + } s; + struct cvmx_pip_stat6_x_s cn68xx; + struct cvmx_pip_stat6_x_s cn68xxp1; }; union cvmx_pip_stat6_prtx { uint64_t u64; struct cvmx_pip_stat6_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t h1024to1518:32; uint64_t h512to1023:32; +#else + uint64_t h512to1023:32; + uint64_t h1024to1518:32; +#endif } s; struct cvmx_pip_stat6_prtx_s cn30xx; struct cvmx_pip_stat6_prtx_s cn31xx; @@ -1051,13 +2751,38 @@ union cvmx_pip_stat6_prtx { struct cvmx_pip_stat6_prtx_s cn56xxp1; struct cvmx_pip_stat6_prtx_s cn58xx; struct cvmx_pip_stat6_prtx_s cn58xxp1; + struct cvmx_pip_stat6_prtx_s cn61xx; + struct cvmx_pip_stat6_prtx_s cn63xx; + struct cvmx_pip_stat6_prtx_s cn63xxp1; + struct cvmx_pip_stat6_prtx_s cn66xx; + struct cvmx_pip_stat6_prtx_s cnf71xx; +}; + +union cvmx_pip_stat7_x { + uint64_t u64; + struct cvmx_pip_stat7_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t fcs:32; + uint64_t h1519:32; +#else + uint64_t h1519:32; + uint64_t fcs:32; +#endif + } s; + struct cvmx_pip_stat7_x_s cn68xx; + struct cvmx_pip_stat7_x_s cn68xxp1; }; union cvmx_pip_stat7_prtx { uint64_t u64; struct cvmx_pip_stat7_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t fcs:32; uint64_t h1519:32; +#else + uint64_t h1519:32; + uint64_t fcs:32; +#endif } s; struct cvmx_pip_stat7_prtx_s cn30xx; struct cvmx_pip_stat7_prtx_s cn31xx; @@ -1070,13 +2795,38 @@ union cvmx_pip_stat7_prtx { struct cvmx_pip_stat7_prtx_s cn56xxp1; struct cvmx_pip_stat7_prtx_s cn58xx; struct cvmx_pip_stat7_prtx_s cn58xxp1; + struct cvmx_pip_stat7_prtx_s cn61xx; + struct cvmx_pip_stat7_prtx_s cn63xx; + struct cvmx_pip_stat7_prtx_s cn63xxp1; + struct cvmx_pip_stat7_prtx_s cn66xx; + struct cvmx_pip_stat7_prtx_s cnf71xx; +}; + +union cvmx_pip_stat8_x { + uint64_t u64; + struct cvmx_pip_stat8_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t frag:32; + uint64_t undersz:32; +#else + uint64_t undersz:32; + uint64_t frag:32; +#endif + } s; + struct cvmx_pip_stat8_x_s cn68xx; + struct cvmx_pip_stat8_x_s cn68xxp1; }; union cvmx_pip_stat8_prtx { uint64_t u64; struct cvmx_pip_stat8_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t frag:32; uint64_t undersz:32; +#else + uint64_t undersz:32; + uint64_t frag:32; +#endif } s; struct cvmx_pip_stat8_prtx_s cn30xx; struct cvmx_pip_stat8_prtx_s cn31xx; @@ -1089,13 +2839,38 @@ union cvmx_pip_stat8_prtx { struct cvmx_pip_stat8_prtx_s cn56xxp1; struct cvmx_pip_stat8_prtx_s cn58xx; struct cvmx_pip_stat8_prtx_s cn58xxp1; + struct cvmx_pip_stat8_prtx_s cn61xx; + struct cvmx_pip_stat8_prtx_s cn63xx; + struct cvmx_pip_stat8_prtx_s cn63xxp1; + struct cvmx_pip_stat8_prtx_s cn66xx; + struct cvmx_pip_stat8_prtx_s cnf71xx; +}; + +union cvmx_pip_stat9_x { + uint64_t u64; + struct cvmx_pip_stat9_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t jabber:32; + uint64_t oversz:32; +#else + uint64_t oversz:32; + uint64_t jabber:32; +#endif + } s; + struct cvmx_pip_stat9_x_s cn68xx; + struct cvmx_pip_stat9_x_s cn68xxp1; }; union cvmx_pip_stat9_prtx { uint64_t u64; struct cvmx_pip_stat9_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t jabber:32; uint64_t oversz:32; +#else + uint64_t oversz:32; + uint64_t jabber:32; +#endif } s; struct cvmx_pip_stat9_prtx_s cn30xx; struct cvmx_pip_stat9_prtx_s cn31xx; @@ -1108,32 +2883,66 @@ union cvmx_pip_stat9_prtx { struct cvmx_pip_stat9_prtx_s cn56xxp1; struct cvmx_pip_stat9_prtx_s cn58xx; struct cvmx_pip_stat9_prtx_s cn58xxp1; + struct cvmx_pip_stat9_prtx_s cn61xx; + struct cvmx_pip_stat9_prtx_s cn63xx; + struct cvmx_pip_stat9_prtx_s cn63xxp1; + struct cvmx_pip_stat9_prtx_s cn66xx; + struct cvmx_pip_stat9_prtx_s cnf71xx; }; union cvmx_pip_stat_ctl { uint64_t u64; struct cvmx_pip_stat_ctl_s { - uint64_t reserved_1_63:63; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_9_63:55; + uint64_t mode:1; + uint64_t reserved_1_7:7; + uint64_t rdclr:1; +#else uint64_t rdclr:1; + uint64_t reserved_1_7:7; + uint64_t mode:1; + uint64_t reserved_9_63:55; +#endif } s; - struct cvmx_pip_stat_ctl_s cn30xx; - struct cvmx_pip_stat_ctl_s cn31xx; - struct cvmx_pip_stat_ctl_s cn38xx; - struct cvmx_pip_stat_ctl_s cn38xxp2; - struct cvmx_pip_stat_ctl_s cn50xx; - struct cvmx_pip_stat_ctl_s cn52xx; - struct cvmx_pip_stat_ctl_s cn52xxp1; - struct cvmx_pip_stat_ctl_s cn56xx; - struct cvmx_pip_stat_ctl_s cn56xxp1; - struct cvmx_pip_stat_ctl_s cn58xx; - struct cvmx_pip_stat_ctl_s cn58xxp1; + struct cvmx_pip_stat_ctl_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_1_63:63; + uint64_t rdclr:1; +#else + uint64_t rdclr:1; + uint64_t reserved_1_63:63; +#endif + } cn30xx; + struct cvmx_pip_stat_ctl_cn30xx cn31xx; + struct cvmx_pip_stat_ctl_cn30xx cn38xx; + struct cvmx_pip_stat_ctl_cn30xx cn38xxp2; + struct cvmx_pip_stat_ctl_cn30xx cn50xx; + struct cvmx_pip_stat_ctl_cn30xx cn52xx; + struct cvmx_pip_stat_ctl_cn30xx cn52xxp1; + struct cvmx_pip_stat_ctl_cn30xx cn56xx; + struct cvmx_pip_stat_ctl_cn30xx cn56xxp1; + struct cvmx_pip_stat_ctl_cn30xx cn58xx; + struct cvmx_pip_stat_ctl_cn30xx cn58xxp1; + struct cvmx_pip_stat_ctl_cn30xx cn61xx; + struct cvmx_pip_stat_ctl_cn30xx cn63xx; + struct cvmx_pip_stat_ctl_cn30xx cn63xxp1; + struct cvmx_pip_stat_ctl_cn30xx cn66xx; + struct cvmx_pip_stat_ctl_s cn68xx; + struct cvmx_pip_stat_ctl_s cn68xxp1; + struct cvmx_pip_stat_ctl_cn30xx cnf71xx; }; union cvmx_pip_stat_inb_errsx { uint64_t u64; struct cvmx_pip_stat_inb_errsx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t errs:16; +#else + uint64_t errs:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pip_stat_inb_errsx_s cn30xx; struct cvmx_pip_stat_inb_errsx_s cn31xx; @@ -1146,13 +2955,38 @@ union cvmx_pip_stat_inb_errsx { struct cvmx_pip_stat_inb_errsx_s cn56xxp1; struct cvmx_pip_stat_inb_errsx_s cn58xx; struct cvmx_pip_stat_inb_errsx_s cn58xxp1; + struct cvmx_pip_stat_inb_errsx_s cn61xx; + struct cvmx_pip_stat_inb_errsx_s cn63xx; + struct cvmx_pip_stat_inb_errsx_s cn63xxp1; + struct cvmx_pip_stat_inb_errsx_s cn66xx; + struct cvmx_pip_stat_inb_errsx_s cnf71xx; +}; + +union cvmx_pip_stat_inb_errs_pkndx { + uint64_t u64; + struct cvmx_pip_stat_inb_errs_pkndx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t errs:16; +#else + uint64_t errs:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_pip_stat_inb_errs_pkndx_s cn68xx; + struct cvmx_pip_stat_inb_errs_pkndx_s cn68xxp1; }; union cvmx_pip_stat_inb_octsx { uint64_t u64; struct cvmx_pip_stat_inb_octsx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t octs:48; +#else + uint64_t octs:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_pip_stat_inb_octsx_s cn30xx; struct cvmx_pip_stat_inb_octsx_s cn31xx; @@ -1165,13 +2999,38 @@ union cvmx_pip_stat_inb_octsx { struct cvmx_pip_stat_inb_octsx_s cn56xxp1; struct cvmx_pip_stat_inb_octsx_s cn58xx; struct cvmx_pip_stat_inb_octsx_s cn58xxp1; + struct cvmx_pip_stat_inb_octsx_s cn61xx; + struct cvmx_pip_stat_inb_octsx_s cn63xx; + struct cvmx_pip_stat_inb_octsx_s cn63xxp1; + struct cvmx_pip_stat_inb_octsx_s cn66xx; + struct cvmx_pip_stat_inb_octsx_s cnf71xx; +}; + +union cvmx_pip_stat_inb_octs_pkndx { + uint64_t u64; + struct cvmx_pip_stat_inb_octs_pkndx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t octs:48; +#else + uint64_t octs:48; + uint64_t reserved_48_63:16; +#endif + } s; + struct cvmx_pip_stat_inb_octs_pkndx_s cn68xx; + struct cvmx_pip_stat_inb_octs_pkndx_s cn68xxp1; }; union cvmx_pip_stat_inb_pktsx { uint64_t u64; struct cvmx_pip_stat_inb_pktsx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pkts:32; +#else + uint64_t pkts:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pip_stat_inb_pktsx_s cn30xx; struct cvmx_pip_stat_inb_pktsx_s cn31xx; @@ -1184,13 +3043,51 @@ union cvmx_pip_stat_inb_pktsx { struct cvmx_pip_stat_inb_pktsx_s cn56xxp1; struct cvmx_pip_stat_inb_pktsx_s cn58xx; struct cvmx_pip_stat_inb_pktsx_s cn58xxp1; + struct cvmx_pip_stat_inb_pktsx_s cn61xx; + struct cvmx_pip_stat_inb_pktsx_s cn63xx; + struct cvmx_pip_stat_inb_pktsx_s cn63xxp1; + struct cvmx_pip_stat_inb_pktsx_s cn66xx; + struct cvmx_pip_stat_inb_pktsx_s cnf71xx; +}; + +union cvmx_pip_stat_inb_pkts_pkndx { + uint64_t u64; + struct cvmx_pip_stat_inb_pkts_pkndx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t pkts:32; +#else + uint64_t pkts:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_pip_stat_inb_pkts_pkndx_s cn68xx; + struct cvmx_pip_stat_inb_pkts_pkndx_s cn68xxp1; +}; + +union cvmx_pip_sub_pkind_fcsx { + uint64_t u64; + struct cvmx_pip_sub_pkind_fcsx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t port_bit:64; +#else + uint64_t port_bit:64; +#endif + } s; + struct cvmx_pip_sub_pkind_fcsx_s cn68xx; + struct cvmx_pip_sub_pkind_fcsx_s cn68xxp1; }; union cvmx_pip_tag_incx { uint64_t u64; struct cvmx_pip_tag_incx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t en:8; +#else + uint64_t en:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_pip_tag_incx_s cn30xx; struct cvmx_pip_tag_incx_s cn31xx; @@ -1203,13 +3100,25 @@ union cvmx_pip_tag_incx { struct cvmx_pip_tag_incx_s cn56xxp1; struct cvmx_pip_tag_incx_s cn58xx; struct cvmx_pip_tag_incx_s cn58xxp1; + struct cvmx_pip_tag_incx_s cn61xx; + struct cvmx_pip_tag_incx_s cn63xx; + struct cvmx_pip_tag_incx_s cn63xxp1; + struct cvmx_pip_tag_incx_s cn66xx; + struct cvmx_pip_tag_incx_s cn68xx; + struct cvmx_pip_tag_incx_s cn68xxp1; + struct cvmx_pip_tag_incx_s cnf71xx; }; union cvmx_pip_tag_mask { uint64_t u64; struct cvmx_pip_tag_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t mask:16; +#else + uint64_t mask:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pip_tag_mask_s cn30xx; struct cvmx_pip_tag_mask_s cn31xx; @@ -1222,14 +3131,27 @@ union cvmx_pip_tag_mask { struct cvmx_pip_tag_mask_s cn56xxp1; struct cvmx_pip_tag_mask_s cn58xx; struct cvmx_pip_tag_mask_s cn58xxp1; + struct cvmx_pip_tag_mask_s cn61xx; + struct cvmx_pip_tag_mask_s cn63xx; + struct cvmx_pip_tag_mask_s cn63xxp1; + struct cvmx_pip_tag_mask_s cn66xx; + struct cvmx_pip_tag_mask_s cn68xx; + struct cvmx_pip_tag_mask_s cn68xxp1; + struct cvmx_pip_tag_mask_s cnf71xx; }; union cvmx_pip_tag_secret { uint64_t u64; struct cvmx_pip_tag_secret_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t dst:16; uint64_t src:16; +#else + uint64_t src:16; + uint64_t dst:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pip_tag_secret_s cn30xx; struct cvmx_pip_tag_secret_s cn31xx; @@ -1242,14 +3164,27 @@ union cvmx_pip_tag_secret { struct cvmx_pip_tag_secret_s cn56xxp1; struct cvmx_pip_tag_secret_s cn58xx; struct cvmx_pip_tag_secret_s cn58xxp1; + struct cvmx_pip_tag_secret_s cn61xx; + struct cvmx_pip_tag_secret_s cn63xx; + struct cvmx_pip_tag_secret_s cn63xxp1; + struct cvmx_pip_tag_secret_s cn66xx; + struct cvmx_pip_tag_secret_s cn68xx; + struct cvmx_pip_tag_secret_s cn68xxp1; + struct cvmx_pip_tag_secret_s cnf71xx; }; union cvmx_pip_todo_entry { uint64_t u64; struct cvmx_pip_todo_entry_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t val:1; uint64_t reserved_62_62:1; uint64_t entry:62; +#else + uint64_t entry:62; + uint64_t reserved_62_62:1; + uint64_t val:1; +#endif } s; struct cvmx_pip_todo_entry_s cn30xx; struct cvmx_pip_todo_entry_s cn31xx; @@ -1262,6 +3197,226 @@ union cvmx_pip_todo_entry { struct cvmx_pip_todo_entry_s cn56xxp1; struct cvmx_pip_todo_entry_s cn58xx; struct cvmx_pip_todo_entry_s cn58xxp1; + struct cvmx_pip_todo_entry_s cn61xx; + struct cvmx_pip_todo_entry_s cn63xx; + struct cvmx_pip_todo_entry_s cn63xxp1; + struct cvmx_pip_todo_entry_s cn66xx; + struct cvmx_pip_todo_entry_s cn68xx; + struct cvmx_pip_todo_entry_s cn68xxp1; + struct cvmx_pip_todo_entry_s cnf71xx; +}; + +union cvmx_pip_vlan_etypesx { + uint64_t u64; + struct cvmx_pip_vlan_etypesx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t type3:16; + uint64_t type2:16; + uint64_t type1:16; + uint64_t type0:16; +#else + uint64_t type0:16; + uint64_t type1:16; + uint64_t type2:16; + uint64_t type3:16; +#endif + } s; + struct cvmx_pip_vlan_etypesx_s cn61xx; + struct cvmx_pip_vlan_etypesx_s cn66xx; + struct cvmx_pip_vlan_etypesx_s cn68xx; + struct cvmx_pip_vlan_etypesx_s cnf71xx; +}; + +union cvmx_pip_xstat0_prtx { + uint64_t u64; + struct cvmx_pip_xstat0_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t drp_pkts:32; + uint64_t drp_octs:32; +#else + uint64_t drp_octs:32; + uint64_t drp_pkts:32; +#endif + } s; + struct cvmx_pip_xstat0_prtx_s cn63xx; + struct cvmx_pip_xstat0_prtx_s cn63xxp1; + struct cvmx_pip_xstat0_prtx_s cn66xx; +}; + +union cvmx_pip_xstat10_prtx { + uint64_t u64; + struct cvmx_pip_xstat10_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bcast:32; + uint64_t mcast:32; +#else + uint64_t mcast:32; + uint64_t bcast:32; +#endif + } s; + struct cvmx_pip_xstat10_prtx_s cn63xx; + struct cvmx_pip_xstat10_prtx_s cn63xxp1; + struct cvmx_pip_xstat10_prtx_s cn66xx; +}; + +union cvmx_pip_xstat11_prtx { + uint64_t u64; + struct cvmx_pip_xstat11_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bcast:32; + uint64_t mcast:32; +#else + uint64_t mcast:32; + uint64_t bcast:32; +#endif + } s; + struct cvmx_pip_xstat11_prtx_s cn63xx; + struct cvmx_pip_xstat11_prtx_s cn63xxp1; + struct cvmx_pip_xstat11_prtx_s cn66xx; +}; + +union cvmx_pip_xstat1_prtx { + uint64_t u64; + struct cvmx_pip_xstat1_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t octs:48; +#else + uint64_t octs:48; + uint64_t reserved_48_63:16; +#endif + } s; + struct cvmx_pip_xstat1_prtx_s cn63xx; + struct cvmx_pip_xstat1_prtx_s cn63xxp1; + struct cvmx_pip_xstat1_prtx_s cn66xx; +}; + +union cvmx_pip_xstat2_prtx { + uint64_t u64; + struct cvmx_pip_xstat2_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t pkts:32; + uint64_t raw:32; +#else + uint64_t raw:32; + uint64_t pkts:32; +#endif + } s; + struct cvmx_pip_xstat2_prtx_s cn63xx; + struct cvmx_pip_xstat2_prtx_s cn63xxp1; + struct cvmx_pip_xstat2_prtx_s cn66xx; +}; + +union cvmx_pip_xstat3_prtx { + uint64_t u64; + struct cvmx_pip_xstat3_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t bcst:32; + uint64_t mcst:32; +#else + uint64_t mcst:32; + uint64_t bcst:32; +#endif + } s; + struct cvmx_pip_xstat3_prtx_s cn63xx; + struct cvmx_pip_xstat3_prtx_s cn63xxp1; + struct cvmx_pip_xstat3_prtx_s cn66xx; +}; + +union cvmx_pip_xstat4_prtx { + uint64_t u64; + struct cvmx_pip_xstat4_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t h65to127:32; + uint64_t h64:32; +#else + uint64_t h64:32; + uint64_t h65to127:32; +#endif + } s; + struct cvmx_pip_xstat4_prtx_s cn63xx; + struct cvmx_pip_xstat4_prtx_s cn63xxp1; + struct cvmx_pip_xstat4_prtx_s cn66xx; +}; + +union cvmx_pip_xstat5_prtx { + uint64_t u64; + struct cvmx_pip_xstat5_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t h256to511:32; + uint64_t h128to255:32; +#else + uint64_t h128to255:32; + uint64_t h256to511:32; +#endif + } s; + struct cvmx_pip_xstat5_prtx_s cn63xx; + struct cvmx_pip_xstat5_prtx_s cn63xxp1; + struct cvmx_pip_xstat5_prtx_s cn66xx; +}; + +union cvmx_pip_xstat6_prtx { + uint64_t u64; + struct cvmx_pip_xstat6_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t h1024to1518:32; + uint64_t h512to1023:32; +#else + uint64_t h512to1023:32; + uint64_t h1024to1518:32; +#endif + } s; + struct cvmx_pip_xstat6_prtx_s cn63xx; + struct cvmx_pip_xstat6_prtx_s cn63xxp1; + struct cvmx_pip_xstat6_prtx_s cn66xx; +}; + +union cvmx_pip_xstat7_prtx { + uint64_t u64; + struct cvmx_pip_xstat7_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t fcs:32; + uint64_t h1519:32; +#else + uint64_t h1519:32; + uint64_t fcs:32; +#endif + } s; + struct cvmx_pip_xstat7_prtx_s cn63xx; + struct cvmx_pip_xstat7_prtx_s cn63xxp1; + struct cvmx_pip_xstat7_prtx_s cn66xx; +}; + +union cvmx_pip_xstat8_prtx { + uint64_t u64; + struct cvmx_pip_xstat8_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t frag:32; + uint64_t undersz:32; +#else + uint64_t undersz:32; + uint64_t frag:32; +#endif + } s; + struct cvmx_pip_xstat8_prtx_s cn63xx; + struct cvmx_pip_xstat8_prtx_s cn63xxp1; + struct cvmx_pip_xstat8_prtx_s cn66xx; +}; + +union cvmx_pip_xstat9_prtx { + uint64_t u64; + struct cvmx_pip_xstat9_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t jabber:32; + uint64_t oversz:32; +#else + uint64_t oversz:32; + uint64_t jabber:32; +#endif + } s; + struct cvmx_pip_xstat9_prtx_s cn63xx; + struct cvmx_pip_xstat9_prtx_s cn63xxp1; + struct cvmx_pip_xstat9_prtx_s cn66xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-pip.h b/arch/mips/include/asm/octeon/cvmx-pip.h index 78dbce8f2c5..df69bfd2b00 100644 --- a/arch/mips/include/asm/octeon/cvmx-pip.h +++ b/arch/mips/include/asm/octeon/cvmx-pip.h @@ -33,12 +33,12 @@ #ifndef __CVMX_PIP_H__ #define __CVMX_PIP_H__ -#include "cvmx-wqe.h" -#include "cvmx-fpa.h" -#include "cvmx-pip-defs.h" +#include <asm/octeon/cvmx-wqe.h> +#include <asm/octeon/cvmx-fpa.h> +#include <asm/octeon/cvmx-pip-defs.h> -#define CVMX_PIP_NUM_INPUT_PORTS 40 -#define CVMX_PIP_NUM_WATCHERS 4 +#define CVMX_PIP_NUM_INPUT_PORTS 40 +#define CVMX_PIP_NUM_WATCHERS 4 /* * Encodes the different error and exception codes @@ -92,10 +92,10 @@ typedef enum { /** * NOTES - * late collision (data received before collision) - * late collisions cannot be detected by the receiver - * they would appear as JAM bits which would appear as bad FCS - * or carrier extend error which is CVMX_PIP_EXTEND_ERR + * late collision (data received before collision) + * late collisions cannot be detected by the receiver + * they would appear as JAM bits which would appear as bad FCS + * or carrier extend error which is CVMX_PIP_EXTEND_ERR */ typedef enum { /* No error */ @@ -122,11 +122,11 @@ typedef enum { * error) */ CVMX_PIP_UNDER_FCS_ERR = 6ull, - /* RGM 7 = FCS error */ + /* RGM 7 = FCS error */ CVMX_PIP_GMX_FCS_ERR = 7ull, /* RGM+SPI 8 = min frame error (pkt len < min frame len) */ CVMX_PIP_UNDER_ERR = 8ull, - /* RGM 9 = Frame carrier extend error */ + /* RGM 9 = Frame carrier extend error */ CVMX_PIP_EXTEND_ERR = 9ull, /* * RGM 10 = length mismatch (len did not match len in L2 @@ -161,10 +161,10 @@ typedef enum { CVMX_PIP_PIP_L2_MAL_HDR = 18L /* * NOTES: xx = late collision (data received before collision) - * late collisions cannot be detected by the receiver - * they would appear as JAM bits which would appear as - * bad FCS or carrier extend error which is - * CVMX_PIP_EXTEND_ERR + * late collisions cannot be detected by the receiver + * they would appear as JAM bits which would appear as + * bad FCS or carrier extend error which is + * CVMX_PIP_EXTEND_ERR */ } cvmx_pip_rcv_err_t; @@ -192,13 +192,13 @@ typedef struct { /* Number of packets processed by PIP */ uint32_t packets; /* - * Number of indentified L2 multicast packets. Does not + * Number of identified L2 multicast packets. Does not * include broadcast packets. Only includes packets whose * parse mode is SKIP_TO_L2 */ uint32_t multicast_packets; /* - * Number of indentified L2 broadcast packets. Does not + * Number of identified L2 broadcast packets. Does not * include multicast packets. Only includes packets whose * parse mode is SKIP_TO_L2 */ @@ -287,7 +287,7 @@ typedef union { * @port_num: Port number to configure * @port_cfg: Port hardware configuration * @port_tag_cfg: - * Port POW tagging configuration + * Port POW tagging configuration */ static inline void cvmx_pip_config_port(uint64_t port_num, union cvmx_pip_prt_cfgx port_cfg, @@ -298,20 +298,20 @@ static inline void cvmx_pip_config_port(uint64_t port_num, } #if 0 /** - * @deprecated This function is a thin wrapper around the Pass1 version - * of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for - * setting the group that is incompatible with this function, - * the preferred upgrade path is to use the CSR directly. + * @deprecated This function is a thin wrapper around the Pass1 version + * of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for + * setting the group that is incompatible with this function, + * the preferred upgrade path is to use the CSR directly. * * Configure the global QoS packet watchers. Each watcher is * capable of matching a field in a packet to determine the * QoS queue for scheduling. * - * @watcher: Watcher number to configure (0 - 3). + * @watcher: Watcher number to configure (0 - 3). * @match_type: Watcher match type * @match_value: - * Value the watcher will match against - * @qos: QoS queue for packets matching this watcher + * Value the watcher will match against + * @qos: QoS queue for packets matching this watcher */ static inline void cvmx_pip_config_watcher(uint64_t watcher, cvmx_pip_qos_watch_types match_type, @@ -331,7 +331,7 @@ static inline void cvmx_pip_config_watcher(uint64_t watcher, * Configure the VLAN priority to QoS queue mapping. * * @vlan_priority: - * VLAN priority (0-7) + * VLAN priority (0-7) * @qos: QoS queue for packets matching this watcher */ static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority, @@ -451,10 +451,10 @@ static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear, * * @interface: Interface to configure (0 or 1) * @invert_result: - * Invert the result of the CRC + * Invert the result of the CRC * @reflect: Reflect * @initialization_vector: - * CRC initialization vector + * CRC initialization vector */ static inline void cvmx_pip_config_crc(uint64_t interface, uint64_t invert_result, uint64_t reflect, @@ -500,13 +500,13 @@ static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index) * * @mask_index: Which tag mask to modify (0..3) * @offset: Offset into the bitmask to set bits at. Use the GCC macro - * offsetof() to determine the offsets into packet headers. - * For example, offsetof(ethhdr, protocol) returns the offset - * of the ethernet protocol field. The bitmask selects which - * bytes to include the the tag, with bit offset X selecting - * byte at offset X from the beginning of the packet data. + * offsetof() to determine the offsets into packet headers. + * For example, offsetof(ethhdr, protocol) returns the offset + * of the ethernet protocol field. The bitmask selects which + * bytes to include the the tag, with bit offset X selecting + * byte at offset X from the beginning of the packet data. * @len: Number of bytes to include. Usually this is the sizeof() - * the field. + * the field. */ static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset, uint64_t len) diff --git a/arch/mips/include/asm/octeon/cvmx-pko-defs.h b/arch/mips/include/asm/octeon/cvmx-pko-defs.h index 50e779cf1ad..87c3b970cad 100644 --- a/arch/mips/include/asm/octeon/cvmx-pko-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pko-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,94 +28,74 @@ #ifndef __CVMX_PKO_DEFS_H__ #define __CVMX_PKO_DEFS_H__ -#define CVMX_PKO_MEM_COUNT0 \ - CVMX_ADD_IO_SEG(0x0001180050001080ull) -#define CVMX_PKO_MEM_COUNT1 \ - CVMX_ADD_IO_SEG(0x0001180050001088ull) -#define CVMX_PKO_MEM_DEBUG0 \ - CVMX_ADD_IO_SEG(0x0001180050001100ull) -#define CVMX_PKO_MEM_DEBUG1 \ - CVMX_ADD_IO_SEG(0x0001180050001108ull) -#define CVMX_PKO_MEM_DEBUG10 \ - CVMX_ADD_IO_SEG(0x0001180050001150ull) -#define CVMX_PKO_MEM_DEBUG11 \ - CVMX_ADD_IO_SEG(0x0001180050001158ull) -#define CVMX_PKO_MEM_DEBUG12 \ - CVMX_ADD_IO_SEG(0x0001180050001160ull) -#define CVMX_PKO_MEM_DEBUG13 \ - CVMX_ADD_IO_SEG(0x0001180050001168ull) -#define CVMX_PKO_MEM_DEBUG14 \ - CVMX_ADD_IO_SEG(0x0001180050001170ull) -#define CVMX_PKO_MEM_DEBUG2 \ - CVMX_ADD_IO_SEG(0x0001180050001110ull) -#define CVMX_PKO_MEM_DEBUG3 \ - CVMX_ADD_IO_SEG(0x0001180050001118ull) -#define CVMX_PKO_MEM_DEBUG4 \ - CVMX_ADD_IO_SEG(0x0001180050001120ull) -#define CVMX_PKO_MEM_DEBUG5 \ - CVMX_ADD_IO_SEG(0x0001180050001128ull) -#define CVMX_PKO_MEM_DEBUG6 \ - CVMX_ADD_IO_SEG(0x0001180050001130ull) -#define CVMX_PKO_MEM_DEBUG7 \ - CVMX_ADD_IO_SEG(0x0001180050001138ull) -#define CVMX_PKO_MEM_DEBUG8 \ - CVMX_ADD_IO_SEG(0x0001180050001140ull) -#define CVMX_PKO_MEM_DEBUG9 \ - CVMX_ADD_IO_SEG(0x0001180050001148ull) -#define CVMX_PKO_MEM_PORT_PTRS \ - CVMX_ADD_IO_SEG(0x0001180050001010ull) -#define CVMX_PKO_MEM_PORT_QOS \ - CVMX_ADD_IO_SEG(0x0001180050001018ull) -#define CVMX_PKO_MEM_PORT_RATE0 \ - CVMX_ADD_IO_SEG(0x0001180050001020ull) -#define CVMX_PKO_MEM_PORT_RATE1 \ - CVMX_ADD_IO_SEG(0x0001180050001028ull) -#define CVMX_PKO_MEM_QUEUE_PTRS \ - CVMX_ADD_IO_SEG(0x0001180050001000ull) -#define CVMX_PKO_MEM_QUEUE_QOS \ - CVMX_ADD_IO_SEG(0x0001180050001008ull) -#define CVMX_PKO_REG_BIST_RESULT \ - CVMX_ADD_IO_SEG(0x0001180050000080ull) -#define CVMX_PKO_REG_CMD_BUF \ - CVMX_ADD_IO_SEG(0x0001180050000010ull) -#define CVMX_PKO_REG_CRC_CTLX(offset) \ - CVMX_ADD_IO_SEG(0x0001180050000028ull + (((offset) & 1) * 8)) -#define CVMX_PKO_REG_CRC_ENABLE \ - CVMX_ADD_IO_SEG(0x0001180050000020ull) -#define CVMX_PKO_REG_CRC_IVX(offset) \ - CVMX_ADD_IO_SEG(0x0001180050000038ull + (((offset) & 1) * 8)) -#define CVMX_PKO_REG_DEBUG0 \ - CVMX_ADD_IO_SEG(0x0001180050000098ull) -#define CVMX_PKO_REG_DEBUG1 \ - CVMX_ADD_IO_SEG(0x00011800500000A0ull) -#define CVMX_PKO_REG_DEBUG2 \ - CVMX_ADD_IO_SEG(0x00011800500000A8ull) -#define CVMX_PKO_REG_DEBUG3 \ - CVMX_ADD_IO_SEG(0x00011800500000B0ull) -#define CVMX_PKO_REG_ENGINE_INFLIGHT \ - CVMX_ADD_IO_SEG(0x0001180050000050ull) -#define CVMX_PKO_REG_ENGINE_THRESH \ - CVMX_ADD_IO_SEG(0x0001180050000058ull) -#define CVMX_PKO_REG_ERROR \ - CVMX_ADD_IO_SEG(0x0001180050000088ull) -#define CVMX_PKO_REG_FLAGS \ - CVMX_ADD_IO_SEG(0x0001180050000000ull) -#define CVMX_PKO_REG_GMX_PORT_MODE \ - CVMX_ADD_IO_SEG(0x0001180050000018ull) -#define CVMX_PKO_REG_INT_MASK \ - CVMX_ADD_IO_SEG(0x0001180050000090ull) -#define CVMX_PKO_REG_QUEUE_MODE \ - CVMX_ADD_IO_SEG(0x0001180050000048ull) -#define CVMX_PKO_REG_QUEUE_PTRS1 \ - CVMX_ADD_IO_SEG(0x0001180050000100ull) -#define CVMX_PKO_REG_READ_IDX \ - CVMX_ADD_IO_SEG(0x0001180050000008ull) +#define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull)) +#define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull)) +#define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull)) +#define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull)) +#define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull)) +#define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull)) +#define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull)) +#define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull)) +#define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(0x0001180050001170ull)) +#define CVMX_PKO_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180050001110ull)) +#define CVMX_PKO_MEM_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180050001118ull)) +#define CVMX_PKO_MEM_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180050001120ull)) +#define CVMX_PKO_MEM_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180050001128ull)) +#define CVMX_PKO_MEM_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180050001130ull)) +#define CVMX_PKO_MEM_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180050001138ull)) +#define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull)) +#define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull)) +#define CVMX_PKO_MEM_IPORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001030ull)) +#define CVMX_PKO_MEM_IPORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001038ull)) +#define CVMX_PKO_MEM_IQUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001040ull)) +#define CVMX_PKO_MEM_IQUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001048ull)) +#define CVMX_PKO_MEM_PORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001010ull)) +#define CVMX_PKO_MEM_PORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001018ull)) +#define CVMX_PKO_MEM_PORT_RATE0 (CVMX_ADD_IO_SEG(0x0001180050001020ull)) +#define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull)) +#define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull)) +#define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull)) +#define CVMX_PKO_MEM_THROTTLE_INT (CVMX_ADD_IO_SEG(0x0001180050001058ull)) +#define CVMX_PKO_MEM_THROTTLE_PIPE (CVMX_ADD_IO_SEG(0x0001180050001050ull)) +#define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull)) +#define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull)) +#define CVMX_PKO_REG_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8) +#define CVMX_PKO_REG_CRC_ENABLE (CVMX_ADD_IO_SEG(0x0001180050000020ull)) +#define CVMX_PKO_REG_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8) +#define CVMX_PKO_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050000098ull)) +#define CVMX_PKO_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x00011800500000A0ull)) +#define CVMX_PKO_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x00011800500000A8ull)) +#define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull)) +#define CVMX_PKO_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x00011800500000B8ull)) +#define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull)) +#define CVMX_PKO_REG_ENGINE_INFLIGHT1 (CVMX_ADD_IO_SEG(0x0001180050000318ull)) +#define CVMX_PKO_REG_ENGINE_STORAGEX(offset) (CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8) +#define CVMX_PKO_REG_ENGINE_THRESH (CVMX_ADD_IO_SEG(0x0001180050000058ull)) +#define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull)) +#define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull)) +#define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull)) +#define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull)) +#define CVMX_PKO_REG_LOOPBACK_BPID (CVMX_ADD_IO_SEG(0x0001180050000118ull)) +#define CVMX_PKO_REG_LOOPBACK_PKIND (CVMX_ADD_IO_SEG(0x0001180050000068ull)) +#define CVMX_PKO_REG_MIN_PKT (CVMX_ADD_IO_SEG(0x0001180050000070ull)) +#define CVMX_PKO_REG_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000110ull)) +#define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull)) +#define CVMX_PKO_REG_QUEUE_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000108ull)) +#define CVMX_PKO_REG_QUEUE_PTRS1 (CVMX_ADD_IO_SEG(0x0001180050000100ull)) +#define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull)) +#define CVMX_PKO_REG_THROTTLE (CVMX_ADD_IO_SEG(0x0001180050000078ull)) +#define CVMX_PKO_REG_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001180050000060ull)) union cvmx_pko_mem_count0 { uint64_t u64; struct cvmx_pko_mem_count0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t count:32; +#else + uint64_t count:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pko_mem_count0_s cn30xx; struct cvmx_pko_mem_count0_s cn31xx; @@ -128,13 +108,25 @@ union cvmx_pko_mem_count0 { struct cvmx_pko_mem_count0_s cn56xxp1; struct cvmx_pko_mem_count0_s cn58xx; struct cvmx_pko_mem_count0_s cn58xxp1; + struct cvmx_pko_mem_count0_s cn61xx; + struct cvmx_pko_mem_count0_s cn63xx; + struct cvmx_pko_mem_count0_s cn63xxp1; + struct cvmx_pko_mem_count0_s cn66xx; + struct cvmx_pko_mem_count0_s cn68xx; + struct cvmx_pko_mem_count0_s cn68xxp1; + struct cvmx_pko_mem_count0_s cnf71xx; }; union cvmx_pko_mem_count1 { uint64_t u64; struct cvmx_pko_mem_count1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t count:48; +#else + uint64_t count:48; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_pko_mem_count1_s cn30xx; struct cvmx_pko_mem_count1_s cn31xx; @@ -147,15 +139,29 @@ union cvmx_pko_mem_count1 { struct cvmx_pko_mem_count1_s cn56xxp1; struct cvmx_pko_mem_count1_s cn58xx; struct cvmx_pko_mem_count1_s cn58xxp1; + struct cvmx_pko_mem_count1_s cn61xx; + struct cvmx_pko_mem_count1_s cn63xx; + struct cvmx_pko_mem_count1_s cn63xxp1; + struct cvmx_pko_mem_count1_s cn66xx; + struct cvmx_pko_mem_count1_s cn68xx; + struct cvmx_pko_mem_count1_s cn68xxp1; + struct cvmx_pko_mem_count1_s cnf71xx; }; union cvmx_pko_mem_debug0 { uint64_t u64; struct cvmx_pko_mem_debug0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t fau:28; uint64_t cmd:14; uint64_t segs:6; uint64_t size:16; +#else + uint64_t size:16; + uint64_t segs:6; + uint64_t cmd:14; + uint64_t fau:28; +#endif } s; struct cvmx_pko_mem_debug0_s cn30xx; struct cvmx_pko_mem_debug0_s cn31xx; @@ -168,16 +174,31 @@ union cvmx_pko_mem_debug0 { struct cvmx_pko_mem_debug0_s cn56xxp1; struct cvmx_pko_mem_debug0_s cn58xx; struct cvmx_pko_mem_debug0_s cn58xxp1; + struct cvmx_pko_mem_debug0_s cn61xx; + struct cvmx_pko_mem_debug0_s cn63xx; + struct cvmx_pko_mem_debug0_s cn63xxp1; + struct cvmx_pko_mem_debug0_s cn66xx; + struct cvmx_pko_mem_debug0_s cn68xx; + struct cvmx_pko_mem_debug0_s cn68xxp1; + struct cvmx_pko_mem_debug0_s cnf71xx; }; union cvmx_pko_mem_debug1 { uint64_t u64; struct cvmx_pko_mem_debug1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t ptr:40; +#else + uint64_t ptr:40; + uint64_t size:16; + uint64_t pool:3; + uint64_t back:4; + uint64_t i:1; +#endif } s; struct cvmx_pko_mem_debug1_s cn30xx; struct cvmx_pko_mem_debug1_s cn31xx; @@ -190,27 +211,52 @@ union cvmx_pko_mem_debug1 { struct cvmx_pko_mem_debug1_s cn56xxp1; struct cvmx_pko_mem_debug1_s cn58xx; struct cvmx_pko_mem_debug1_s cn58xxp1; + struct cvmx_pko_mem_debug1_s cn61xx; + struct cvmx_pko_mem_debug1_s cn63xx; + struct cvmx_pko_mem_debug1_s cn63xxp1; + struct cvmx_pko_mem_debug1_s cn66xx; + struct cvmx_pko_mem_debug1_s cn68xx; + struct cvmx_pko_mem_debug1_s cn68xxp1; + struct cvmx_pko_mem_debug1_s cnf71xx; }; union cvmx_pko_mem_debug10 { uint64_t u64; struct cvmx_pko_mem_debug10_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_mem_debug10_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t fau:28; uint64_t cmd:14; uint64_t segs:6; uint64_t size:16; +#else + uint64_t size:16; + uint64_t segs:6; + uint64_t cmd:14; + uint64_t fau:28; +#endif } cn30xx; struct cvmx_pko_mem_debug10_cn30xx cn31xx; struct cvmx_pko_mem_debug10_cn30xx cn38xx; struct cvmx_pko_mem_debug10_cn30xx cn38xxp2; struct cvmx_pko_mem_debug10_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t ptrs1:17; uint64_t reserved_17_31:15; uint64_t ptrs2:17; +#else + uint64_t ptrs2:17; + uint64_t reserved_17_31:15; + uint64_t ptrs1:17; + uint64_t reserved_49_63:15; +#endif } cn50xx; struct cvmx_pko_mem_debug10_cn50xx cn52xx; struct cvmx_pko_mem_debug10_cn50xx cn52xxp1; @@ -218,28 +264,52 @@ union cvmx_pko_mem_debug10 { struct cvmx_pko_mem_debug10_cn50xx cn56xxp1; struct cvmx_pko_mem_debug10_cn50xx cn58xx; struct cvmx_pko_mem_debug10_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug10_cn50xx cn61xx; + struct cvmx_pko_mem_debug10_cn50xx cn63xx; + struct cvmx_pko_mem_debug10_cn50xx cn63xxp1; + struct cvmx_pko_mem_debug10_cn50xx cn66xx; + struct cvmx_pko_mem_debug10_cn50xx cn68xx; + struct cvmx_pko_mem_debug10_cn50xx cn68xxp1; + struct cvmx_pko_mem_debug10_cn50xx cnf71xx; }; union cvmx_pko_mem_debug11 { uint64_t u64; struct cvmx_pko_mem_debug11_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t reserved_0_39:40; +#else + uint64_t reserved_0_39:40; + uint64_t size:16; + uint64_t pool:3; + uint64_t back:4; + uint64_t i:1; +#endif } s; struct cvmx_pko_mem_debug11_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t ptr:40; +#else + uint64_t ptr:40; + uint64_t size:16; + uint64_t pool:3; + uint64_t back:4; + uint64_t i:1; +#endif } cn30xx; struct cvmx_pko_mem_debug11_cn30xx cn31xx; struct cvmx_pko_mem_debug11_cn30xx cn38xx; struct cvmx_pko_mem_debug11_cn30xx cn38xxp2; struct cvmx_pko_mem_debug11_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t maj:1; uint64_t uid:3; @@ -248,6 +318,16 @@ union cvmx_pko_mem_debug11 { uint64_t chk:1; uint64_t cnt:13; uint64_t mod:3; +#else + uint64_t mod:3; + uint64_t cnt:13; + uint64_t chk:1; + uint64_t len:1; + uint64_t sop:1; + uint64_t uid:3; + uint64_t maj:1; + uint64_t reserved_23_63:41; +#endif } cn50xx; struct cvmx_pko_mem_debug11_cn50xx cn52xx; struct cvmx_pko_mem_debug11_cn50xx cn52xxp1; @@ -255,24 +335,46 @@ union cvmx_pko_mem_debug11 { struct cvmx_pko_mem_debug11_cn50xx cn56xxp1; struct cvmx_pko_mem_debug11_cn50xx cn58xx; struct cvmx_pko_mem_debug11_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug11_cn50xx cn61xx; + struct cvmx_pko_mem_debug11_cn50xx cn63xx; + struct cvmx_pko_mem_debug11_cn50xx cn63xxp1; + struct cvmx_pko_mem_debug11_cn50xx cn66xx; + struct cvmx_pko_mem_debug11_cn50xx cn68xx; + struct cvmx_pko_mem_debug11_cn50xx cn68xxp1; + struct cvmx_pko_mem_debug11_cn50xx cnf71xx; }; union cvmx_pko_mem_debug12 { uint64_t u64; struct cvmx_pko_mem_debug12_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_mem_debug12_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; +#else + uint64_t data:64; +#endif } cn30xx; struct cvmx_pko_mem_debug12_cn30xx cn31xx; struct cvmx_pko_mem_debug12_cn30xx cn38xx; struct cvmx_pko_mem_debug12_cn30xx cn38xxp2; struct cvmx_pko_mem_debug12_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t fau:28; uint64_t cmd:14; uint64_t segs:6; uint64_t size:16; +#else + uint64_t size:16; + uint64_t segs:6; + uint64_t cmd:14; + uint64_t fau:28; +#endif } cn50xx; struct cvmx_pko_mem_debug12_cn50xx cn52xx; struct cvmx_pko_mem_debug12_cn50xx cn52xxp1; @@ -280,31 +382,60 @@ union cvmx_pko_mem_debug12 { struct cvmx_pko_mem_debug12_cn50xx cn56xxp1; struct cvmx_pko_mem_debug12_cn50xx cn58xx; struct cvmx_pko_mem_debug12_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug12_cn50xx cn61xx; + struct cvmx_pko_mem_debug12_cn50xx cn63xx; + struct cvmx_pko_mem_debug12_cn50xx cn63xxp1; + struct cvmx_pko_mem_debug12_cn50xx cn66xx; + struct cvmx_pko_mem_debug12_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t state:64; +#else + uint64_t state:64; +#endif + } cn68xx; + struct cvmx_pko_mem_debug12_cn68xx cn68xxp1; + struct cvmx_pko_mem_debug12_cn50xx cnf71xx; }; union cvmx_pko_mem_debug13 { uint64_t u64; struct cvmx_pko_mem_debug13_s { - uint64_t i:1; - uint64_t back:4; - uint64_t pool:3; - uint64_t reserved_0_55:56; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_mem_debug13_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_51_63:13; uint64_t widx:17; uint64_t ridx2:17; uint64_t widx2:17; +#else + uint64_t widx2:17; + uint64_t ridx2:17; + uint64_t widx:17; + uint64_t reserved_51_63:13; +#endif } cn30xx; struct cvmx_pko_mem_debug13_cn30xx cn31xx; struct cvmx_pko_mem_debug13_cn30xx cn38xx; struct cvmx_pko_mem_debug13_cn30xx cn38xxp2; struct cvmx_pko_mem_debug13_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t ptr:40; +#else + uint64_t ptr:40; + uint64_t size:16; + uint64_t pool:3; + uint64_t back:4; + uint64_t i:1; +#endif } cn50xx; struct cvmx_pko_mem_debug13_cn50xx cn52xx; struct cvmx_pko_mem_debug13_cn50xx cn52xxp1; @@ -312,36 +443,75 @@ union cvmx_pko_mem_debug13 { struct cvmx_pko_mem_debug13_cn50xx cn56xxp1; struct cvmx_pko_mem_debug13_cn50xx cn58xx; struct cvmx_pko_mem_debug13_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug13_cn50xx cn61xx; + struct cvmx_pko_mem_debug13_cn50xx cn63xx; + struct cvmx_pko_mem_debug13_cn50xx cn63xxp1; + struct cvmx_pko_mem_debug13_cn50xx cn66xx; + struct cvmx_pko_mem_debug13_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t state:64; +#else + uint64_t state:64; +#endif + } cn68xx; + struct cvmx_pko_mem_debug13_cn68xx cn68xxp1; + struct cvmx_pko_mem_debug13_cn50xx cnf71xx; }; union cvmx_pko_mem_debug14 { uint64_t u64; struct cvmx_pko_mem_debug14_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_mem_debug14_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t ridx:17; +#else + uint64_t ridx:17; + uint64_t reserved_17_63:47; +#endif } cn30xx; struct cvmx_pko_mem_debug14_cn30xx cn31xx; struct cvmx_pko_mem_debug14_cn30xx cn38xx; struct cvmx_pko_mem_debug14_cn30xx cn38xxp2; struct cvmx_pko_mem_debug14_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } cn52xx; struct cvmx_pko_mem_debug14_cn52xx cn52xxp1; struct cvmx_pko_mem_debug14_cn52xx cn56xx; struct cvmx_pko_mem_debug14_cn52xx cn56xxp1; + struct cvmx_pko_mem_debug14_cn52xx cn61xx; + struct cvmx_pko_mem_debug14_cn52xx cn63xx; + struct cvmx_pko_mem_debug14_cn52xx cn63xxp1; + struct cvmx_pko_mem_debug14_cn52xx cn66xx; + struct cvmx_pko_mem_debug14_cn52xx cnf71xx; }; union cvmx_pko_mem_debug2 { uint64_t u64; struct cvmx_pko_mem_debug2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t ptr:40; +#else + uint64_t ptr:40; + uint64_t size:16; + uint64_t pool:3; + uint64_t back:4; + uint64_t i:1; +#endif } s; struct cvmx_pko_mem_debug2_s cn30xx; struct cvmx_pko_mem_debug2_s cn31xx; @@ -354,25 +524,48 @@ union cvmx_pko_mem_debug2 { struct cvmx_pko_mem_debug2_s cn56xxp1; struct cvmx_pko_mem_debug2_s cn58xx; struct cvmx_pko_mem_debug2_s cn58xxp1; + struct cvmx_pko_mem_debug2_s cn61xx; + struct cvmx_pko_mem_debug2_s cn63xx; + struct cvmx_pko_mem_debug2_s cn63xxp1; + struct cvmx_pko_mem_debug2_s cn66xx; + struct cvmx_pko_mem_debug2_s cn68xx; + struct cvmx_pko_mem_debug2_s cn68xxp1; + struct cvmx_pko_mem_debug2_s cnf71xx; }; union cvmx_pko_mem_debug3 { uint64_t u64; struct cvmx_pko_mem_debug3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_mem_debug3_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t i:1; uint64_t back:4; uint64_t pool:3; uint64_t size:16; uint64_t ptr:40; +#else + uint64_t ptr:40; + uint64_t size:16; + uint64_t pool:3; + uint64_t back:4; + uint64_t i:1; +#endif } cn30xx; struct cvmx_pko_mem_debug3_cn30xx cn31xx; struct cvmx_pko_mem_debug3_cn30xx cn38xx; struct cvmx_pko_mem_debug3_cn30xx cn38xxp2; struct cvmx_pko_mem_debug3_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } cn50xx; struct cvmx_pko_mem_debug3_cn50xx cn52xx; struct cvmx_pko_mem_debug3_cn50xx cn52xxp1; @@ -380,20 +573,36 @@ union cvmx_pko_mem_debug3 { struct cvmx_pko_mem_debug3_cn50xx cn56xxp1; struct cvmx_pko_mem_debug3_cn50xx cn58xx; struct cvmx_pko_mem_debug3_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug3_cn50xx cn61xx; + struct cvmx_pko_mem_debug3_cn50xx cn63xx; + struct cvmx_pko_mem_debug3_cn50xx cn63xxp1; + struct cvmx_pko_mem_debug3_cn50xx cn66xx; + struct cvmx_pko_mem_debug3_cn50xx cn68xx; + struct cvmx_pko_mem_debug3_cn50xx cn68xxp1; + struct cvmx_pko_mem_debug3_cn50xx cnf71xx; }; union cvmx_pko_mem_debug4 { uint64_t u64; struct cvmx_pko_mem_debug4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_mem_debug4_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t data:64; +#else + uint64_t data:64; +#endif } cn30xx; struct cvmx_pko_mem_debug4_cn30xx cn31xx; struct cvmx_pko_mem_debug4_cn30xx cn38xx; struct cvmx_pko_mem_debug4_cn30xx cn38xxp2; struct cvmx_pko_mem_debug4_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t cmnd_segs:3; uint64_t cmnd_siz:16; uint64_t cmnd_off:6; @@ -412,8 +621,29 @@ union cvmx_pko_mem_debug4 { uint64_t wait:1; uint64_t minor:2; uint64_t major:3; +#else + uint64_t major:3; + uint64_t minor:2; + uint64_t wait:1; + uint64_t qid_base:8; + uint64_t qid_off:4; + uint64_t qid_off_max:4; + uint64_t qcb_ridx:5; + uint64_t qos:3; + uint64_t static_p:1; + uint64_t active:1; + uint64_t chk_mode:1; + uint64_t chk_once:1; + uint64_t init_dwrite:1; + uint64_t dread_sop:1; + uint64_t uid:3; + uint64_t cmnd_off:6; + uint64_t cmnd_siz:16; + uint64_t cmnd_segs:3; +#endif } cn50xx; struct cvmx_pko_mem_debug4_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t curr_siz:8; uint64_t curr_off:16; uint64_t cmnd_segs:6; @@ -427,20 +657,47 @@ union cvmx_pko_mem_debug4 { uint64_t wait:1; uint64_t minor:2; uint64_t major:3; +#else + uint64_t major:3; + uint64_t minor:2; + uint64_t wait:1; + uint64_t chk_mode:1; + uint64_t chk_once:1; + uint64_t init_dwrite:1; + uint64_t dread_sop:1; + uint64_t uid:2; + uint64_t cmnd_off:6; + uint64_t cmnd_siz:16; + uint64_t cmnd_segs:6; + uint64_t curr_off:16; + uint64_t curr_siz:8; +#endif } cn52xx; struct cvmx_pko_mem_debug4_cn52xx cn52xxp1; struct cvmx_pko_mem_debug4_cn52xx cn56xx; struct cvmx_pko_mem_debug4_cn52xx cn56xxp1; struct cvmx_pko_mem_debug4_cn50xx cn58xx; struct cvmx_pko_mem_debug4_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug4_cn52xx cn61xx; + struct cvmx_pko_mem_debug4_cn52xx cn63xx; + struct cvmx_pko_mem_debug4_cn52xx cn63xxp1; + struct cvmx_pko_mem_debug4_cn52xx cn66xx; + struct cvmx_pko_mem_debug4_cn52xx cn68xx; + struct cvmx_pko_mem_debug4_cn52xx cn68xxp1; + struct cvmx_pko_mem_debug4_cn52xx cnf71xx; }; union cvmx_pko_mem_debug5 { uint64_t u64; struct cvmx_pko_mem_debug5_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_mem_debug5_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dwri_mod:1; uint64_t dwri_sop:1; uint64_t dwri_len:1; @@ -460,32 +717,109 @@ union cvmx_pko_mem_debug5 { uint64_t wait:1; uint64_t minor:2; uint64_t major:4; +#else + uint64_t major:4; + uint64_t minor:2; + uint64_t wait:1; + uint64_t qid_base:7; + uint64_t qid_off:3; + uint64_t qcb_ridx:5; + uint64_t qos:3; + uint64_t active:1; + uint64_t chk_mode:1; + uint64_t reserved_27_27:1; + uint64_t cbuf_fre:1; + uint64_t xfer_dwr:1; + uint64_t xfer_wor:1; + uint64_t uid:1; + uint64_t cmnd_siz:16; + uint64_t dwri_cnt:13; + uint64_t dwri_len:1; + uint64_t dwri_sop:1; + uint64_t dwri_mod:1; +#endif } cn30xx; struct cvmx_pko_mem_debug5_cn30xx cn31xx; struct cvmx_pko_mem_debug5_cn30xx cn38xx; struct cvmx_pko_mem_debug5_cn30xx cn38xxp2; struct cvmx_pko_mem_debug5_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t curr_ptr:29; uint64_t curr_siz:16; uint64_t curr_off:16; uint64_t cmnd_segs:3; +#else + uint64_t cmnd_segs:3; + uint64_t curr_off:16; + uint64_t curr_siz:16; + uint64_t curr_ptr:29; +#endif } cn50xx; struct cvmx_pko_mem_debug5_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t nxt_inflt:6; uint64_t curr_ptr:40; uint64_t curr_siz:8; +#else + uint64_t curr_siz:8; + uint64_t curr_ptr:40; + uint64_t nxt_inflt:6; + uint64_t reserved_54_63:10; +#endif } cn52xx; struct cvmx_pko_mem_debug5_cn52xx cn52xxp1; struct cvmx_pko_mem_debug5_cn52xx cn56xx; struct cvmx_pko_mem_debug5_cn52xx cn56xxp1; struct cvmx_pko_mem_debug5_cn50xx cn58xx; struct cvmx_pko_mem_debug5_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug5_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t ptp:1; + uint64_t major_3:1; + uint64_t nxt_inflt:6; + uint64_t curr_ptr:40; + uint64_t curr_siz:8; +#else + uint64_t curr_siz:8; + uint64_t curr_ptr:40; + uint64_t nxt_inflt:6; + uint64_t major_3:1; + uint64_t ptp:1; + uint64_t reserved_56_63:8; +#endif + } cn61xx; + struct cvmx_pko_mem_debug5_cn61xx cn63xx; + struct cvmx_pko_mem_debug5_cn61xx cn63xxp1; + struct cvmx_pko_mem_debug5_cn61xx cn66xx; + struct cvmx_pko_mem_debug5_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_57_63:7; + uint64_t uid_2:1; + uint64_t ptp:1; + uint64_t major_3:1; + uint64_t nxt_inflt:6; + uint64_t curr_ptr:40; + uint64_t curr_siz:8; +#else + uint64_t curr_siz:8; + uint64_t curr_ptr:40; + uint64_t nxt_inflt:6; + uint64_t major_3:1; + uint64_t ptp:1; + uint64_t uid_2:1; + uint64_t reserved_57_63:7; +#endif + } cn68xx; + struct cvmx_pko_mem_debug5_cn68xx cn68xxp1; + struct cvmx_pko_mem_debug5_cn61xx cnf71xx; }; union cvmx_pko_mem_debug6 { uint64_t u64; struct cvmx_pko_mem_debug6_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t qid_offres:4; uint64_t qid_offths:4; @@ -498,8 +832,23 @@ union cvmx_pko_mem_debug6 { uint64_t qcb_ridx:5; uint64_t qid_offmax:4; uint64_t reserved_0_11:12; +#else + uint64_t reserved_0_11:12; + uint64_t qid_offmax:4; + uint64_t qcb_ridx:5; + uint64_t qos:3; + uint64_t statc:1; + uint64_t active:1; + uint64_t preempted:1; + uint64_t preemptee:1; + uint64_t preempter:1; + uint64_t qid_offths:4; + uint64_t qid_offres:4; + uint64_t reserved_37_63:27; +#endif } s; struct cvmx_pko_mem_debug6_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t qid_offm:3; uint64_t static_p:1; @@ -507,15 +856,30 @@ union cvmx_pko_mem_debug6 { uint64_t dwri_chk:1; uint64_t dwri_uid:1; uint64_t dwri_mod:2; +#else + uint64_t dwri_mod:2; + uint64_t dwri_uid:1; + uint64_t dwri_chk:1; + uint64_t work_min:3; + uint64_t static_p:1; + uint64_t qid_offm:3; + uint64_t reserved_11_63:53; +#endif } cn30xx; struct cvmx_pko_mem_debug6_cn30xx cn31xx; struct cvmx_pko_mem_debug6_cn30xx cn38xx; struct cvmx_pko_mem_debug6_cn30xx cn38xxp2; struct cvmx_pko_mem_debug6_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t curr_ptr:11; +#else + uint64_t curr_ptr:11; + uint64_t reserved_11_63:53; +#endif } cn50xx; struct cvmx_pko_mem_debug6_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_37_63:27; uint64_t qid_offres:4; uint64_t qid_offths:4; @@ -529,37 +893,77 @@ union cvmx_pko_mem_debug6 { uint64_t qid_offmax:4; uint64_t qid_off:4; uint64_t qid_base:8; +#else + uint64_t qid_base:8; + uint64_t qid_off:4; + uint64_t qid_offmax:4; + uint64_t qcb_ridx:5; + uint64_t qos:3; + uint64_t statc:1; + uint64_t active:1; + uint64_t preempted:1; + uint64_t preemptee:1; + uint64_t preempter:1; + uint64_t qid_offths:4; + uint64_t qid_offres:4; + uint64_t reserved_37_63:27; +#endif } cn52xx; struct cvmx_pko_mem_debug6_cn52xx cn52xxp1; struct cvmx_pko_mem_debug6_cn52xx cn56xx; struct cvmx_pko_mem_debug6_cn52xx cn56xxp1; struct cvmx_pko_mem_debug6_cn50xx cn58xx; struct cvmx_pko_mem_debug6_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug6_cn52xx cn61xx; + struct cvmx_pko_mem_debug6_cn52xx cn63xx; + struct cvmx_pko_mem_debug6_cn52xx cn63xxp1; + struct cvmx_pko_mem_debug6_cn52xx cn66xx; + struct cvmx_pko_mem_debug6_cn52xx cn68xx; + struct cvmx_pko_mem_debug6_cn52xx cn68xxp1; + struct cvmx_pko_mem_debug6_cn52xx cnf71xx; }; union cvmx_pko_mem_debug7 { uint64_t u64; struct cvmx_pko_mem_debug7_s { - uint64_t qos:5; - uint64_t tail:1; - uint64_t reserved_0_57:58; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_mem_debug7_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t dwb:9; uint64_t start:33; uint64_t size:16; +#else + uint64_t size:16; + uint64_t start:33; + uint64_t dwb:9; + uint64_t reserved_58_63:6; +#endif } cn30xx; struct cvmx_pko_mem_debug7_cn30xx cn31xx; struct cvmx_pko_mem_debug7_cn30xx cn38xx; struct cvmx_pko_mem_debug7_cn30xx cn38xxp2; struct cvmx_pko_mem_debug7_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t qos:5; uint64_t tail:1; uint64_t buf_siz:13; uint64_t buf_ptr:33; uint64_t qcb_widx:6; uint64_t qcb_ridx:6; +#else + uint64_t qcb_ridx:6; + uint64_t qcb_widx:6; + uint64_t buf_ptr:33; + uint64_t buf_siz:13; + uint64_t tail:1; + uint64_t qos:5; +#endif } cn50xx; struct cvmx_pko_mem_debug7_cn50xx cn52xx; struct cvmx_pko_mem_debug7_cn50xx cn52xxp1; @@ -567,28 +971,68 @@ union cvmx_pko_mem_debug7 { struct cvmx_pko_mem_debug7_cn50xx cn56xxp1; struct cvmx_pko_mem_debug7_cn50xx cn58xx; struct cvmx_pko_mem_debug7_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug7_cn50xx cn61xx; + struct cvmx_pko_mem_debug7_cn50xx cn63xx; + struct cvmx_pko_mem_debug7_cn50xx cn63xxp1; + struct cvmx_pko_mem_debug7_cn50xx cn66xx; + struct cvmx_pko_mem_debug7_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t qos:3; + uint64_t tail:1; + uint64_t buf_siz:13; + uint64_t buf_ptr:33; + uint64_t qcb_widx:7; + uint64_t qcb_ridx:7; +#else + uint64_t qcb_ridx:7; + uint64_t qcb_widx:7; + uint64_t buf_ptr:33; + uint64_t buf_siz:13; + uint64_t tail:1; + uint64_t qos:3; +#endif + } cn68xx; + struct cvmx_pko_mem_debug7_cn68xx cn68xxp1; + struct cvmx_pko_mem_debug7_cn50xx cnf71xx; }; union cvmx_pko_mem_debug8 { uint64_t u64; struct cvmx_pko_mem_debug8_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t tail:1; uint64_t buf_siz:13; uint64_t reserved_0_44:45; +#else + uint64_t reserved_0_44:45; + uint64_t buf_siz:13; + uint64_t tail:1; + uint64_t reserved_59_63:5; +#endif } s; struct cvmx_pko_mem_debug8_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t qos:5; uint64_t tail:1; uint64_t buf_siz:13; uint64_t buf_ptr:33; uint64_t qcb_widx:6; uint64_t qcb_ridx:6; +#else + uint64_t qcb_ridx:6; + uint64_t qcb_widx:6; + uint64_t buf_ptr:33; + uint64_t buf_siz:13; + uint64_t tail:1; + uint64_t qos:5; +#endif } cn30xx; struct cvmx_pko_mem_debug8_cn30xx cn31xx; struct cvmx_pko_mem_debug8_cn30xx cn38xx; struct cvmx_pko_mem_debug8_cn30xx cn38xxp2; struct cvmx_pko_mem_debug8_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t doorbell:20; uint64_t reserved_6_7:2; @@ -596,8 +1040,18 @@ union cvmx_pko_mem_debug8 { uint64_t s_tail:1; uint64_t static_q:1; uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t static_q:1; + uint64_t s_tail:1; + uint64_t static_p:1; + uint64_t reserved_6_7:2; + uint64_t doorbell:20; + uint64_t reserved_28_63:36; +#endif } cn50xx; struct cvmx_pko_mem_debug8_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t preempter:1; uint64_t doorbell:20; @@ -607,31 +1061,115 @@ union cvmx_pko_mem_debug8 { uint64_t s_tail:1; uint64_t static_q:1; uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t static_q:1; + uint64_t s_tail:1; + uint64_t static_p:1; + uint64_t preemptee:1; + uint64_t reserved_7_7:1; + uint64_t doorbell:20; + uint64_t preempter:1; + uint64_t reserved_29_63:35; +#endif } cn52xx; struct cvmx_pko_mem_debug8_cn52xx cn52xxp1; struct cvmx_pko_mem_debug8_cn52xx cn56xx; struct cvmx_pko_mem_debug8_cn52xx cn56xxp1; struct cvmx_pko_mem_debug8_cn50xx cn58xx; struct cvmx_pko_mem_debug8_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug8_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_42_63:22; + uint64_t qid_qqos:8; + uint64_t reserved_33_33:1; + uint64_t qid_idx:4; + uint64_t preempter:1; + uint64_t doorbell:20; + uint64_t reserved_7_7:1; + uint64_t preemptee:1; + uint64_t static_p:1; + uint64_t s_tail:1; + uint64_t static_q:1; + uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t static_q:1; + uint64_t s_tail:1; + uint64_t static_p:1; + uint64_t preemptee:1; + uint64_t reserved_7_7:1; + uint64_t doorbell:20; + uint64_t preempter:1; + uint64_t qid_idx:4; + uint64_t reserved_33_33:1; + uint64_t qid_qqos:8; + uint64_t reserved_42_63:22; +#endif + } cn61xx; + struct cvmx_pko_mem_debug8_cn52xx cn63xx; + struct cvmx_pko_mem_debug8_cn52xx cn63xxp1; + struct cvmx_pko_mem_debug8_cn61xx cn66xx; + struct cvmx_pko_mem_debug8_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_37_63:27; + uint64_t preempter:1; + uint64_t doorbell:20; + uint64_t reserved_9_15:7; + uint64_t preemptee:1; + uint64_t static_p:1; + uint64_t s_tail:1; + uint64_t static_q:1; + uint64_t qos:5; +#else + uint64_t qos:5; + uint64_t static_q:1; + uint64_t s_tail:1; + uint64_t static_p:1; + uint64_t preemptee:1; + uint64_t reserved_9_15:7; + uint64_t doorbell:20; + uint64_t preempter:1; + uint64_t reserved_37_63:27; +#endif + } cn68xx; + struct cvmx_pko_mem_debug8_cn68xx cn68xxp1; + struct cvmx_pko_mem_debug8_cn61xx cnf71xx; }; union cvmx_pko_mem_debug9 { uint64_t u64; struct cvmx_pko_mem_debug9_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t ptrs0:17; uint64_t reserved_0_31:32; +#else + uint64_t reserved_0_31:32; + uint64_t ptrs0:17; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_pko_mem_debug9_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t doorbell:20; uint64_t reserved_5_7:3; uint64_t s_tail:1; uint64_t static_q:1; uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t static_q:1; + uint64_t s_tail:1; + uint64_t reserved_5_7:3; + uint64_t doorbell:20; + uint64_t reserved_28_63:36; +#endif } cn30xx; struct cvmx_pko_mem_debug9_cn30xx cn31xx; struct cvmx_pko_mem_debug9_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t doorbell:20; uint64_t reserved_6_7:2; @@ -639,13 +1177,29 @@ union cvmx_pko_mem_debug9 { uint64_t s_tail:1; uint64_t static_q:1; uint64_t qos:3; +#else + uint64_t qos:3; + uint64_t static_q:1; + uint64_t s_tail:1; + uint64_t static_p:1; + uint64_t reserved_6_7:2; + uint64_t doorbell:20; + uint64_t reserved_28_63:36; +#endif } cn38xx; struct cvmx_pko_mem_debug9_cn38xx cn38xxp2; struct cvmx_pko_mem_debug9_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t ptrs0:17; uint64_t reserved_17_31:15; uint64_t ptrs3:17; +#else + uint64_t ptrs3:17; + uint64_t reserved_17_31:15; + uint64_t ptrs0:17; + uint64_t reserved_49_63:15; +#endif } cn50xx; struct cvmx_pko_mem_debug9_cn50xx cn52xx; struct cvmx_pko_mem_debug9_cn50xx cn52xxp1; @@ -653,11 +1207,131 @@ union cvmx_pko_mem_debug9 { struct cvmx_pko_mem_debug9_cn50xx cn56xxp1; struct cvmx_pko_mem_debug9_cn50xx cn58xx; struct cvmx_pko_mem_debug9_cn50xx cn58xxp1; + struct cvmx_pko_mem_debug9_cn50xx cn61xx; + struct cvmx_pko_mem_debug9_cn50xx cn63xx; + struct cvmx_pko_mem_debug9_cn50xx cn63xxp1; + struct cvmx_pko_mem_debug9_cn50xx cn66xx; + struct cvmx_pko_mem_debug9_cn50xx cn68xx; + struct cvmx_pko_mem_debug9_cn50xx cn68xxp1; + struct cvmx_pko_mem_debug9_cn50xx cnf71xx; +}; + +union cvmx_pko_mem_iport_ptrs { + uint64_t u64; + struct cvmx_pko_mem_iport_ptrs_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_63_63:1; + uint64_t crc:1; + uint64_t static_p:1; + uint64_t qos_mask:8; + uint64_t min_pkt:3; + uint64_t reserved_31_49:19; + uint64_t pipe:7; + uint64_t reserved_21_23:3; + uint64_t intr:5; + uint64_t reserved_13_15:3; + uint64_t eid:5; + uint64_t reserved_7_7:1; + uint64_t ipid:7; +#else + uint64_t ipid:7; + uint64_t reserved_7_7:1; + uint64_t eid:5; + uint64_t reserved_13_15:3; + uint64_t intr:5; + uint64_t reserved_21_23:3; + uint64_t pipe:7; + uint64_t reserved_31_49:19; + uint64_t min_pkt:3; + uint64_t qos_mask:8; + uint64_t static_p:1; + uint64_t crc:1; + uint64_t reserved_63_63:1; +#endif + } s; + struct cvmx_pko_mem_iport_ptrs_s cn68xx; + struct cvmx_pko_mem_iport_ptrs_s cn68xxp1; +}; + +union cvmx_pko_mem_iport_qos { + uint64_t u64; + struct cvmx_pko_mem_iport_qos_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_61_63:3; + uint64_t qos_mask:8; + uint64_t reserved_13_52:40; + uint64_t eid:5; + uint64_t reserved_7_7:1; + uint64_t ipid:7; +#else + uint64_t ipid:7; + uint64_t reserved_7_7:1; + uint64_t eid:5; + uint64_t reserved_13_52:40; + uint64_t qos_mask:8; + uint64_t reserved_61_63:3; +#endif + } s; + struct cvmx_pko_mem_iport_qos_s cn68xx; + struct cvmx_pko_mem_iport_qos_s cn68xxp1; +}; + +union cvmx_pko_mem_iqueue_ptrs { + uint64_t u64; + struct cvmx_pko_mem_iqueue_ptrs_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t s_tail:1; + uint64_t static_p:1; + uint64_t static_q:1; + uint64_t qos_mask:8; + uint64_t buf_ptr:31; + uint64_t tail:1; + uint64_t index:5; + uint64_t reserved_15_15:1; + uint64_t ipid:7; + uint64_t qid:8; +#else + uint64_t qid:8; + uint64_t ipid:7; + uint64_t reserved_15_15:1; + uint64_t index:5; + uint64_t tail:1; + uint64_t buf_ptr:31; + uint64_t qos_mask:8; + uint64_t static_q:1; + uint64_t static_p:1; + uint64_t s_tail:1; +#endif + } s; + struct cvmx_pko_mem_iqueue_ptrs_s cn68xx; + struct cvmx_pko_mem_iqueue_ptrs_s cn68xxp1; +}; + +union cvmx_pko_mem_iqueue_qos { + uint64_t u64; + struct cvmx_pko_mem_iqueue_qos_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_61_63:3; + uint64_t qos_mask:8; + uint64_t reserved_15_52:38; + uint64_t ipid:7; + uint64_t qid:8; +#else + uint64_t qid:8; + uint64_t ipid:7; + uint64_t reserved_15_52:38; + uint64_t qos_mask:8; + uint64_t reserved_61_63:3; +#endif + } s; + struct cvmx_pko_mem_iqueue_qos_s cn68xx; + struct cvmx_pko_mem_iqueue_qos_s cn68xxp1; }; union cvmx_pko_mem_port_ptrs { uint64_t u64; struct cvmx_pko_mem_port_ptrs_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t static_p:1; uint64_t qos_mask:8; @@ -665,60 +1339,143 @@ union cvmx_pko_mem_port_ptrs { uint64_t bp_port:6; uint64_t eid:4; uint64_t pid:6; +#else + uint64_t pid:6; + uint64_t eid:4; + uint64_t bp_port:6; + uint64_t reserved_16_52:37; + uint64_t qos_mask:8; + uint64_t static_p:1; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_pko_mem_port_ptrs_s cn52xx; struct cvmx_pko_mem_port_ptrs_s cn52xxp1; struct cvmx_pko_mem_port_ptrs_s cn56xx; struct cvmx_pko_mem_port_ptrs_s cn56xxp1; + struct cvmx_pko_mem_port_ptrs_s cn61xx; + struct cvmx_pko_mem_port_ptrs_s cn63xx; + struct cvmx_pko_mem_port_ptrs_s cn63xxp1; + struct cvmx_pko_mem_port_ptrs_s cn66xx; + struct cvmx_pko_mem_port_ptrs_s cnf71xx; }; union cvmx_pko_mem_port_qos { uint64_t u64; struct cvmx_pko_mem_port_qos_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t qos_mask:8; uint64_t reserved_10_52:43; uint64_t eid:4; uint64_t pid:6; +#else + uint64_t pid:6; + uint64_t eid:4; + uint64_t reserved_10_52:43; + uint64_t qos_mask:8; + uint64_t reserved_61_63:3; +#endif } s; struct cvmx_pko_mem_port_qos_s cn52xx; struct cvmx_pko_mem_port_qos_s cn52xxp1; struct cvmx_pko_mem_port_qos_s cn56xx; struct cvmx_pko_mem_port_qos_s cn56xxp1; + struct cvmx_pko_mem_port_qos_s cn61xx; + struct cvmx_pko_mem_port_qos_s cn63xx; + struct cvmx_pko_mem_port_qos_s cn63xxp1; + struct cvmx_pko_mem_port_qos_s cn66xx; + struct cvmx_pko_mem_port_qos_s cnf71xx; }; union cvmx_pko_mem_port_rate0 { uint64_t u64; struct cvmx_pko_mem_port_rate0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_51_63:13; + uint64_t rate_word:19; + uint64_t rate_pkt:24; + uint64_t reserved_7_7:1; + uint64_t pid:7; +#else + uint64_t pid:7; + uint64_t reserved_7_7:1; + uint64_t rate_pkt:24; + uint64_t rate_word:19; + uint64_t reserved_51_63:13; +#endif + } s; + struct cvmx_pko_mem_port_rate0_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_51_63:13; uint64_t rate_word:19; uint64_t rate_pkt:24; uint64_t reserved_6_7:2; uint64_t pid:6; - } s; - struct cvmx_pko_mem_port_rate0_s cn52xx; - struct cvmx_pko_mem_port_rate0_s cn52xxp1; - struct cvmx_pko_mem_port_rate0_s cn56xx; - struct cvmx_pko_mem_port_rate0_s cn56xxp1; +#else + uint64_t pid:6; + uint64_t reserved_6_7:2; + uint64_t rate_pkt:24; + uint64_t rate_word:19; + uint64_t reserved_51_63:13; +#endif + } cn52xx; + struct cvmx_pko_mem_port_rate0_cn52xx cn52xxp1; + struct cvmx_pko_mem_port_rate0_cn52xx cn56xx; + struct cvmx_pko_mem_port_rate0_cn52xx cn56xxp1; + struct cvmx_pko_mem_port_rate0_cn52xx cn61xx; + struct cvmx_pko_mem_port_rate0_cn52xx cn63xx; + struct cvmx_pko_mem_port_rate0_cn52xx cn63xxp1; + struct cvmx_pko_mem_port_rate0_cn52xx cn66xx; + struct cvmx_pko_mem_port_rate0_s cn68xx; + struct cvmx_pko_mem_port_rate0_s cn68xxp1; + struct cvmx_pko_mem_port_rate0_cn52xx cnf71xx; }; union cvmx_pko_mem_port_rate1 { uint64_t u64; struct cvmx_pko_mem_port_rate1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t rate_lim:24; + uint64_t reserved_7_7:1; + uint64_t pid:7; +#else + uint64_t pid:7; + uint64_t reserved_7_7:1; + uint64_t rate_lim:24; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_pko_mem_port_rate1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rate_lim:24; uint64_t reserved_6_7:2; uint64_t pid:6; - } s; - struct cvmx_pko_mem_port_rate1_s cn52xx; - struct cvmx_pko_mem_port_rate1_s cn52xxp1; - struct cvmx_pko_mem_port_rate1_s cn56xx; - struct cvmx_pko_mem_port_rate1_s cn56xxp1; +#else + uint64_t pid:6; + uint64_t reserved_6_7:2; + uint64_t rate_lim:24; + uint64_t reserved_32_63:32; +#endif + } cn52xx; + struct cvmx_pko_mem_port_rate1_cn52xx cn52xxp1; + struct cvmx_pko_mem_port_rate1_cn52xx cn56xx; + struct cvmx_pko_mem_port_rate1_cn52xx cn56xxp1; + struct cvmx_pko_mem_port_rate1_cn52xx cn61xx; + struct cvmx_pko_mem_port_rate1_cn52xx cn63xx; + struct cvmx_pko_mem_port_rate1_cn52xx cn63xxp1; + struct cvmx_pko_mem_port_rate1_cn52xx cn66xx; + struct cvmx_pko_mem_port_rate1_s cn68xx; + struct cvmx_pko_mem_port_rate1_s cn68xxp1; + struct cvmx_pko_mem_port_rate1_cn52xx cnf71xx; }; union cvmx_pko_mem_queue_ptrs { uint64_t u64; struct cvmx_pko_mem_queue_ptrs_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t s_tail:1; uint64_t static_p:1; uint64_t static_q:1; @@ -728,6 +1485,17 @@ union cvmx_pko_mem_queue_ptrs { uint64_t index:3; uint64_t port:6; uint64_t queue:7; +#else + uint64_t queue:7; + uint64_t port:6; + uint64_t index:3; + uint64_t tail:1; + uint64_t buf_ptr:36; + uint64_t qos_mask:8; + uint64_t static_q:1; + uint64_t static_p:1; + uint64_t s_tail:1; +#endif } s; struct cvmx_pko_mem_queue_ptrs_s cn30xx; struct cvmx_pko_mem_queue_ptrs_s cn31xx; @@ -740,16 +1508,29 @@ union cvmx_pko_mem_queue_ptrs { struct cvmx_pko_mem_queue_ptrs_s cn56xxp1; struct cvmx_pko_mem_queue_ptrs_s cn58xx; struct cvmx_pko_mem_queue_ptrs_s cn58xxp1; + struct cvmx_pko_mem_queue_ptrs_s cn61xx; + struct cvmx_pko_mem_queue_ptrs_s cn63xx; + struct cvmx_pko_mem_queue_ptrs_s cn63xxp1; + struct cvmx_pko_mem_queue_ptrs_s cn66xx; + struct cvmx_pko_mem_queue_ptrs_s cnf71xx; }; union cvmx_pko_mem_queue_qos { uint64_t u64; struct cvmx_pko_mem_queue_qos_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t qos_mask:8; uint64_t reserved_13_52:40; uint64_t pid:6; uint64_t qid:7; +#else + uint64_t qid:7; + uint64_t pid:6; + uint64_t reserved_13_52:40; + uint64_t qos_mask:8; + uint64_t reserved_61_63:3; +#endif } s; struct cvmx_pko_mem_queue_qos_s cn30xx; struct cvmx_pko_mem_queue_qos_s cn31xx; @@ -762,14 +1543,70 @@ union cvmx_pko_mem_queue_qos { struct cvmx_pko_mem_queue_qos_s cn56xxp1; struct cvmx_pko_mem_queue_qos_s cn58xx; struct cvmx_pko_mem_queue_qos_s cn58xxp1; + struct cvmx_pko_mem_queue_qos_s cn61xx; + struct cvmx_pko_mem_queue_qos_s cn63xx; + struct cvmx_pko_mem_queue_qos_s cn63xxp1; + struct cvmx_pko_mem_queue_qos_s cn66xx; + struct cvmx_pko_mem_queue_qos_s cnf71xx; +}; + +union cvmx_pko_mem_throttle_int { + uint64_t u64; + struct cvmx_pko_mem_throttle_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_47_63:17; + uint64_t word:15; + uint64_t reserved_14_31:18; + uint64_t packet:6; + uint64_t reserved_5_7:3; + uint64_t intr:5; +#else + uint64_t intr:5; + uint64_t reserved_5_7:3; + uint64_t packet:6; + uint64_t reserved_14_31:18; + uint64_t word:15; + uint64_t reserved_47_63:17; +#endif + } s; + struct cvmx_pko_mem_throttle_int_s cn68xx; + struct cvmx_pko_mem_throttle_int_s cn68xxp1; +}; + +union cvmx_pko_mem_throttle_pipe { + uint64_t u64; + struct cvmx_pko_mem_throttle_pipe_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_47_63:17; + uint64_t word:15; + uint64_t reserved_14_31:18; + uint64_t packet:6; + uint64_t reserved_7_7:1; + uint64_t pipe:7; +#else + uint64_t pipe:7; + uint64_t reserved_7_7:1; + uint64_t packet:6; + uint64_t reserved_14_31:18; + uint64_t word:15; + uint64_t reserved_47_63:17; +#endif + } s; + struct cvmx_pko_mem_throttle_pipe_s cn68xx; + struct cvmx_pko_mem_throttle_pipe_s cn68xxp1; }; union cvmx_pko_reg_bist_result { uint64_t u64; struct cvmx_pko_reg_bist_result_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif } s; struct cvmx_pko_reg_bist_result_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t psb2:5; uint64_t count:1; @@ -783,11 +1620,27 @@ union cvmx_pko_reg_bist_result { uint64_t qcb:2; uint64_t pdb:4; uint64_t psb:7; +#else + uint64_t psb:7; + uint64_t pdb:4; + uint64_t qcb:2; + uint64_t qsb:2; + uint64_t chk:1; + uint64_t crc:1; + uint64_t out:1; + uint64_t ncb:1; + uint64_t wif:1; + uint64_t rif:1; + uint64_t count:1; + uint64_t psb2:5; + uint64_t reserved_27_63:37; +#endif } cn30xx; struct cvmx_pko_reg_bist_result_cn30xx cn31xx; struct cvmx_pko_reg_bist_result_cn30xx cn38xx; struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2; struct cvmx_pko_reg_bist_result_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_33_63:31; uint64_t csr:1; uint64_t iob:1; @@ -803,8 +1656,26 @@ union cvmx_pko_reg_bist_result { uint64_t prt_qsb:3; uint64_t dat_dat:4; uint64_t dat_ptr:4; +#else + uint64_t dat_ptr:4; + uint64_t dat_dat:4; + uint64_t prt_qsb:3; + uint64_t prt_qcb:2; + uint64_t ncb_inb:2; + uint64_t prt_psb:6; + uint64_t prt_nxt:1; + uint64_t prt_chk:3; + uint64_t out_wif:1; + uint64_t out_sta:1; + uint64_t out_ctl:3; + uint64_t out_crc:1; + uint64_t iob:1; + uint64_t csr:1; + uint64_t reserved_33_63:31; +#endif } cn50xx; struct cvmx_pko_reg_bist_result_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_35_63:29; uint64_t csr:1; uint64_t iob:1; @@ -821,21 +1692,139 @@ union cvmx_pko_reg_bist_result { uint64_t prt_ctl:2; uint64_t dat_dat:2; uint64_t dat_ptr:4; +#else + uint64_t dat_ptr:4; + uint64_t dat_dat:2; + uint64_t prt_ctl:2; + uint64_t prt_qsb:3; + uint64_t prt_qcb:2; + uint64_t ncb_inb:2; + uint64_t prt_psb:8; + uint64_t prt_nxt:1; + uint64_t prt_chk:3; + uint64_t out_wif:1; + uint64_t out_sta:1; + uint64_t out_ctl:3; + uint64_t out_dat:1; + uint64_t iob:1; + uint64_t csr:1; + uint64_t reserved_35_63:29; +#endif } cn52xx; struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1; struct cvmx_pko_reg_bist_result_cn52xx cn56xx; struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1; struct cvmx_pko_reg_bist_result_cn50xx cn58xx; struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1; + struct cvmx_pko_reg_bist_result_cn52xx cn61xx; + struct cvmx_pko_reg_bist_result_cn52xx cn63xx; + struct cvmx_pko_reg_bist_result_cn52xx cn63xxp1; + struct cvmx_pko_reg_bist_result_cn52xx cn66xx; + struct cvmx_pko_reg_bist_result_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_36_63:28; + uint64_t crc:1; + uint64_t csr:1; + uint64_t iob:1; + uint64_t out_dat:1; + uint64_t reserved_31_31:1; + uint64_t out_ctl:2; + uint64_t out_sta:1; + uint64_t out_wif:1; + uint64_t prt_chk:3; + uint64_t prt_nxt:1; + uint64_t prt_psb7:1; + uint64_t reserved_21_21:1; + uint64_t prt_psb:6; + uint64_t ncb_inb:2; + uint64_t prt_qcb:2; + uint64_t prt_qsb:3; + uint64_t prt_ctl:2; + uint64_t dat_dat:2; + uint64_t dat_ptr:4; +#else + uint64_t dat_ptr:4; + uint64_t dat_dat:2; + uint64_t prt_ctl:2; + uint64_t prt_qsb:3; + uint64_t prt_qcb:2; + uint64_t ncb_inb:2; + uint64_t prt_psb:6; + uint64_t reserved_21_21:1; + uint64_t prt_psb7:1; + uint64_t prt_nxt:1; + uint64_t prt_chk:3; + uint64_t out_wif:1; + uint64_t out_sta:1; + uint64_t out_ctl:2; + uint64_t reserved_31_31:1; + uint64_t out_dat:1; + uint64_t iob:1; + uint64_t csr:1; + uint64_t crc:1; + uint64_t reserved_36_63:28; +#endif + } cn68xx; + struct cvmx_pko_reg_bist_result_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_35_63:29; + uint64_t csr:1; + uint64_t iob:1; + uint64_t out_dat:1; + uint64_t reserved_31_31:1; + uint64_t out_ctl:2; + uint64_t out_sta:1; + uint64_t out_wif:1; + uint64_t prt_chk:3; + uint64_t prt_nxt:1; + uint64_t prt_psb7:1; + uint64_t reserved_21_21:1; + uint64_t prt_psb:6; + uint64_t ncb_inb:2; + uint64_t prt_qcb:2; + uint64_t prt_qsb:3; + uint64_t prt_ctl:2; + uint64_t dat_dat:2; + uint64_t dat_ptr:4; +#else + uint64_t dat_ptr:4; + uint64_t dat_dat:2; + uint64_t prt_ctl:2; + uint64_t prt_qsb:3; + uint64_t prt_qcb:2; + uint64_t ncb_inb:2; + uint64_t prt_psb:6; + uint64_t reserved_21_21:1; + uint64_t prt_psb7:1; + uint64_t prt_nxt:1; + uint64_t prt_chk:3; + uint64_t out_wif:1; + uint64_t out_sta:1; + uint64_t out_ctl:2; + uint64_t reserved_31_31:1; + uint64_t out_dat:1; + uint64_t iob:1; + uint64_t csr:1; + uint64_t reserved_35_63:29; +#endif + } cn68xxp1; + struct cvmx_pko_reg_bist_result_cn52xx cnf71xx; }; union cvmx_pko_reg_cmd_buf { uint64_t u64; struct cvmx_pko_reg_cmd_buf_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t pool:3; uint64_t reserved_13_19:7; uint64_t size:13; +#else + uint64_t size:13; + uint64_t reserved_13_19:7; + uint64_t pool:3; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_pko_reg_cmd_buf_s cn30xx; struct cvmx_pko_reg_cmd_buf_s cn31xx; @@ -848,14 +1837,27 @@ union cvmx_pko_reg_cmd_buf { struct cvmx_pko_reg_cmd_buf_s cn56xxp1; struct cvmx_pko_reg_cmd_buf_s cn58xx; struct cvmx_pko_reg_cmd_buf_s cn58xxp1; + struct cvmx_pko_reg_cmd_buf_s cn61xx; + struct cvmx_pko_reg_cmd_buf_s cn63xx; + struct cvmx_pko_reg_cmd_buf_s cn63xxp1; + struct cvmx_pko_reg_cmd_buf_s cn66xx; + struct cvmx_pko_reg_cmd_buf_s cn68xx; + struct cvmx_pko_reg_cmd_buf_s cn68xxp1; + struct cvmx_pko_reg_cmd_buf_s cnf71xx; }; union cvmx_pko_reg_crc_ctlx { uint64_t u64; struct cvmx_pko_reg_crc_ctlx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t invres:1; uint64_t refin:1; +#else + uint64_t refin:1; + uint64_t invres:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_pko_reg_crc_ctlx_s cn38xx; struct cvmx_pko_reg_crc_ctlx_s cn38xxp2; @@ -866,8 +1868,13 @@ union cvmx_pko_reg_crc_ctlx { union cvmx_pko_reg_crc_enable { uint64_t u64; struct cvmx_pko_reg_crc_enable_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enable:32; +#else + uint64_t enable:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pko_reg_crc_enable_s cn38xx; struct cvmx_pko_reg_crc_enable_s cn38xxp2; @@ -878,8 +1885,13 @@ union cvmx_pko_reg_crc_enable { union cvmx_pko_reg_crc_ivx { uint64_t u64; struct cvmx_pko_reg_crc_ivx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iv:32; +#else + uint64_t iv:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pko_reg_crc_ivx_s cn38xx; struct cvmx_pko_reg_crc_ivx_s cn38xxp2; @@ -890,11 +1902,20 @@ union cvmx_pko_reg_crc_ivx { union cvmx_pko_reg_debug0 { uint64_t u64; struct cvmx_pko_reg_debug0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t asserts:64; +#else uint64_t asserts:64; +#endif } s; struct cvmx_pko_reg_debug0_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t asserts:17; +#else + uint64_t asserts:17; + uint64_t reserved_17_63:47; +#endif } cn30xx; struct cvmx_pko_reg_debug0_cn30xx cn31xx; struct cvmx_pko_reg_debug0_cn30xx cn38xx; @@ -906,12 +1927,23 @@ union cvmx_pko_reg_debug0 { struct cvmx_pko_reg_debug0_s cn56xxp1; struct cvmx_pko_reg_debug0_s cn58xx; struct cvmx_pko_reg_debug0_s cn58xxp1; + struct cvmx_pko_reg_debug0_s cn61xx; + struct cvmx_pko_reg_debug0_s cn63xx; + struct cvmx_pko_reg_debug0_s cn63xxp1; + struct cvmx_pko_reg_debug0_s cn66xx; + struct cvmx_pko_reg_debug0_s cn68xx; + struct cvmx_pko_reg_debug0_s cn68xxp1; + struct cvmx_pko_reg_debug0_s cnf71xx; }; union cvmx_pko_reg_debug1 { uint64_t u64; struct cvmx_pko_reg_debug1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t asserts:64; +#else uint64_t asserts:64; +#endif } s; struct cvmx_pko_reg_debug1_s cn50xx; struct cvmx_pko_reg_debug1_s cn52xx; @@ -920,12 +1952,23 @@ union cvmx_pko_reg_debug1 { struct cvmx_pko_reg_debug1_s cn56xxp1; struct cvmx_pko_reg_debug1_s cn58xx; struct cvmx_pko_reg_debug1_s cn58xxp1; + struct cvmx_pko_reg_debug1_s cn61xx; + struct cvmx_pko_reg_debug1_s cn63xx; + struct cvmx_pko_reg_debug1_s cn63xxp1; + struct cvmx_pko_reg_debug1_s cn66xx; + struct cvmx_pko_reg_debug1_s cn68xx; + struct cvmx_pko_reg_debug1_s cn68xxp1; + struct cvmx_pko_reg_debug1_s cnf71xx; }; union cvmx_pko_reg_debug2 { uint64_t u64; struct cvmx_pko_reg_debug2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t asserts:64; +#else + uint64_t asserts:64; +#endif } s; struct cvmx_pko_reg_debug2_s cn50xx; struct cvmx_pko_reg_debug2_s cn52xx; @@ -934,12 +1977,23 @@ union cvmx_pko_reg_debug2 { struct cvmx_pko_reg_debug2_s cn56xxp1; struct cvmx_pko_reg_debug2_s cn58xx; struct cvmx_pko_reg_debug2_s cn58xxp1; + struct cvmx_pko_reg_debug2_s cn61xx; + struct cvmx_pko_reg_debug2_s cn63xx; + struct cvmx_pko_reg_debug2_s cn63xxp1; + struct cvmx_pko_reg_debug2_s cn66xx; + struct cvmx_pko_reg_debug2_s cn68xx; + struct cvmx_pko_reg_debug2_s cn68xxp1; + struct cvmx_pko_reg_debug2_s cnf71xx; }; union cvmx_pko_reg_debug3 { uint64_t u64; struct cvmx_pko_reg_debug3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t asserts:64; +#else uint64_t asserts:64; +#endif } s; struct cvmx_pko_reg_debug3_s cn50xx; struct cvmx_pko_reg_debug3_s cn52xx; @@ -948,11 +2002,69 @@ union cvmx_pko_reg_debug3 { struct cvmx_pko_reg_debug3_s cn56xxp1; struct cvmx_pko_reg_debug3_s cn58xx; struct cvmx_pko_reg_debug3_s cn58xxp1; + struct cvmx_pko_reg_debug3_s cn61xx; + struct cvmx_pko_reg_debug3_s cn63xx; + struct cvmx_pko_reg_debug3_s cn63xxp1; + struct cvmx_pko_reg_debug3_s cn66xx; + struct cvmx_pko_reg_debug3_s cn68xx; + struct cvmx_pko_reg_debug3_s cn68xxp1; + struct cvmx_pko_reg_debug3_s cnf71xx; +}; + +union cvmx_pko_reg_debug4 { + uint64_t u64; + struct cvmx_pko_reg_debug4_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t asserts:64; +#else + uint64_t asserts:64; +#endif + } s; + struct cvmx_pko_reg_debug4_s cn68xx; + struct cvmx_pko_reg_debug4_s cn68xxp1; }; union cvmx_pko_reg_engine_inflight { uint64_t u64; struct cvmx_pko_reg_engine_inflight_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t engine15:4; + uint64_t engine14:4; + uint64_t engine13:4; + uint64_t engine12:4; + uint64_t engine11:4; + uint64_t engine10:4; + uint64_t engine9:4; + uint64_t engine8:4; + uint64_t engine7:4; + uint64_t engine6:4; + uint64_t engine5:4; + uint64_t engine4:4; + uint64_t engine3:4; + uint64_t engine2:4; + uint64_t engine1:4; + uint64_t engine0:4; +#else + uint64_t engine0:4; + uint64_t engine1:4; + uint64_t engine2:4; + uint64_t engine3:4; + uint64_t engine4:4; + uint64_t engine5:4; + uint64_t engine6:4; + uint64_t engine7:4; + uint64_t engine8:4; + uint64_t engine9:4; + uint64_t engine10:4; + uint64_t engine11:4; + uint64_t engine12:4; + uint64_t engine13:4; + uint64_t engine14:4; + uint64_t engine15:4; +#endif + } s; + struct cvmx_pko_reg_engine_inflight_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t engine9:4; uint64_t engine8:4; @@ -964,78 +2076,380 @@ union cvmx_pko_reg_engine_inflight { uint64_t engine2:4; uint64_t engine1:4; uint64_t engine0:4; +#else + uint64_t engine0:4; + uint64_t engine1:4; + uint64_t engine2:4; + uint64_t engine3:4; + uint64_t engine4:4; + uint64_t engine5:4; + uint64_t engine6:4; + uint64_t engine7:4; + uint64_t engine8:4; + uint64_t engine9:4; + uint64_t reserved_40_63:24; +#endif + } cn52xx; + struct cvmx_pko_reg_engine_inflight_cn52xx cn52xxp1; + struct cvmx_pko_reg_engine_inflight_cn52xx cn56xx; + struct cvmx_pko_reg_engine_inflight_cn52xx cn56xxp1; + struct cvmx_pko_reg_engine_inflight_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_56_63:8; + uint64_t engine13:4; + uint64_t engine12:4; + uint64_t engine11:4; + uint64_t engine10:4; + uint64_t engine9:4; + uint64_t engine8:4; + uint64_t engine7:4; + uint64_t engine6:4; + uint64_t engine5:4; + uint64_t engine4:4; + uint64_t engine3:4; + uint64_t engine2:4; + uint64_t engine1:4; + uint64_t engine0:4; +#else + uint64_t engine0:4; + uint64_t engine1:4; + uint64_t engine2:4; + uint64_t engine3:4; + uint64_t engine4:4; + uint64_t engine5:4; + uint64_t engine6:4; + uint64_t engine7:4; + uint64_t engine8:4; + uint64_t engine9:4; + uint64_t engine10:4; + uint64_t engine11:4; + uint64_t engine12:4; + uint64_t engine13:4; + uint64_t reserved_56_63:8; +#endif + } cn61xx; + struct cvmx_pko_reg_engine_inflight_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_48_63:16; + uint64_t engine11:4; + uint64_t engine10:4; + uint64_t engine9:4; + uint64_t engine8:4; + uint64_t engine7:4; + uint64_t engine6:4; + uint64_t engine5:4; + uint64_t engine4:4; + uint64_t engine3:4; + uint64_t engine2:4; + uint64_t engine1:4; + uint64_t engine0:4; +#else + uint64_t engine0:4; + uint64_t engine1:4; + uint64_t engine2:4; + uint64_t engine3:4; + uint64_t engine4:4; + uint64_t engine5:4; + uint64_t engine6:4; + uint64_t engine7:4; + uint64_t engine8:4; + uint64_t engine9:4; + uint64_t engine10:4; + uint64_t engine11:4; + uint64_t reserved_48_63:16; +#endif + } cn63xx; + struct cvmx_pko_reg_engine_inflight_cn63xx cn63xxp1; + struct cvmx_pko_reg_engine_inflight_cn61xx cn66xx; + struct cvmx_pko_reg_engine_inflight_s cn68xx; + struct cvmx_pko_reg_engine_inflight_s cn68xxp1; + struct cvmx_pko_reg_engine_inflight_cn61xx cnf71xx; +}; + +union cvmx_pko_reg_engine_inflight1 { + uint64_t u64; + struct cvmx_pko_reg_engine_inflight1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t engine19:4; + uint64_t engine18:4; + uint64_t engine17:4; + uint64_t engine16:4; +#else + uint64_t engine16:4; + uint64_t engine17:4; + uint64_t engine18:4; + uint64_t engine19:4; + uint64_t reserved_16_63:48; +#endif } s; - struct cvmx_pko_reg_engine_inflight_s cn52xx; - struct cvmx_pko_reg_engine_inflight_s cn52xxp1; - struct cvmx_pko_reg_engine_inflight_s cn56xx; - struct cvmx_pko_reg_engine_inflight_s cn56xxp1; + struct cvmx_pko_reg_engine_inflight1_s cn68xx; + struct cvmx_pko_reg_engine_inflight1_s cn68xxp1; +}; + +union cvmx_pko_reg_engine_storagex { + uint64_t u64; + struct cvmx_pko_reg_engine_storagex_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t engine15:4; + uint64_t engine14:4; + uint64_t engine13:4; + uint64_t engine12:4; + uint64_t engine11:4; + uint64_t engine10:4; + uint64_t engine9:4; + uint64_t engine8:4; + uint64_t engine7:4; + uint64_t engine6:4; + uint64_t engine5:4; + uint64_t engine4:4; + uint64_t engine3:4; + uint64_t engine2:4; + uint64_t engine1:4; + uint64_t engine0:4; +#else + uint64_t engine0:4; + uint64_t engine1:4; + uint64_t engine2:4; + uint64_t engine3:4; + uint64_t engine4:4; + uint64_t engine5:4; + uint64_t engine6:4; + uint64_t engine7:4; + uint64_t engine8:4; + uint64_t engine9:4; + uint64_t engine10:4; + uint64_t engine11:4; + uint64_t engine12:4; + uint64_t engine13:4; + uint64_t engine14:4; + uint64_t engine15:4; +#endif + } s; + struct cvmx_pko_reg_engine_storagex_s cn68xx; + struct cvmx_pko_reg_engine_storagex_s cn68xxp1; }; union cvmx_pko_reg_engine_thresh { uint64_t u64; struct cvmx_pko_reg_engine_thresh_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t mask:20; +#else + uint64_t mask:20; + uint64_t reserved_20_63:44; +#endif + } s; + struct cvmx_pko_reg_engine_thresh_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t mask:10; - } s; - struct cvmx_pko_reg_engine_thresh_s cn52xx; - struct cvmx_pko_reg_engine_thresh_s cn52xxp1; - struct cvmx_pko_reg_engine_thresh_s cn56xx; - struct cvmx_pko_reg_engine_thresh_s cn56xxp1; +#else + uint64_t mask:10; + uint64_t reserved_10_63:54; +#endif + } cn52xx; + struct cvmx_pko_reg_engine_thresh_cn52xx cn52xxp1; + struct cvmx_pko_reg_engine_thresh_cn52xx cn56xx; + struct cvmx_pko_reg_engine_thresh_cn52xx cn56xxp1; + struct cvmx_pko_reg_engine_thresh_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_14_63:50; + uint64_t mask:14; +#else + uint64_t mask:14; + uint64_t reserved_14_63:50; +#endif + } cn61xx; + struct cvmx_pko_reg_engine_thresh_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t mask:12; +#else + uint64_t mask:12; + uint64_t reserved_12_63:52; +#endif + } cn63xx; + struct cvmx_pko_reg_engine_thresh_cn63xx cn63xxp1; + struct cvmx_pko_reg_engine_thresh_cn61xx cn66xx; + struct cvmx_pko_reg_engine_thresh_s cn68xx; + struct cvmx_pko_reg_engine_thresh_s cn68xxp1; + struct cvmx_pko_reg_engine_thresh_cn61xx cnf71xx; }; union cvmx_pko_reg_error { uint64_t u64; struct cvmx_pko_reg_error_s { - uint64_t reserved_3_63:61; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t loopback:1; uint64_t currzero:1; uint64_t doorbell:1; uint64_t parity:1; +#else + uint64_t parity:1; + uint64_t doorbell:1; + uint64_t currzero:1; + uint64_t loopback:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_pko_reg_error_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t doorbell:1; uint64_t parity:1; +#else + uint64_t parity:1; + uint64_t doorbell:1; + uint64_t reserved_2_63:62; +#endif } cn30xx; struct cvmx_pko_reg_error_cn30xx cn31xx; struct cvmx_pko_reg_error_cn30xx cn38xx; struct cvmx_pko_reg_error_cn30xx cn38xxp2; - struct cvmx_pko_reg_error_s cn50xx; - struct cvmx_pko_reg_error_s cn52xx; - struct cvmx_pko_reg_error_s cn52xxp1; - struct cvmx_pko_reg_error_s cn56xx; - struct cvmx_pko_reg_error_s cn56xxp1; - struct cvmx_pko_reg_error_s cn58xx; - struct cvmx_pko_reg_error_s cn58xxp1; + struct cvmx_pko_reg_error_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_3_63:61; + uint64_t currzero:1; + uint64_t doorbell:1; + uint64_t parity:1; +#else + uint64_t parity:1; + uint64_t doorbell:1; + uint64_t currzero:1; + uint64_t reserved_3_63:61; +#endif + } cn50xx; + struct cvmx_pko_reg_error_cn50xx cn52xx; + struct cvmx_pko_reg_error_cn50xx cn52xxp1; + struct cvmx_pko_reg_error_cn50xx cn56xx; + struct cvmx_pko_reg_error_cn50xx cn56xxp1; + struct cvmx_pko_reg_error_cn50xx cn58xx; + struct cvmx_pko_reg_error_cn50xx cn58xxp1; + struct cvmx_pko_reg_error_cn50xx cn61xx; + struct cvmx_pko_reg_error_cn50xx cn63xx; + struct cvmx_pko_reg_error_cn50xx cn63xxp1; + struct cvmx_pko_reg_error_cn50xx cn66xx; + struct cvmx_pko_reg_error_s cn68xx; + struct cvmx_pko_reg_error_s cn68xxp1; + struct cvmx_pko_reg_error_cn50xx cnf71xx; }; union cvmx_pko_reg_flags { uint64_t u64; struct cvmx_pko_reg_flags_s { - uint64_t reserved_4_63:60; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_9_63:55; + uint64_t dis_perf3:1; + uint64_t dis_perf2:1; + uint64_t dis_perf1:1; + uint64_t dis_perf0:1; + uint64_t ena_throttle:1; uint64_t reset:1; uint64_t store_be:1; uint64_t ena_dwb:1; uint64_t ena_pko:1; +#else + uint64_t ena_pko:1; + uint64_t ena_dwb:1; + uint64_t store_be:1; + uint64_t reset:1; + uint64_t ena_throttle:1; + uint64_t dis_perf0:1; + uint64_t dis_perf1:1; + uint64_t dis_perf2:1; + uint64_t dis_perf3:1; + uint64_t reserved_9_63:55; +#endif } s; - struct cvmx_pko_reg_flags_s cn30xx; - struct cvmx_pko_reg_flags_s cn31xx; - struct cvmx_pko_reg_flags_s cn38xx; - struct cvmx_pko_reg_flags_s cn38xxp2; - struct cvmx_pko_reg_flags_s cn50xx; - struct cvmx_pko_reg_flags_s cn52xx; - struct cvmx_pko_reg_flags_s cn52xxp1; - struct cvmx_pko_reg_flags_s cn56xx; - struct cvmx_pko_reg_flags_s cn56xxp1; - struct cvmx_pko_reg_flags_s cn58xx; - struct cvmx_pko_reg_flags_s cn58xxp1; + struct cvmx_pko_reg_flags_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t reset:1; + uint64_t store_be:1; + uint64_t ena_dwb:1; + uint64_t ena_pko:1; +#else + uint64_t ena_pko:1; + uint64_t ena_dwb:1; + uint64_t store_be:1; + uint64_t reset:1; + uint64_t reserved_4_63:60; +#endif + } cn30xx; + struct cvmx_pko_reg_flags_cn30xx cn31xx; + struct cvmx_pko_reg_flags_cn30xx cn38xx; + struct cvmx_pko_reg_flags_cn30xx cn38xxp2; + struct cvmx_pko_reg_flags_cn30xx cn50xx; + struct cvmx_pko_reg_flags_cn30xx cn52xx; + struct cvmx_pko_reg_flags_cn30xx cn52xxp1; + struct cvmx_pko_reg_flags_cn30xx cn56xx; + struct cvmx_pko_reg_flags_cn30xx cn56xxp1; + struct cvmx_pko_reg_flags_cn30xx cn58xx; + struct cvmx_pko_reg_flags_cn30xx cn58xxp1; + struct cvmx_pko_reg_flags_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_9_63:55; + uint64_t dis_perf3:1; + uint64_t dis_perf2:1; + uint64_t reserved_4_6:3; + uint64_t reset:1; + uint64_t store_be:1; + uint64_t ena_dwb:1; + uint64_t ena_pko:1; +#else + uint64_t ena_pko:1; + uint64_t ena_dwb:1; + uint64_t store_be:1; + uint64_t reset:1; + uint64_t reserved_4_6:3; + uint64_t dis_perf2:1; + uint64_t dis_perf3:1; + uint64_t reserved_9_63:55; +#endif + } cn61xx; + struct cvmx_pko_reg_flags_cn30xx cn63xx; + struct cvmx_pko_reg_flags_cn30xx cn63xxp1; + struct cvmx_pko_reg_flags_cn61xx cn66xx; + struct cvmx_pko_reg_flags_s cn68xx; + struct cvmx_pko_reg_flags_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_7_63:57; + uint64_t dis_perf1:1; + uint64_t dis_perf0:1; + uint64_t ena_throttle:1; + uint64_t reset:1; + uint64_t store_be:1; + uint64_t ena_dwb:1; + uint64_t ena_pko:1; +#else + uint64_t ena_pko:1; + uint64_t ena_dwb:1; + uint64_t store_be:1; + uint64_t reset:1; + uint64_t ena_throttle:1; + uint64_t dis_perf0:1; + uint64_t dis_perf1:1; + uint64_t reserved_7_63:57; +#endif + } cn68xxp1; + struct cvmx_pko_reg_flags_cn61xx cnf71xx; }; union cvmx_pko_reg_gmx_port_mode { uint64_t u64; struct cvmx_pko_reg_gmx_port_mode_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mode1:3; uint64_t mode0:3; +#else + uint64_t mode0:3; + uint64_t mode1:3; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_pko_reg_gmx_port_mode_s cn30xx; struct cvmx_pko_reg_gmx_port_mode_s cn31xx; @@ -1048,38 +2462,223 @@ union cvmx_pko_reg_gmx_port_mode { struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1; struct cvmx_pko_reg_gmx_port_mode_s cn58xx; struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1; + struct cvmx_pko_reg_gmx_port_mode_s cn61xx; + struct cvmx_pko_reg_gmx_port_mode_s cn63xx; + struct cvmx_pko_reg_gmx_port_mode_s cn63xxp1; + struct cvmx_pko_reg_gmx_port_mode_s cn66xx; + struct cvmx_pko_reg_gmx_port_mode_s cnf71xx; }; union cvmx_pko_reg_int_mask { uint64_t u64; struct cvmx_pko_reg_int_mask_s { - uint64_t reserved_3_63:61; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t loopback:1; uint64_t currzero:1; uint64_t doorbell:1; uint64_t parity:1; +#else + uint64_t parity:1; + uint64_t doorbell:1; + uint64_t currzero:1; + uint64_t loopback:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_pko_reg_int_mask_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t doorbell:1; uint64_t parity:1; +#else + uint64_t parity:1; + uint64_t doorbell:1; + uint64_t reserved_2_63:62; +#endif } cn30xx; struct cvmx_pko_reg_int_mask_cn30xx cn31xx; struct cvmx_pko_reg_int_mask_cn30xx cn38xx; struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2; - struct cvmx_pko_reg_int_mask_s cn50xx; - struct cvmx_pko_reg_int_mask_s cn52xx; - struct cvmx_pko_reg_int_mask_s cn52xxp1; - struct cvmx_pko_reg_int_mask_s cn56xx; - struct cvmx_pko_reg_int_mask_s cn56xxp1; - struct cvmx_pko_reg_int_mask_s cn58xx; - struct cvmx_pko_reg_int_mask_s cn58xxp1; + struct cvmx_pko_reg_int_mask_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_3_63:61; + uint64_t currzero:1; + uint64_t doorbell:1; + uint64_t parity:1; +#else + uint64_t parity:1; + uint64_t doorbell:1; + uint64_t currzero:1; + uint64_t reserved_3_63:61; +#endif + } cn50xx; + struct cvmx_pko_reg_int_mask_cn50xx cn52xx; + struct cvmx_pko_reg_int_mask_cn50xx cn52xxp1; + struct cvmx_pko_reg_int_mask_cn50xx cn56xx; + struct cvmx_pko_reg_int_mask_cn50xx cn56xxp1; + struct cvmx_pko_reg_int_mask_cn50xx cn58xx; + struct cvmx_pko_reg_int_mask_cn50xx cn58xxp1; + struct cvmx_pko_reg_int_mask_cn50xx cn61xx; + struct cvmx_pko_reg_int_mask_cn50xx cn63xx; + struct cvmx_pko_reg_int_mask_cn50xx cn63xxp1; + struct cvmx_pko_reg_int_mask_cn50xx cn66xx; + struct cvmx_pko_reg_int_mask_s cn68xx; + struct cvmx_pko_reg_int_mask_s cn68xxp1; + struct cvmx_pko_reg_int_mask_cn50xx cnf71xx; +}; + +union cvmx_pko_reg_loopback_bpid { + uint64_t u64; + struct cvmx_pko_reg_loopback_bpid_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_59_63:5; + uint64_t bpid7:6; + uint64_t reserved_52_52:1; + uint64_t bpid6:6; + uint64_t reserved_45_45:1; + uint64_t bpid5:6; + uint64_t reserved_38_38:1; + uint64_t bpid4:6; + uint64_t reserved_31_31:1; + uint64_t bpid3:6; + uint64_t reserved_24_24:1; + uint64_t bpid2:6; + uint64_t reserved_17_17:1; + uint64_t bpid1:6; + uint64_t reserved_10_10:1; + uint64_t bpid0:6; + uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t bpid0:6; + uint64_t reserved_10_10:1; + uint64_t bpid1:6; + uint64_t reserved_17_17:1; + uint64_t bpid2:6; + uint64_t reserved_24_24:1; + uint64_t bpid3:6; + uint64_t reserved_31_31:1; + uint64_t bpid4:6; + uint64_t reserved_38_38:1; + uint64_t bpid5:6; + uint64_t reserved_45_45:1; + uint64_t bpid6:6; + uint64_t reserved_52_52:1; + uint64_t bpid7:6; + uint64_t reserved_59_63:5; +#endif + } s; + struct cvmx_pko_reg_loopback_bpid_s cn68xx; + struct cvmx_pko_reg_loopback_bpid_s cn68xxp1; +}; + +union cvmx_pko_reg_loopback_pkind { + uint64_t u64; + struct cvmx_pko_reg_loopback_pkind_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_59_63:5; + uint64_t pkind7:6; + uint64_t reserved_52_52:1; + uint64_t pkind6:6; + uint64_t reserved_45_45:1; + uint64_t pkind5:6; + uint64_t reserved_38_38:1; + uint64_t pkind4:6; + uint64_t reserved_31_31:1; + uint64_t pkind3:6; + uint64_t reserved_24_24:1; + uint64_t pkind2:6; + uint64_t reserved_17_17:1; + uint64_t pkind1:6; + uint64_t reserved_10_10:1; + uint64_t pkind0:6; + uint64_t num_ports:4; +#else + uint64_t num_ports:4; + uint64_t pkind0:6; + uint64_t reserved_10_10:1; + uint64_t pkind1:6; + uint64_t reserved_17_17:1; + uint64_t pkind2:6; + uint64_t reserved_24_24:1; + uint64_t pkind3:6; + uint64_t reserved_31_31:1; + uint64_t pkind4:6; + uint64_t reserved_38_38:1; + uint64_t pkind5:6; + uint64_t reserved_45_45:1; + uint64_t pkind6:6; + uint64_t reserved_52_52:1; + uint64_t pkind7:6; + uint64_t reserved_59_63:5; +#endif + } s; + struct cvmx_pko_reg_loopback_pkind_s cn68xx; + struct cvmx_pko_reg_loopback_pkind_s cn68xxp1; +}; + +union cvmx_pko_reg_min_pkt { + uint64_t u64; + struct cvmx_pko_reg_min_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t size7:8; + uint64_t size6:8; + uint64_t size5:8; + uint64_t size4:8; + uint64_t size3:8; + uint64_t size2:8; + uint64_t size1:8; + uint64_t size0:8; +#else + uint64_t size0:8; + uint64_t size1:8; + uint64_t size2:8; + uint64_t size3:8; + uint64_t size4:8; + uint64_t size5:8; + uint64_t size6:8; + uint64_t size7:8; +#endif + } s; + struct cvmx_pko_reg_min_pkt_s cn68xx; + struct cvmx_pko_reg_min_pkt_s cn68xxp1; +}; + +union cvmx_pko_reg_preempt { + uint64_t u64; + struct cvmx_pko_reg_preempt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_16_63:48; + uint64_t min_size:16; +#else + uint64_t min_size:16; + uint64_t reserved_16_63:48; +#endif + } s; + struct cvmx_pko_reg_preempt_s cn52xx; + struct cvmx_pko_reg_preempt_s cn52xxp1; + struct cvmx_pko_reg_preempt_s cn56xx; + struct cvmx_pko_reg_preempt_s cn56xxp1; + struct cvmx_pko_reg_preempt_s cn61xx; + struct cvmx_pko_reg_preempt_s cn63xx; + struct cvmx_pko_reg_preempt_s cn63xxp1; + struct cvmx_pko_reg_preempt_s cn66xx; + struct cvmx_pko_reg_preempt_s cn68xx; + struct cvmx_pko_reg_preempt_s cn68xxp1; + struct cvmx_pko_reg_preempt_s cnf71xx; }; union cvmx_pko_reg_queue_mode { uint64_t u64; struct cvmx_pko_reg_queue_mode_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t mode:2; +#else + uint64_t mode:2; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_pko_reg_queue_mode_s cn30xx; struct cvmx_pko_reg_queue_mode_s cn31xx; @@ -1092,14 +2691,53 @@ union cvmx_pko_reg_queue_mode { struct cvmx_pko_reg_queue_mode_s cn56xxp1; struct cvmx_pko_reg_queue_mode_s cn58xx; struct cvmx_pko_reg_queue_mode_s cn58xxp1; + struct cvmx_pko_reg_queue_mode_s cn61xx; + struct cvmx_pko_reg_queue_mode_s cn63xx; + struct cvmx_pko_reg_queue_mode_s cn63xxp1; + struct cvmx_pko_reg_queue_mode_s cn66xx; + struct cvmx_pko_reg_queue_mode_s cn68xx; + struct cvmx_pko_reg_queue_mode_s cn68xxp1; + struct cvmx_pko_reg_queue_mode_s cnf71xx; +}; + +union cvmx_pko_reg_queue_preempt { + uint64_t u64; + struct cvmx_pko_reg_queue_preempt_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_2_63:62; + uint64_t preemptee:1; + uint64_t preempter:1; +#else + uint64_t preempter:1; + uint64_t preemptee:1; + uint64_t reserved_2_63:62; +#endif + } s; + struct cvmx_pko_reg_queue_preempt_s cn52xx; + struct cvmx_pko_reg_queue_preempt_s cn52xxp1; + struct cvmx_pko_reg_queue_preempt_s cn56xx; + struct cvmx_pko_reg_queue_preempt_s cn56xxp1; + struct cvmx_pko_reg_queue_preempt_s cn61xx; + struct cvmx_pko_reg_queue_preempt_s cn63xx; + struct cvmx_pko_reg_queue_preempt_s cn63xxp1; + struct cvmx_pko_reg_queue_preempt_s cn66xx; + struct cvmx_pko_reg_queue_preempt_s cn68xx; + struct cvmx_pko_reg_queue_preempt_s cn68xxp1; + struct cvmx_pko_reg_queue_preempt_s cnf71xx; }; union cvmx_pko_reg_queue_ptrs1 { uint64_t u64; struct cvmx_pko_reg_queue_ptrs1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t idx3:1; uint64_t qid7:1; +#else + uint64_t qid7:1; + uint64_t idx3:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_pko_reg_queue_ptrs1_s cn50xx; struct cvmx_pko_reg_queue_ptrs1_s cn52xx; @@ -1108,14 +2746,25 @@ union cvmx_pko_reg_queue_ptrs1 { struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1; struct cvmx_pko_reg_queue_ptrs1_s cn58xx; struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1; + struct cvmx_pko_reg_queue_ptrs1_s cn61xx; + struct cvmx_pko_reg_queue_ptrs1_s cn63xx; + struct cvmx_pko_reg_queue_ptrs1_s cn63xxp1; + struct cvmx_pko_reg_queue_ptrs1_s cn66xx; + struct cvmx_pko_reg_queue_ptrs1_s cnf71xx; }; union cvmx_pko_reg_read_idx { uint64_t u64; struct cvmx_pko_reg_read_idx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t inc:8; uint64_t index:8; +#else + uint64_t index:8; + uint64_t inc:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_pko_reg_read_idx_s cn30xx; struct cvmx_pko_reg_read_idx_s cn31xx; @@ -1128,6 +2777,48 @@ union cvmx_pko_reg_read_idx { struct cvmx_pko_reg_read_idx_s cn56xxp1; struct cvmx_pko_reg_read_idx_s cn58xx; struct cvmx_pko_reg_read_idx_s cn58xxp1; + struct cvmx_pko_reg_read_idx_s cn61xx; + struct cvmx_pko_reg_read_idx_s cn63xx; + struct cvmx_pko_reg_read_idx_s cn63xxp1; + struct cvmx_pko_reg_read_idx_s cn66xx; + struct cvmx_pko_reg_read_idx_s cn68xx; + struct cvmx_pko_reg_read_idx_s cn68xxp1; + struct cvmx_pko_reg_read_idx_s cnf71xx; +}; + +union cvmx_pko_reg_throttle { + uint64_t u64; + struct cvmx_pko_reg_throttle_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_32_63:32; + uint64_t int_mask:32; +#else + uint64_t int_mask:32; + uint64_t reserved_32_63:32; +#endif + } s; + struct cvmx_pko_reg_throttle_s cn68xx; + struct cvmx_pko_reg_throttle_s cn68xxp1; +}; + +union cvmx_pko_reg_timestamp { + uint64_t u64; + struct cvmx_pko_reg_timestamp_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_4_63:60; + uint64_t wqe_word:4; +#else + uint64_t wqe_word:4; + uint64_t reserved_4_63:60; +#endif + } s; + struct cvmx_pko_reg_timestamp_s cn61xx; + struct cvmx_pko_reg_timestamp_s cn63xx; + struct cvmx_pko_reg_timestamp_s cn63xxp1; + struct cvmx_pko_reg_timestamp_s cn66xx; + struct cvmx_pko_reg_timestamp_s cn68xx; + struct cvmx_pko_reg_timestamp_s cn68xxp1; + struct cvmx_pko_reg_timestamp_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h index de3412aada5..f7d2a671884 100644 --- a/arch/mips/include/asm/octeon/cvmx-pko.h +++ b/arch/mips/include/asm/octeon/cvmx-pko.h @@ -58,10 +58,10 @@ #ifndef __CVMX_PKO_H__ #define __CVMX_PKO_H__ -#include "cvmx-fpa.h" -#include "cvmx-pow.h" -#include "cvmx-cmd-queue.h" -#include "cvmx-pko-defs.h" +#include <asm/octeon/cvmx-fpa.h> +#include <asm/octeon/cvmx-pow.h> +#include <asm/octeon/cvmx-cmd-queue.h> +#include <asm/octeon/cvmx-pko-defs.h> /* Adjust the command buffer size by 1 word so that in the case of using only * two word PKO commands no command words stradle buffers. The useful values @@ -69,16 +69,16 @@ #define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1) #define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256 -#define CVMX_PKO_MAX_OUTPUT_QUEUES ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \ +#define CVMX_PKO_MAX_OUTPUT_QUEUES ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \ OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \ OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \ (OCTEON_IS_MODEL(OCTEON_CN58XX) || \ OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128) -#define CVMX_PKO_NUM_OUTPUT_PORTS 40 +#define CVMX_PKO_NUM_OUTPUT_PORTS 40 /* use this for queues that are not used */ #define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63 -#define CVMX_PKO_QUEUE_STATIC_PRIORITY 9 -#define CVMX_PKO_ILLEGAL_QUEUE 0xFFFF +#define CVMX_PKO_QUEUE_STATIC_PRIORITY 9 +#define CVMX_PKO_ILLEGAL_QUEUE 0xFFFF #define CVMX_PKO_MAX_QUEUE_DEPTH 0 typedef enum { @@ -269,13 +269,13 @@ extern void cvmx_pko_shutdown(void); /** * Configure a output port and the associated queues for use. * - * @port: Port to configure. + * @port: Port to configure. * @base_queue: First queue number to associate with this port. * @num_queues: Number of queues t oassociate with this port - * @priority: Array of priority levels for each queue. Values are - * allowed to be 1-8. A value of 8 get 8 times the traffic - * of a value of 1. There must be num_queues elements in the - * array. + * @priority: Array of priority levels for each queue. Values are + * allowed to be 1-8. A value of 8 get 8 times the traffic + * of a value of 1. There must be num_queues elements in the + * array. */ extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, @@ -285,7 +285,7 @@ extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, /** * Ring the packet output doorbell. This tells the packet * output hardware that "len" command words have been added - * to its pending list. This command includes the required + * to its pending list. This command includes the required * CVMX_SYNCWS before the doorbell ring. * * @port: Port the packet is for @@ -322,18 +322,18 @@ static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue, * The use_locking parameter allows the caller to use three * possible locking modes. * - CVMX_PKO_LOCK_NONE - * - PKO doesn't do any locking. It is the responsibility - * of the application to make sure that no other core - * is accessing the same queue at the same time. + * - PKO doesn't do any locking. It is the responsibility + * of the application to make sure that no other core + * is accessing the same queue at the same time. * - CVMX_PKO_LOCK_ATOMIC_TAG - * - PKO performs an atomic tagswitch to insure exclusive - * access to the output queue. This will maintain - * packet ordering on output. + * - PKO performs an atomic tagswitch to insure exclusive + * access to the output queue. This will maintain + * packet ordering on output. * - CVMX_PKO_LOCK_CMD_QUEUE - * - PKO uses the common command queue locks to insure - * exclusive access to the output queue. This is a - * memory based ll/sc. This is the most portable - * locking mechanism. + * - PKO uses the common command queue locks to insure + * exclusive access to the output queue. This is a + * memory based ll/sc. This is the most portable + * locking mechanism. * * NOTE: If atomic locking is used, the POW entry CANNOT be * descheduled, as it does not contain a valid WQE pointer. @@ -341,7 +341,7 @@ static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue, * @port: Port to send it on * @queue: Queue to use * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or - * CVMX_PKO_LOCK_CMD_QUEUE + * CVMX_PKO_LOCK_CMD_QUEUE */ static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue, @@ -351,11 +351,11 @@ static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue, /* * Must do a full switch here to handle all cases. We * use a fake WQE pointer, as the POW does not access - * this memory. The WQE pointer and group are only + * this memory. The WQE pointer and group are only * used if this work is descheduled, which is not * supported by the * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish - * combination. Note that this is a special case in + * combination. Note that this is a special case in * which these fake values can be used - this is not a * general technique. */ @@ -377,10 +377,10 @@ static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue, * @port: Port to send it on * @queue: Queue to use * @pko_command: - * PKO HW command word + * PKO HW command word * @packet: Packet to send * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or - * CVMX_PKO_LOCK_CMD_QUEUE + * CVMX_PKO_LOCK_CMD_QUEUE * * Returns returns CVMX_PKO_SUCCESS on success, or error code on * failure of output @@ -418,12 +418,12 @@ static inline cvmx_pko_status_t cvmx_pko_send_packet_finish( * @port: Port to send it on * @queue: Queue to use * @pko_command: - * PKO HW command word + * PKO HW command word * @packet: Packet to send * @addr: Plysical address of a work queue entry or physical address - * to zero on complete. + * to zero on complete. * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or - * CVMX_PKO_LOCK_CMD_QUEUE + * CVMX_PKO_LOCK_CMD_QUEUE * * Returns returns CVMX_PKO_SUCCESS on success, or error code on * failure of output @@ -588,7 +588,7 @@ static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear, * @port: Port to rate limit * @packets_s: Maximum packet/sec * @burst: Maximum number of packets to burst in a row before rate - * limiting cuts in. + * limiting cuts in. * * Returns Zero on success, negative on failure */ @@ -601,7 +601,7 @@ extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst); * @port: Port to rate limit * @bits_s: PKO rate limit in bits/sec * @burst: Maximum number of bits to burst before rate - * limiting cuts in. + * limiting cuts in. * * Returns Zero on success, negative on failure */ diff --git a/arch/mips/include/asm/octeon/cvmx-pow-defs.h b/arch/mips/include/asm/octeon/cvmx-pow-defs.h index 39fd75b03f7..9020ef44373 100644 --- a/arch/mips/include/asm/octeon/cvmx-pow-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pow-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -55,11 +55,18 @@ union cvmx_pow_bist_stat { uint64_t u64; struct cvmx_pow_bist_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pp:16; uint64_t reserved_0_15:16; +#else + uint64_t reserved_0_15:16; + uint64_t pp:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_bist_stat_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t pp:1; uint64_t reserved_9_15:7; @@ -72,8 +79,23 @@ union cvmx_pow_bist_stat { uint64_t nbr0:1; uint64_t pend:1; uint64_t adr:1; +#else + uint64_t adr:1; + uint64_t pend:1; + uint64_t nbr0:1; + uint64_t nbr1:1; + uint64_t fidx:1; + uint64_t index:1; + uint64_t nbt0:1; + uint64_t nbt1:1; + uint64_t cam:1; + uint64_t reserved_9_15:7; + uint64_t pp:1; + uint64_t reserved_17_63:47; +#endif } cn30xx; struct cvmx_pow_bist_stat_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t pp:2; uint64_t reserved_9_15:7; @@ -86,8 +108,23 @@ union cvmx_pow_bist_stat { uint64_t nbr0:1; uint64_t pend:1; uint64_t adr:1; +#else + uint64_t adr:1; + uint64_t pend:1; + uint64_t nbr0:1; + uint64_t nbr1:1; + uint64_t fidx:1; + uint64_t index:1; + uint64_t nbt0:1; + uint64_t nbt1:1; + uint64_t cam:1; + uint64_t reserved_9_15:7; + uint64_t pp:2; + uint64_t reserved_18_63:46; +#endif } cn31xx; struct cvmx_pow_bist_stat_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t pp:16; uint64_t reserved_10_15:6; @@ -101,10 +138,26 @@ union cvmx_pow_bist_stat { uint64_t pend0:1; uint64_t adr1:1; uint64_t adr0:1; +#else + uint64_t adr0:1; + uint64_t adr1:1; + uint64_t pend0:1; + uint64_t pend1:1; + uint64_t nbr0:1; + uint64_t nbr1:1; + uint64_t fidx:1; + uint64_t index:1; + uint64_t nbt:1; + uint64_t cam:1; + uint64_t reserved_10_15:6; + uint64_t pp:16; + uint64_t reserved_32_63:32; +#endif } cn38xx; struct cvmx_pow_bist_stat_cn38xx cn38xxp2; struct cvmx_pow_bist_stat_cn31xx cn50xx; struct cvmx_pow_bist_stat_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t pp:4; uint64_t reserved_9_15:7; @@ -117,9 +170,24 @@ union cvmx_pow_bist_stat { uint64_t nbr0:1; uint64_t pend:1; uint64_t adr:1; +#else + uint64_t adr:1; + uint64_t pend:1; + uint64_t nbr0:1; + uint64_t nbr1:1; + uint64_t fidx:1; + uint64_t index:1; + uint64_t nbt0:1; + uint64_t nbt1:1; + uint64_t cam:1; + uint64_t reserved_9_15:7; + uint64_t pp:4; + uint64_t reserved_20_63:44; +#endif } cn52xx; struct cvmx_pow_bist_stat_cn52xx cn52xxp1; struct cvmx_pow_bist_stat_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t pp:12; uint64_t reserved_10_15:6; @@ -133,11 +201,52 @@ union cvmx_pow_bist_stat { uint64_t pend0:1; uint64_t adr1:1; uint64_t adr0:1; +#else + uint64_t adr0:1; + uint64_t adr1:1; + uint64_t pend0:1; + uint64_t pend1:1; + uint64_t nbr0:1; + uint64_t nbr1:1; + uint64_t fidx:1; + uint64_t index:1; + uint64_t nbt:1; + uint64_t cam:1; + uint64_t reserved_10_15:6; + uint64_t pp:12; + uint64_t reserved_28_63:36; +#endif } cn56xx; struct cvmx_pow_bist_stat_cn56xx cn56xxp1; struct cvmx_pow_bist_stat_cn38xx cn58xx; struct cvmx_pow_bist_stat_cn38xx cn58xxp1; + struct cvmx_pow_bist_stat_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_20_63:44; + uint64_t pp:4; + uint64_t reserved_12_15:4; + uint64_t cam:1; + uint64_t nbr:3; + uint64_t nbt:4; + uint64_t index:1; + uint64_t fidx:1; + uint64_t pend:1; + uint64_t adr:1; +#else + uint64_t adr:1; + uint64_t pend:1; + uint64_t fidx:1; + uint64_t index:1; + uint64_t nbt:4; + uint64_t nbr:3; + uint64_t cam:1; + uint64_t reserved_12_15:4; + uint64_t pp:4; + uint64_t reserved_20_63:44; +#endif + } cn61xx; struct cvmx_pow_bist_stat_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t pp:6; uint64_t reserved_12_15:4; @@ -148,15 +257,58 @@ union cvmx_pow_bist_stat { uint64_t fidx:1; uint64_t pend:1; uint64_t adr:1; +#else + uint64_t adr:1; + uint64_t pend:1; + uint64_t fidx:1; + uint64_t index:1; + uint64_t nbt:4; + uint64_t nbr:3; + uint64_t cam:1; + uint64_t reserved_12_15:4; + uint64_t pp:6; + uint64_t reserved_22_63:42; +#endif } cn63xx; struct cvmx_pow_bist_stat_cn63xx cn63xxp1; + struct cvmx_pow_bist_stat_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_26_63:38; + uint64_t pp:10; + uint64_t reserved_12_15:4; + uint64_t cam:1; + uint64_t nbr:3; + uint64_t nbt:4; + uint64_t index:1; + uint64_t fidx:1; + uint64_t pend:1; + uint64_t adr:1; +#else + uint64_t adr:1; + uint64_t pend:1; + uint64_t fidx:1; + uint64_t index:1; + uint64_t nbt:4; + uint64_t nbr:3; + uint64_t cam:1; + uint64_t reserved_12_15:4; + uint64_t pp:10; + uint64_t reserved_26_63:38; +#endif + } cn66xx; + struct cvmx_pow_bist_stat_cn61xx cnf71xx; }; union cvmx_pow_ds_pc { uint64_t u64; struct cvmx_pow_ds_pc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ds_pc:32; +#else + uint64_t ds_pc:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_ds_pc_s cn30xx; struct cvmx_pow_ds_pc_s cn31xx; @@ -169,13 +321,17 @@ union cvmx_pow_ds_pc { struct cvmx_pow_ds_pc_s cn56xxp1; struct cvmx_pow_ds_pc_s cn58xx; struct cvmx_pow_ds_pc_s cn58xxp1; + struct cvmx_pow_ds_pc_s cn61xx; struct cvmx_pow_ds_pc_s cn63xx; struct cvmx_pow_ds_pc_s cn63xxp1; + struct cvmx_pow_ds_pc_s cn66xx; + struct cvmx_pow_ds_pc_s cnf71xx; }; union cvmx_pow_ecc_err { uint64_t u64; struct cvmx_pow_ecc_err_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t iop_ie:13; uint64_t reserved_29_31:3; @@ -189,9 +345,25 @@ union cvmx_pow_ecc_err { uint64_t sbe_ie:1; uint64_t dbe:1; uint64_t sbe:1; +#else + uint64_t sbe:1; + uint64_t dbe:1; + uint64_t sbe_ie:1; + uint64_t dbe_ie:1; + uint64_t syn:5; + uint64_t reserved_9_11:3; + uint64_t rpe:1; + uint64_t rpe_ie:1; + uint64_t reserved_14_15:2; + uint64_t iop:13; + uint64_t reserved_29_31:3; + uint64_t iop_ie:13; + uint64_t reserved_45_63:19; +#endif } s; struct cvmx_pow_ecc_err_s cn30xx; struct cvmx_pow_ecc_err_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t rpe_ie:1; uint64_t rpe:1; @@ -201,6 +373,17 @@ union cvmx_pow_ecc_err { uint64_t sbe_ie:1; uint64_t dbe:1; uint64_t sbe:1; +#else + uint64_t sbe:1; + uint64_t dbe:1; + uint64_t sbe_ie:1; + uint64_t dbe_ie:1; + uint64_t syn:5; + uint64_t reserved_9_11:3; + uint64_t rpe:1; + uint64_t rpe_ie:1; + uint64_t reserved_14_63:50; +#endif } cn31xx; struct cvmx_pow_ecc_err_s cn38xx; struct cvmx_pow_ecc_err_cn31xx cn38xxp2; @@ -211,16 +394,25 @@ union cvmx_pow_ecc_err { struct cvmx_pow_ecc_err_s cn56xxp1; struct cvmx_pow_ecc_err_s cn58xx; struct cvmx_pow_ecc_err_s cn58xxp1; + struct cvmx_pow_ecc_err_s cn61xx; struct cvmx_pow_ecc_err_s cn63xx; struct cvmx_pow_ecc_err_s cn63xxp1; + struct cvmx_pow_ecc_err_s cn66xx; + struct cvmx_pow_ecc_err_s cnf71xx; }; union cvmx_pow_int_ctl { uint64_t u64; struct cvmx_pow_int_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t pfr_dis:1; uint64_t nbr_thr:5; +#else + uint64_t nbr_thr:5; + uint64_t pfr_dis:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_pow_int_ctl_s cn30xx; struct cvmx_pow_int_ctl_s cn31xx; @@ -233,15 +425,23 @@ union cvmx_pow_int_ctl { struct cvmx_pow_int_ctl_s cn56xxp1; struct cvmx_pow_int_ctl_s cn58xx; struct cvmx_pow_int_ctl_s cn58xxp1; + struct cvmx_pow_int_ctl_s cn61xx; struct cvmx_pow_int_ctl_s cn63xx; struct cvmx_pow_int_ctl_s cn63xxp1; + struct cvmx_pow_int_ctl_s cn66xx; + struct cvmx_pow_int_ctl_s cnf71xx; }; union cvmx_pow_iq_cntx { uint64_t u64; struct cvmx_pow_iq_cntx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iq_cnt:32; +#else + uint64_t iq_cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_iq_cntx_s cn30xx; struct cvmx_pow_iq_cntx_s cn31xx; @@ -254,15 +454,23 @@ union cvmx_pow_iq_cntx { struct cvmx_pow_iq_cntx_s cn56xxp1; struct cvmx_pow_iq_cntx_s cn58xx; struct cvmx_pow_iq_cntx_s cn58xxp1; + struct cvmx_pow_iq_cntx_s cn61xx; struct cvmx_pow_iq_cntx_s cn63xx; struct cvmx_pow_iq_cntx_s cn63xxp1; + struct cvmx_pow_iq_cntx_s cn66xx; + struct cvmx_pow_iq_cntx_s cnf71xx; }; union cvmx_pow_iq_com_cnt { uint64_t u64; struct cvmx_pow_iq_com_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iq_cnt:32; +#else + uint64_t iq_cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_iq_com_cnt_s cn30xx; struct cvmx_pow_iq_com_cnt_s cn31xx; @@ -275,90 +483,150 @@ union cvmx_pow_iq_com_cnt { struct cvmx_pow_iq_com_cnt_s cn56xxp1; struct cvmx_pow_iq_com_cnt_s cn58xx; struct cvmx_pow_iq_com_cnt_s cn58xxp1; + struct cvmx_pow_iq_com_cnt_s cn61xx; struct cvmx_pow_iq_com_cnt_s cn63xx; struct cvmx_pow_iq_com_cnt_s cn63xxp1; + struct cvmx_pow_iq_com_cnt_s cn66xx; + struct cvmx_pow_iq_com_cnt_s cnf71xx; }; union cvmx_pow_iq_int { uint64_t u64; struct cvmx_pow_iq_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t iq_int:8; +#else + uint64_t iq_int:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_pow_iq_int_s cn52xx; struct cvmx_pow_iq_int_s cn52xxp1; struct cvmx_pow_iq_int_s cn56xx; struct cvmx_pow_iq_int_s cn56xxp1; + struct cvmx_pow_iq_int_s cn61xx; struct cvmx_pow_iq_int_s cn63xx; struct cvmx_pow_iq_int_s cn63xxp1; + struct cvmx_pow_iq_int_s cn66xx; + struct cvmx_pow_iq_int_s cnf71xx; }; union cvmx_pow_iq_int_en { uint64_t u64; struct cvmx_pow_iq_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t int_en:8; +#else + uint64_t int_en:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_pow_iq_int_en_s cn52xx; struct cvmx_pow_iq_int_en_s cn52xxp1; struct cvmx_pow_iq_int_en_s cn56xx; struct cvmx_pow_iq_int_en_s cn56xxp1; + struct cvmx_pow_iq_int_en_s cn61xx; struct cvmx_pow_iq_int_en_s cn63xx; struct cvmx_pow_iq_int_en_s cn63xxp1; + struct cvmx_pow_iq_int_en_s cn66xx; + struct cvmx_pow_iq_int_en_s cnf71xx; }; union cvmx_pow_iq_thrx { uint64_t u64; struct cvmx_pow_iq_thrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iq_thr:32; +#else + uint64_t iq_thr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_iq_thrx_s cn52xx; struct cvmx_pow_iq_thrx_s cn52xxp1; struct cvmx_pow_iq_thrx_s cn56xx; struct cvmx_pow_iq_thrx_s cn56xxp1; + struct cvmx_pow_iq_thrx_s cn61xx; struct cvmx_pow_iq_thrx_s cn63xx; struct cvmx_pow_iq_thrx_s cn63xxp1; + struct cvmx_pow_iq_thrx_s cn66xx; + struct cvmx_pow_iq_thrx_s cnf71xx; }; union cvmx_pow_nos_cnt { uint64_t u64; struct cvmx_pow_nos_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t nos_cnt:12; +#else + uint64_t nos_cnt:12; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_pow_nos_cnt_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t nos_cnt:7; +#else + uint64_t nos_cnt:7; + uint64_t reserved_7_63:57; +#endif } cn30xx; struct cvmx_pow_nos_cnt_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t nos_cnt:9; +#else + uint64_t nos_cnt:9; + uint64_t reserved_9_63:55; +#endif } cn31xx; struct cvmx_pow_nos_cnt_s cn38xx; struct cvmx_pow_nos_cnt_s cn38xxp2; struct cvmx_pow_nos_cnt_cn31xx cn50xx; struct cvmx_pow_nos_cnt_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t nos_cnt:10; +#else + uint64_t nos_cnt:10; + uint64_t reserved_10_63:54; +#endif } cn52xx; struct cvmx_pow_nos_cnt_cn52xx cn52xxp1; struct cvmx_pow_nos_cnt_s cn56xx; struct cvmx_pow_nos_cnt_s cn56xxp1; struct cvmx_pow_nos_cnt_s cn58xx; struct cvmx_pow_nos_cnt_s cn58xxp1; + struct cvmx_pow_nos_cnt_cn52xx cn61xx; struct cvmx_pow_nos_cnt_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t nos_cnt:11; +#else + uint64_t nos_cnt:11; + uint64_t reserved_11_63:53; +#endif } cn63xx; struct cvmx_pow_nos_cnt_cn63xx cn63xxp1; + struct cvmx_pow_nos_cnt_cn63xx cn66xx; + struct cvmx_pow_nos_cnt_cn52xx cnf71xx; }; union cvmx_pow_nw_tim { uint64_t u64; struct cvmx_pow_nw_tim_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t nw_tim:10; +#else + uint64_t nw_tim:10; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_pow_nw_tim_s cn30xx; struct cvmx_pow_nw_tim_s cn31xx; @@ -371,15 +639,23 @@ union cvmx_pow_nw_tim { struct cvmx_pow_nw_tim_s cn56xxp1; struct cvmx_pow_nw_tim_s cn58xx; struct cvmx_pow_nw_tim_s cn58xxp1; + struct cvmx_pow_nw_tim_s cn61xx; struct cvmx_pow_nw_tim_s cn63xx; struct cvmx_pow_nw_tim_s cn63xxp1; + struct cvmx_pow_nw_tim_s cn66xx; + struct cvmx_pow_nw_tim_s cnf71xx; }; union cvmx_pow_pf_rst_msk { uint64_t u64; struct cvmx_pow_pf_rst_msk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t rst_msk:8; +#else + uint64_t rst_msk:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_pow_pf_rst_msk_s cn50xx; struct cvmx_pow_pf_rst_msk_s cn52xx; @@ -388,13 +664,17 @@ union cvmx_pow_pf_rst_msk { struct cvmx_pow_pf_rst_msk_s cn56xxp1; struct cvmx_pow_pf_rst_msk_s cn58xx; struct cvmx_pow_pf_rst_msk_s cn58xxp1; + struct cvmx_pow_pf_rst_msk_s cn61xx; struct cvmx_pow_pf_rst_msk_s cn63xx; struct cvmx_pow_pf_rst_msk_s cn63xxp1; + struct cvmx_pow_pf_rst_msk_s cn66xx; + struct cvmx_pow_pf_rst_msk_s cnf71xx; }; union cvmx_pow_pp_grp_mskx { uint64_t u64; struct cvmx_pow_pp_grp_mskx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t qos7_pri:4; uint64_t qos6_pri:4; @@ -405,10 +685,27 @@ union cvmx_pow_pp_grp_mskx { uint64_t qos1_pri:4; uint64_t qos0_pri:4; uint64_t grp_msk:16; +#else + uint64_t grp_msk:16; + uint64_t qos0_pri:4; + uint64_t qos1_pri:4; + uint64_t qos2_pri:4; + uint64_t qos3_pri:4; + uint64_t qos4_pri:4; + uint64_t qos5_pri:4; + uint64_t qos6_pri:4; + uint64_t qos7_pri:4; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_pow_pp_grp_mskx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t grp_msk:16; +#else + uint64_t grp_msk:16; + uint64_t reserved_16_63:48; +#endif } cn30xx; struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx; struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx; @@ -420,18 +717,29 @@ union cvmx_pow_pp_grp_mskx { struct cvmx_pow_pp_grp_mskx_s cn56xxp1; struct cvmx_pow_pp_grp_mskx_s cn58xx; struct cvmx_pow_pp_grp_mskx_s cn58xxp1; + struct cvmx_pow_pp_grp_mskx_s cn61xx; struct cvmx_pow_pp_grp_mskx_s cn63xx; struct cvmx_pow_pp_grp_mskx_s cn63xxp1; + struct cvmx_pow_pp_grp_mskx_s cn66xx; + struct cvmx_pow_pp_grp_mskx_s cnf71xx; }; union cvmx_pow_qos_rndx { uint64_t u64; struct cvmx_pow_qos_rndx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rnd_p3:8; uint64_t rnd_p2:8; uint64_t rnd_p1:8; uint64_t rnd:8; +#else + uint64_t rnd:8; + uint64_t rnd_p1:8; + uint64_t rnd_p2:8; + uint64_t rnd_p3:8; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_qos_rndx_s cn30xx; struct cvmx_pow_qos_rndx_s cn31xx; @@ -444,13 +752,17 @@ union cvmx_pow_qos_rndx { struct cvmx_pow_qos_rndx_s cn56xxp1; struct cvmx_pow_qos_rndx_s cn58xx; struct cvmx_pow_qos_rndx_s cn58xxp1; + struct cvmx_pow_qos_rndx_s cn61xx; struct cvmx_pow_qos_rndx_s cn63xx; struct cvmx_pow_qos_rndx_s cn63xxp1; + struct cvmx_pow_qos_rndx_s cn66xx; + struct cvmx_pow_qos_rndx_s cnf71xx; }; union cvmx_pow_qos_thrx { uint64_t u64; struct cvmx_pow_qos_thrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t des_cnt:12; uint64_t buf_cnt:12; @@ -459,8 +771,19 @@ union cvmx_pow_qos_thrx { uint64_t max_thr:11; uint64_t reserved_11_11:1; uint64_t min_thr:11; +#else + uint64_t min_thr:11; + uint64_t reserved_11_11:1; + uint64_t max_thr:11; + uint64_t reserved_23_23:1; + uint64_t free_cnt:12; + uint64_t buf_cnt:12; + uint64_t des_cnt:12; + uint64_t reserved_60_63:4; +#endif } s; struct cvmx_pow_qos_thrx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_55_63:9; uint64_t des_cnt:7; uint64_t reserved_43_47:5; @@ -471,8 +794,21 @@ union cvmx_pow_qos_thrx { uint64_t max_thr:6; uint64_t reserved_6_11:6; uint64_t min_thr:6; +#else + uint64_t min_thr:6; + uint64_t reserved_6_11:6; + uint64_t max_thr:6; + uint64_t reserved_18_23:6; + uint64_t free_cnt:7; + uint64_t reserved_31_35:5; + uint64_t buf_cnt:7; + uint64_t reserved_43_47:5; + uint64_t des_cnt:7; + uint64_t reserved_55_63:9; +#endif } cn30xx; struct cvmx_pow_qos_thrx_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_57_63:7; uint64_t des_cnt:9; uint64_t reserved_45_47:3; @@ -483,11 +819,24 @@ union cvmx_pow_qos_thrx { uint64_t max_thr:8; uint64_t reserved_8_11:4; uint64_t min_thr:8; +#else + uint64_t min_thr:8; + uint64_t reserved_8_11:4; + uint64_t max_thr:8; + uint64_t reserved_20_23:4; + uint64_t free_cnt:9; + uint64_t reserved_33_35:3; + uint64_t buf_cnt:9; + uint64_t reserved_45_47:3; + uint64_t des_cnt:9; + uint64_t reserved_57_63:7; +#endif } cn31xx; struct cvmx_pow_qos_thrx_s cn38xx; struct cvmx_pow_qos_thrx_s cn38xxp2; struct cvmx_pow_qos_thrx_cn31xx cn50xx; struct cvmx_pow_qos_thrx_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_58_63:6; uint64_t des_cnt:10; uint64_t reserved_46_47:2; @@ -498,13 +847,27 @@ union cvmx_pow_qos_thrx { uint64_t max_thr:9; uint64_t reserved_9_11:3; uint64_t min_thr:9; +#else + uint64_t min_thr:9; + uint64_t reserved_9_11:3; + uint64_t max_thr:9; + uint64_t reserved_21_23:3; + uint64_t free_cnt:10; + uint64_t reserved_34_35:2; + uint64_t buf_cnt:10; + uint64_t reserved_46_47:2; + uint64_t des_cnt:10; + uint64_t reserved_58_63:6; +#endif } cn52xx; struct cvmx_pow_qos_thrx_cn52xx cn52xxp1; struct cvmx_pow_qos_thrx_s cn56xx; struct cvmx_pow_qos_thrx_s cn56xxp1; struct cvmx_pow_qos_thrx_s cn58xx; struct cvmx_pow_qos_thrx_s cn58xxp1; + struct cvmx_pow_qos_thrx_cn52xx cn61xx; struct cvmx_pow_qos_thrx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_59_63:5; uint64_t des_cnt:11; uint64_t reserved_47_47:1; @@ -515,15 +878,34 @@ union cvmx_pow_qos_thrx { uint64_t max_thr:10; uint64_t reserved_10_11:2; uint64_t min_thr:10; +#else + uint64_t min_thr:10; + uint64_t reserved_10_11:2; + uint64_t max_thr:10; + uint64_t reserved_22_23:2; + uint64_t free_cnt:11; + uint64_t reserved_35_35:1; + uint64_t buf_cnt:11; + uint64_t reserved_47_47:1; + uint64_t des_cnt:11; + uint64_t reserved_59_63:5; +#endif } cn63xx; struct cvmx_pow_qos_thrx_cn63xx cn63xxp1; + struct cvmx_pow_qos_thrx_cn63xx cn66xx; + struct cvmx_pow_qos_thrx_cn52xx cnf71xx; }; union cvmx_pow_ts_pc { uint64_t u64; struct cvmx_pow_ts_pc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ts_pc:32; +#else + uint64_t ts_pc:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_ts_pc_s cn30xx; struct cvmx_pow_ts_pc_s cn31xx; @@ -536,15 +918,23 @@ union cvmx_pow_ts_pc { struct cvmx_pow_ts_pc_s cn56xxp1; struct cvmx_pow_ts_pc_s cn58xx; struct cvmx_pow_ts_pc_s cn58xxp1; + struct cvmx_pow_ts_pc_s cn61xx; struct cvmx_pow_ts_pc_s cn63xx; struct cvmx_pow_ts_pc_s cn63xxp1; + struct cvmx_pow_ts_pc_s cn66xx; + struct cvmx_pow_ts_pc_s cnf71xx; }; union cvmx_pow_wa_com_pc { uint64_t u64; struct cvmx_pow_wa_com_pc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t wa_pc:32; +#else + uint64_t wa_pc:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_wa_com_pc_s cn30xx; struct cvmx_pow_wa_com_pc_s cn31xx; @@ -557,15 +947,23 @@ union cvmx_pow_wa_com_pc { struct cvmx_pow_wa_com_pc_s cn56xxp1; struct cvmx_pow_wa_com_pc_s cn58xx; struct cvmx_pow_wa_com_pc_s cn58xxp1; + struct cvmx_pow_wa_com_pc_s cn61xx; struct cvmx_pow_wa_com_pc_s cn63xx; struct cvmx_pow_wa_com_pc_s cn63xxp1; + struct cvmx_pow_wa_com_pc_s cn66xx; + struct cvmx_pow_wa_com_pc_s cnf71xx; }; union cvmx_pow_wa_pcx { uint64_t u64; struct cvmx_pow_wa_pcx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t wa_pc:32; +#else + uint64_t wa_pc:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_wa_pcx_s cn30xx; struct cvmx_pow_wa_pcx_s cn31xx; @@ -578,16 +976,25 @@ union cvmx_pow_wa_pcx { struct cvmx_pow_wa_pcx_s cn56xxp1; struct cvmx_pow_wa_pcx_s cn58xx; struct cvmx_pow_wa_pcx_s cn58xxp1; + struct cvmx_pow_wa_pcx_s cn61xx; struct cvmx_pow_wa_pcx_s cn63xx; struct cvmx_pow_wa_pcx_s cn63xxp1; + struct cvmx_pow_wa_pcx_s cn66xx; + struct cvmx_pow_wa_pcx_s cnf71xx; }; union cvmx_pow_wq_int { uint64_t u64; struct cvmx_pow_wq_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iq_dis:16; uint64_t wq_int:16; +#else + uint64_t wq_int:16; + uint64_t iq_dis:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_wq_int_s cn30xx; struct cvmx_pow_wq_int_s cn31xx; @@ -600,69 +1007,126 @@ union cvmx_pow_wq_int { struct cvmx_pow_wq_int_s cn56xxp1; struct cvmx_pow_wq_int_s cn58xx; struct cvmx_pow_wq_int_s cn58xxp1; + struct cvmx_pow_wq_int_s cn61xx; struct cvmx_pow_wq_int_s cn63xx; struct cvmx_pow_wq_int_s cn63xxp1; + struct cvmx_pow_wq_int_s cn66xx; + struct cvmx_pow_wq_int_s cnf71xx; }; union cvmx_pow_wq_int_cntx { uint64_t u64; struct cvmx_pow_wq_int_cntx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t tc_cnt:4; uint64_t ds_cnt:12; uint64_t iq_cnt:12; +#else + uint64_t iq_cnt:12; + uint64_t ds_cnt:12; + uint64_t tc_cnt:4; + uint64_t reserved_28_63:36; +#endif } s; struct cvmx_pow_wq_int_cntx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t tc_cnt:4; uint64_t reserved_19_23:5; uint64_t ds_cnt:7; uint64_t reserved_7_11:5; uint64_t iq_cnt:7; +#else + uint64_t iq_cnt:7; + uint64_t reserved_7_11:5; + uint64_t ds_cnt:7; + uint64_t reserved_19_23:5; + uint64_t tc_cnt:4; + uint64_t reserved_28_63:36; +#endif } cn30xx; struct cvmx_pow_wq_int_cntx_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t tc_cnt:4; uint64_t reserved_21_23:3; uint64_t ds_cnt:9; uint64_t reserved_9_11:3; uint64_t iq_cnt:9; +#else + uint64_t iq_cnt:9; + uint64_t reserved_9_11:3; + uint64_t ds_cnt:9; + uint64_t reserved_21_23:3; + uint64_t tc_cnt:4; + uint64_t reserved_28_63:36; +#endif } cn31xx; struct cvmx_pow_wq_int_cntx_s cn38xx; struct cvmx_pow_wq_int_cntx_s cn38xxp2; struct cvmx_pow_wq_int_cntx_cn31xx cn50xx; struct cvmx_pow_wq_int_cntx_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t tc_cnt:4; uint64_t reserved_22_23:2; uint64_t ds_cnt:10; uint64_t reserved_10_11:2; uint64_t iq_cnt:10; +#else + uint64_t iq_cnt:10; + uint64_t reserved_10_11:2; + uint64_t ds_cnt:10; + uint64_t reserved_22_23:2; + uint64_t tc_cnt:4; + uint64_t reserved_28_63:36; +#endif } cn52xx; struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1; struct cvmx_pow_wq_int_cntx_s cn56xx; struct cvmx_pow_wq_int_cntx_s cn56xxp1; struct cvmx_pow_wq_int_cntx_s cn58xx; struct cvmx_pow_wq_int_cntx_s cn58xxp1; + struct cvmx_pow_wq_int_cntx_cn52xx cn61xx; struct cvmx_pow_wq_int_cntx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t tc_cnt:4; uint64_t reserved_23_23:1; uint64_t ds_cnt:11; uint64_t reserved_11_11:1; uint64_t iq_cnt:11; +#else + uint64_t iq_cnt:11; + uint64_t reserved_11_11:1; + uint64_t ds_cnt:11; + uint64_t reserved_23_23:1; + uint64_t tc_cnt:4; + uint64_t reserved_28_63:36; +#endif } cn63xx; struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1; + struct cvmx_pow_wq_int_cntx_cn63xx cn66xx; + struct cvmx_pow_wq_int_cntx_cn52xx cnf71xx; }; union cvmx_pow_wq_int_pc { uint64_t u64; struct cvmx_pow_wq_int_pc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_60_63:4; uint64_t pc:28; uint64_t reserved_28_31:4; uint64_t pc_thr:20; uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t pc_thr:20; + uint64_t reserved_28_31:4; + uint64_t pc:28; + uint64_t reserved_60_63:4; +#endif } s; struct cvmx_pow_wq_int_pc_s cn30xx; struct cvmx_pow_wq_int_pc_s cn31xx; @@ -675,13 +1139,17 @@ union cvmx_pow_wq_int_pc { struct cvmx_pow_wq_int_pc_s cn56xxp1; struct cvmx_pow_wq_int_pc_s cn58xx; struct cvmx_pow_wq_int_pc_s cn58xxp1; + struct cvmx_pow_wq_int_pc_s cn61xx; struct cvmx_pow_wq_int_pc_s cn63xx; struct cvmx_pow_wq_int_pc_s cn63xxp1; + struct cvmx_pow_wq_int_pc_s cn66xx; + struct cvmx_pow_wq_int_pc_s cnf71xx; }; union cvmx_pow_wq_int_thrx { uint64_t u64; struct cvmx_pow_wq_int_thrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t tc_en:1; uint64_t tc_thr:4; @@ -689,8 +1157,18 @@ union cvmx_pow_wq_int_thrx { uint64_t ds_thr:11; uint64_t reserved_11_11:1; uint64_t iq_thr:11; +#else + uint64_t iq_thr:11; + uint64_t reserved_11_11:1; + uint64_t ds_thr:11; + uint64_t reserved_23_23:1; + uint64_t tc_thr:4; + uint64_t tc_en:1; + uint64_t reserved_29_63:35; +#endif } s; struct cvmx_pow_wq_int_thrx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t tc_en:1; uint64_t tc_thr:4; @@ -698,8 +1176,18 @@ union cvmx_pow_wq_int_thrx { uint64_t ds_thr:6; uint64_t reserved_6_11:6; uint64_t iq_thr:6; +#else + uint64_t iq_thr:6; + uint64_t reserved_6_11:6; + uint64_t ds_thr:6; + uint64_t reserved_18_23:6; + uint64_t tc_thr:4; + uint64_t tc_en:1; + uint64_t reserved_29_63:35; +#endif } cn30xx; struct cvmx_pow_wq_int_thrx_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t tc_en:1; uint64_t tc_thr:4; @@ -707,11 +1195,21 @@ union cvmx_pow_wq_int_thrx { uint64_t ds_thr:8; uint64_t reserved_8_11:4; uint64_t iq_thr:8; +#else + uint64_t iq_thr:8; + uint64_t reserved_8_11:4; + uint64_t ds_thr:8; + uint64_t reserved_20_23:4; + uint64_t tc_thr:4; + uint64_t tc_en:1; + uint64_t reserved_29_63:35; +#endif } cn31xx; struct cvmx_pow_wq_int_thrx_s cn38xx; struct cvmx_pow_wq_int_thrx_s cn38xxp2; struct cvmx_pow_wq_int_thrx_cn31xx cn50xx; struct cvmx_pow_wq_int_thrx_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t tc_en:1; uint64_t tc_thr:4; @@ -719,13 +1217,24 @@ union cvmx_pow_wq_int_thrx { uint64_t ds_thr:9; uint64_t reserved_9_11:3; uint64_t iq_thr:9; +#else + uint64_t iq_thr:9; + uint64_t reserved_9_11:3; + uint64_t ds_thr:9; + uint64_t reserved_21_23:3; + uint64_t tc_thr:4; + uint64_t tc_en:1; + uint64_t reserved_29_63:35; +#endif } cn52xx; struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1; struct cvmx_pow_wq_int_thrx_s cn56xx; struct cvmx_pow_wq_int_thrx_s cn56xxp1; struct cvmx_pow_wq_int_thrx_s cn58xx; struct cvmx_pow_wq_int_thrx_s cn58xxp1; + struct cvmx_pow_wq_int_thrx_cn52xx cn61xx; struct cvmx_pow_wq_int_thrx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_29_63:35; uint64_t tc_en:1; uint64_t tc_thr:4; @@ -733,15 +1242,31 @@ union cvmx_pow_wq_int_thrx { uint64_t ds_thr:10; uint64_t reserved_10_11:2; uint64_t iq_thr:10; +#else + uint64_t iq_thr:10; + uint64_t reserved_10_11:2; + uint64_t ds_thr:10; + uint64_t reserved_22_23:2; + uint64_t tc_thr:4; + uint64_t tc_en:1; + uint64_t reserved_29_63:35; +#endif } cn63xx; struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1; + struct cvmx_pow_wq_int_thrx_cn63xx cn66xx; + struct cvmx_pow_wq_int_thrx_cn52xx cnf71xx; }; union cvmx_pow_ws_pcx { uint64_t u64; struct cvmx_pow_ws_pcx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ws_pc:32; +#else + uint64_t ws_pc:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_pow_ws_pcx_s cn30xx; struct cvmx_pow_ws_pcx_s cn31xx; @@ -754,8 +1279,11 @@ union cvmx_pow_ws_pcx { struct cvmx_pow_ws_pcx_s cn56xxp1; struct cvmx_pow_ws_pcx_s cn58xx; struct cvmx_pow_ws_pcx_s cn58xxp1; + struct cvmx_pow_ws_pcx_s cn61xx; struct cvmx_pow_ws_pcx_s cn63xx; struct cvmx_pow_ws_pcx_s cn63xxp1; + struct cvmx_pow_ws_pcx_s cn66xx; + struct cvmx_pow_ws_pcx_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h index 999aefe3274..4b4d0ecfd9e 100644 --- a/arch/mips/include/asm/octeon/cvmx-pow.h +++ b/arch/mips/include/asm/octeon/cvmx-pow.h @@ -53,8 +53,8 @@ #include <asm/octeon/cvmx-pow-defs.h> -#include "cvmx-scratch.h" -#include "cvmx-wqe.h" +#include <asm/octeon/cvmx-scratch.h> +#include <asm/octeon/cvmx-wqe.h> /* Default to having all POW constancy checks turned on */ #ifndef CVMX_ENABLE_POW_CHECKS @@ -70,7 +70,7 @@ enum cvmx_pow_tag_type { * The work queue entry from the order - NEVER tag switch from * NULL to NULL */ - CVMX_POW_TAG_TYPE_NULL = 2L, + CVMX_POW_TAG_TYPE_NULL = 2L, /* A tag switch to NULL, and there is no space reserved in POW * - NEVER tag switch to NULL_NULL * - NEVER tag switch from NULL_NULL @@ -90,7 +90,7 @@ typedef enum { } cvmx_pow_wait_t; /** - * POW tag operations. These are used in the data stored to the POW. + * POW tag operations. These are used in the data stored to the POW. */ typedef enum { /* @@ -341,14 +341,14 @@ typedef union { * lists. The two memory-input queue lists associated * with each QOS level are: * - * - qosgrp = 0, qosgrp = 8: QOS0 - * - qosgrp = 1, qosgrp = 9: QOS1 - * - qosgrp = 2, qosgrp = 10: QOS2 - * - qosgrp = 3, qosgrp = 11: QOS3 - * - qosgrp = 4, qosgrp = 12: QOS4 - * - qosgrp = 5, qosgrp = 13: QOS5 - * - qosgrp = 6, qosgrp = 14: QOS6 - * - qosgrp = 7, qosgrp = 15: QOS7 + * - qosgrp = 0, qosgrp = 8: QOS0 + * - qosgrp = 1, qosgrp = 9: QOS1 + * - qosgrp = 2, qosgrp = 10: QOS2 + * - qosgrp = 3, qosgrp = 11: QOS3 + * - qosgrp = 4, qosgrp = 12: QOS4 + * - qosgrp = 5, qosgrp = 13: QOS5 + * - qosgrp = 6, qosgrp = 14: QOS6 + * - qosgrp = 7, qosgrp = 15: QOS7 */ uint64_t qosgrp:4; /* @@ -942,11 +942,11 @@ typedef union { * operations. * * NOTE: The following is the behavior of the pending switch bit at the PP - * for POW stores (i.e. when did<7:3> == 0xc) - * - did<2:0> == 0 => pending switch bit is set - * - did<2:0> == 1 => no affect on the pending switch bit - * - did<2:0> == 3 => pending switch bit is cleared - * - did<2:0> == 7 => no affect on the pending switch bit + * for POW stores (i.e. when did<7:3> == 0xc) + * - did<2:0> == 0 => pending switch bit is set + * - did<2:0> == 1 => no affect on the pending switch bit + * - did<2:0> == 3 => pending switch bit is cleared + * - did<2:0> == 7 => no affect on the pending switch bit * - did<2:0> == others => must not be used * - No other loads/stores have an affect on the pending switch bit * - The switch bus from POW can clear the pending switch bit @@ -1053,7 +1053,7 @@ static inline cvmx_wqe_t *cvmx_pow_get_current_wqp(void) } #ifndef CVMX_MF_CHORD -#define CVMX_MF_CHORD(dest) CVMX_RDHWR(dest, 30) +#define CVMX_MF_CHORD(dest) CVMX_RDHWR(dest, 30) #endif /** @@ -1097,7 +1097,7 @@ static inline void cvmx_pow_tag_sw_wait(void) * so the caller must ensure that there is not a pending tag switch. * * @wait: When set, call stalls until work becomes avaiable, or times out. - * If not set, returns immediately. + * If not set, returns immediately. * * Returns Returns the WQE pointer from POW. Returns NULL if no work * was available. @@ -1131,7 +1131,7 @@ static inline cvmx_wqe_t *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_t * requesting the new work. * * @wait: When set, call stalls until work becomes avaiable, or times out. - * If not set, returns immediately. + * If not set, returns immediately. * * Returns Returns the WQE pointer from POW. Returns NULL if no work * was available. @@ -1148,7 +1148,7 @@ static inline cvmx_wqe_t *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait) } /** - * Synchronous null_rd request. Requests a switch out of NULL_NULL POW state. + * Synchronous null_rd request. Requests a switch out of NULL_NULL POW state. * This function waits for any previous tag switch to complete before * requesting the null_rd. * @@ -1183,11 +1183,11 @@ static inline enum cvmx_pow_tag_type cvmx_pow_work_request_null_rd(void) * there is not a pending tag switch. * * @scr_addr: Scratch memory address that response will be returned - * to, which is either a valid WQE, or a response with the - * invalid bit set. Byte address, must be 8 byte aligned. + * to, which is either a valid WQE, or a response with the + * invalid bit set. Byte address, must be 8 byte aligned. * * @wait: 1 to cause response to wait for work to become available (or - * timeout), 0 to cause response to return immediately + * timeout), 0 to cause response to return immediately */ static inline void cvmx_pow_work_request_async_nocheck(int scr_addr, cvmx_pow_wait_t wait) @@ -1212,11 +1212,11 @@ static inline void cvmx_pow_work_request_async_nocheck(int scr_addr, * tag switch to complete before requesting the new work. * * @scr_addr: Scratch memory address that response will be returned - * to, which is either a valid WQE, or a response with the - * invalid bit set. Byte address, must be 8 byte aligned. + * to, which is either a valid WQE, or a response with the + * invalid bit set. Byte address, must be 8 byte aligned. * * @wait: 1 to cause response to wait for work to become available (or - * timeout), 0 to cause response to return immediately + * timeout), 0 to cause response to return immediately */ static inline void cvmx_pow_work_request_async(int scr_addr, cvmx_pow_wait_t wait) @@ -1234,7 +1234,7 @@ static inline void cvmx_pow_work_request_async(int scr_addr, * to wait for the response. * * @scr_addr: Scratch memory address to get result from Byte address, - * must be 8 byte aligned. + * must be 8 byte aligned. * * Returns Returns the WQE from the scratch register, or NULL if no * work was available. @@ -1260,7 +1260,7 @@ static inline cvmx_wqe_t *cvmx_pow_work_response_async(int scr_addr) * @wqe_ptr: pointer to a work queue entry returned by the POW * * Returns 0 if pointer is valid - * 1 if invalid (no work was returned) + * 1 if invalid (no work was returned) */ static inline uint64_t cvmx_pow_work_invalid(cvmx_wqe_t *wqe_ptr) { @@ -1314,7 +1314,7 @@ static inline void cvmx_pow_tag_sw_nocheck(uint32_t tag, /* * Note that WQE in DRAM is not updated here, as the POW does * not read from DRAM once the WQE is in flight. See hardware - * manual for complete details. It is the application's + * manual for complete details. It is the application's * responsibility to keep track of the current tag value if * that is important. */ @@ -1361,7 +1361,7 @@ static inline void cvmx_pow_tag_sw(uint32_t tag, /* * Note that WQE in DRAM is not updated here, as the POW does * not read from DRAM once the WQE is in flight. See hardware - * manual for complete details. It is the application's + * manual for complete details. It is the application's * responsibility to keep track of the current tag value if * that is important. */ @@ -1390,7 +1390,7 @@ static inline void cvmx_pow_tag_sw(uint32_t tag, * previous tag switch has completed. * * @wqp: pointer to work queue entry to submit. This entry is - * updated to match the other parameters + * updated to match the other parameters * @tag: tag value to be assigned to work queue entry * @tag_type: type of tag * @group: group value for the work queue entry. @@ -1429,7 +1429,7 @@ static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag, /* * Note that WQE in DRAM is not updated here, as the POW does * not read from DRAM once the WQE is in flight. See hardware - * manual for complete details. It is the application's + * manual for complete details. It is the application's * responsibility to keep track of the current tag value if * that is important. */ @@ -1468,10 +1468,10 @@ static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag, * before requesting the tag switch. * * @wqp: pointer to work queue entry to submit. This entry is updated - * to match the other parameters + * to match the other parameters * @tag: tag value to be assigned to work queue entry * @tag_type: type of tag - * @group: group value for the work queue entry. + * @group: group value for the work queue entry. */ static inline void cvmx_pow_tag_sw_full(cvmx_wqe_t *wqp, uint32_t tag, enum cvmx_pow_tag_type tag_type, @@ -1560,7 +1560,7 @@ static inline void cvmx_pow_tag_sw_null(void) * unrelated to the tag that the core currently holds. * * @wqp: pointer to work queue entry to submit. This entry is - * updated to match the other parameters + * updated to match the other parameters * @tag: tag value to be assigned to work queue entry * @tag_type: type of tag * @qos: Input queue to add to. @@ -1592,7 +1592,7 @@ static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag, ptr.sio.offset = cvmx_ptr_to_phys(wqp); /* - * SYNC write to memory before the work submit. This is + * SYNC write to memory before the work submit. This is * necessary as POW may read values from DRAM at this time. */ CVMX_SYNCWS; @@ -1604,11 +1604,11 @@ static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag, * indicates which groups each core will accept work from. There are * 16 groups. * - * @core_num: core to apply mask to + * @core_num: core to apply mask to * @mask: Group mask. There are 16 groups, so only bits 0-15 are valid, - * representing groups 0-15. - * Each 1 bit in the mask enables the core to accept work from - * the corresponding group. + * representing groups 0-15. + * Each 1 bit in the mask enables the core to accept work from + * the corresponding group. */ static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask) { @@ -1623,14 +1623,14 @@ static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask) * This function sets POW static priorities for a core. Each input queue has * an associated priority value. * - * @core_num: core to apply priorities to - * @priority: Vector of 8 priorities, one per POW Input Queue (0-7). - * Highest priority is 0 and lowest is 7. A priority value - * of 0xF instructs POW to skip the Input Queue when - * scheduling to this specific core. - * NOTE: priorities should not have gaps in values, meaning - * {0,1,1,1,1,1,1,1} is a valid configuration while - * {0,2,2,2,2,2,2,2} is not. + * @core_num: core to apply priorities to + * @priority: Vector of 8 priorities, one per POW Input Queue (0-7). + * Highest priority is 0 and lowest is 7. A priority value + * of 0xF instructs POW to skip the Input Queue when + * scheduling to this specific core. + * NOTE: priorities should not have gaps in values, meaning + * {0,1,1,1,1,1,1,1} is a valid configuration while + * {0,2,2,2,2,2,2,2} is not. */ static inline void cvmx_pow_set_priority(uint64_t core_num, const uint8_t priority[]) @@ -1708,8 +1708,8 @@ static inline void cvmx_pow_set_priority(uint64_t core_num, * @tag_type: New tag type * @group: New group value * @no_sched: Control whether this work queue entry will be rescheduled. - * - 1 : don't schedule this work - * - 0 : allow this work to be scheduled. + * - 1 : don't schedule this work + * - 0 : allow this work to be scheduled. */ static inline void cvmx_pow_tag_sw_desched_nocheck( uint32_t tag, @@ -1794,8 +1794,8 @@ static inline void cvmx_pow_tag_sw_desched_nocheck( * @tag_type: New tag type * @group: New group value * @no_sched: Control whether this work queue entry will be rescheduled. - * - 1 : don't schedule this work - * - 0 : allow this work to be scheduled. + * - 1 : don't schedule this work + * - 0 : allow this work to be scheduled. */ static inline void cvmx_pow_tag_sw_desched(uint32_t tag, enum cvmx_pow_tag_type tag_type, @@ -1819,8 +1819,8 @@ static inline void cvmx_pow_tag_sw_desched(uint32_t tag, * Descchedules the current work queue entry. * * @no_sched: no schedule flag value to be set on the work queue - * entry. If this is set the entry will not be - * rescheduled. + * entry. If this is set the entry will not be + * rescheduled. */ static inline void cvmx_pow_desched(uint64_t no_sched) { @@ -1863,7 +1863,7 @@ static inline void cvmx_pow_desched(uint64_t no_sched) *****************************************************/ /* - * Number of bits of the tag used by software. The SW bits are always + * Number of bits of the tag used by software. The SW bits are always * a contiguous block of the high starting at bit 31. The hardware * bits are always the low bits. By default, the top 8 bits of the * tag are reserved for software, and the low 24 are set by the IPD @@ -1890,7 +1890,7 @@ static inline void cvmx_pow_desched(uint64_t no_sched) * are defined here. */ /* Mask for the value portion of the tag */ -#define CVMX_TAG_SUBGROUP_MASK 0xFFFF +#define CVMX_TAG_SUBGROUP_MASK 0xFFFF #define CVMX_TAG_SUBGROUP_SHIFT 16 #define CVMX_TAG_SUBGROUP_PKO 0x1 @@ -1905,12 +1905,12 @@ static inline void cvmx_pow_desched(uint64_t no_sched) * This function creates a 32 bit tag value from the two values provided. * * @sw_bits: The upper bits (number depends on configuration) are set - * to this value. The remainder of bits are set by the - * hw_bits parameter. + * to this value. The remainder of bits are set by the + * hw_bits parameter. * * @hw_bits: The lower bits (number depends on configuration) are set - * to this value. The remainder of bits are set by the - * sw_bits parameter. + * to this value. The remainder of bits are set by the + * sw_bits parameter. * * Returns 32 bit value of the combined hw and sw bits. */ @@ -1957,7 +1957,7 @@ static inline uint32_t cvmx_pow_tag_get_hw_bits(uint64_t tag) * * @buffer: Buffer to store capture into * @buffer_size: - * The size of the supplied buffer + * The size of the supplied buffer * * Returns Zero on success, negative on failure */ @@ -1968,7 +1968,7 @@ extern int cvmx_pow_capture(void *buffer, int buffer_size); * * @buffer: POW capture from cvmx_pow_capture() * @buffer_size: - * Size of the buffer + * Size of the buffer */ extern void cvmx_pow_display(void *buffer, int buffer_size); diff --git a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h index c45da1f35ea..87d6f92a548 100644 --- a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,8 +28,6 @@ #ifndef __CVMX_RNM_DEFS_H__ #define __CVMX_RNM_DEFS_H__ -#include <linux/types.h> - #define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull)) #define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull)) #define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull)) @@ -39,9 +37,15 @@ union cvmx_rnm_bist_status { uint64_t u64; struct cvmx_rnm_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t rrc:1; uint64_t mem:1; +#else + uint64_t mem:1; + uint64_t rrc:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_rnm_bist_status_s cn30xx; struct cvmx_rnm_bist_status_s cn31xx; @@ -54,14 +58,21 @@ union cvmx_rnm_bist_status { struct cvmx_rnm_bist_status_s cn56xxp1; struct cvmx_rnm_bist_status_s cn58xx; struct cvmx_rnm_bist_status_s cn58xxp1; + struct cvmx_rnm_bist_status_s cn61xx; struct cvmx_rnm_bist_status_s cn63xx; struct cvmx_rnm_bist_status_s cn63xxp1; + struct cvmx_rnm_bist_status_s cn66xx; + struct cvmx_rnm_bist_status_s cn68xx; + struct cvmx_rnm_bist_status_s cn68xxp1; + struct cvmx_rnm_bist_status_s cnf71xx; }; union cvmx_rnm_ctl_status { uint64_t u64; struct cvmx_rnm_ctl_status_s { - uint64_t reserved_11_63:53; +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_12_63:52; + uint64_t dis_mak:1; uint64_t eer_lck:1; uint64_t eer_val:1; uint64_t ent_sel:4; @@ -70,18 +81,39 @@ union cvmx_rnm_ctl_status { uint64_t rnm_rst:1; uint64_t rng_en:1; uint64_t ent_en:1; +#else + uint64_t ent_en:1; + uint64_t rng_en:1; + uint64_t rnm_rst:1; + uint64_t rng_rst:1; + uint64_t exp_ent:1; + uint64_t ent_sel:4; + uint64_t eer_val:1; + uint64_t eer_lck:1; + uint64_t dis_mak:1; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_rnm_ctl_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t rng_rst:1; uint64_t rnm_rst:1; uint64_t rng_en:1; uint64_t ent_en:1; +#else + uint64_t ent_en:1; + uint64_t rng_en:1; + uint64_t rnm_rst:1; + uint64_t rng_rst:1; + uint64_t reserved_4_63:60; +#endif } cn30xx; struct cvmx_rnm_ctl_status_cn30xx cn31xx; struct cvmx_rnm_ctl_status_cn30xx cn38xx; struct cvmx_rnm_ctl_status_cn30xx cn38xxp2; struct cvmx_rnm_ctl_status_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t ent_sel:4; uint64_t exp_ent:1; @@ -89,6 +121,15 @@ union cvmx_rnm_ctl_status { uint64_t rnm_rst:1; uint64_t rng_en:1; uint64_t ent_en:1; +#else + uint64_t ent_en:1; + uint64_t rng_en:1; + uint64_t rnm_rst:1; + uint64_t rng_rst:1; + uint64_t exp_ent:1; + uint64_t ent_sel:4; + uint64_t reserved_9_63:55; +#endif } cn50xx; struct cvmx_rnm_ctl_status_cn50xx cn52xx; struct cvmx_rnm_ctl_status_cn50xx cn52xxp1; @@ -96,34 +137,88 @@ union cvmx_rnm_ctl_status { struct cvmx_rnm_ctl_status_cn50xx cn56xxp1; struct cvmx_rnm_ctl_status_cn50xx cn58xx; struct cvmx_rnm_ctl_status_cn50xx cn58xxp1; - struct cvmx_rnm_ctl_status_s cn63xx; - struct cvmx_rnm_ctl_status_s cn63xxp1; + struct cvmx_rnm_ctl_status_s cn61xx; + struct cvmx_rnm_ctl_status_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t reserved_11_63:53; + uint64_t eer_lck:1; + uint64_t eer_val:1; + uint64_t ent_sel:4; + uint64_t exp_ent:1; + uint64_t rng_rst:1; + uint64_t rnm_rst:1; + uint64_t rng_en:1; + uint64_t ent_en:1; +#else + uint64_t ent_en:1; + uint64_t rng_en:1; + uint64_t rnm_rst:1; + uint64_t rng_rst:1; + uint64_t exp_ent:1; + uint64_t ent_sel:4; + uint64_t eer_val:1; + uint64_t eer_lck:1; + uint64_t reserved_11_63:53; +#endif + } cn63xx; + struct cvmx_rnm_ctl_status_cn63xx cn63xxp1; + struct cvmx_rnm_ctl_status_s cn66xx; + struct cvmx_rnm_ctl_status_cn63xx cn68xx; + struct cvmx_rnm_ctl_status_cn63xx cn68xxp1; + struct cvmx_rnm_ctl_status_s cnf71xx; }; union cvmx_rnm_eer_dbg { uint64_t u64; struct cvmx_rnm_eer_dbg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t dat:64; +#else + uint64_t dat:64; +#endif } s; + struct cvmx_rnm_eer_dbg_s cn61xx; struct cvmx_rnm_eer_dbg_s cn63xx; struct cvmx_rnm_eer_dbg_s cn63xxp1; + struct cvmx_rnm_eer_dbg_s cn66xx; + struct cvmx_rnm_eer_dbg_s cn68xx; + struct cvmx_rnm_eer_dbg_s cn68xxp1; + struct cvmx_rnm_eer_dbg_s cnf71xx; }; union cvmx_rnm_eer_key { uint64_t u64; struct cvmx_rnm_eer_key_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t key:64; +#else uint64_t key:64; +#endif } s; + struct cvmx_rnm_eer_key_s cn61xx; struct cvmx_rnm_eer_key_s cn63xx; struct cvmx_rnm_eer_key_s cn63xxp1; + struct cvmx_rnm_eer_key_s cn66xx; + struct cvmx_rnm_eer_key_s cn68xx; + struct cvmx_rnm_eer_key_s cn68xxp1; + struct cvmx_rnm_eer_key_s cnf71xx; }; union cvmx_rnm_serial_num { uint64_t u64; struct cvmx_rnm_serial_num_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dat:64; +#else uint64_t dat:64; +#endif } s; + struct cvmx_rnm_serial_num_s cn61xx; struct cvmx_rnm_serial_num_s cn63xx; + struct cvmx_rnm_serial_num_s cn66xx; + struct cvmx_rnm_serial_num_s cn68xx; + struct cvmx_rnm_serial_num_s cn68xxp1; + struct cvmx_rnm_serial_num_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-scratch.h b/arch/mips/include/asm/octeon/cvmx-scratch.h index 96b70cfd624..8d21cc5e4e4 100644 --- a/arch/mips/include/asm/octeon/cvmx-scratch.h +++ b/arch/mips/include/asm/octeon/cvmx-scratch.h @@ -39,7 +39,7 @@ * Note: This define must be a long, not a long long in order to * compile without warnings for both 32bit and 64bit. */ -#define CVMX_SCRATCH_BASE (-32768l) /* 0xffffffffffff8000 */ +#define CVMX_SCRATCH_BASE (-32768l) /* 0xffffffffffff8000 */ /** * Reads an 8 bit value from the processor local scratchpad memory. diff --git a/arch/mips/include/asm/octeon/cvmx-sli-defs.h b/arch/mips/include/asm/octeon/cvmx-sli-defs.h index 7c6c901d3d2..e697c2f52a6 100644 --- a/arch/mips/include/asm/octeon/cvmx-sli-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-sli-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2011 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -127,6 +127,7 @@ union cvmx_sli_bist_status { uint64_t u64; struct cvmx_sli_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ncb_req:1; uint64_t n2p0_c:1; @@ -153,8 +154,37 @@ union cvmx_sli_bist_status { uint64_t dsi0_0:1; uint64_t msi:1; uint64_t ncb_cmd:1; +#else + uint64_t ncb_cmd:1; + uint64_t msi:1; + uint64_t dsi0_0:1; + uint64_t dsi0_1:1; + uint64_t dsi1_0:1; + uint64_t dsi1_1:1; + uint64_t reserved_6_8:3; + uint64_t p2n1_p1:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_n:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_c0:1; + uint64_t p2n0_p1:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_n:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_c0:1; + uint64_t reserved_19_24:6; + uint64_t cpl_p1:1; + uint64_t cpl_p0:1; + uint64_t n2p1_o:1; + uint64_t n2p1_c:1; + uint64_t n2p0_o:1; + uint64_t n2p0_c:1; + uint64_t ncb_req:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_bist_status_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t n2p0_c:1; uint64_t n2p0_o:1; @@ -179,8 +209,35 @@ union cvmx_sli_bist_status { uint64_t dsi0_0:1; uint64_t msi:1; uint64_t ncb_cmd:1; +#else + uint64_t ncb_cmd:1; + uint64_t msi:1; + uint64_t dsi0_0:1; + uint64_t dsi0_1:1; + uint64_t dsi1_0:1; + uint64_t dsi1_1:1; + uint64_t reserved_6_8:3; + uint64_t p2n1_p1:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_n:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_c0:1; + uint64_t p2n0_p1:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_n:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_c0:1; + uint64_t reserved_19_24:6; + uint64_t cpl_p1:1; + uint64_t cpl_p0:1; + uint64_t reserved_27_28:2; + uint64_t n2p0_o:1; + uint64_t n2p0_c:1; + uint64_t reserved_31_63:33; +#endif } cn61xx; struct cvmx_sli_bist_status_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_31_63:33; uint64_t n2p0_c:1; uint64_t n2p0_o:1; @@ -206,16 +263,45 @@ union cvmx_sli_bist_status { uint64_t dsi0_0:1; uint64_t msi:1; uint64_t ncb_cmd:1; +#else + uint64_t ncb_cmd:1; + uint64_t msi:1; + uint64_t dsi0_0:1; + uint64_t dsi0_1:1; + uint64_t dsi1_0:1; + uint64_t dsi1_1:1; + uint64_t reserved_6_8:3; + uint64_t p2n1_p1:1; + uint64_t p2n1_p0:1; + uint64_t p2n1_n:1; + uint64_t p2n1_c1:1; + uint64_t p2n1_c0:1; + uint64_t p2n0_p1:1; + uint64_t p2n0_p0:1; + uint64_t p2n0_n:1; + uint64_t p2n0_c1:1; + uint64_t p2n0_c0:1; + uint64_t reserved_19_24:6; + uint64_t cpl_p1:1; + uint64_t cpl_p0:1; + uint64_t n2p1_o:1; + uint64_t n2p1_c:1; + uint64_t n2p0_o:1; + uint64_t n2p0_c:1; + uint64_t reserved_31_63:33; +#endif } cn63xx; struct cvmx_sli_bist_status_cn63xx cn63xxp1; struct cvmx_sli_bist_status_cn61xx cn66xx; struct cvmx_sli_bist_status_s cn68xx; struct cvmx_sli_bist_status_s cn68xxp1; + struct cvmx_sli_bist_status_cn61xx cnf71xx; }; union cvmx_sli_ctl_portx { uint64_t u64; struct cvmx_sli_ctl_portx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t intd:1; uint64_t intc:1; @@ -232,6 +318,24 @@ union cvmx_sli_ctl_portx { uint64_t ptlp_ro:1; uint64_t reserved_1_4:4; uint64_t wait_com:1; +#else + uint64_t wait_com:1; + uint64_t reserved_1_4:4; + uint64_t ptlp_ro:1; + uint64_t reserved_6_6:1; + uint64_t ctlp_ro:1; + uint64_t inta_map:2; + uint64_t intb_map:2; + uint64_t intc_map:2; + uint64_t intd_map:2; + uint64_t waitl_com:1; + uint64_t dis_port:1; + uint64_t inta:1; + uint64_t intb:1; + uint64_t intc:1; + uint64_t intd:1; + uint64_t reserved_22_63:42; +#endif } s; struct cvmx_sli_ctl_portx_s cn61xx; struct cvmx_sli_ctl_portx_s cn63xx; @@ -239,36 +343,59 @@ union cvmx_sli_ctl_portx { struct cvmx_sli_ctl_portx_s cn66xx; struct cvmx_sli_ctl_portx_s cn68xx; struct cvmx_sli_ctl_portx_s cn68xxp1; + struct cvmx_sli_ctl_portx_s cnf71xx; }; union cvmx_sli_ctl_status { uint64_t u64; struct cvmx_sli_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t p1_ntags:6; uint64_t p0_ntags:6; uint64_t chip_rev:8; +#else + uint64_t chip_rev:8; + uint64_t p0_ntags:6; + uint64_t p1_ntags:6; + uint64_t reserved_20_63:44; +#endif } s; struct cvmx_sli_ctl_status_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t p0_ntags:6; uint64_t chip_rev:8; +#else + uint64_t chip_rev:8; + uint64_t p0_ntags:6; + uint64_t reserved_14_63:50; +#endif } cn61xx; struct cvmx_sli_ctl_status_s cn63xx; struct cvmx_sli_ctl_status_s cn63xxp1; struct cvmx_sli_ctl_status_cn61xx cn66xx; struct cvmx_sli_ctl_status_s cn68xx; struct cvmx_sli_ctl_status_s cn68xxp1; + struct cvmx_sli_ctl_status_cn61xx cnf71xx; }; union cvmx_sli_data_out_cnt { uint64_t u64; struct cvmx_sli_data_out_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t p1_ucnt:16; uint64_t p1_fcnt:6; uint64_t p0_ucnt:16; uint64_t p0_fcnt:6; +#else + uint64_t p0_fcnt:6; + uint64_t p0_ucnt:16; + uint64_t p1_fcnt:6; + uint64_t p1_ucnt:16; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_sli_data_out_cnt_s cn61xx; struct cvmx_sli_data_out_cnt_s cn63xx; @@ -276,14 +403,21 @@ union cvmx_sli_data_out_cnt { struct cvmx_sli_data_out_cnt_s cn66xx; struct cvmx_sli_data_out_cnt_s cn68xx; struct cvmx_sli_data_out_cnt_s cn68xxp1; + struct cvmx_sli_data_out_cnt_s cnf71xx; }; union cvmx_sli_dbg_data { uint64_t u64; struct cvmx_sli_dbg_data_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t dsel_ext:1; uint64_t data:17; +#else + uint64_t data:17; + uint64_t dsel_ext:1; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_sli_dbg_data_s cn61xx; struct cvmx_sli_dbg_data_s cn63xx; @@ -291,14 +425,21 @@ union cvmx_sli_dbg_data { struct cvmx_sli_dbg_data_s cn66xx; struct cvmx_sli_dbg_data_s cn68xx; struct cvmx_sli_dbg_data_s cn68xxp1; + struct cvmx_sli_dbg_data_s cnf71xx; }; union cvmx_sli_dbg_select { uint64_t u64; struct cvmx_sli_dbg_select_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_33_63:31; uint64_t adbg_sel:1; uint64_t dbg_sel:32; +#else + uint64_t dbg_sel:32; + uint64_t adbg_sel:1; + uint64_t reserved_33_63:31; +#endif } s; struct cvmx_sli_dbg_select_s cn61xx; struct cvmx_sli_dbg_select_s cn63xx; @@ -306,13 +447,19 @@ union cvmx_sli_dbg_select { struct cvmx_sli_dbg_select_s cn66xx; struct cvmx_sli_dbg_select_s cn68xx; struct cvmx_sli_dbg_select_s cn68xxp1; + struct cvmx_sli_dbg_select_s cnf71xx; }; union cvmx_sli_dmax_cnt { uint64_t u64; struct cvmx_sli_dmax_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_dmax_cnt_s cn61xx; struct cvmx_sli_dmax_cnt_s cn63xx; @@ -320,13 +467,19 @@ union cvmx_sli_dmax_cnt { struct cvmx_sli_dmax_cnt_s cn66xx; struct cvmx_sli_dmax_cnt_s cn68xx; struct cvmx_sli_dmax_cnt_s cn68xxp1; + struct cvmx_sli_dmax_cnt_s cnf71xx; }; union cvmx_sli_dmax_int_level { uint64_t u64; struct cvmx_sli_dmax_int_level_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t time:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t time:32; +#endif } s; struct cvmx_sli_dmax_int_level_s cn61xx; struct cvmx_sli_dmax_int_level_s cn63xx; @@ -334,13 +487,19 @@ union cvmx_sli_dmax_int_level { struct cvmx_sli_dmax_int_level_s cn66xx; struct cvmx_sli_dmax_int_level_s cn68xx; struct cvmx_sli_dmax_int_level_s cn68xxp1; + struct cvmx_sli_dmax_int_level_s cnf71xx; }; union cvmx_sli_dmax_tim { uint64_t u64; struct cvmx_sli_dmax_tim_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t tim:32; +#else + uint64_t tim:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_dmax_tim_s cn61xx; struct cvmx_sli_dmax_tim_s cn63xx; @@ -348,11 +507,13 @@ union cvmx_sli_dmax_tim { struct cvmx_sli_dmax_tim_s cn66xx; struct cvmx_sli_dmax_tim_s cn68xx; struct cvmx_sli_dmax_tim_s cn68xxp1; + struct cvmx_sli_dmax_tim_s cnf71xx; }; union cvmx_sli_int_enb_ciu { uint64_t u64; struct cvmx_sli_int_enb_ciu_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -399,8 +560,57 @@ union cvmx_sli_int_enb_ciu { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t reserved_18_19:2; + uint64_t m2_up_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_un_wi:1; + uint64_t m3_up_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_un_wi:1; + uint64_t reserved_28_31:4; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t sprt2_err:1; + uint64_t sprt3_err:1; + uint64_t ill_pad:1; + uint64_t pipe_err:1; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_sli_int_enb_ciu_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t sprt3_err:1; @@ -446,8 +656,56 @@ union cvmx_sli_int_enb_ciu { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t reserved_18_19:2; + uint64_t m2_up_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_un_wi:1; + uint64_t m3_up_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_un_wi:1; + uint64_t reserved_28_31:4; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t sprt2_err:1; + uint64_t sprt3_err:1; + uint64_t ill_pad:1; + uint64_t reserved_61_63:3; +#endif } cn61xx; struct cvmx_sli_int_enb_ciu_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t reserved_58_59:2; @@ -483,10 +741,48 @@ union cvmx_sli_int_enb_ciu { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t reserved_18_31:14; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t reserved_58_59:2; + uint64_t ill_pad:1; + uint64_t reserved_61_63:3; +#endif } cn63xx; struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1; struct cvmx_sli_int_enb_ciu_cn61xx cn66xx; struct cvmx_sli_int_enb_ciu_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -523,13 +819,53 @@ union cvmx_sli_int_enb_ciu { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t reserved_18_31:14; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t reserved_51_51:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t reserved_58_59:2; + uint64_t ill_pad:1; + uint64_t pipe_err:1; + uint64_t reserved_62_63:2; +#endif } cn68xx; struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1; + struct cvmx_sli_int_enb_ciu_cn61xx cnf71xx; }; union cvmx_sli_int_enb_portx { uint64_t u64; struct cvmx_sli_int_enb_portx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -577,8 +913,58 @@ union cvmx_sli_int_enb_portx { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t mac0_int:1; + uint64_t mac1_int:1; + uint64_t m2_up_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_un_wi:1; + uint64_t m3_up_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_un_wi:1; + uint64_t reserved_28_31:4; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t sprt2_err:1; + uint64_t sprt3_err:1; + uint64_t ill_pad:1; + uint64_t pipe_err:1; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_sli_int_enb_portx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t sprt3_err:1; @@ -625,8 +1011,57 @@ union cvmx_sli_int_enb_portx { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t mac0_int:1; + uint64_t mac1_int:1; + uint64_t m2_up_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_un_wi:1; + uint64_t m3_up_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_un_wi:1; + uint64_t reserved_28_31:4; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t sprt2_err:1; + uint64_t sprt3_err:1; + uint64_t ill_pad:1; + uint64_t reserved_61_63:3; +#endif } cn61xx; struct cvmx_sli_int_enb_portx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t reserved_58_59:2; @@ -664,10 +1099,50 @@ union cvmx_sli_int_enb_portx { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t mac0_int:1; + uint64_t mac1_int:1; + uint64_t reserved_20_31:12; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t reserved_58_59:2; + uint64_t ill_pad:1; + uint64_t reserved_61_63:3; +#endif } cn63xx; struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1; struct cvmx_sli_int_enb_portx_cn61xx cn66xx; struct cvmx_sli_int_enb_portx_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -706,13 +1181,55 @@ union cvmx_sli_int_enb_portx { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t mac0_int:1; + uint64_t mac1_int:1; + uint64_t reserved_20_31:12; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t reserved_51_51:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t reserved_58_59:2; + uint64_t ill_pad:1; + uint64_t pipe_err:1; + uint64_t reserved_62_63:2; +#endif } cn68xx; struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1; + struct cvmx_sli_int_enb_portx_cn61xx cnf71xx; }; union cvmx_sli_int_sum { uint64_t u64; struct cvmx_sli_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -760,8 +1277,58 @@ union cvmx_sli_int_sum { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t mac0_int:1; + uint64_t mac1_int:1; + uint64_t m2_up_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_un_wi:1; + uint64_t m3_up_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_un_wi:1; + uint64_t reserved_28_31:4; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t sprt2_err:1; + uint64_t sprt3_err:1; + uint64_t ill_pad:1; + uint64_t pipe_err:1; + uint64_t reserved_62_63:2; +#endif } s; struct cvmx_sli_int_sum_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t sprt3_err:1; @@ -808,8 +1375,57 @@ union cvmx_sli_int_sum { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t mac0_int:1; + uint64_t mac1_int:1; + uint64_t m2_up_b0:1; + uint64_t m2_up_wi:1; + uint64_t m2_un_b0:1; + uint64_t m2_un_wi:1; + uint64_t m3_up_b0:1; + uint64_t m3_up_wi:1; + uint64_t m3_un_b0:1; + uint64_t m3_un_wi:1; + uint64_t reserved_28_31:4; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t sprt2_err:1; + uint64_t sprt3_err:1; + uint64_t ill_pad:1; + uint64_t reserved_61_63:3; +#endif } cn61xx; struct cvmx_sli_int_sum_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_61_63:3; uint64_t ill_pad:1; uint64_t reserved_58_59:2; @@ -847,10 +1463,50 @@ union cvmx_sli_int_sum { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t mac0_int:1; + uint64_t mac1_int:1; + uint64_t reserved_20_31:12; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t pin_bp:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t reserved_58_59:2; + uint64_t ill_pad:1; + uint64_t reserved_61_63:3; +#endif } cn63xx; struct cvmx_sli_int_sum_cn63xx cn63xxp1; struct cvmx_sli_int_sum_cn61xx cn66xx; struct cvmx_sli_int_sum_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_62_63:2; uint64_t pipe_err:1; uint64_t ill_pad:1; @@ -889,14 +1545,59 @@ union cvmx_sli_int_sum { uint64_t bar0_to:1; uint64_t reserved_1_1:1; uint64_t rml_to:1; +#else + uint64_t rml_to:1; + uint64_t reserved_1_1:1; + uint64_t bar0_to:1; + uint64_t iob2big:1; + uint64_t pcnt:1; + uint64_t ptime:1; + uint64_t reserved_6_7:2; + uint64_t m0_up_b0:1; + uint64_t m0_up_wi:1; + uint64_t m0_un_b0:1; + uint64_t m0_un_wi:1; + uint64_t m1_up_b0:1; + uint64_t m1_up_wi:1; + uint64_t m1_un_b0:1; + uint64_t m1_un_wi:1; + uint64_t mio_int0:1; + uint64_t mio_int1:1; + uint64_t mac0_int:1; + uint64_t mac1_int:1; + uint64_t reserved_20_31:12; + uint64_t dmafi:2; + uint64_t dcnt:2; + uint64_t dtime:2; + uint64_t reserved_38_47:10; + uint64_t pidbof:1; + uint64_t psldbof:1; + uint64_t pout_err:1; + uint64_t reserved_51_51:1; + uint64_t pgl_err:1; + uint64_t pdi_err:1; + uint64_t pop_err:1; + uint64_t pins_err:1; + uint64_t sprt0_err:1; + uint64_t sprt1_err:1; + uint64_t reserved_58_59:2; + uint64_t ill_pad:1; + uint64_t pipe_err:1; + uint64_t reserved_62_63:2; +#endif } cn68xx; struct cvmx_sli_int_sum_cn68xx cn68xxp1; + struct cvmx_sli_int_sum_cn61xx cnf71xx; }; union cvmx_sli_last_win_rdata0 { uint64_t u64; struct cvmx_sli_last_win_rdata0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_sli_last_win_rdata0_s cn61xx; struct cvmx_sli_last_win_rdata0_s cn63xx; @@ -904,12 +1605,17 @@ union cvmx_sli_last_win_rdata0 { struct cvmx_sli_last_win_rdata0_s cn66xx; struct cvmx_sli_last_win_rdata0_s cn68xx; struct cvmx_sli_last_win_rdata0_s cn68xxp1; + struct cvmx_sli_last_win_rdata0_s cnf71xx; }; union cvmx_sli_last_win_rdata1 { uint64_t u64; struct cvmx_sli_last_win_rdata1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_sli_last_win_rdata1_s cn61xx; struct cvmx_sli_last_win_rdata1_s cn63xx; @@ -917,29 +1623,41 @@ union cvmx_sli_last_win_rdata1 { struct cvmx_sli_last_win_rdata1_s cn66xx; struct cvmx_sli_last_win_rdata1_s cn68xx; struct cvmx_sli_last_win_rdata1_s cn68xxp1; + struct cvmx_sli_last_win_rdata1_s cnf71xx; }; union cvmx_sli_last_win_rdata2 { uint64_t u64; struct cvmx_sli_last_win_rdata2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_sli_last_win_rdata2_s cn61xx; struct cvmx_sli_last_win_rdata2_s cn66xx; + struct cvmx_sli_last_win_rdata2_s cnf71xx; }; union cvmx_sli_last_win_rdata3 { uint64_t u64; struct cvmx_sli_last_win_rdata3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_sli_last_win_rdata3_s cn61xx; struct cvmx_sli_last_win_rdata3_s cn66xx; + struct cvmx_sli_last_win_rdata3_s cnf71xx; }; union cvmx_sli_mac_credit_cnt { uint64_t u64; struct cvmx_sli_mac_credit_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t p1_c_d:1; uint64_t p1_n_d:1; @@ -953,10 +1671,26 @@ union cvmx_sli_mac_credit_cnt { uint64_t p0_ccnt:8; uint64_t p0_ncnt:8; uint64_t p0_pcnt:8; +#else + uint64_t p0_pcnt:8; + uint64_t p0_ncnt:8; + uint64_t p0_ccnt:8; + uint64_t p1_pcnt:8; + uint64_t p1_ncnt:8; + uint64_t p1_ccnt:8; + uint64_t p0_p_d:1; + uint64_t p0_n_d:1; + uint64_t p0_c_d:1; + uint64_t p1_p_d:1; + uint64_t p1_n_d:1; + uint64_t p1_c_d:1; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_sli_mac_credit_cnt_s cn61xx; struct cvmx_sli_mac_credit_cnt_s cn63xx; struct cvmx_sli_mac_credit_cnt_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t p1_ccnt:8; uint64_t p1_ncnt:8; @@ -964,15 +1698,26 @@ union cvmx_sli_mac_credit_cnt { uint64_t p0_ccnt:8; uint64_t p0_ncnt:8; uint64_t p0_pcnt:8; +#else + uint64_t p0_pcnt:8; + uint64_t p0_ncnt:8; + uint64_t p0_ccnt:8; + uint64_t p1_pcnt:8; + uint64_t p1_ncnt:8; + uint64_t p1_ccnt:8; + uint64_t reserved_48_63:16; +#endif } cn63xxp1; struct cvmx_sli_mac_credit_cnt_s cn66xx; struct cvmx_sli_mac_credit_cnt_s cn68xx; struct cvmx_sli_mac_credit_cnt_s cn68xxp1; + struct cvmx_sli_mac_credit_cnt_s cnf71xx; }; union cvmx_sli_mac_credit_cnt2 { uint64_t u64; struct cvmx_sli_mac_credit_cnt2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t p3_c_d:1; uint64_t p3_n_d:1; @@ -986,34 +1731,68 @@ union cvmx_sli_mac_credit_cnt2 { uint64_t p2_ccnt:8; uint64_t p2_ncnt:8; uint64_t p2_pcnt:8; +#else + uint64_t p2_pcnt:8; + uint64_t p2_ncnt:8; + uint64_t p2_ccnt:8; + uint64_t p3_pcnt:8; + uint64_t p3_ncnt:8; + uint64_t p3_ccnt:8; + uint64_t p2_p_d:1; + uint64_t p2_n_d:1; + uint64_t p2_c_d:1; + uint64_t p3_p_d:1; + uint64_t p3_n_d:1; + uint64_t p3_c_d:1; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_sli_mac_credit_cnt2_s cn61xx; struct cvmx_sli_mac_credit_cnt2_s cn66xx; + struct cvmx_sli_mac_credit_cnt2_s cnf71xx; }; union cvmx_sli_mac_number { uint64_t u64; struct cvmx_sli_mac_number_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t a_mode:1; uint64_t num:8; +#else + uint64_t num:8; + uint64_t a_mode:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_sli_mac_number_s cn61xx; struct cvmx_sli_mac_number_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t num:8; +#else + uint64_t num:8; + uint64_t reserved_8_63:56; +#endif } cn63xx; struct cvmx_sli_mac_number_s cn66xx; struct cvmx_sli_mac_number_cn63xx cn68xx; struct cvmx_sli_mac_number_cn63xx cn68xxp1; + struct cvmx_sli_mac_number_s cnf71xx; }; union cvmx_sli_mem_access_ctl { uint64_t u64; struct cvmx_sli_mem_access_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t max_word:4; uint64_t timer:10; +#else + uint64_t timer:10; + uint64_t max_word:4; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_sli_mem_access_ctl_s cn61xx; struct cvmx_sli_mem_access_ctl_s cn63xx; @@ -1021,11 +1800,13 @@ union cvmx_sli_mem_access_ctl { struct cvmx_sli_mem_access_ctl_s cn66xx; struct cvmx_sli_mem_access_ctl_s cn68xx; struct cvmx_sli_mem_access_ctl_s cn68xxp1; + struct cvmx_sli_mem_access_ctl_s cnf71xx; }; union cvmx_sli_mem_access_subidx { uint64_t u64; struct cvmx_sli_mem_access_subidx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_43_63:21; uint64_t zero:1; uint64_t port:3; @@ -1035,8 +1816,20 @@ union cvmx_sli_mem_access_subidx { uint64_t wtype:2; uint64_t rtype:2; uint64_t reserved_0_29:30; +#else + uint64_t reserved_0_29:30; + uint64_t rtype:2; + uint64_t wtype:2; + uint64_t esw:2; + uint64_t esr:2; + uint64_t nmerge:1; + uint64_t port:3; + uint64_t zero:1; + uint64_t reserved_43_63:21; +#endif } s; struct cvmx_sli_mem_access_subidx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_43_63:21; uint64_t zero:1; uint64_t port:3; @@ -1046,11 +1839,23 @@ union cvmx_sli_mem_access_subidx { uint64_t wtype:2; uint64_t rtype:2; uint64_t ba:30; +#else + uint64_t ba:30; + uint64_t rtype:2; + uint64_t wtype:2; + uint64_t esw:2; + uint64_t esr:2; + uint64_t nmerge:1; + uint64_t port:3; + uint64_t zero:1; + uint64_t reserved_43_63:21; +#endif } cn61xx; struct cvmx_sli_mem_access_subidx_cn61xx cn63xx; struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1; struct cvmx_sli_mem_access_subidx_cn61xx cn66xx; struct cvmx_sli_mem_access_subidx_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_43_63:21; uint64_t zero:1; uint64_t port:3; @@ -1061,14 +1866,31 @@ union cvmx_sli_mem_access_subidx { uint64_t rtype:2; uint64_t ba:28; uint64_t reserved_0_1:2; +#else + uint64_t reserved_0_1:2; + uint64_t ba:28; + uint64_t rtype:2; + uint64_t wtype:2; + uint64_t esw:2; + uint64_t esr:2; + uint64_t nmerge:1; + uint64_t port:3; + uint64_t zero:1; + uint64_t reserved_43_63:21; +#endif } cn68xx; struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1; + struct cvmx_sli_mem_access_subidx_cn61xx cnf71xx; }; union cvmx_sli_msi_enb0 { uint64_t u64; struct cvmx_sli_msi_enb0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t enb:64; +#else uint64_t enb:64; +#endif } s; struct cvmx_sli_msi_enb0_s cn61xx; struct cvmx_sli_msi_enb0_s cn63xx; @@ -1076,12 +1898,17 @@ union cvmx_sli_msi_enb0 { struct cvmx_sli_msi_enb0_s cn66xx; struct cvmx_sli_msi_enb0_s cn68xx; struct cvmx_sli_msi_enb0_s cn68xxp1; + struct cvmx_sli_msi_enb0_s cnf71xx; }; union cvmx_sli_msi_enb1 { uint64_t u64; struct cvmx_sli_msi_enb1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t enb:64; +#else uint64_t enb:64; +#endif } s; struct cvmx_sli_msi_enb1_s cn61xx; struct cvmx_sli_msi_enb1_s cn63xx; @@ -1089,12 +1916,17 @@ union cvmx_sli_msi_enb1 { struct cvmx_sli_msi_enb1_s cn66xx; struct cvmx_sli_msi_enb1_s cn68xx; struct cvmx_sli_msi_enb1_s cn68xxp1; + struct cvmx_sli_msi_enb1_s cnf71xx; }; union cvmx_sli_msi_enb2 { uint64_t u64; struct cvmx_sli_msi_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t enb:64; +#else uint64_t enb:64; +#endif } s; struct cvmx_sli_msi_enb2_s cn61xx; struct cvmx_sli_msi_enb2_s cn63xx; @@ -1102,12 +1934,17 @@ union cvmx_sli_msi_enb2 { struct cvmx_sli_msi_enb2_s cn66xx; struct cvmx_sli_msi_enb2_s cn68xx; struct cvmx_sli_msi_enb2_s cn68xxp1; + struct cvmx_sli_msi_enb2_s cnf71xx; }; union cvmx_sli_msi_enb3 { uint64_t u64; struct cvmx_sli_msi_enb3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t enb:64; +#else uint64_t enb:64; +#endif } s; struct cvmx_sli_msi_enb3_s cn61xx; struct cvmx_sli_msi_enb3_s cn63xx; @@ -1115,12 +1952,17 @@ union cvmx_sli_msi_enb3 { struct cvmx_sli_msi_enb3_s cn66xx; struct cvmx_sli_msi_enb3_s cn68xx; struct cvmx_sli_msi_enb3_s cn68xxp1; + struct cvmx_sli_msi_enb3_s cnf71xx; }; union cvmx_sli_msi_rcv0 { uint64_t u64; struct cvmx_sli_msi_rcv0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t intr:64; +#else uint64_t intr:64; +#endif } s; struct cvmx_sli_msi_rcv0_s cn61xx; struct cvmx_sli_msi_rcv0_s cn63xx; @@ -1128,12 +1970,17 @@ union cvmx_sli_msi_rcv0 { struct cvmx_sli_msi_rcv0_s cn66xx; struct cvmx_sli_msi_rcv0_s cn68xx; struct cvmx_sli_msi_rcv0_s cn68xxp1; + struct cvmx_sli_msi_rcv0_s cnf71xx; }; union cvmx_sli_msi_rcv1 { uint64_t u64; struct cvmx_sli_msi_rcv1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t intr:64; +#else uint64_t intr:64; +#endif } s; struct cvmx_sli_msi_rcv1_s cn61xx; struct cvmx_sli_msi_rcv1_s cn63xx; @@ -1141,12 +1988,17 @@ union cvmx_sli_msi_rcv1 { struct cvmx_sli_msi_rcv1_s cn66xx; struct cvmx_sli_msi_rcv1_s cn68xx; struct cvmx_sli_msi_rcv1_s cn68xxp1; + struct cvmx_sli_msi_rcv1_s cnf71xx; }; union cvmx_sli_msi_rcv2 { uint64_t u64; struct cvmx_sli_msi_rcv2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t intr:64; +#else uint64_t intr:64; +#endif } s; struct cvmx_sli_msi_rcv2_s cn61xx; struct cvmx_sli_msi_rcv2_s cn63xx; @@ -1154,12 +2006,17 @@ union cvmx_sli_msi_rcv2 { struct cvmx_sli_msi_rcv2_s cn66xx; struct cvmx_sli_msi_rcv2_s cn68xx; struct cvmx_sli_msi_rcv2_s cn68xxp1; + struct cvmx_sli_msi_rcv2_s cnf71xx; }; union cvmx_sli_msi_rcv3 { uint64_t u64; struct cvmx_sli_msi_rcv3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t intr:64; +#else uint64_t intr:64; +#endif } s; struct cvmx_sli_msi_rcv3_s cn61xx; struct cvmx_sli_msi_rcv3_s cn63xx; @@ -1167,14 +2024,21 @@ union cvmx_sli_msi_rcv3 { struct cvmx_sli_msi_rcv3_s cn66xx; struct cvmx_sli_msi_rcv3_s cn68xx; struct cvmx_sli_msi_rcv3_s cn68xxp1; + struct cvmx_sli_msi_rcv3_s cnf71xx; }; union cvmx_sli_msi_rd_map { uint64_t u64; struct cvmx_sli_msi_rd_map_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t rd_int:8; uint64_t msi_int:8; +#else + uint64_t msi_int:8; + uint64_t rd_int:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_sli_msi_rd_map_s cn61xx; struct cvmx_sli_msi_rd_map_s cn63xx; @@ -1182,12 +2046,17 @@ union cvmx_sli_msi_rd_map { struct cvmx_sli_msi_rd_map_s cn66xx; struct cvmx_sli_msi_rd_map_s cn68xx; struct cvmx_sli_msi_rd_map_s cn68xxp1; + struct cvmx_sli_msi_rd_map_s cnf71xx; }; union cvmx_sli_msi_w1c_enb0 { uint64_t u64; struct cvmx_sli_msi_w1c_enb0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t clr:64; +#else uint64_t clr:64; +#endif } s; struct cvmx_sli_msi_w1c_enb0_s cn61xx; struct cvmx_sli_msi_w1c_enb0_s cn63xx; @@ -1195,12 +2064,17 @@ union cvmx_sli_msi_w1c_enb0 { struct cvmx_sli_msi_w1c_enb0_s cn66xx; struct cvmx_sli_msi_w1c_enb0_s cn68xx; struct cvmx_sli_msi_w1c_enb0_s cn68xxp1; + struct cvmx_sli_msi_w1c_enb0_s cnf71xx; }; union cvmx_sli_msi_w1c_enb1 { uint64_t u64; struct cvmx_sli_msi_w1c_enb1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t clr:64; +#else uint64_t clr:64; +#endif } s; struct cvmx_sli_msi_w1c_enb1_s cn61xx; struct cvmx_sli_msi_w1c_enb1_s cn63xx; @@ -1208,12 +2082,17 @@ union cvmx_sli_msi_w1c_enb1 { struct cvmx_sli_msi_w1c_enb1_s cn66xx; struct cvmx_sli_msi_w1c_enb1_s cn68xx; struct cvmx_sli_msi_w1c_enb1_s cn68xxp1; + struct cvmx_sli_msi_w1c_enb1_s cnf71xx; }; union cvmx_sli_msi_w1c_enb2 { uint64_t u64; struct cvmx_sli_msi_w1c_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t clr:64; +#else uint64_t clr:64; +#endif } s; struct cvmx_sli_msi_w1c_enb2_s cn61xx; struct cvmx_sli_msi_w1c_enb2_s cn63xx; @@ -1221,12 +2100,17 @@ union cvmx_sli_msi_w1c_enb2 { struct cvmx_sli_msi_w1c_enb2_s cn66xx; struct cvmx_sli_msi_w1c_enb2_s cn68xx; struct cvmx_sli_msi_w1c_enb2_s cn68xxp1; + struct cvmx_sli_msi_w1c_enb2_s cnf71xx; }; union cvmx_sli_msi_w1c_enb3 { uint64_t u64; struct cvmx_sli_msi_w1c_enb3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t clr:64; +#else uint64_t clr:64; +#endif } s; struct cvmx_sli_msi_w1c_enb3_s cn61xx; struct cvmx_sli_msi_w1c_enb3_s cn63xx; @@ -1234,12 +2118,17 @@ union cvmx_sli_msi_w1c_enb3 { struct cvmx_sli_msi_w1c_enb3_s cn66xx; struct cvmx_sli_msi_w1c_enb3_s cn68xx; struct cvmx_sli_msi_w1c_enb3_s cn68xxp1; + struct cvmx_sli_msi_w1c_enb3_s cnf71xx; }; union cvmx_sli_msi_w1s_enb0 { uint64_t u64; struct cvmx_sli_msi_w1s_enb0_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t set:64; +#else uint64_t set:64; +#endif } s; struct cvmx_sli_msi_w1s_enb0_s cn61xx; struct cvmx_sli_msi_w1s_enb0_s cn63xx; @@ -1247,12 +2136,17 @@ union cvmx_sli_msi_w1s_enb0 { struct cvmx_sli_msi_w1s_enb0_s cn66xx; struct cvmx_sli_msi_w1s_enb0_s cn68xx; struct cvmx_sli_msi_w1s_enb0_s cn68xxp1; + struct cvmx_sli_msi_w1s_enb0_s cnf71xx; }; union cvmx_sli_msi_w1s_enb1 { uint64_t u64; struct cvmx_sli_msi_w1s_enb1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t set:64; +#else uint64_t set:64; +#endif } s; struct cvmx_sli_msi_w1s_enb1_s cn61xx; struct cvmx_sli_msi_w1s_enb1_s cn63xx; @@ -1260,12 +2154,17 @@ union cvmx_sli_msi_w1s_enb1 { struct cvmx_sli_msi_w1s_enb1_s cn66xx; struct cvmx_sli_msi_w1s_enb1_s cn68xx; struct cvmx_sli_msi_w1s_enb1_s cn68xxp1; + struct cvmx_sli_msi_w1s_enb1_s cnf71xx; }; union cvmx_sli_msi_w1s_enb2 { uint64_t u64; struct cvmx_sli_msi_w1s_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t set:64; +#else uint64_t set:64; +#endif } s; struct cvmx_sli_msi_w1s_enb2_s cn61xx; struct cvmx_sli_msi_w1s_enb2_s cn63xx; @@ -1273,12 +2172,17 @@ union cvmx_sli_msi_w1s_enb2 { struct cvmx_sli_msi_w1s_enb2_s cn66xx; struct cvmx_sli_msi_w1s_enb2_s cn68xx; struct cvmx_sli_msi_w1s_enb2_s cn68xxp1; + struct cvmx_sli_msi_w1s_enb2_s cnf71xx; }; union cvmx_sli_msi_w1s_enb3 { uint64_t u64; struct cvmx_sli_msi_w1s_enb3_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t set:64; +#else uint64_t set:64; +#endif } s; struct cvmx_sli_msi_w1s_enb3_s cn61xx; struct cvmx_sli_msi_w1s_enb3_s cn63xx; @@ -1286,14 +2190,21 @@ union cvmx_sli_msi_w1s_enb3 { struct cvmx_sli_msi_w1s_enb3_s cn66xx; struct cvmx_sli_msi_w1s_enb3_s cn68xx; struct cvmx_sli_msi_w1s_enb3_s cn68xxp1; + struct cvmx_sli_msi_w1s_enb3_s cnf71xx; }; union cvmx_sli_msi_wr_map { uint64_t u64; struct cvmx_sli_msi_wr_map_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ciu_int:8; uint64_t msi_int:8; +#else + uint64_t msi_int:8; + uint64_t ciu_int:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_sli_msi_wr_map_s cn61xx; struct cvmx_sli_msi_wr_map_s cn63xx; @@ -1301,13 +2212,19 @@ union cvmx_sli_msi_wr_map { struct cvmx_sli_msi_wr_map_s cn66xx; struct cvmx_sli_msi_wr_map_s cn68xx; struct cvmx_sli_msi_wr_map_s cn68xxp1; + struct cvmx_sli_msi_wr_map_s cnf71xx; }; union cvmx_sli_pcie_msi_rcv { uint64_t u64; struct cvmx_sli_pcie_msi_rcv_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t intr:8; +#else + uint64_t intr:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_sli_pcie_msi_rcv_s cn61xx; struct cvmx_sli_pcie_msi_rcv_s cn63xx; @@ -1315,14 +2232,21 @@ union cvmx_sli_pcie_msi_rcv { struct cvmx_sli_pcie_msi_rcv_s cn66xx; struct cvmx_sli_pcie_msi_rcv_s cn68xx; struct cvmx_sli_pcie_msi_rcv_s cn68xxp1; + struct cvmx_sli_pcie_msi_rcv_s cnf71xx; }; union cvmx_sli_pcie_msi_rcv_b1 { uint64_t u64; struct cvmx_sli_pcie_msi_rcv_b1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t intr:8; uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t intr:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx; struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx; @@ -1330,14 +2254,21 @@ union cvmx_sli_pcie_msi_rcv_b1 { struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx; struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx; struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1; + struct cvmx_sli_pcie_msi_rcv_b1_s cnf71xx; }; union cvmx_sli_pcie_msi_rcv_b2 { uint64_t u64; struct cvmx_sli_pcie_msi_rcv_b2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t intr:8; uint64_t reserved_0_15:16; +#else + uint64_t reserved_0_15:16; + uint64_t intr:8; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx; struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx; @@ -1345,14 +2276,21 @@ union cvmx_sli_pcie_msi_rcv_b2 { struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx; struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx; struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1; + struct cvmx_sli_pcie_msi_rcv_b2_s cnf71xx; }; union cvmx_sli_pcie_msi_rcv_b3 { uint64_t u64; struct cvmx_sli_pcie_msi_rcv_b3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t intr:8; uint64_t reserved_0_23:24; +#else + uint64_t reserved_0_23:24; + uint64_t intr:8; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx; struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx; @@ -1360,14 +2298,21 @@ union cvmx_sli_pcie_msi_rcv_b3 { struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx; struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx; struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1; + struct cvmx_sli_pcie_msi_rcv_b3_s cnf71xx; }; union cvmx_sli_pktx_cnts { uint64_t u64; struct cvmx_sli_pktx_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t timer:22; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t timer:22; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_sli_pktx_cnts_s cn61xx; struct cvmx_sli_pktx_cnts_s cn63xx; @@ -1375,25 +2320,37 @@ union cvmx_sli_pktx_cnts { struct cvmx_sli_pktx_cnts_s cn66xx; struct cvmx_sli_pktx_cnts_s cn68xx; struct cvmx_sli_pktx_cnts_s cn68xxp1; + struct cvmx_sli_pktx_cnts_s cnf71xx; }; union cvmx_sli_pktx_in_bp { uint64_t u64; struct cvmx_sli_pktx_in_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wmark:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t wmark:32; +#endif } s; struct cvmx_sli_pktx_in_bp_s cn61xx; struct cvmx_sli_pktx_in_bp_s cn63xx; struct cvmx_sli_pktx_in_bp_s cn63xxp1; struct cvmx_sli_pktx_in_bp_s cn66xx; + struct cvmx_sli_pktx_in_bp_s cnf71xx; }; union cvmx_sli_pktx_instr_baddr { uint64_t u64; struct cvmx_sli_pktx_instr_baddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:61; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t addr:61; +#endif } s; struct cvmx_sli_pktx_instr_baddr_s cn61xx; struct cvmx_sli_pktx_instr_baddr_s cn63xx; @@ -1401,13 +2358,19 @@ union cvmx_sli_pktx_instr_baddr { struct cvmx_sli_pktx_instr_baddr_s cn66xx; struct cvmx_sli_pktx_instr_baddr_s cn68xx; struct cvmx_sli_pktx_instr_baddr_s cn68xxp1; + struct cvmx_sli_pktx_instr_baddr_s cnf71xx; }; union cvmx_sli_pktx_instr_baoff_dbell { uint64_t u64; struct cvmx_sli_pktx_instr_baoff_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t aoff:32; uint64_t dbell:32; +#else + uint64_t dbell:32; + uint64_t aoff:32; +#endif } s; struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx; struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx; @@ -1415,16 +2378,25 @@ union cvmx_sli_pktx_instr_baoff_dbell { struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx; struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx; struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1; + struct cvmx_sli_pktx_instr_baoff_dbell_s cnf71xx; }; union cvmx_sli_pktx_instr_fifo_rsize { uint64_t u64; struct cvmx_sli_pktx_instr_fifo_rsize_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t max:9; uint64_t rrp:9; uint64_t wrp:9; uint64_t fcnt:5; uint64_t rsize:32; +#else + uint64_t rsize:32; + uint64_t fcnt:5; + uint64_t wrp:9; + uint64_t rrp:9; + uint64_t max:9; +#endif } s; struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx; struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx; @@ -1432,11 +2404,13 @@ union cvmx_sli_pktx_instr_fifo_rsize { struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx; struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx; struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1; + struct cvmx_sli_pktx_instr_fifo_rsize_s cnf71xx; }; union cvmx_sli_pktx_instr_header { uint64_t u64; struct cvmx_sli_pktx_instr_header_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t reserved_38_42:5; @@ -1458,8 +2432,32 @@ union cvmx_sli_pktx_instr_header { uint64_t ngrp:1; uint64_t ntt:1; uint64_t ntag:1; +#else + uint64_t ntag:1; + uint64_t ntt:1; + uint64_t ngrp:1; + uint64_t nqos:1; + uint64_t ngrpext:2; + uint64_t skp_len:7; + uint64_t reserved_13_13:1; + uint64_t par_mode:2; + uint64_t reserved_16_20:5; + uint64_t use_ihdr:1; + uint64_t rntag:1; + uint64_t rntt:1; + uint64_t rngrp:1; + uint64_t rnqos:1; + uint64_t rngrpext:2; + uint64_t rskp_len:7; + uint64_t reserved_35_35:1; + uint64_t rparmode:2; + uint64_t reserved_38_42:5; + uint64_t pbp:1; + uint64_t reserved_44_63:20; +#endif } s; struct cvmx_sli_pktx_instr_header_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t pbp:1; uint64_t reserved_38_42:5; @@ -1481,20 +2479,50 @@ union cvmx_sli_pktx_instr_header { uint64_t ngrp:1; uint64_t ntt:1; uint64_t ntag:1; +#else + uint64_t ntag:1; + uint64_t ntt:1; + uint64_t ngrp:1; + uint64_t nqos:1; + uint64_t reserved_4_5:2; + uint64_t skp_len:7; + uint64_t reserved_13_13:1; + uint64_t par_mode:2; + uint64_t reserved_16_20:5; + uint64_t use_ihdr:1; + uint64_t rntag:1; + uint64_t rntt:1; + uint64_t rngrp:1; + uint64_t rnqos:1; + uint64_t reserved_26_27:2; + uint64_t rskp_len:7; + uint64_t reserved_35_35:1; + uint64_t rparmode:2; + uint64_t reserved_38_42:5; + uint64_t pbp:1; + uint64_t reserved_44_63:20; +#endif } cn61xx; struct cvmx_sli_pktx_instr_header_cn61xx cn63xx; struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1; struct cvmx_sli_pktx_instr_header_cn61xx cn66xx; struct cvmx_sli_pktx_instr_header_s cn68xx; struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1; + struct cvmx_sli_pktx_instr_header_cn61xx cnf71xx; }; union cvmx_sli_pktx_out_size { uint64_t u64; struct cvmx_sli_pktx_out_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t isize:7; uint64_t bsize:16; +#else + uint64_t bsize:16; + uint64_t isize:7; + uint64_t reserved_23_63:41; +#endif } s; struct cvmx_sli_pktx_out_size_s cn61xx; struct cvmx_sli_pktx_out_size_s cn63xx; @@ -1502,13 +2530,19 @@ union cvmx_sli_pktx_out_size { struct cvmx_sli_pktx_out_size_s cn66xx; struct cvmx_sli_pktx_out_size_s cn68xx; struct cvmx_sli_pktx_out_size_s cn68xxp1; + struct cvmx_sli_pktx_out_size_s cnf71xx; }; union cvmx_sli_pktx_slist_baddr { uint64_t u64; struct cvmx_sli_pktx_slist_baddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t addr:60; uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t addr:60; +#endif } s; struct cvmx_sli_pktx_slist_baddr_s cn61xx; struct cvmx_sli_pktx_slist_baddr_s cn63xx; @@ -1516,13 +2550,19 @@ union cvmx_sli_pktx_slist_baddr { struct cvmx_sli_pktx_slist_baddr_s cn66xx; struct cvmx_sli_pktx_slist_baddr_s cn68xx; struct cvmx_sli_pktx_slist_baddr_s cn68xxp1; + struct cvmx_sli_pktx_slist_baddr_s cnf71xx; }; union cvmx_sli_pktx_slist_baoff_dbell { uint64_t u64; struct cvmx_sli_pktx_slist_baoff_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t aoff:32; uint64_t dbell:32; +#else + uint64_t dbell:32; + uint64_t aoff:32; +#endif } s; struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx; struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx; @@ -1530,13 +2570,19 @@ union cvmx_sli_pktx_slist_baoff_dbell { struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx; struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx; struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1; + struct cvmx_sli_pktx_slist_baoff_dbell_s cnf71xx; }; union cvmx_sli_pktx_slist_fifo_rsize { uint64_t u64; struct cvmx_sli_pktx_slist_fifo_rsize_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t rsize:32; +#else + uint64_t rsize:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx; struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx; @@ -1544,13 +2590,19 @@ union cvmx_sli_pktx_slist_fifo_rsize { struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx; struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx; struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1; + struct cvmx_sli_pktx_slist_fifo_rsize_s cnf71xx; }; union cvmx_sli_pkt_cnt_int { uint64_t u64; struct cvmx_sli_pkt_cnt_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; +#else + uint64_t port:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_cnt_int_s cn61xx; struct cvmx_sli_pkt_cnt_int_s cn63xx; @@ -1558,13 +2610,19 @@ union cvmx_sli_pkt_cnt_int { struct cvmx_sli_pkt_cnt_int_s cn66xx; struct cvmx_sli_pkt_cnt_int_s cn68xx; struct cvmx_sli_pkt_cnt_int_s cn68xxp1; + struct cvmx_sli_pkt_cnt_int_s cnf71xx; }; union cvmx_sli_pkt_cnt_int_enb { uint64_t u64; struct cvmx_sli_pkt_cnt_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; +#else + uint64_t port:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_cnt_int_enb_s cn61xx; struct cvmx_sli_pkt_cnt_int_enb_s cn63xx; @@ -1572,14 +2630,21 @@ union cvmx_sli_pkt_cnt_int_enb { struct cvmx_sli_pkt_cnt_int_enb_s cn66xx; struct cvmx_sli_pkt_cnt_int_enb_s cn68xx; struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1; + struct cvmx_sli_pkt_cnt_int_enb_s cnf71xx; }; union cvmx_sli_pkt_ctl { uint64_t u64; struct cvmx_sli_pkt_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t ring_en:1; uint64_t pkt_bp:4; +#else + uint64_t pkt_bp:4; + uint64_t ring_en:1; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_sli_pkt_ctl_s cn61xx; struct cvmx_sli_pkt_ctl_s cn63xx; @@ -1587,12 +2652,17 @@ union cvmx_sli_pkt_ctl { struct cvmx_sli_pkt_ctl_s cn66xx; struct cvmx_sli_pkt_ctl_s cn68xx; struct cvmx_sli_pkt_ctl_s cn68xxp1; + struct cvmx_sli_pkt_ctl_s cnf71xx; }; union cvmx_sli_pkt_data_out_es { uint64_t u64; struct cvmx_sli_pkt_data_out_es_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t es:64; +#else uint64_t es:64; +#endif } s; struct cvmx_sli_pkt_data_out_es_s cn61xx; struct cvmx_sli_pkt_data_out_es_s cn63xx; @@ -1600,13 +2670,19 @@ union cvmx_sli_pkt_data_out_es { struct cvmx_sli_pkt_data_out_es_s cn66xx; struct cvmx_sli_pkt_data_out_es_s cn68xx; struct cvmx_sli_pkt_data_out_es_s cn68xxp1; + struct cvmx_sli_pkt_data_out_es_s cnf71xx; }; union cvmx_sli_pkt_data_out_ns { uint64_t u64; struct cvmx_sli_pkt_data_out_ns_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t nsr:32; +#else + uint64_t nsr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_data_out_ns_s cn61xx; struct cvmx_sli_pkt_data_out_ns_s cn63xx; @@ -1614,13 +2690,19 @@ union cvmx_sli_pkt_data_out_ns { struct cvmx_sli_pkt_data_out_ns_s cn66xx; struct cvmx_sli_pkt_data_out_ns_s cn68xx; struct cvmx_sli_pkt_data_out_ns_s cn68xxp1; + struct cvmx_sli_pkt_data_out_ns_s cnf71xx; }; union cvmx_sli_pkt_data_out_ror { uint64_t u64; struct cvmx_sli_pkt_data_out_ror_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ror:32; +#else + uint64_t ror:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_data_out_ror_s cn61xx; struct cvmx_sli_pkt_data_out_ror_s cn63xx; @@ -1628,13 +2710,19 @@ union cvmx_sli_pkt_data_out_ror { struct cvmx_sli_pkt_data_out_ror_s cn66xx; struct cvmx_sli_pkt_data_out_ror_s cn68xx; struct cvmx_sli_pkt_data_out_ror_s cn68xxp1; + struct cvmx_sli_pkt_data_out_ror_s cnf71xx; }; union cvmx_sli_pkt_dpaddr { uint64_t u64; struct cvmx_sli_pkt_dpaddr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t dptr:32; +#else + uint64_t dptr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_dpaddr_s cn61xx; struct cvmx_sli_pkt_dpaddr_s cn63xx; @@ -1642,25 +2730,37 @@ union cvmx_sli_pkt_dpaddr { struct cvmx_sli_pkt_dpaddr_s cn66xx; struct cvmx_sli_pkt_dpaddr_s cn68xx; struct cvmx_sli_pkt_dpaddr_s cn68xxp1; + struct cvmx_sli_pkt_dpaddr_s cnf71xx; }; union cvmx_sli_pkt_in_bp { uint64_t u64; struct cvmx_sli_pkt_in_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bp:32; +#else + uint64_t bp:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_in_bp_s cn61xx; struct cvmx_sli_pkt_in_bp_s cn63xx; struct cvmx_sli_pkt_in_bp_s cn63xxp1; struct cvmx_sli_pkt_in_bp_s cn66xx; + struct cvmx_sli_pkt_in_bp_s cnf71xx; }; union cvmx_sli_pkt_in_donex_cnts { uint64_t u64; struct cvmx_sli_pkt_in_donex_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_in_donex_cnts_s cn61xx; struct cvmx_sli_pkt_in_donex_cnts_s cn63xx; @@ -1668,13 +2768,19 @@ union cvmx_sli_pkt_in_donex_cnts { struct cvmx_sli_pkt_in_donex_cnts_s cn66xx; struct cvmx_sli_pkt_in_donex_cnts_s cn68xx; struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1; + struct cvmx_sli_pkt_in_donex_cnts_s cnf71xx; }; union cvmx_sli_pkt_in_instr_counts { uint64_t u64; struct cvmx_sli_pkt_in_instr_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_cnt:32; uint64_t rd_cnt:32; +#else + uint64_t rd_cnt:32; + uint64_t wr_cnt:32; +#endif } s; struct cvmx_sli_pkt_in_instr_counts_s cn61xx; struct cvmx_sli_pkt_in_instr_counts_s cn63xx; @@ -1682,12 +2788,17 @@ union cvmx_sli_pkt_in_instr_counts { struct cvmx_sli_pkt_in_instr_counts_s cn66xx; struct cvmx_sli_pkt_in_instr_counts_s cn68xx; struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1; + struct cvmx_sli_pkt_in_instr_counts_s cnf71xx; }; union cvmx_sli_pkt_in_pcie_port { uint64_t u64; struct cvmx_sli_pkt_in_pcie_port_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t pp:64; +#else uint64_t pp:64; +#endif } s; struct cvmx_sli_pkt_in_pcie_port_s cn61xx; struct cvmx_sli_pkt_in_pcie_port_s cn63xx; @@ -1695,11 +2806,13 @@ union cvmx_sli_pkt_in_pcie_port { struct cvmx_sli_pkt_in_pcie_port_s cn66xx; struct cvmx_sli_pkt_in_pcie_port_s cn68xx; struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1; + struct cvmx_sli_pkt_in_pcie_port_s cnf71xx; }; union cvmx_sli_pkt_input_control { uint64_t u64; struct cvmx_sli_pkt_input_control_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t prd_erst:1; uint64_t prd_rds:7; uint64_t gii_erst:1; @@ -1717,9 +2830,29 @@ union cvmx_sli_pkt_input_control { uint64_t nsr:1; uint64_t esr:2; uint64_t ror:1; +#else + uint64_t ror:1; + uint64_t esr:2; + uint64_t nsr:1; + uint64_t use_csr:1; + uint64_t d_ror:1; + uint64_t d_esr:2; + uint64_t d_nsr:1; + uint64_t pbp_dhi:13; + uint64_t pkt_rr:1; + uint64_t pin_rst:1; + uint64_t reserved_24_39:16; + uint64_t prc_idle:1; + uint64_t reserved_41_47:7; + uint64_t gii_rds:7; + uint64_t gii_erst:1; + uint64_t prd_rds:7; + uint64_t prd_erst:1; +#endif } s; struct cvmx_sli_pkt_input_control_s cn61xx; struct cvmx_sli_pkt_input_control_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_23_63:41; uint64_t pkt_rr:1; uint64_t pbp_dhi:13; @@ -1730,18 +2863,36 @@ union cvmx_sli_pkt_input_control { uint64_t nsr:1; uint64_t esr:2; uint64_t ror:1; +#else + uint64_t ror:1; + uint64_t esr:2; + uint64_t nsr:1; + uint64_t use_csr:1; + uint64_t d_ror:1; + uint64_t d_esr:2; + uint64_t d_nsr:1; + uint64_t pbp_dhi:13; + uint64_t pkt_rr:1; + uint64_t reserved_23_63:41; +#endif } cn63xx; struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1; struct cvmx_sli_pkt_input_control_s cn66xx; struct cvmx_sli_pkt_input_control_s cn68xx; struct cvmx_sli_pkt_input_control_s cn68xxp1; + struct cvmx_sli_pkt_input_control_s cnf71xx; }; union cvmx_sli_pkt_instr_enb { uint64_t u64; struct cvmx_sli_pkt_instr_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enb:32; +#else + uint64_t enb:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_instr_enb_s cn61xx; struct cvmx_sli_pkt_instr_enb_s cn63xx; @@ -1749,12 +2900,17 @@ union cvmx_sli_pkt_instr_enb { struct cvmx_sli_pkt_instr_enb_s cn66xx; struct cvmx_sli_pkt_instr_enb_s cn68xx; struct cvmx_sli_pkt_instr_enb_s cn68xxp1; + struct cvmx_sli_pkt_instr_enb_s cnf71xx; }; union cvmx_sli_pkt_instr_rd_size { uint64_t u64; struct cvmx_sli_pkt_instr_rd_size_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rdsize:64; +#else uint64_t rdsize:64; +#endif } s; struct cvmx_sli_pkt_instr_rd_size_s cn61xx; struct cvmx_sli_pkt_instr_rd_size_s cn63xx; @@ -1762,13 +2918,19 @@ union cvmx_sli_pkt_instr_rd_size { struct cvmx_sli_pkt_instr_rd_size_s cn66xx; struct cvmx_sli_pkt_instr_rd_size_s cn68xx; struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1; + struct cvmx_sli_pkt_instr_rd_size_s cnf71xx; }; union cvmx_sli_pkt_instr_size { uint64_t u64; struct cvmx_sli_pkt_instr_size_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t is_64b:32; +#else + uint64_t is_64b:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_instr_size_s cn61xx; struct cvmx_sli_pkt_instr_size_s cn63xx; @@ -1776,14 +2938,21 @@ union cvmx_sli_pkt_instr_size { struct cvmx_sli_pkt_instr_size_s cn66xx; struct cvmx_sli_pkt_instr_size_s cn68xx; struct cvmx_sli_pkt_instr_size_s cn68xxp1; + struct cvmx_sli_pkt_instr_size_s cnf71xx; }; union cvmx_sli_pkt_int_levels { uint64_t u64; struct cvmx_sli_pkt_int_levels_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t time:22; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t time:22; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_sli_pkt_int_levels_s cn61xx; struct cvmx_sli_pkt_int_levels_s cn63xx; @@ -1791,13 +2960,19 @@ union cvmx_sli_pkt_int_levels { struct cvmx_sli_pkt_int_levels_s cn66xx; struct cvmx_sli_pkt_int_levels_s cn68xx; struct cvmx_sli_pkt_int_levels_s cn68xxp1; + struct cvmx_sli_pkt_int_levels_s cnf71xx; }; union cvmx_sli_pkt_iptr { uint64_t u64; struct cvmx_sli_pkt_iptr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t iptr:32; +#else + uint64_t iptr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_iptr_s cn61xx; struct cvmx_sli_pkt_iptr_s cn63xx; @@ -1805,13 +2980,19 @@ union cvmx_sli_pkt_iptr { struct cvmx_sli_pkt_iptr_s cn66xx; struct cvmx_sli_pkt_iptr_s cn68xx; struct cvmx_sli_pkt_iptr_s cn68xxp1; + struct cvmx_sli_pkt_iptr_s cnf71xx; }; union cvmx_sli_pkt_out_bmode { uint64_t u64; struct cvmx_sli_pkt_out_bmode_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bmode:32; +#else + uint64_t bmode:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_out_bmode_s cn61xx; struct cvmx_sli_pkt_out_bmode_s cn63xx; @@ -1819,13 +3000,19 @@ union cvmx_sli_pkt_out_bmode { struct cvmx_sli_pkt_out_bmode_s cn66xx; struct cvmx_sli_pkt_out_bmode_s cn68xx; struct cvmx_sli_pkt_out_bmode_s cn68xxp1; + struct cvmx_sli_pkt_out_bmode_s cnf71xx; }; union cvmx_sli_pkt_out_bp_en { uint64_t u64; struct cvmx_sli_pkt_out_bp_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bp_en:32; +#else + uint64_t bp_en:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_out_bp_en_s cn68xx; struct cvmx_sli_pkt_out_bp_en_s cn68xxp1; @@ -1834,8 +3021,13 @@ union cvmx_sli_pkt_out_bp_en { union cvmx_sli_pkt_out_enb { uint64_t u64; struct cvmx_sli_pkt_out_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enb:32; +#else + uint64_t enb:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_out_enb_s cn61xx; struct cvmx_sli_pkt_out_enb_s cn63xx; @@ -1843,13 +3035,19 @@ union cvmx_sli_pkt_out_enb { struct cvmx_sli_pkt_out_enb_s cn66xx; struct cvmx_sli_pkt_out_enb_s cn68xx; struct cvmx_sli_pkt_out_enb_s cn68xxp1; + struct cvmx_sli_pkt_out_enb_s cnf71xx; }; union cvmx_sli_pkt_output_wmark { uint64_t u64; struct cvmx_sli_pkt_output_wmark_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t wmark:32; +#else + uint64_t wmark:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_output_wmark_s cn61xx; struct cvmx_sli_pkt_output_wmark_s cn63xx; @@ -1857,12 +3055,17 @@ union cvmx_sli_pkt_output_wmark { struct cvmx_sli_pkt_output_wmark_s cn66xx; struct cvmx_sli_pkt_output_wmark_s cn68xx; struct cvmx_sli_pkt_output_wmark_s cn68xxp1; + struct cvmx_sli_pkt_output_wmark_s cnf71xx; }; union cvmx_sli_pkt_pcie_port { uint64_t u64; struct cvmx_sli_pkt_pcie_port_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t pp:64; +#else uint64_t pp:64; +#endif } s; struct cvmx_sli_pkt_pcie_port_s cn61xx; struct cvmx_sli_pkt_pcie_port_s cn63xx; @@ -1870,13 +3073,19 @@ union cvmx_sli_pkt_pcie_port { struct cvmx_sli_pkt_pcie_port_s cn66xx; struct cvmx_sli_pkt_pcie_port_s cn68xx; struct cvmx_sli_pkt_pcie_port_s cn68xxp1; + struct cvmx_sli_pkt_pcie_port_s cnf71xx; }; union cvmx_sli_pkt_port_in_rst { uint64_t u64; struct cvmx_sli_pkt_port_in_rst_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t in_rst:32; uint64_t out_rst:32; +#else + uint64_t out_rst:32; + uint64_t in_rst:32; +#endif } s; struct cvmx_sli_pkt_port_in_rst_s cn61xx; struct cvmx_sli_pkt_port_in_rst_s cn63xx; @@ -1884,12 +3093,17 @@ union cvmx_sli_pkt_port_in_rst { struct cvmx_sli_pkt_port_in_rst_s cn66xx; struct cvmx_sli_pkt_port_in_rst_s cn68xx; struct cvmx_sli_pkt_port_in_rst_s cn68xxp1; + struct cvmx_sli_pkt_port_in_rst_s cnf71xx; }; union cvmx_sli_pkt_slist_es { uint64_t u64; struct cvmx_sli_pkt_slist_es_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t es:64; +#else + uint64_t es:64; +#endif } s; struct cvmx_sli_pkt_slist_es_s cn61xx; struct cvmx_sli_pkt_slist_es_s cn63xx; @@ -1897,13 +3111,19 @@ union cvmx_sli_pkt_slist_es { struct cvmx_sli_pkt_slist_es_s cn66xx; struct cvmx_sli_pkt_slist_es_s cn68xx; struct cvmx_sli_pkt_slist_es_s cn68xxp1; + struct cvmx_sli_pkt_slist_es_s cnf71xx; }; union cvmx_sli_pkt_slist_ns { uint64_t u64; struct cvmx_sli_pkt_slist_ns_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t nsr:32; +#else + uint64_t nsr:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_slist_ns_s cn61xx; struct cvmx_sli_pkt_slist_ns_s cn63xx; @@ -1911,13 +3131,19 @@ union cvmx_sli_pkt_slist_ns { struct cvmx_sli_pkt_slist_ns_s cn66xx; struct cvmx_sli_pkt_slist_ns_s cn68xx; struct cvmx_sli_pkt_slist_ns_s cn68xxp1; + struct cvmx_sli_pkt_slist_ns_s cnf71xx; }; union cvmx_sli_pkt_slist_ror { uint64_t u64; struct cvmx_sli_pkt_slist_ror_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t ror:32; +#else + uint64_t ror:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_slist_ror_s cn61xx; struct cvmx_sli_pkt_slist_ror_s cn63xx; @@ -1925,13 +3151,19 @@ union cvmx_sli_pkt_slist_ror { struct cvmx_sli_pkt_slist_ror_s cn66xx; struct cvmx_sli_pkt_slist_ror_s cn68xx; struct cvmx_sli_pkt_slist_ror_s cn68xxp1; + struct cvmx_sli_pkt_slist_ror_s cnf71xx; }; union cvmx_sli_pkt_time_int { uint64_t u64; struct cvmx_sli_pkt_time_int_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; +#else + uint64_t port:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_time_int_s cn61xx; struct cvmx_sli_pkt_time_int_s cn63xx; @@ -1939,13 +3171,19 @@ union cvmx_sli_pkt_time_int { struct cvmx_sli_pkt_time_int_s cn66xx; struct cvmx_sli_pkt_time_int_s cn68xx; struct cvmx_sli_pkt_time_int_s cn68xxp1; + struct cvmx_sli_pkt_time_int_s cnf71xx; }; union cvmx_sli_pkt_time_int_enb { uint64_t u64; struct cvmx_sli_pkt_time_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t port:32; +#else + uint64_t port:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_pkt_time_int_enb_s cn61xx; struct cvmx_sli_pkt_time_int_enb_s cn63xx; @@ -1953,11 +3191,13 @@ union cvmx_sli_pkt_time_int_enb { struct cvmx_sli_pkt_time_int_enb_s cn66xx; struct cvmx_sli_pkt_time_int_enb_s cn68xx; struct cvmx_sli_pkt_time_int_enb_s cn68xxp1; + struct cvmx_sli_pkt_time_int_enb_s cnf71xx; }; union cvmx_sli_portx_pkind { uint64_t u64; struct cvmx_sli_portx_pkind_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t rpk_enb:1; uint64_t reserved_22_23:2; @@ -1966,23 +3206,47 @@ union cvmx_sli_portx_pkind { uint64_t bpkind:6; uint64_t reserved_6_7:2; uint64_t pkind:6; +#else + uint64_t pkind:6; + uint64_t reserved_6_7:2; + uint64_t bpkind:6; + uint64_t reserved_14_15:2; + uint64_t pkindr:6; + uint64_t reserved_22_23:2; + uint64_t rpk_enb:1; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_sli_portx_pkind_s cn68xx; struct cvmx_sli_portx_pkind_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t bpkind:6; uint64_t reserved_6_7:2; uint64_t pkind:6; +#else + uint64_t pkind:6; + uint64_t reserved_6_7:2; + uint64_t bpkind:6; + uint64_t reserved_14_63:50; +#endif } cn68xxp1; }; union cvmx_sli_s2m_portx_ctl { uint64_t u64; struct cvmx_sli_s2m_portx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t wind_d:1; uint64_t bar0_d:1; uint64_t mrrs:3; +#else + uint64_t mrrs:3; + uint64_t bar0_d:1; + uint64_t wind_d:1; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_sli_s2m_portx_ctl_s cn61xx; struct cvmx_sli_s2m_portx_ctl_s cn63xx; @@ -1990,12 +3254,17 @@ union cvmx_sli_s2m_portx_ctl { struct cvmx_sli_s2m_portx_ctl_s cn66xx; struct cvmx_sli_s2m_portx_ctl_s cn68xx; struct cvmx_sli_s2m_portx_ctl_s cn68xxp1; + struct cvmx_sli_s2m_portx_ctl_s cnf71xx; }; union cvmx_sli_scratch_1 { uint64_t u64; struct cvmx_sli_scratch_1_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_sli_scratch_1_s cn61xx; struct cvmx_sli_scratch_1_s cn63xx; @@ -2003,12 +3272,17 @@ union cvmx_sli_scratch_1 { struct cvmx_sli_scratch_1_s cn66xx; struct cvmx_sli_scratch_1_s cn68xx; struct cvmx_sli_scratch_1_s cn68xxp1; + struct cvmx_sli_scratch_1_s cnf71xx; }; union cvmx_sli_scratch_2 { uint64_t u64; struct cvmx_sli_scratch_2_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t data:64; +#else uint64_t data:64; +#endif } s; struct cvmx_sli_scratch_2_s cn61xx; struct cvmx_sli_scratch_2_s cn63xx; @@ -2016,15 +3290,23 @@ union cvmx_sli_scratch_2 { struct cvmx_sli_scratch_2_s cn66xx; struct cvmx_sli_scratch_2_s cn68xx; struct cvmx_sli_scratch_2_s cn68xxp1; + struct cvmx_sli_scratch_2_s cnf71xx; }; union cvmx_sli_state1 { uint64_t u64; struct cvmx_sli_state1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t cpl1:12; uint64_t cpl0:12; uint64_t arb:1; uint64_t csr:39; +#else + uint64_t csr:39; + uint64_t arb:1; + uint64_t cpl0:12; + uint64_t cpl1:12; +#endif } s; struct cvmx_sli_state1_s cn61xx; struct cvmx_sli_state1_s cn63xx; @@ -2032,11 +3314,13 @@ union cvmx_sli_state1 { struct cvmx_sli_state1_s cn66xx; struct cvmx_sli_state1_s cn68xx; struct cvmx_sli_state1_s cn68xxp1; + struct cvmx_sli_state1_s cnf71xx; }; union cvmx_sli_state2 { uint64_t u64; struct cvmx_sli_state2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t nnp1:8; uint64_t reserved_47_47:1; @@ -2045,6 +3329,16 @@ union cvmx_sli_state2 { uint64_t csm0:15; uint64_t nnp0:8; uint64_t nnd:8; +#else + uint64_t nnd:8; + uint64_t nnp0:8; + uint64_t csm0:15; + uint64_t csm1:15; + uint64_t rac:1; + uint64_t reserved_47_47:1; + uint64_t nnp1:8; + uint64_t reserved_56_63:8; +#endif } s; struct cvmx_sli_state2_s cn61xx; struct cvmx_sli_state2_s cn63xx; @@ -2052,16 +3346,25 @@ union cvmx_sli_state2 { struct cvmx_sli_state2_s cn66xx; struct cvmx_sli_state2_s cn68xx; struct cvmx_sli_state2_s cn68xxp1; + struct cvmx_sli_state2_s cnf71xx; }; union cvmx_sli_state3 { uint64_t u64; struct cvmx_sli_state3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t psm1:15; uint64_t psm0:15; uint64_t nsm1:13; uint64_t nsm0:13; +#else + uint64_t nsm0:13; + uint64_t nsm1:13; + uint64_t psm0:15; + uint64_t psm1:15; + uint64_t reserved_56_63:8; +#endif } s; struct cvmx_sli_state3_s cn61xx; struct cvmx_sli_state3_s cn63xx; @@ -2069,15 +3372,23 @@ union cvmx_sli_state3 { struct cvmx_sli_state3_s cn66xx; struct cvmx_sli_state3_s cn68xx; struct cvmx_sli_state3_s cn68xxp1; + struct cvmx_sli_state3_s cnf71xx; }; union cvmx_sli_tx_pipe { uint64_t u64; struct cvmx_sli_tx_pipe_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t nump:8; uint64_t reserved_7_15:9; uint64_t base:7; +#else + uint64_t base:7; + uint64_t reserved_7_15:9; + uint64_t nump:8; + uint64_t reserved_24_63:40; +#endif } s; struct cvmx_sli_tx_pipe_s cn68xx; struct cvmx_sli_tx_pipe_s cn68xxp1; @@ -2086,10 +3397,17 @@ union cvmx_sli_tx_pipe { union cvmx_sli_win_rd_addr { uint64_t u64; struct cvmx_sli_win_rd_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_51_63:13; uint64_t ld_cmd:2; uint64_t iobit:1; uint64_t rd_addr:48; +#else + uint64_t rd_addr:48; + uint64_t iobit:1; + uint64_t ld_cmd:2; + uint64_t reserved_51_63:13; +#endif } s; struct cvmx_sli_win_rd_addr_s cn61xx; struct cvmx_sli_win_rd_addr_s cn63xx; @@ -2097,12 +3415,17 @@ union cvmx_sli_win_rd_addr { struct cvmx_sli_win_rd_addr_s cn66xx; struct cvmx_sli_win_rd_addr_s cn68xx; struct cvmx_sli_win_rd_addr_s cn68xxp1; + struct cvmx_sli_win_rd_addr_s cnf71xx; }; union cvmx_sli_win_rd_data { uint64_t u64; struct cvmx_sli_win_rd_data_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t rd_data:64; +#else uint64_t rd_data:64; +#endif } s; struct cvmx_sli_win_rd_data_s cn61xx; struct cvmx_sli_win_rd_data_s cn63xx; @@ -2110,15 +3433,23 @@ union cvmx_sli_win_rd_data { struct cvmx_sli_win_rd_data_s cn66xx; struct cvmx_sli_win_rd_data_s cn68xx; struct cvmx_sli_win_rd_data_s cn68xxp1; + struct cvmx_sli_win_rd_data_s cnf71xx; }; union cvmx_sli_win_wr_addr { uint64_t u64; struct cvmx_sli_win_wr_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_49_63:15; uint64_t iobit:1; uint64_t wr_addr:45; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t wr_addr:45; + uint64_t iobit:1; + uint64_t reserved_49_63:15; +#endif } s; struct cvmx_sli_win_wr_addr_s cn61xx; struct cvmx_sli_win_wr_addr_s cn63xx; @@ -2126,12 +3457,17 @@ union cvmx_sli_win_wr_addr { struct cvmx_sli_win_wr_addr_s cn66xx; struct cvmx_sli_win_wr_addr_s cn68xx; struct cvmx_sli_win_wr_addr_s cn68xxp1; + struct cvmx_sli_win_wr_addr_s cnf71xx; }; union cvmx_sli_win_wr_data { uint64_t u64; struct cvmx_sli_win_wr_data_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_data:64; +#else + uint64_t wr_data:64; +#endif } s; struct cvmx_sli_win_wr_data_s cn61xx; struct cvmx_sli_win_wr_data_s cn63xx; @@ -2139,13 +3475,19 @@ union cvmx_sli_win_wr_data { struct cvmx_sli_win_wr_data_s cn66xx; struct cvmx_sli_win_wr_data_s cn68xx; struct cvmx_sli_win_wr_data_s cn68xxp1; + struct cvmx_sli_win_wr_data_s cnf71xx; }; union cvmx_sli_win_wr_mask { uint64_t u64; struct cvmx_sli_win_wr_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t wr_mask:8; +#else + uint64_t wr_mask:8; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_sli_win_wr_mask_s cn61xx; struct cvmx_sli_win_wr_mask_s cn63xx; @@ -2153,13 +3495,19 @@ union cvmx_sli_win_wr_mask { struct cvmx_sli_win_wr_mask_s cn66xx; struct cvmx_sli_win_wr_mask_s cn68xx; struct cvmx_sli_win_wr_mask_s cn68xxp1; + struct cvmx_sli_win_wr_mask_s cnf71xx; }; union cvmx_sli_window_ctl { uint64_t u64; struct cvmx_sli_window_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t time:32; +#else + uint64_t time:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sli_window_ctl_s cn61xx; struct cvmx_sli_window_ctl_s cn63xx; @@ -2167,6 +3515,7 @@ union cvmx_sli_window_ctl { struct cvmx_sli_window_ctl_s cn66xx; struct cvmx_sli_window_ctl_s cn68xx; struct cvmx_sli_window_ctl_s cn68xxp1; + struct cvmx_sli_window_ctl_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/arch/mips/include/asm/octeon/cvmx-smix-defs.h index 4f3c0666e94..8a278e6ddba 100644 --- a/arch/mips/include/asm/octeon/cvmx-smix-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-smix-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,15 +28,120 @@ #ifndef __CVMX_SMIX_DEFS_H__ #define __CVMX_SMIX_DEFS_H__ -#define CVMX_SMIX_CLK(offset) (CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256) -#define CVMX_SMIX_CMD(offset) (CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256) -#define CVMX_SMIX_EN(offset) (CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256) -#define CVMX_SMIX_RD_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256) -#define CVMX_SMIX_WR_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256) +static inline uint64_t CVMX_SMIX_CLK(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000003818ull) + (offset) * 128; + } + return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256; +} + +static inline uint64_t CVMX_SMIX_CMD(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000003800ull) + (offset) * 128; + } + return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256; +} + +static inline uint64_t CVMX_SMIX_EN(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000003820ull) + (offset) * 128; + } + return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256; +} + +static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000003810ull) + (offset) * 128; + } + return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256; +} + +static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180000003808ull) + (offset) * 128; + } + return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256; +} union cvmx_smix_clk { uint64_t u64; struct cvmx_smix_clk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t mode:1; uint64_t reserved_21_23:3; @@ -47,8 +152,21 @@ union cvmx_smix_clk { uint64_t preamble:1; uint64_t sample:4; uint64_t phase:8; +#else + uint64_t phase:8; + uint64_t sample:4; + uint64_t preamble:1; + uint64_t clk_idle:1; + uint64_t reserved_14_14:1; + uint64_t sample_mode:1; + uint64_t sample_hi:5; + uint64_t reserved_21_23:3; + uint64_t mode:1; + uint64_t reserved_25_63:39; +#endif } s; struct cvmx_smix_clk_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_21_63:43; uint64_t sample_hi:5; uint64_t sample_mode:1; @@ -57,6 +175,16 @@ union cvmx_smix_clk { uint64_t preamble:1; uint64_t sample:4; uint64_t phase:8; +#else + uint64_t phase:8; + uint64_t sample:4; + uint64_t preamble:1; + uint64_t clk_idle:1; + uint64_t reserved_14_14:1; + uint64_t sample_mode:1; + uint64_t sample_hi:5; + uint64_t reserved_21_63:43; +#endif } cn30xx; struct cvmx_smix_clk_cn30xx cn31xx; struct cvmx_smix_clk_cn30xx cn38xx; @@ -68,27 +196,50 @@ union cvmx_smix_clk { struct cvmx_smix_clk_s cn56xxp1; struct cvmx_smix_clk_cn30xx cn58xx; struct cvmx_smix_clk_cn30xx cn58xxp1; + struct cvmx_smix_clk_s cn61xx; struct cvmx_smix_clk_s cn63xx; struct cvmx_smix_clk_s cn63xxp1; + struct cvmx_smix_clk_s cn66xx; + struct cvmx_smix_clk_s cn68xx; + struct cvmx_smix_clk_s cn68xxp1; + struct cvmx_smix_clk_s cnf71xx; }; union cvmx_smix_cmd { uint64_t u64; struct cvmx_smix_cmd_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t phy_op:2; uint64_t reserved_13_15:3; uint64_t phy_adr:5; uint64_t reserved_5_7:3; uint64_t reg_adr:5; +#else + uint64_t reg_adr:5; + uint64_t reserved_5_7:3; + uint64_t phy_adr:5; + uint64_t reserved_13_15:3; + uint64_t phy_op:2; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_smix_cmd_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t phy_op:1; uint64_t reserved_13_15:3; uint64_t phy_adr:5; uint64_t reserved_5_7:3; uint64_t reg_adr:5; +#else + uint64_t reg_adr:5; + uint64_t reserved_5_7:3; + uint64_t phy_adr:5; + uint64_t reserved_13_15:3; + uint64_t phy_op:1; + uint64_t reserved_17_63:47; +#endif } cn30xx; struct cvmx_smix_cmd_cn30xx cn31xx; struct cvmx_smix_cmd_cn30xx cn38xx; @@ -100,15 +251,25 @@ union cvmx_smix_cmd { struct cvmx_smix_cmd_s cn56xxp1; struct cvmx_smix_cmd_cn30xx cn58xx; struct cvmx_smix_cmd_cn30xx cn58xxp1; + struct cvmx_smix_cmd_s cn61xx; struct cvmx_smix_cmd_s cn63xx; struct cvmx_smix_cmd_s cn63xxp1; + struct cvmx_smix_cmd_s cn66xx; + struct cvmx_smix_cmd_s cn68xx; + struct cvmx_smix_cmd_s cn68xxp1; + struct cvmx_smix_cmd_s cnf71xx; }; union cvmx_smix_en { uint64_t u64; struct cvmx_smix_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t en:1; +#else + uint64_t en:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_smix_en_s cn30xx; struct cvmx_smix_en_s cn31xx; @@ -121,17 +282,29 @@ union cvmx_smix_en { struct cvmx_smix_en_s cn56xxp1; struct cvmx_smix_en_s cn58xx; struct cvmx_smix_en_s cn58xxp1; + struct cvmx_smix_en_s cn61xx; struct cvmx_smix_en_s cn63xx; struct cvmx_smix_en_s cn63xxp1; + struct cvmx_smix_en_s cn66xx; + struct cvmx_smix_en_s cn68xx; + struct cvmx_smix_en_s cn68xxp1; + struct cvmx_smix_en_s cnf71xx; }; union cvmx_smix_rd_dat { uint64_t u64; struct cvmx_smix_rd_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t pending:1; uint64_t val:1; uint64_t dat:16; +#else + uint64_t dat:16; + uint64_t val:1; + uint64_t pending:1; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_smix_rd_dat_s cn30xx; struct cvmx_smix_rd_dat_s cn31xx; @@ -144,17 +317,29 @@ union cvmx_smix_rd_dat { struct cvmx_smix_rd_dat_s cn56xxp1; struct cvmx_smix_rd_dat_s cn58xx; struct cvmx_smix_rd_dat_s cn58xxp1; + struct cvmx_smix_rd_dat_s cn61xx; struct cvmx_smix_rd_dat_s cn63xx; struct cvmx_smix_rd_dat_s cn63xxp1; + struct cvmx_smix_rd_dat_s cn66xx; + struct cvmx_smix_rd_dat_s cn68xx; + struct cvmx_smix_rd_dat_s cn68xxp1; + struct cvmx_smix_rd_dat_s cnf71xx; }; union cvmx_smix_wr_dat { uint64_t u64; struct cvmx_smix_wr_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_18_63:46; uint64_t pending:1; uint64_t val:1; uint64_t dat:16; +#else + uint64_t dat:16; + uint64_t val:1; + uint64_t pending:1; + uint64_t reserved_18_63:46; +#endif } s; struct cvmx_smix_wr_dat_s cn30xx; struct cvmx_smix_wr_dat_s cn31xx; @@ -167,8 +352,13 @@ union cvmx_smix_wr_dat { struct cvmx_smix_wr_dat_s cn56xxp1; struct cvmx_smix_wr_dat_s cn58xx; struct cvmx_smix_wr_dat_s cn58xxp1; + struct cvmx_smix_wr_dat_s cn61xx; struct cvmx_smix_wr_dat_s cn63xx; struct cvmx_smix_wr_dat_s cn63xxp1; + struct cvmx_smix_wr_dat_s cn66xx; + struct cvmx_smix_wr_dat_s cn68xx; + struct cvmx_smix_wr_dat_s cn68xxp1; + struct cvmx_smix_wr_dat_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-spi.h b/arch/mips/include/asm/octeon/cvmx-spi.h index e814648953a..d5038cc4b47 100644 --- a/arch/mips/include/asm/octeon/cvmx-spi.h +++ b/arch/mips/include/asm/octeon/cvmx-spi.h @@ -32,7 +32,7 @@ #ifndef __CVMX_SPI_H__ #define __CVMX_SPI_H__ -#include "cvmx-gmxx-defs.h" +#include <asm/octeon/cvmx-gmxx-defs.h> /* CSR typedefs have been moved to cvmx-csr-*.h */ @@ -84,11 +84,11 @@ static inline int cvmx_spi_is_spi_interface(int interface) * Initialize and start the SPI interface. * * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. + * use as a SPI interface. * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). * @timeout: Timeout to wait for clock synchronization in seconds * @num_ports: Number of SPI ports to configure * @@ -102,11 +102,11 @@ extern int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, * with its corespondant system. * * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. + * use as a SPI interface. * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). * @timeout: Timeout to wait for clock synchronization in seconds * Returns Zero on success, negative of failure. */ @@ -154,7 +154,7 @@ static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed( /** * Get current SPI4 initialization callbacks * - * @callbacks: Pointer to the callbacks structure.to fill + * @callbacks: Pointer to the callbacks structure.to fill * * Returns Pointer to cvmx_spi_callbacks_t structure. */ @@ -171,11 +171,11 @@ extern void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks); * Callback to perform SPI4 reset * * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. + * use as a SPI interface. * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). * * Returns Zero on success, non-zero error code on failure (will cause * SPI initialization to abort) @@ -187,11 +187,11 @@ extern int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode); * detection * * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. + * use as a SPI interface. * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). * @num_ports: Number of ports to configure on SPI * * Returns Zero on success, non-zero error code on failure (will cause @@ -204,11 +204,11 @@ extern int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, * Callback to perform clock detection * * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. + * use as a SPI interface. * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). * @timeout: Timeout to wait for clock synchronization in seconds * * Returns Zero on success, non-zero error code on failure (will cause @@ -221,11 +221,11 @@ extern int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, * Callback to perform link training * * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. + * use as a SPI interface. * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). * @timeout: Timeout to wait for link to be trained (in seconds) * * Returns Zero on success, non-zero error code on failure (will cause @@ -238,11 +238,11 @@ extern int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, * Callback to perform calendar data synchronization * * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. + * use as a SPI interface. * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). * @timeout: Timeout to wait for calendar data in seconds * * Returns Zero on success, non-zero error code on failure (will cause @@ -255,11 +255,11 @@ extern int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, * Callback to handle interface up * * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. + * use as a SPI interface. * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). * * Returns Zero on success, non-zero error code on failure (will cause * SPI initialization to abort) diff --git a/arch/mips/include/asm/octeon/cvmx-spinlock.h b/arch/mips/include/asm/octeon/cvmx-spinlock.h index 2fbf0871df1..4f09cff8b8c 100644 --- a/arch/mips/include/asm/octeon/cvmx-spinlock.h +++ b/arch/mips/include/asm/octeon/cvmx-spinlock.h @@ -26,7 +26,7 @@ ***********************license end**************************************/ /** - * Implementation of spinlocks for Octeon CVMX. Although similar in + * Implementation of spinlocks for Octeon CVMX. Although similar in * function to Linux kernel spinlocks, they are not compatible. * Octeon CVMX spinlocks are only used to synchronize with the boot * monitor and other non-Linux programs running in the system. @@ -35,7 +35,7 @@ #ifndef __CVMX_SPINLOCK_H__ #define __CVMX_SPINLOCK_H__ -#include "cvmx-asm.h" +#include <asm/octeon/cvmx-asm.h> /* Spinlocks for Octeon */ @@ -50,8 +50,8 @@ typedef struct { } cvmx_spinlock_t; /* note - macros not expanded in inline ASM, so values hardcoded */ -#define CVMX_SPINLOCK_UNLOCKED_VAL 0 -#define CVMX_SPINLOCK_LOCKED_VAL 1 +#define CVMX_SPINLOCK_UNLOCKED_VAL 0 +#define CVMX_SPINLOCK_LOCKED_VAL 1 #define CVMX_SPINLOCK_UNLOCKED_INITIALIZER {CVMX_SPINLOCK_UNLOCKED_VAL} @@ -96,7 +96,7 @@ static inline void cvmx_spinlock_unlock(cvmx_spinlock_t *lock) * @lock: pointer to lock structure * * Returns 0: lock successfully taken - * 1: lock not taken, held by someone else + * 1: lock not taken, held by someone else * These return values match the Linux semantics. */ @@ -104,16 +104,16 @@ static inline unsigned int cvmx_spinlock_trylock(cvmx_spinlock_t *lock) { unsigned int tmp; - __asm__ __volatile__(".set noreorder \n" + __asm__ __volatile__(".set noreorder \n" "1: ll %[tmp], %[val] \n" /* if lock held, fail immediately */ - " bnez %[tmp], 2f \n" - " li %[tmp], 1 \n" - " sc %[tmp], %[val] \n" - " beqz %[tmp], 1b \n" - " li %[tmp], 0 \n" - "2: \n" - ".set reorder \n" : + " bnez %[tmp], 2f \n" + " li %[tmp], 1 \n" + " sc %[tmp], %[val] \n" + " beqz %[tmp], 1b \n" + " li %[tmp], 0 \n" + "2: \n" + ".set reorder \n" : [val] "+m"(lock->value), [tmp] "=&r"(tmp) : : "memory"); @@ -129,14 +129,14 @@ static inline void cvmx_spinlock_lock(cvmx_spinlock_t *lock) { unsigned int tmp; - __asm__ __volatile__(".set noreorder \n" + __asm__ __volatile__(".set noreorder \n" "1: ll %[tmp], %[val] \n" - " bnez %[tmp], 1b \n" - " li %[tmp], 1 \n" - " sc %[tmp], %[val] \n" - " beqz %[tmp], 1b \n" - " nop \n" - ".set reorder \n" : + " bnez %[tmp], 1b \n" + " li %[tmp], 1 \n" + " sc %[tmp], %[val] \n" + " beqz %[tmp], 1b \n" + " nop \n" + ".set reorder \n" : [val] "+m"(lock->value), [tmp] "=&r"(tmp) : : "memory"); @@ -163,17 +163,17 @@ static inline void cvmx_spinlock_bit_lock(uint32_t *word) unsigned int tmp; unsigned int sav; - __asm__ __volatile__(".set noreorder \n" - ".set noat \n" + __asm__ __volatile__(".set noreorder \n" + ".set noat \n" "1: ll %[tmp], %[val] \n" - " bbit1 %[tmp], 31, 1b \n" - " li $at, 1 \n" - " ins %[tmp], $at, 31, 1 \n" - " sc %[tmp], %[val] \n" - " beqz %[tmp], 1b \n" - " nop \n" - ".set at \n" - ".set reorder \n" : + " bbit1 %[tmp], 31, 1b \n" + " li $at, 1 \n" + " ins %[tmp], $at, 31, 1 \n" + " sc %[tmp], %[val] \n" + " beqz %[tmp], 1b \n" + " nop \n" + ".set at \n" + ".set reorder \n" : [val] "+m"(*word), [tmp] "=&r"(tmp), [sav] "=&r"(sav) : : "memory"); @@ -187,7 +187,7 @@ static inline void cvmx_spinlock_bit_lock(uint32_t *word) * * @word: word to lock bit 31 of * Returns 0: lock successfully taken - * 1: lock not taken, held by someone else + * 1: lock not taken, held by someone else * These return values match the Linux semantics. */ static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word) @@ -198,15 +198,15 @@ static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word) ".set noat\n" "1: ll %[tmp], %[val] \n" /* if lock held, fail immediately */ - " bbit1 %[tmp], 31, 2f \n" - " li $at, 1 \n" - " ins %[tmp], $at, 31, 1 \n" - " sc %[tmp], %[val] \n" - " beqz %[tmp], 1b \n" - " li %[tmp], 0 \n" - "2: \n" - ".set at \n" - ".set reorder \n" : + " bbit1 %[tmp], 31, 2f \n" + " li $at, 1 \n" + " ins %[tmp], $at, 31, 1 \n" + " sc %[tmp], %[val] \n" + " beqz %[tmp], 1b \n" + " li %[tmp], 0 \n" + "2: \n" + ".set at \n" + ".set reorder \n" : [val] "+m"(*word), [tmp] "=&r"(tmp) : : "memory"); diff --git a/arch/mips/include/asm/octeon/cvmx-spxx-defs.h b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h index b16940e32c8..c7d601d9446 100644 --- a/arch/mips/include/asm/octeon/cvmx-spxx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,44 +28,33 @@ #ifndef __CVMX_SPXX_DEFS_H__ #define __CVMX_SPXX_DEFS_H__ -#define CVMX_SPXX_BCKPRS_CNT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000340ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_BIST_STAT(block_id) \ - CVMX_ADD_IO_SEG(0x00011800900007F8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_CLK_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000348ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_CLK_STAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000350ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000368ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000370ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_DRV_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000358ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_ERR_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000320ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_INT_DAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000318ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_INT_MSK(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000308ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_INT_REG(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000300ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_INT_SYNC(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000310ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_TPA_ACC(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000338ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_TPA_MAX(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000330ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_TPA_SEL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000328ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_TRN4_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000360ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull) union cvmx_spxx_bckprs_cnt { uint64_t u64; struct cvmx_spxx_bckprs_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_spxx_bckprs_cnt_s cn38xx; struct cvmx_spxx_bckprs_cnt_s cn38xxp2; @@ -76,10 +65,17 @@ union cvmx_spxx_bckprs_cnt { union cvmx_spxx_bist_stat { uint64_t u64; struct cvmx_spxx_bist_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t stat2:1; uint64_t stat1:1; uint64_t stat0:1; +#else + uint64_t stat0:1; + uint64_t stat1:1; + uint64_t stat2:1; + uint64_t reserved_3_63:61; +#endif } s; struct cvmx_spxx_bist_stat_s cn38xx; struct cvmx_spxx_bist_stat_s cn38xxp2; @@ -90,6 +86,7 @@ union cvmx_spxx_bist_stat { union cvmx_spxx_clk_ctl { uint64_t u64; struct cvmx_spxx_clk_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t seetrn:1; uint64_t reserved_12_15:4; @@ -101,6 +98,19 @@ union cvmx_spxx_clk_ctl { uint64_t drptrn:1; uint64_t rcvtrn:1; uint64_t srxdlck:1; +#else + uint64_t srxdlck:1; + uint64_t rcvtrn:1; + uint64_t drptrn:1; + uint64_t sndtrn:1; + uint64_t statrcv:1; + uint64_t statdrv:1; + uint64_t runbist:1; + uint64_t clkdly:5; + uint64_t reserved_12_15:4; + uint64_t seetrn:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_spxx_clk_ctl_s cn38xx; struct cvmx_spxx_clk_ctl_s cn38xxp2; @@ -111,6 +121,7 @@ union cvmx_spxx_clk_ctl { union cvmx_spxx_clk_stat { uint64_t u64; struct cvmx_spxx_clk_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_11_63:53; uint64_t stxcal:1; uint64_t reserved_9_9:1; @@ -120,6 +131,17 @@ union cvmx_spxx_clk_stat { uint64_t d4clk1:1; uint64_t d4clk0:1; uint64_t reserved_0_3:4; +#else + uint64_t reserved_0_3:4; + uint64_t d4clk0:1; + uint64_t d4clk1:1; + uint64_t s4clk0:1; + uint64_t s4clk1:1; + uint64_t srxtrn:1; + uint64_t reserved_9_9:1; + uint64_t stxcal:1; + uint64_t reserved_11_63:53; +#endif } s; struct cvmx_spxx_clk_stat_s cn38xx; struct cvmx_spxx_clk_stat_s cn38xxp2; @@ -130,6 +152,7 @@ union cvmx_spxx_clk_stat { union cvmx_spxx_dbg_deskew_ctl { uint64_t u64; struct cvmx_spxx_dbg_deskew_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_30_63:34; uint64_t fallnop:1; uint64_t fall8:1; @@ -146,6 +169,24 @@ union cvmx_spxx_dbg_deskew_ctl { uint64_t offdly:6; uint64_t dllfrc:1; uint64_t dlldis:1; +#else + uint64_t dlldis:1; + uint64_t dllfrc:1; + uint64_t offdly:6; + uint64_t bitsel:5; + uint64_t offset:5; + uint64_t mux:1; + uint64_t inc:1; + uint64_t dec:1; + uint64_t clrdly:1; + uint64_t reserved_22_23:2; + uint64_t sstep:1; + uint64_t sstep_go:1; + uint64_t reserved_26_27:2; + uint64_t fall8:1; + uint64_t fallnop:1; + uint64_t reserved_30_63:34; +#endif } s; struct cvmx_spxx_dbg_deskew_ctl_s cn38xx; struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2; @@ -156,11 +197,19 @@ union cvmx_spxx_dbg_deskew_ctl { union cvmx_spxx_dbg_deskew_state { uint64_t u64; struct cvmx_spxx_dbg_deskew_state_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t testres:1; uint64_t unxterm:1; uint64_t muxsel:2; uint64_t offset:5; +#else + uint64_t offset:5; + uint64_t muxsel:2; + uint64_t unxterm:1; + uint64_t testres:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_spxx_dbg_deskew_state_s cn38xx; struct cvmx_spxx_dbg_deskew_state_s cn38xxp2; @@ -171,21 +220,40 @@ union cvmx_spxx_dbg_deskew_state { union cvmx_spxx_drv_ctl { uint64_t u64; struct cvmx_spxx_drv_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_0_63:64; +#else + uint64_t reserved_0_63:64; +#endif } s; struct cvmx_spxx_drv_ctl_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t stx4ncmp:4; uint64_t stx4pcmp:4; uint64_t srx4cmp:8; +#else + uint64_t srx4cmp:8; + uint64_t stx4pcmp:4; + uint64_t stx4ncmp:4; + uint64_t reserved_16_63:48; +#endif } cn38xx; struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2; struct cvmx_spxx_drv_ctl_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_24_63:40; uint64_t stx4ncmp:4; uint64_t stx4pcmp:4; uint64_t reserved_10_15:6; uint64_t srx4cmp:10; +#else + uint64_t srx4cmp:10; + uint64_t reserved_10_15:6; + uint64_t stx4pcmp:4; + uint64_t stx4ncmp:4; + uint64_t reserved_24_63:40; +#endif } cn58xx; struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1; }; @@ -193,12 +261,21 @@ union cvmx_spxx_drv_ctl { union cvmx_spxx_err_ctl { uint64_t u64; struct cvmx_spxx_err_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t prtnxa:1; uint64_t dipcls:1; uint64_t dippay:1; uint64_t reserved_4_5:2; uint64_t errcnt:4; +#else + uint64_t errcnt:4; + uint64_t reserved_4_5:2; + uint64_t dippay:1; + uint64_t dipcls:1; + uint64_t prtnxa:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_spxx_err_ctl_s cn38xx; struct cvmx_spxx_err_ctl_s cn38xxp2; @@ -209,12 +286,21 @@ union cvmx_spxx_err_ctl { union cvmx_spxx_int_dat { uint64_t u64; struct cvmx_spxx_int_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t mul:1; uint64_t reserved_14_30:17; uint64_t calbnk:2; uint64_t rsvop:4; uint64_t prt:8; +#else + uint64_t prt:8; + uint64_t rsvop:4; + uint64_t calbnk:2; + uint64_t reserved_14_30:17; + uint64_t mul:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_spxx_int_dat_s cn38xx; struct cvmx_spxx_int_dat_s cn38xxp2; @@ -225,6 +311,7 @@ union cvmx_spxx_int_dat { union cvmx_spxx_int_msk { uint64_t u64; struct cvmx_spxx_int_msk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t calerr:1; uint64_t syncerr:1; @@ -237,6 +324,20 @@ union cvmx_spxx_int_msk { uint64_t reserved_2_3:2; uint64_t abnorm:1; uint64_t prtnxa:1; +#else + uint64_t prtnxa:1; + uint64_t abnorm:1; + uint64_t reserved_2_3:2; + uint64_t spiovr:1; + uint64_t clserr:1; + uint64_t drwnng:1; + uint64_t rsverr:1; + uint64_t tpaovr:1; + uint64_t diperr:1; + uint64_t syncerr:1; + uint64_t calerr:1; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_spxx_int_msk_s cn38xx; struct cvmx_spxx_int_msk_s cn38xxp2; @@ -247,6 +348,7 @@ union cvmx_spxx_int_msk { union cvmx_spxx_int_reg { uint64_t u64; struct cvmx_spxx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t spf:1; uint64_t reserved_12_30:19; @@ -261,6 +363,22 @@ union cvmx_spxx_int_reg { uint64_t reserved_2_3:2; uint64_t abnorm:1; uint64_t prtnxa:1; +#else + uint64_t prtnxa:1; + uint64_t abnorm:1; + uint64_t reserved_2_3:2; + uint64_t spiovr:1; + uint64_t clserr:1; + uint64_t drwnng:1; + uint64_t rsverr:1; + uint64_t tpaovr:1; + uint64_t diperr:1; + uint64_t syncerr:1; + uint64_t calerr:1; + uint64_t reserved_12_30:19; + uint64_t spf:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_spxx_int_reg_s cn38xx; struct cvmx_spxx_int_reg_s cn38xxp2; @@ -271,6 +389,7 @@ union cvmx_spxx_int_reg { union cvmx_spxx_int_sync { uint64_t u64; struct cvmx_spxx_int_sync_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_12_63:52; uint64_t calerr:1; uint64_t syncerr:1; @@ -283,6 +402,20 @@ union cvmx_spxx_int_sync { uint64_t reserved_2_3:2; uint64_t abnorm:1; uint64_t prtnxa:1; +#else + uint64_t prtnxa:1; + uint64_t abnorm:1; + uint64_t reserved_2_3:2; + uint64_t spiovr:1; + uint64_t clserr:1; + uint64_t drwnng:1; + uint64_t rsverr:1; + uint64_t tpaovr:1; + uint64_t diperr:1; + uint64_t syncerr:1; + uint64_t calerr:1; + uint64_t reserved_12_63:52; +#endif } s; struct cvmx_spxx_int_sync_s cn38xx; struct cvmx_spxx_int_sync_s cn38xxp2; @@ -293,8 +426,13 @@ union cvmx_spxx_int_sync { union cvmx_spxx_tpa_acc { uint64_t u64; struct cvmx_spxx_tpa_acc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_spxx_tpa_acc_s cn38xx; struct cvmx_spxx_tpa_acc_s cn38xxp2; @@ -305,8 +443,13 @@ union cvmx_spxx_tpa_acc { union cvmx_spxx_tpa_max { uint64_t u64; struct cvmx_spxx_tpa_max_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t max:32; +#else + uint64_t max:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_spxx_tpa_max_s cn38xx; struct cvmx_spxx_tpa_max_s cn38xxp2; @@ -317,8 +460,13 @@ union cvmx_spxx_tpa_max { union cvmx_spxx_tpa_sel { uint64_t u64; struct cvmx_spxx_tpa_sel_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t prtsel:4; +#else + uint64_t prtsel:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_spxx_tpa_sel_s cn38xx; struct cvmx_spxx_tpa_sel_s cn38xxp2; @@ -329,6 +477,7 @@ union cvmx_spxx_tpa_sel { union cvmx_spxx_trn4_ctl { uint64_t u64; struct cvmx_spxx_trn4_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_13_63:51; uint64_t trntest:1; uint64_t jitter:3; @@ -337,6 +486,16 @@ union cvmx_spxx_trn4_ctl { uint64_t maxdist:5; uint64_t macro_en:1; uint64_t mux_en:1; +#else + uint64_t mux_en:1; + uint64_t macro_en:1; + uint64_t maxdist:5; + uint64_t set_boot:1; + uint64_t clr_boot:1; + uint64_t jitter:3; + uint64_t trntest:1; + uint64_t reserved_13_63:51; +#endif } s; struct cvmx_spxx_trn4_ctl_s cn38xx; struct cvmx_spxx_trn4_ctl_s cn38xxp2; diff --git a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h index 7be7e9ed746..5140f2d2ad1 100644 --- a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2011 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -79,6 +79,7 @@ union cvmx_sriox_acc_ctrl { uint64_t u64; struct cvmx_sriox_acc_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_7_63:57; uint64_t deny_adr2:1; uint64_t deny_adr1:1; @@ -87,12 +88,29 @@ union cvmx_sriox_acc_ctrl { uint64_t deny_bar2:1; uint64_t deny_bar1:1; uint64_t deny_bar0:1; +#else + uint64_t deny_bar0:1; + uint64_t deny_bar1:1; + uint64_t deny_bar2:1; + uint64_t reserved_3_3:1; + uint64_t deny_adr0:1; + uint64_t deny_adr1:1; + uint64_t deny_adr2:1; + uint64_t reserved_7_63:57; +#endif } s; struct cvmx_sriox_acc_ctrl_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_3_63:61; uint64_t deny_bar2:1; uint64_t deny_bar1:1; uint64_t deny_bar0:1; +#else + uint64_t deny_bar0:1; + uint64_t deny_bar1:1; + uint64_t deny_bar2:1; + uint64_t reserved_3_63:61; +#endif } cn63xx; struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1; struct cvmx_sriox_acc_ctrl_s cn66xx; @@ -101,9 +119,15 @@ union cvmx_sriox_acc_ctrl { union cvmx_sriox_asmbly_id { uint64_t u64; struct cvmx_sriox_asmbly_id_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t assy_id:16; uint64_t assy_ven:16; +#else + uint64_t assy_ven:16; + uint64_t assy_id:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_asmbly_id_s cn63xx; struct cvmx_sriox_asmbly_id_s cn63xxp1; @@ -113,9 +137,15 @@ union cvmx_sriox_asmbly_id { union cvmx_sriox_asmbly_info { uint64_t u64; struct cvmx_sriox_asmbly_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t assy_rev:16; uint64_t reserved_0_15:16; +#else + uint64_t reserved_0_15:16; + uint64_t assy_rev:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_asmbly_info_s cn63xx; struct cvmx_sriox_asmbly_info_s cn63xxp1; @@ -125,11 +155,19 @@ union cvmx_sriox_asmbly_info { union cvmx_sriox_bell_resp_ctrl { uint64_t u64; struct cvmx_sriox_bell_resp_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t rp1_sid:1; uint64_t rp0_sid:2; uint64_t rp1_pid:1; uint64_t rp0_pid:2; +#else + uint64_t rp0_pid:2; + uint64_t rp1_pid:1; + uint64_t rp0_sid:2; + uint64_t rp1_sid:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_sriox_bell_resp_ctrl_s cn63xx; struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1; @@ -139,6 +177,7 @@ union cvmx_sriox_bell_resp_ctrl { union cvmx_sriox_bist_status { uint64_t u64; struct cvmx_sriox_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_45_63:19; uint64_t lram:1; uint64_t mram:2; @@ -159,8 +198,31 @@ union cvmx_sriox_bist_status { uint64_t rxbuf:2; uint64_t imsg:5; uint64_t omsg:7; +#else + uint64_t omsg:7; + uint64_t imsg:5; + uint64_t rxbuf:2; + uint64_t txbuf:2; + uint64_t ospf:1; + uint64_t ispf:1; + uint64_t oarb:2; + uint64_t rxbuf2:2; + uint64_t oarb2:2; + uint64_t optrs:4; + uint64_t obulk:4; + uint64_t rtn:2; + uint64_t ofree:1; + uint64_t itag:1; + uint64_t otag:2; + uint64_t bell:2; + uint64_t cram:2; + uint64_t mram:2; + uint64_t lram:1; + uint64_t reserved_45_63:19; +#endif } s; struct cvmx_sriox_bist_status_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t mram:2; uint64_t cram:2; @@ -180,8 +242,30 @@ union cvmx_sriox_bist_status { uint64_t rxbuf:2; uint64_t imsg:5; uint64_t omsg:7; +#else + uint64_t omsg:7; + uint64_t imsg:5; + uint64_t rxbuf:2; + uint64_t txbuf:2; + uint64_t ospf:1; + uint64_t ispf:1; + uint64_t oarb:2; + uint64_t rxbuf2:2; + uint64_t oarb2:2; + uint64_t optrs:4; + uint64_t obulk:4; + uint64_t rtn:2; + uint64_t ofree:1; + uint64_t itag:1; + uint64_t otag:2; + uint64_t bell:2; + uint64_t cram:2; + uint64_t mram:2; + uint64_t reserved_44_63:20; +#endif } cn63xx; struct cvmx_sriox_bist_status_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_44_63:20; uint64_t mram:2; uint64_t cram:2; @@ -200,6 +284,26 @@ union cvmx_sriox_bist_status { uint64_t rxbuf:2; uint64_t imsg:5; uint64_t omsg:7; +#else + uint64_t omsg:7; + uint64_t imsg:5; + uint64_t rxbuf:2; + uint64_t txbuf:2; + uint64_t ospf:1; + uint64_t ispf:1; + uint64_t oarb:2; + uint64_t reserved_20_23:4; + uint64_t optrs:4; + uint64_t obulk:4; + uint64_t rtn:2; + uint64_t ofree:1; + uint64_t itag:1; + uint64_t otag:2; + uint64_t bell:2; + uint64_t cram:2; + uint64_t mram:2; + uint64_t reserved_44_63:20; +#endif } cn63xxp1; struct cvmx_sriox_bist_status_s cn66xx; }; @@ -207,6 +311,7 @@ union cvmx_sriox_bist_status { union cvmx_sriox_imsg_ctrl { uint64_t u64; struct cvmx_sriox_imsg_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t to_mode:1; uint64_t reserved_30_30:1; @@ -221,6 +326,22 @@ union cvmx_sriox_imsg_ctrl { uint64_t lttr:4; uint64_t prio:4; uint64_t mbox:4; +#else + uint64_t mbox:4; + uint64_t prio:4; + uint64_t lttr:4; + uint64_t prt_sel:3; + uint64_t reserved_15_15:1; + uint64_t rp0_pid:2; + uint64_t rp1_pid:1; + uint64_t rp0_sid:2; + uint64_t rp1_sid:1; + uint64_t reserved_22_23:2; + uint64_t rsp_thr:6; + uint64_t reserved_30_30:1; + uint64_t to_mode:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_imsg_ctrl_s cn63xx; struct cvmx_sriox_imsg_ctrl_s cn63xxp1; @@ -230,6 +351,7 @@ union cvmx_sriox_imsg_ctrl { union cvmx_sriox_imsg_inst_hdrx { uint64_t u64; struct cvmx_sriox_imsg_inst_hdrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t r:1; uint64_t reserved_58_62:5; uint64_t pm:2; @@ -244,6 +366,22 @@ union cvmx_sriox_imsg_inst_hdrx { uint64_t rs:1; uint64_t tt:2; uint64_t tag:32; +#else + uint64_t tag:32; + uint64_t tt:2; + uint64_t rs:1; + uint64_t reserved_35_41:7; + uint64_t ntag:1; + uint64_t ntt:1; + uint64_t ngrp:1; + uint64_t nqos:1; + uint64_t reserved_46_47:2; + uint64_t sl:7; + uint64_t reserved_55_55:1; + uint64_t pm:2; + uint64_t reserved_58_62:5; + uint64_t r:1; +#endif } s; struct cvmx_sriox_imsg_inst_hdrx_s cn63xx; struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1; @@ -253,6 +391,7 @@ union cvmx_sriox_imsg_inst_hdrx { union cvmx_sriox_imsg_qos_grpx { uint64_t u64; struct cvmx_sriox_imsg_qos_grpx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_63_63:1; uint64_t qos7:3; uint64_t grp7:4; @@ -277,6 +416,32 @@ union cvmx_sriox_imsg_qos_grpx { uint64_t reserved_7_7:1; uint64_t qos0:3; uint64_t grp0:4; +#else + uint64_t grp0:4; + uint64_t qos0:3; + uint64_t reserved_7_7:1; + uint64_t grp1:4; + uint64_t qos1:3; + uint64_t reserved_15_15:1; + uint64_t grp2:4; + uint64_t qos2:3; + uint64_t reserved_23_23:1; + uint64_t grp3:4; + uint64_t qos3:3; + uint64_t reserved_31_31:1; + uint64_t grp4:4; + uint64_t qos4:3; + uint64_t reserved_39_39:1; + uint64_t grp5:4; + uint64_t qos5:3; + uint64_t reserved_47_47:1; + uint64_t grp6:4; + uint64_t qos6:3; + uint64_t reserved_55_55:1; + uint64_t grp7:4; + uint64_t qos7:3; + uint64_t reserved_63_63:1; +#endif } s; struct cvmx_sriox_imsg_qos_grpx_s cn63xx; struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1; @@ -286,6 +451,7 @@ union cvmx_sriox_imsg_qos_grpx { union cvmx_sriox_imsg_statusx { uint64_t u64; struct cvmx_sriox_imsg_statusx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t val1:1; uint64_t err1:1; uint64_t toe1:1; @@ -310,6 +476,32 @@ union cvmx_sriox_imsg_statusx { uint64_t mbox0:2; uint64_t lttr0:2; uint64_t sid0:16; +#else + uint64_t sid0:16; + uint64_t lttr0:2; + uint64_t mbox0:2; + uint64_t seg0:4; + uint64_t dis0:1; + uint64_t tt0:1; + uint64_t reserved_26_26:1; + uint64_t prt0:1; + uint64_t toc0:1; + uint64_t toe0:1; + uint64_t err0:1; + uint64_t val0:1; + uint64_t sid1:16; + uint64_t lttr1:2; + uint64_t mbox1:2; + uint64_t seg1:4; + uint64_t dis1:1; + uint64_t tt1:1; + uint64_t reserved_58_58:1; + uint64_t prt1:1; + uint64_t toc1:1; + uint64_t toe1:1; + uint64_t err1:1; + uint64_t val1:1; +#endif } s; struct cvmx_sriox_imsg_statusx_s cn63xx; struct cvmx_sriox_imsg_statusx_s cn63xxp1; @@ -319,6 +511,7 @@ union cvmx_sriox_imsg_statusx { union cvmx_sriox_imsg_vport_thr { uint64_t u64; struct cvmx_sriox_imsg_vport_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_54_63:10; uint64_t max_tot:6; uint64_t reserved_46_47:2; @@ -332,6 +525,21 @@ union cvmx_sriox_imsg_vport_thr { uint64_t max_p1:6; uint64_t reserved_6_7:2; uint64_t max_p0:6; +#else + uint64_t max_p0:6; + uint64_t reserved_6_7:2; + uint64_t max_p1:6; + uint64_t reserved_14_15:2; + uint64_t buf_thr:4; + uint64_t reserved_20_30:11; + uint64_t sp_vport:1; + uint64_t max_s0:6; + uint64_t reserved_38_39:2; + uint64_t max_s1:6; + uint64_t reserved_46_47:2; + uint64_t max_tot:6; + uint64_t reserved_54_63:10; +#endif } s; struct cvmx_sriox_imsg_vport_thr_s cn63xx; struct cvmx_sriox_imsg_vport_thr_s cn63xxp1; @@ -341,11 +549,19 @@ union cvmx_sriox_imsg_vport_thr { union cvmx_sriox_imsg_vport_thr2 { uint64_t u64; struct cvmx_sriox_imsg_vport_thr2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_46_63:18; uint64_t max_s3:6; uint64_t reserved_38_39:2; uint64_t max_s2:6; uint64_t reserved_0_31:32; +#else + uint64_t reserved_0_31:32; + uint64_t max_s2:6; + uint64_t reserved_38_39:2; + uint64_t max_s3:6; + uint64_t reserved_46_63:18; +#endif } s; struct cvmx_sriox_imsg_vport_thr2_s cn66xx; }; @@ -353,8 +569,13 @@ union cvmx_sriox_imsg_vport_thr2 { union cvmx_sriox_int2_enable { uint64_t u64; struct cvmx_sriox_int2_enable_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t pko_rst:1; +#else + uint64_t pko_rst:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_sriox_int2_enable_s cn63xx; struct cvmx_sriox_int2_enable_s cn66xx; @@ -363,10 +584,17 @@ union cvmx_sriox_int2_enable { union cvmx_sriox_int2_reg { uint64_t u64; struct cvmx_sriox_int2_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t int_sum:1; uint64_t reserved_1_30:30; uint64_t pko_rst:1; +#else + uint64_t pko_rst:1; + uint64_t reserved_1_30:30; + uint64_t int_sum:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_int2_reg_s cn63xx; struct cvmx_sriox_int2_reg_s cn66xx; @@ -375,6 +603,7 @@ union cvmx_sriox_int2_reg { union cvmx_sriox_int_enable { uint64_t u64; struct cvmx_sriox_int_enable_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_27_63:37; uint64_t zero_pkt:1; uint64_t ttl_tout:1; @@ -403,9 +632,40 @@ union cvmx_sriox_int_enable { uint64_t rxbell:1; uint64_t bell_err:1; uint64_t txbell:1; +#else + uint64_t txbell:1; + uint64_t bell_err:1; + uint64_t rxbell:1; + uint64_t maint_op:1; + uint64_t bar_err:1; + uint64_t deny_wr:1; + uint64_t sli_err:1; + uint64_t wr_done:1; + uint64_t mce_tx:1; + uint64_t mce_rx:1; + uint64_t soft_tx:1; + uint64_t soft_rx:1; + uint64_t log_erb:1; + uint64_t phy_erb:1; + uint64_t link_dwn:1; + uint64_t link_up:1; + uint64_t omsg0:1; + uint64_t omsg1:1; + uint64_t omsg_err:1; + uint64_t pko_err:1; + uint64_t rtry_err:1; + uint64_t f_error:1; + uint64_t mac_buf:1; + uint64_t degrade:1; + uint64_t fail:1; + uint64_t ttl_tout:1; + uint64_t zero_pkt:1; + uint64_t reserved_27_63:37; +#endif } s; struct cvmx_sriox_int_enable_s cn63xx; struct cvmx_sriox_int_enable_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t f_error:1; uint64_t rtry_err:1; @@ -429,6 +689,31 @@ union cvmx_sriox_int_enable { uint64_t rxbell:1; uint64_t bell_err:1; uint64_t txbell:1; +#else + uint64_t txbell:1; + uint64_t bell_err:1; + uint64_t rxbell:1; + uint64_t maint_op:1; + uint64_t bar_err:1; + uint64_t deny_wr:1; + uint64_t sli_err:1; + uint64_t wr_done:1; + uint64_t mce_tx:1; + uint64_t mce_rx:1; + uint64_t soft_tx:1; + uint64_t soft_rx:1; + uint64_t log_erb:1; + uint64_t phy_erb:1; + uint64_t link_dwn:1; + uint64_t link_up:1; + uint64_t omsg0:1; + uint64_t omsg1:1; + uint64_t omsg_err:1; + uint64_t pko_err:1; + uint64_t rtry_err:1; + uint64_t f_error:1; + uint64_t reserved_22_63:42; +#endif } cn63xxp1; struct cvmx_sriox_int_enable_s cn66xx; }; @@ -436,6 +721,7 @@ union cvmx_sriox_int_enable { union cvmx_sriox_int_info0 { uint64_t u64; struct cvmx_sriox_int_info0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t cmd:4; uint64_t type:4; uint64_t tag:8; @@ -445,6 +731,17 @@ union cvmx_sriox_int_info0 { uint64_t reserved_16_28:13; uint64_t be0:8; uint64_t be1:8; +#else + uint64_t be1:8; + uint64_t be0:8; + uint64_t reserved_16_28:13; + uint64_t status:3; + uint64_t length:10; + uint64_t reserved_42_47:6; + uint64_t tag:8; + uint64_t type:4; + uint64_t cmd:4; +#endif } s; struct cvmx_sriox_int_info0_s cn63xx; struct cvmx_sriox_int_info0_s cn63xxp1; @@ -454,7 +751,11 @@ union cvmx_sriox_int_info0 { union cvmx_sriox_int_info1 { uint64_t u64; struct cvmx_sriox_int_info1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t info1:64; +#else + uint64_t info1:64; +#endif } s; struct cvmx_sriox_int_info1_s cn63xx; struct cvmx_sriox_int_info1_s cn63xxp1; @@ -464,6 +765,7 @@ union cvmx_sriox_int_info1 { union cvmx_sriox_int_info2 { uint64_t u64; struct cvmx_sriox_int_info2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t prio:2; uint64_t tt:1; uint64_t sis:1; @@ -475,6 +777,19 @@ union cvmx_sriox_int_info2 { uint64_t rsrvd:30; uint64_t lns:1; uint64_t intr:1; +#else + uint64_t intr:1; + uint64_t lns:1; + uint64_t rsrvd:30; + uint64_t letter:2; + uint64_t mbox:2; + uint64_t xmbox:4; + uint64_t did:16; + uint64_t ssize:4; + uint64_t sis:1; + uint64_t tt:1; + uint64_t prio:2; +#endif } s; struct cvmx_sriox_int_info2_s cn63xx; struct cvmx_sriox_int_info2_s cn63xxp1; @@ -484,11 +799,19 @@ union cvmx_sriox_int_info2 { union cvmx_sriox_int_info3 { uint64_t u64; struct cvmx_sriox_int_info3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t prio:2; uint64_t tt:2; uint64_t type:4; uint64_t other:48; uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t other:48; + uint64_t type:4; + uint64_t tt:2; + uint64_t prio:2; +#endif } s; struct cvmx_sriox_int_info3_s cn63xx; struct cvmx_sriox_int_info3_s cn63xxp1; @@ -498,6 +821,7 @@ union cvmx_sriox_int_info3 { union cvmx_sriox_int_reg { uint64_t u64; struct cvmx_sriox_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t int2_sum:1; uint64_t reserved_27_30:4; @@ -528,9 +852,42 @@ union cvmx_sriox_int_reg { uint64_t rxbell:1; uint64_t bell_err:1; uint64_t txbell:1; +#else + uint64_t txbell:1; + uint64_t bell_err:1; + uint64_t rxbell:1; + uint64_t maint_op:1; + uint64_t bar_err:1; + uint64_t deny_wr:1; + uint64_t sli_err:1; + uint64_t wr_done:1; + uint64_t mce_tx:1; + uint64_t mce_rx:1; + uint64_t soft_tx:1; + uint64_t soft_rx:1; + uint64_t log_erb:1; + uint64_t phy_erb:1; + uint64_t link_dwn:1; + uint64_t link_up:1; + uint64_t omsg0:1; + uint64_t omsg1:1; + uint64_t omsg_err:1; + uint64_t pko_err:1; + uint64_t rtry_err:1; + uint64_t f_error:1; + uint64_t mac_buf:1; + uint64_t degrad:1; + uint64_t fail:1; + uint64_t ttl_tout:1; + uint64_t zero_pkt:1; + uint64_t reserved_27_30:4; + uint64_t int2_sum:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_int_reg_s cn63xx; struct cvmx_sriox_int_reg_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_22_63:42; uint64_t f_error:1; uint64_t rtry_err:1; @@ -554,6 +911,31 @@ union cvmx_sriox_int_reg { uint64_t rxbell:1; uint64_t bell_err:1; uint64_t txbell:1; +#else + uint64_t txbell:1; + uint64_t bell_err:1; + uint64_t rxbell:1; + uint64_t maint_op:1; + uint64_t bar_err:1; + uint64_t deny_wr:1; + uint64_t sli_err:1; + uint64_t wr_done:1; + uint64_t mce_tx:1; + uint64_t mce_rx:1; + uint64_t soft_tx:1; + uint64_t soft_rx:1; + uint64_t log_erb:1; + uint64_t phy_erb:1; + uint64_t link_dwn:1; + uint64_t link_up:1; + uint64_t omsg0:1; + uint64_t omsg1:1; + uint64_t omsg_err:1; + uint64_t pko_err:1; + uint64_t rtry_err:1; + uint64_t f_error:1; + uint64_t reserved_22_63:42; +#endif } cn63xxp1; struct cvmx_sriox_int_reg_s cn66xx; }; @@ -561,6 +943,7 @@ union cvmx_sriox_int_reg { union cvmx_sriox_ip_feature { uint64_t u64; struct cvmx_sriox_ip_feature_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t ops:32; uint64_t reserved_15_31:17; uint64_t no_vmin:1; @@ -571,8 +954,21 @@ union cvmx_sriox_ip_feature { uint64_t pt_width:2; uint64_t tx_pol:4; uint64_t rx_pol:4; +#else + uint64_t rx_pol:4; + uint64_t tx_pol:4; + uint64_t pt_width:2; + uint64_t tx_flow:1; + uint64_t reserved_11_11:1; + uint64_t a50:1; + uint64_t a66:1; + uint64_t no_vmin:1; + uint64_t reserved_15_31:17; + uint64_t ops:32; +#endif } s; struct cvmx_sriox_ip_feature_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t ops:32; uint64_t reserved_14_31:18; uint64_t a66:1; @@ -582,6 +978,17 @@ union cvmx_sriox_ip_feature { uint64_t pt_width:2; uint64_t tx_pol:4; uint64_t rx_pol:4; +#else + uint64_t rx_pol:4; + uint64_t tx_pol:4; + uint64_t pt_width:2; + uint64_t tx_flow:1; + uint64_t reserved_11_11:1; + uint64_t a50:1; + uint64_t a66:1; + uint64_t reserved_14_31:18; + uint64_t ops:32; +#endif } cn63xx; struct cvmx_sriox_ip_feature_cn63xx cn63xxp1; struct cvmx_sriox_ip_feature_s cn66xx; @@ -590,6 +997,7 @@ union cvmx_sriox_ip_feature { union cvmx_sriox_mac_buffers { uint64_t u64; struct cvmx_sriox_mac_buffers_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_56_63:8; uint64_t tx_enb:8; uint64_t reserved_44_47:4; @@ -600,6 +1008,18 @@ union cvmx_sriox_mac_buffers { uint64_t reserved_12_15:4; uint64_t rx_inuse:4; uint64_t rx_stat:8; +#else + uint64_t rx_stat:8; + uint64_t rx_inuse:4; + uint64_t reserved_12_15:4; + uint64_t rx_enb:8; + uint64_t reserved_24_31:8; + uint64_t tx_stat:8; + uint64_t tx_inuse:4; + uint64_t reserved_44_47:4; + uint64_t tx_enb:8; + uint64_t reserved_56_63:8; +#endif } s; struct cvmx_sriox_mac_buffers_s cn63xx; struct cvmx_sriox_mac_buffers_s cn66xx; @@ -608,12 +1028,21 @@ union cvmx_sriox_mac_buffers { union cvmx_sriox_maint_op { uint64_t u64; struct cvmx_sriox_maint_op_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t wr_data:32; uint64_t reserved_27_31:5; uint64_t fail:1; uint64_t pending:1; uint64_t op:1; uint64_t addr:24; +#else + uint64_t addr:24; + uint64_t op:1; + uint64_t pending:1; + uint64_t fail:1; + uint64_t reserved_27_31:5; + uint64_t wr_data:32; +#endif } s; struct cvmx_sriox_maint_op_s cn63xx; struct cvmx_sriox_maint_op_s cn63xxp1; @@ -623,9 +1052,15 @@ union cvmx_sriox_maint_op { union cvmx_sriox_maint_rd_data { uint64_t u64; struct cvmx_sriox_maint_rd_data_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_33_63:31; uint64_t valid:1; uint64_t rd_data:32; +#else + uint64_t rd_data:32; + uint64_t valid:1; + uint64_t reserved_33_63:31; +#endif } s; struct cvmx_sriox_maint_rd_data_s cn63xx; struct cvmx_sriox_maint_rd_data_s cn63xxp1; @@ -635,8 +1070,13 @@ union cvmx_sriox_maint_rd_data { union cvmx_sriox_mce_tx_ctl { uint64_t u64; struct cvmx_sriox_mce_tx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t mce:1; +#else + uint64_t mce:1; + uint64_t reserved_1_63:63; +#endif } s; struct cvmx_sriox_mce_tx_ctl_s cn63xx; struct cvmx_sriox_mce_tx_ctl_s cn63xxp1; @@ -646,6 +1086,7 @@ union cvmx_sriox_mce_tx_ctl { union cvmx_sriox_mem_op_ctrl { uint64_t u64; struct cvmx_sriox_mem_op_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t rr_ro:1; uint64_t w_ro:1; @@ -654,6 +1095,16 @@ union cvmx_sriox_mem_op_ctrl { uint64_t rp0_sid:2; uint64_t rp1_pid:1; uint64_t rp0_pid:2; +#else + uint64_t rp0_pid:2; + uint64_t rp1_pid:1; + uint64_t rp0_sid:2; + uint64_t rp1_sid:1; + uint64_t reserved_6_7:2; + uint64_t w_ro:1; + uint64_t rr_ro:1; + uint64_t reserved_10_63:54; +#endif } s; struct cvmx_sriox_mem_op_ctrl_s cn63xx; struct cvmx_sriox_mem_op_ctrl_s cn63xxp1; @@ -663,6 +1114,7 @@ union cvmx_sriox_mem_op_ctrl { union cvmx_sriox_omsg_ctrlx { uint64_t u64; struct cvmx_sriox_omsg_ctrlx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t testmode:1; uint64_t reserved_37_62:26; uint64_t silo_max:5; @@ -674,9 +1126,23 @@ union cvmx_sriox_omsg_ctrlx { uint64_t idm_did:1; uint64_t lttr_sp:4; uint64_t lttr_mp:4; +#else + uint64_t lttr_mp:4; + uint64_t lttr_sp:4; + uint64_t idm_did:1; + uint64_t idm_sis:1; + uint64_t idm_tt:1; + uint64_t reserved_11_14:4; + uint64_t rtry_en:1; + uint64_t rtry_thr:16; + uint64_t silo_max:5; + uint64_t reserved_37_62:26; + uint64_t testmode:1; +#endif } s; struct cvmx_sriox_omsg_ctrlx_s cn63xx; struct cvmx_sriox_omsg_ctrlx_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t testmode:1; uint64_t reserved_32_62:31; uint64_t rtry_thr:16; @@ -687,6 +1153,18 @@ union cvmx_sriox_omsg_ctrlx { uint64_t idm_did:1; uint64_t lttr_sp:4; uint64_t lttr_mp:4; +#else + uint64_t lttr_mp:4; + uint64_t lttr_sp:4; + uint64_t idm_did:1; + uint64_t idm_sis:1; + uint64_t idm_tt:1; + uint64_t reserved_11_14:4; + uint64_t rtry_en:1; + uint64_t rtry_thr:16; + uint64_t reserved_32_62:31; + uint64_t testmode:1; +#endif } cn63xxp1; struct cvmx_sriox_omsg_ctrlx_s cn66xx; }; @@ -694,9 +1172,15 @@ union cvmx_sriox_omsg_ctrlx { union cvmx_sriox_omsg_done_countsx { uint64_t u64; struct cvmx_sriox_omsg_done_countsx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bad:16; uint64_t good:16; +#else + uint64_t good:16; + uint64_t bad:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_omsg_done_countsx_s cn63xx; struct cvmx_sriox_omsg_done_countsx_s cn66xx; @@ -705,6 +1189,7 @@ union cvmx_sriox_omsg_done_countsx { union cvmx_sriox_omsg_fmp_mrx { uint64_t u64; struct cvmx_sriox_omsg_fmp_mrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t ctlr_sp:1; uint64_t ctlr_fmp:1; @@ -721,6 +1206,24 @@ union cvmx_sriox_omsg_fmp_mrx { uint64_t all_fmp:1; uint64_t all_nmp:1; uint64_t all_psd:1; +#else + uint64_t all_psd:1; + uint64_t all_nmp:1; + uint64_t all_fmp:1; + uint64_t all_sp:1; + uint64_t mbox_psd:1; + uint64_t mbox_nmp:1; + uint64_t mbox_fmp:1; + uint64_t mbox_sp:1; + uint64_t id_psd:1; + uint64_t id_nmp:1; + uint64_t id_fmp:1; + uint64_t id_sp:1; + uint64_t ctlr_nmp:1; + uint64_t ctlr_fmp:1; + uint64_t ctlr_sp:1; + uint64_t reserved_15_63:49; +#endif } s; struct cvmx_sriox_omsg_fmp_mrx_s cn63xx; struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1; @@ -730,6 +1233,7 @@ union cvmx_sriox_omsg_fmp_mrx { union cvmx_sriox_omsg_nmp_mrx { uint64_t u64; struct cvmx_sriox_omsg_nmp_mrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_15_63:49; uint64_t ctlr_sp:1; uint64_t ctlr_fmp:1; @@ -746,6 +1250,24 @@ union cvmx_sriox_omsg_nmp_mrx { uint64_t all_fmp:1; uint64_t all_nmp:1; uint64_t reserved_0_0:1; +#else + uint64_t reserved_0_0:1; + uint64_t all_nmp:1; + uint64_t all_fmp:1; + uint64_t all_sp:1; + uint64_t reserved_4_4:1; + uint64_t mbox_nmp:1; + uint64_t mbox_fmp:1; + uint64_t mbox_sp:1; + uint64_t reserved_8_8:1; + uint64_t id_nmp:1; + uint64_t id_fmp:1; + uint64_t id_sp:1; + uint64_t ctlr_nmp:1; + uint64_t ctlr_fmp:1; + uint64_t ctlr_sp:1; + uint64_t reserved_15_63:49; +#endif } s; struct cvmx_sriox_omsg_nmp_mrx_s cn63xx; struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1; @@ -755,16 +1277,30 @@ union cvmx_sriox_omsg_nmp_mrx { union cvmx_sriox_omsg_portx { uint64_t u64; struct cvmx_sriox_omsg_portx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enable:1; uint64_t reserved_3_30:28; uint64_t port:3; +#else + uint64_t port:3; + uint64_t reserved_3_30:28; + uint64_t enable:1; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_omsg_portx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t enable:1; uint64_t reserved_2_30:29; uint64_t port:2; +#else + uint64_t port:2; + uint64_t reserved_2_30:29; + uint64_t enable:1; + uint64_t reserved_32_63:32; +#endif } cn63xx; struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1; struct cvmx_sriox_omsg_portx_s cn66xx; @@ -773,8 +1309,13 @@ union cvmx_sriox_omsg_portx { union cvmx_sriox_omsg_silo_thr { uint64_t u64; struct cvmx_sriox_omsg_silo_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t tot_silo:5; +#else + uint64_t tot_silo:5; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_sriox_omsg_silo_thr_s cn63xx; struct cvmx_sriox_omsg_silo_thr_s cn66xx; @@ -783,6 +1324,7 @@ union cvmx_sriox_omsg_silo_thr { union cvmx_sriox_omsg_sp_mrx { uint64_t u64; struct cvmx_sriox_omsg_sp_mrx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t xmbox_sp:1; uint64_t ctlr_sp:1; @@ -800,6 +1342,25 @@ union cvmx_sriox_omsg_sp_mrx { uint64_t all_fmp:1; uint64_t all_nmp:1; uint64_t all_psd:1; +#else + uint64_t all_psd:1; + uint64_t all_nmp:1; + uint64_t all_fmp:1; + uint64_t all_sp:1; + uint64_t mbox_psd:1; + uint64_t mbox_nmp:1; + uint64_t mbox_fmp:1; + uint64_t mbox_sp:1; + uint64_t id_psd:1; + uint64_t id_nmp:1; + uint64_t id_fmp:1; + uint64_t id_sp:1; + uint64_t ctlr_nmp:1; + uint64_t ctlr_fmp:1; + uint64_t ctlr_sp:1; + uint64_t xmbox_sp:1; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_sriox_omsg_sp_mrx_s cn63xx; struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1; @@ -809,9 +1370,15 @@ union cvmx_sriox_omsg_sp_mrx { union cvmx_sriox_priox_in_use { uint64_t u64; struct cvmx_sriox_priox_in_use_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t end_cnt:16; uint64_t start_cnt:16; +#else + uint64_t start_cnt:16; + uint64_t end_cnt:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_priox_in_use_s cn63xx; struct cvmx_sriox_priox_in_use_s cn66xx; @@ -820,6 +1387,7 @@ union cvmx_sriox_priox_in_use { union cvmx_sriox_rx_bell { uint64_t u64; struct cvmx_sriox_rx_bell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t data:16; uint64_t src_id:16; @@ -829,6 +1397,17 @@ union cvmx_sriox_rx_bell { uint64_t id16:1; uint64_t reserved_2_2:1; uint64_t priority:2; +#else + uint64_t priority:2; + uint64_t reserved_2_2:1; + uint64_t id16:1; + uint64_t dest_id:1; + uint64_t reserved_5_7:3; + uint64_t count:8; + uint64_t src_id:16; + uint64_t data:16; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_sriox_rx_bell_s cn63xx; struct cvmx_sriox_rx_bell_s cn63xxp1; @@ -838,9 +1417,15 @@ union cvmx_sriox_rx_bell { union cvmx_sriox_rx_bell_seq { uint64_t u64; struct cvmx_sriox_rx_bell_seq_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_40_63:24; uint64_t count:8; uint64_t seq:32; +#else + uint64_t seq:32; + uint64_t count:8; + uint64_t reserved_40_63:24; +#endif } s; struct cvmx_sriox_rx_bell_seq_s cn63xx; struct cvmx_sriox_rx_bell_seq_s cn63xxp1; @@ -850,6 +1435,7 @@ union cvmx_sriox_rx_bell_seq { union cvmx_sriox_rx_status { uint64_t u64; struct cvmx_sriox_rx_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t rtn_pr3:8; uint64_t rtn_pr2:8; uint64_t rtn_pr1:8; @@ -859,6 +1445,17 @@ union cvmx_sriox_rx_status { uint64_t reserved_13_15:3; uint64_t n_post:5; uint64_t post:8; +#else + uint64_t post:8; + uint64_t n_post:5; + uint64_t reserved_13_15:3; + uint64_t comp:8; + uint64_t mbox:4; + uint64_t reserved_28_39:12; + uint64_t rtn_pr1:8; + uint64_t rtn_pr2:8; + uint64_t rtn_pr3:8; +#endif } s; struct cvmx_sriox_rx_status_s cn63xx; struct cvmx_sriox_rx_status_s cn63xxp1; @@ -868,6 +1465,7 @@ union cvmx_sriox_rx_status { union cvmx_sriox_s2m_typex { uint64_t u64; struct cvmx_sriox_s2m_typex_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t wr_op:3; uint64_t reserved_15_15:1; @@ -879,6 +1477,19 @@ union cvmx_sriox_s2m_typex { uint64_t id16:1; uint64_t reserved_2_3:2; uint64_t iaow_sel:2; +#else + uint64_t iaow_sel:2; + uint64_t reserved_2_3:2; + uint64_t id16:1; + uint64_t src_id:1; + uint64_t reserved_6_7:2; + uint64_t rd_prior:2; + uint64_t wr_prior:2; + uint64_t rd_op:3; + uint64_t reserved_15_15:1; + uint64_t wr_op:3; + uint64_t reserved_19_63:45; +#endif } s; struct cvmx_sriox_s2m_typex_s cn63xx; struct cvmx_sriox_s2m_typex_s cn63xxp1; @@ -888,8 +1499,13 @@ union cvmx_sriox_s2m_typex { union cvmx_sriox_seq { uint64_t u64; struct cvmx_sriox_seq_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t seq:32; +#else + uint64_t seq:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_seq_s cn63xx; struct cvmx_sriox_seq_s cn63xxp1; @@ -899,9 +1515,15 @@ union cvmx_sriox_seq { union cvmx_sriox_status_reg { uint64_t u64; struct cvmx_sriox_status_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_2_63:62; uint64_t access:1; uint64_t srio:1; +#else + uint64_t srio:1; + uint64_t access:1; + uint64_t reserved_2_63:62; +#endif } s; struct cvmx_sriox_status_reg_s cn63xx; struct cvmx_sriox_status_reg_s cn63xxp1; @@ -911,12 +1533,21 @@ union cvmx_sriox_status_reg { union cvmx_sriox_tag_ctrl { uint64_t u64; struct cvmx_sriox_tag_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t o_clr:1; uint64_t reserved_13_15:3; uint64_t otag:5; uint64_t reserved_5_7:3; uint64_t itag:5; +#else + uint64_t itag:5; + uint64_t reserved_5_7:3; + uint64_t otag:5; + uint64_t reserved_13_15:3; + uint64_t o_clr:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_sriox_tag_ctrl_s cn63xx; struct cvmx_sriox_tag_ctrl_s cn63xxp1; @@ -926,12 +1557,21 @@ union cvmx_sriox_tag_ctrl { union cvmx_sriox_tlp_credits { uint64_t u64; struct cvmx_sriox_tlp_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_28_63:36; uint64_t mbox:4; uint64_t comp:8; uint64_t reserved_13_15:3; uint64_t n_post:5; uint64_t post:8; +#else + uint64_t post:8; + uint64_t n_post:5; + uint64_t reserved_13_15:3; + uint64_t comp:8; + uint64_t mbox:4; + uint64_t reserved_28_63:36; +#endif } s; struct cvmx_sriox_tlp_credits_s cn63xx; struct cvmx_sriox_tlp_credits_s cn63xxp1; @@ -941,6 +1581,7 @@ union cvmx_sriox_tlp_credits { union cvmx_sriox_tx_bell { uint64_t u64; struct cvmx_sriox_tx_bell_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t data:16; uint64_t dest_id:16; @@ -951,6 +1592,18 @@ union cvmx_sriox_tx_bell { uint64_t id16:1; uint64_t reserved_2_2:1; uint64_t priority:2; +#else + uint64_t priority:2; + uint64_t reserved_2_2:1; + uint64_t id16:1; + uint64_t src_id:1; + uint64_t reserved_5_7:3; + uint64_t pending:1; + uint64_t reserved_9_15:7; + uint64_t dest_id:16; + uint64_t data:16; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_sriox_tx_bell_s cn63xx; struct cvmx_sriox_tx_bell_s cn63xxp1; @@ -960,6 +1613,7 @@ union cvmx_sriox_tx_bell { union cvmx_sriox_tx_bell_info { uint64_t u64; struct cvmx_sriox_tx_bell_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_48_63:16; uint64_t data:16; uint64_t dest_id:16; @@ -971,6 +1625,19 @@ union cvmx_sriox_tx_bell_info { uint64_t id16:1; uint64_t reserved_2_2:1; uint64_t priority:2; +#else + uint64_t priority:2; + uint64_t reserved_2_2:1; + uint64_t id16:1; + uint64_t src_id:1; + uint64_t retry:1; + uint64_t error:1; + uint64_t timeout:1; + uint64_t reserved_8_15:8; + uint64_t dest_id:16; + uint64_t data:16; + uint64_t reserved_48_63:16; +#endif } s; struct cvmx_sriox_tx_bell_info_s cn63xx; struct cvmx_sriox_tx_bell_info_s cn63xxp1; @@ -980,6 +1647,7 @@ union cvmx_sriox_tx_bell_info { union cvmx_sriox_tx_ctrl { uint64_t u64; struct cvmx_sriox_tx_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_53_63:11; uint64_t tag_th2:5; uint64_t reserved_45_47:3; @@ -992,6 +1660,20 @@ union cvmx_sriox_tx_ctrl { uint64_t tx_th1:4; uint64_t reserved_4_7:4; uint64_t tx_th0:4; +#else + uint64_t tx_th0:4; + uint64_t reserved_4_7:4; + uint64_t tx_th1:4; + uint64_t reserved_12_15:4; + uint64_t tx_th2:4; + uint64_t reserved_20_31:12; + uint64_t tag_th0:5; + uint64_t reserved_37_39:3; + uint64_t tag_th1:5; + uint64_t reserved_45_47:3; + uint64_t tag_th2:5; + uint64_t reserved_53_63:11; +#endif } s; struct cvmx_sriox_tx_ctrl_s cn63xx; struct cvmx_sriox_tx_ctrl_s cn63xxp1; @@ -1001,8 +1683,13 @@ union cvmx_sriox_tx_ctrl { union cvmx_sriox_tx_emphasis { uint64_t u64; struct cvmx_sriox_tx_emphasis_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t emph:4; +#else + uint64_t emph:4; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_sriox_tx_emphasis_s cn63xx; struct cvmx_sriox_tx_emphasis_s cn66xx; @@ -1011,11 +1698,19 @@ union cvmx_sriox_tx_emphasis { union cvmx_sriox_tx_status { uint64_t u64; struct cvmx_sriox_tx_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t s2m_pr3:8; uint64_t s2m_pr2:8; uint64_t s2m_pr1:8; uint64_t s2m_pr0:8; +#else + uint64_t s2m_pr0:8; + uint64_t s2m_pr1:8; + uint64_t s2m_pr2:8; + uint64_t s2m_pr3:8; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_tx_status_s cn63xx; struct cvmx_sriox_tx_status_s cn63xxp1; @@ -1025,9 +1720,15 @@ union cvmx_sriox_tx_status { union cvmx_sriox_wr_done_counts { uint64_t u64; struct cvmx_sriox_wr_done_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t bad:16; uint64_t good:16; +#else + uint64_t good:16; + uint64_t bad:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_sriox_wr_done_counts_s cn63xx; struct cvmx_sriox_wr_done_counts_s cn66xx; diff --git a/arch/mips/include/asm/octeon/cvmx-srxx-defs.h b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h index d82b366c279..c98e625cd4e 100644 --- a/arch/mips/include/asm/octeon/cvmx-srxx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,27 +28,29 @@ #ifndef __CVMX_SRXX_DEFS_H__ #define __CVMX_SRXX_DEFS_H__ -#define CVMX_SRXX_COM_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000200ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SRXX_IGN_RX_FULL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000218ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SRXX_SPI4_CALX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000000ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SRXX_SPI4_STAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000208ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SRXX_SW_TICK_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000220ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SRXX_SW_TICK_DAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000228ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull) union cvmx_srxx_com_ctl { uint64_t u64; struct cvmx_srxx_com_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t prts:4; uint64_t st_en:1; uint64_t reserved_1_2:2; uint64_t inf_en:1; +#else + uint64_t inf_en:1; + uint64_t reserved_1_2:2; + uint64_t st_en:1; + uint64_t prts:4; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_srxx_com_ctl_s cn38xx; struct cvmx_srxx_com_ctl_s cn38xxp2; @@ -59,8 +61,13 @@ union cvmx_srxx_com_ctl { union cvmx_srxx_ign_rx_full { uint64_t u64; struct cvmx_srxx_ign_rx_full_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t ignore:16; +#else + uint64_t ignore:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_srxx_ign_rx_full_s cn38xx; struct cvmx_srxx_ign_rx_full_s cn38xxp2; @@ -71,12 +78,21 @@ union cvmx_srxx_ign_rx_full { union cvmx_srxx_spi4_calx { uint64_t u64; struct cvmx_srxx_spi4_calx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t oddpar:1; uint64_t prt3:4; uint64_t prt2:4; uint64_t prt1:4; uint64_t prt0:4; +#else + uint64_t prt0:4; + uint64_t prt1:4; + uint64_t prt2:4; + uint64_t prt3:4; + uint64_t oddpar:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_srxx_spi4_calx_s cn38xx; struct cvmx_srxx_spi4_calx_s cn38xxp2; @@ -87,10 +103,17 @@ union cvmx_srxx_spi4_calx { union cvmx_srxx_spi4_stat { uint64_t u64; struct cvmx_srxx_spi4_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t m:8; uint64_t reserved_7_7:1; uint64_t len:7; +#else + uint64_t len:7; + uint64_t reserved_7_7:1; + uint64_t m:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_srxx_spi4_stat_s cn38xx; struct cvmx_srxx_spi4_stat_s cn38xxp2; @@ -101,12 +124,21 @@ union cvmx_srxx_spi4_stat { union cvmx_srxx_sw_tick_ctl { uint64_t u64; struct cvmx_srxx_sw_tick_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_14_63:50; uint64_t eop:1; uint64_t sop:1; uint64_t mod:4; uint64_t opc:4; uint64_t adr:4; +#else + uint64_t adr:4; + uint64_t opc:4; + uint64_t mod:4; + uint64_t sop:1; + uint64_t eop:1; + uint64_t reserved_14_63:50; +#endif } s; struct cvmx_srxx_sw_tick_ctl_s cn38xx; struct cvmx_srxx_sw_tick_ctl_s cn58xx; @@ -116,7 +148,11 @@ union cvmx_srxx_sw_tick_ctl { union cvmx_srxx_sw_tick_dat { uint64_t u64; struct cvmx_srxx_sw_tick_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint64_t dat:64; +#else uint64_t dat:64; +#endif } s; struct cvmx_srxx_sw_tick_dat_s cn38xx; struct cvmx_srxx_sw_tick_dat_s cn58xx; diff --git a/arch/mips/include/asm/octeon/cvmx-stxx-defs.h b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h index 4f209b62cae..146354005d3 100644 --- a/arch/mips/include/asm/octeon/cvmx-stxx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,47 +28,39 @@ #ifndef __CVMX_STXX_DEFS_H__ #define __CVMX_STXX_DEFS_H__ -#define CVMX_STXX_ARB_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000608ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_BCKPRS_CNT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000688ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_COM_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000600ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_DIP_CNT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000690ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_IGN_CAL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000610ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_INT_MSK(block_id) \ - CVMX_ADD_IO_SEG(0x00011800900006A0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_INT_REG(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000698ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_INT_SYNC(block_id) \ - CVMX_ADD_IO_SEG(0x00011800900006A8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_MIN_BST(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000618ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_SPI4_CALX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000400ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_SPI4_DAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000628ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_SPI4_STAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000630ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_STAT_BYTES_HI(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000648ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_STAT_BYTES_LO(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000680ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_STAT_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000638ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_STAT_PKT_XMT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000640ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull) union cvmx_stxx_arb_ctl { uint64_t u64; struct cvmx_stxx_arb_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t mintrn:1; uint64_t reserved_4_4:1; uint64_t igntpa:1; uint64_t reserved_0_2:3; +#else + uint64_t reserved_0_2:3; + uint64_t igntpa:1; + uint64_t reserved_4_4:1; + uint64_t mintrn:1; + uint64_t reserved_6_63:58; +#endif } s; struct cvmx_stxx_arb_ctl_s cn38xx; struct cvmx_stxx_arb_ctl_s cn38xxp2; @@ -79,8 +71,13 @@ union cvmx_stxx_arb_ctl { union cvmx_stxx_bckprs_cnt { uint64_t u64; struct cvmx_stxx_bckprs_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_stxx_bckprs_cnt_s cn38xx; struct cvmx_stxx_bckprs_cnt_s cn38xxp2; @@ -91,10 +88,17 @@ union cvmx_stxx_bckprs_cnt { union cvmx_stxx_com_ctl { uint64_t u64; struct cvmx_stxx_com_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_4_63:60; uint64_t st_en:1; uint64_t reserved_1_2:2; uint64_t inf_en:1; +#else + uint64_t inf_en:1; + uint64_t reserved_1_2:2; + uint64_t st_en:1; + uint64_t reserved_4_63:60; +#endif } s; struct cvmx_stxx_com_ctl_s cn38xx; struct cvmx_stxx_com_ctl_s cn38xxp2; @@ -105,9 +109,15 @@ union cvmx_stxx_com_ctl { union cvmx_stxx_dip_cnt { uint64_t u64; struct cvmx_stxx_dip_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t frmmax:4; uint64_t dipmax:4; +#else + uint64_t dipmax:4; + uint64_t frmmax:4; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_stxx_dip_cnt_s cn38xx; struct cvmx_stxx_dip_cnt_s cn38xxp2; @@ -118,8 +128,13 @@ union cvmx_stxx_dip_cnt { union cvmx_stxx_ign_cal { uint64_t u64; struct cvmx_stxx_ign_cal_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t igntpa:16; +#else + uint64_t igntpa:16; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_stxx_ign_cal_s cn38xx; struct cvmx_stxx_ign_cal_s cn38xxp2; @@ -130,6 +145,7 @@ union cvmx_stxx_ign_cal { union cvmx_stxx_int_msk { uint64_t u64; struct cvmx_stxx_int_msk_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t frmerr:1; uint64_t unxfrm:1; @@ -139,6 +155,17 @@ union cvmx_stxx_int_msk { uint64_t ovrbst:1; uint64_t calpar1:1; uint64_t calpar0:1; +#else + uint64_t calpar0:1; + uint64_t calpar1:1; + uint64_t ovrbst:1; + uint64_t datovr:1; + uint64_t diperr:1; + uint64_t nosync:1; + uint64_t unxfrm:1; + uint64_t frmerr:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_stxx_int_msk_s cn38xx; struct cvmx_stxx_int_msk_s cn38xxp2; @@ -149,6 +176,7 @@ union cvmx_stxx_int_msk { union cvmx_stxx_int_reg { uint64_t u64; struct cvmx_stxx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t syncerr:1; uint64_t frmerr:1; @@ -159,6 +187,18 @@ union cvmx_stxx_int_reg { uint64_t ovrbst:1; uint64_t calpar1:1; uint64_t calpar0:1; +#else + uint64_t calpar0:1; + uint64_t calpar1:1; + uint64_t ovrbst:1; + uint64_t datovr:1; + uint64_t diperr:1; + uint64_t nosync:1; + uint64_t unxfrm:1; + uint64_t frmerr:1; + uint64_t syncerr:1; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_stxx_int_reg_s cn38xx; struct cvmx_stxx_int_reg_s cn38xxp2; @@ -169,6 +209,7 @@ union cvmx_stxx_int_reg { union cvmx_stxx_int_sync { uint64_t u64; struct cvmx_stxx_int_sync_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t frmerr:1; uint64_t unxfrm:1; @@ -178,6 +219,17 @@ union cvmx_stxx_int_sync { uint64_t ovrbst:1; uint64_t calpar1:1; uint64_t calpar0:1; +#else + uint64_t calpar0:1; + uint64_t calpar1:1; + uint64_t ovrbst:1; + uint64_t datovr:1; + uint64_t diperr:1; + uint64_t nosync:1; + uint64_t unxfrm:1; + uint64_t frmerr:1; + uint64_t reserved_8_63:56; +#endif } s; struct cvmx_stxx_int_sync_s cn38xx; struct cvmx_stxx_int_sync_s cn38xxp2; @@ -188,8 +240,13 @@ union cvmx_stxx_int_sync { union cvmx_stxx_min_bst { uint64_t u64; struct cvmx_stxx_min_bst_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_9_63:55; uint64_t minb:9; +#else + uint64_t minb:9; + uint64_t reserved_9_63:55; +#endif } s; struct cvmx_stxx_min_bst_s cn38xx; struct cvmx_stxx_min_bst_s cn38xxp2; @@ -200,12 +257,21 @@ union cvmx_stxx_min_bst { union cvmx_stxx_spi4_calx { uint64_t u64; struct cvmx_stxx_spi4_calx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_17_63:47; uint64_t oddpar:1; uint64_t prt3:4; uint64_t prt2:4; uint64_t prt1:4; uint64_t prt0:4; +#else + uint64_t prt0:4; + uint64_t prt1:4; + uint64_t prt2:4; + uint64_t prt3:4; + uint64_t oddpar:1; + uint64_t reserved_17_63:47; +#endif } s; struct cvmx_stxx_spi4_calx_s cn38xx; struct cvmx_stxx_spi4_calx_s cn38xxp2; @@ -216,9 +282,15 @@ union cvmx_stxx_spi4_calx { union cvmx_stxx_spi4_dat { uint64_t u64; struct cvmx_stxx_spi4_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t alpha:16; uint64_t max_t:16; +#else + uint64_t max_t:16; + uint64_t alpha:16; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_stxx_spi4_dat_s cn38xx; struct cvmx_stxx_spi4_dat_s cn38xxp2; @@ -229,10 +301,17 @@ union cvmx_stxx_spi4_dat { union cvmx_stxx_spi4_stat { uint64_t u64; struct cvmx_stxx_spi4_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_16_63:48; uint64_t m:8; uint64_t reserved_7_7:1; uint64_t len:7; +#else + uint64_t len:7; + uint64_t reserved_7_7:1; + uint64_t m:8; + uint64_t reserved_16_63:48; +#endif } s; struct cvmx_stxx_spi4_stat_s cn38xx; struct cvmx_stxx_spi4_stat_s cn38xxp2; @@ -243,8 +322,13 @@ union cvmx_stxx_spi4_stat { union cvmx_stxx_stat_bytes_hi { uint64_t u64; struct cvmx_stxx_stat_bytes_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_stxx_stat_bytes_hi_s cn38xx; struct cvmx_stxx_stat_bytes_hi_s cn38xxp2; @@ -255,8 +339,13 @@ union cvmx_stxx_stat_bytes_hi { union cvmx_stxx_stat_bytes_lo { uint64_t u64; struct cvmx_stxx_stat_bytes_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_stxx_stat_bytes_lo_s cn38xx; struct cvmx_stxx_stat_bytes_lo_s cn38xxp2; @@ -267,9 +356,15 @@ union cvmx_stxx_stat_bytes_lo { union cvmx_stxx_stat_ctl { uint64_t u64; struct cvmx_stxx_stat_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t clr:1; uint64_t bckprs:4; +#else + uint64_t bckprs:4; + uint64_t clr:1; + uint64_t reserved_5_63:59; +#endif } s; struct cvmx_stxx_stat_ctl_s cn38xx; struct cvmx_stxx_stat_ctl_s cn38xxp2; @@ -280,8 +375,13 @@ union cvmx_stxx_stat_ctl { union cvmx_stxx_stat_pkt_xmt { uint64_t u64; struct cvmx_stxx_stat_pkt_xmt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t cnt:32; +#else + uint64_t cnt:32; + uint64_t reserved_32_63:32; +#endif } s; struct cvmx_stxx_stat_pkt_xmt_s cn38xx; struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2; diff --git a/arch/mips/include/asm/octeon/cvmx-sysinfo.h b/arch/mips/include/asm/octeon/cvmx-sysinfo.h index 61dd5741afe..2131197422e 100644 --- a/arch/mips/include/asm/octeon/cvmx-sysinfo.h +++ b/arch/mips/include/asm/octeon/cvmx-sysinfo.h @@ -85,7 +85,7 @@ struct cvmx_sysinfo { char board_serial_number[OCTEON_SERIAL_LEN]; /* * Several boards support compact flash on the Octeon boot - * bus. The CF memory spaces may be mapped to different + * bus. The CF memory spaces may be mapped to different * addresses on different boards. These values will be 0 if * CF is not present. Note that these addresses are physical * addresses, and it is up to the application to use the @@ -123,25 +123,25 @@ extern struct cvmx_sysinfo *cvmx_sysinfo_get(void); /** * This function is used in non-simple executive environments (such as - * Linux kernel, u-boot, etc.) to configure the minimal fields that + * Linux kernel, u-boot, etc.) to configure the minimal fields that * are required to use simple executive files directly. * * Locking (if required) must be handled outside of this * function * * @phy_mem_desc_ptr: Pointer to global physical memory descriptor - * (bootmem descriptor) @board_type: Octeon board - * type enumeration + * (bootmem descriptor) @board_type: Octeon board + * type enumeration * * @board_rev_major: - * Board major revision + * Board major revision * @board_rev_minor: - * Board minor revision + * Board minor revision * @cpu_clock_hz: - * CPU clock freqency in hertz + * CPU clock freqency in hertz * * Returns 0: Failure - * 1: success + * 1: success */ extern int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr, uint16_t board_type, diff --git a/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h b/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h index 594f1b68cd6..bc5b80c6bbe 100644 --- a/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2010 Cavium Networks + * Copyright (c) 2003-2012 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -25,8 +25,8 @@ * Contact Cavium Networks for more information ***********************license end**************************************/ -#ifndef __CVMX_UCTLX_TYPEDEFS_H__ -#define __CVMX_UCTLX_TYPEDEFS_H__ +#ifndef __CVMX_UCTLX_DEFS_H__ +#define __CVMX_UCTLX_DEFS_H__ #define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull)) #define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull)) @@ -45,6 +45,7 @@ union cvmx_uctlx_bist_status { uint64_t u64; struct cvmx_uctlx_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t data_bis:1; uint64_t desc_bis:1; @@ -52,14 +53,29 @@ union cvmx_uctlx_bist_status { uint64_t orbm_bis:1; uint64_t wrbm_bis:1; uint64_t ppaf_bis:1; +#else + uint64_t ppaf_bis:1; + uint64_t wrbm_bis:1; + uint64_t orbm_bis:1; + uint64_t erbm_bis:1; + uint64_t desc_bis:1; + uint64_t data_bis:1; + uint64_t reserved_6_63:58; +#endif } s; - struct cvmx_uctlx_bist_status_s cn63xx; - struct cvmx_uctlx_bist_status_s cn63xxp1; + struct cvmx_uctlx_bist_status_s cn61xx; + struct cvmx_uctlx_bist_status_s cn63xx; + struct cvmx_uctlx_bist_status_s cn63xxp1; + struct cvmx_uctlx_bist_status_s cn66xx; + struct cvmx_uctlx_bist_status_s cn68xx; + struct cvmx_uctlx_bist_status_s cn68xxp1; + struct cvmx_uctlx_bist_status_s cnf71xx; }; union cvmx_uctlx_clk_rst_ctl { uint64_t u64; struct cvmx_uctlx_clk_rst_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_25_63:39; uint64_t clear_bist:1; uint64_t start_bist:1; @@ -81,14 +97,43 @@ union cvmx_uctlx_clk_rst_ctl { uint64_t p_por:1; uint64_t p_prst:1; uint64_t hrst:1; +#else + uint64_t hrst:1; + uint64_t p_prst:1; + uint64_t p_por:1; + uint64_t p_com_on:1; + uint64_t reserved_4_4:1; + uint64_t p_refclk_div:2; + uint64_t p_refclk_sel:2; + uint64_t h_div:4; + uint64_t o_clkdiv_en:1; + uint64_t h_clkdiv_en:1; + uint64_t h_clkdiv_rst:1; + uint64_t h_clkdiv_byp:1; + uint64_t o_clkdiv_rst:1; + uint64_t app_start_clk:1; + uint64_t ohci_susp_lgcy:1; + uint64_t ohci_sm:1; + uint64_t ohci_clkcktrst:1; + uint64_t ehci_sm:1; + uint64_t start_bist:1; + uint64_t clear_bist:1; + uint64_t reserved_25_63:39; +#endif } s; - struct cvmx_uctlx_clk_rst_ctl_s cn63xx; - struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1; + struct cvmx_uctlx_clk_rst_ctl_s cn61xx; + struct cvmx_uctlx_clk_rst_ctl_s cn63xx; + struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1; + struct cvmx_uctlx_clk_rst_ctl_s cn66xx; + struct cvmx_uctlx_clk_rst_ctl_s cn68xx; + struct cvmx_uctlx_clk_rst_ctl_s cn68xxp1; + struct cvmx_uctlx_clk_rst_ctl_s cnf71xx; }; union cvmx_uctlx_ehci_ctl { uint64_t u64; struct cvmx_uctlx_ehci_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_20_63:44; uint64_t desc_rbm:1; uint64_t reg_nb:1; @@ -101,45 +146,96 @@ union cvmx_uctlx_ehci_ctl { uint64_t inv_reg_a2:1; uint64_t ehci_64b_addr_en:1; uint64_t l2c_addr_msb:8; +#else + uint64_t l2c_addr_msb:8; + uint64_t ehci_64b_addr_en:1; + uint64_t inv_reg_a2:1; + uint64_t l2c_desc_emod:2; + uint64_t l2c_buff_emod:2; + uint64_t l2c_stt:1; + uint64_t l2c_0pag:1; + uint64_t l2c_bc:1; + uint64_t l2c_dc:1; + uint64_t reg_nb:1; + uint64_t desc_rbm:1; + uint64_t reserved_20_63:44; +#endif } s; - struct cvmx_uctlx_ehci_ctl_s cn63xx; - struct cvmx_uctlx_ehci_ctl_s cn63xxp1; + struct cvmx_uctlx_ehci_ctl_s cn61xx; + struct cvmx_uctlx_ehci_ctl_s cn63xx; + struct cvmx_uctlx_ehci_ctl_s cn63xxp1; + struct cvmx_uctlx_ehci_ctl_s cn66xx; + struct cvmx_uctlx_ehci_ctl_s cn68xx; + struct cvmx_uctlx_ehci_ctl_s cn68xxp1; + struct cvmx_uctlx_ehci_ctl_s cnf71xx; }; union cvmx_uctlx_ehci_fla { uint64_t u64; struct cvmx_uctlx_ehci_fla_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_6_63:58; uint64_t fla:6; +#else + uint64_t fla:6; + uint64_t reserved_6_63:58; +#endif } s; - struct cvmx_uctlx_ehci_fla_s cn63xx; - struct cvmx_uctlx_ehci_fla_s cn63xxp1; + struct cvmx_uctlx_ehci_fla_s cn61xx; + struct cvmx_uctlx_ehci_fla_s cn63xx; + struct cvmx_uctlx_ehci_fla_s cn63xxp1; + struct cvmx_uctlx_ehci_fla_s cn66xx; + struct cvmx_uctlx_ehci_fla_s cn68xx; + struct cvmx_uctlx_ehci_fla_s cn68xxp1; + struct cvmx_uctlx_ehci_fla_s cnf71xx; }; union cvmx_uctlx_erto_ctl { uint64_t u64; struct cvmx_uctlx_erto_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t to_val:27; uint64_t reserved_0_4:5; +#else + uint64_t reserved_0_4:5; + uint64_t to_val:27; + uint64_t reserved_32_63:32; +#endif } s; - struct cvmx_uctlx_erto_ctl_s cn63xx; - struct cvmx_uctlx_erto_ctl_s cn63xxp1; + struct cvmx_uctlx_erto_ctl_s cn61xx; + struct cvmx_uctlx_erto_ctl_s cn63xx; + struct cvmx_uctlx_erto_ctl_s cn63xxp1; + struct cvmx_uctlx_erto_ctl_s cn66xx; + struct cvmx_uctlx_erto_ctl_s cn68xx; + struct cvmx_uctlx_erto_ctl_s cn68xxp1; + struct cvmx_uctlx_erto_ctl_s cnf71xx; }; union cvmx_uctlx_if_ena { uint64_t u64; struct cvmx_uctlx_if_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_1_63:63; uint64_t en:1; +#else + uint64_t en:1; + uint64_t reserved_1_63:63; +#endif } s; - struct cvmx_uctlx_if_ena_s cn63xx; - struct cvmx_uctlx_if_ena_s cn63xxp1; + struct cvmx_uctlx_if_ena_s cn61xx; + struct cvmx_uctlx_if_ena_s cn63xx; + struct cvmx_uctlx_if_ena_s cn63xxp1; + struct cvmx_uctlx_if_ena_s cn66xx; + struct cvmx_uctlx_if_ena_s cn68xx; + struct cvmx_uctlx_if_ena_s cn68xxp1; + struct cvmx_uctlx_if_ena_s cnf71xx; }; union cvmx_uctlx_int_ena { uint64_t u64; struct cvmx_uctlx_int_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ec_ovf_e:1; uint64_t oc_ovf_e:1; @@ -149,14 +245,31 @@ union cvmx_uctlx_int_ena { uint64_t or_psh_f:1; uint64_t er_psh_f:1; uint64_t pp_psh_f:1; +#else + uint64_t pp_psh_f:1; + uint64_t er_psh_f:1; + uint64_t or_psh_f:1; + uint64_t cf_psh_f:1; + uint64_t wb_psh_f:1; + uint64_t wb_pop_e:1; + uint64_t oc_ovf_e:1; + uint64_t ec_ovf_e:1; + uint64_t reserved_8_63:56; +#endif } s; - struct cvmx_uctlx_int_ena_s cn63xx; - struct cvmx_uctlx_int_ena_s cn63xxp1; + struct cvmx_uctlx_int_ena_s cn61xx; + struct cvmx_uctlx_int_ena_s cn63xx; + struct cvmx_uctlx_int_ena_s cn63xxp1; + struct cvmx_uctlx_int_ena_s cn66xx; + struct cvmx_uctlx_int_ena_s cn68xx; + struct cvmx_uctlx_int_ena_s cn68xxp1; + struct cvmx_uctlx_int_ena_s cnf71xx; }; union cvmx_uctlx_int_reg { uint64_t u64; struct cvmx_uctlx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_8_63:56; uint64_t ec_ovf_e:1; uint64_t oc_ovf_e:1; @@ -166,14 +279,31 @@ union cvmx_uctlx_int_reg { uint64_t or_psh_f:1; uint64_t er_psh_f:1; uint64_t pp_psh_f:1; +#else + uint64_t pp_psh_f:1; + uint64_t er_psh_f:1; + uint64_t or_psh_f:1; + uint64_t cf_psh_f:1; + uint64_t wb_psh_f:1; + uint64_t wb_pop_e:1; + uint64_t oc_ovf_e:1; + uint64_t ec_ovf_e:1; + uint64_t reserved_8_63:56; +#endif } s; - struct cvmx_uctlx_int_reg_s cn63xx; - struct cvmx_uctlx_int_reg_s cn63xxp1; + struct cvmx_uctlx_int_reg_s cn61xx; + struct cvmx_uctlx_int_reg_s cn63xx; + struct cvmx_uctlx_int_reg_s cn63xxp1; + struct cvmx_uctlx_int_reg_s cn66xx; + struct cvmx_uctlx_int_reg_s cn68xx; + struct cvmx_uctlx_int_reg_s cn68xxp1; + struct cvmx_uctlx_int_reg_s cnf71xx; }; union cvmx_uctlx_ohci_ctl { uint64_t u64; struct cvmx_uctlx_ohci_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_19_63:45; uint64_t reg_nb:1; uint64_t l2c_dc:1; @@ -185,35 +315,73 @@ union cvmx_uctlx_ohci_ctl { uint64_t inv_reg_a2:1; uint64_t reserved_8_8:1; uint64_t l2c_addr_msb:8; +#else + uint64_t l2c_addr_msb:8; + uint64_t reserved_8_8:1; + uint64_t inv_reg_a2:1; + uint64_t l2c_desc_emod:2; + uint64_t l2c_buff_emod:2; + uint64_t l2c_stt:1; + uint64_t l2c_0pag:1; + uint64_t l2c_bc:1; + uint64_t l2c_dc:1; + uint64_t reg_nb:1; + uint64_t reserved_19_63:45; +#endif } s; - struct cvmx_uctlx_ohci_ctl_s cn63xx; - struct cvmx_uctlx_ohci_ctl_s cn63xxp1; + struct cvmx_uctlx_ohci_ctl_s cn61xx; + struct cvmx_uctlx_ohci_ctl_s cn63xx; + struct cvmx_uctlx_ohci_ctl_s cn63xxp1; + struct cvmx_uctlx_ohci_ctl_s cn66xx; + struct cvmx_uctlx_ohci_ctl_s cn68xx; + struct cvmx_uctlx_ohci_ctl_s cn68xxp1; + struct cvmx_uctlx_ohci_ctl_s cnf71xx; }; union cvmx_uctlx_orto_ctl { uint64_t u64; struct cvmx_uctlx_orto_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_32_63:32; uint64_t to_val:24; uint64_t reserved_0_7:8; +#else + uint64_t reserved_0_7:8; + uint64_t to_val:24; + uint64_t reserved_32_63:32; +#endif } s; - struct cvmx_uctlx_orto_ctl_s cn63xx; - struct cvmx_uctlx_orto_ctl_s cn63xxp1; + struct cvmx_uctlx_orto_ctl_s cn61xx; + struct cvmx_uctlx_orto_ctl_s cn63xx; + struct cvmx_uctlx_orto_ctl_s cn63xxp1; + struct cvmx_uctlx_orto_ctl_s cn66xx; + struct cvmx_uctlx_orto_ctl_s cn68xx; + struct cvmx_uctlx_orto_ctl_s cn68xxp1; + struct cvmx_uctlx_orto_ctl_s cnf71xx; }; union cvmx_uctlx_ppaf_wm { uint64_t u64; struct cvmx_uctlx_ppaf_wm_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_5_63:59; uint64_t wm:5; +#else + uint64_t wm:5; + uint64_t reserved_5_63:59; +#endif } s; - struct cvmx_uctlx_ppaf_wm_s cn63xx; - struct cvmx_uctlx_ppaf_wm_s cn63xxp1; + struct cvmx_uctlx_ppaf_wm_s cn61xx; + struct cvmx_uctlx_ppaf_wm_s cn63xx; + struct cvmx_uctlx_ppaf_wm_s cn63xxp1; + struct cvmx_uctlx_ppaf_wm_s cn66xx; + struct cvmx_uctlx_ppaf_wm_s cnf71xx; }; union cvmx_uctlx_uphy_ctl_status { uint64_t u64; struct cvmx_uctlx_uphy_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_10_63:54; uint64_t bist_done:1; uint64_t bist_err:1; @@ -225,14 +393,33 @@ union cvmx_uctlx_uphy_ctl_status { uint64_t uphy_bist:1; uint64_t bist_en:1; uint64_t ate_reset:1; +#else + uint64_t ate_reset:1; + uint64_t bist_en:1; + uint64_t uphy_bist:1; + uint64_t vtest_en:1; + uint64_t siddq:1; + uint64_t lsbist:1; + uint64_t fsbist:1; + uint64_t hsbist:1; + uint64_t bist_err:1; + uint64_t bist_done:1; + uint64_t reserved_10_63:54; +#endif } s; - struct cvmx_uctlx_uphy_ctl_status_s cn63xx; - struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1; + struct cvmx_uctlx_uphy_ctl_status_s cn61xx; + struct cvmx_uctlx_uphy_ctl_status_s cn63xx; + struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1; + struct cvmx_uctlx_uphy_ctl_status_s cn66xx; + struct cvmx_uctlx_uphy_ctl_status_s cn68xx; + struct cvmx_uctlx_uphy_ctl_status_s cn68xxp1; + struct cvmx_uctlx_uphy_ctl_status_s cnf71xx; }; union cvmx_uctlx_uphy_portx_ctl_status { uint64_t u64; struct cvmx_uctlx_uphy_portx_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint64_t reserved_43_63:21; uint64_t tdata_out:4; uint64_t txbiststuffenh:1; @@ -253,9 +440,36 @@ union cvmx_uctlx_uphy_portx_ctl_status { uint64_t tdata_sel:1; uint64_t taddr_in:4; uint64_t tdata_in:8; +#else + uint64_t tdata_in:8; + uint64_t taddr_in:4; + uint64_t tdata_sel:1; + uint64_t tclk:1; + uint64_t loop_en:1; + uint64_t compdistune:3; + uint64_t sqrxtune:3; + uint64_t txfslstune:4; + uint64_t txpreemphasistune:1; + uint64_t txrisetune:1; + uint64_t txvreftune:4; + uint64_t txhsvxtune:2; + uint64_t portreset:1; + uint64_t vbusvldext:1; + uint64_t dppulldown:1; + uint64_t dmpulldown:1; + uint64_t txbiststuffen:1; + uint64_t txbiststuffenh:1; + uint64_t tdata_out:4; + uint64_t reserved_43_63:21; +#endif } s; + struct cvmx_uctlx_uphy_portx_ctl_status_s cn61xx; struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx; struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1; + struct cvmx_uctlx_uphy_portx_ctl_status_s cn66xx; + struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xx; + struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xxp1; + struct cvmx_uctlx_uphy_portx_ctl_status_s cnf71xx; }; #endif diff --git a/arch/mips/include/asm/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h index 653610953d2..aa0d3d0de75 100644 --- a/arch/mips/include/asm/octeon/cvmx-wqe.h +++ b/arch/mips/include/asm/octeon/cvmx-wqe.h @@ -40,7 +40,7 @@ #ifndef __CVMX_WQE_H__ #define __CVMX_WQE_H__ -#include "cvmx-packet.h" +#include <asm/octeon/cvmx-packet.h> #define OCT_TAG_TYPE_STRING(x) \ @@ -101,23 +101,23 @@ typedef union { * - 1 = Malformed L4 * - 2 = L4 Checksum Error: the L4 checksum value is * - 3 = UDP Length Error: The UDP length field would - * make the UDP data longer than what remains in - * the IP packet (as defined by the IP header - * length field). + * make the UDP data longer than what remains in + * the IP packet (as defined by the IP header + * length field). * - 4 = Bad L4 Port: either the source or destination - * TCP/UDP port is 0. + * TCP/UDP port is 0. * - 8 = TCP FIN Only: the packet is TCP and only the - * FIN flag set. + * FIN flag set. * - 9 = TCP No Flags: the packet is TCP and no flags - * are set. + * are set. * - 10 = TCP FIN RST: the packet is TCP and both FIN - * and RST are set. + * and RST are set. * - 11 = TCP SYN URG: the packet is TCP and both SYN - * and URG are set. + * and URG are set. * - 12 = TCP SYN RST: the packet is TCP and both SYN - * and RST are set. + * and RST are set. * - 13 = TCP SYN FIN: the packet is TCP and both SYN - * and FIN are set. + * and FIN are set. */ uint64_t L4_error:1; /* set if the packet is a fragment */ @@ -127,16 +127,16 @@ typedef union { * failure indicated in err_code below, decode: * * - 1 = Not IP: the IP version field is neither 4 nor - * 6. + * 6. * - 2 = IPv4 Header Checksum Error: the IPv4 header - * has a checksum violation. + * has a checksum violation. * - 3 = IP Malformed Header: the packet is not long - * enough to contain the IP header. + * enough to contain the IP header. * - 4 = IP Malformed: the packet is not long enough * to contain the bytes indicated by the IP * header. Pad is allowed. * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 - * Hop Count field are zero. + * Hop Count field are zero. * - 6 = IP Options */ uint64_t IP_exc:1; @@ -243,46 +243,46 @@ typedef union { * decode: * * - 1 = partial error: a packet was partially - * received, but internal buffering / bandwidth - * was not adequate to receive the entire - * packet. + * received, but internal buffering / bandwidth + * was not adequate to receive the entire + * packet. * - 2 = jabber error: the RGMII packet was too large - * and is truncated. + * and is truncated. * - 3 = overrun error: the RGMII packet is longer - * than allowed and had an FCS error. + * than allowed and had an FCS error. * - 4 = oversize error: the RGMII packet is longer - * than allowed. + * than allowed. * - 5 = alignment error: the RGMII packet is not an - * integer number of bytes - * and had an FCS error (100M and 10M only). + * integer number of bytes + * and had an FCS error (100M and 10M only). * - 6 = fragment error: the RGMII packet is shorter - * than allowed and had an FCS error. + * than allowed and had an FCS error. * - 7 = GMX FCS error: the RGMII packet had an FCS - * error. + * error. * - 8 = undersize error: the RGMII packet is shorter - * than allowed. + * than allowed. * - 9 = extend error: the RGMII packet had an extend - * error. + * error. * - 10 = length mismatch error: the RGMII packet had - * a length that did not match the length field - * in the L2 HDR. + * a length that did not match the length field + * in the L2 HDR. * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII - * packet had one or more data reception errors - * (RXERR) or the SPI4 packet had one or more - * DIP4 errors. + * packet had one or more data reception errors + * (RXERR) or the SPI4 packet had one or more + * DIP4 errors. * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII - * packet was not large enough to cover the - * skipped bytes or the SPI4 packet was - * terminated with an About EOPS. + * packet was not large enough to cover the + * skipped bytes or the SPI4 packet was + * terminated with an About EOPS. * - 13 = RGMII nibble error/SPI4 Port NXA Error: the - * RGMII packet had a studder error (data not - * repeated - 10/100M only) or the SPI4 packet - * was sent to an NXA. + * RGMII packet had a studder error (data not + * repeated - 10/100M only) or the SPI4 packet + * was sent to an NXA. * - 16 = FCS error: a SPI4.2 packet had an FCS error. * - 17 = Skip error: a packet was not large enough to - * cover the skipped bytes. + * cover the skipped bytes. * - 18 = L2 header malformed: the packet is not long - * enough to contain the L2. + * enough to contain the L2. */ uint64_t rcv_error:1; @@ -309,7 +309,7 @@ typedef struct { /***************************************************************** * WORD 0 - * HW WRITE: the following 64 bits are filled by HW when a packet arrives + * HW WRITE: the following 64 bits are filled by HW when a packet arrives */ /** @@ -323,14 +323,14 @@ typedef struct { /** * Next pointer used by hardware for list maintenance. * May be written/read by HW before the work queue - * entry is scheduled to a PP + * entry is scheduled to a PP * (Only 36 bits used in Octeon 1) */ uint64_t next_ptr:40; /***************************************************************** * WORD 1 - * HW WRITE: the following 64 bits are filled by HW when a packet arrives + * HW WRITE: the following 64 bits are filled by HW when a packet arrives */ /** @@ -362,8 +362,8 @@ typedef struct { /** * WORD 2 HW WRITE: the following 64-bits are filled in by - * hardware when a packet arrives This indicates a variety of - * status and error conditions. + * hardware when a packet arrives This indicates a variety of + * status and error conditions. */ cvmx_pip_wqe_word2 word2; @@ -373,15 +373,15 @@ typedef struct { union cvmx_buf_ptr packet_ptr; /** - * HW WRITE: octeon will fill in a programmable amount from the - * packet, up to (at most, but perhaps less) the amount - * needed to fill the work queue entry to 128 bytes + * HW WRITE: octeon will fill in a programmable amount from the + * packet, up to (at most, but perhaps less) the amount + * needed to fill the work queue entry to 128 bytes * - * If the packet is recognized to be IP, the hardware starts - * (except that the IPv4 header is padded for appropriate - * alignment) writing here where the IP header starts. If the - * packet is not recognized to be IP, the hardware starts - * writing the beginning of the packet here. + * If the packet is recognized to be IP, the hardware starts + * (except that the IPv4 header is padded for appropriate + * alignment) writing here where the IP header starts. If the + * packet is not recognized to be IP, the hardware starts + * writing the beginning of the packet here. */ uint8_t packet_data[96]; diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h index 740be97a325..f991e7701d3 100644 --- a/arch/mips/include/asm/octeon/cvmx.h +++ b/arch/mips/include/asm/octeon/cvmx.h @@ -52,38 +52,38 @@ enum cvmx_mips_space { #define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) #endif -#include "cvmx-asm.h" -#include "cvmx-packet.h" -#include "cvmx-sysinfo.h" - -#include "cvmx-ciu-defs.h" -#include "cvmx-gpio-defs.h" -#include "cvmx-iob-defs.h" -#include "cvmx-ipd-defs.h" -#include "cvmx-l2c-defs.h" -#include "cvmx-l2d-defs.h" -#include "cvmx-l2t-defs.h" -#include "cvmx-led-defs.h" -#include "cvmx-mio-defs.h" -#include "cvmx-pow-defs.h" - -#include "cvmx-bootinfo.h" -#include "cvmx-bootmem.h" -#include "cvmx-l2c.h" +#include <asm/octeon/cvmx-asm.h> +#include <asm/octeon/cvmx-packet.h> +#include <asm/octeon/cvmx-sysinfo.h> + +#include <asm/octeon/cvmx-ciu-defs.h> +#include <asm/octeon/cvmx-gpio-defs.h> +#include <asm/octeon/cvmx-iob-defs.h> +#include <asm/octeon/cvmx-ipd-defs.h> +#include <asm/octeon/cvmx-l2c-defs.h> +#include <asm/octeon/cvmx-l2d-defs.h> +#include <asm/octeon/cvmx-l2t-defs.h> +#include <asm/octeon/cvmx-led-defs.h> +#include <asm/octeon/cvmx-mio-defs.h> +#include <asm/octeon/cvmx-pow-defs.h> + +#include <asm/octeon/cvmx-bootinfo.h> +#include <asm/octeon/cvmx-bootmem.h> +#include <asm/octeon/cvmx-l2c.h> #ifndef CVMX_ENABLE_DEBUG_PRINTS #define CVMX_ENABLE_DEBUG_PRINTS 1 #endif #if CVMX_ENABLE_DEBUG_PRINTS -#define cvmx_dprintf printk +#define cvmx_dprintf printk #else #define cvmx_dprintf(...) {} #endif -#define CVMX_MAX_CORES (16) -#define CVMX_CACHE_LINE_SIZE (128) /* In bytes */ -#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */ +#define CVMX_MAX_CORES (16) +#define CVMX_CACHE_LINE_SIZE (128) /* In bytes */ +#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */ #define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE))) #define CAST64(v) ((long long)(long)(v)) #define CASTPTR(type, v) ((type *)(long)(v)) @@ -133,8 +133,8 @@ static inline uint64_t cvmx_build_io_address(uint64_t major_did, * * Example: cvmx_build_bits(39,24,value) * <pre> - * 6 5 4 3 3 2 1 - * 3 5 7 9 1 3 5 7 0 + * 6 5 4 3 3 2 1 + * 3 5 7 9 1 3 5 7 0 * +-------+-------+-------+-------+-------+-------+-------+------+ * 000000000000000000000000___________value000000000000000000000000 * </pre> @@ -183,7 +183,7 @@ static inline uint64_t cvmx_ptr_to_phys(void *ptr) * memory pointer (void *). * * @physical_address: - * Hardware physical address to memory + * Hardware physical address to memory * Returns Pointer to memory */ static inline void *cvmx_phys_to_ptr(uint64_t physical_address) @@ -207,10 +207,10 @@ static inline void *cvmx_phys_to_ptr(uint64_t physical_address) /* We have a full 64bit ABI. Writing to a 64bit address can be done with a simple volatile pointer */ -#define CVMX_BUILD_WRITE64(TYPE, ST) \ -static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \ -{ \ - *CASTPTR(volatile TYPE##_t, addr) = val; \ +#define CVMX_BUILD_WRITE64(TYPE, ST) \ +static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \ +{ \ + *CASTPTR(volatile TYPE##_t, addr) = val; \ } @@ -221,19 +221,19 @@ static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \ /* We have a full 64bit ABI. Writing to a 64bit address can be done with a simple volatile pointer */ -#define CVMX_BUILD_READ64(TYPE, LT) \ -static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \ -{ \ +#define CVMX_BUILD_READ64(TYPE, LT) \ +static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \ +{ \ return *CASTPTR(volatile TYPE##_t, addr); \ } /* The following defines 8 functions for writing to a 64bit address. Each takes two arguments, the address and the value to write. - cvmx_write64_int64 cvmx_write64_uint64 - cvmx_write64_int32 cvmx_write64_uint32 - cvmx_write64_int16 cvmx_write64_uint16 - cvmx_write64_int8 cvmx_write64_uint8 */ + cvmx_write64_int64 cvmx_write64_uint64 + cvmx_write64_int32 cvmx_write64_uint32 + cvmx_write64_int16 cvmx_write64_uint16 + cvmx_write64_int8 cvmx_write64_uint8 */ CVMX_BUILD_WRITE64(int64, "sd"); CVMX_BUILD_WRITE64(int32, "sw"); CVMX_BUILD_WRITE64(int16, "sh"); @@ -246,10 +246,10 @@ CVMX_BUILD_WRITE64(uint8, "sb"); /* The following defines 8 functions for reading from a 64bit address. Each takes the address as the only argument - cvmx_read64_int64 cvmx_read64_uint64 - cvmx_read64_int32 cvmx_read64_uint32 - cvmx_read64_int16 cvmx_read64_uint16 - cvmx_read64_int8 cvmx_read64_uint8 */ + cvmx_read64_int64 cvmx_read64_uint64 + cvmx_read64_int32 cvmx_read64_uint32 + cvmx_read64_int16 cvmx_read64_uint16 + cvmx_read64_int8 cvmx_read64_uint8 */ CVMX_BUILD_READ64(int64, "ld"); CVMX_BUILD_READ64(int32, "lw"); CVMX_BUILD_READ64(int16, "lh"); @@ -389,7 +389,7 @@ static inline void cvmx_wait(uint64_t cycles) /** * Reads a chip global cycle counter. This counts CPU cycles since - * chip reset. The counter is 64 bit. + * chip reset. The counter is 64 bit. * This register does not exist on CN38XX pass 1 silicion * * Returns Global chip cycle count since chip reset. @@ -453,7 +453,7 @@ static inline uint32_t cvmx_octeon_num_cores(void) /** * Read a byte of fuse data - * @byte_addr: address to read + * @byte_addr: address to read * * Returns fuse value: 0 or 1 */ diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h index 8008da2f877..90e05a8d4b1 100644 --- a/arch/mips/include/asm/octeon/octeon-feature.h +++ b/arch/mips/include/asm/octeon/octeon-feature.h @@ -35,7 +35,7 @@ #include <asm/octeon/cvmx-rnm-defs.h> enum octeon_feature { - /* CN68XX uses port kinds for packet interface */ + /* CN68XX uses port kinds for packet interface */ OCTEON_FEATURE_PKND, /* CN68XX has different fields in word0 - word2 */ OCTEON_FEATURE_CN68XX_WQE, @@ -51,7 +51,7 @@ enum octeon_feature { OCTEON_FEATURE_DORM_CRYPTO, /* Does this Octeon support PCI express? */ OCTEON_FEATURE_PCIE, - /* Does this Octeon support SRIOs */ + /* Does this Octeon support SRIOs */ OCTEON_FEATURE_SRIO, /* Does this Octeon support Interlaken */ OCTEON_FEATURE_ILK, @@ -75,7 +75,7 @@ enum octeon_feature { /* Octeon MDIO block supports clause 45 transactions for 10 * Gig support */ OCTEON_FEATURE_MDIO_CLAUSE_45, - /* + /* * CN52XX and CN56XX used a block named NPEI for PCIe * access. Newer chips replaced this with SLI+DPI. */ @@ -94,10 +94,10 @@ static inline int cvmx_fuse_read(int fuse); * be kept out of fast path code. * * @feature: Feature to check for. This should always be a constant so the - * compiler can remove the switch statement through optimization. + * compiler can remove the switch statement through optimization. * * Returns Non zero if the feature exists. Zero if the feature does not - * exist. + * exist. */ static inline int octeon_has_feature(enum octeon_feature feature) { diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h index 4e338a4d942..e2c122c6a65 100644 --- a/arch/mips/include/asm/octeon/octeon-model.h +++ b/arch/mips/include/asm/octeon/octeon-model.h @@ -29,7 +29,7 @@ /* * The defines below should be used with the OCTEON_IS_MODEL() macro - * to determine what model of chip the software is running on. Models + * to determine what model of chip the software is running on. Models * ending in 'XX' match multiple models (families), while specific * models match only that model. If a pass (revision) is specified, * then only that revision will be matched. Care should be taken when @@ -40,173 +40,189 @@ * subject to change at anytime without notice. * * NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN* - * macros should be used outside of this file. All other macros are + * macros should be used outside of this file. All other macros are * for internal use only, and may change without notice. */ -#define OCTEON_FAMILY_MASK 0x00ffff00 +#define OCTEON_FAMILY_MASK 0x00ffff00 /* Flag bits in top byte */ /* Ignores revision in model checks */ -#define OM_IGNORE_REVISION 0x01000000 +#define OM_IGNORE_REVISION 0x01000000 /* Check submodels */ -#define OM_CHECK_SUBMODEL 0x02000000 +#define OM_CHECK_SUBMODEL 0x02000000 /* Match all models previous than the one specified */ #define OM_MATCH_PREVIOUS_MODELS 0x04000000 /* Ignores the minor revison on newer parts */ #define OM_IGNORE_MINOR_REVISION 0x08000000 -#define OM_FLAG_MASK 0xff000000 +#define OM_FLAG_MASK 0xff000000 /* Match all cn5XXX Octeon models. */ -#define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000 +#define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000 /* Match all cn6XXX Octeon models. */ -#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000 +#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000 +/* Match all cnf7XXX Octeon models. */ +#define OM_MATCH_F7XXX_FAMILY_MODELS 0x80000000 + +/* + * CNF7XXX models with new revision encoding + */ +#define OCTEON_CNF71XX_PASS1_0 0x000d9400 + +#define OCTEON_CNF71XX (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CNF71XX_PASS1_X (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) /* * CN6XXX models with new revision encoding */ -#define OCTEON_CN68XX_PASS1_0 0x000d9100 -#define OCTEON_CN68XX_PASS1_1 0x000d9101 -#define OCTEON_CN68XX_PASS1_2 0x000d9102 -#define OCTEON_CN68XX_PASS2_0 0x000d9108 +#define OCTEON_CN68XX_PASS1_0 0x000d9100 +#define OCTEON_CN68XX_PASS1_1 0x000d9101 +#define OCTEON_CN68XX_PASS1_2 0x000d9102 +#define OCTEON_CN68XX_PASS2_0 0x000d9108 -#define OCTEON_CN68XX (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION) -#define OCTEON_CN68XX_PASS1_X (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN68XX_PASS2_X (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN68XX (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION) +#define OCTEON_CN68XX_PASS1_X (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN68XX_PASS2_X (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) #define OCTEON_CN68XX_PASS1 OCTEON_CN68XX_PASS1_X #define OCTEON_CN68XX_PASS2 OCTEON_CN68XX_PASS2_X -#define OCTEON_CN66XX_PASS1_0 0x000d9200 -#define OCTEON_CN66XX_PASS1_2 0x000d9202 +#define OCTEON_CN66XX_PASS1_0 0x000d9200 +#define OCTEON_CN66XX_PASS1_2 0x000d9202 -#define OCTEON_CN66XX (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_REVISION) -#define OCTEON_CN66XX_PASS1_X (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN66XX (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN66XX_PASS1_X (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN63XX_PASS1_0 0x000d9000 -#define OCTEON_CN63XX_PASS1_1 0x000d9001 -#define OCTEON_CN63XX_PASS1_2 0x000d9002 -#define OCTEON_CN63XX_PASS2_0 0x000d9008 -#define OCTEON_CN63XX_PASS2_1 0x000d9009 -#define OCTEON_CN63XX_PASS2_2 0x000d900a +#define OCTEON_CN63XX_PASS1_0 0x000d9000 +#define OCTEON_CN63XX_PASS1_1 0x000d9001 +#define OCTEON_CN63XX_PASS1_2 0x000d9002 +#define OCTEON_CN63XX_PASS2_0 0x000d9008 +#define OCTEON_CN63XX_PASS2_1 0x000d9009 +#define OCTEON_CN63XX_PASS2_2 0x000d900a -#define OCTEON_CN63XX (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION) -#define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN63XX (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION) +#define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN61XX_PASS1_0 0x000d9300 +#define OCTEON_CN61XX_PASS1_0 0x000d9300 -#define OCTEON_CN61XX (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION) -#define OCTEON_CN61XX_PASS1_X (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN61XX (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN61XX_PASS1_X (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) /* * CN5XXX models with new revision encoding */ -#define OCTEON_CN58XX_PASS1_0 0x000d0300 -#define OCTEON_CN58XX_PASS1_1 0x000d0301 -#define OCTEON_CN58XX_PASS1_2 0x000d0303 -#define OCTEON_CN58XX_PASS2_0 0x000d0308 -#define OCTEON_CN58XX_PASS2_1 0x000d0309 -#define OCTEON_CN58XX_PASS2_2 0x000d030a -#define OCTEON_CN58XX_PASS2_3 0x000d030b - -#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION) -#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X -#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X - -#define OCTEON_CN56XX_PASS1_0 0x000d0400 -#define OCTEON_CN56XX_PASS1_1 0x000d0401 -#define OCTEON_CN56XX_PASS2_0 0x000d0408 -#define OCTEON_CN56XX_PASS2_1 0x000d0409 - -#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION) -#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X -#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X - -#define OCTEON_CN57XX OCTEON_CN56XX -#define OCTEON_CN57XX_PASS1 OCTEON_CN56XX_PASS1 -#define OCTEON_CN57XX_PASS2 OCTEON_CN56XX_PASS2 - -#define OCTEON_CN55XX OCTEON_CN56XX -#define OCTEON_CN55XX_PASS1 OCTEON_CN56XX_PASS1 -#define OCTEON_CN55XX_PASS2 OCTEON_CN56XX_PASS2 - -#define OCTEON_CN54XX OCTEON_CN56XX -#define OCTEON_CN54XX_PASS1 OCTEON_CN56XX_PASS1 -#define OCTEON_CN54XX_PASS2 OCTEON_CN56XX_PASS2 - -#define OCTEON_CN50XX_PASS1_0 0x000d0600 - -#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION) -#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X +#define OCTEON_CN58XX_PASS1_0 0x000d0300 +#define OCTEON_CN58XX_PASS1_1 0x000d0301 +#define OCTEON_CN58XX_PASS1_2 0x000d0303 +#define OCTEON_CN58XX_PASS2_0 0x000d0308 +#define OCTEON_CN58XX_PASS2_1 0x000d0309 +#define OCTEON_CN58XX_PASS2_2 0x000d030a +#define OCTEON_CN58XX_PASS2_3 0x000d030b + +#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X +#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X + +#define OCTEON_CN56XX_PASS1_0 0x000d0400 +#define OCTEON_CN56XX_PASS1_1 0x000d0401 +#define OCTEON_CN56XX_PASS2_0 0x000d0408 +#define OCTEON_CN56XX_PASS2_1 0x000d0409 + +#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION) +#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X +#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X + +#define OCTEON_CN57XX OCTEON_CN56XX +#define OCTEON_CN57XX_PASS1 OCTEON_CN56XX_PASS1 +#define OCTEON_CN57XX_PASS2 OCTEON_CN56XX_PASS2 + +#define OCTEON_CN55XX OCTEON_CN56XX +#define OCTEON_CN55XX_PASS1 OCTEON_CN56XX_PASS1 +#define OCTEON_CN55XX_PASS2 OCTEON_CN56XX_PASS2 + +#define OCTEON_CN54XX OCTEON_CN56XX +#define OCTEON_CN54XX_PASS1 OCTEON_CN56XX_PASS1 +#define OCTEON_CN54XX_PASS2 OCTEON_CN56XX_PASS2 + +#define OCTEON_CN50XX_PASS1_0 0x000d0600 + +#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X /* * NOTE: Octeon CN5000F model is not identifiable using the * OCTEON_IS_MODEL() functions, but are treated as CN50XX. */ -#define OCTEON_CN52XX_PASS1_0 0x000d0700 -#define OCTEON_CN52XX_PASS2_0 0x000d0708 +#define OCTEON_CN52XX_PASS1_0 0x000d0700 +#define OCTEON_CN52XX_PASS2_0 0x000d0708 -#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION) -#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X -#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X +#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION) +#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X +#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X /* * CN3XXX models with old revision enconding */ -#define OCTEON_CN38XX_PASS1 0x000d0000 -#define OCTEON_CN38XX_PASS2 0x000d0001 -#define OCTEON_CN38XX_PASS3 0x000d0003 -#define OCTEON_CN38XX (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION) +#define OCTEON_CN38XX_PASS1 0x000d0000 +#define OCTEON_CN38XX_PASS2 0x000d0001 +#define OCTEON_CN38XX_PASS3 0x000d0003 +#define OCTEON_CN38XX (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION) -#define OCTEON_CN36XX OCTEON_CN38XX -#define OCTEON_CN36XX_PASS2 OCTEON_CN38XX_PASS2 -#define OCTEON_CN36XX_PASS3 OCTEON_CN38XX_PASS3 +#define OCTEON_CN36XX OCTEON_CN38XX +#define OCTEON_CN36XX_PASS2 OCTEON_CN38XX_PASS2 +#define OCTEON_CN36XX_PASS3 OCTEON_CN38XX_PASS3 /* The OCTEON_CN31XX matches CN31XX models and the CN3020 */ -#define OCTEON_CN31XX_PASS1 0x000d0100 -#define OCTEON_CN31XX_PASS1_1 0x000d0102 -#define OCTEON_CN31XX (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION) +#define OCTEON_CN31XX_PASS1 0x000d0100 +#define OCTEON_CN31XX_PASS1_1 0x000d0102 +#define OCTEON_CN31XX (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION) /* * This model is only used for internal checks, it is not a valid * model for the OCTEON_MODEL environment variable. This matches the * CN3010 and CN3005 but NOT the CN3020. */ -#define OCTEON_CN30XX_PASS1 0x000d0200 -#define OCTEON_CN30XX_PASS1_1 0x000d0202 -#define OCTEON_CN30XX (OCTEON_CN30XX_PASS1 | OM_IGNORE_REVISION) +#define OCTEON_CN30XX_PASS1 0x000d0200 +#define OCTEON_CN30XX_PASS1_1 0x000d0202 +#define OCTEON_CN30XX (OCTEON_CN30XX_PASS1 | OM_IGNORE_REVISION) -#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) +#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) -#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) +#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) -#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) +#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) /* * This matches the complete family of CN3xxx CPUs, and not subsequent * models */ -#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION) -#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS) -#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS) +#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION) +#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS) +#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS) + +/* These are used to cover entire families of OCTEON processors */ +#define OCTEON_FAM_1 (OCTEON_CN3XXX) +#define OCTEON_FAM_PLUS (OCTEON_CN5XXX) +#define OCTEON_FAM_1_PLUS (OCTEON_FAM_PLUS | OM_MATCH_PREVIOUS_MODELS) +#define OCTEON_FAM_2 (OCTEON_CN6XXX) /* The revision byte (low byte) has two different encodings. * CN3XXX: @@ -227,18 +243,18 @@ */ /* Masks used for the various types of model/family/revision matching */ -#define OCTEON_38XX_FAMILY_MASK 0x00ffff00 +#define OCTEON_38XX_FAMILY_MASK 0x00ffff00 #define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f -#define OCTEON_38XX_MODEL_MASK 0x00ffff10 +#define OCTEON_38XX_MODEL_MASK 0x00ffff10 #define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK | OCTEON_38XX_MODEL_MASK) /* CN5XXX and later use different layout of bits in the revision ID field */ -#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK +#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK #define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f -#define OCTEON_58XX_MODEL_MASK 0x00ffffc0 +#define OCTEON_58XX_MODEL_MASK 0x00ffffc0 #define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK) #define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00fffff8) -#define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0 +#define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0 /* forward declarations */ static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure)); @@ -248,7 +264,7 @@ static inline uint64_t cvmx_read_csr(uint64_t csr_addr); /* NOTE: This for internal use only! */ #define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model) \ -((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) && ( \ +((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) && ( \ ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \ && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_MASK)) || \ ((((arg_model) & (OM_FLAG_MASK)) == 0) \ @@ -260,7 +276,7 @@ static inline uint64_t cvmx_read_csr(uint64_t csr_addr); ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \ && (((chip_model) & OCTEON_38XX_MODEL_MASK) < ((arg_model) & OCTEON_38XX_MODEL_MASK))) \ )) || \ - (((arg_model & OCTEON_38XX_FAMILY_MASK) >= OCTEON_CN58XX_PASS1_0) && ( \ + (((arg_model & OCTEON_38XX_FAMILY_MASK) >= OCTEON_CN58XX_PASS1_0) && ( \ ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \ && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \ ((((arg_model) & (OM_FLAG_MASK)) == 0) \ @@ -304,7 +320,7 @@ static inline int __octeon_is_model_runtime__(uint32_t model) * Use of the macro in preprocessor directives ( #if OCTEON_IS_MODEL(...) ) * is NOT SUPPORTED, and should be replaced with CVMX_COMPILED_FOR() * I.e.: - * #if OCTEON_IS_MODEL(OCTEON_CN56XX) -> #if CVMX_COMPILED_FOR(OCTEON_CN56XX) + * #if OCTEON_IS_MODEL(OCTEON_CN56XX) -> #if CVMX_COMPILED_FOR(OCTEON_CN56XX) */ #define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x) #define OCTEON_IS_COMMON_BINARY() 1 @@ -313,6 +329,14 @@ static inline int __octeon_is_model_runtime__(uint32_t model) const char *octeon_model_get_string(uint32_t chip_id); const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer); -#include "octeon-feature.h" +/* + * Return the octeon family, i.e., ProcessorID of the PrID register. + */ +static inline uint32_t cvmx_get_octeon_family(void) +{ + return cvmx_get_proc_id() & OCTEON_FAMILY_MASK; +} + +#include <asm/octeon/octeon-feature.h> #endif /* __OCTEON_MODEL_H__ */ diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index f72f768cd3a..d781f9e6688 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -8,7 +8,7 @@ #ifndef __ASM_OCTEON_OCTEON_H #define __ASM_OCTEON_OCTEON_H -#include "cvmx.h" +#include <asm/octeon/cvmx.h> extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size, uint64_t alignment, @@ -52,6 +52,7 @@ extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task); extern void octeon_init_cvmcount(void); extern void octeon_setup_delays(void); +extern void octeon_io_clk_delay(unsigned long); #define OCTEON_ARGV_MAX_ARGS 64 #define OCTOEN_SERIAL_LEN 20 @@ -74,15 +75,15 @@ struct octeon_boot_descriptor { uint32_t argc; uint32_t argv[OCTEON_ARGV_MAX_ARGS]; -#define BOOT_FLAG_INIT_CORE (1 << 0) -#define OCTEON_BL_FLAG_DEBUG (1 << 1) -#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2) +#define BOOT_FLAG_INIT_CORE (1 << 0) +#define OCTEON_BL_FLAG_DEBUG (1 << 1) +#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2) /* If set, use uart1 for console */ -#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3) +#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3) /* If set, use PCI console */ -#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4) +#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4) /* Call exit on break on serial port */ -#define OCTEON_BL_FLAG_BREAK (1 << 5) +#define OCTEON_BL_FLAG_BREAK (1 << 5) uint32_t flags; uint32_t core_mask; @@ -208,21 +209,8 @@ union octeon_cvmemctl { } s; }; -struct octeon_cf_data { - unsigned long base_region_bias; - unsigned int base_region; /* The chip select region used by CF */ - int is16bit; /* 0 - 8bit, !0 - 16bit */ - int dma_engine; /* -1 for no DMA */ -}; - -struct octeon_i2c_data { - unsigned int sys_freq; - unsigned int i2c_freq; -}; - extern void octeon_write_lcd(const char *s); extern void octeon_check_cpu_bist(void); -extern int octeon_get_boot_debug_flag(void); extern int octeon_get_boot_uart(void); struct uart_port; @@ -259,4 +247,9 @@ extern uint64_t octeon_bootloader_entry_addr; extern void (*octeon_irq_setup_secondary)(void); +typedef void (*octeon_irq_ip4_handler_t)(void); +void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t); + +extern void octeon_fixup_irqs(void); + #endif /* __ASM_OCTEON_OCTEON_H */ diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h index c66734bd338..64ba56a0284 100644 --- a/arch/mips/include/asm/octeon/pci-octeon.h +++ b/arch/mips/include/asm/octeon/pci-octeon.h @@ -22,7 +22,7 @@ #define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28) /* - * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2, + * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2, * place BAR1 so it is the same for both. */ #define CVMX_PCIE_BAR1_RC_BASE (1ull << 41) |