diff options
Diffstat (limited to 'arch/mips/include/asm/mach-db1x00')
| -rw-r--r-- | arch/mips/include/asm/mach-db1x00/bcsr.h | 40 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-db1x00/db1200.h | 86 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-db1x00/db1x00.h | 79 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-db1x00/irq.h | 23 |
4 files changed, 54 insertions, 174 deletions
diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h index 618d2de02ed..3c3ed4ae45e 100644 --- a/arch/mips/include/asm/mach-db1x00/bcsr.h +++ b/arch/mips/include/asm/mach-db1x00/bcsr.h @@ -34,6 +34,8 @@ #define PB1200_BCSR_PHYS_ADDR 0x0D800000 #define PB1200_BCSR_HEXLED_OFS 0x00400000 +#define DB1300_BCSR_PHYS_ADDR 0x19800000 +#define DB1300_BCSR_HEXLED_OFS 0x00400000 enum bcsr_id { /* BCSR base 1 */ @@ -105,9 +107,10 @@ enum bcsr_whoami_boards { BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1, BCSR_WHOAMI_PB1200_DDR2, BCSR_WHOAMI_DB1200, + BCSR_WHOAMI_DB1300, }; -/* STATUS reg. Unless otherwise noted, they're valid on all boards. +/* STATUS reg. Unless otherwise noted, they're valid on all boards. * PB1200 = DB1200. */ #define BCSR_STATUS_PC0VS 0x0003 @@ -118,12 +121,12 @@ enum bcsr_whoami_boards { #define BCSR_STATUS_SRAMWIDTH 0x0080 #define BCSR_STATUS_FLASHBUSY 0x0100 #define BCSR_STATUS_ROMBUSY 0x0400 -#define BCSR_STATUS_SD0WP 0x0400 /* DB1200 */ +#define BCSR_STATUS_SD0WP 0x0400 /* DB1200/DB1300:SD1 */ #define BCSR_STATUS_SD1WP 0x0800 #define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */ #define BCSR_STATUS_DB1000_SWAPBOOT 0x2000 -#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200 */ -#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200 */ +#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200/1300 */ +#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200/1300 */ #define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */ #define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */ #define BCSR_STATUS_FLASHDEN 0xC000 @@ -133,6 +136,11 @@ enum bcsr_whoami_boards { #define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */ #define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */ +#define BCSR_STATUS_CFWP 0x4000 /* DB1300 */ +#define BCSR_STATUS_USBOCn 0x2000 /* DB1300 */ +#define BCSR_STATUS_OTGOCn 0x1000 /* DB1300 */ +#define BCSR_STATUS_DCDMARQ 0x0010 /* DB1300 */ +#define BCSR_STATUS_IDEDMARQ 0x0020 /* DB1300 */ /* DB/PB1000,1100,1500,1550 */ #define BCSR_RESETS_PHY0 0x0001 @@ -154,18 +162,20 @@ enum bcsr_whoami_boards { #define BCSR_BOARD_PCIEXTARB 0x0200 #define BCSR_BOARD_GPIO200RST 0x0400 #define BCSR_BOARD_PCICLKOUT 0x0800 +#define BCSR_BOARD_PB1100_SD0PWR 0x0400 +#define BCSR_BOARD_PB1100_SD1PWR 0x0800 #define BCSR_BOARD_PCICFG 0x1000 -#define BCSR_BOARD_SPISEL 0x4000 /* PB/DB1550 */ +#define BCSR_BOARD_SPISEL 0x2000 /* PB/DB1550 */ #define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */ #define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ -/* DB/PB1200 */ +/* DB/PB1200/1300 */ #define BCSR_RESETS_ETH 0x0001 #define BCSR_RESETS_CAMERA 0x0002 #define BCSR_RESETS_DC 0x0004 #define BCSR_RESETS_IDE 0x0008 -#define BCSR_RESETS_TV 0x0010 /* DB1200 */ +#define BCSR_RESETS_TV 0x0010 /* DB1200/1300 */ /* Not resets but in the same register */ #define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */ #define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */ @@ -174,13 +184,22 @@ enum bcsr_whoami_boards { #define BCSR_RESETS_SPISEL 0x4000 #define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */ +#define BCSR_RESETS_VDDQSHDN 0x0200 /* DB1300 */ +#define BCSR_RESETS_OTPPGM 0x0400 /* DB1300 */ +#define BCSR_RESETS_OTPSCLK 0x0800 /* DB1300 */ +#define BCSR_RESETS_OTPWRPROT 0x1000 /* DB1300 */ +#define BCSR_RESETS_OTPCSB 0x2000 /* DB1300 */ +#define BCSR_RESETS_OTGPWR 0x4000 /* DB1300 */ +#define BCSR_RESETS_USBHPWR 0x8000 /* DB1300 */ + #define BCSR_BOARD_LCDVEE 0x0001 #define BCSR_BOARD_LCDVDD 0x0002 #define BCSR_BOARD_LCDBL 0x0004 #define BCSR_BOARD_CAMSNAP 0x0010 #define BCSR_BOARD_CAMPWR 0x0020 #define BCSR_BOARD_SD0PWR 0x0040 - +#define BCSR_BOARD_CAMCS 0x0010 /* DB1300 */ +#define BCSR_BOARD_HDMI_DE 0x0040 /* DB1300 */ #define BCSR_SWITCHES_DIP 0x00FF #define BCSR_SWITCHES_DIP_1 0x0080 @@ -214,7 +233,10 @@ enum bcsr_whoami_boards { #define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */ #define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */ #define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */ - +#define BCSR_SYSTEM_DEBUGCSMASK 0x003F /* DB1300 */ +#define BCSR_SYSTEM_UDMAMODE 0x0100 /* DB1300 */ +#define BCSR_SYSTEM_WAKEONIRQ 0x0200 /* DB1300 */ +#define BCSR_SYSTEM_VDDI1300 0x3C00 /* DB1300 */ diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h deleted file mode 100644 index 3404248f509..00000000000 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * AMD Alchemy DBAu1200 Reference Board - * Board register defines. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_DB1200_H -#define __ASM_DB1200_H - -#include <linux/types.h> -#include <asm/mach-au1x00/au1000.h> -#include <asm/mach-au1x00/au1xxx_psc.h> - -/* Bit positions for the different interrupt sources */ -#define BCSR_INT_IDE 0x0001 -#define BCSR_INT_ETH 0x0002 -#define BCSR_INT_PC0 0x0004 -#define BCSR_INT_PC0STSCHG 0x0008 -#define BCSR_INT_PC1 0x0010 -#define BCSR_INT_PC1STSCHG 0x0020 -#define BCSR_INT_DC 0x0040 -#define BCSR_INT_FLASHBUSY 0x0080 -#define BCSR_INT_PC0INSERT 0x0100 -#define BCSR_INT_PC0EJECT 0x0200 -#define BCSR_INT_PC1INSERT 0x0400 -#define BCSR_INT_PC1EJECT 0x0800 -#define BCSR_INT_SD0INSERT 0x1000 -#define BCSR_INT_SD0EJECT 0x2000 - -#define IDE_PHYS_ADDR 0x18800000 -#define IDE_REG_SHIFT 5 -#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 -#define IDE_RQSIZE 128 - -#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR -#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) -#define DB1200_ETH_PHYS_ADDR 0x19000300 -#define DB1200_NAND_PHYS_ADDR 0x20000000 - -/* - * External Interrupts for DBAu1200 as of 8/6/2004. - * Bit positions in the CPLD registers can be calculated by taking - * the interrupt define and subtracting the DB1200_INT_BEGIN value. - * - * Example: IDE bis pos is = 64 - 64 - * ETH bit pos is = 65 - 64 - */ -enum external_db1200_ints { - DB1200_INT_BEGIN = AU1000_MAX_INTR + 1, - - DB1200_IDE_INT = DB1200_INT_BEGIN, - DB1200_ETH_INT, - DB1200_PC0_INT, - DB1200_PC0_STSCHG_INT, - DB1200_PC1_INT, - DB1200_PC1_STSCHG_INT, - DB1200_DC_INT, - DB1200_FLASHBUSY_INT, - DB1200_PC0_INSERT_INT, - DB1200_PC0_EJECT_INT, - DB1200_PC1_INSERT_INT, - DB1200_PC1_EJECT_INT, - DB1200_SD0_INSERT_INT, - DB1200_SD0_EJECT_INT, - - DB1200_INT_END = DB1200_INT_BEGIN + 15, -}; - -#endif /* __ASM_DB1200_H */ diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h deleted file mode 100644 index a919dac525a..00000000000 --- a/arch/mips/include/asm/mach-db1x00/db1x00.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * AMD Alchemy DBAu1x00 Reference Boards - * - * Copyright 2001, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. <source@mvista.com> - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ -#ifndef __ASM_DB1X00_H -#define __ASM_DB1X00_H - -#include <asm/mach-au1x00/au1xxx_psc.h> - -#ifdef CONFIG_MIPS_DB1550 - -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX - -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define AC97_PSC_BASE PSC1_BASE_ADDR -#define SMBUS_PSC_BASE PSC2_BASE_ADDR -#define I2S_PSC_BASE PSC3_BASE_ADDR - -#define NAND_PHYS_ADDR 0x20000000 - -#endif - -/* - * NAND defines - * - * Timing values as described in databook, * ns value stripped of the - * lower 2 bits. - * These defines are here rather than an Au1550 generic file because - * the parts chosen on another board may be different and may require - * different timings. - */ -#define NAND_T_H (18 >> 2) -#define NAND_T_PUL (30 >> 2) -#define NAND_T_SU (30 >> 2) -#define NAND_T_WH (30 >> 2) - -/* Bitfield shift amounts */ -#define NAND_T_H_SHIFT 0 -#define NAND_T_PUL_SHIFT 4 -#define NAND_T_SU_SHIFT 8 -#define NAND_T_WH_SHIFT 12 - -#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ - ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ - ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ - ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)) -#define NAND_CS 1 - -/* Should be done by YAMON */ -#define NAND_STCFG 0x00400005 /* 8-bit NAND */ -#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */ -#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ - -#endif /* __ASM_DB1X00_H */ diff --git a/arch/mips/include/asm/mach-db1x00/irq.h b/arch/mips/include/asm/mach-db1x00/irq.h new file mode 100644 index 00000000000..15b26693238 --- /dev/null +++ b/arch/mips/include/asm/mach-db1x00/irq.h @@ -0,0 +1,23 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_GENERIC_IRQ_H +#define __ASM_MACH_GENERIC_IRQ_H + + +#ifdef NR_IRQS +#undef NR_IRQS +#endif + +#ifndef MIPS_CPU_IRQ_BASE +#define MIPS_CPU_IRQ_BASE 0 +#endif + +/* 8 (MIPS) + 128 (au1300) + 16 (cpld) */ +#define NR_IRQS 152 + +#endif /* __ASM_MACH_GENERIC_IRQ_H */ |