diff options
Diffstat (limited to 'arch/mips/include/asm/mach-au1x00')
18 files changed, 2149 insertions, 1501 deletions
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 62f91f50b5b..b4c3ecb17d4 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -43,6 +43,8 @@ #include <linux/io.h> #include <linux/irq.h> +#include <asm/cpu.h> + /* cpu pipeline flush */ void static inline au_sync(void) { @@ -130,6 +132,114 @@ static inline int au1xxx_cpu_needs_config_od(void) return 0; } +#define ALCHEMY_CPU_UNKNOWN -1 +#define ALCHEMY_CPU_AU1000 0 +#define ALCHEMY_CPU_AU1500 1 +#define ALCHEMY_CPU_AU1100 2 +#define ALCHEMY_CPU_AU1550 3 +#define ALCHEMY_CPU_AU1200 4 +#define ALCHEMY_CPU_AU1300 5 + +static inline int alchemy_get_cputype(void) +{ + switch (read_c0_prid() & (PRID_OPT_MASK | PRID_COMP_MASK)) { + case 0x00030000: + return ALCHEMY_CPU_AU1000; + break; + case 0x01030000: + return ALCHEMY_CPU_AU1500; + break; + case 0x02030000: + return ALCHEMY_CPU_AU1100; + break; + case 0x03030000: + return ALCHEMY_CPU_AU1550; + break; + case 0x04030000: + case 0x05030000: + return ALCHEMY_CPU_AU1200; + break; + case 0x800c0000: + return ALCHEMY_CPU_AU1300; + break; + } + + return ALCHEMY_CPU_UNKNOWN; +} + +/* return number of uarts on a given cputype */ +static inline int alchemy_get_uarts(int type) +{ + switch (type) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1300: + return 4; + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1200: + return 2; + case ALCHEMY_CPU_AU1100: + case ALCHEMY_CPU_AU1550: + return 3; + } + return 0; +} + +/* enable an UART block if it isn't already */ +static inline void alchemy_uart_enable(u32 uart_phys) +{ + void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys); + + /* reset, enable clock, deassert reset */ + if ((__raw_readl(addr + 0x100) & 3) != 3) { + __raw_writel(0, addr + 0x100); + wmb(); + __raw_writel(1, addr + 0x100); + wmb(); + } + __raw_writel(3, addr + 0x100); + wmb(); +} + +static inline void alchemy_uart_disable(u32 uart_phys) +{ + void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys); + __raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */ + wmb(); +} + +static inline void alchemy_uart_putchar(u32 uart_phys, u8 c) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys); + int timeout, i; + + /* check LSR TX_EMPTY bit */ + timeout = 0xffffff; + do { + if (__raw_readl(base + 0x1c) & 0x20) + break; + /* slow down */ + for (i = 10000; i; i--) + asm volatile ("nop"); + } while (--timeout); + + __raw_writel(c, base + 0x04); /* tx */ + wmb(); +} + +/* return number of ethernet MACs on a given cputype */ +static inline int alchemy_get_macs(int type) +{ + switch (type) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1550: + return 2; + case ALCHEMY_CPU_AU1100: + return 1; + } + return 0; +} + /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); @@ -138,428 +248,124 @@ extern unsigned long get_au1x00_uart_baud_base(void); extern unsigned long au1xxx_calc_clock(void); /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ -void au1xxx_save_and_sleep(void); +void alchemy_sleep_au1000(void); +void alchemy_sleep_au1550(void); +void alchemy_sleep_au1300(void); void au_sleep(void); -void save_au1xxx_intctl(void); -void restore_au1xxx_intctl(void); -/* - * Every board describes its IRQ mapping with this table. - */ -struct au1xxx_irqmap { - int im_irq; - int im_type; - int im_request; +/* USB: drivers/usb/host/alchemy-common.c */ +enum alchemy_usb_block { + ALCHEMY_USB_OHCI0, + ALCHEMY_USB_UDC0, + ALCHEMY_USB_EHCI0, + ALCHEMY_USB_OTG0, + ALCHEMY_USB_OHCI1, +}; +int alchemy_usb_control(int block, int enable); + +/* PCI controller platform data */ +struct alchemy_pci_platdata { + int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin); + int (*board_pci_idsel)(unsigned int devsel, int assert); + /* bits to set/clear in PCI_CONFIG register */ + unsigned long pci_cfg_set; + unsigned long pci_cfg_clr; }; -/* core calls this function to let boards initialize other IRQ sources */ -void board_init_irq(void); - -/* boards call this to register additional (GPIO) interrupts */ -void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count); - -#endif /* !defined (_LANGUAGE_ASSEMBLY) */ - -/* - * SDRAM register offsets - */ -#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \ - defined(CONFIG_SOC_AU1100) -#define MEM_SDMODE0 0x0000 -#define MEM_SDMODE1 0x0004 -#define MEM_SDMODE2 0x0008 -#define MEM_SDADDR0 0x000C -#define MEM_SDADDR1 0x0010 -#define MEM_SDADDR2 0x0014 -#define MEM_SDREFCFG 0x0018 -#define MEM_SDPRECMD 0x001C -#define MEM_SDAUTOREF 0x0020 -#define MEM_SDWRMD0 0x0024 -#define MEM_SDWRMD1 0x0028 -#define MEM_SDWRMD2 0x002C -#define MEM_SDSLEEP 0x0030 -#define MEM_SDSMCKE 0x0034 - -/* - * MEM_SDMODE register content definitions - */ -#define MEM_SDMODE_F (1 << 22) -#define MEM_SDMODE_SR (1 << 21) -#define MEM_SDMODE_BS (1 << 20) -#define MEM_SDMODE_RS (3 << 18) -#define MEM_SDMODE_CS (7 << 15) -#define MEM_SDMODE_TRAS (15 << 11) -#define MEM_SDMODE_TMRD (3 << 9) -#define MEM_SDMODE_TWR (3 << 7) -#define MEM_SDMODE_TRP (3 << 5) -#define MEM_SDMODE_TRCD (3 << 3) -#define MEM_SDMODE_TCL (7 << 0) - -#define MEM_SDMODE_BS_2Bank (0 << 20) -#define MEM_SDMODE_BS_4Bank (1 << 20) -#define MEM_SDMODE_RS_11Row (0 << 18) -#define MEM_SDMODE_RS_12Row (1 << 18) -#define MEM_SDMODE_RS_13Row (2 << 18) -#define MEM_SDMODE_RS_N(N) ((N) << 18) -#define MEM_SDMODE_CS_7Col (0 << 15) -#define MEM_SDMODE_CS_8Col (1 << 15) -#define MEM_SDMODE_CS_9Col (2 << 15) -#define MEM_SDMODE_CS_10Col (3 << 15) -#define MEM_SDMODE_CS_11Col (4 << 15) -#define MEM_SDMODE_CS_N(N) ((N) << 15) -#define MEM_SDMODE_TRAS_N(N) ((N) << 11) -#define MEM_SDMODE_TMRD_N(N) ((N) << 9) -#define MEM_SDMODE_TWR_N(N) ((N) << 7) -#define MEM_SDMODE_TRP_N(N) ((N) << 5) -#define MEM_SDMODE_TRCD_N(N) ((N) << 3) -#define MEM_SDMODE_TCL_N(N) ((N) << 0) - -/* - * MEM_SDADDR register contents definitions - */ -#define MEM_SDADDR_E (1 << 20) -#define MEM_SDADDR_CSBA (0x03FF << 10) -#define MEM_SDADDR_CSMASK (0x03FF << 0) -#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) -#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) - -/* - * MEM_SDREFCFG register content definitions - */ -#define MEM_SDREFCFG_TRC (15 << 28) -#define MEM_SDREFCFG_TRPM (3 << 26) -#define MEM_SDREFCFG_E (1 << 25) -#define MEM_SDREFCFG_RE (0x1ffffff << 0) -#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) -#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) -#define MEM_SDREFCFG_REF_N(N) (N) -#endif - -/***********************************************************************/ - -/* - * Au1550 SDRAM Register Offsets +/* Multifunction pins: Each of these pins can either be assigned to the + * GPIO controller or a on-chip peripheral. + * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to + * assign one of these to either the GPIO controller or the device. */ +enum au1300_multifunc_pins { + /* wake-from-str pins 0-3 */ + AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2, + AU1300_PIN_WAKE3, + /* external clock sources for PSCs: 4-5 */ + AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1, + /* 8bit MMC interface on SD0: 6-9 */ + AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, + AU1300_PIN_SD0DAT7, + /* aux clk input for freqgen 3: 10 */ + AU1300_PIN_FG3AUX, + /* UART1 pins: 11-18 */ + AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, + AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, + AU1300_PIN_U1RX, AU1300_PIN_U1TX, + /* UART0 pins: 19-24 */ + AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, + AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, + /* UART2: 25-26 */ + AU1300_PIN_U2RX, AU1300_PIN_U2TX, + /* UART3: 27-28 */ + AU1300_PIN_U3RX, AU1300_PIN_U3TX, + /* LCD controller PWMs, ext pixclock: 29-31 */ + AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, + /* SD1 interface: 32-37 */ + AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, + AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, + /* SD2 interface: 38-43 */ + AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, + AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, + /* PSC0/1 clocks: 44-45 */ + AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, + /* PSCs: 46-49/50-53/54-57/58-61 */ + AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, + AU1300_PIN_PSC0D1, + AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, + AU1300_PIN_PSC1D1, + AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0, + AU1300_PIN_PSC2D1, + AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, + AU1300_PIN_PSC3D1, + /* PCMCIA interface: 62-70 */ + AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, + AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, + AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, + /* camera interface H/V sync inputs: 71-72 */ + AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, + /* PSC2/3 clocks: 73-74 */ + AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, +}; -/***********************************************************************/ - -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) -#define MEM_SDMODE0 0x0800 -#define MEM_SDMODE1 0x0808 -#define MEM_SDMODE2 0x0810 -#define MEM_SDADDR0 0x0820 -#define MEM_SDADDR1 0x0828 -#define MEM_SDADDR2 0x0830 -#define MEM_SDCONFIGA 0x0840 -#define MEM_SDCONFIGB 0x0848 -#define MEM_SDSTAT 0x0850 -#define MEM_SDERRADDR 0x0858 -#define MEM_SDSTRIDE0 0x0860 -#define MEM_SDSTRIDE1 0x0868 -#define MEM_SDSTRIDE2 0x0870 -#define MEM_SDWRMD0 0x0880 -#define MEM_SDWRMD1 0x0888 -#define MEM_SDWRMD2 0x0890 -#define MEM_SDPRECMD 0x08C0 -#define MEM_SDAUTOREF 0x08C8 -#define MEM_SDSREF 0x08D0 -#define MEM_SDSLEEP MEM_SDSREF - -#endif - -/* - * Physical base addresses for integrated peripherals - */ - -#ifdef CONFIG_SOC_AU1000 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define DMA0_PHYS_ADDR 0x14002000 -#define DMA1_PHYS_ADDR 0x14002100 -#define DMA2_PHYS_ADDR 0x14002200 -#define DMA3_PHYS_ADDR 0x14002300 -#define DMA4_PHYS_ADDR 0x14002400 -#define DMA5_PHYS_ADDR 0x14002500 -#define DMA6_PHYS_ADDR 0x14002600 -#define DMA7_PHYS_ADDR 0x14002700 -#define IC0_PHYS_ADDR 0x10400000 -#define IC1_PHYS_ADDR 0x11800000 -#define AC97_PHYS_ADDR 0x10000000 -#define USBH_PHYS_ADDR 0x10100000 -#define USBD_PHYS_ADDR 0x10200000 -#define IRDA_PHYS_ADDR 0x10300000 -#define MAC0_PHYS_ADDR 0x10500000 -#define MAC1_PHYS_ADDR 0x10510000 -#define MACEN_PHYS_ADDR 0x10520000 -#define MACDMA0_PHYS_ADDR 0x14004000 -#define MACDMA1_PHYS_ADDR 0x14004200 -#define I2S_PHYS_ADDR 0x11000000 -#define UART0_PHYS_ADDR 0x11100000 -#define UART1_PHYS_ADDR 0x11200000 -#define UART2_PHYS_ADDR 0x11300000 -#define UART3_PHYS_ADDR 0x11400000 -#define SSI0_PHYS_ADDR 0x11600000 -#define SSI1_PHYS_ADDR 0x11680000 -#define SYS_PHYS_ADDR 0x11900000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/********************************************************************/ - -#ifdef CONFIG_SOC_AU1500 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define DMA0_PHYS_ADDR 0x14002000 -#define DMA1_PHYS_ADDR 0x14002100 -#define DMA2_PHYS_ADDR 0x14002200 -#define DMA3_PHYS_ADDR 0x14002300 -#define DMA4_PHYS_ADDR 0x14002400 -#define DMA5_PHYS_ADDR 0x14002500 -#define DMA6_PHYS_ADDR 0x14002600 -#define DMA7_PHYS_ADDR 0x14002700 -#define IC0_PHYS_ADDR 0x10400000 -#define IC1_PHYS_ADDR 0x11800000 -#define AC97_PHYS_ADDR 0x10000000 -#define USBH_PHYS_ADDR 0x10100000 -#define USBD_PHYS_ADDR 0x10200000 -#define PCI_PHYS_ADDR 0x14005000 -#define MAC0_PHYS_ADDR 0x11500000 -#define MAC1_PHYS_ADDR 0x11510000 -#define MACEN_PHYS_ADDR 0x11520000 -#define MACDMA0_PHYS_ADDR 0x14004000 -#define MACDMA1_PHYS_ADDR 0x14004200 -#define I2S_PHYS_ADDR 0x11000000 -#define UART0_PHYS_ADDR 0x11100000 -#define UART3_PHYS_ADDR 0x11400000 -#define GPIO2_PHYS_ADDR 0x11700000 -#define SYS_PHYS_ADDR 0x11900000 -#define PCI_MEM_PHYS_ADDR 0x400000000ULL -#define PCI_IO_PHYS_ADDR 0x500000000ULL -#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL -#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/********************************************************************/ - -#ifdef CONFIG_SOC_AU1100 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define DMA0_PHYS_ADDR 0x14002000 -#define DMA1_PHYS_ADDR 0x14002100 -#define DMA2_PHYS_ADDR 0x14002200 -#define DMA3_PHYS_ADDR 0x14002300 -#define DMA4_PHYS_ADDR 0x14002400 -#define DMA5_PHYS_ADDR 0x14002500 -#define DMA6_PHYS_ADDR 0x14002600 -#define DMA7_PHYS_ADDR 0x14002700 -#define IC0_PHYS_ADDR 0x10400000 -#define SD0_PHYS_ADDR 0x10600000 -#define SD1_PHYS_ADDR 0x10680000 -#define IC1_PHYS_ADDR 0x11800000 -#define AC97_PHYS_ADDR 0x10000000 -#define USBH_PHYS_ADDR 0x10100000 -#define USBD_PHYS_ADDR 0x10200000 -#define IRDA_PHYS_ADDR 0x10300000 -#define MAC0_PHYS_ADDR 0x10500000 -#define MACEN_PHYS_ADDR 0x10520000 -#define MACDMA0_PHYS_ADDR 0x14004000 -#define MACDMA1_PHYS_ADDR 0x14004200 -#define I2S_PHYS_ADDR 0x11000000 -#define UART0_PHYS_ADDR 0x11100000 -#define UART1_PHYS_ADDR 0x11200000 -#define UART3_PHYS_ADDR 0x11400000 -#define SSI0_PHYS_ADDR 0x11600000 -#define SSI1_PHYS_ADDR 0x11680000 -#define GPIO2_PHYS_ADDR 0x11700000 -#define SYS_PHYS_ADDR 0x11900000 -#define LCD_PHYS_ADDR 0x15000000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/***********************************************************************/ - -#ifdef CONFIG_SOC_AU1550 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define IC0_PHYS_ADDR 0x10400000 -#define IC1_PHYS_ADDR 0x11800000 -#define USBH_PHYS_ADDR 0x14020000 -#define USBD_PHYS_ADDR 0x10200000 -#define PCI_PHYS_ADDR 0x14005000 -#define MAC0_PHYS_ADDR 0x10500000 -#define MAC1_PHYS_ADDR 0x10510000 -#define MACEN_PHYS_ADDR 0x10520000 -#define MACDMA0_PHYS_ADDR 0x14004000 -#define MACDMA1_PHYS_ADDR 0x14004200 -#define UART0_PHYS_ADDR 0x11100000 -#define UART1_PHYS_ADDR 0x11200000 -#define UART3_PHYS_ADDR 0x11400000 -#define GPIO2_PHYS_ADDR 0x11700000 -#define SYS_PHYS_ADDR 0x11900000 -#define DDMA_PHYS_ADDR 0x14002000 -#define PE_PHYS_ADDR 0x14008000 -#define PSC0_PHYS_ADDR 0x11A00000 -#define PSC1_PHYS_ADDR 0x11B00000 -#define PSC2_PHYS_ADDR 0x10A00000 -#define PSC3_PHYS_ADDR 0x10B00000 -#define PCI_MEM_PHYS_ADDR 0x400000000ULL -#define PCI_IO_PHYS_ADDR 0x500000000ULL -#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL -#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/***********************************************************************/ - -#ifdef CONFIG_SOC_AU1200 -#define MEM_PHYS_ADDR 0x14000000 -#define STATIC_MEM_PHYS_ADDR 0x14001000 -#define AES_PHYS_ADDR 0x10300000 -#define CIM_PHYS_ADDR 0x14004000 -#define IC0_PHYS_ADDR 0x10400000 -#define IC1_PHYS_ADDR 0x11800000 -#define USBM_PHYS_ADDR 0x14020000 -#define USBH_PHYS_ADDR 0x14020100 -#define UART0_PHYS_ADDR 0x11100000 -#define UART1_PHYS_ADDR 0x11200000 -#define GPIO2_PHYS_ADDR 0x11700000 -#define SYS_PHYS_ADDR 0x11900000 -#define DDMA_PHYS_ADDR 0x14002000 -#define PSC0_PHYS_ADDR 0x11A00000 -#define PSC1_PHYS_ADDR 0x11B00000 -#define SD0_PHYS_ADDR 0x10600000 -#define SD1_PHYS_ADDR 0x10680000 -#define LCD_PHYS_ADDR 0x15000000 -#define SWCNT_PHYS_ADDR 0x1110010C -#define MAEFE_PHYS_ADDR 0x14012000 -#define MAEBE_PHYS_ADDR 0x14010000 -#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL -#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL -#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL -#endif - -/* Static Bus Controller */ -#define MEM_STCFG0 0xB4001000 -#define MEM_STTIME0 0xB4001004 -#define MEM_STADDR0 0xB4001008 - -#define MEM_STCFG1 0xB4001010 -#define MEM_STTIME1 0xB4001014 -#define MEM_STADDR1 0xB4001018 +/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */ +extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio); +extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio); +extern void au1300_set_irq_priority(unsigned int irq, int p); +extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio); + +/* Au1300 allows to disconnect certain blocks from internal power supply */ +enum au1300_vss_block { + AU1300_VSS_MPE = 0, + AU1300_VSS_BSA, + AU1300_VSS_GPE, + AU1300_VSS_MGP, +}; -#define MEM_STCFG2 0xB4001020 -#define MEM_STTIME2 0xB4001024 -#define MEM_STADDR2 0xB4001028 +extern void au1300_vss_block_control(int block, int enable); -#define MEM_STCFG3 0xB4001030 -#define MEM_STTIME3 0xB4001034 -#define MEM_STADDR3 0xB4001038 -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) -#define MEM_STNDCTL 0xB4001100 -#define MEM_STSTAT 0xB4001104 +/* SOC Interrupt numbers */ +/* Au1000-style (IC0/1): 2 controllers with 32 sources each */ +#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) +#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) +#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) +#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) +#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST -#define MEM_STNAND_CMD 0x0 -#define MEM_STNAND_ADDR 0x4 -#define MEM_STNAND_DATA 0x20 -#endif +/* Au1300-style (GPIC): 1 controller with up to 128 sources */ +#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8) +#define ALCHEMY_GPIC_INT_NUM 128 +#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1) -/* Interrupt Controller 0 */ -#define IC0_CFG0RD 0xB0400040 -#define IC0_CFG0SET 0xB0400040 -#define IC0_CFG0CLR 0xB0400044 - -#define IC0_CFG1RD 0xB0400048 -#define IC0_CFG1SET 0xB0400048 -#define IC0_CFG1CLR 0xB040004C - -#define IC0_CFG2RD 0xB0400050 -#define IC0_CFG2SET 0xB0400050 -#define IC0_CFG2CLR 0xB0400054 - -#define IC0_REQ0INT 0xB0400054 -#define IC0_SRCRD 0xB0400058 -#define IC0_SRCSET 0xB0400058 -#define IC0_SRCCLR 0xB040005C -#define IC0_REQ1INT 0xB040005C - -#define IC0_ASSIGNRD 0xB0400060 -#define IC0_ASSIGNSET 0xB0400060 -#define IC0_ASSIGNCLR 0xB0400064 - -#define IC0_WAKERD 0xB0400068 -#define IC0_WAKESET 0xB0400068 -#define IC0_WAKECLR 0xB040006C - -#define IC0_MASKRD 0xB0400070 -#define IC0_MASKSET 0xB0400070 -#define IC0_MASKCLR 0xB0400074 - -#define IC0_RISINGRD 0xB0400078 -#define IC0_RISINGCLR 0xB0400078 -#define IC0_FALLINGRD 0xB040007C -#define IC0_FALLINGCLR 0xB040007C - -#define IC0_TESTBIT 0xB0400080 - -/* Interrupt Controller 1 */ -#define IC1_CFG0RD 0xB1800040 -#define IC1_CFG0SET 0xB1800040 -#define IC1_CFG0CLR 0xB1800044 - -#define IC1_CFG1RD 0xB1800048 -#define IC1_CFG1SET 0xB1800048 -#define IC1_CFG1CLR 0xB180004C - -#define IC1_CFG2RD 0xB1800050 -#define IC1_CFG2SET 0xB1800050 -#define IC1_CFG2CLR 0xB1800054 - -#define IC1_REQ0INT 0xB1800054 -#define IC1_SRCRD 0xB1800058 -#define IC1_SRCSET 0xB1800058 -#define IC1_SRCCLR 0xB180005C -#define IC1_REQ1INT 0xB180005C - -#define IC1_ASSIGNRD 0xB1800060 -#define IC1_ASSIGNSET 0xB1800060 -#define IC1_ASSIGNCLR 0xB1800064 - -#define IC1_WAKERD 0xB1800068 -#define IC1_WAKESET 0xB1800068 -#define IC1_WAKECLR 0xB180006C - -#define IC1_MASKRD 0xB1800070 -#define IC1_MASKSET 0xB1800070 -#define IC1_MASKCLR 0xB1800074 - -#define IC1_RISINGRD 0xB1800078 -#define IC1_RISINGCLR 0xB1800078 -#define IC1_FALLINGRD 0xB180007C -#define IC1_FALLINGCLR 0xB180007C - -#define IC1_TESTBIT 0xB1800080 - -/* Interrupt Numbers */ -/* Au1000 */ -#ifdef CONFIG_SOC_AU1000 enum soc_au1000_ints { - AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, + AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, AU1000_UART0_INT = AU1000_FIRST_INT, - AU1000_UART1_INT, /* au1000 */ - AU1000_UART2_INT, /* au1000 */ + AU1000_UART1_INT, + AU1000_UART2_INT, AU1000_UART3_INT, - AU1000_SSI0_INT, /* au1000 */ - AU1000_SSI1_INT, /* au1000 */ + AU1000_SSI0_INT, + AU1000_SSI1_INT, AU1000_DMA_INT_BASE, AU1000_TOY_INT = AU1000_FIRST_INT + 14, @@ -570,226 +376,175 @@ enum soc_au1000_ints { AU1000_RTC_MATCH0_INT, AU1000_RTC_MATCH1_INT, AU1000_RTC_MATCH2_INT, - AU1000_IRDA_TX_INT, /* au1000 */ - AU1000_IRDA_RX_INT, /* au1000 */ + AU1000_IRDA_TX_INT, + AU1000_IRDA_RX_INT, AU1000_USB_DEV_REQ_INT, AU1000_USB_DEV_SUS_INT, AU1000_USB_HOST_INT, AU1000_ACSYNC_INT, AU1000_MAC0_DMA_INT, AU1000_MAC1_DMA_INT, - AU1000_I2S_UO_INT, /* au1000 */ + AU1000_I2S_UO_INT, AU1000_AC97C_INT, - AU1000_GPIO_0, - AU1000_GPIO_1, - AU1000_GPIO_2, - AU1000_GPIO_3, - AU1000_GPIO_4, - AU1000_GPIO_5, - AU1000_GPIO_6, - AU1000_GPIO_7, - AU1000_GPIO_8, - AU1000_GPIO_9, - AU1000_GPIO_10, - AU1000_GPIO_11, - AU1000_GPIO_12, - AU1000_GPIO_13, - AU1000_GPIO_14, - AU1000_GPIO_15, - AU1000_GPIO_16, - AU1000_GPIO_17, - AU1000_GPIO_18, - AU1000_GPIO_19, - AU1000_GPIO_20, - AU1000_GPIO_21, - AU1000_GPIO_22, - AU1000_GPIO_23, - AU1000_GPIO_24, - AU1000_GPIO_25, - AU1000_GPIO_26, - AU1000_GPIO_27, - AU1000_GPIO_28, - AU1000_GPIO_29, - AU1000_GPIO_30, - AU1000_GPIO_31, + AU1000_GPIO0_INT, + AU1000_GPIO1_INT, + AU1000_GPIO2_INT, + AU1000_GPIO3_INT, + AU1000_GPIO4_INT, + AU1000_GPIO5_INT, + AU1000_GPIO6_INT, + AU1000_GPIO7_INT, + AU1000_GPIO8_INT, + AU1000_GPIO9_INT, + AU1000_GPIO10_INT, + AU1000_GPIO11_INT, + AU1000_GPIO12_INT, + AU1000_GPIO13_INT, + AU1000_GPIO14_INT, + AU1000_GPIO15_INT, + AU1000_GPIO16_INT, + AU1000_GPIO17_INT, + AU1000_GPIO18_INT, + AU1000_GPIO19_INT, + AU1000_GPIO20_INT, + AU1000_GPIO21_INT, + AU1000_GPIO22_INT, + AU1000_GPIO23_INT, + AU1000_GPIO24_INT, + AU1000_GPIO25_INT, + AU1000_GPIO26_INT, + AU1000_GPIO27_INT, + AU1000_GPIO28_INT, + AU1000_GPIO29_INT, + AU1000_GPIO30_INT, + AU1000_GPIO31_INT, }; -#define UART0_ADDR 0xB1100000 -#define UART1_ADDR 0xB1200000 -#define UART2_ADDR 0xB1300000 -#define UART3_ADDR 0xB1400000 - -#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ -#define USB_HOST_CONFIG 0xB017FFFC - -#define AU1000_ETH0_BASE 0xB0500000 -#define AU1000_ETH1_BASE 0xB0510000 -#define AU1000_MAC0_ENABLE 0xB0520000 -#define AU1000_MAC1_ENABLE 0xB0520004 -#define NUM_ETH_INTERFACES 2 -#endif /* CONFIG_SOC_AU1000 */ +enum soc_au1100_ints { + AU1100_FIRST_INT = AU1000_INTC0_INT_BASE, + AU1100_UART0_INT = AU1100_FIRST_INT, + AU1100_UART1_INT, + AU1100_SD_INT, + AU1100_UART3_INT, + AU1100_SSI0_INT, + AU1100_SSI1_INT, + AU1100_DMA_INT_BASE, + + AU1100_TOY_INT = AU1100_FIRST_INT + 14, + AU1100_TOY_MATCH0_INT, + AU1100_TOY_MATCH1_INT, + AU1100_TOY_MATCH2_INT, + AU1100_RTC_INT, + AU1100_RTC_MATCH0_INT, + AU1100_RTC_MATCH1_INT, + AU1100_RTC_MATCH2_INT, + AU1100_IRDA_TX_INT, + AU1100_IRDA_RX_INT, + AU1100_USB_DEV_REQ_INT, + AU1100_USB_DEV_SUS_INT, + AU1100_USB_HOST_INT, + AU1100_ACSYNC_INT, + AU1100_MAC0_DMA_INT, + AU1100_GPIO208_215_INT, + AU1100_LCD_INT, + AU1100_AC97C_INT, + AU1100_GPIO0_INT, + AU1100_GPIO1_INT, + AU1100_GPIO2_INT, + AU1100_GPIO3_INT, + AU1100_GPIO4_INT, + AU1100_GPIO5_INT, + AU1100_GPIO6_INT, + AU1100_GPIO7_INT, + AU1100_GPIO8_INT, + AU1100_GPIO9_INT, + AU1100_GPIO10_INT, + AU1100_GPIO11_INT, + AU1100_GPIO12_INT, + AU1100_GPIO13_INT, + AU1100_GPIO14_INT, + AU1100_GPIO15_INT, + AU1100_GPIO16_INT, + AU1100_GPIO17_INT, + AU1100_GPIO18_INT, + AU1100_GPIO19_INT, + AU1100_GPIO20_INT, + AU1100_GPIO21_INT, + AU1100_GPIO22_INT, + AU1100_GPIO23_INT, + AU1100_GPIO24_INT, + AU1100_GPIO25_INT, + AU1100_GPIO26_INT, + AU1100_GPIO27_INT, + AU1100_GPIO28_INT, + AU1100_GPIO29_INT, + AU1100_GPIO30_INT, + AU1100_GPIO31_INT, +}; -/* Au1500 */ -#ifdef CONFIG_SOC_AU1500 enum soc_au1500_ints { - AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, + AU1500_FIRST_INT = AU1000_INTC0_INT_BASE, AU1500_UART0_INT = AU1500_FIRST_INT, - AU1000_PCI_INTA, /* au1500 */ - AU1000_PCI_INTB, /* au1500 */ + AU1500_PCI_INTA, + AU1500_PCI_INTB, AU1500_UART3_INT, - AU1000_PCI_INTC, /* au1500 */ - AU1000_PCI_INTD, /* au1500 */ - AU1000_DMA_INT_BASE, - - AU1000_TOY_INT = AU1500_FIRST_INT + 14, - AU1000_TOY_MATCH0_INT, - AU1000_TOY_MATCH1_INT, - AU1000_TOY_MATCH2_INT, - AU1000_RTC_INT, - AU1000_RTC_MATCH0_INT, - AU1000_RTC_MATCH1_INT, - AU1000_RTC_MATCH2_INT, + AU1500_PCI_INTC, + AU1500_PCI_INTD, + AU1500_DMA_INT_BASE, + + AU1500_TOY_INT = AU1500_FIRST_INT + 14, + AU1500_TOY_MATCH0_INT, + AU1500_TOY_MATCH1_INT, + AU1500_TOY_MATCH2_INT, + AU1500_RTC_INT, + AU1500_RTC_MATCH0_INT, + AU1500_RTC_MATCH1_INT, + AU1500_RTC_MATCH2_INT, AU1500_PCI_ERR_INT, AU1500_RESERVED_INT, - AU1000_USB_DEV_REQ_INT, - AU1000_USB_DEV_SUS_INT, - AU1000_USB_HOST_INT, - AU1000_ACSYNC_INT, + AU1500_USB_DEV_REQ_INT, + AU1500_USB_DEV_SUS_INT, + AU1500_USB_HOST_INT, + AU1500_ACSYNC_INT, AU1500_MAC0_DMA_INT, AU1500_MAC1_DMA_INT, - AU1000_AC97C_INT = AU1500_FIRST_INT + 31, - AU1000_GPIO_0, - AU1000_GPIO_1, - AU1000_GPIO_2, - AU1000_GPIO_3, - AU1000_GPIO_4, - AU1000_GPIO_5, - AU1000_GPIO_6, - AU1000_GPIO_7, - AU1000_GPIO_8, - AU1000_GPIO_9, - AU1000_GPIO_10, - AU1000_GPIO_11, - AU1000_GPIO_12, - AU1000_GPIO_13, - AU1000_GPIO_14, - AU1000_GPIO_15, - AU1500_GPIO_200, - AU1500_GPIO_201, - AU1500_GPIO_202, - AU1500_GPIO_203, - AU1500_GPIO_20, - AU1500_GPIO_204, - AU1500_GPIO_205, - AU1500_GPIO_23, - AU1500_GPIO_24, - AU1500_GPIO_25, - AU1500_GPIO_26, - AU1500_GPIO_27, - AU1500_GPIO_28, - AU1500_GPIO_206, - AU1500_GPIO_207, - AU1500_GPIO_208_215, + AU1500_AC97C_INT = AU1500_FIRST_INT + 31, + AU1500_GPIO0_INT, + AU1500_GPIO1_INT, + AU1500_GPIO2_INT, + AU1500_GPIO3_INT, + AU1500_GPIO4_INT, + AU1500_GPIO5_INT, + AU1500_GPIO6_INT, + AU1500_GPIO7_INT, + AU1500_GPIO8_INT, + AU1500_GPIO9_INT, + AU1500_GPIO10_INT, + AU1500_GPIO11_INT, + AU1500_GPIO12_INT, + AU1500_GPIO13_INT, + AU1500_GPIO14_INT, + AU1500_GPIO15_INT, + AU1500_GPIO200_INT, + AU1500_GPIO201_INT, + AU1500_GPIO202_INT, + AU1500_GPIO203_INT, + AU1500_GPIO20_INT, + AU1500_GPIO204_INT, + AU1500_GPIO205_INT, + AU1500_GPIO23_INT, + AU1500_GPIO24_INT, + AU1500_GPIO25_INT, + AU1500_GPIO26_INT, + AU1500_GPIO27_INT, + AU1500_GPIO28_INT, + AU1500_GPIO206_INT, + AU1500_GPIO207_INT, + AU1500_GPIO208_215_INT, }; -/* shortcuts */ -#define INTA AU1000_PCI_INTA -#define INTB AU1000_PCI_INTB -#define INTC AU1000_PCI_INTC -#define INTD AU1000_PCI_INTD - -#define UART0_ADDR 0xB1100000 -#define UART3_ADDR 0xB1400000 - -#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ -#define USB_HOST_CONFIG 0xB017fffc - -#define AU1500_ETH0_BASE 0xB1500000 -#define AU1500_ETH1_BASE 0xB1510000 -#define AU1500_MAC0_ENABLE 0xB1520000 -#define AU1500_MAC1_ENABLE 0xB1520004 -#define NUM_ETH_INTERFACES 2 -#endif /* CONFIG_SOC_AU1500 */ - -/* Au1100 */ -#ifdef CONFIG_SOC_AU1100 -enum soc_au1100_ints { - AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, - AU1100_UART0_INT, - AU1100_UART1_INT, - AU1100_SD_INT, - AU1100_UART3_INT, - AU1000_SSI0_INT, - AU1000_SSI1_INT, - AU1000_DMA_INT_BASE, - - AU1000_TOY_INT = AU1100_FIRST_INT + 14, - AU1000_TOY_MATCH0_INT, - AU1000_TOY_MATCH1_INT, - AU1000_TOY_MATCH2_INT, - AU1000_RTC_INT, - AU1000_RTC_MATCH0_INT, - AU1000_RTC_MATCH1_INT, - AU1000_RTC_MATCH2_INT, - AU1000_IRDA_TX_INT, - AU1000_IRDA_RX_INT, - AU1000_USB_DEV_REQ_INT, - AU1000_USB_DEV_SUS_INT, - AU1000_USB_HOST_INT, - AU1000_ACSYNC_INT, - AU1100_MAC0_DMA_INT, - AU1100_GPIO_208_215, - AU1100_LCD_INT, - AU1000_AC97C_INT, - AU1000_GPIO_0, - AU1000_GPIO_1, - AU1000_GPIO_2, - AU1000_GPIO_3, - AU1000_GPIO_4, - AU1000_GPIO_5, - AU1000_GPIO_6, - AU1000_GPIO_7, - AU1000_GPIO_8, - AU1000_GPIO_9, - AU1000_GPIO_10, - AU1000_GPIO_11, - AU1000_GPIO_12, - AU1000_GPIO_13, - AU1000_GPIO_14, - AU1000_GPIO_15, - AU1000_GPIO_16, - AU1000_GPIO_17, - AU1000_GPIO_18, - AU1000_GPIO_19, - AU1000_GPIO_20, - AU1000_GPIO_21, - AU1000_GPIO_22, - AU1000_GPIO_23, - AU1000_GPIO_24, - AU1000_GPIO_25, - AU1000_GPIO_26, - AU1000_GPIO_27, - AU1000_GPIO_28, - AU1000_GPIO_29, - AU1000_GPIO_30, - AU1000_GPIO_31, -}; - -#define UART0_ADDR 0xB1100000 -#define UART1_ADDR 0xB1200000 -#define UART3_ADDR 0xB1400000 - -#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ -#define USB_HOST_CONFIG 0xB017FFFC - -#define AU1100_ETH0_BASE 0xB0500000 -#define AU1100_MAC0_ENABLE 0xB0520000 -#define NUM_ETH_INTERFACES 1 -#endif /* CONFIG_SOC_AU1100 */ - -#ifdef CONFIG_SOC_AU1550 enum soc_au1550_ints { - AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, + AU1550_FIRST_INT = AU1000_INTC0_INT_BASE, AU1550_UART0_INT = AU1550_FIRST_INT, AU1550_PCI_INTA, AU1550_PCI_INTB, @@ -804,208 +559,433 @@ enum soc_au1550_ints { AU1550_PSC1_INT, AU1550_PSC2_INT, AU1550_PSC3_INT, - AU1000_TOY_INT, - AU1000_TOY_MATCH0_INT, - AU1000_TOY_MATCH1_INT, - AU1000_TOY_MATCH2_INT, - AU1000_RTC_INT, - AU1000_RTC_MATCH0_INT, - AU1000_RTC_MATCH1_INT, - AU1000_RTC_MATCH2_INT, - - AU1550_NAND_INT = AU1550_FIRST_INT + 23, + AU1550_TOY_INT, + AU1550_TOY_MATCH0_INT, + AU1550_TOY_MATCH1_INT, + AU1550_TOY_MATCH2_INT, + AU1550_RTC_INT, + AU1550_RTC_MATCH0_INT, + AU1550_RTC_MATCH1_INT, + AU1550_RTC_MATCH2_INT, + + AU1550_NAND_INT = AU1550_FIRST_INT + 23, AU1550_USB_DEV_REQ_INT, - AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT, AU1550_USB_DEV_SUS_INT, - AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT, AU1550_USB_HOST_INT, - AU1000_USB_HOST_INT = AU1550_USB_HOST_INT, AU1550_MAC0_DMA_INT, AU1550_MAC1_DMA_INT, - AU1000_GPIO_0 = AU1550_FIRST_INT + 32, - AU1000_GPIO_1, - AU1000_GPIO_2, - AU1000_GPIO_3, - AU1000_GPIO_4, - AU1000_GPIO_5, - AU1000_GPIO_6, - AU1000_GPIO_7, - AU1000_GPIO_8, - AU1000_GPIO_9, - AU1000_GPIO_10, - AU1000_GPIO_11, - AU1000_GPIO_12, - AU1000_GPIO_13, - AU1000_GPIO_14, - AU1000_GPIO_15, - AU1550_GPIO_200, - AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */ - AU1500_GPIO_16, - AU1500_GPIO_17, - AU1500_GPIO_20, - AU1500_GPIO_21, - AU1500_GPIO_22, - AU1500_GPIO_23, - AU1500_GPIO_24, - AU1500_GPIO_25, - AU1500_GPIO_26, - AU1500_GPIO_27, - AU1500_GPIO_28, - AU1500_GPIO_206, - AU1500_GPIO_207, - AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */ + AU1550_GPIO0_INT = AU1550_FIRST_INT + 32, + AU1550_GPIO1_INT, + AU1550_GPIO2_INT, + AU1550_GPIO3_INT, + AU1550_GPIO4_INT, + AU1550_GPIO5_INT, + AU1550_GPIO6_INT, + AU1550_GPIO7_INT, + AU1550_GPIO8_INT, + AU1550_GPIO9_INT, + AU1550_GPIO10_INT, + AU1550_GPIO11_INT, + AU1550_GPIO12_INT, + AU1550_GPIO13_INT, + AU1550_GPIO14_INT, + AU1550_GPIO15_INT, + AU1550_GPIO200_INT, + AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */ + AU1550_GPIO16_INT, + AU1550_GPIO17_INT, + AU1550_GPIO20_INT, + AU1550_GPIO21_INT, + AU1550_GPIO22_INT, + AU1550_GPIO23_INT, + AU1550_GPIO24_INT, + AU1550_GPIO25_INT, + AU1550_GPIO26_INT, + AU1550_GPIO27_INT, + AU1550_GPIO28_INT, + AU1550_GPIO206_INT, + AU1550_GPIO207_INT, + AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */ }; -/* shortcuts */ -#define INTA AU1550_PCI_INTA -#define INTB AU1550_PCI_INTB -#define INTC AU1550_PCI_INTC -#define INTD AU1550_PCI_INTD - -#define UART0_ADDR 0xB1100000 -#define UART1_ADDR 0xB1200000 -#define UART3_ADDR 0xB1400000 - -#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ -#define USB_OHCI_LEN 0x00060000 -#define USB_HOST_CONFIG 0xB4027ffc - -#define AU1550_ETH0_BASE 0xB0500000 -#define AU1550_ETH1_BASE 0xB0510000 -#define AU1550_MAC0_ENABLE 0xB0520000 -#define AU1550_MAC1_ENABLE 0xB0520004 -#define NUM_ETH_INTERFACES 2 -#endif /* CONFIG_SOC_AU1550 */ - -#ifdef CONFIG_SOC_AU1200 enum soc_au1200_ints { - AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, + AU1200_FIRST_INT = AU1000_INTC0_INT_BASE, AU1200_UART0_INT = AU1200_FIRST_INT, AU1200_SWT_INT, AU1200_SD_INT, AU1200_DDMA_INT, AU1200_MAE_BE_INT, - AU1200_GPIO_200, - AU1200_GPIO_201, - AU1200_GPIO_202, + AU1200_GPIO200_INT, + AU1200_GPIO201_INT, + AU1200_GPIO202_INT, AU1200_UART1_INT, AU1200_MAE_FE_INT, AU1200_PSC0_INT, AU1200_PSC1_INT, AU1200_AES_INT, AU1200_CAMERA_INT, - AU1000_TOY_INT, - AU1000_TOY_MATCH0_INT, - AU1000_TOY_MATCH1_INT, - AU1000_TOY_MATCH2_INT, - AU1000_RTC_INT, - AU1000_RTC_MATCH0_INT, - AU1000_RTC_MATCH1_INT, - AU1000_RTC_MATCH2_INT, - - AU1200_NAND_INT = AU1200_FIRST_INT + 23, - AU1200_GPIO_204, - AU1200_GPIO_205, - AU1200_GPIO_206, - AU1200_GPIO_207, - AU1200_GPIO_208_215, /* Logical OR of 208:215 */ + AU1200_TOY_INT, + AU1200_TOY_MATCH0_INT, + AU1200_TOY_MATCH1_INT, + AU1200_TOY_MATCH2_INT, + AU1200_RTC_INT, + AU1200_RTC_MATCH0_INT, + AU1200_RTC_MATCH1_INT, + AU1200_RTC_MATCH2_INT, + AU1200_GPIO203_INT, + AU1200_NAND_INT, + AU1200_GPIO204_INT, + AU1200_GPIO205_INT, + AU1200_GPIO206_INT, + AU1200_GPIO207_INT, + AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */ AU1200_USB_INT, - AU1000_USB_HOST_INT = AU1200_USB_INT, AU1200_LCD_INT, AU1200_MAE_BOTH_INT, - AU1000_GPIO_0, - AU1000_GPIO_1, - AU1000_GPIO_2, - AU1000_GPIO_3, - AU1000_GPIO_4, - AU1000_GPIO_5, - AU1000_GPIO_6, - AU1000_GPIO_7, - AU1000_GPIO_8, - AU1000_GPIO_9, - AU1000_GPIO_10, - AU1000_GPIO_11, - AU1000_GPIO_12, - AU1000_GPIO_13, - AU1000_GPIO_14, - AU1000_GPIO_15, - AU1000_GPIO_16, - AU1000_GPIO_17, - AU1000_GPIO_18, - AU1000_GPIO_19, - AU1000_GPIO_20, - AU1000_GPIO_21, - AU1000_GPIO_22, - AU1000_GPIO_23, - AU1000_GPIO_24, - AU1000_GPIO_25, - AU1000_GPIO_26, - AU1000_GPIO_27, - AU1000_GPIO_28, - AU1000_GPIO_29, - AU1000_GPIO_30, - AU1000_GPIO_31, + AU1200_GPIO0_INT, + AU1200_GPIO1_INT, + AU1200_GPIO2_INT, + AU1200_GPIO3_INT, + AU1200_GPIO4_INT, + AU1200_GPIO5_INT, + AU1200_GPIO6_INT, + AU1200_GPIO7_INT, + AU1200_GPIO8_INT, + AU1200_GPIO9_INT, + AU1200_GPIO10_INT, + AU1200_GPIO11_INT, + AU1200_GPIO12_INT, + AU1200_GPIO13_INT, + AU1200_GPIO14_INT, + AU1200_GPIO15_INT, + AU1200_GPIO16_INT, + AU1200_GPIO17_INT, + AU1200_GPIO18_INT, + AU1200_GPIO19_INT, + AU1200_GPIO20_INT, + AU1200_GPIO21_INT, + AU1200_GPIO22_INT, + AU1200_GPIO23_INT, + AU1200_GPIO24_INT, + AU1200_GPIO25_INT, + AU1200_GPIO26_INT, + AU1200_GPIO27_INT, + AU1200_GPIO28_INT, + AU1200_GPIO29_INT, + AU1200_GPIO30_INT, + AU1200_GPIO31_INT, }; -#define UART0_ADDR 0xB1100000 -#define UART1_ADDR 0xB1200000 - -#define USB_UOC_BASE 0x14020020 -#define USB_UOC_LEN 0x20 -#define USB_OHCI_BASE 0x14020100 -#define USB_OHCI_LEN 0x100 -#define USB_EHCI_BASE 0x14020200 -#define USB_EHCI_LEN 0x100 -#define USB_UDC_BASE 0x14022000 -#define USB_UDC_LEN 0x2000 -#define USB_MSR_BASE 0xB4020000 -#define USB_MSR_MCFG 4 -#define USBMSRMCFG_OMEMEN 0 -#define USBMSRMCFG_OBMEN 1 -#define USBMSRMCFG_EMEMEN 2 -#define USBMSRMCFG_EBMEN 3 -#define USBMSRMCFG_DMEMEN 4 -#define USBMSRMCFG_DBMEN 5 -#define USBMSRMCFG_GMEMEN 6 -#define USBMSRMCFG_OHCCLKEN 16 -#define USBMSRMCFG_EHCCLKEN 17 -#define USBMSRMCFG_UDCCLKEN 18 -#define USBMSRMCFG_PHYPLLEN 19 -#define USBMSRMCFG_RDCOMB 30 -#define USBMSRMCFG_PFEN 31 - -#endif /* CONFIG_SOC_AU1200 */ +#endif /* !defined (_LANGUAGE_ASSEMBLY) */ -#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) -#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) -#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32) -#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) +/* Au1300 peripheral interrupt numbers */ +#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE) +#define AU1300_UART1_INT (AU1300_FIRST_INT + 17) +#define AU1300_UART2_INT (AU1300_FIRST_INT + 25) +#define AU1300_UART3_INT (AU1300_FIRST_INT + 27) +#define AU1300_SD1_INT (AU1300_FIRST_INT + 32) +#define AU1300_SD2_INT (AU1300_FIRST_INT + 38) +#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48) +#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52) +#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56) +#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60) +#define AU1300_NAND_INT (AU1300_FIRST_INT + 62) +#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75) +#define AU1300_MMU_INT (AU1300_FIRST_INT + 76) +#define AU1300_MPU_INT (AU1300_FIRST_INT + 77) +#define AU1300_GPU_INT (AU1300_FIRST_INT + 78) +#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79) +#define AU1300_TOY_INT (AU1300_FIRST_INT + 80) +#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81) +#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82) +#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83) +#define AU1300_RTC_INT (AU1300_FIRST_INT + 84) +#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85) +#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86) +#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87) +#define AU1300_UART0_INT (AU1300_FIRST_INT + 88) +#define AU1300_SD0_INT (AU1300_FIRST_INT + 89) +#define AU1300_USB_INT (AU1300_FIRST_INT + 90) +#define AU1300_LCD_INT (AU1300_FIRST_INT + 91) +#define AU1300_BSA_INT (AU1300_FIRST_INT + 92) +#define AU1300_MPE_INT (AU1300_FIRST_INT + 93) +#define AU1300_ITE_INT (AU1300_FIRST_INT + 94) +#define AU1300_AES_INT (AU1300_FIRST_INT + 95) +#define AU1300_CIM_INT (AU1300_FIRST_INT + 96) + +/**********************************************************************/ + +/* + * Physical base addresses for integrated peripherals + * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300 + */ + +#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ +#define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */ +#define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */ +#define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */ +#define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */ +#define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */ +#define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */ +#define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */ +#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ +#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ +#define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */ +#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */ +#define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */ +#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ +#define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */ +#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ +#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ +#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ +#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */ +#define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */ +#define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */ +#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ +#define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */ +#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */ +#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */ +#define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */ +#define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */ +#define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */ +#define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */ +#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ +#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ +#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ +#define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */ +#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */ +#define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */ +#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */ +#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ +#define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */ +#define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */ +#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */ +#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ +#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ +#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */ +#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */ +#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */ +#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */ +#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */ +#define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */ +#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ +#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */ +#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */ +#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ +#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ +#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */ +#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */ +#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */ +#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */ +#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */ +#define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */ +#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */ +#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ +#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ +#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ +#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ +#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ +#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ +#define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */ +#define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */ +#define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */ +#define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */ +#define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */ +#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */ +#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */ +#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */ +#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */ +#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */ +#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */ +#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */ +#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */ +#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */ +#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */ + +/**********************************************************************/ + + +/* + * Au1300 GPIO+INT controller (GPIC) register offsets and bits + * Registers are 128bits (0x10 bytes), divided into 4 "banks". + */ +#define AU1300_GPIC_PINVAL 0x0000 +#define AU1300_GPIC_PINVALCLR 0x0010 +#define AU1300_GPIC_IPEND 0x0020 +#define AU1300_GPIC_PRIENC 0x0030 +#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */ +#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */ +#define AU1300_GPIC_DMASEL 0x0060 +#define AU1300_GPIC_DEVSEL 0x0080 +#define AU1300_GPIC_DEVCLR 0x0090 +#define AU1300_GPIC_RSTVAL 0x00a0 +/* pin configuration space. one 32bit register for up to 128 IRQs */ +#define AU1300_GPIC_PINCFG 0x1000 + +#define GPIC_GPIO_TO_BIT(gpio) \ + (1 << ((gpio) & 0x1f)) + +#define GPIC_GPIO_BANKOFF(gpio) \ + (((gpio) >> 5) * 4) + +/* Pin Control bits: who owns the pin, what does it do */ +#define GPIC_CFG_PC_GPIN 0 +#define GPIC_CFG_PC_DEV 1 +#define GPIC_CFG_PC_GPOLOW 2 +#define GPIC_CFG_PC_GPOHIGH 3 +#define GPIC_CFG_PC_MASK 3 + +/* assign pin to MIPS IRQ line */ +#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2) +#define GPIC_CFG_IL_MASK (3 << 2) + +/* pin interrupt type setup */ +#define GPIC_CFG_IC_OFF (0 << 4) +#define GPIC_CFG_IC_LEVEL_LOW (1 << 4) +#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4) +#define GPIC_CFG_IC_EDGE_FALL (5 << 4) +#define GPIC_CFG_IC_EDGE_RISE (6 << 4) +#define GPIC_CFG_IC_EDGE_BOTH (7 << 4) +#define GPIC_CFG_IC_MASK (7 << 4) + +/* allow interrupt to wake cpu from 'wait' */ +#define GPIC_CFG_IDLEWAKE (1 << 7) + +/***********************************************************************/ + +/* Au1000 SDRAM memory controller register offsets */ +#define AU1000_MEM_SDMODE0 0x0000 +#define AU1000_MEM_SDMODE1 0x0004 +#define AU1000_MEM_SDMODE2 0x0008 +#define AU1000_MEM_SDADDR0 0x000C +#define AU1000_MEM_SDADDR1 0x0010 +#define AU1000_MEM_SDADDR2 0x0014 +#define AU1000_MEM_SDREFCFG 0x0018 +#define AU1000_MEM_SDPRECMD 0x001C +#define AU1000_MEM_SDAUTOREF 0x0020 +#define AU1000_MEM_SDWRMD0 0x0024 +#define AU1000_MEM_SDWRMD1 0x0028 +#define AU1000_MEM_SDWRMD2 0x002C +#define AU1000_MEM_SDSLEEP 0x0030 +#define AU1000_MEM_SDSMCKE 0x0034 + +/* MEM_SDMODE register content definitions */ +#define MEM_SDMODE_F (1 << 22) +#define MEM_SDMODE_SR (1 << 21) +#define MEM_SDMODE_BS (1 << 20) +#define MEM_SDMODE_RS (3 << 18) +#define MEM_SDMODE_CS (7 << 15) +#define MEM_SDMODE_TRAS (15 << 11) +#define MEM_SDMODE_TMRD (3 << 9) +#define MEM_SDMODE_TWR (3 << 7) +#define MEM_SDMODE_TRP (3 << 5) +#define MEM_SDMODE_TRCD (3 << 3) +#define MEM_SDMODE_TCL (7 << 0) + +#define MEM_SDMODE_BS_2Bank (0 << 20) +#define MEM_SDMODE_BS_4Bank (1 << 20) +#define MEM_SDMODE_RS_11Row (0 << 18) +#define MEM_SDMODE_RS_12Row (1 << 18) +#define MEM_SDMODE_RS_13Row (2 << 18) +#define MEM_SDMODE_RS_N(N) ((N) << 18) +#define MEM_SDMODE_CS_7Col (0 << 15) +#define MEM_SDMODE_CS_8Col (1 << 15) +#define MEM_SDMODE_CS_9Col (2 << 15) +#define MEM_SDMODE_CS_10Col (3 << 15) +#define MEM_SDMODE_CS_11Col (4 << 15) +#define MEM_SDMODE_CS_N(N) ((N) << 15) +#define MEM_SDMODE_TRAS_N(N) ((N) << 11) +#define MEM_SDMODE_TMRD_N(N) ((N) << 9) +#define MEM_SDMODE_TWR_N(N) ((N) << 7) +#define MEM_SDMODE_TRP_N(N) ((N) << 5) +#define MEM_SDMODE_TRCD_N(N) ((N) << 3) +#define MEM_SDMODE_TCL_N(N) ((N) << 0) + +/* MEM_SDADDR register contents definitions */ +#define MEM_SDADDR_E (1 << 20) +#define MEM_SDADDR_CSBA (0x03FF << 10) +#define MEM_SDADDR_CSMASK (0x03FF << 0) +#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) +#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) + +/* MEM_SDREFCFG register content definitions */ +#define MEM_SDREFCFG_TRC (15 << 28) +#define MEM_SDREFCFG_TRPM (3 << 26) +#define MEM_SDREFCFG_E (1 << 25) +#define MEM_SDREFCFG_RE (0x1ffffff << 0) +#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) +#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) +#define MEM_SDREFCFG_REF_N(N) (N) + +/* Au1550 SDRAM Register Offsets */ +#define AU1550_MEM_SDMODE0 0x0800 +#define AU1550_MEM_SDMODE1 0x0808 +#define AU1550_MEM_SDMODE2 0x0810 +#define AU1550_MEM_SDADDR0 0x0820 +#define AU1550_MEM_SDADDR1 0x0828 +#define AU1550_MEM_SDADDR2 0x0830 +#define AU1550_MEM_SDCONFIGA 0x0840 +#define AU1550_MEM_SDCONFIGB 0x0848 +#define AU1550_MEM_SDSTAT 0x0850 +#define AU1550_MEM_SDERRADDR 0x0858 +#define AU1550_MEM_SDSTRIDE0 0x0860 +#define AU1550_MEM_SDSTRIDE1 0x0868 +#define AU1550_MEM_SDSTRIDE2 0x0870 +#define AU1550_MEM_SDWRMD0 0x0880 +#define AU1550_MEM_SDWRMD1 0x0888 +#define AU1550_MEM_SDWRMD2 0x0890 +#define AU1550_MEM_SDPRECMD 0x08C0 +#define AU1550_MEM_SDAUTOREF 0x08C8 +#define AU1550_MEM_SDSREF 0x08D0 +#define AU1550_MEM_SDSLEEP MEM_SDSREF + +/* Static Bus Controller */ +#define MEM_STCFG0 0xB4001000 +#define MEM_STTIME0 0xB4001004 +#define MEM_STADDR0 0xB4001008 + +#define MEM_STCFG1 0xB4001010 +#define MEM_STTIME1 0xB4001014 +#define MEM_STADDR1 0xB4001018 + +#define MEM_STCFG2 0xB4001020 +#define MEM_STTIME2 0xB4001024 +#define MEM_STADDR2 0xB4001028 + +#define MEM_STCFG3 0xB4001030 +#define MEM_STTIME3 0xB4001034 +#define MEM_STADDR3 0xB4001038 + +#define MEM_STNDCTL 0xB4001100 +#define MEM_STSTAT 0xB4001104 + +#define MEM_STNAND_CMD 0x0 +#define MEM_STNAND_ADDR 0x4 +#define MEM_STNAND_DATA 0x20 -#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST -#define INTX 0xFF /* not valid */ /* Programmable Counters 0 and 1 */ #define SYS_BASE 0xB1900000 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) -# define SYS_CNTRL_E1S (1 << 23) -# define SYS_CNTRL_T1S (1 << 20) -# define SYS_CNTRL_M21 (1 << 19) -# define SYS_CNTRL_M11 (1 << 18) -# define SYS_CNTRL_M01 (1 << 17) -# define SYS_CNTRL_C1S (1 << 16) +# define SYS_CNTRL_E1S (1 << 23) +# define SYS_CNTRL_T1S (1 << 20) +# define SYS_CNTRL_M21 (1 << 19) +# define SYS_CNTRL_M11 (1 << 18) +# define SYS_CNTRL_M01 (1 << 17) +# define SYS_CNTRL_C1S (1 << 16) # define SYS_CNTRL_BP (1 << 14) -# define SYS_CNTRL_EN1 (1 << 13) -# define SYS_CNTRL_BT1 (1 << 12) -# define SYS_CNTRL_EN0 (1 << 11) -# define SYS_CNTRL_BT0 (1 << 10) +# define SYS_CNTRL_EN1 (1 << 13) +# define SYS_CNTRL_BT1 (1 << 12) +# define SYS_CNTRL_EN0 (1 << 11) +# define SYS_CNTRL_BT0 (1 << 10) # define SYS_CNTRL_E0 (1 << 8) -# define SYS_CNTRL_E0S (1 << 7) -# define SYS_CNTRL_32S (1 << 5) -# define SYS_CNTRL_T0S (1 << 4) -# define SYS_CNTRL_M20 (1 << 3) -# define SYS_CNTRL_M10 (1 << 2) -# define SYS_CNTRL_M00 (1 << 1) -# define SYS_CNTRL_C0S (1 << 0) +# define SYS_CNTRL_E0S (1 << 7) +# define SYS_CNTRL_32S (1 << 5) +# define SYS_CNTRL_T0S (1 << 4) +# define SYS_CNTRL_M20 (1 << 3) +# define SYS_CNTRL_M10 (1 << 2) +# define SYS_CNTRL_M00 (1 << 1) +# define SYS_CNTRL_C0S (1 << 0) /* Programmable Counter 0 Registers */ #define SYS_TOYTRIM (SYS_BASE + 0) @@ -1025,100 +1005,50 @@ enum soc_au1200_ints { /* I2S Controller */ #define I2S_DATA 0xB1000000 -# define I2S_DATA_MASK 0xffffff +# define I2S_DATA_MASK 0xffffff #define I2S_CONFIG 0xB1000004 -# define I2S_CONFIG_XU (1 << 25) -# define I2S_CONFIG_XO (1 << 24) -# define I2S_CONFIG_RU (1 << 23) -# define I2S_CONFIG_RO (1 << 22) -# define I2S_CONFIG_TR (1 << 21) -# define I2S_CONFIG_TE (1 << 20) -# define I2S_CONFIG_TF (1 << 19) -# define I2S_CONFIG_RR (1 << 18) -# define I2S_CONFIG_RE (1 << 17) -# define I2S_CONFIG_RF (1 << 16) -# define I2S_CONFIG_PD (1 << 11) -# define I2S_CONFIG_LB (1 << 10) -# define I2S_CONFIG_IC (1 << 9) +# define I2S_CONFIG_XU (1 << 25) +# define I2S_CONFIG_XO (1 << 24) +# define I2S_CONFIG_RU (1 << 23) +# define I2S_CONFIG_RO (1 << 22) +# define I2S_CONFIG_TR (1 << 21) +# define I2S_CONFIG_TE (1 << 20) +# define I2S_CONFIG_TF (1 << 19) +# define I2S_CONFIG_RR (1 << 18) +# define I2S_CONFIG_RE (1 << 17) +# define I2S_CONFIG_RF (1 << 16) +# define I2S_CONFIG_PD (1 << 11) +# define I2S_CONFIG_LB (1 << 10) +# define I2S_CONFIG_IC (1 << 9) # define I2S_CONFIG_FM_BIT 7 # define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) # define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) # define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) # define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) -# define I2S_CONFIG_TN (1 << 6) -# define I2S_CONFIG_RN (1 << 5) +# define I2S_CONFIG_TN (1 << 6) +# define I2S_CONFIG_RN (1 << 5) # define I2S_CONFIG_SZ_BIT 0 # define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) #define I2S_CONTROL 0xB1000008 -# define I2S_CONTROL_D (1 << 1) +# define I2S_CONTROL_D (1 << 1) # define I2S_CONTROL_CE (1 << 0) -/* USB Host Controller */ -#ifndef USB_OHCI_LEN -#define USB_OHCI_LEN 0x00100000 -#endif - -#ifndef CONFIG_SOC_AU1200 - -/* USB Device Controller */ -#define USBD_EP0RD 0xB0200000 -#define USBD_EP0WR 0xB0200004 -#define USBD_EP2WR 0xB0200008 -#define USBD_EP3WR 0xB020000C -#define USBD_EP4RD 0xB0200010 -#define USBD_EP5RD 0xB0200014 -#define USBD_INTEN 0xB0200018 -#define USBD_INTSTAT 0xB020001C -# define USBDEV_INT_SOF (1 << 12) -# define USBDEV_INT_HF_BIT 6 -# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) -# define USBDEV_INT_CMPLT_BIT 0 -# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) -#define USBD_CONFIG 0xB0200020 -#define USBD_EP0CS 0xB0200024 -#define USBD_EP2CS 0xB0200028 -#define USBD_EP3CS 0xB020002C -#define USBD_EP4CS 0xB0200030 -#define USBD_EP5CS 0xB0200034 -# define USBDEV_CS_SU (1 << 14) -# define USBDEV_CS_NAK (1 << 13) -# define USBDEV_CS_ACK (1 << 12) -# define USBDEV_CS_BUSY (1 << 11) -# define USBDEV_CS_TSIZE_BIT 1 -# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) -# define USBDEV_CS_STALL (1 << 0) -#define USBD_EP0RDSTAT 0xB0200040 -#define USBD_EP0WRSTAT 0xB0200044 -#define USBD_EP2WRSTAT 0xB0200048 -#define USBD_EP3WRSTAT 0xB020004C -#define USBD_EP4RDSTAT 0xB0200050 -#define USBD_EP5RDSTAT 0xB0200054 -# define USBDEV_FSTAT_FLUSH (1 << 6) -# define USBDEV_FSTAT_UF (1 << 5) -# define USBDEV_FSTAT_OF (1 << 4) -# define USBDEV_FSTAT_FCNT_BIT 0 -# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) -#define USBD_ENABLE 0xB0200058 -# define USBDEV_ENABLE (1 << 1) -# define USBDEV_CE (1 << 0) - -#endif /* !CONFIG_SOC_AU1200 */ /* Ethernet Controllers */ /* 4 byte offsets from AU1000_ETH_BASE */ #define MAC_CONTROL 0x0 -# define MAC_RX_ENABLE (1 << 2) -# define MAC_TX_ENABLE (1 << 3) -# define MAC_DEF_CHECK (1 << 5) -# define MAC_SET_BL(X) (((X) & 0x3) << 6) +# define MAC_RX_ENABLE (1 << 2) +# define MAC_TX_ENABLE (1 << 3) +# define MAC_DEF_CHECK (1 << 5) +# define MAC_SET_BL(X) (((X) & 0x3) << 6) # define MAC_AUTO_PAD (1 << 8) # define MAC_DISABLE_RETRY (1 << 10) # define MAC_DISABLE_BCAST (1 << 11) # define MAC_LATE_COL (1 << 12) -# define MAC_HASH_MODE (1 << 13) -# define MAC_HASH_ONLY (1 << 15) +# define MAC_HASH_MODE (1 << 13) +# define MAC_HASH_ONLY (1 << 15) # define MAC_PASS_ALL (1 << 16) # define MAC_INVERSE_FILTER (1 << 17) # define MAC_PROMISCUOUS (1 << 18) @@ -1155,9 +1085,9 @@ enum soc_au1200_ints { # define MAC_EN_RESET0 (1 << 1) # define MAC_EN_TOSS (0 << 2) # define MAC_EN_CACHEABLE (1 << 3) -# define MAC_EN_RESET1 (1 << 4) -# define MAC_EN_RESET2 (1 << 5) -# define MAC_DMA_RESET (1 << 6) +# define MAC_EN_RESET1 (1 << 4) +# define MAC_EN_RESET2 (1 << 5) +# define MAC_DMA_RESET (1 << 6) /* Ethernet Controller DMA Channels */ @@ -1167,7 +1097,7 @@ enum soc_au1200_ints { #define MAC_TX_BUFF0_STATUS 0x0 # define TX_FRAME_ABORTED (1 << 0) # define TX_JAB_TIMEOUT (1 << 1) -# define TX_NO_CARRIER (1 << 2) +# define TX_NO_CARRIER (1 << 2) # define TX_LOSS_CARRIER (1 << 3) # define TX_EXC_DEF (1 << 4) # define TX_LATE_COLL_ABORT (1 << 5) @@ -1178,7 +1108,7 @@ enum soc_au1200_ints { # define TX_COLL_CNT_MASK (0xF << 10) # define TX_PKT_RETRY (1 << 31) #define MAC_TX_BUFF0_ADDR 0x4 -# define TX_DMA_ENABLE (1 << 0) +# define TX_DMA_ENABLE (1 << 0) # define TX_T_DONE (1 << 1) # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) #define MAC_TX_BUFF0_LEN 0x8 @@ -1197,7 +1127,7 @@ enum soc_au1200_ints { /* offsets from MAC_RX_RING_ADDR */ #define MAC_RX_BUFF0_STATUS 0x0 # define RX_FRAME_LEN_MASK 0x3fff -# define RX_WDOG_TIMER (1 << 14) +# define RX_WDOG_TIMER (1 << 14) # define RX_RUNT (1 << 15) # define RX_OVERLEN (1 << 16) # define RX_COLL (1 << 17) @@ -1220,7 +1150,7 @@ enum soc_au1200_ints { RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) #define MAC_RX_BUFF0_ADDR 0x4 -# define RX_DMA_ENABLE (1 << 0) +# define RX_DMA_ENABLE (1 << 0) # define RX_T_DONE (1 << 1) # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0) @@ -1231,134 +1161,36 @@ enum soc_au1200_ints { #define MAC_RX_BUFF3_STATUS 0x30 #define MAC_RX_BUFF3_ADDR 0x34 -/* UARTS 0-3 */ -#define UART_BASE UART0_ADDR -#ifdef CONFIG_SOC_AU1200 -#define UART_DEBUG_BASE UART1_ADDR -#else -#define UART_DEBUG_BASE UART3_ADDR -#endif - -#define UART_RX 0 /* Receive buffer */ -#define UART_TX 4 /* Transmit buffer */ -#define UART_IER 8 /* Interrupt Enable Register */ -#define UART_IIR 0xC /* Interrupt ID Register */ -#define UART_FCR 0x10 /* FIFO Control Register */ -#define UART_LCR 0x14 /* Line Control Register */ -#define UART_MCR 0x18 /* Modem Control Register */ -#define UART_LSR 0x1C /* Line Status Register */ -#define UART_MSR 0x20 /* Modem Status Register */ -#define UART_CLK 0x28 /* Baud Rate Clock Divider */ -#define UART_MOD_CNTRL 0x100 /* Module Control */ - -#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ -#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ -#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ -#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ -#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */ -#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */ -#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */ -#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */ -#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */ -#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */ -#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */ -#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */ -#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */ - -/* - * These are the definitions for the Line Control Register - */ -#define UART_LCR_SBC 0x40 /* Set break control */ -#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ -#define UART_LCR_EPAR 0x10 /* Even parity select */ -#define UART_LCR_PARITY 0x08 /* Parity Enable */ -#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ -#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ -#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ -#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ -#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ - -/* - * These are the definitions for the Line Status Register - */ -#define UART_LSR_TEMT 0x40 /* Transmitter empty */ -#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ -#define UART_LSR_BI 0x10 /* Break interrupt indicator */ -#define UART_LSR_FE 0x08 /* Frame error indicator */ -#define UART_LSR_PE 0x04 /* Parity error indicator */ -#define UART_LSR_OE 0x02 /* Overrun error indicator */ -#define UART_LSR_DR 0x01 /* Receiver data ready */ - -/* - * These are the definitions for the Interrupt Identification Register - */ -#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ -#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ -#define UART_IIR_MSI 0x00 /* Modem status interrupt */ -#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ -#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ -#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ - -/* - * These are the definitions for the Interrupt Enable Register - */ -#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ -#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ -#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ -#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ - -/* - * These are the definitions for the Modem Control Register - */ -#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ -#define UART_MCR_OUT2 0x08 /* Out2 complement */ -#define UART_MCR_OUT1 0x04 /* Out1 complement */ -#define UART_MCR_RTS 0x02 /* RTS complement */ -#define UART_MCR_DTR 0x01 /* DTR complement */ - -/* - * These are the definitions for the Modem Status Register - */ -#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ -#define UART_MSR_RI 0x40 /* Ring Indicator */ -#define UART_MSR_DSR 0x20 /* Data Set Ready */ -#define UART_MSR_CTS 0x10 /* Clear to Send */ -#define UART_MSR_DDCD 0x08 /* Delta DCD */ -#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ -#define UART_MSR_DDSR 0x02 /* Delta DSR */ -#define UART_MSR_DCTS 0x01 /* Delta CTS */ -#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ - /* SSIO */ #define SSI0_STATUS 0xB1600000 -# define SSI_STATUS_BF (1 << 4) -# define SSI_STATUS_OF (1 << 3) -# define SSI_STATUS_UF (1 << 2) +# define SSI_STATUS_BF (1 << 4) +# define SSI_STATUS_OF (1 << 3) +# define SSI_STATUS_UF (1 << 2) # define SSI_STATUS_D (1 << 1) # define SSI_STATUS_B (1 << 0) #define SSI0_INT 0xB1600004 # define SSI_INT_OI (1 << 3) # define SSI_INT_UI (1 << 2) # define SSI_INT_DI (1 << 1) -#define SSI0_INT_ENABLE 0xB1600008 +#define SSI0_INT_ENABLE 0xB1600008 # define SSI_INTE_OIE (1 << 3) # define SSI_INTE_UIE (1 << 2) # define SSI_INTE_DIE (1 << 1) #define SSI0_CONFIG 0xB1600020 -# define SSI_CONFIG_AO (1 << 24) -# define SSI_CONFIG_DO (1 << 23) +# define SSI_CONFIG_AO (1 << 24) +# define SSI_CONFIG_DO (1 << 23) # define SSI_CONFIG_ALEN_BIT 20 # define SSI_CONFIG_ALEN_MASK (0x7 << 20) # define SSI_CONFIG_DLEN_BIT 16 # define SSI_CONFIG_DLEN_MASK (0x7 << 16) -# define SSI_CONFIG_DD (1 << 11) -# define SSI_CONFIG_AD (1 << 10) +# define SSI_CONFIG_DD (1 << 11) +# define SSI_CONFIG_AD (1 << 10) # define SSI_CONFIG_BM_BIT 8 # define SSI_CONFIG_BM_MASK (0x3 << 8) -# define SSI_CONFIG_CE (1 << 7) -# define SSI_CONFIG_DP (1 << 6) -# define SSI_CONFIG_DL (1 << 5) -# define SSI_CONFIG_EP (1 << 4) +# define SSI_CONFIG_CE (1 << 7) +# define SSI_CONFIG_DP (1 << 6) +# define SSI_CONFIG_DL (1 << 5) +# define SSI_CONFIG_EP (1 << 4) #define SSI0_ADATA 0xB1600024 # define SSI_AD_D (1 << 24) # define SSI_AD_ADDR_BIT 16 @@ -1368,12 +1200,12 @@ enum soc_au1200_ints { #define SSI0_CLKDIV 0xB1600028 #define SSI0_CONTROL 0xB1600100 # define SSI_CONTROL_CD (1 << 1) -# define SSI_CONTROL_E (1 << 0) +# define SSI_CONTROL_E (1 << 0) /* SSI1 */ #define SSI1_STATUS 0xB1680000 #define SSI1_INT 0xB1680004 -#define SSI1_INT_ENABLE 0xB1680008 +#define SSI1_INT_ENABLE 0xB1680008 #define SSI1_CONFIG 0xB1680020 #define SSI1_ADATA 0xB1680024 #define SSI1_CLKDIV 0xB1680028 @@ -1400,8 +1232,8 @@ enum soc_au1200_ints { #define SSI_CONFIG_AO (1 << 24) #define SSI_CONFIG_DO (1 << 23) -#define SSI_CONFIG_ALEN (7 << 20) -#define SSI_CONFIG_DLEN (15 << 16) +#define SSI_CONFIG_ALEN (7 << 20) +#define SSI_CONFIG_DLEN (15 << 16) #define SSI_CONFIG_DD (1 << 11) #define SSI_CONFIG_AD (1 << 10) #define SSI_CONFIG_BM (3 << 8) @@ -1423,44 +1255,20 @@ enum soc_au1200_ints { #define SSI_ENABLE_CD (1 << 1) #define SSI_ENABLE_E (1 << 0) -/* IrDA Controller */ -#define IRDA_BASE 0xB0300000 -#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00) -#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04) -#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08) -#define IR_RING_SIZE (IRDA_BASE + 0x0C) -#define IR_RING_PROMPT (IRDA_BASE + 0x10) -#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14) -#define IR_INT_CLEAR (IRDA_BASE + 0x18) -#define IR_CONFIG_1 (IRDA_BASE + 0x20) -# define IR_RX_INVERT_LED (1 << 0) -# define IR_TX_INVERT_LED (1 << 1) -# define IR_ST (1 << 2) -# define IR_SF (1 << 3) -# define IR_SIR (1 << 4) -# define IR_MIR (1 << 5) -# define IR_FIR (1 << 6) -# define IR_16CRC (1 << 7) -# define IR_TD (1 << 8) -# define IR_RX_ALL (1 << 9) -# define IR_DMA_ENABLE (1 << 10) -# define IR_RX_ENABLE (1 << 11) -# define IR_TX_ENABLE (1 << 12) -# define IR_LOOPBACK (1 << 14) -# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ - IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) -#define IR_SIR_FLAGS (IRDA_BASE + 0x24) -#define IR_ENABLE (IRDA_BASE + 0x28) -# define IR_RX_STATUS (1 << 9) -# define IR_TX_STATUS (1 << 10) -#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C) -#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30) -#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34) -#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38) -#define IR_CONFIG_2 (IRDA_BASE + 0x3C) -# define IR_MODE_INV (1 << 0) -# define IR_ONE_PIN (1 << 1) -#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40) + +/* + * The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's not + * used to select FIR/SIR mode on the transceiver but as a GPIO. Instead a + * CPLD has to be told about the mode. + */ +#define AU1000_IRDA_PHY_MODE_OFF 0 +#define AU1000_IRDA_PHY_MODE_SIR 1 +#define AU1000_IRDA_PHY_MODE_FIR 2 + +struct au1k_irda_platform_data { + void(*set_phy_mode)(int mode); +}; + /* GPIO */ #define SYS_PINFUNC 0xB190002C @@ -1487,7 +1295,7 @@ enum soc_au1200_ints { # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */ # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */ -/* Au1550 only. Redefines lots of pins */ +/* Au1550 only. Redefines lots of pins */ # define SYS_PF_PSC2_MASK (7 << 17) # define SYS_PF_PSC2_AC97 0 # define SYS_PF_PSC2_SPI 0 @@ -1504,51 +1312,33 @@ enum soc_au1200_ints { # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) /* Au1200 only */ -#ifdef CONFIG_SOC_AU1200 -#define SYS_PINFUNC_DMA (1 << 31) -#define SYS_PINFUNC_S0A (1 << 30) -#define SYS_PINFUNC_S1A (1 << 29) -#define SYS_PINFUNC_LP0 (1 << 28) -#define SYS_PINFUNC_LP1 (1 << 27) -#define SYS_PINFUNC_LD16 (1 << 26) -#define SYS_PINFUNC_LD8 (1 << 25) -#define SYS_PINFUNC_LD1 (1 << 24) -#define SYS_PINFUNC_LD0 (1 << 23) -#define SYS_PINFUNC_P1A (3 << 21) -#define SYS_PINFUNC_P1B (1 << 20) -#define SYS_PINFUNC_FS3 (1 << 19) -#define SYS_PINFUNC_P0A (3 << 17) +#define SYS_PINFUNC_DMA (1 << 31) +#define SYS_PINFUNC_S0A (1 << 30) +#define SYS_PINFUNC_S1A (1 << 29) +#define SYS_PINFUNC_LP0 (1 << 28) +#define SYS_PINFUNC_LP1 (1 << 27) +#define SYS_PINFUNC_LD16 (1 << 26) +#define SYS_PINFUNC_LD8 (1 << 25) +#define SYS_PINFUNC_LD1 (1 << 24) +#define SYS_PINFUNC_LD0 (1 << 23) +#define SYS_PINFUNC_P1A (3 << 21) +#define SYS_PINFUNC_P1B (1 << 20) +#define SYS_PINFUNC_FS3 (1 << 19) +#define SYS_PINFUNC_P0A (3 << 17) #define SYS_PINFUNC_CS (1 << 16) -#define SYS_PINFUNC_CIM (1 << 15) -#define SYS_PINFUNC_P1C (1 << 14) -#define SYS_PINFUNC_U1T (1 << 12) -#define SYS_PINFUNC_U1R (1 << 11) -#define SYS_PINFUNC_EX1 (1 << 10) -#define SYS_PINFUNC_EX0 (1 << 9) -#define SYS_PINFUNC_U0R (1 << 8) +#define SYS_PINFUNC_CIM (1 << 15) +#define SYS_PINFUNC_P1C (1 << 14) +#define SYS_PINFUNC_U1T (1 << 12) +#define SYS_PINFUNC_U1R (1 << 11) +#define SYS_PINFUNC_EX1 (1 << 10) +#define SYS_PINFUNC_EX0 (1 << 9) +#define SYS_PINFUNC_U0R (1 << 8) #define SYS_PINFUNC_MC (1 << 7) -#define SYS_PINFUNC_S0B (1 << 6) -#define SYS_PINFUNC_S0C (1 << 5) -#define SYS_PINFUNC_P0B (1 << 4) -#define SYS_PINFUNC_U0T (1 << 3) -#define SYS_PINFUNC_S1B (1 << 2) -#endif - -#define SYS_TRIOUTRD 0xB1900100 -#define SYS_TRIOUTCLR 0xB1900100 -#define SYS_OUTPUTRD 0xB1900108 -#define SYS_OUTPUTSET 0xB1900108 -#define SYS_OUTPUTCLR 0xB190010C -#define SYS_PINSTATERD 0xB1900110 -#define SYS_PININPUTEN 0xB1900110 - -/* GPIO2, Au1500, Au1550 only */ -#define GPIO2_BASE 0xB1700000 -#define GPIO2_DIR (GPIO2_BASE + 0) -#define GPIO2_OUTPUT (GPIO2_BASE + 8) -#define GPIO2_PINSTATE (GPIO2_BASE + 0xC) -#define GPIO2_INTENABLE (GPIO2_BASE + 0x10) -#define GPIO2_ENABLE (GPIO2_BASE + 0x14) +#define SYS_PINFUNC_S0B (1 << 6) +#define SYS_PINFUNC_S0C (1 << 5) +#define SYS_PINFUNC_P0B (1 << 4) +#define SYS_PINFUNC_U0T (1 << 3) +#define SYS_PINFUNC_S1B (1 << 2) /* Power Management */ #define SYS_SCRATCH0 0xB1900018 @@ -1604,12 +1394,12 @@ enum soc_au1200_ints { # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT) # define SYS_CS_DI2 (1 << 16) # define SYS_CS_CI2 (1 << 15) -#ifdef CONFIG_SOC_AU1100 -# define SYS_CS_ML_BIT 7 + +# define SYS_CS_ML_BIT 7 # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT) # define SYS_CS_DL (1 << 6) # define SYS_CS_CL (1 << 5) -#else + # define SYS_CS_MUH_BIT 12 # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT) # define SYS_CS_DUH (1 << 11) @@ -1618,7 +1408,7 @@ enum soc_au1200_ints { # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT) # define SYS_CS_DUD (1 << 6) # define SYS_CS_CUD (1 << 5) -#endif + # define SYS_CS_MIR_BIT 2 # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT) # define SYS_CS_DIR (1 << 1) @@ -1665,127 +1455,108 @@ enum soc_au1200_ints { # define AC97C_RS (1 << 1) # define AC97C_CE (1 << 0) -/* Secure Digital (SD) Controller */ -#define SD0_XMIT_FIFO 0xB0600000 -#define SD0_RECV_FIFO 0xB0600004 -#define SD1_XMIT_FIFO 0xB0680000 -#define SD1_RECV_FIFO 0xB0680004 - -#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) -/* Au1500 PCI Controller */ -#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */ -#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) -#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) -# define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \ - (1 << 25) | (1 << 26) | (1 << 27)) -#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) -#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) -#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) -#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) -#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) -#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) -#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) -#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) -#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) -#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) -#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) -#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) - -#define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */ -/* - * All of our structures, like PCI resource, have 32-bit members. - * Drivers are expected to do an ioremap on the PCI MEM resource, but it's - * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch - * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and - * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM - * addresses. For PCI I/O, it's simpler because we get to do the ioremap - * ourselves and then adjust the device's resources. +/* The PCI chip selects are outside the 32bit space, and since we can't + * just program the 36bit addresses into BARs, we have to take a chunk + * out of the 32bit space and reserve it for PCI. When these addresses + * are ioremap()ed, they'll be fixed up to the real 36bit address before + * being passed to the real ioremap function. */ -#define Au1500_EXT_CFG 0x600000000ULL -#define Au1500_EXT_CFG_TYPE1 0x680000000ULL -#define Au1500_PCI_IO_START 0x500000000ULL -#define Au1500_PCI_IO_END 0x5000FFFFFULL -#define Au1500_PCI_MEM_START 0x440000000ULL -#define Au1500_PCI_MEM_END 0x44FFFFFFFULL +#define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4) +#define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF) -#define PCI_IO_START 0x00001000 -#define PCI_IO_END 0x000FFFFF -#define PCI_MEM_START 0x40000000 -#define PCI_MEM_END 0x4FFFFFFF +/* for PCI IO it's simpler because we get to do the ioremap ourselves and then + * adjust the device's resources. + */ +#define ALCHEMY_PCI_IOWIN_START 0x00001000 +#define ALCHEMY_PCI_IOWIN_END 0x0000FFFF -#define PCI_FIRST_DEVFN (0 << 3) -#define PCI_LAST_DEVFN (19 << 3) +#ifdef CONFIG_PCI #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ #define IOPORT_RESOURCE_END 0xffffffff #define IOMEM_RESOURCE_START 0x10000000 -#define IOMEM_RESOURCE_END 0xffffffff +#define IOMEM_RESOURCE_END 0xfffffffffULL -#else /* Au1000 and Au1100 and Au1200 */ +#else /* Don't allow any legacy ports probing */ #define IOPORT_RESOURCE_START 0x10000000 #define IOPORT_RESOURCE_END 0xffffffff #define IOMEM_RESOURCE_START 0x10000000 -#define IOMEM_RESOURCE_END 0xffffffff - -#define PCI_IO_START 0 -#define PCI_IO_END 0 -#define PCI_MEM_START 0 -#define PCI_MEM_END 0 -#define PCI_FIRST_DEVFN 0 -#define PCI_LAST_DEVFN 0 +#define IOMEM_RESOURCE_END 0xfffffffffULL #endif -#ifndef _LANGUAGE_ASSEMBLY -typedef volatile struct { - /* 0x0000 */ u32 toytrim; - /* 0x0004 */ u32 toywrite; - /* 0x0008 */ u32 toymatch0; - /* 0x000C */ u32 toymatch1; - /* 0x0010 */ u32 toymatch2; - /* 0x0014 */ u32 cntrctrl; - /* 0x0018 */ u32 scratch0; - /* 0x001C */ u32 scratch1; - /* 0x0020 */ u32 freqctrl0; - /* 0x0024 */ u32 freqctrl1; - /* 0x0028 */ u32 clksrc; - /* 0x002C */ u32 pinfunc; - /* 0x0030 */ u32 reserved0; - /* 0x0034 */ u32 wakemsk; - /* 0x0038 */ u32 endian; - /* 0x003C */ u32 powerctrl; - /* 0x0040 */ u32 toyread; - /* 0x0044 */ u32 rtctrim; - /* 0x0048 */ u32 rtcwrite; - /* 0x004C */ u32 rtcmatch0; - /* 0x0050 */ u32 rtcmatch1; - /* 0x0054 */ u32 rtcmatch2; - /* 0x0058 */ u32 rtcread; - /* 0x005C */ u32 wakesrc; - /* 0x0060 */ u32 cpupll; - /* 0x0064 */ u32 auxpll; - /* 0x0068 */ u32 reserved1; - /* 0x006C */ u32 reserved2; - /* 0x0070 */ u32 reserved3; - /* 0x0074 */ u32 reserved4; - /* 0x0078 */ u32 slppwr; - /* 0x007C */ u32 sleep; - /* 0x0080 */ u32 reserved5[32]; - /* 0x0100 */ u32 trioutrd; -#define trioutclr trioutrd - /* 0x0104 */ u32 reserved6; - /* 0x0108 */ u32 outputrd; -#define outputset outputrd - /* 0x010C */ u32 outputclr; - /* 0x0110 */ u32 pinstaterd; -#define pininputen pinstaterd -} AU1X00_SYS; - -static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE; - -#endif +/* PCI controller block register offsets */ +#define PCI_REG_CMEM 0x0000 +#define PCI_REG_CONFIG 0x0004 +#define PCI_REG_B2BMASK_CCH 0x0008 +#define PCI_REG_B2BBASE0_VID 0x000C +#define PCI_REG_B2BBASE1_SID 0x0010 +#define PCI_REG_MWMASK_DEV 0x0014 +#define PCI_REG_MWBASE_REV_CCL 0x0018 +#define PCI_REG_ERR_ADDR 0x001C +#define PCI_REG_SPEC_INTACK 0x0020 +#define PCI_REG_ID 0x0100 +#define PCI_REG_STATCMD 0x0104 +#define PCI_REG_CLASSREV 0x0108 +#define PCI_REG_PARAM 0x010C +#define PCI_REG_MBAR 0x0110 +#define PCI_REG_TIMEOUT 0x0140 + +/* PCI controller block register bits */ +#define PCI_CMEM_E (1 << 28) /* enable cacheable memory */ +#define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14) +#define PCI_CMEM_CMMASK(x) ((x) & 0x3fff) +#define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */ +#define PCI_CONFIG_ET (1 << 26) /* error in target mode */ +#define PCI_CONFIG_EF (1 << 25) /* fatal error */ +#define PCI_CONFIG_EP (1 << 24) /* parity error */ +#define PCI_CONFIG_EM (1 << 23) /* multiple errors */ +#define PCI_CONFIG_BM (1 << 22) /* bad master error */ +#define PCI_CONFIG_PD (1 << 20) /* PCI Disable */ +#define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */ +#define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */ +#define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */ +#define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */ +#define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */ +#define PCI_CONFIG_IMM (1 << 11) /* int on master abort */ +#define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */ +#define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */ +#define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */ +#define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */ +#define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */ +#define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */ +#define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */ +#define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */ +#define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */ +#define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */ +#define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */ +#define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */ +#define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */ +#define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16) +#define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */ +#define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16) +#define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff) +#define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16) +#define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff) +#define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16) +#define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff) +#define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16) +#define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8) +#define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff) +#define PCI_ID_DID(x) (((x) & 0xffff) << 16) +#define PCI_ID_VID(x) ((x) & 0xffff) +#define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16) +#define PCI_STATCMD_CMD(x) ((x) & 0xffff) +#define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8) +#define PCI_CLASSREV_REV(x) ((x) & 0xff) +#define PCI_PARAM_BIST(x) (((x) & 0xff) << 24) +#define PCI_PARAM_HT(x) (((x) & 0xff) << 16) +#define PCI_PARAM_LT(x) (((x) & 0xff) << 8) +#define PCI_PARAM_CLS(x) ((x) & 0xff) +#define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */ +#define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */ #endif diff --git a/arch/mips/include/asm/mach-au1x00/au1000_dma.h b/arch/mips/include/asm/mach-au1x00/au1000_dma.h index c333b4e1cd4..7cedca5a305 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000_dma.h +++ b/arch/mips/include/asm/mach-au1x00/au1000_dma.h @@ -33,13 +33,8 @@ #include <linux/io.h> /* need byte IO */ #include <linux/spinlock.h> /* And spinlocks */ #include <linux/delay.h> -#include <asm/system.h> -#define NUM_AU1000_DMA_CHANNELS 8 - -/* DMA Channel Base Addresses */ -#define DMA_CHANNEL_BASE 0xB4002000 -#define DMA_CHANNEL_LEN 0x00000100 +#define NUM_AU1000_DMA_CHANNELS 8 /* DMA Channel Register Offsets */ #define DMA_MODE_SET 0x00000000 @@ -52,7 +47,7 @@ #define DMA_DS (1 << 15) #define DMA_BE (1 << 13) #define DMA_DR (1 << 12) -#define DMA_TS8 (1 << 11) +#define DMA_TS8 (1 << 11) #define DMA_DW_BIT 9 #define DMA_DW_MASK (0x03 << DMA_DW_BIT) #define DMA_DW8 (0 << DMA_DW_BIT) @@ -64,9 +59,9 @@ #define DMA_GO (1 << 5) #define DMA_AB (1 << 4) #define DMA_D1 (1 << 3) -#define DMA_BE1 (1 << 2) +#define DMA_BE1 (1 << 2) #define DMA_D0 (1 << 1) -#define DMA_BE0 (1 << 0) +#define DMA_BE0 (1 << 0) #define DMA_PERIPHERAL_ADDR 0x00000008 #define DMA_BUFFER0_START 0x0000000C @@ -251,7 +246,7 @@ static inline void init_dma(unsigned int dmanr) mode |= DMA_IE; au_writel(~mode, chan->io + DMA_MODE_CLEAR); - au_writel(mode, chan->io + DMA_MODE_SET); + au_writel(mode, chan->io + DMA_MODE_SET); } /* diff --git a/arch/mips/include/asm/mach-au1x00/au1000_gpio.h b/arch/mips/include/asm/mach-au1x00/au1000_gpio.h deleted file mode 100644 index d8c96fda554..00000000000 --- a/arch/mips/include/asm/mach-au1x00/au1000_gpio.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * FILE NAME au1000_gpio.h - * - * BRIEF MODULE DESCRIPTION - * API to Alchemy Au1xx0 GPIO device. - * - * Author: MontaVista Software, Inc. <source@mvista.com> - * Steve Longerbeam - * - * Copyright 2001, 2008 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __AU1000_GPIO_H -#define __AU1000_GPIO_H - -#include <linux/ioctl.h> - -#define AU1000GPIO_IOC_MAGIC 'A' - -#define AU1000GPIO_IN _IOR(AU1000GPIO_IOC_MAGIC, 0, int) -#define AU1000GPIO_SET _IOW(AU1000GPIO_IOC_MAGIC, 1, int) -#define AU1000GPIO_CLEAR _IOW(AU1000GPIO_IOC_MAGIC, 2, int) -#define AU1000GPIO_OUT _IOW(AU1000GPIO_IOC_MAGIC, 3, int) -#define AU1000GPIO_TRISTATE _IOW(AU1000GPIO_IOC_MAGIC, 4, int) -#define AU1000GPIO_AVAIL_MASK _IOR(AU1000GPIO_IOC_MAGIC, 5, int) - -#ifdef __KERNEL__ -extern u32 get_au1000_avail_gpio_mask(void); -extern int au1000gpio_tristate(u32 data); -extern int au1000gpio_in(u32 *data); -extern int au1000gpio_set(u32 data); -extern int au1000gpio_clear(u32 data); -extern int au1000gpio_out(u32 data); -#endif - -#endif diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h index c35e2091849..cadab91cee2 100644 --- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h +++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h @@ -46,6 +46,7 @@ struct au1xmmc_platform_data { int(*card_readonly)(void *mmc_host); void(*set_power)(void *mmc_host, int state); struct led_classdev *led; + unsigned long mask_host_caps; }; #define SD0_BASE 0xB0600000 @@ -129,8 +130,10 @@ struct au1xmmc_platform_data { #define SD_CONFIG2_DF (0x00000008) #define SD_CONFIG2_DC (0x00000010) #define SD_CONFIG2_xx2 (0x000000e0) +#define SD_CONFIG2_BB (0x00000080) #define SD_CONFIG2_WB (0x00000100) #define SD_CONFIG2_RW (0x00000200) +#define SD_CONFIG2_DP (0x00000400) /* @@ -145,7 +148,7 @@ struct au1xmmc_platform_data { /* * SD_STATUS bit definitions. */ -#define SD_STATUS_DCRCW (0x00000007) +#define SD_STATUS_DCRCW (0x00000007) #define SD_STATUS_xx1 (0x00000008) #define SD_STATUS_CB (0x00000010) #define SD_STATUS_DB (0x00000020) @@ -205,4 +208,3 @@ struct au1xmmc_platform_data { #endif /* __ASM_AU1100_MMC_H */ - diff --git a/arch/mips/include/asm/mach-au1x00/au1200fb.h b/arch/mips/include/asm/mach-au1x00/au1200fb.h new file mode 100644 index 00000000000..b3c87cc64bb --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/au1200fb.h @@ -0,0 +1,14 @@ +/* + * platform data for au1200fb driver. + */ + +#ifndef _AU1200FB_PLAT_H_ +#define _AU1200FB_PLAT_H_ + +struct au1200fb_platdata { + int (*panel_index)(void); + int (*panel_init)(void); + int (*panel_shutdown)(void); +}; + +#endif diff --git a/arch/mips/include/asm/mach-au1x00/au1550nd.h b/arch/mips/include/asm/mach-au1x00/au1550nd.h new file mode 100644 index 00000000000..ad4c0a03afe --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/au1550nd.h @@ -0,0 +1,16 @@ +/* + * platform data for the Au1550 NAND driver + */ + +#ifndef _AU1550ND_H_ +#define _AU1550ND_H_ + +#include <linux/mtd/partitions.h> + +struct au1550nd_platdata { + struct mtd_partition *parts; + int num_parts; + int devwidth; /* 0 = 8bit device, 1 = 16bit device */ +}; + +#endif diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx.h b/arch/mips/include/asm/mach-au1x00/au1xxx.h deleted file mode 100644 index 1b3655090ed..00000000000 --- a/arch/mips/include/asm/mach-au1x00/au1xxx.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef _AU1XXX_H_ -#define _AU1XXX_H_ - -#include <asm/mach-au1x00/au1000.h> - -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \ - defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550) -#include <asm/mach-db1x00/db1x00.h> - -#elif defined(CONFIG_MIPS_PB1550) -#include <asm/mach-pb1x00/pb1550.h> - -#elif defined(CONFIG_MIPS_PB1200) -#include <asm/mach-pb1x00/pb1200.h> - -#elif defined(CONFIG_MIPS_DB1200) -#include <asm/mach-db1x00/db1200.h> - -#endif - -#endif /* _AU1XXX_H_ */ diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index 06f68f43800..ca8077afac4 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -37,14 +37,6 @@ #ifndef _LANGUAGE_ASSEMBLY -/* - * The DMA base addresses. - * The channels are every 256 bytes (0x0100) from the channel 0 base. - * Interrupt status/enable is bits 15:0 for channels 15 to zero. - */ -#define DDMA_GLOBAL_BASE 0xb4003000 -#define DDMA_CHANNEL_BASE 0xb4002000 - typedef volatile struct dbdma_global { u32 ddma_config; u32 ddma_intstat; @@ -111,7 +103,7 @@ typedef volatile struct au1xxx_ddma_desc { * Lets have some SW data following -- make sure it's 32 bytes. */ u32 sw_status; - u32 sw_context; + u32 sw_context; u32 sw_reserved[6]; } au1x_ddma_desc_t; @@ -131,69 +123,96 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */ #define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */ -#define SW_STATUS_INUSE (1 << 0) +#define SW_STATUS_INUSE (1 << 0) /* Command 0 device IDs. */ -#ifdef CONFIG_SOC_AU1550 -#define DSCR_CMD0_UART0_TX 0 -#define DSCR_CMD0_UART0_RX 1 -#define DSCR_CMD0_UART3_TX 2 -#define DSCR_CMD0_UART3_RX 3 -#define DSCR_CMD0_DMA_REQ0 4 -#define DSCR_CMD0_DMA_REQ1 5 -#define DSCR_CMD0_DMA_REQ2 6 -#define DSCR_CMD0_DMA_REQ3 7 -#define DSCR_CMD0_USBDEV_RX0 8 -#define DSCR_CMD0_USBDEV_TX0 9 -#define DSCR_CMD0_USBDEV_TX1 10 -#define DSCR_CMD0_USBDEV_TX2 11 -#define DSCR_CMD0_USBDEV_RX3 12 -#define DSCR_CMD0_USBDEV_RX4 13 -#define DSCR_CMD0_PSC0_TX 14 -#define DSCR_CMD0_PSC0_RX 15 -#define DSCR_CMD0_PSC1_TX 16 -#define DSCR_CMD0_PSC1_RX 17 -#define DSCR_CMD0_PSC2_TX 18 -#define DSCR_CMD0_PSC2_RX 19 -#define DSCR_CMD0_PSC3_TX 20 -#define DSCR_CMD0_PSC3_RX 21 -#define DSCR_CMD0_PCI_WRITE 22 -#define DSCR_CMD0_NAND_FLASH 23 -#define DSCR_CMD0_MAC0_RX 24 -#define DSCR_CMD0_MAC0_TX 25 -#define DSCR_CMD0_MAC1_RX 26 -#define DSCR_CMD0_MAC1_TX 27 -#endif /* CONFIG_SOC_AU1550 */ - -#ifdef CONFIG_SOC_AU1200 -#define DSCR_CMD0_UART0_TX 0 -#define DSCR_CMD0_UART0_RX 1 -#define DSCR_CMD0_UART1_TX 2 -#define DSCR_CMD0_UART1_RX 3 -#define DSCR_CMD0_DMA_REQ0 4 -#define DSCR_CMD0_DMA_REQ1 5 -#define DSCR_CMD0_MAE_BE 6 -#define DSCR_CMD0_MAE_FE 7 -#define DSCR_CMD0_SDMS_TX0 8 -#define DSCR_CMD0_SDMS_RX0 9 -#define DSCR_CMD0_SDMS_TX1 10 -#define DSCR_CMD0_SDMS_RX1 11 -#define DSCR_CMD0_AES_TX 13 -#define DSCR_CMD0_AES_RX 12 -#define DSCR_CMD0_PSC0_TX 14 -#define DSCR_CMD0_PSC0_RX 15 -#define DSCR_CMD0_PSC1_TX 16 -#define DSCR_CMD0_PSC1_RX 17 -#define DSCR_CMD0_CIM_RXA 18 -#define DSCR_CMD0_CIM_RXB 19 -#define DSCR_CMD0_CIM_RXC 20 -#define DSCR_CMD0_MAE_BOTH 21 -#define DSCR_CMD0_LCD 22 -#define DSCR_CMD0_NAND_FLASH 23 -#define DSCR_CMD0_PSC0_SYNC 24 -#define DSCR_CMD0_PSC1_SYNC 25 -#define DSCR_CMD0_CIM_SYNC 26 -#endif /* CONFIG_SOC_AU1200 */ +#define AU1550_DSCR_CMD0_UART0_TX 0 +#define AU1550_DSCR_CMD0_UART0_RX 1 +#define AU1550_DSCR_CMD0_UART3_TX 2 +#define AU1550_DSCR_CMD0_UART3_RX 3 +#define AU1550_DSCR_CMD0_DMA_REQ0 4 +#define AU1550_DSCR_CMD0_DMA_REQ1 5 +#define AU1550_DSCR_CMD0_DMA_REQ2 6 +#define AU1550_DSCR_CMD0_DMA_REQ3 7 +#define AU1550_DSCR_CMD0_USBDEV_RX0 8 +#define AU1550_DSCR_CMD0_USBDEV_TX0 9 +#define AU1550_DSCR_CMD0_USBDEV_TX1 10 +#define AU1550_DSCR_CMD0_USBDEV_TX2 11 +#define AU1550_DSCR_CMD0_USBDEV_RX3 12 +#define AU1550_DSCR_CMD0_USBDEV_RX4 13 +#define AU1550_DSCR_CMD0_PSC0_TX 14 +#define AU1550_DSCR_CMD0_PSC0_RX 15 +#define AU1550_DSCR_CMD0_PSC1_TX 16 +#define AU1550_DSCR_CMD0_PSC1_RX 17 +#define AU1550_DSCR_CMD0_PSC2_TX 18 +#define AU1550_DSCR_CMD0_PSC2_RX 19 +#define AU1550_DSCR_CMD0_PSC3_TX 20 +#define AU1550_DSCR_CMD0_PSC3_RX 21 +#define AU1550_DSCR_CMD0_PCI_WRITE 22 +#define AU1550_DSCR_CMD0_NAND_FLASH 23 +#define AU1550_DSCR_CMD0_MAC0_RX 24 +#define AU1550_DSCR_CMD0_MAC0_TX 25 +#define AU1550_DSCR_CMD0_MAC1_RX 26 +#define AU1550_DSCR_CMD0_MAC1_TX 27 + +#define AU1200_DSCR_CMD0_UART0_TX 0 +#define AU1200_DSCR_CMD0_UART0_RX 1 +#define AU1200_DSCR_CMD0_UART1_TX 2 +#define AU1200_DSCR_CMD0_UART1_RX 3 +#define AU1200_DSCR_CMD0_DMA_REQ0 4 +#define AU1200_DSCR_CMD0_DMA_REQ1 5 +#define AU1200_DSCR_CMD0_MAE_BE 6 +#define AU1200_DSCR_CMD0_MAE_FE 7 +#define AU1200_DSCR_CMD0_SDMS_TX0 8 +#define AU1200_DSCR_CMD0_SDMS_RX0 9 +#define AU1200_DSCR_CMD0_SDMS_TX1 10 +#define AU1200_DSCR_CMD0_SDMS_RX1 11 +#define AU1200_DSCR_CMD0_AES_TX 13 +#define AU1200_DSCR_CMD0_AES_RX 12 +#define AU1200_DSCR_CMD0_PSC0_TX 14 +#define AU1200_DSCR_CMD0_PSC0_RX 15 +#define AU1200_DSCR_CMD0_PSC1_TX 16 +#define AU1200_DSCR_CMD0_PSC1_RX 17 +#define AU1200_DSCR_CMD0_CIM_RXA 18 +#define AU1200_DSCR_CMD0_CIM_RXB 19 +#define AU1200_DSCR_CMD0_CIM_RXC 20 +#define AU1200_DSCR_CMD0_MAE_BOTH 21 +#define AU1200_DSCR_CMD0_LCD 22 +#define AU1200_DSCR_CMD0_NAND_FLASH 23 +#define AU1200_DSCR_CMD0_PSC0_SYNC 24 +#define AU1200_DSCR_CMD0_PSC1_SYNC 25 +#define AU1200_DSCR_CMD0_CIM_SYNC 26 + +#define AU1300_DSCR_CMD0_UART0_TX 0 +#define AU1300_DSCR_CMD0_UART0_RX 1 +#define AU1300_DSCR_CMD0_UART1_TX 2 +#define AU1300_DSCR_CMD0_UART1_RX 3 +#define AU1300_DSCR_CMD0_UART2_TX 4 +#define AU1300_DSCR_CMD0_UART2_RX 5 +#define AU1300_DSCR_CMD0_UART3_TX 6 +#define AU1300_DSCR_CMD0_UART3_RX 7 +#define AU1300_DSCR_CMD0_SDMS_TX0 8 +#define AU1300_DSCR_CMD0_SDMS_RX0 9 +#define AU1300_DSCR_CMD0_SDMS_TX1 10 +#define AU1300_DSCR_CMD0_SDMS_RX1 11 +#define AU1300_DSCR_CMD0_AES_TX 12 +#define AU1300_DSCR_CMD0_AES_RX 13 +#define AU1300_DSCR_CMD0_PSC0_TX 14 +#define AU1300_DSCR_CMD0_PSC0_RX 15 +#define AU1300_DSCR_CMD0_PSC1_TX 16 +#define AU1300_DSCR_CMD0_PSC1_RX 17 +#define AU1300_DSCR_CMD0_PSC2_TX 18 +#define AU1300_DSCR_CMD0_PSC2_RX 19 +#define AU1300_DSCR_CMD0_PSC3_TX 20 +#define AU1300_DSCR_CMD0_PSC3_RX 21 +#define AU1300_DSCR_CMD0_LCD 22 +#define AU1300_DSCR_CMD0_NAND_FLASH 23 +#define AU1300_DSCR_CMD0_SDMS_TX2 24 +#define AU1300_DSCR_CMD0_SDMS_RX2 25 +#define AU1300_DSCR_CMD0_CIM_SYNC 26 +#define AU1300_DSCR_CMD0_UDMA 27 +#define AU1300_DSCR_CMD0_DMA_REQ0 28 +#define AU1300_DSCR_CMD0_DMA_REQ1 29 #define DSCR_CMD0_THROTTLE 30 #define DSCR_CMD0_ALWAYS 31 @@ -279,7 +298,7 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_NXTPTR_MS (1 << 27) /* The number of DBDMA channels. */ -#define NUM_DBDMA_CHANS 16 +#define NUM_DBDMA_CHANS 16 /* * DDMA API definitions @@ -297,7 +316,7 @@ typedef struct dbdma_device_table { typedef struct dbdma_chan_config { - spinlock_t lock; + spinlock_t lock; u32 chan_flags; u32 chan_index; @@ -305,6 +324,7 @@ typedef struct dbdma_chan_config { dbdev_tab_t *chan_dest; au1x_dma_chan_t *chan_ptr; au1x_ddma_desc_t *chan_desc_base; + u32 cdb_membase; /* kmalloc base of above */ au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr; void *chan_callparam; void (*chan_callback)(int, void *); @@ -338,8 +358,8 @@ u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits); u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries); /* Put buffers on source/destination descriptors. */ -u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags); -u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags); +u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags); +u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags); /* Get a buffer from the destination descriptor. */ u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes); @@ -357,29 +377,6 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr); u32 au1xxx_ddma_add_device(dbdev_tab_t *dev); extern void au1xxx_ddma_del_device(u32 devid); void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); -#ifdef CONFIG_PM -void au1xxx_dbdma_suspend(void); -void au1xxx_dbdma_resume(void); -#endif - - -/* - * Some compatibilty macros -- needed to make changes to API - * without breaking existing drivers. - */ -#define au1xxx_dbdma_put_source(chanid, buf, nbytes) \ - _au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) -#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) \ - _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) -#define put_source_flags(chanid, buf, nbytes, flags) \ - au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) - -#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) \ - _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) -#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) \ - _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) -#define put_dest_flags(chanid, buf, nbytes, flags) \ - au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) /* * Flags for the put_source/put_dest functions. diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h new file mode 100644 index 00000000000..49dc8d9db18 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h @@ -0,0 +1,18 @@ +#ifndef __AU1X00_ETH_DATA_H +#define __AU1X00_ETH_DATA_H + +/* Platform specific PHY configuration passed to the MAC driver */ +struct au1000_eth_platform_data { + int phy_static_config; + int phy_search_highest_addr; + int phy1_search_mac0; + int phy_addr; + int phy_busid; + int phy_irq; + char mac[6]; +}; + +void __init au1xxx_override_eth_cfg(unsigned port, + struct au1000_eth_platform_data *eth_data); + +#endif /* __AU1X00_ETH_DATA_H */ diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h index 60638b8969b..bb91b8923a4 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h @@ -1,5 +1,5 @@ /* - * include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005 + * include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005 * * BRIEF MODULE DESCRIPTION * AMD Alchemy Au1xxx IDE interface routines over the Static Bus @@ -27,14 +27,14 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. * * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE - * Interface and Linux Device Driver" Application Note. + * Interface and Linux Device Driver" Application Note. */ #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA #define DMA_WAIT_TIMEOUT 100 -#define NUM_DESCRIPTORS PRD_ENTRIES +#define NUM_DESCRIPTORS PRD_ENTRIES #else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */ -#define NUM_DESCRIPTORS 2 +#define NUM_DESCRIPTORS 2 #endif #ifndef AU1XXX_ATA_RQSIZE @@ -46,20 +46,6 @@ #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0 #endif -#ifdef CONFIG_PM -/* - * This will enable the device to be powered up when write() or read() - * is called. If this is not defined, the driver will return -EBUSY. - */ -#define WAKE_ON_ACCESS 1 - -typedef struct { - spinlock_t lock; /* Used to block on state transitions */ - au1xxx_power_dev_t *dev; /* Power Managers device structure */ - unsigned stopped; /* Used to signal device is stopped */ -} pm_state; -#endif - typedef struct { u32 tx_dev_id, rx_dev_id, target_dev_id; u32 tx_chan, rx_chan; @@ -72,9 +58,7 @@ typedef struct { #endif int irq; u32 regbase; -#ifdef CONFIG_PM - pm_state pm; -#endif + int ddma_id; } _auide_hwif; /******************************************************************************/ @@ -100,8 +84,8 @@ typedef struct { #define TWP_MASK (0x3F << 14) #define TCSW_MASK (0x0F << 10) #define TPM_MASK (0x0F << 6) -#define TA_MASK (0x3F << 0) -#define TS_MASK (1 << 8) +#define TA_MASK (0x3F << 0) +#define TS_MASK (1 << 8) /* Timing parameters PIO mode 0 */ #define SBC_IDE_PIO0_TCSOE (0x04 << 29) @@ -112,7 +96,7 @@ typedef struct { #define SBC_IDE_PIO0_TWP (0x10 << 14) #define SBC_IDE_PIO0_TCSW (0x04 << 10) #define SBC_IDE_PIO0_TPM (0x00 << 6) -#define SBC_IDE_PIO0_TA (0x15 << 0) +#define SBC_IDE_PIO0_TA (0x15 << 0) /* Timing parameters PIO mode 1 */ #define SBC_IDE_PIO1_TCSOE (0x03 << 29) #define SBC_IDE_PIO1_TOECS (0x01 << 26) @@ -122,7 +106,7 @@ typedef struct { #define SBC_IDE_PIO1_TWP (0x08 << 14) #define SBC_IDE_PIO1_TCSW (0x03 << 10) #define SBC_IDE_PIO1_TPM (0x00 << 6) -#define SBC_IDE_PIO1_TA (0x0B << 0) +#define SBC_IDE_PIO1_TA (0x0B << 0) /* Timing parameters PIO mode 2 */ #define SBC_IDE_PIO2_TCSOE (0x05 << 29) #define SBC_IDE_PIO2_TOECS (0x01 << 26) @@ -132,7 +116,7 @@ typedef struct { #define SBC_IDE_PIO2_TWP (0x1F << 14) #define SBC_IDE_PIO2_TCSW (0x05 << 10) #define SBC_IDE_PIO2_TPM (0x00 << 6) -#define SBC_IDE_PIO2_TA (0x22 << 0) +#define SBC_IDE_PIO2_TA (0x22 << 0) /* Timing parameters PIO mode 3 */ #define SBC_IDE_PIO3_TCSOE (0x05 << 29) #define SBC_IDE_PIO3_TOECS (0x01 << 26) @@ -142,7 +126,7 @@ typedef struct { #define SBC_IDE_PIO3_TWP (0x15 << 14) #define SBC_IDE_PIO3_TCSW (0x05 << 10) #define SBC_IDE_PIO3_TPM (0x00 << 6) -#define SBC_IDE_PIO3_TA (0x1A << 0) +#define SBC_IDE_PIO3_TA (0x1A << 0) /* Timing parameters PIO mode 4 */ #define SBC_IDE_PIO4_TCSOE (0x04 << 29) #define SBC_IDE_PIO4_TOECS (0x01 << 26) @@ -152,7 +136,7 @@ typedef struct { #define SBC_IDE_PIO4_TWP (0x0D << 14) #define SBC_IDE_PIO4_TCSW (0x03 << 10) #define SBC_IDE_PIO4_TPM (0x00 << 6) -#define SBC_IDE_PIO4_TA (0x12 << 0) +#define SBC_IDE_PIO4_TA (0x12 << 0) /* Timing parameters MDMA mode 0 */ #define SBC_IDE_MDMA0_TCSOE (0x03 << 29) #define SBC_IDE_MDMA0_TOECS (0x01 << 26) diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h index 892b7f168eb..8a9cd754be2 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h @@ -33,19 +33,6 @@ #ifndef _AU1000_PSC_H_ #define _AU1000_PSC_H_ -/* The PSC base addresses. */ -#ifdef CONFIG_SOC_AU1550 -#define PSC0_BASE_ADDR 0xb1a00000 -#define PSC1_BASE_ADDR 0xb1b00000 -#define PSC2_BASE_ADDR 0xb0a00000 -#define PSC3_BASE_ADDR 0xb0b00000 -#endif - -#ifdef CONFIG_SOC_AU1200 -#define PSC0_BASE_ADDR 0xb1a00000 -#define PSC1_BASE_ADDR 0xb1b00000 -#endif - /* * The PSC select and control registers are common to all protocols. */ @@ -66,7 +53,7 @@ #define PSC_CTRL_DISABLE 0 #define PSC_CTRL_SUSPEND 2 -#define PSC_CTRL_ENABLE 3 +#define PSC_CTRL_ENABLE 3 /* AC97 Registers. */ #define PSC_AC97CFG_OFFSET 0x00000008 @@ -80,19 +67,6 @@ #define PSC_AC97GPO_OFFSET 0x00000028 #define PSC_AC97GPI_OFFSET 0x0000002c -#define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET) -#define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET) -#define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET) -#define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET) -#define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET) -#define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET) -#define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET) -#define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET) -#define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET) -#define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET) -#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET) -#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET) - /* AC97 Config Register. */ #define PSC_AC97CFG_RT_MASK (3 << 30) #define PSC_AC97CFG_RT_FIFO1 (0 << 30) @@ -111,8 +85,8 @@ #define PSC_AC97CFG_SE_ENABLE (1 << 25) #define PSC_AC97CFG_LEN_MASK (0xf << 21) -#define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11) -#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1) +#define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11) +#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1) #define PSC_AC97CFG_GE_ENABLE (1) /* Enable slots 3-12. */ @@ -121,7 +95,7 @@ /* * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately. - * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the + * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the * arithmetic in the macro. */ #define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21) @@ -394,19 +368,6 @@ typedef struct psc_spi { #define PSC_SPITXRX_LC (1 << 29) #define PSC_SPITXRX_SR (1 << 28) -/* PSC in SMBus (I2C) Mode. */ -typedef struct psc_smb { - u32 psc_sel; - u32 psc_ctrl; - u32 psc_smbcfg; - u32 psc_smbmsk; - u32 psc_smbpcr; - u32 psc_smbstat; - u32 psc_smbevnt; - u32 psc_smbtxrx; - u32 psc_smbtmr; -} psc_smb_t; - /* SMBus Config Register. */ #define PSC_SMBCFG_RT_MASK (3 << 30) #define PSC_SMBCFG_RT_FIFO1 (0 << 30) diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h new file mode 100644 index 00000000000..09f45e6afad --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h @@ -0,0 +1,53 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 +#define cpu_has_mcheck 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 +#define cpu_has_mips16 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 1 +#define cpu_has_pindexed_dcache 0 +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 +#define cpu_has_dsp 0 +#define cpu_has_dsp2 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_vint 0 +#define cpu_has_veic 0 +#define cpu_has_inclusive_pcaches 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h new file mode 100644 index 00000000000..796afd051c3 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h @@ -0,0 +1,662 @@ +/* + * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200 + * + * Copyright (c) 2009 Manuel Lauss. + * + * Licensed under the terms outlined in the file COPYING. + */ + +#ifndef _ALCHEMY_GPIO_AU1000_H_ +#define _ALCHEMY_GPIO_AU1000_H_ + +#include <asm/mach-au1x00/au1000.h> + +/* The default GPIO numberspace as documented in the Alchemy manuals. + * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block. + */ +#define ALCHEMY_GPIO1_BASE 0 +#define ALCHEMY_GPIO2_BASE 200 + +#define ALCHEMY_GPIO1_NUM 32 +#define ALCHEMY_GPIO2_NUM 16 +#define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1) +#define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1) + +#define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off)) + +/* GPIO1 registers within SYS_ area */ +#define SYS_TRIOUTRD 0x100 +#define SYS_TRIOUTCLR 0x100 +#define SYS_OUTPUTRD 0x108 +#define SYS_OUTPUTSET 0x108 +#define SYS_OUTPUTCLR 0x10C +#define SYS_PINSTATERD 0x110 +#define SYS_PININPUTEN 0x110 + +/* register offsets within GPIO2 block */ +#define GPIO2_DIR 0x00 +#define GPIO2_OUTPUT 0x08 +#define GPIO2_PINSTATE 0x0C +#define GPIO2_INTENABLE 0x10 +#define GPIO2_ENABLE 0x14 + +struct gpio; + +static inline int au1000_gpio1_to_irq(int gpio) +{ + return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); +} + +static inline int au1000_gpio2_to_irq(int gpio) +{ + return -ENXIO; +} + +static inline int au1000_irq_to_gpio(int irq) +{ + if ((irq >= AU1000_GPIO0_INT) && (irq <= AU1000_GPIO31_INT)) + return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0; + + return -ENXIO; +} + +static inline int au1500_gpio1_to_irq(int gpio) +{ + gpio -= ALCHEMY_GPIO1_BASE; + + switch (gpio) { + case 0 ... 15: + case 20: + case 23 ... 28: return MAKE_IRQ(1, gpio); + } + + return -ENXIO; +} + +static inline int au1500_gpio2_to_irq(int gpio) +{ + gpio -= ALCHEMY_GPIO2_BASE; + + switch (gpio) { + case 0 ... 3: return MAKE_IRQ(1, 16 + gpio - 0); + case 4 ... 5: return MAKE_IRQ(1, 21 + gpio - 4); + case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6); + } + + return -ENXIO; +} + +static inline int au1500_irq_to_gpio(int irq) +{ + switch (irq) { + case AU1500_GPIO0_INT ... AU1500_GPIO15_INT: + case AU1500_GPIO20_INT: + case AU1500_GPIO23_INT ... AU1500_GPIO28_INT: + return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0; + case AU1500_GPIO200_INT ... AU1500_GPIO203_INT: + return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0; + case AU1500_GPIO204_INT ... AU1500_GPIO205_INT: + return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4; + case AU1500_GPIO206_INT ... AU1500_GPIO207_INT: + return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6; + case AU1500_GPIO208_215_INT: + return ALCHEMY_GPIO2_BASE + 8; + } + + return -ENXIO; +} + +static inline int au1100_gpio1_to_irq(int gpio) +{ + return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); +} + +static inline int au1100_gpio2_to_irq(int gpio) +{ + gpio -= ALCHEMY_GPIO2_BASE; + + if ((gpio >= 8) && (gpio <= 15)) + return MAKE_IRQ(0, 29); /* shared GPIO208_215 */ + + return -ENXIO; +} + +static inline int au1100_irq_to_gpio(int irq) +{ + switch (irq) { + case AU1100_GPIO0_INT ... AU1100_GPIO31_INT: + return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0; + case AU1100_GPIO208_215_INT: + return ALCHEMY_GPIO2_BASE + 8; + } + + return -ENXIO; +} + +static inline int au1550_gpio1_to_irq(int gpio) +{ + gpio -= ALCHEMY_GPIO1_BASE; + + switch (gpio) { + case 0 ... 15: + case 20 ... 28: return MAKE_IRQ(1, gpio); + case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16); + } + + return -ENXIO; +} + +static inline int au1550_gpio2_to_irq(int gpio) +{ + gpio -= ALCHEMY_GPIO2_BASE; + + switch (gpio) { + case 0: return MAKE_IRQ(1, 16); + case 1 ... 5: return MAKE_IRQ(1, 17); /* shared GPIO201_205 */ + case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6); + case 8 ... 15: return MAKE_IRQ(1, 31); /* shared GPIO208_215 */ + } + + return -ENXIO; +} + +static inline int au1550_irq_to_gpio(int irq) +{ + switch (irq) { + case AU1550_GPIO0_INT ... AU1550_GPIO15_INT: + return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0; + case AU1550_GPIO200_INT: + case AU1550_GPIO201_205_INT: + return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0; + case AU1550_GPIO16_INT ... AU1550_GPIO28_INT: + return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16; + case AU1550_GPIO206_INT ... AU1550_GPIO208_215_INT: + return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6; + } + + return -ENXIO; +} + +static inline int au1200_gpio1_to_irq(int gpio) +{ + return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); +} + +static inline int au1200_gpio2_to_irq(int gpio) +{ + gpio -= ALCHEMY_GPIO2_BASE; + + switch (gpio) { + case 0 ... 2: return MAKE_IRQ(0, 5 + gpio - 0); + case 3: return MAKE_IRQ(0, 22); + case 4 ... 7: return MAKE_IRQ(0, 24 + gpio - 4); + case 8 ... 15: return MAKE_IRQ(0, 28); /* shared GPIO208_215 */ + } + + return -ENXIO; +} + +static inline int au1200_irq_to_gpio(int irq) +{ + switch (irq) { + case AU1200_GPIO0_INT ... AU1200_GPIO31_INT: + return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0; + case AU1200_GPIO200_INT ... AU1200_GPIO202_INT: + return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0; + case AU1200_GPIO203_INT: + return ALCHEMY_GPIO2_BASE + 3; + case AU1200_GPIO204_INT ... AU1200_GPIO208_215_INT: + return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4; + } + + return -ENXIO; +} + +/* + * GPIO1 block macros for common linux gpio functions. + */ +static inline void alchemy_gpio1_set_value(int gpio, int v) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); + unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); + unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR; + __raw_writel(mask, base + r); + wmb(); +} + +static inline int alchemy_gpio1_get_value(int gpio) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); + unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); + return __raw_readl(base + SYS_PINSTATERD) & mask; +} + +static inline int alchemy_gpio1_direction_input(int gpio) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); + unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); + __raw_writel(mask, base + SYS_TRIOUTCLR); + wmb(); + return 0; +} + +static inline int alchemy_gpio1_direction_output(int gpio, int v) +{ + /* hardware switches to "output" mode when one of the two + * "set_value" registers is accessed. + */ + alchemy_gpio1_set_value(gpio, v); + return 0; +} + +static inline int alchemy_gpio1_is_valid(int gpio) +{ + return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX)); +} + +static inline int alchemy_gpio1_to_irq(int gpio) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + return au1000_gpio1_to_irq(gpio); + case ALCHEMY_CPU_AU1100: + return au1100_gpio1_to_irq(gpio); + case ALCHEMY_CPU_AU1500: + return au1500_gpio1_to_irq(gpio); + case ALCHEMY_CPU_AU1550: + return au1550_gpio1_to_irq(gpio); + case ALCHEMY_CPU_AU1200: + return au1200_gpio1_to_irq(gpio); + } + return -ENXIO; +} + +/* + * GPIO2 block macros for common linux GPIO functions. The 'gpio' + * parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX. + */ +static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); + unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE); + unsigned long d = __raw_readl(base + GPIO2_DIR); + + if (to_out) + d |= mask; + else + d &= ~mask; + __raw_writel(d, base + GPIO2_DIR); + wmb(); +} + +static inline void alchemy_gpio2_set_value(int gpio, int v) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); + unsigned long mask; + mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE); + __raw_writel(mask, base + GPIO2_OUTPUT); + wmb(); +} + +static inline int alchemy_gpio2_get_value(int gpio) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); + return __raw_readl(base + GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE)); +} + +static inline int alchemy_gpio2_direction_input(int gpio) +{ + unsigned long flags; + local_irq_save(flags); + __alchemy_gpio2_mod_dir(gpio, 0); + local_irq_restore(flags); + return 0; +} + +static inline int alchemy_gpio2_direction_output(int gpio, int v) +{ + unsigned long flags; + alchemy_gpio2_set_value(gpio, v); + local_irq_save(flags); + __alchemy_gpio2_mod_dir(gpio, 1); + local_irq_restore(flags); + return 0; +} + +static inline int alchemy_gpio2_is_valid(int gpio) +{ + return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX)); +} + +static inline int alchemy_gpio2_to_irq(int gpio) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + return au1000_gpio2_to_irq(gpio); + case ALCHEMY_CPU_AU1100: + return au1100_gpio2_to_irq(gpio); + case ALCHEMY_CPU_AU1500: + return au1500_gpio2_to_irq(gpio); + case ALCHEMY_CPU_AU1550: + return au1550_gpio2_to_irq(gpio); + case ALCHEMY_CPU_AU1200: + return au1200_gpio2_to_irq(gpio); + } + return -ENXIO; +} + +/**********************************************************************/ + +/* GPIO2 shared interrupts and control */ + +static inline void __alchemy_gpio2_mod_int(int gpio2, int en) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); + unsigned long r = __raw_readl(base + GPIO2_INTENABLE); + if (en) + r |= 1 << gpio2; + else + r &= ~(1 << gpio2); + __raw_writel(r, base + GPIO2_INTENABLE); + wmb(); +} + +/** + * alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution. + * @gpio2: The GPIO2 pin to activate (200...215). + * + * GPIO208-215 have one shared interrupt line to the INTC. They are + * and'ed with a per-pin enable bit and finally or'ed together to form + * a single irq request (useful for active-high sources). + * With this function, a pins' individual contribution to the int request + * can be enabled. As with all other GPIO-based interrupts, the INTC + * must be programmed to accept the GPIO208_215 interrupt as well. + * + * NOTE: Calling this macro is only necessary for GPIO208-215; all other + * GPIO2-based interrupts have their own request to the INTC. Please + * consult your Alchemy databook for more information! + * + * NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request + * line to the INTC, GPIO201_205. This function can be used for those + * as well. + * + * NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace + * (200-215 by default). No sanity checks are made, + */ +static inline void alchemy_gpio2_enable_int(int gpio2) +{ + unsigned long flags; + + gpio2 -= ALCHEMY_GPIO2_BASE; + + /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1100: + case ALCHEMY_CPU_AU1500: + gpio2 -= 8; + } + + local_irq_save(flags); + __alchemy_gpio2_mod_int(gpio2, 1); + local_irq_restore(flags); +} + +/** + * alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution. + * @gpio2: The GPIO2 pin to activate (200...215). + * + * see function alchemy_gpio2_enable_int() for more information. + */ +static inline void alchemy_gpio2_disable_int(int gpio2) +{ + unsigned long flags; + + gpio2 -= ALCHEMY_GPIO2_BASE; + + /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1100: + case ALCHEMY_CPU_AU1500: + gpio2 -= 8; + } + + local_irq_save(flags); + __alchemy_gpio2_mod_int(gpio2, 0); + local_irq_restore(flags); +} + +/** + * alchemy_gpio2_enable - Activate GPIO2 block. + * + * The GPIO2 block must be enabled excplicitly to work. On systems + * where this isn't done by the bootloader, this macro can be used. + */ +static inline void alchemy_gpio2_enable(void) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); + __raw_writel(3, base + GPIO2_ENABLE); /* reset, clock enabled */ + wmb(); + __raw_writel(1, base + GPIO2_ENABLE); /* clock enabled */ + wmb(); +} + +/** + * alchemy_gpio2_disable - disable GPIO2 block. + * + * Disable and put GPIO2 block in low-power mode. + */ +static inline void alchemy_gpio2_disable(void) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); + __raw_writel(2, base + GPIO2_ENABLE); /* reset, clock disabled */ + wmb(); +} + +/**********************************************************************/ + +/* wrappers for on-chip gpios; can be used before gpio chips have been + * registered with gpiolib. + */ +static inline int alchemy_gpio_direction_input(int gpio) +{ + return (gpio >= ALCHEMY_GPIO2_BASE) ? + alchemy_gpio2_direction_input(gpio) : + alchemy_gpio1_direction_input(gpio); +} + +static inline int alchemy_gpio_direction_output(int gpio, int v) +{ + return (gpio >= ALCHEMY_GPIO2_BASE) ? + alchemy_gpio2_direction_output(gpio, v) : + alchemy_gpio1_direction_output(gpio, v); +} + +static inline int alchemy_gpio_get_value(int gpio) +{ + return (gpio >= ALCHEMY_GPIO2_BASE) ? + alchemy_gpio2_get_value(gpio) : + alchemy_gpio1_get_value(gpio); +} + +static inline void alchemy_gpio_set_value(int gpio, int v) +{ + if (gpio >= ALCHEMY_GPIO2_BASE) + alchemy_gpio2_set_value(gpio, v); + else + alchemy_gpio1_set_value(gpio, v); +} + +static inline int alchemy_gpio_is_valid(int gpio) +{ + return (gpio >= ALCHEMY_GPIO2_BASE) ? + alchemy_gpio2_is_valid(gpio) : + alchemy_gpio1_is_valid(gpio); +} + +static inline int alchemy_gpio_cansleep(int gpio) +{ + return 0; /* Alchemy never gets tired */ +} + +static inline int alchemy_gpio_to_irq(int gpio) +{ + return (gpio >= ALCHEMY_GPIO2_BASE) ? + alchemy_gpio2_to_irq(gpio) : + alchemy_gpio1_to_irq(gpio); +} + +static inline int alchemy_irq_to_gpio(int irq) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + return au1000_irq_to_gpio(irq); + case ALCHEMY_CPU_AU1100: + return au1100_irq_to_gpio(irq); + case ALCHEMY_CPU_AU1500: + return au1500_irq_to_gpio(irq); + case ALCHEMY_CPU_AU1550: + return au1550_irq_to_gpio(irq); + case ALCHEMY_CPU_AU1200: + return au1200_irq_to_gpio(irq); + } + return -ENXIO; +} + +/**********************************************************************/ + +/* Linux gpio framework integration. + * + * 4 use cases of Au1000-Au1200 GPIOS: + *(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y: + * Board must register gpiochips. + *(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n: + * 2 (1 for Au1000) gpio_chips are registered. + * + *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y: + * the boards' gpio.h must provide the linux gpio wrapper functions, + * + *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n: + * inlinable gpio functions are provided which enable access to the + * Au1000 gpios only by using the numbers straight out of the data- + * sheets. + + * Cases 1 and 3 are intended for boards which want to provide their own + * GPIO namespace and -operations (i.e. for example you have 8 GPIOs + * which are in part provided by spare Au1000 GPIO pins and in part by + * an external FPGA but you still want them to be accssible in linux + * as gpio0-7. The board can of course use the alchemy_gpioX_* functions + * as required). + */ + +#ifndef CONFIG_GPIOLIB + +#ifdef CONFIG_ALCHEMY_GPIOINT_AU1000 + +#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */ + +static inline int gpio_direction_input(int gpio) +{ + return alchemy_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(int gpio, int v) +{ + return alchemy_gpio_direction_output(gpio, v); +} + +static inline int gpio_get_value(int gpio) +{ + return alchemy_gpio_get_value(gpio); +} + +static inline void gpio_set_value(int gpio, int v) +{ + alchemy_gpio_set_value(gpio, v); +} + +static inline int gpio_get_value_cansleep(unsigned gpio) +{ + return gpio_get_value(gpio); +} + +static inline void gpio_set_value_cansleep(unsigned gpio, int value) +{ + gpio_set_value(gpio, value); +} + +static inline int gpio_is_valid(int gpio) +{ + return alchemy_gpio_is_valid(gpio); +} + +static inline int gpio_cansleep(int gpio) +{ + return alchemy_gpio_cansleep(gpio); +} + +static inline int gpio_to_irq(int gpio) +{ + return alchemy_gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(int irq) +{ + return alchemy_irq_to_gpio(irq); +} + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +static inline int gpio_request_one(unsigned gpio, + unsigned long flags, const char *label) +{ + return 0; +} + +static inline int gpio_request_array(struct gpio *array, size_t num) +{ + return 0; +} + +static inline void gpio_free(unsigned gpio) +{ +} + +static inline void gpio_free_array(struct gpio *array, size_t num) +{ +} + +static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) +{ + return -ENOSYS; +} + +static inline int gpio_export(unsigned gpio, bool direction_may_change) +{ + return -ENOSYS; +} + +static inline int gpio_export_link(struct device *dev, const char *name, + unsigned gpio) +{ + return -ENOSYS; +} + +static inline int gpio_sysfs_set_active_low(unsigned gpio, int value) +{ + return -ENOSYS; +} + +static inline void gpio_unexport(unsigned gpio) +{ +} + +#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ + +#endif /* CONFIG_ALCHEMY_GPIOINT_AU1000 */ + +#endif /* !CONFIG_GPIOLIB */ + +#endif /* _ALCHEMY_GPIO_AU1000_H_ */ diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h new file mode 100644 index 00000000000..ce02894271c --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h @@ -0,0 +1,259 @@ +/* + * gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles. + * + * Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com> + */ + +#ifndef _GPIO_AU1300_H_ +#define _GPIO_AU1300_H_ + +#include <asm/addrspace.h> +#include <asm/io.h> +#include <asm/mach-au1x00/au1000.h> + +struct gpio; +struct gpio_chip; + +/* with the current GPIC design, up to 128 GPIOs are possible. + * The only implementation so far is in the Au1300, which has 75 externally + * available GPIOs. + */ +#define AU1300_GPIO_BASE 0 +#define AU1300_GPIO_NUM 75 +#define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1) + +#define AU1300_GPIC_ADDR \ + (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR) + +static inline int au1300_gpio_get_value(unsigned int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + int bit; + + gpio -= AU1300_GPIO_BASE; + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit; +} + +static inline int au1300_gpio_direction_input(unsigned int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long bit; + + gpio -= AU1300_GPIO_BASE; + + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, roff + AU1300_GPIC_DEVCLR); + wmb(); + + return 0; +} + +static inline int au1300_gpio_set_value(unsigned int gpio, int v) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long bit; + + gpio -= AU1300_GPIO_BASE; + + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL + : AU1300_GPIC_PINVALCLR)); + wmb(); + + return 0; +} + +static inline int au1300_gpio_direction_output(unsigned int gpio, int v) +{ + /* hw switches to output automatically */ + return au1300_gpio_set_value(gpio, v); +} + +static inline int au1300_gpio_to_irq(unsigned int gpio) +{ + return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE); +} + +static inline int au1300_irq_to_gpio(unsigned int irq) +{ + return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE; +} + +static inline int au1300_gpio_is_valid(unsigned int gpio) +{ + int ret; + + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1300: + ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX)); + break; + default: + ret = 0; + } + return ret; +} + +static inline int au1300_gpio_cansleep(unsigned int gpio) +{ + return 0; +} + +/* hardware remembers gpio 0-63 levels on powerup */ +static inline int au1300_gpio_getinitlvl(unsigned int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long v; + + if (unlikely(gpio > 63)) + return 0; + else if (gpio > 31) { + gpio -= 32; + roff += 4; + } + + v = __raw_readl(roff + AU1300_GPIC_RSTVAL); + return (v >> gpio) & 1; +} + +/**********************************************************************/ + +/* Linux gpio framework integration. +* +* 4 use cases of Alchemy GPIOS: +*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y: +* Board must register gpiochips. +*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n: +* A gpiochip for the 75 GPIOs is registered. +* +*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y: +* the boards' gpio.h must provide the linux gpio wrapper functions, +* +*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n: +* inlinable gpio functions are provided which enable access to the +* Au1300 gpios only by using the numbers straight out of the data- +* sheets. + +* Cases 1 and 3 are intended for boards which want to provide their own +* GPIO namespace and -operations (i.e. for example you have 8 GPIOs +* which are in part provided by spare Au1300 GPIO pins and in part by +* an external FPGA but you still want them to be accssible in linux +* as gpio0-7. The board can of course use the alchemy_gpioX_* functions +* as required). +*/ + +#ifndef CONFIG_GPIOLIB + +#ifdef CONFIG_ALCHEMY_GPIOINT_AU1300 + +#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */ + +static inline int gpio_direction_input(unsigned int gpio) +{ + return au1300_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned int gpio, int v) +{ + return au1300_gpio_direction_output(gpio, v); +} + +static inline int gpio_get_value(unsigned int gpio) +{ + return au1300_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned int gpio, int v) +{ + au1300_gpio_set_value(gpio, v); +} + +static inline int gpio_get_value_cansleep(unsigned gpio) +{ + return gpio_get_value(gpio); +} + +static inline void gpio_set_value_cansleep(unsigned gpio, int value) +{ + gpio_set_value(gpio, value); +} + +static inline int gpio_is_valid(unsigned int gpio) +{ + return au1300_gpio_is_valid(gpio); +} + +static inline int gpio_cansleep(unsigned int gpio) +{ + return au1300_gpio_cansleep(gpio); +} + +static inline int gpio_to_irq(unsigned int gpio) +{ + return au1300_gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(unsigned int irq) +{ + return au1300_irq_to_gpio(irq); +} + +static inline int gpio_request(unsigned int gpio, const char *label) +{ + return 0; +} + +static inline int gpio_request_one(unsigned gpio, + unsigned long flags, const char *label) +{ + return 0; +} + +static inline int gpio_request_array(struct gpio *array, size_t num) +{ + return 0; +} + +static inline void gpio_free(unsigned gpio) +{ +} + +static inline void gpio_free_array(struct gpio *array, size_t num) +{ +} + +static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) +{ + return -ENOSYS; +} + +static inline void gpio_unexport(unsigned gpio) +{ +} + +static inline int gpio_export(unsigned gpio, bool direction_may_change) +{ + return -ENOSYS; +} + +static inline int gpio_sysfs_set_active_low(unsigned gpio, int value) +{ + return -ENOSYS; +} + +static inline int gpio_export_link(struct device *dev, const char *name, + unsigned gpio) +{ + return -ENOSYS; +} + +#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ + +#endif /* CONFIG_ALCHEMY_GPIOINT_AU1300 */ + +#endif /* CONFIG GPIOLIB */ + +#endif /* _GPIO_AU1300_H_ */ diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h index 2dc61e009a0..22e7ff17fc4 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio.h +++ b/arch/mips/include/asm/mach-au1x00/gpio.h @@ -1,69 +1,86 @@ -#ifndef _AU1XXX_GPIO_H_ -#define _AU1XXX_GPIO_H_ - -#include <linux/types.h> - -#define AU1XXX_GPIO_BASE 200 - -struct au1x00_gpio2 { - u32 dir; - u32 reserved; - u32 output; - u32 pinstate; - u32 inten; - u32 enable; -}; - -extern int au1xxx_gpio_get_value(unsigned gpio); -extern void au1xxx_gpio_set_value(unsigned gpio, int value); -extern int au1xxx_gpio_direction_input(unsigned gpio); -extern int au1xxx_gpio_direction_output(unsigned gpio, int value); - - -/* Wrappers for the arch-neutral GPIO API */ - -static inline int gpio_request(unsigned gpio, const char *label) +/* + * Alchemy GPIO support. + * + * With CONFIG_GPIOLIB=y different types of on-chip GPIO can be supported within + * the same kernel image. + * With CONFIG_GPIOLIB=n, your board must select ALCHEMY_GPIOINT_AU1XXX for the + * appropriate CPU type (AU1000 currently). + */ + +#ifndef _ALCHEMY_GPIO_H_ +#define _ALCHEMY_GPIO_H_ + +#include <asm/mach-au1x00/au1000.h> +#include <asm/mach-au1x00/gpio-au1000.h> +#include <asm/mach-au1x00/gpio-au1300.h> + +/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before + * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this + * register enables use of GPIOs as wake source. + */ +static inline void alchemy_gpio1_input_enable(void) { - /* Not yet implemented */ - return 0; + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); + __raw_writel(0, base + 0x110); /* the write op is key */ + wmb(); } -static inline void gpio_free(unsigned gpio) -{ - /* Not yet implemented */ -} -static inline int gpio_direction_input(unsigned gpio) +/* Linux gpio framework integration. +* +* 4 use cases of Alchemy GPIOS: +*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y: +* Board must register gpiochips. +*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n: +* A gpiochip for the 75 GPIOs is registered. +* +*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y: +* the boards' gpio.h must provide the linux gpio wrapper functions, +* +*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n: +* inlinable gpio functions are provided which enable access to the +* Au1300 gpios only by using the numbers straight out of the data- +* sheets. + +* Cases 1 and 3 are intended for boards which want to provide their own +* GPIO namespace and -operations (i.e. for example you have 8 GPIOs +* which are in part provided by spare Au1300 GPIO pins and in part by +* an external FPGA but you still want them to be accssible in linux +* as gpio0-7. The board can of course use the alchemy_gpioX_* functions +* as required). +*/ + +#ifdef CONFIG_GPIOLIB + +/* wraps the cpu-dependent irq_to_gpio functions */ +/* FIXME: gpiolib needs an irq_to_gpio hook */ +static inline int __au_irq_to_gpio(unsigned int irq) { - return au1xxx_gpio_direction_input(gpio); + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200: + return alchemy_irq_to_gpio(irq); + case ALCHEMY_CPU_AU1300: + return au1300_irq_to_gpio(irq); + } + return -EINVAL; } -static inline int gpio_direction_output(unsigned gpio, int value) -{ - return au1xxx_gpio_direction_output(gpio, value); -} -static inline int gpio_get_value(unsigned gpio) -{ - return au1xxx_gpio_get_value(gpio); -} +/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */ +#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */ -static inline void gpio_set_value(unsigned gpio, int value) -{ - au1xxx_gpio_set_value(gpio, value); -} +/* get everything through gpiolib */ +#define gpio_to_irq __gpio_to_irq +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define irq_to_gpio __au_irq_to_gpio -static inline int gpio_to_irq(unsigned gpio) -{ - return gpio; -} +#include <asm-generic/gpio.h> -static inline int irq_to_gpio(unsigned irq) -{ - return irq; -} +#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ -/* For cansleep */ -#include <asm-generic/gpio.h> -#endif /* _AU1XXX_GPIO_H_ */ +#endif /* CONFIG_GPIOLIB */ + +#endif /* _ALCHEMY_GPIO_H_ */ diff --git a/arch/mips/include/asm/mach-au1x00/ioremap.h b/arch/mips/include/asm/mach-au1x00/ioremap.h index 364cea2dc71..75a94ad3ac9 100644 --- a/arch/mips/include/asm/mach-au1x00/ioremap.h +++ b/arch/mips/include/asm/mach-au1x00/ioremap.h @@ -11,7 +11,7 @@ #include <linux/types.h> -#ifdef CONFIG_64BIT_PHYS_ADDR +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_PCI) extern phys_t __fixup_bigphys_addr(phys_t, phys_t); #else static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) diff --git a/arch/mips/include/asm/mach-au1x00/prom.h b/arch/mips/include/asm/mach-au1x00/prom.h index e38715577c5..4c0e09cf173 100644 --- a/arch/mips/include/asm/mach-au1x00/prom.h +++ b/arch/mips/include/asm/mach-au1x00/prom.h @@ -6,7 +6,6 @@ extern char **prom_argv; extern char **prom_envp; extern void prom_init_cmdline(void); -extern char *prom_getcmdline(void); extern char *prom_getenv(char *envname); extern int prom_get_ethernet_addr(char *ethernet_addr); diff --git a/arch/mips/include/asm/mach-au1x00/war.h b/arch/mips/include/asm/mach-au1x00/war.h index dd57d03d68b..72e260d24e5 100644 --- a/arch/mips/include/asm/mach-au1x00/war.h +++ b/arch/mips/include/asm/mach-au1x00/war.h @@ -17,7 +17,6 @@ #define MIPS4K_ICACHE_REFILL_WAR 0 #define MIPS_CACHE_SYNC_WAR 0 #define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 #define ICACHE_REFILLS_WORKAROUND_WAR 0 #define R10000_LLSC_WAR 0 #define MIPS34K_MISSED_ITLB_WAR 0 |