diff options
Diffstat (limited to 'arch/m68k/include/asm/m54xxsim.h')
| -rw-r--r-- | arch/m68k/include/asm/m54xxsim.h | 66 |
1 files changed, 52 insertions, 14 deletions
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h index 462ae532844..a5fbd17ab0a 100644 --- a/arch/m68k/include/asm/m54xxsim.h +++ b/arch/m68k/include/asm/m54xxsim.h @@ -7,6 +7,7 @@ #define CPU_NAME "COLDFIRE(m54xx)" #define CPU_INSTR_PER_JIFFY 2 +#define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m54xxacr.h> @@ -15,7 +16,8 @@ /* * Interrupt Controller Registers */ -#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */ + #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ @@ -29,34 +31,70 @@ /* * UART module. */ -#define MCFUART_BASE1 0x8600 /* Base address of UART1 */ -#define MCFUART_BASE2 0x8700 /* Base address of UART2 */ -#define MCFUART_BASE3 0x8800 /* Base address of UART3 */ -#define MCFUART_BASE4 0x8900 /* Base address of UART4 */ +#define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */ +#define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */ +#define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */ +#define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */ /* * Define system peripheral IRQ usage. */ -#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */ -#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */ +#define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */ +#define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */ +#define MCF_IRQ_UART0 (MCFINT_VECBASE + 35) +#define MCF_IRQ_UART1 (MCFINT_VECBASE + 34) +#define MCF_IRQ_UART2 (MCFINT_VECBASE + 33) +#define MCF_IRQ_UART3 (MCFINT_VECBASE + 32) + +/* + * Slice Timer support. + */ +#define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */ +#define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */ /* * Generic GPIO support */ -#define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */ -#define MCFGPIO_IRQ_MAX -1 -#define MCFGPIO_IRQ_VECBASE -1 +#define MCFGPIO_PODR (MCF_MBAR + 0xA00) +#define MCFGPIO_PDDR (MCF_MBAR + 0xA10) +#define MCFGPIO_PPDR (MCF_MBAR + 0xA20) +#define MCFGPIO_SETR (MCF_MBAR + 0xA20) +#define MCFGPIO_CLRR (MCF_MBAR + 0xA30) + +#define MCFGPIO_PIN_MAX 136 /* 128 gpio + 8 eport */ +#define MCFGPIO_IRQ_MAX 8 +#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE /* - * Some PSC related definitions + * EDGE Port support. */ -#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3)) +#define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */ +#define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */ +#define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */ +#define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */ +#define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */ +#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */ + +/* + * Pin Assignment register definitions + */ +#define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40) +#define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42) +#define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43) +#define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44) +#define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */ +#define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */ +#define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F) +#define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E) +#define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D) +#define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C) +#define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50) +#define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52) + #define MCF_PAR_SDA (0x0008) #define MCF_PAR_SCL (0x0004) #define MCF_PAR_PSC_TXD (0x04) #define MCF_PAR_PSC_RXD (0x08) -#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4) -#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6) #define MCF_PAR_PSC_CTS_GPIO (0x00) #define MCF_PAR_PSC_CTS_BCLK (0x80) #define MCF_PAR_PSC_CTS_CTS (0xC0) |