diff options
Diffstat (limited to 'arch/cris/arch-v32/mm')
| -rw-r--r-- | arch/cris/arch-v32/mm/init.c | 31 | ||||
| -rw-r--r-- | arch/cris/arch-v32/mm/intmem.c | 13 | ||||
| -rw-r--r-- | arch/cris/arch-v32/mm/mmu.S | 6 | ||||
| -rw-r--r-- | arch/cris/arch-v32/mm/tlb.c | 4 |
4 files changed, 30 insertions, 24 deletions
diff --git a/arch/cris/arch-v32/mm/init.c b/arch/cris/arch-v32/mm/init.c index caeb921a92e..3deca5253d9 100644 --- a/arch/cris/arch-v32/mm/init.c +++ b/arch/cris/arch-v32/mm/init.c @@ -27,8 +27,7 @@ extern void tlb_init(void); * at kseg_4 thus the ksegs are set up again. Also clear the TLB and do various * other paging stuff. */ -void __init -cris_mmu_init(void) +void __init cris_mmu_init(void) { unsigned long mmu_config; unsigned long mmu_kbase_hi; @@ -55,21 +54,26 @@ cris_mmu_init(void) /* Initialise the TLB. Function found in tlb.c. */ tlb_init(); - /* Enable exceptions and initialize the kernel segments. */ + /* + * Enable exceptions and initialize the kernel segments. + * See head.S for differences between ARTPEC-3 and ETRAX FS. + */ mmu_config = ( REG_STATE(mmu, rw_mm_cfg, we, on) | REG_STATE(mmu, rw_mm_cfg, acc, on) | REG_STATE(mmu, rw_mm_cfg, ex, on) | REG_STATE(mmu, rw_mm_cfg, inv, on) | +#ifdef CONFIG_CRIS_MACH_ARTPEC3 + REG_STATE(mmu, rw_mm_cfg, seg_f, page) | + REG_STATE(mmu, rw_mm_cfg, seg_e, page) | + REG_STATE(mmu, rw_mm_cfg, seg_d, linear) | +#else REG_STATE(mmu, rw_mm_cfg, seg_f, linear) | REG_STATE(mmu, rw_mm_cfg, seg_e, linear) | REG_STATE(mmu, rw_mm_cfg, seg_d, page) | +#endif REG_STATE(mmu, rw_mm_cfg, seg_c, linear) | REG_STATE(mmu, rw_mm_cfg, seg_b, linear) | -#ifndef CONFIG_ETRAX_VCS_SIM REG_STATE(mmu, rw_mm_cfg, seg_a, page) | -#else - REG_STATE(mmu, rw_mm_cfg, seg_a, linear) | -#endif REG_STATE(mmu, rw_mm_cfg, seg_9, page) | REG_STATE(mmu, rw_mm_cfg, seg_8, page) | REG_STATE(mmu, rw_mm_cfg, seg_7, page) | @@ -81,16 +85,18 @@ cris_mmu_init(void) REG_STATE(mmu, rw_mm_cfg, seg_1, page) | REG_STATE(mmu, rw_mm_cfg, seg_0, page)); + /* See head.S for differences between ARTPEC-3 and ETRAX FS. */ mmu_kbase_hi = ( REG_FIELD(mmu, rw_mm_kbase_hi, base_f, 0x0) | +#ifdef CONFIG_CRIS_MACH_ARTPEC3 + REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x0) | + REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x5) | +#else REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x8) | REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x0) | +#endif REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x4) | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) | -#ifndef CONFIG_ETRAX_VCS_SIM REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0x0) | -#else - REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0xa) | -#endif REG_FIELD(mmu, rw_mm_kbase_hi, base_9, 0x0) | REG_FIELD(mmu, rw_mm_kbase_hi, base_8, 0x0)); @@ -129,8 +135,7 @@ cris_mmu_init(void) SUPP_REG_WR(RW_GC_CFG, 0xf); /* IMMU, DMMU, ICache, DCache on */ } -void __init -paging_init(void) +void __init paging_init(void) { int i; unsigned long zones_size[MAX_NR_ZONES]; diff --git a/arch/cris/arch-v32/mm/intmem.c b/arch/cris/arch-v32/mm/intmem.c index 9e8b69cdf19..1b17d92cef8 100644 --- a/arch/cris/arch-v32/mm/intmem.c +++ b/arch/cris/arch-v32/mm/intmem.c @@ -33,8 +33,8 @@ static void crisv32_intmem_init(void) { static int initiated = 0; if (!initiated) { - struct intmem_allocation* alloc = - (struct intmem_allocation*)kmalloc(sizeof *alloc, GFP_KERNEL); + struct intmem_allocation* alloc; + alloc = kmalloc(sizeof *alloc, GFP_KERNEL); INIT_LIST_HEAD(&intmem_allocations); intmem_virtual = ioremap(MEM_INTMEM_START + RESERVED_SIZE, MEM_INTMEM_SIZE - RESERVED_SIZE); @@ -62,9 +62,8 @@ void* crisv32_intmem_alloc(unsigned size, unsigned align) if (allocation->status == STATUS_FREE && allocation->size >= size + alignment) { if (allocation->size > size + alignment) { - struct intmem_allocation* alloc = - (struct intmem_allocation*) - kmalloc(sizeof *alloc, GFP_ATOMIC); + struct intmem_allocation* alloc; + alloc = kmalloc(sizeof *alloc, GFP_ATOMIC); alloc->status = STATUS_FREE; alloc->size = allocation->size - size - alignment; @@ -74,9 +73,7 @@ void* crisv32_intmem_alloc(unsigned size, unsigned align) if (alignment) { struct intmem_allocation *tmp; - tmp = (struct intmem_allocation *) - kmalloc(sizeof *tmp, - GFP_ATOMIC); + tmp = kmalloc(sizeof *tmp, GFP_ATOMIC); tmp->offset = allocation->offset; tmp->size = alignment; tmp->status = STATUS_FREE; diff --git a/arch/cris/arch-v32/mm/mmu.S b/arch/cris/arch-v32/mm/mmu.S index 2238d154bde..72727c1d8e6 100644 --- a/arch/cris/arch-v32/mm/mmu.S +++ b/arch/cris/arch-v32/mm/mmu.S @@ -38,6 +38,7 @@ ; to handle the fault. .macro MMU_BUS_FAULT_HANDLER handler, mmu, we, ex .globl \handler + .type \handler,"function" \handler: SAVE_ALL move \mmu, $srs ; Select MMU support register bank @@ -52,6 +53,7 @@ nop ba ret_from_intr nop + .size \handler, . - \handler .endm ; Refill handler. Three cases may occur: @@ -84,6 +86,7 @@ 2: .dword 0 ; last_refill_cause .text .globl \handler + .type \handler, "function" \handler: subq 4, $sp ; (The pipeline stalls for one cycle; $sp used as address in the next cycle.) @@ -115,7 +118,7 @@ #ifdef CONFIG_SMP move $s7, $acr ; PGD #else - move.d per_cpu__current_pgd, $acr ; PGD + move.d current_pgd, $acr ; PGD #endif ; Look up PMD in PGD lsrq 24, $r0 ; Get PMD index into PGD (bit 24-31) @@ -196,6 +199,7 @@ ; Return ba ret_from_intr nop + .size \handler, . - \handler .endm ; This is the MMU bus fault handlers. diff --git a/arch/cris/arch-v32/mm/tlb.c b/arch/cris/arch-v32/mm/tlb.c index 55ade36fe8a..c030d020660 100644 --- a/arch/cris/arch-v32/mm/tlb.c +++ b/arch/cris/arch-v32/mm/tlb.c @@ -185,11 +185,11 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, /* Make sure there is a MMU context. */ spin_lock(&mmu_context_lock); get_mmu_context(next); - cpu_set(cpu, next->cpu_vm_mask); + cpumask_set_cpu(cpu, mm_cpumask(next)); spin_unlock(&mmu_context_lock); /* - * Remember the pgd for the fault handlers. Keep a seperate + * Remember the pgd for the fault handlers. Keep a separate * copy of it because current and active_mm might be invalid * at points where * there's still a need to derefer the pgd. */ |