diff options
Diffstat (limited to 'arch/blackfin/mach-common')
| -rw-r--r-- | arch/blackfin/mach-common/Makefile | 7 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/cache-c.c | 15 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/clock.h | 27 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/clocks-init.c | 29 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/cpufreq.c | 219 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/dpmc.c | 35 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/dpmc_modes.S | 600 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/entry.S | 84 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/head.S | 40 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/ints-priority.c | 1255 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/pm.c | 74 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/scb-init.c | 52 | ||||
| -rw-r--r-- | arch/blackfin/mach-common/smp.c | 311 |
13 files changed, 984 insertions, 1764 deletions
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile index ff299f24aba..f0997920404 100644 --- a/arch/blackfin/mach-common/Makefile +++ b/arch/blackfin/mach-common/Makefile @@ -6,8 +6,11 @@ obj-y := \ cache.o cache-c.o entry.o head.o \ interrupt.o arch_checks.o ints-priority.o -obj-$(CONFIG_PM) += pm.o dpmc_modes.o -obj-$(CONFIG_CPU_FREQ) += cpufreq.o +obj-$(CONFIG_PM) += pm.o +ifneq ($(CONFIG_BF60x),y) +obj-$(CONFIG_PM) += dpmc_modes.o +endif +obj-$(CONFIG_SCB_PRIORITY) += scb-init.o obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c index a60a24f5035..f4adedc9289 100644 --- a/arch/blackfin/mach-common/cache-c.c +++ b/arch/blackfin/mach-common/cache-c.c @@ -6,7 +6,6 @@ * Licensed under the GPL-2 or later. */ -#include <linux/init.h> #include <asm/blackfin.h> #include <asm/cplbinit.h> @@ -42,6 +41,16 @@ bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr, unsigned long mem_mask) { int i; +#ifdef CONFIG_L1_PARITY_CHECK + u32 ctrl; + + if (cplb_addr == DCPLB_ADDR0) { + ctrl = bfin_read32(mem_control) | (1 << RDCHK); + CSYNC(); + bfin_write32(mem_control, ctrl); + SSYNC(); + } +#endif for (i = 0; i < MAX_CPLBS; i++) { bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr); @@ -52,7 +61,7 @@ bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr, } #ifdef CONFIG_BFIN_ICACHE -void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl) +void bfin_icache_init(struct cplb_entry *icplb_tbl) { bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL, (IMC | ENICPLB)); @@ -60,7 +69,7 @@ void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl) #endif #ifdef CONFIG_BFIN_DCACHE -void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) +void bfin_dcache_init(struct cplb_entry *dcplb_tbl) { /* * Anomaly notes: diff --git a/arch/blackfin/mach-common/clock.h b/arch/blackfin/mach-common/clock.h new file mode 100644 index 00000000000..645ff460a1f --- /dev/null +++ b/arch/blackfin/mach-common/clock.h @@ -0,0 +1,27 @@ +#ifndef __MACH_COMMON_CLKDEV_H +#define __MACH_COMMON_CLKDEV_H + +#include <linux/clk.h> + +struct clk_ops { + unsigned long (*get_rate)(struct clk *clk); + unsigned long (*round_rate)(struct clk *clk, unsigned long rate); + int (*set_rate)(struct clk *clk, unsigned long rate); + int (*enable)(struct clk *clk); + int (*disable)(struct clk *clk); +}; + +struct clk { + const char *name; + unsigned long rate; + spinlock_t lock; + u32 flags; + const struct clk_ops *ops; + const struct params *params; + void __iomem *reg; + u32 mask; + u32 shift; +}; + +#endif + diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c index d5cfe611b77..d436bd907fc 100644 --- a/arch/blackfin/mach-common/clocks-init.c +++ b/arch/blackfin/mach-common/clocks-init.c @@ -7,7 +7,6 @@ */ #include <linux/linkage.h> -#include <linux/init.h> #include <asm/blackfin.h> #include <asm/dma.h> @@ -15,10 +14,30 @@ #include <asm/mem_init.h> #include <asm/dpmc.h> +#ifdef CONFIG_BF60x + +#define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF) +#define CGU_DIV_VAL \ + ((CONFIG_CCLK_DIV << CSEL_OFFSET) | \ + (CONFIG_SCLK_DIV << SYSSEL_OFFSET) | \ + (CONFIG_SCLK0_DIV << S0SEL_OFFSET) | \ + (CONFIG_SCLK1_DIV << S1SEL_OFFSET) | \ + (CONFIG_DCLK_DIV << DSEL_OFFSET)) + +#define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000) +#if ((CONFIG_BFIN_DCLK != 125) && \ + (CONFIG_BFIN_DCLK != 133) && (CONFIG_BFIN_DCLK != 150) && \ + (CONFIG_BFIN_DCLK != 166) && (CONFIG_BFIN_DCLK != 200) && \ + (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250)) +#error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz" +#endif + +#else #define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ #define PLL_CTL_VAL \ (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ - (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000)) + (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000)) +#endif __attribute__((l1_text)) static void do_sync(void) @@ -33,6 +52,10 @@ void init_clocks(void) * in the middle of reprogramming things, and that'll screw us up. * For example, any automatic DMAs left by U-Boot for splash screens. */ +#ifdef CONFIG_BF60x + init_cgu(CGU_DIV_VAL, CGU_CTL_VAL); + init_dmc(CONFIG_BFIN_DCLK); +#else size_t i; for (i = 0; i < MAX_DMA_CHANNELS; ++i) { struct dma_register *dma = dma_io_base_addr[i]; @@ -91,6 +114,8 @@ void init_clocks(void) bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE); #endif #endif +#endif do_sync(); bfin_read16(0); + } diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c deleted file mode 100644 index 85dc6d69f9c..00000000000 --- a/arch/blackfin/mach-common/cpufreq.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Blackfin core clock scaling - * - * Copyright 2008-2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/cpufreq.h> -#include <linux/fs.h> -#include <linux/delay.h> -#include <asm/blackfin.h> -#include <asm/time.h> -#include <asm/dpmc.h> - -/* this is the table of CCLK frequencies, in Hz */ -/* .index is the entry in the auxiliary dpm_state_table[] */ -static struct cpufreq_frequency_table bfin_freq_table[] = { - { - .frequency = CPUFREQ_TABLE_END, - .index = 0, - }, - { - .frequency = CPUFREQ_TABLE_END, - .index = 1, - }, - { - .frequency = CPUFREQ_TABLE_END, - .index = 2, - }, - { - .frequency = CPUFREQ_TABLE_END, - .index = 0, - }, -}; - -static struct bfin_dpm_state { - unsigned int csel; /* system clock divider */ - unsigned int tscale; /* change the divider on the core timer interrupt */ -} dpm_state_table[3]; - -#if defined(CONFIG_CYCLES_CLOCKSOURCE) -/* - * normalized to maximum frequency offset for CYCLES, - * used in time-ts cycles clock source, but could be used - * somewhere also. - */ -unsigned long long __bfin_cycles_off; -unsigned int __bfin_cycles_mod; -#endif - -/**************************************************************************/ -static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk) -{ - - unsigned long csel, min_cclk; - int index; - - /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */ -#if ANOMALY_05000273 || ANOMALY_05000274 || \ - (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE)) - min_cclk = sclk * 2; -#else - min_cclk = sclk; -#endif - csel = ((bfin_read_PLL_DIV() & CSEL) >> 4); - - for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) { - bfin_freq_table[index].frequency = cclk >> index; - dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */ - dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1; - - pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n", - bfin_freq_table[index].frequency, - dpm_state_table[index].csel, - dpm_state_table[index].tscale); - } - return; -} - -static void bfin_adjust_core_timer(void *info) -{ - unsigned int tscale; - unsigned int index = *(unsigned int *)info; - - /* we have to adjust the core timer, because it is using cclk */ - tscale = dpm_state_table[index].tscale; - bfin_write_TSCALE(tscale); - return; -} - -static unsigned int bfin_getfreq_khz(unsigned int cpu) -{ - /* Both CoreA/B have the same core clock */ - return get_cclk() / 1000; -} - -static int bfin_target(struct cpufreq_policy *poli, - unsigned int target_freq, unsigned int relation) -{ - unsigned int index, plldiv, cpu; - unsigned long flags, cclk_hz; - struct cpufreq_freqs freqs; - static unsigned long lpj_ref; - static unsigned int lpj_ref_freq; - -#if defined(CONFIG_CYCLES_CLOCKSOURCE) - cycles_t cycles; -#endif - - for_each_online_cpu(cpu) { - struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); - - if (!policy) - continue; - - if (cpufreq_frequency_table_target(policy, bfin_freq_table, - target_freq, relation, &index)) - return -EINVAL; - - cclk_hz = bfin_freq_table[index].frequency; - - freqs.old = bfin_getfreq_khz(0); - freqs.new = cclk_hz; - freqs.cpu = cpu; - - pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n", - cclk_hz, target_freq, freqs.old); - - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); - if (cpu == CPUFREQ_CPU) { - flags = hard_local_irq_save(); - plldiv = (bfin_read_PLL_DIV() & SSEL) | - dpm_state_table[index].csel; - bfin_write_PLL_DIV(plldiv); - on_each_cpu(bfin_adjust_core_timer, &index, 1); -#if defined(CONFIG_CYCLES_CLOCKSOURCE) - cycles = get_cycles(); - SSYNC(); - cycles += 10; /* ~10 cycles we lose after get_cycles() */ - __bfin_cycles_off += - (cycles << __bfin_cycles_mod) - (cycles << index); - __bfin_cycles_mod = index; -#endif - if (!lpj_ref_freq) { - lpj_ref = loops_per_jiffy; - lpj_ref_freq = freqs.old; - } - if (freqs.new != freqs.old) { - loops_per_jiffy = cpufreq_scale(lpj_ref, - lpj_ref_freq, freqs.new); - } - hard_local_irq_restore(flags); - } - /* TODO: just test case for cycles clock source, remove later */ - cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - } - - pr_debug("cpufreq: done\n"); - return 0; -} - -static int bfin_verify_speed(struct cpufreq_policy *policy) -{ - return cpufreq_frequency_table_verify(policy, bfin_freq_table); -} - -static int __init __bfin_cpu_init(struct cpufreq_policy *policy) -{ - - unsigned long cclk, sclk; - - cclk = get_cclk() / 1000; - sclk = get_sclk() / 1000; - - if (policy->cpu == CPUFREQ_CPU) - bfin_init_tables(cclk, sclk); - - policy->cpuinfo.transition_latency = 50000; /* 50us assumed */ - - policy->cur = cclk; - cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu); - return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table); -} - -static struct freq_attr *bfin_freq_attr[] = { - &cpufreq_freq_attr_scaling_available_freqs, - NULL, -}; - -static struct cpufreq_driver bfin_driver = { - .verify = bfin_verify_speed, - .target = bfin_target, - .get = bfin_getfreq_khz, - .init = __bfin_cpu_init, - .name = "bfin cpufreq", - .owner = THIS_MODULE, - .attr = bfin_freq_attr, -}; - -static int __init bfin_cpu_init(void) -{ - return cpufreq_register_driver(&bfin_driver); -} - -static void __exit bfin_cpu_exit(void) -{ - cpufreq_unregister_driver(&bfin_driver); -} - -MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); -MODULE_DESCRIPTION("cpufreq driver for Blackfin"); -MODULE_LICENSE("GPL"); - -module_init(bfin_cpu_init); -module_exit(bfin_cpu_exit); diff --git a/arch/blackfin/mach-common/dpmc.c b/arch/blackfin/mach-common/dpmc.c index 382099fd556..724a8c5f557 100644 --- a/arch/blackfin/mach-common/dpmc.c +++ b/arch/blackfin/mach-common/dpmc.c @@ -19,9 +19,6 @@ #define DRIVER_NAME "bfin dpmc" -#define dprintk(msg...) \ - cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, DRIVER_NAME, msg) - struct bfin_dpmc_platform_data *pdata; /** @@ -88,10 +85,11 @@ static void bfin_wakeup_cpu(void) { unsigned int cpu; unsigned int this_cpu = smp_processor_id(); - cpumask_t mask = cpu_online_map; + cpumask_t mask; - cpu_clear(this_cpu, mask); - for_each_cpu_mask(cpu, mask) + cpumask_copy(&mask, cpu_online_mask); + cpumask_clear_cpu(this_cpu, &mask); + for_each_cpu(cpu, &mask) platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); } @@ -131,7 +129,7 @@ static struct notifier_block vreg_cpufreq_notifier_block = { * bfin_dpmc_probe - * */ -static int __devinit bfin_dpmc_probe(struct platform_device *pdev) +static int bfin_dpmc_probe(struct platform_device *pdev) { if (pdev->dev.platform_data) pdata = pdev->dev.platform_data; @@ -145,7 +143,7 @@ static int __devinit bfin_dpmc_probe(struct platform_device *pdev) /** * bfin_dpmc_remove - */ -static int __devexit bfin_dpmc_remove(struct platform_device *pdev) +static int bfin_dpmc_remove(struct platform_device *pdev) { pdata = NULL; return cpufreq_unregister_notifier(&vreg_cpufreq_notifier_block, @@ -154,29 +152,12 @@ static int __devexit bfin_dpmc_remove(struct platform_device *pdev) struct platform_driver bfin_dpmc_device_driver = { .probe = bfin_dpmc_probe, - .remove = __devexit_p(bfin_dpmc_remove), + .remove = bfin_dpmc_remove, .driver = { .name = DRIVER_NAME, } }; - -/** - * bfin_dpmc_init - Init driver - */ -static int __init bfin_dpmc_init(void) -{ - return platform_driver_register(&bfin_dpmc_device_driver); -} -module_init(bfin_dpmc_init); - -/** - * bfin_dpmc_exit - break down driver - */ -static void __exit bfin_dpmc_exit(void) -{ - platform_driver_unregister(&bfin_dpmc_device_driver); -} -module_exit(bfin_dpmc_exit); +module_platform_driver(bfin_dpmc_device_driver); MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); MODULE_DESCRIPTION("cpu power management driver for Blackfin"); diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S index 9cfdd49a312..de99f3aac2c 100644 --- a/arch/blackfin/mach-common/dpmc_modes.S +++ b/arch/blackfin/mach-common/dpmc_modes.S @@ -10,10 +10,9 @@ #include <asm/dpmc.h> .section .l1.text - ENTRY(_sleep_mode) - [--SP] = ( R7:0, P5:0 ); - [--SP] = RETS; + [--SP] = (R7:4, P5:3); + [--SP] = RETS; call _set_sic_iwr; @@ -43,18 +42,32 @@ ENTRY(_sleep_mode) BITCLR (R7, 5); w[p0] = R7.L; IDLE; + + bfin_init_pm_bench_cycles; + call _test_pll_locked; RETS = [SP++]; - ( R7:0, P5:0 ) = [SP++]; + (R7:4, P5:3) = [SP++]; RTS; ENDPROC(_sleep_mode) +/* + * This func never returns as it puts the part into hibernate, and + * is only called from do_hibernate, so we don't bother saving or + * restoring any of the normal C runtime state. When we wake up, + * the entry point will be in do_hibernate and not here. + * + * We accept just one argument -- the value to write to VR_CTL. + */ + ENTRY(_hibernate_mode) - [--SP] = ( R7:0, P5:0 ); - [--SP] = RETS; + /* Save/setup the regs we need early for minor pipeline optimization */ + R4 = R0; - R3 = R0; + P3.H = hi(VR_CTL); + P3.L = lo(VR_CTL); + /* Disable all wakeup sources */ R0 = IWR_DISABLE_ALL; R1 = IWR_DISABLE_ALL; R2 = IWR_DISABLE_ALL; @@ -62,10 +75,11 @@ ENTRY(_hibernate_mode) call _set_dram_srfs; SSYNC; - P0.H = hi(VR_CTL); - P0.L = lo(VR_CTL); + /* Finally, we climb into our cave to hibernate */ + W[P3] = R4.L; + + bfin_init_pm_bench_cycles; - W[P0] = R3.L; CLI R2; IDLE; .Lforever: @@ -73,8 +87,8 @@ ENTRY(_hibernate_mode) ENDPROC(_hibernate_mode) ENTRY(_sleep_deeper) - [--SP] = ( R7:0, P5:0 ); - [--SP] = RETS; + [--SP] = (R7:4, P5:3); + [--SP] = RETS; CLI R4; @@ -150,6 +164,8 @@ ENTRY(_sleep_deeper) SSYNC; IDLE; + bfin_init_pm_bench_cycles; + call _test_pll_locked; P0.H = hi(PLL_DIV); @@ -167,7 +183,7 @@ ENTRY(_sleep_deeper) STI R4; RETS = [SP++]; - ( R7:0, P5:0 ) = [SP++]; + (R7:4, P5:3) = [SP++]; RTS; ENDPROC(_sleep_deeper) @@ -188,21 +204,20 @@ ENTRY(_set_dram_srfs) #else /* SDRAM */ P0.L = lo(EBIU_SDGCTL); P0.H = hi(EBIU_SDGCTL); + P1.L = lo(EBIU_SDSTAT); + P1.H = hi(EBIU_SDSTAT); + R2 = [P0]; BITSET(R2, 24); /* SRFS enter self-refresh mode */ [P0] = R2; SSYNC; - P0.L = lo(EBIU_SDSTAT); - P0.H = hi(EBIU_SDSTAT); 1: - R2 = w[P0]; + R2 = w[P1]; SSYNC; cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */ if !cc jump 1b; - P0.L = lo(EBIU_SDGCTL); - P0.H = hi(EBIU_SDGCTL); R2 = [P0]; BITCLR(R2, 0); /* SCTLE disable CLKOUT */ [P0] = R2; @@ -212,6 +227,7 @@ ENDPROC(_set_dram_srfs) ENTRY(_unset_dram_srfs) /* set the dram out of self refresh mode */ + #if defined(EBIU_RSTCTL) /* DDR */ P0.H = hi(EBIU_RSTCTL); P0.L = lo(EBIU_RSTCTL); @@ -219,42 +235,39 @@ ENTRY(_unset_dram_srfs) BITCLR(R2, 3); /* clear SRREQ bit */ [P0] = R2; #elif defined(EBIU_SDGCTL) /* SDRAM */ - - P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */ + /* release CLKOUT from self-refresh */ + P0.L = lo(EBIU_SDGCTL); P0.H = hi(EBIU_SDGCTL); + R2 = [P0]; BITSET(R2, 0); /* SCTLE enable CLKOUT */ [P0] = R2 SSYNC; - P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */ - P0.H = hi(EBIU_SDGCTL); + /* release SDRAM from self-refresh */ R2 = [P0]; BITCLR(R2, 24); /* clear SRFS bit */ [P0] = R2 #endif + SSYNC; RTS; ENDPROC(_unset_dram_srfs) ENTRY(_set_sic_iwr) -#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \ - defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x) - P0.H = hi(SIC_IWR0); - P0.L = lo(SIC_IWR0); - P1.H = hi(SIC_IWR1); - P1.L = lo(SIC_IWR1); - [P1] = R1; -#if defined(CONFIG_BF54x) - P1.H = hi(SIC_IWR2); - P1.L = lo(SIC_IWR2); - [P1] = R2; -#endif +#ifdef SIC_IWR0 + P0.H = hi(SYSMMR_BASE); + P0.L = lo(SYSMMR_BASE); + [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0; + [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1; +# ifdef SIC_IWR2 + [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2; +# endif #else P0.H = hi(SIC_IWR); P0.L = lo(SIC_IWR); -#endif [P0] = R0; +#endif SSYNC; RTS; @@ -271,514 +284,37 @@ ENTRY(_test_pll_locked) ENDPROC(_test_pll_locked) .section .text - ENTRY(_do_hibernate) - [--SP] = ( R7:0, P5:0 ); - [--SP] = RETS; - /* Save System MMRs */ - R2 = R0; - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); + bfin_cpu_reg_save; + bfin_sys_mmr_save; + bfin_core_mmr_save; -#ifdef SIC_IMASK0 - PM_SYS_PUSH(SIC_IMASK0) -#endif -#ifdef SIC_IMASK1 - PM_SYS_PUSH(SIC_IMASK1) -#endif -#ifdef SIC_IMASK2 - PM_SYS_PUSH(SIC_IMASK2) -#endif -#ifdef SIC_IMASK - PM_SYS_PUSH(SIC_IMASK) -#endif -#ifdef SIC_IAR0 - PM_SYS_PUSH(SIC_IAR0) - PM_SYS_PUSH(SIC_IAR1) - PM_SYS_PUSH(SIC_IAR2) -#endif -#ifdef SIC_IAR3 - PM_SYS_PUSH(SIC_IAR3) -#endif -#ifdef SIC_IAR4 - PM_SYS_PUSH(SIC_IAR4) - PM_SYS_PUSH(SIC_IAR5) - PM_SYS_PUSH(SIC_IAR6) -#endif -#ifdef SIC_IAR7 - PM_SYS_PUSH(SIC_IAR7) -#endif -#ifdef SIC_IAR8 - PM_SYS_PUSH(SIC_IAR8) - PM_SYS_PUSH(SIC_IAR9) - PM_SYS_PUSH(SIC_IAR10) - PM_SYS_PUSH(SIC_IAR11) -#endif - -#ifdef SIC_IWR - PM_SYS_PUSH(SIC_IWR) -#endif -#ifdef SIC_IWR0 - PM_SYS_PUSH(SIC_IWR0) -#endif -#ifdef SIC_IWR1 - PM_SYS_PUSH(SIC_IWR1) -#endif -#ifdef SIC_IWR2 - PM_SYS_PUSH(SIC_IWR2) -#endif - -#ifdef PINT0_ASSIGN - PM_SYS_PUSH(PINT0_MASK_SET) - PM_SYS_PUSH(PINT1_MASK_SET) - PM_SYS_PUSH(PINT2_MASK_SET) - PM_SYS_PUSH(PINT3_MASK_SET) - PM_SYS_PUSH(PINT0_ASSIGN) - PM_SYS_PUSH(PINT1_ASSIGN) - PM_SYS_PUSH(PINT2_ASSIGN) - PM_SYS_PUSH(PINT3_ASSIGN) - PM_SYS_PUSH(PINT0_INVERT_SET) - PM_SYS_PUSH(PINT1_INVERT_SET) - PM_SYS_PUSH(PINT2_INVERT_SET) - PM_SYS_PUSH(PINT3_INVERT_SET) - PM_SYS_PUSH(PINT0_EDGE_SET) - PM_SYS_PUSH(PINT1_EDGE_SET) - PM_SYS_PUSH(PINT2_EDGE_SET) - PM_SYS_PUSH(PINT3_EDGE_SET) -#endif - - PM_SYS_PUSH(EBIU_AMBCTL0) - PM_SYS_PUSH(EBIU_AMBCTL1) - PM_SYS_PUSH16(EBIU_AMGCTL) - -#ifdef EBIU_FCTL - PM_SYS_PUSH(EBIU_MBSCTL) - PM_SYS_PUSH(EBIU_MODE) - PM_SYS_PUSH(EBIU_FCTL) -#endif - -#ifdef PORTCIO_FER - PM_SYS_PUSH16(PORTCIO_DIR) - PM_SYS_PUSH16(PORTCIO_INEN) - PM_SYS_PUSH16(PORTCIO) - PM_SYS_PUSH16(PORTCIO_FER) - PM_SYS_PUSH16(PORTDIO_DIR) - PM_SYS_PUSH16(PORTDIO_INEN) - PM_SYS_PUSH16(PORTDIO) - PM_SYS_PUSH16(PORTDIO_FER) - PM_SYS_PUSH16(PORTEIO_DIR) - PM_SYS_PUSH16(PORTEIO_INEN) - PM_SYS_PUSH16(PORTEIO) - PM_SYS_PUSH16(PORTEIO_FER) -#endif - - PM_SYS_PUSH16(SYSCR) - - /* Save Core MMRs */ - P0.H = hi(SRAM_BASE_ADDRESS); - P0.L = lo(SRAM_BASE_ADDRESS); - - PM_PUSH(DMEM_CONTROL) - PM_PUSH(DCPLB_ADDR0) - PM_PUSH(DCPLB_ADDR1) - PM_PUSH(DCPLB_ADDR2) - PM_PUSH(DCPLB_ADDR3) - PM_PUSH(DCPLB_ADDR4) - PM_PUSH(DCPLB_ADDR5) - PM_PUSH(DCPLB_ADDR6) - PM_PUSH(DCPLB_ADDR7) - PM_PUSH(DCPLB_ADDR8) - PM_PUSH(DCPLB_ADDR9) - PM_PUSH(DCPLB_ADDR10) - PM_PUSH(DCPLB_ADDR11) - PM_PUSH(DCPLB_ADDR12) - PM_PUSH(DCPLB_ADDR13) - PM_PUSH(DCPLB_ADDR14) - PM_PUSH(DCPLB_ADDR15) - PM_PUSH(DCPLB_DATA0) - PM_PUSH(DCPLB_DATA1) - PM_PUSH(DCPLB_DATA2) - PM_PUSH(DCPLB_DATA3) - PM_PUSH(DCPLB_DATA4) - PM_PUSH(DCPLB_DATA5) - PM_PUSH(DCPLB_DATA6) - PM_PUSH(DCPLB_DATA7) - PM_PUSH(DCPLB_DATA8) - PM_PUSH(DCPLB_DATA9) - PM_PUSH(DCPLB_DATA10) - PM_PUSH(DCPLB_DATA11) - PM_PUSH(DCPLB_DATA12) - PM_PUSH(DCPLB_DATA13) - PM_PUSH(DCPLB_DATA14) - PM_PUSH(DCPLB_DATA15) - PM_PUSH(IMEM_CONTROL) - PM_PUSH(ICPLB_ADDR0) - PM_PUSH(ICPLB_ADDR1) - PM_PUSH(ICPLB_ADDR2) - PM_PUSH(ICPLB_ADDR3) - PM_PUSH(ICPLB_ADDR4) - PM_PUSH(ICPLB_ADDR5) - PM_PUSH(ICPLB_ADDR6) - PM_PUSH(ICPLB_ADDR7) - PM_PUSH(ICPLB_ADDR8) - PM_PUSH(ICPLB_ADDR9) - PM_PUSH(ICPLB_ADDR10) - PM_PUSH(ICPLB_ADDR11) - PM_PUSH(ICPLB_ADDR12) - PM_PUSH(ICPLB_ADDR13) - PM_PUSH(ICPLB_ADDR14) - PM_PUSH(ICPLB_ADDR15) - PM_PUSH(ICPLB_DATA0) - PM_PUSH(ICPLB_DATA1) - PM_PUSH(ICPLB_DATA2) - PM_PUSH(ICPLB_DATA3) - PM_PUSH(ICPLB_DATA4) - PM_PUSH(ICPLB_DATA5) - PM_PUSH(ICPLB_DATA6) - PM_PUSH(ICPLB_DATA7) - PM_PUSH(ICPLB_DATA8) - PM_PUSH(ICPLB_DATA9) - PM_PUSH(ICPLB_DATA10) - PM_PUSH(ICPLB_DATA11) - PM_PUSH(ICPLB_DATA12) - PM_PUSH(ICPLB_DATA13) - PM_PUSH(ICPLB_DATA14) - PM_PUSH(ICPLB_DATA15) - PM_PUSH(EVT0) - PM_PUSH(EVT1) - PM_PUSH(EVT2) - PM_PUSH(EVT3) - PM_PUSH(EVT4) - PM_PUSH(EVT5) - PM_PUSH(EVT6) - PM_PUSH(EVT7) - PM_PUSH(EVT8) - PM_PUSH(EVT9) - PM_PUSH(EVT10) - PM_PUSH(EVT11) - PM_PUSH(EVT12) - PM_PUSH(EVT13) - PM_PUSH(EVT14) - PM_PUSH(EVT15) - PM_PUSH(IMASK) - PM_PUSH(ILAT) - PM_PUSH(IPRIO) - PM_PUSH(TCNTL) - PM_PUSH(TPERIOD) - PM_PUSH(TSCALE) - PM_PUSH(TCOUNT) - PM_PUSH(TBUFCTL) - - /* Save Core Registers */ - [--sp] = SYSCFG; - [--sp] = ( R7:0, P5:0 ); - [--sp] = fp; - [--sp] = usp; - - [--sp] = i0; - [--sp] = i1; - [--sp] = i2; - [--sp] = i3; - - [--sp] = m0; - [--sp] = m1; - [--sp] = m2; - [--sp] = m3; - - [--sp] = l0; - [--sp] = l1; - [--sp] = l2; - [--sp] = l3; - - [--sp] = b0; - [--sp] = b1; - [--sp] = b2; - [--sp] = b3; - [--sp] = a0.x; - [--sp] = a0.w; - [--sp] = a1.x; - [--sp] = a1.w; - - [--sp] = LC0; - [--sp] = LC1; - [--sp] = LT0; - [--sp] = LT1; - [--sp] = LB0; - [--sp] = LB1; - - [--sp] = ASTAT; - [--sp] = CYCLES; - [--sp] = CYCLES2; - - [--sp] = RETS; - r0 = RETI; - [--sp] = r0; - [--sp] = RETX; - [--sp] = RETN; - [--sp] = RETE; - [--sp] = SEQSTAT; + /* Setup args to hibernate mode early for pipeline optimization */ + R0 = M3; + P1.H = _hibernate_mode; + P1.L = _hibernate_mode; /* Save Magic, return address and Stack Pointer */ - P0.H = 0; - P0.L = 0; - R0.H = 0xDEAD; /* Hibernate Magic */ - R0.L = 0xBEEF; - [P0++] = R0; /* Store Hibernate Magic */ - R0.H = .Lpm_resume_here; - R0.L = .Lpm_resume_here; - [P0++] = R0; /* Save Return Address */ + P0 = 0; + R1.H = 0xDEAD; /* Hibernate Magic */ + R1.L = 0xBEEF; + R2.H = .Lpm_resume_here; + R2.L = .Lpm_resume_here; + [P0++] = R1; /* Store Hibernate Magic */ + [P0++] = R2; /* Save Return Address */ [P0++] = SP; /* Save Stack Pointer */ - P0.H = _hibernate_mode; - P0.L = _hibernate_mode; - R0 = R2; - call (P0); /* Goodbye */ -.Lpm_resume_here: + /* Must use an indirect call as we need to jump to L1 */ + call (P1); /* Goodbye */ - /* Restore Core Registers */ - SEQSTAT = [sp++]; - RETE = [sp++]; - RETN = [sp++]; - RETX = [sp++]; - r0 = [sp++]; - RETI = r0; - RETS = [sp++]; - - CYCLES2 = [sp++]; - CYCLES = [sp++]; - ASTAT = [sp++]; - - LB1 = [sp++]; - LB0 = [sp++]; - LT1 = [sp++]; - LT0 = [sp++]; - LC1 = [sp++]; - LC0 = [sp++]; - - a1.w = [sp++]; - a1.x = [sp++]; - a0.w = [sp++]; - a0.x = [sp++]; - b3 = [sp++]; - b2 = [sp++]; - b1 = [sp++]; - b0 = [sp++]; - - l3 = [sp++]; - l2 = [sp++]; - l1 = [sp++]; - l0 = [sp++]; - - m3 = [sp++]; - m2 = [sp++]; - m1 = [sp++]; - m0 = [sp++]; - - i3 = [sp++]; - i2 = [sp++]; - i1 = [sp++]; - i0 = [sp++]; - - usp = [sp++]; - fp = [sp++]; - - ( R7 : 0, P5 : 0) = [ SP ++ ]; - SYSCFG = [sp++]; - - /* Restore Core MMRs */ - - PM_POP(TBUFCTL) - PM_POP(TCOUNT) - PM_POP(TSCALE) - PM_POP(TPERIOD) - PM_POP(TCNTL) - PM_POP(IPRIO) - PM_POP(ILAT) - PM_POP(IMASK) - PM_POP(EVT15) - PM_POP(EVT14) - PM_POP(EVT13) - PM_POP(EVT12) - PM_POP(EVT11) - PM_POP(EVT10) - PM_POP(EVT9) - PM_POP(EVT8) - PM_POP(EVT7) - PM_POP(EVT6) - PM_POP(EVT5) - PM_POP(EVT4) - PM_POP(EVT3) - PM_POP(EVT2) - PM_POP(EVT1) - PM_POP(EVT0) - PM_POP(ICPLB_DATA15) - PM_POP(ICPLB_DATA14) - PM_POP(ICPLB_DATA13) - PM_POP(ICPLB_DATA12) - PM_POP(ICPLB_DATA11) - PM_POP(ICPLB_DATA10) - PM_POP(ICPLB_DATA9) - PM_POP(ICPLB_DATA8) - PM_POP(ICPLB_DATA7) - PM_POP(ICPLB_DATA6) - PM_POP(ICPLB_DATA5) - PM_POP(ICPLB_DATA4) - PM_POP(ICPLB_DATA3) - PM_POP(ICPLB_DATA2) - PM_POP(ICPLB_DATA1) - PM_POP(ICPLB_DATA0) - PM_POP(ICPLB_ADDR15) - PM_POP(ICPLB_ADDR14) - PM_POP(ICPLB_ADDR13) - PM_POP(ICPLB_ADDR12) - PM_POP(ICPLB_ADDR11) - PM_POP(ICPLB_ADDR10) - PM_POP(ICPLB_ADDR9) - PM_POP(ICPLB_ADDR8) - PM_POP(ICPLB_ADDR7) - PM_POP(ICPLB_ADDR6) - PM_POP(ICPLB_ADDR5) - PM_POP(ICPLB_ADDR4) - PM_POP(ICPLB_ADDR3) - PM_POP(ICPLB_ADDR2) - PM_POP(ICPLB_ADDR1) - PM_POP(ICPLB_ADDR0) - PM_POP(IMEM_CONTROL) - PM_POP(DCPLB_DATA15) - PM_POP(DCPLB_DATA14) - PM_POP(DCPLB_DATA13) - PM_POP(DCPLB_DATA12) - PM_POP(DCPLB_DATA11) - PM_POP(DCPLB_DATA10) - PM_POP(DCPLB_DATA9) - PM_POP(DCPLB_DATA8) - PM_POP(DCPLB_DATA7) - PM_POP(DCPLB_DATA6) - PM_POP(DCPLB_DATA5) - PM_POP(DCPLB_DATA4) - PM_POP(DCPLB_DATA3) - PM_POP(DCPLB_DATA2) - PM_POP(DCPLB_DATA1) - PM_POP(DCPLB_DATA0) - PM_POP(DCPLB_ADDR15) - PM_POP(DCPLB_ADDR14) - PM_POP(DCPLB_ADDR13) - PM_POP(DCPLB_ADDR12) - PM_POP(DCPLB_ADDR11) - PM_POP(DCPLB_ADDR10) - PM_POP(DCPLB_ADDR9) - PM_POP(DCPLB_ADDR8) - PM_POP(DCPLB_ADDR7) - PM_POP(DCPLB_ADDR6) - PM_POP(DCPLB_ADDR5) - PM_POP(DCPLB_ADDR4) - PM_POP(DCPLB_ADDR3) - PM_POP(DCPLB_ADDR2) - PM_POP(DCPLB_ADDR1) - PM_POP(DCPLB_ADDR0) - PM_POP(DMEM_CONTROL) - - /* Restore System MMRs */ - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - PM_SYS_POP16(SYSCR) - -#ifdef PORTCIO_FER - PM_SYS_POP16(PORTEIO_FER) - PM_SYS_POP16(PORTEIO) - PM_SYS_POP16(PORTEIO_INEN) - PM_SYS_POP16(PORTEIO_DIR) - PM_SYS_POP16(PORTDIO_FER) - PM_SYS_POP16(PORTDIO) - PM_SYS_POP16(PORTDIO_INEN) - PM_SYS_POP16(PORTDIO_DIR) - PM_SYS_POP16(PORTCIO_FER) - PM_SYS_POP16(PORTCIO) - PM_SYS_POP16(PORTCIO_INEN) - PM_SYS_POP16(PORTCIO_DIR) -#endif - -#ifdef EBIU_FCTL - PM_SYS_POP(EBIU_FCTL) - PM_SYS_POP(EBIU_MODE) - PM_SYS_POP(EBIU_MBSCTL) -#endif - PM_SYS_POP16(EBIU_AMGCTL) - PM_SYS_POP(EBIU_AMBCTL1) - PM_SYS_POP(EBIU_AMBCTL0) - -#ifdef PINT0_ASSIGN - PM_SYS_POP(PINT3_EDGE_SET) - PM_SYS_POP(PINT2_EDGE_SET) - PM_SYS_POP(PINT1_EDGE_SET) - PM_SYS_POP(PINT0_EDGE_SET) - PM_SYS_POP(PINT3_INVERT_SET) - PM_SYS_POP(PINT2_INVERT_SET) - PM_SYS_POP(PINT1_INVERT_SET) - PM_SYS_POP(PINT0_INVERT_SET) - PM_SYS_POP(PINT3_ASSIGN) - PM_SYS_POP(PINT2_ASSIGN) - PM_SYS_POP(PINT1_ASSIGN) - PM_SYS_POP(PINT0_ASSIGN) - PM_SYS_POP(PINT3_MASK_SET) - PM_SYS_POP(PINT2_MASK_SET) - PM_SYS_POP(PINT1_MASK_SET) - PM_SYS_POP(PINT0_MASK_SET) -#endif - -#ifdef SIC_IWR2 - PM_SYS_POP(SIC_IWR2) -#endif -#ifdef SIC_IWR1 - PM_SYS_POP(SIC_IWR1) -#endif -#ifdef SIC_IWR0 - PM_SYS_POP(SIC_IWR0) -#endif -#ifdef SIC_IWR - PM_SYS_POP(SIC_IWR) -#endif +.Lpm_resume_here: -#ifdef SIC_IAR8 - PM_SYS_POP(SIC_IAR11) - PM_SYS_POP(SIC_IAR10) - PM_SYS_POP(SIC_IAR9) - PM_SYS_POP(SIC_IAR8) -#endif -#ifdef SIC_IAR7 - PM_SYS_POP(SIC_IAR7) -#endif -#ifdef SIC_IAR6 - PM_SYS_POP(SIC_IAR6) - PM_SYS_POP(SIC_IAR5) - PM_SYS_POP(SIC_IAR4) -#endif -#ifdef SIC_IAR3 - PM_SYS_POP(SIC_IAR3) -#endif -#ifdef SIC_IAR0 - PM_SYS_POP(SIC_IAR2) - PM_SYS_POP(SIC_IAR1) - PM_SYS_POP(SIC_IAR0) -#endif -#ifdef SIC_IMASK - PM_SYS_POP(SIC_IMASK) -#endif -#ifdef SIC_IMASK2 - PM_SYS_POP(SIC_IMASK2) -#endif -#ifdef SIC_IMASK1 - PM_SYS_POP(SIC_IMASK1) -#endif -#ifdef SIC_IMASK0 - PM_SYS_POP(SIC_IMASK0) -#endif + bfin_core_mmr_restore; + bfin_sys_mmr_restore; + bfin_cpu_reg_restore; [--sp] = RETI; /* Clear Global Interrupt Disable */ SP += 4; - RETS = [SP++]; - ( R7:0, P5:0 ) = [SP++]; RTS; ENDPROC(_do_hibernate) diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index 757943f620e..86b5a095c5a 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -25,13 +25,6 @@ #include <asm/context.S> -#if defined(CONFIG_BFIN_SCRATCH_REG_RETN) -# define EX_SCRATCH_REG RETN -#elif defined(CONFIG_BFIN_SCRATCH_REG_RETE) -# define EX_SCRATCH_REG RETE -#else -# define EX_SCRATCH_REG CYCLES -#endif #ifdef CONFIG_EXCPT_IRQ_SYSC_L1 .section .l1.text @@ -268,7 +261,7 @@ ENTRY(_handle_bad_cplb) /* To get here, we just tried and failed to change a CPLB * so, handle things in trap_c (C code), by lowering to * IRQ5, just like we normally do. Since this is not a - * "normal" return path, we have a do alot of stuff to + * "normal" return path, we have a do a lot of stuff to * the stack to get ready so, we can fall through - we * need to make a CPLB exception look like a normal exception */ @@ -537,61 +530,6 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/ jump .Lsyscall_really_exit; ENDPROC(_trap) -ENTRY(_kernel_execve) - link SIZEOF_PTREGS; - p0 = sp; - r3 = SIZEOF_PTREGS / 4; - r4 = 0(x); -.Lclear_regs: - [p0++] = r4; - r3 += -1; - cc = r3 == 0; - if !cc jump .Lclear_regs (bp); - - p0 = sp; - sp += -16; - [sp + 12] = p0; - pseudo_long_call _do_execve, p5; - SP += 16; - cc = r0 == 0; - if ! cc jump .Lexecve_failed; - /* Success. Copy our temporary pt_regs to the top of the kernel - * stack and do a normal exception return. - */ - r1 = sp; - r0 = (-KERNEL_STACK_SIZE) (x); - r1 = r1 & r0; - p2 = r1; - p3 = [p2]; - r0 = KERNEL_STACK_SIZE - 4 (z); - p1 = r0; - p1 = p1 + p2; - - p0 = fp; - r4 = [p0--]; - r3 = SIZEOF_PTREGS / 4; -.Lcopy_regs: - r4 = [p0--]; - [p1--] = r4; - r3 += -1; - cc = r3 == 0; - if ! cc jump .Lcopy_regs (bp); - - r0 = (KERNEL_STACK_SIZE - SIZEOF_PTREGS) (z); - p1 = r0; - p1 = p1 + p2; - sp = p1; - r0 = syscfg; - [SP + PT_SYSCFG] = r0; - [p3 + (TASK_THREAD + THREAD_KSP)] = sp; - - RESTORE_CONTEXT; - rti; -.Lexecve_failed: - unlink; - rts; -ENDPROC(_kernel_execve) - ENTRY(_system_call) /* Store IPEND */ p2.l = lo(IPEND); @@ -711,8 +649,6 @@ ENTRY(_system_call) jump .Lresume_userspace_1; .Lsyscall_sigpending: - cc = BITTST(r7, TIF_RESTORE_SIGMASK); - if cc jump .Lsyscall_do_signals; cc = BITTST(r7, TIF_SIGPENDING); if cc jump .Lsyscall_do_signals; cc = BITTST(r7, TIF_NOTIFY_RESUME); @@ -817,7 +753,7 @@ _new_old_task: rets = [sp++]; /* - * When we come out of resume, r0 carries "old" task, becuase we are + * When we come out of resume, r0 carries "old" task, because we are * in "new" task. */ rts; @@ -1141,7 +1077,8 @@ ENTRY(_schedule_and_signal_from_int) sti r0; /* finish the userspace "atomic" functions for it */ - r1 = FIXED_CODE_END; + r1.l = lo(FIXED_CODE_END); + r1.h = hi(FIXED_CODE_END); r2 = [sp + PT_PC]; cc = r1 <= r2; if cc jump .Lresume_userspace (bp); @@ -1244,7 +1181,7 @@ ENTRY(_software_trace_buff) .endr #endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND */ -#if CONFIG_EARLY_PRINTK +#ifdef CONFIG_EARLY_PRINTK __INIT ENTRY(_early_trap) SAVE_ALL_SYS @@ -1376,7 +1313,7 @@ END(_ex_table) ENTRY(_sys_call_table) .long _sys_restart_syscall /* 0 */ .long _sys_exit - .long _sys_fork + .long _sys_ni_syscall /* fork */ .long _sys_read .long _sys_write .long _sys_open /* 5 */ @@ -1494,7 +1431,7 @@ ENTRY(_sys_call_table) .long _sys_ni_syscall /* old sys_ipc */ .long _sys_fsync .long _sys_ni_syscall /* old sys_sigreturn */ - .long _sys_clone /* 120 */ + .long _bfin_clone /* 120 */ .long _sys_setdomainname .long _sys_newuname .long _sys_ni_syscall /* old sys_modify_ldt */ @@ -1543,7 +1480,7 @@ ENTRY(_sys_call_table) .long _sys_ni_syscall /* for vm86 */ .long _sys_ni_syscall /* old "query_module" */ .long _sys_ni_syscall /* sys_poll */ - .long _sys_nfsservctl + .long _sys_ni_syscall /* old nfsservctl */ .long _sys_setresgid /* setresgid16 */ /* 170 */ .long _sys_getresgid /* getresgid16 */ .long _sys_prctl @@ -1752,6 +1689,11 @@ ENTRY(_sys_call_table) .long _sys_name_to_handle_at /* 375 */ .long _sys_open_by_handle_at .long _sys_clock_adjtime + .long _sys_syncfs + .long _sys_setns + .long _sys_sendmmsg /* 380 */ + .long _sys_process_vm_readv + .long _sys_process_vm_writev .rept NR_syscalls-(.-_sys_call_table)/4 .long _sys_ni_syscall diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S index 581e2b0a71a..31515f0146f 100644 --- a/arch/blackfin/mach-common/head.S +++ b/arch/blackfin/mach-common/head.S @@ -85,37 +85,25 @@ ENTRY(__start) SSYNC; /* in case of double faults, save a few things */ - p0.l = _init_retx; - p0.h = _init_retx; - R0 = RETX; - [P0] = R0; - + p1.l = _initial_pda; + p1.h = _initial_pda; + r4 = RETX; #ifdef CONFIG_DEBUG_DOUBLEFAULT /* Only save these if we are storing them, * This happens here, since L1 gets clobbered * below */ GET_PDA(p0, r0); - r5 = [p0 + PDA_DF_RETX]; - p1.l = _init_saved_retx; - p1.h = _init_saved_retx; - [p1] = r5; - - r5 = [p0 + PDA_DF_DCPLB]; - p1.l = _init_saved_dcplb_fault_addr; - p1.h = _init_saved_dcplb_fault_addr; - [p1] = r5; - - r5 = [p0 + PDA_DF_ICPLB]; - p1.l = _init_saved_icplb_fault_addr; - p1.h = _init_saved_icplb_fault_addr; - [p1] = r5; - - r5 = [p0 + PDA_DF_SEQSTAT]; - p1.l = _init_saved_seqstat; - p1.h = _init_saved_seqstat; - [p1] = r5; + r0 = [p0 + PDA_DF_RETX]; + r1 = [p0 + PDA_DF_DCPLB]; + r2 = [p0 + PDA_DF_ICPLB]; + r3 = [p0 + PDA_DF_SEQSTAT]; + [p1 + PDA_INIT_DF_RETX] = r0; + [p1 + PDA_INIT_DF_DCPLB] = r1; + [p1 + PDA_INIT_DF_ICPLB] = r2; + [p1 + PDA_INIT_DF_SEQSTAT] = r3; #endif + [p1 + PDA_INIT_RETX] = r4; /* Initialize stack pointer */ sp.l = _init_thread_union + THREAD_SIZE; @@ -174,7 +162,7 @@ ENTRY(__start) sp.l = lo(KERNEL_CLOCK_STACK); sp.h = hi(KERNEL_CLOCK_STACK); call _init_clocks; - sp = usp; /* usp hasnt been touched, so restore from there */ + sp = usp; /* usp hasn't been touched, so restore from there */ #endif /* This section keeps the processor in supervisor mode @@ -222,14 +210,12 @@ ENDPROC(__start) ENTRY(_real_start) /* Enable nested interrupts */ [--sp] = reti; - /* watchdog off for now */ p0.l = lo(WDOG_CTL); p0.h = hi(WDOG_CTL); r0 = 0xAD6(z); w[p0] = r0; ssync; - /* Pass the u-boot arguments to the global value command line */ R0 = R7; call _cmdline_init; diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 6cd52395a99..1f94784eab6 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c @@ -16,34 +16,17 @@ #include <linux/seq_file.h> #include <linux/irq.h> #include <linux/sched.h> +#include <linux/syscore_ops.h> +#include <asm/delay.h> #ifdef CONFIG_IPIPE #include <linux/ipipe.h> #endif -#ifdef CONFIG_KGDB -#include <linux/kgdb.h> -#endif #include <asm/traps.h> #include <asm/blackfin.h> #include <asm/gpio.h> #include <asm/irq_handler.h> #include <asm/dpmc.h> -#include <asm/bfin5xx_spi.h> -#include <asm/bfin_sport.h> -#include <asm/bfin_can.h> - -#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) - -#ifdef BF537_FAMILY -# define BF537_GENERIC_ERROR_INT_DEMUX -# define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */ -# define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */ -# define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */ -# define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */ -# define UART_ERR_MASK (0x6) /* UART_IIR */ -# define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */ -#else -# undef BF537_GENERIC_ERROR_INT_DEMUX -#endif +#include <asm/traps.h> /* * NOTES: @@ -63,22 +46,20 @@ unsigned long bfin_irq_flags = 0x1f; EXPORT_SYMBOL(bfin_irq_flags); #endif -/* The number of spurious interrupts */ -atomic_t num_spurious; - #ifdef CONFIG_PM unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */ unsigned vr_wakeup; #endif -struct ivgx { +#ifndef SEC_GCTL +static struct ivgx { /* irq number for request_irq, available in mach-bf5xx/irq.h */ unsigned int irqno; /* corresponding bit in the SIC_ISR register */ unsigned int isrflag; } ivg_table[NR_PERI_INTS]; -struct ivg_slice { +static struct ivg_slice { /* position of first irq in ivg_table for given ivg */ struct ivgx *ifirst; struct ivgx *istop; @@ -99,7 +80,8 @@ static void __init search_IAR(void) for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) { int irqn; - u32 iar = bfin_read32((unsigned long *)SIC_IAR0 + + u32 iar = + bfin_read32((unsigned long *)SIC_IAR0 + #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \ defined(CONFIG_BF538) || defined(CONFIG_BF539) ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4)) @@ -107,7 +89,6 @@ static void __init search_IAR(void) (irqN >> 3) #endif ); - for (irqn = irqN; irqn < irqN + 4; ++irqn) { int iar_shift = (irqn & 7) * 4; if (ivg == (0xf & (iar >> iar_shift))) { @@ -120,12 +101,12 @@ static void __init search_IAR(void) } } } +#endif /* * This is for core internal IRQs */ - -static void bfin_ack_noop(struct irq_data *d) +void bfin_ack_noop(struct irq_data *d) { /* Dummy function. */ } @@ -154,26 +135,23 @@ static void bfin_core_unmask_irq(struct irq_data *d) return; } -static void bfin_internal_mask_irq(unsigned int irq) +#ifndef SEC_GCTL +void bfin_internal_mask_irq(unsigned int irq) { - unsigned long flags; - -#ifdef CONFIG_BF53x - flags = hard_local_irq_save(); - bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & - ~(1 << SIC_SYSIRQ(irq))); -#else - unsigned mask_bank, mask_bit; - flags = hard_local_irq_save(); - mask_bank = SIC_SYSIRQ(irq) / 32; - mask_bit = SIC_SYSIRQ(irq) % 32; + unsigned long flags = hard_local_irq_save(); +#ifdef SIC_IMASK0 + unsigned mask_bank = BFIN_SYSIRQ(irq) / 32; + unsigned mask_bit = BFIN_SYSIRQ(irq) % 32; bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & - ~(1 << mask_bit)); -#ifdef CONFIG_SMP + ~(1 << mask_bit)); +# if defined(CONFIG_SMP) || defined(CONFIG_ICC) bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) & - ~(1 << mask_bit)); -#endif -#endif + ~(1 << mask_bit)); +# endif +#else + bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & + ~(1 << BFIN_SYSIRQ(irq))); +#endif /* end of SIC_IMASK0 */ hard_local_irq_restore(flags); } @@ -183,35 +161,32 @@ static void bfin_internal_mask_irq_chip(struct irq_data *d) } #ifdef CONFIG_SMP -static void bfin_internal_unmask_irq_affinity(unsigned int irq, +void bfin_internal_unmask_irq_affinity(unsigned int irq, const struct cpumask *affinity) #else -static void bfin_internal_unmask_irq(unsigned int irq) +void bfin_internal_unmask_irq(unsigned int irq) #endif { - unsigned long flags; + unsigned long flags = hard_local_irq_save(); -#ifdef CONFIG_BF53x - flags = hard_local_irq_save(); - bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | - (1 << SIC_SYSIRQ(irq))); -#else - unsigned mask_bank, mask_bit; - flags = hard_local_irq_save(); - mask_bank = SIC_SYSIRQ(irq) / 32; - mask_bit = SIC_SYSIRQ(irq) % 32; -#ifdef CONFIG_SMP +#ifdef SIC_IMASK0 + unsigned mask_bank = BFIN_SYSIRQ(irq) / 32; + unsigned mask_bit = BFIN_SYSIRQ(irq) % 32; +# ifdef CONFIG_SMP if (cpumask_test_cpu(0, affinity)) -#endif +# endif bfin_write_SIC_IMASK(mask_bank, - bfin_read_SIC_IMASK(mask_bank) | - (1 << mask_bit)); -#ifdef CONFIG_SMP + bfin_read_SIC_IMASK(mask_bank) | + (1 << mask_bit)); +# ifdef CONFIG_SMP if (cpumask_test_cpu(1, affinity)) bfin_write_SICB_IMASK(mask_bank, - bfin_read_SICB_IMASK(mask_bank) | - (1 << mask_bit)); -#endif + bfin_read_SICB_IMASK(mask_bank) | + (1 << mask_bit)); +# endif +#else + bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | + (1 << BFIN_SYSIRQ(irq))); #endif hard_local_irq_restore(flags); } @@ -237,13 +212,13 @@ static void bfin_internal_unmask_irq_chip(struct irq_data *d) } #endif -#ifdef CONFIG_PM +#if defined(CONFIG_PM) int bfin_internal_set_wake(unsigned int irq, unsigned int state) { u32 bank, bit, wakeup = 0; unsigned long flags; - bank = SIC_SYSIRQ(irq) / 32; - bit = SIC_SYSIRQ(irq) % 32; + bank = BFIN_SYSIRQ(irq) / 32; + bit = BFIN_SYSIRQ(irq) % 32; switch (irq) { #ifdef IRQ_RTC @@ -295,32 +270,294 @@ static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state) { return bfin_internal_set_wake(d->irq, state); } +#else +inline int bfin_internal_set_wake(unsigned int irq, unsigned int state) +{ + return 0; +} +# define bfin_internal_set_wake_chip NULL #endif +#else /* SEC_GCTL */ +static void bfin_sec_preflow_handler(struct irq_data *d) +{ + unsigned long flags = hard_local_irq_save(); + unsigned int sid = BFIN_SYSIRQ(d->irq); + + bfin_write_SEC_SCI(0, SEC_CSID, sid); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_mask_ack_irq(struct irq_data *d) +{ + unsigned long flags = hard_local_irq_save(); + unsigned int sid = BFIN_SYSIRQ(d->irq); + + bfin_write_SEC_SCI(0, SEC_CSID, sid); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_unmask_irq(struct irq_data *d) +{ + unsigned long flags = hard_local_irq_save(); + unsigned int sid = BFIN_SYSIRQ(d->irq); + + bfin_write32(SEC_END, sid); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_enable_ssi(unsigned int sid) +{ + unsigned long flags = hard_local_irq_save(); + uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); + + reg_sctl |= SEC_SCTL_SRC_EN; + bfin_write_SEC_SCTL(sid, reg_sctl); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_disable_ssi(unsigned int sid) +{ + unsigned long flags = hard_local_irq_save(); + uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); + + reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN); + bfin_write_SEC_SCTL(sid, reg_sctl); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid) +{ + unsigned long flags = hard_local_irq_save(); + uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); + + reg_sctl &= ((uint32_t)~SEC_SCTL_CTG); + bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG)); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_enable_sci(unsigned int sid) +{ + unsigned long flags = hard_local_irq_save(); + uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); + + if (sid == BFIN_SYSIRQ(IRQ_WATCH0)) + reg_sctl |= SEC_SCTL_FAULT_EN; + else + reg_sctl |= SEC_SCTL_INT_EN; + bfin_write_SEC_SCTL(sid, reg_sctl); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_disable_sci(unsigned int sid) +{ + unsigned long flags = hard_local_irq_save(); + uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); + + reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN); + bfin_write_SEC_SCTL(sid, reg_sctl); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_enable(struct irq_data *d) +{ + unsigned long flags = hard_local_irq_save(); + unsigned int sid = BFIN_SYSIRQ(d->irq); + + bfin_sec_enable_sci(sid); + bfin_sec_enable_ssi(sid); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_disable(struct irq_data *d) +{ + unsigned long flags = hard_local_irq_save(); + unsigned int sid = BFIN_SYSIRQ(d->irq); + + bfin_sec_disable_sci(sid); + bfin_sec_disable_ssi(sid); + + hard_local_irq_restore(flags); +} + +static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority) +{ + unsigned long flags = hard_local_irq_save(); + uint32_t reg_sctl; + int i; + + bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels); + + for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) { + reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO; + reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET; + bfin_write_SEC_SCTL(i, reg_sctl); + } + + hard_local_irq_restore(flags); +} + +void bfin_sec_raise_irq(unsigned int irq) +{ + unsigned long flags = hard_local_irq_save(); + unsigned int sid = BFIN_SYSIRQ(irq); + + bfin_write32(SEC_RAISE, sid); + + hard_local_irq_restore(flags); +} + +static void init_software_driven_irq(void) +{ + bfin_sec_set_ssi_coreid(34, 0); + bfin_sec_set_ssi_coreid(35, 1); + + bfin_sec_enable_sci(35); + bfin_sec_enable_ssi(35); + bfin_sec_set_ssi_coreid(36, 0); + bfin_sec_set_ssi_coreid(37, 1); + bfin_sec_enable_sci(37); + bfin_sec_enable_ssi(37); +} + +void bfin_sec_resume(void) +{ + bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); + udelay(100); + bfin_write_SEC_GCTL(SEC_GCTL_EN); + bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); +} + +void handle_sec_sfi_fault(uint32_t gstat) +{ + +} + +void handle_sec_sci_fault(uint32_t gstat) +{ + uint32_t core_id; + uint32_t cstat; + + core_id = gstat & SEC_GSTAT_SCI; + cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT); + if (cstat & SEC_CSTAT_ERR) { + switch (cstat & SEC_CSTAT_ERRC) { + case SEC_CSTAT_ACKERR: + printk(KERN_DEBUG "sec ack err\n"); + break; + default: + printk(KERN_DEBUG "sec sci unknow err\n"); + } + } + +} + +void handle_sec_ssi_fault(uint32_t gstat) +{ + uint32_t sid; + uint32_t sstat; + + sid = gstat & SEC_GSTAT_SID; + sstat = bfin_read_SEC_SSTAT(sid); + +} + +void handle_sec_fault(uint32_t sec_gstat) +{ + if (sec_gstat & SEC_GSTAT_ERR) { + + switch (sec_gstat & SEC_GSTAT_ERRC) { + case 0: + handle_sec_sfi_fault(sec_gstat); + break; + case SEC_GSTAT_SCIERR: + handle_sec_sci_fault(sec_gstat); + break; + case SEC_GSTAT_SSIERR: + handle_sec_ssi_fault(sec_gstat); + break; + } + + + } +} + +static struct irqaction bfin_fault_irq = { + .name = "Blackfin fault", +}; + +static irqreturn_t bfin_fault_routine(int irq, void *data) +{ + struct pt_regs *fp = get_irq_regs(); + + switch (irq) { + case IRQ_C0_DBL_FAULT: + double_fault_c(fp); + break; + case IRQ_C0_HW_ERR: + dump_bfin_process(fp); + dump_bfin_mem(fp); + show_regs(fp); + printk(KERN_NOTICE "Kernel Stack\n"); + show_stack(current, NULL); + print_modules(); + panic("Core 0 hardware error"); + break; + case IRQ_C0_NMI_L1_PARITY_ERR: + panic("Core 0 NMI L1 parity error"); + break; + case IRQ_SEC_ERR: + pr_err("SEC error\n"); + handle_sec_fault(bfin_read32(SEC_GSTAT)); + break; + default: + panic("Unknown fault %d", irq); + } + + return IRQ_HANDLED; +} +#endif /* SEC_GCTL */ + static struct irq_chip bfin_core_irqchip = { .name = "CORE", - .irq_ack = bfin_ack_noop, .irq_mask = bfin_core_mask_irq, .irq_unmask = bfin_core_unmask_irq, }; +#ifndef SEC_GCTL static struct irq_chip bfin_internal_irqchip = { .name = "INTN", - .irq_ack = bfin_ack_noop, .irq_mask = bfin_internal_mask_irq_chip, .irq_unmask = bfin_internal_unmask_irq_chip, - .irq_mask_ack = bfin_internal_mask_irq_chip, .irq_disable = bfin_internal_mask_irq_chip, .irq_enable = bfin_internal_unmask_irq_chip, #ifdef CONFIG_SMP .irq_set_affinity = bfin_internal_set_affinity, #endif -#ifdef CONFIG_PM .irq_set_wake = bfin_internal_set_wake_chip, -#endif }; +#else +static struct irq_chip bfin_sec_irqchip = { + .name = "SEC", + .irq_mask_ack = bfin_sec_mask_ack_irq, + .irq_mask = bfin_sec_mask_ack_irq, + .irq_unmask = bfin_sec_unmask_irq, + .irq_eoi = bfin_sec_unmask_irq, + .irq_disable = bfin_sec_disable, + .irq_enable = bfin_sec_enable, +}; +#endif -static void bfin_handle_irq(unsigned irq) +void bfin_handle_irq(unsigned irq) { #ifdef CONFIG_IPIPE struct pt_regs regs; /* Contents not used. */ @@ -332,102 +569,6 @@ static void bfin_handle_irq(unsigned irq) #endif /* !CONFIG_IPIPE */ } -#ifdef BF537_GENERIC_ERROR_INT_DEMUX -static int error_int_mask; - -static void bfin_generic_error_mask_irq(struct irq_data *d) -{ - error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR)); - if (!error_int_mask) - bfin_internal_mask_irq(IRQ_GENERIC_ERROR); -} - -static void bfin_generic_error_unmask_irq(struct irq_data *d) -{ - bfin_internal_unmask_irq(IRQ_GENERIC_ERROR); - error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR); -} - -static struct irq_chip bfin_generic_error_irqchip = { - .name = "ERROR", - .irq_ack = bfin_ack_noop, - .irq_mask_ack = bfin_generic_error_mask_irq, - .irq_mask = bfin_generic_error_mask_irq, - .irq_unmask = bfin_generic_error_unmask_irq, -}; - -static void bfin_demux_error_irq(unsigned int int_err_irq, - struct irq_desc *inta_desc) -{ - int irq = 0; - -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) - if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK) - irq = IRQ_MAC_ERROR; - else -#endif - if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK) - irq = IRQ_SPORT0_ERROR; - else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK) - irq = IRQ_SPORT1_ERROR; - else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK) - irq = IRQ_PPI_ERROR; - else if (bfin_read_CAN_GIF() & CAN_ERR_MASK) - irq = IRQ_CAN_ERROR; - else if (bfin_read_SPI_STAT() & SPI_ERR_MASK) - irq = IRQ_SPI_ERROR; - else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK) - irq = IRQ_UART0_ERROR; - else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK) - irq = IRQ_UART1_ERROR; - - if (irq) { - if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) - bfin_handle_irq(irq); - else { - - switch (irq) { - case IRQ_PPI_ERROR: - bfin_write_PPI_STATUS(PPI_ERR_MASK); - break; -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) - case IRQ_MAC_ERROR: - bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK); - break; -#endif - case IRQ_SPORT0_ERROR: - bfin_write_SPORT0_STAT(SPORT_ERR_MASK); - break; - - case IRQ_SPORT1_ERROR: - bfin_write_SPORT1_STAT(SPORT_ERR_MASK); - break; - - case IRQ_CAN_ERROR: - bfin_write_CAN_GIS(CAN_ERR_MASK); - break; - - case IRQ_SPI_ERROR: - bfin_write_SPI_STAT(SPI_ERR_MASK); - break; - - default: - break; - } - - pr_debug("IRQ %d:" - " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n", - irq); - } - } else - printk(KERN_ERR - "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR" - " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", - __func__, __FILE__, __LINE__); - -} -#endif /* BF537_GENERIC_ERROR_INT_DEMUX */ - #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) static int mac_stat_int_mask; @@ -468,7 +609,7 @@ static void bfin_mac_status_mask_irq(struct irq_data *d) unsigned int irq = d->irq; mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT)); -#ifdef BF537_GENERIC_ERROR_INT_DEMUX +#ifdef BF537_FAMILY switch (irq) { case IRQ_MAC_PHYINT: bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE); @@ -487,7 +628,7 @@ static void bfin_mac_status_unmask_irq(struct irq_data *d) { unsigned int irq = d->irq; -#ifdef BF537_GENERIC_ERROR_INT_DEMUX +#ifdef BF537_FAMILY switch (irq) { case IRQ_MAC_PHYINT: bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE); @@ -505,27 +646,25 @@ static void bfin_mac_status_unmask_irq(struct irq_data *d) #ifdef CONFIG_PM int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state) { -#ifdef BF537_GENERIC_ERROR_INT_DEMUX +#ifdef BF537_FAMILY return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state); #else return bfin_internal_set_wake(IRQ_MAC_ERROR, state); #endif } +#else +# define bfin_mac_status_set_wake NULL #endif static struct irq_chip bfin_mac_status_irqchip = { .name = "MACST", - .irq_ack = bfin_ack_noop, - .irq_mask_ack = bfin_mac_status_mask_irq, .irq_mask = bfin_mac_status_mask_irq, .irq_unmask = bfin_mac_status_unmask_irq, -#ifdef CONFIG_PM .irq_set_wake = bfin_mac_status_set_wake, -#endif }; -static void bfin_demux_mac_status_irq(unsigned int int_err_irq, - struct irq_desc *inta_desc) +void bfin_demux_mac_status_irq(unsigned int int_err_irq, + struct irq_desc *inta_desc) { int i, irq = 0; u32 status = bfin_read_EMAC_SYSTAT(); @@ -542,15 +681,15 @@ static void bfin_demux_mac_status_irq(unsigned int int_err_irq, } else { bfin_mac_status_ack_irq(irq); pr_debug("IRQ %d:" - " MASKED MAC ERROR INTERRUPT ASSERTED\n", - irq); + " MASKED MAC ERROR INTERRUPT ASSERTED\n", + irq); } } else printk(KERN_ERR - "%s : %s : LINE %d :\nIRQ ?: MAC ERROR" - " INTERRUPT ASSERTED BUT NO SOURCE FOUND" - "(EMAC_SYSTAT=0x%X)\n", - __func__, __FILE__, __LINE__, status); + "%s : %s : LINE %d :\nIRQ ?: MAC ERROR" + " INTERRUPT ASSERTED BUT NO SOURCE FOUND" + "(EMAC_SYSTAT=0x%X)\n", + __func__, __FILE__, __LINE__, status); } #endif @@ -559,13 +698,12 @@ static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) #ifdef CONFIG_IPIPE handle = handle_level_irq; #endif - __set_irq_handler_unlocked(irq, handle); + __irq_set_handler_locked(irq, handle); } -static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); -extern void bfin_gpio_irq_prepare(unsigned gpio); +#ifdef CONFIG_GPIO_ADI -#if !defined(CONFIG_BF54x) +static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); static void bfin_gpio_ack_irq(struct irq_data *d) { @@ -578,10 +716,9 @@ static void bfin_gpio_ack_irq(struct irq_data *d) static void bfin_gpio_mask_ack_irq(struct irq_data *d) { unsigned int irq = d->irq; - struct irq_desc *desc = irq_to_desc(irq); u32 gpionr = irq_to_gpio(irq); - if (desc->handle_irq == handle_edge_irq) + if (!irqd_is_level_type(d)) set_gpio_data(gpionr, 0); set_gpio_maska(gpionr, 0); @@ -680,30 +817,40 @@ static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type) return 0; } -#ifdef CONFIG_PM -int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) +static void bfin_demux_gpio_block(unsigned int irq) { - return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state); + unsigned int gpio, mask; + + gpio = irq_to_gpio(irq); + mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio); + + while (mask) { + if (mask & 1) + bfin_handle_irq(irq); + irq++; + mask >>= 1; + } } -#endif -static void bfin_demux_gpio_irq(unsigned int inta_irq, - struct irq_desc *desc) +void bfin_demux_gpio_irq(unsigned int inta_irq, + struct irq_desc *desc) { - unsigned int i, gpio, mask, irq, search = 0; + unsigned int irq; switch (inta_irq) { -#if defined(CONFIG_BF53x) - case IRQ_PROG_INTA: - irq = IRQ_PF0; - search = 1; +#if defined(BF537_FAMILY) + case IRQ_PF_INTA_PG_INTA: + bfin_demux_gpio_block(IRQ_PF0); + irq = IRQ_PG0; break; -# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) - case IRQ_MAC_RX: + case IRQ_PH_INTA_MAC_RX: irq = IRQ_PH0; break; -# endif -#elif defined(CONFIG_BF538) || defined(CONFIG_BF539) +#elif defined(BF533_FAMILY) + case IRQ_PROG_INTA: + irq = IRQ_PF0; + break; +#elif defined(BF538_FAMILY) case IRQ_PORTF_INTA: irq = IRQ_PF0; break; @@ -733,373 +880,74 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq, return; } - if (search) { - for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { - irq += i; - - mask = get_gpiop_data(i) & get_gpiop_maska(i); - - while (mask) { - if (mask & 1) - bfin_handle_irq(irq); - irq++; - mask >>= 1; - } - } - } else { - gpio = irq_to_gpio(irq); - mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio); - - do { - if (mask & 1) - bfin_handle_irq(irq); - irq++; - mask >>= 1; - } while (mask); - } - -} - -#else /* CONFIG_BF54x */ - -#define NR_PINT_SYS_IRQS 4 -#define NR_PINT_BITS 32 -#define NR_PINTS 160 -#define IRQ_NOT_AVAIL 0xFF - -#define PINT_2_BANK(x) ((x) >> 5) -#define PINT_2_BIT(x) ((x) & 0x1F) -#define PINT_BIT(x) (1 << (PINT_2_BIT(x))) - -static unsigned char irq2pint_lut[NR_PINTS]; -static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; - -struct pin_int_t { - unsigned int mask_set; - unsigned int mask_clear; - unsigned int request; - unsigned int assign; - unsigned int edge_set; - unsigned int edge_clear; - unsigned int invert_set; - unsigned int invert_clear; - unsigned int pinstate; - unsigned int latch; -}; - -static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = { - (struct pin_int_t *)PINT0_MASK_SET, - (struct pin_int_t *)PINT1_MASK_SET, - (struct pin_int_t *)PINT2_MASK_SET, - (struct pin_int_t *)PINT3_MASK_SET, -}; - -inline unsigned int get_irq_base(u32 bank, u8 bmap) -{ - unsigned int irq_base; - - if (bank < 2) { /*PA-PB */ - irq_base = IRQ_PA0 + bmap * 16; - } else { /*PC-PJ */ - irq_base = IRQ_PC0 + bmap * 16; - } - - return irq_base; -} - - /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ -void init_pint_lut(void) -{ - u16 bank, bit, irq_base, bit_pos; - u32 pint_assign; - u8 bmap; - - memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut)); - - for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { - - pint_assign = pint[bank]->assign; - - for (bit = 0; bit < NR_PINT_BITS; bit++) { - - bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF; - - irq_base = get_irq_base(bank, bmap); - - irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0); - bit_pos = bit + bank * NR_PINT_BITS; - - pint2irq_lut[bit_pos] = irq_base - SYS_IRQS; - irq2pint_lut[irq_base - SYS_IRQS] = bit_pos; - } - } -} - -static void bfin_gpio_ack_irq(struct irq_data *d) -{ - struct irq_desc *desc = irq_to_desc(d->irq); - u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; - u32 pintbit = PINT_BIT(pint_val); - u32 bank = PINT_2_BANK(pint_val); - - if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { - if (pint[bank]->invert_set & pintbit) - pint[bank]->invert_clear = pintbit; - else - pint[bank]->invert_set = pintbit; - } - pint[bank]->request = pintbit; - -} - -static void bfin_gpio_mask_ack_irq(struct irq_data *d) -{ - struct irq_desc *desc = irq_to_desc(d->irq); - u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; - u32 pintbit = PINT_BIT(pint_val); - u32 bank = PINT_2_BANK(pint_val); - - if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { - if (pint[bank]->invert_set & pintbit) - pint[bank]->invert_clear = pintbit; - else - pint[bank]->invert_set = pintbit; - } - - pint[bank]->request = pintbit; - pint[bank]->mask_clear = pintbit; -} - -static void bfin_gpio_mask_irq(struct irq_data *d) -{ - u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; - - pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); -} - -static void bfin_gpio_unmask_irq(struct irq_data *d) -{ - u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; - u32 pintbit = PINT_BIT(pint_val); - u32 bank = PINT_2_BANK(pint_val); - - pint[bank]->mask_set = pintbit; + bfin_demux_gpio_block(irq); } -static unsigned int bfin_gpio_irq_startup(struct irq_data *d) -{ - unsigned int irq = d->irq; - u32 gpionr = irq_to_gpio(irq); - u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; - - if (pint_val == IRQ_NOT_AVAIL) { - printk(KERN_ERR - "GPIO IRQ %d :Not in PINT Assign table " - "Reconfigure Interrupt to Port Assignemt\n", irq); - return -ENODEV; - } - - if (__test_and_set_bit(gpionr, gpio_enabled)) - bfin_gpio_irq_prepare(gpionr); - - bfin_gpio_unmask_irq(d); - - return 0; -} +#ifdef CONFIG_PM -static void bfin_gpio_irq_shutdown(struct irq_data *d) +static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) { - u32 gpionr = irq_to_gpio(d->irq); - - bfin_gpio_mask_irq(d); - __clear_bit(gpionr, gpio_enabled); - bfin_gpio_irq_free(gpionr); + return bfin_gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state); } -static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type) -{ - unsigned int irq = d->irq; - int ret; - char buf[16]; - u32 gpionr = irq_to_gpio(irq); - u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; - u32 pintbit = PINT_BIT(pint_val); - u32 bank = PINT_2_BANK(pint_val); - - if (pint_val == IRQ_NOT_AVAIL) - return -ENODEV; - - if (type == IRQ_TYPE_PROBE) { - /* only probe unenabled GPIO interrupt lines */ - if (test_bit(gpionr, gpio_enabled)) - return 0; - type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; - } - - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | - IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { - - snprintf(buf, 16, "gpio-irq%d", irq); - ret = bfin_gpio_irq_request(gpionr, buf); - if (ret) - return ret; - - if (__test_and_set_bit(gpionr, gpio_enabled)) - bfin_gpio_irq_prepare(gpionr); - - } else { - __clear_bit(gpionr, gpio_enabled); - return 0; - } +#else - if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) - pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */ - else - pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */ +# define bfin_gpio_set_wake NULL - if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) - == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { - if (gpio_get_value(gpionr)) - pint[bank]->invert_set = pintbit; - else - pint[bank]->invert_clear = pintbit; - } +#endif - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { - pint[bank]->edge_set = pintbit; - bfin_set_irq_handler(irq, handle_edge_irq); - } else { - pint[bank]->edge_clear = pintbit; - bfin_set_irq_handler(irq, handle_level_irq); - } +static struct irq_chip bfin_gpio_irqchip = { + .name = "GPIO", + .irq_ack = bfin_gpio_ack_irq, + .irq_mask = bfin_gpio_mask_irq, + .irq_mask_ack = bfin_gpio_mask_ack_irq, + .irq_unmask = bfin_gpio_unmask_irq, + .irq_disable = bfin_gpio_mask_irq, + .irq_enable = bfin_gpio_unmask_irq, + .irq_set_type = bfin_gpio_irq_type, + .irq_startup = bfin_gpio_irq_startup, + .irq_shutdown = bfin_gpio_irq_shutdown, + .irq_set_wake = bfin_gpio_set_wake, +}; - return 0; -} +#endif #ifdef CONFIG_PM -u32 pint_saved_masks[NR_PINT_SYS_IRQS]; -u32 pint_wakeup_masks[NR_PINT_SYS_IRQS]; -int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) -{ - u32 pint_irq; - u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; - u32 bank = PINT_2_BANK(pint_val); - u32 pintbit = PINT_BIT(pint_val); - - switch (bank) { - case 0: - pint_irq = IRQ_PINT0; - break; - case 2: - pint_irq = IRQ_PINT2; - break; - case 3: - pint_irq = IRQ_PINT3; - break; - case 1: - pint_irq = IRQ_PINT1; - break; - default: - return -EINVAL; - } - - bfin_internal_set_wake(pint_irq, state); +#ifdef SEC_GCTL +static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS]; - if (state) - pint_wakeup_masks[bank] |= pintbit; - else - pint_wakeup_masks[bank] &= ~pintbit; - - return 0; -} - -u32 bfin_pm_setup(void) +static int sec_suspend(void) { - u32 val, i; - - for (i = 0; i < NR_PINT_SYS_IRQS; i++) { - val = pint[i]->mask_clear; - pint_saved_masks[i] = val; - if (val ^ pint_wakeup_masks[i]) { - pint[i]->mask_clear = val; - pint[i]->mask_set = pint_wakeup_masks[i]; - } - } + u32 bank; + for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) + save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0)); return 0; } -void bfin_pm_restore(void) +static void sec_resume(void) { - u32 i, val; + u32 bank; - for (i = 0; i < NR_PINT_SYS_IRQS; i++) { - val = pint_saved_masks[i]; - if (val ^ pint_wakeup_masks[i]) { - pint[i]->mask_clear = pint[i]->mask_clear; - pint[i]->mask_set = val; - } - } -} -#endif - -static void bfin_demux_gpio_irq(unsigned int inta_irq, - struct irq_desc *desc) -{ - u32 bank, pint_val; - u32 request, irq; - - switch (inta_irq) { - case IRQ_PINT0: - bank = 0; - break; - case IRQ_PINT2: - bank = 2; - break; - case IRQ_PINT3: - bank = 3; - break; - case IRQ_PINT1: - bank = 1; - break; - default: - return; - } - - pint_val = bank * NR_PINT_BITS; - - request = pint[bank]->request; - - while (request) { - if (request & 1) { - irq = pint2irq_lut[pint_val] + SYS_IRQS; - bfin_handle_irq(irq); - } - pint_val++; - request >>= 1; - } + bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); + udelay(100); + bfin_write_SEC_GCTL(SEC_GCTL_EN); + bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); + for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) + bfin_write_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]); } + +static struct syscore_ops sec_pm_syscore_ops = { + .suspend = sec_suspend, + .resume = sec_resume, +}; #endif -static struct irq_chip bfin_gpio_irqchip = { - .name = "GPIO", - .irq_ack = bfin_gpio_ack_irq, - .irq_mask = bfin_gpio_mask_irq, - .irq_mask_ack = bfin_gpio_mask_ack_irq, - .irq_unmask = bfin_gpio_unmask_irq, - .irq_disable = bfin_gpio_mask_irq, - .irq_enable = bfin_gpio_unmask_irq, - .irq_set_type = bfin_gpio_irq_type, - .irq_startup = bfin_gpio_irq_startup, - .irq_shutdown = bfin_gpio_irq_shutdown, -#ifdef CONFIG_PM - .irq_set_wake = bfin_gpio_set_wake, #endif -}; -void __cpuinit init_exception_vectors(void) +void init_exception_vectors(void) { /* cannot program in software: * evt0 - emulation (jtag) @@ -1121,6 +969,7 @@ void __cpuinit init_exception_vectors(void) CSYNC(); } +#ifndef SEC_GCTL /* * This function should be called during kernel startup to initialize * the BFin IRQ handling routines. @@ -1130,15 +979,15 @@ int __init init_arch_irq(void) { int irq; unsigned long ilat = 0; + /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ -#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \ - || defined(BF538_FAMILY) || defined(CONFIG_BF51x) +#ifdef SIC_IMASK0 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); -# ifdef CONFIG_BF54x +# ifdef SIC_IMASK2 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); # endif -# ifdef CONFIG_SMP +# if defined(CONFIG_SMP) || defined(CONFIG_ICC) bfin_write_SICB_IMASK0(SIC_UNMASK_ALL); bfin_write_SICB_IMASK1(SIC_UNMASK_ALL); # endif @@ -1148,39 +997,19 @@ int __init init_arch_irq(void) local_irq_disable(); -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) - /* Clear EMAC Interrupt Status bits so we can demux it later */ - bfin_write_EMAC_SYSTAT(-1); -#endif - -#ifdef CONFIG_BF54x -# ifdef CONFIG_PINTx_REASSIGN - pint[0]->assign = CONFIG_PINT0_ASSIGN; - pint[1]->assign = CONFIG_PINT1_ASSIGN; - pint[2]->assign = CONFIG_PINT2_ASSIGN; - pint[3]->assign = CONFIG_PINT3_ASSIGN; -# endif - /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ - init_pint_lut(); -#endif - for (irq = 0; irq <= SYS_IRQS; irq++) { if (irq <= IRQ_CORETMR) - set_irq_chip(irq, &bfin_core_irqchip); + irq_set_chip(irq, &bfin_core_irqchip); else - set_irq_chip(irq, &bfin_internal_irqchip); + irq_set_chip(irq, &bfin_internal_irqchip); switch (irq) { -#if defined(CONFIG_BF53x) +#if !BFIN_GPIO_PINT +#if defined(BF537_FAMILY) + case IRQ_PH_INTA_MAC_RX: + case IRQ_PF_INTA_PG_INTA: +#elif defined(BF533_FAMILY) case IRQ_PROG_INTA: -# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) - case IRQ_MAC_RX: -# endif -#elif defined(CONFIG_BF54x) - case IRQ_PINT0: - case IRQ_PINT1: - case IRQ_PINT2: - case IRQ_PINT3: #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) case IRQ_PORTF_INTA: case IRQ_PORTG_INTA: @@ -1189,78 +1018,65 @@ int __init init_arch_irq(void) case IRQ_PROG0_INTA: case IRQ_PROG1_INTA: case IRQ_PROG2_INTA: -#elif defined(CONFIG_BF538) || defined(CONFIG_BF539) +#elif defined(BF538_FAMILY) case IRQ_PORTF_INTA: #endif - set_irq_chained_handler(irq, - bfin_demux_gpio_irq); - break; -#ifdef BF537_GENERIC_ERROR_INT_DEMUX - case IRQ_GENERIC_ERROR: - set_irq_chained_handler(irq, bfin_demux_error_irq); + irq_set_chained_handler(irq, bfin_demux_gpio_irq); break; #endif #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) case IRQ_MAC_ERROR: - set_irq_chained_handler(irq, bfin_demux_mac_status_irq); + irq_set_chained_handler(irq, + bfin_demux_mac_status_irq); break; #endif -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) || defined(CONFIG_ICC) case IRQ_SUPPLE_0: case IRQ_SUPPLE_1: - set_irq_handler(irq, handle_percpu_irq); + irq_set_handler(irq, handle_percpu_irq); break; #endif #ifdef CONFIG_TICKSOURCE_CORETMR case IRQ_CORETMR: # ifdef CONFIG_SMP - set_irq_handler(irq, handle_percpu_irq); - break; + irq_set_handler(irq, handle_percpu_irq); # else - set_irq_handler(irq, handle_simple_irq); - break; + irq_set_handler(irq, handle_simple_irq); # endif + break; #endif #ifdef CONFIG_TICKSOURCE_GPTMR0 case IRQ_TIMER0: - set_irq_handler(irq, handle_simple_irq); + irq_set_handler(irq, handle_simple_irq); break; #endif -#ifdef CONFIG_IPIPE default: - set_irq_handler(irq, handle_level_irq); - break; -#else /* !CONFIG_IPIPE */ - default: - set_irq_handler(irq, handle_simple_irq); +#ifdef CONFIG_IPIPE + irq_set_handler(irq, handle_level_irq); +#else + irq_set_handler(irq, handle_simple_irq); +#endif break; -#endif /* !CONFIG_IPIPE */ } } -#ifdef BF537_GENERIC_ERROR_INT_DEMUX - for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) - set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip, - handle_level_irq); -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) - set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq); -#endif -#endif + init_mach_irq(); -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) +#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) - set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip, + irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip, handle_level_irq); #endif /* if configured as edge, then will be changed to do_edge_IRQ */ +#ifdef CONFIG_GPIO_ADI for (irq = GPIO_IRQ_BASE; irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) - set_irq_chip_and_handler(irq, &bfin_gpio_irqchip, + irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, handle_level_irq); - +#endif bfin_write_IMASK(0); CSYNC(); ilat = bfin_read_ILAT(); @@ -1278,8 +1094,9 @@ int __init init_arch_irq(void) /* Enable interrupts IVG7-15 */ bfin_irq_flags |= IMASK_IVG15 | - IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | - IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; + IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | + IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; + /* This implicitly covers ANOMALY_05000171 * Boot-ROM code modifies SICA_IWRx wakeup registers @@ -1303,60 +1120,146 @@ int __init init_arch_irq(void) #else bfin_write_SIC_IWR(IWR_DISABLE_ALL); #endif - return 0; } #ifdef CONFIG_DO_IRQ_L1 __attribute__((l1_text)) #endif -void do_irq(int vec, struct pt_regs *fp) +static int vec_to_irq(int vec) { - if (vec == EVT_IVTMR_P) { - vec = IRQ_CORETMR; - } else { - struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; - struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; -#if defined(SIC_ISR0) - unsigned long sic_status[3]; - - if (smp_processor_id()) { + struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; + struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; + unsigned long sic_status[3]; + if (likely(vec == EVT_IVTMR_P)) + return IRQ_CORETMR; +#ifdef SIC_ISR + sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); +#else + if (smp_processor_id()) { # ifdef SICB_ISR0 - /* This will be optimized out in UP mode. */ - sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0(); - sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1(); -# endif - } else { - sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); - sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); - } -# ifdef SIC_ISR2 - sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); + /* This will be optimized out in UP mode. */ + sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0(); + sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1(); # endif - for (;; ivg++) { - if (ivg >= ivg_stop) { - atomic_inc(&num_spurious); - return; - } - if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) - break; - } + } else { + sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); + sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); + } +#endif +#ifdef SIC_ISR2 + sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); +#endif + + for (;; ivg++) { + if (ivg >= ivg_stop) + return -1; +#ifdef SIC_ISR + if (sic_status[0] & ivg->isrflag) #else - unsigned long sic_status; + if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) +#endif + return ivg->irqno; + } +} - sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); +#else /* SEC_GCTL */ - for (;; ivg++) { - if (ivg >= ivg_stop) { - atomic_inc(&num_spurious); - return; - } else if (sic_status & ivg->isrflag) - break; - } +/* + * This function should be called during kernel startup to initialize + * the BFin IRQ handling routines. + */ + +int __init init_arch_irq(void) +{ + int irq; + unsigned long ilat = 0; + + bfin_write_SEC_GCTL(SEC_GCTL_RESET); + + local_irq_disable(); + + for (irq = 0; irq <= SYS_IRQS; irq++) { + if (irq <= IRQ_CORETMR) { + irq_set_chip_and_handler(irq, &bfin_core_irqchip, + handle_simple_irq); +#if defined(CONFIG_TICKSOURCE_CORETMR) && defined(CONFIG_SMP) + if (irq == IRQ_CORETMR) + irq_set_handler(irq, handle_percpu_irq); #endif - vec = ivg->irqno; + } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) { + irq_set_chip_and_handler(irq, &bfin_sec_irqchip, + handle_percpu_irq); + } else { + irq_set_chip(irq, &bfin_sec_irqchip); + irq_set_handler(irq, handle_fasteoi_irq); + __irq_set_preflow_handler(irq, bfin_sec_preflow_handler); + } } - asm_do_IRQ(vec, fp); + + bfin_write_IMASK(0); + CSYNC(); + ilat = bfin_read_ILAT(); + CSYNC(); + bfin_write_ILAT(ilat); + CSYNC(); + + printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); + + bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority); + + /* Enable interrupts IVG7-15 */ + bfin_irq_flags |= IMASK_IVG15 | + IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | + IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; + + + bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN); + bfin_sec_enable_sci(BFIN_SYSIRQ(IRQ_WATCH0)); + bfin_sec_enable_ssi(BFIN_SYSIRQ(IRQ_WATCH0)); + bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); + udelay(100); + bfin_write_SEC_GCTL(SEC_GCTL_EN); + bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); + bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); + + init_software_driven_irq(); + +#ifdef CONFIG_PM + register_syscore_ops(&sec_pm_syscore_ops); +#endif + + bfin_fault_irq.handler = bfin_fault_routine; +#ifdef CONFIG_L1_PARITY_CHECK + setup_irq(IRQ_C0_NMI_L1_PARITY_ERR, &bfin_fault_irq); +#endif + setup_irq(IRQ_C0_DBL_FAULT, &bfin_fault_irq); + setup_irq(IRQ_SEC_ERR, &bfin_fault_irq); + + return 0; +} + +#ifdef CONFIG_DO_IRQ_L1 +__attribute__((l1_text)) +#endif +static int vec_to_irq(int vec) +{ + if (likely(vec == EVT_IVTMR_P)) + return IRQ_CORETMR; + + return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID)); +} +#endif /* SEC_GCTL */ + +#ifdef CONFIG_DO_IRQ_L1 +__attribute__((l1_text)) +#endif +void do_irq(int vec, struct pt_regs *fp) +{ + int irq = vec_to_irq(vec); + if (irq == -1) + return; + asm_do_IRQ(irq, fp); } #ifdef CONFIG_IPIPE @@ -1368,6 +1271,10 @@ int __ipipe_get_irq_priority(unsigned irq) if (irq <= IRQ_CORETMR) return irq; +#ifdef SEC_GCTL + if (irq >= BFIN_IRQ(0)) + return IVG11; +#else for (ient = 0; ient < NR_PERI_INTS; ient++) { struct ivgx *ivg = ivg_table + ient; if (ivg->irqno == irq) { @@ -1378,6 +1285,7 @@ int __ipipe_get_irq_priority(unsigned irq) } } } +#endif return IVG15; } @@ -1390,44 +1298,11 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) { struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); struct ipipe_domain *this_domain = __ipipe_current_domain; - struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; - struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; int irq, s = 0; - if (likely(vec == EVT_IVTMR_P)) - irq = IRQ_CORETMR; - else { -#if defined(SIC_ISR0) - unsigned long sic_status[3]; - - sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); - sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); -# ifdef SIC_ISR2 - sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); -# endif - for (;; ivg++) { - if (ivg >= ivg_stop) { - atomic_inc(&num_spurious); - return 0; - } - if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) - break; - } -#else - unsigned long sic_status; - - sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); - - for (;; ivg++) { - if (ivg >= ivg_stop) { - atomic_inc(&num_spurious); - return 0; - } else if (sic_status & ivg->isrflag) - break; - } -#endif - irq = ivg->irqno; - } + irq = vec_to_irq(vec); + if (irq == -1) + return 0; if (irq == IRQ_SYSTMR) { #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0) diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index 3c648a077e7..1387a94bcfd 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c @@ -19,20 +19,33 @@ #include <asm/gpio.h> #include <asm/dma.h> #include <asm/dpmc.h> +#include <asm/pm.h> +#ifdef CONFIG_BF60x +struct bfin_cpu_pm_fns *bfin_cpu_pm; +#endif void bfin_pm_suspend_standby_enter(void) { +#if !BFIN_GPIO_PINT bfin_pm_standby_setup(); +#endif -#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER - sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]); +#ifdef CONFIG_BF60x + bfin_cpu_pm->enter(PM_SUSPEND_STANDBY); #else +# ifdef CONFIG_PM_BFIN_SLEEP_DEEPER + sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]); +# else sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]); +# endif #endif +#if !BFIN_GPIO_PINT bfin_pm_standby_restore(); +#endif +#ifndef CONFIG_BF60x #ifdef SIC_IWR0 bfin_write_SIC_IWR0(IWR_DISABLE_ALL); # ifdef SIC_IWR1 @@ -52,6 +65,8 @@ void bfin_pm_suspend_standby_enter(void) #else bfin_write_SIC_IWR(IWR_DISABLE_ALL); #endif + +#endif } int bf53x_suspend_l1_mem(unsigned char *memptr) @@ -83,10 +98,13 @@ int bf53x_resume_l1_mem(unsigned char *memptr) } #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) +# ifdef CONFIG_BF60x +__attribute__((l1_text)) +# endif static void flushinv_all_dcache(void) { - u32 way, bank, subbank, set; - u32 status, addr; + register u32 way, bank, subbank, set; + register u32 status, addr; u32 dmem_ctl = bfin_read_DMEM_CONTROL(); for (bank = 0; bank < 2; ++bank) { @@ -110,6 +128,7 @@ static void flushinv_all_dcache(void) if ((status & 0x3) != 0x3) continue; + /* construct the address using the tag */ addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5); @@ -122,17 +141,21 @@ static void flushinv_all_dcache(void) int bfin_pm_suspend_mem_enter(void) { - int wakeup, ret; + int ret; +#ifndef CONFIG_BF60x + int wakeup; +#endif unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH, - GFP_KERNEL); + GFP_ATOMIC); if (memptr == NULL) { panic("bf53x_suspend_l1_mem malloc failed"); return -ENOMEM; } +#ifndef CONFIG_BF60x wakeup = bfin_read_VR_CTL() & ~FREQ; wakeup |= SCKELOW; @@ -142,6 +165,7 @@ int bfin_pm_suspend_mem_enter(void) #ifdef CONFIG_PM_BFIN_WAKE_GP wakeup |= GPWE; #endif +#endif ret = blackfin_dma_suspend(); @@ -150,7 +174,9 @@ int bfin_pm_suspend_mem_enter(void) return ret; } +#ifdef CONFIG_GPIO_ADI bfin_gpio_pm_hibernate_suspend(); +#endif #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) flushinv_all_dcache(); @@ -159,14 +185,20 @@ int bfin_pm_suspend_mem_enter(void) _disable_icplb(); bf53x_suspend_l1_mem(memptr); +#ifndef CONFIG_BF60x do_hibernate(wakeup | vr_wakeup); /* See you later! */ +#else + bfin_cpu_pm->enter(PM_SUSPEND_MEM); +#endif bf53x_resume_l1_mem(memptr); _enable_icplb(); _enable_dcplb(); +#ifdef CONFIG_GPIO_ADI bfin_gpio_pm_hibernate_restore(); +#endif blackfin_dma_resume(); kfree(memptr); @@ -223,9 +255,39 @@ static int bfin_pm_enter(suspend_state_t state) return 0; } +#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH +void bfin_pm_end(void) +{ + u32 cycle, cycle2; + u64 usec64; + u32 usec; + + __asm__ __volatile__ ( + "1: %0 = CYCLES2\n" + "%1 = CYCLES\n" + "%2 = CYCLES2\n" + "CC = %2 == %0\n" + "if ! CC jump 1b\n" + : "=d,a" (cycle2), "=d,a" (cycle), "=d,a" (usec) : : "CC" + ); + + usec64 = ((u64)cycle2 << 32) + cycle; + do_div(usec64, get_cclk() / USEC_PER_SEC); + usec = usec64; + if (usec == 0) + usec = 1; + + pr_info("PM: resume of kernel completes after %ld msec %03ld usec\n", + usec / USEC_PER_MSEC, usec % USEC_PER_MSEC); +} +#endif + static const struct platform_suspend_ops bfin_pm_ops = { .enter = bfin_pm_enter, .valid = bfin_pm_valid, +#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH + .end = bfin_pm_end, +#endif }; static int __init bfin_pm_init(void) diff --git a/arch/blackfin/mach-common/scb-init.c b/arch/blackfin/mach-common/scb-init.c new file mode 100644 index 00000000000..8923398db66 --- /dev/null +++ b/arch/blackfin/mach-common/scb-init.c @@ -0,0 +1,52 @@ +/* + * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority + * + * Copyright 2012 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <linux/errno.h> +#include <linux/kernel.h> +#include <asm/scb.h> + +__attribute__((l1_text)) +inline void scb_mi_write(unsigned long scb_mi_arbw, unsigned int slots, + unsigned char *scb_mi_prio) +{ + unsigned int i; + + for (i = 0; i < slots; ++i) + bfin_write32(scb_mi_arbw, (i << SCB_SLOT_OFFSET) | scb_mi_prio[i]); +} + +__attribute__((l1_text)) +inline void scb_mi_read(unsigned long scb_mi_arbw, unsigned int slots, + unsigned char *scb_mi_prio) +{ + unsigned int i; + + for (i = 0; i < slots; ++i) { + bfin_write32(scb_mi_arbw, (0xFF << SCB_SLOT_OFFSET) | i); + scb_mi_prio[i] = bfin_read32(scb_mi_arbw); + } +} + +__attribute__((l1_text)) +void init_scb(void) +{ + unsigned int i, j; + unsigned char scb_tmp_prio[32]; + + pr_info("Init System Crossbar\n"); + for (i = 0; scb_data[i].scb_mi_arbr > 0; ++i) { + + scb_mi_write(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_data[i].scb_mi_prio); + + pr_debug("scb priority at 0x%lx:\n", scb_data[i].scb_mi_arbr); + scb_mi_read(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_tmp_prio); + for (j = 0; j < scb_data[i].scb_mi_slots; ++j) + pr_debug("slot %d = %d\n", j, scb_tmp_prio[j]); + } + +} diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c index 6e17a265c4d..ba6c30d8534 100644 --- a/arch/blackfin/mach-common/smp.c +++ b/arch/blackfin/mach-common/smp.c @@ -14,6 +14,7 @@ #include <linux/sched.h> #include <linux/interrupt.h> #include <linux/cache.h> +#include <linux/clockchips.h> #include <linux/profile.h> #include <linux/errno.h> #include <linux/mm.h> @@ -23,8 +24,9 @@ #include <linux/seq_file.h> #include <linux/irq.h> #include <linux/slab.h> -#include <asm/atomic.h> +#include <linux/atomic.h> #include <asm/cacheflush.h> +#include <asm/irq_handler.h> #include <asm/mmu_context.h> #include <asm/pgtable.h> #include <asm/pgalloc.h> @@ -44,13 +46,15 @@ struct corelock_slot corelock __attribute__ ((__section__(".l2.bss"))); unsigned long blackfin_iflush_l1_entry[NR_CPUS]; #endif -void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb, - *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb, - *init_saved_dcplb_fault_addr_coreb; +struct blackfin_initial_pda initial_pda_coreb; -#define BFIN_IPI_RESCHEDULE 0 -#define BFIN_IPI_CALL_FUNC 1 -#define BFIN_IPI_CPU_STOP 2 +enum ipi_message_type { + BFIN_IPI_NONE, + BFIN_IPI_TIMER, + BFIN_IPI_RESCHEDULE, + BFIN_IPI_CALL_FUNC, + BFIN_IPI_CPU_STOP, +}; struct blackfin_flush_data { unsigned long start; @@ -59,35 +63,20 @@ struct blackfin_flush_data { void *secondary_stack; - -struct smp_call_struct { - void (*func)(void *info); - void *info; - int wait; - cpumask_t *waitmask; -}; - static struct blackfin_flush_data smp_flush_data; static DEFINE_SPINLOCK(stop_lock); -struct ipi_message { - unsigned long type; - struct smp_call_struct call_struct; -}; - /* A magic number - stress test shows this is safe for common cases */ #define BFIN_IPI_MSGQ_LEN 5 /* Simple FIFO buffer, overflow leads to panic */ -struct ipi_message_queue { - spinlock_t lock; - unsigned long count; - unsigned long head; /* head of the queue */ - struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN]; +struct ipi_data { + atomic_t count; + atomic_t bits; }; -static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue); +static DEFINE_PER_CPU(struct ipi_data, bfin_ipi); static void ipi_cpu_stop(unsigned int cpu) { @@ -96,7 +85,7 @@ static void ipi_cpu_stop(unsigned int cpu) dump_stack(); spin_unlock(&stop_lock); - cpu_clear(cpu, cpu_online_map); + set_cpu_online(cpu, false); local_irq_disable(); @@ -109,32 +98,23 @@ static void ipi_flush_icache(void *info) struct blackfin_flush_data *fdata = info; /* Invalidate the memory holding the bounds of the flushed region. */ - invalidate_dcache_range((unsigned long)fdata, - (unsigned long)fdata + sizeof(*fdata)); - - flush_icache_range(fdata->start, fdata->end); -} + blackfin_dcache_invalidate_range((unsigned long)fdata, + (unsigned long)fdata + sizeof(*fdata)); + + /* Make sure all write buffers in the data side of the core + * are flushed before trying to invalidate the icache. This + * needs to be after the data flush and before the icache + * flush so that the SSYNC does the right thing in preventing + * the instruction prefetcher from hitting things in cached + * memory at the wrong time -- it runs much further ahead than + * the pipeline. + */ + SSYNC(); -static void ipi_call_function(unsigned int cpu, struct ipi_message *msg) -{ - int wait; - void (*func)(void *info); - void *info; - func = msg->call_struct.func; - info = msg->call_struct.info; - wait = msg->call_struct.wait; - func(info); - if (wait) { -#ifdef __ARCH_SYNC_CORE_DCACHE - /* - * 'wait' usually means synchronization between CPUs. - * Invalidate D cache in case shared data was changed - * by func() to ensure cache coherence. - */ - resync_core_dcache(); -#endif - cpu_clear(cpu, *msg->call_struct.waitmask); - } + /* ipi_flaush_icache is invoked by generic flush_icache_range, + * so call blackfin arch icache flush directly here. + */ + blackfin_icache_flush_range(fdata->start, fdata->end); } /* Use IRQ_SUPPLE_0 to request reschedule. @@ -148,173 +128,127 @@ static irqreturn_t ipi_handler_int0(int irq, void *dev_instance) return IRQ_HANDLED; } +DECLARE_PER_CPU(struct clock_event_device, coretmr_events); +void ipi_timer(void) +{ + int cpu = smp_processor_id(); + struct clock_event_device *evt = &per_cpu(coretmr_events, cpu); + evt->event_handler(evt); +} + static irqreturn_t ipi_handler_int1(int irq, void *dev_instance) { - struct ipi_message *msg; - struct ipi_message_queue *msg_queue; + struct ipi_data *bfin_ipi_data; unsigned int cpu = smp_processor_id(); - unsigned long flags; + unsigned long pending; + unsigned long msg; platform_clear_ipi(cpu, IRQ_SUPPLE_1); - msg_queue = &__get_cpu_var(ipi_msg_queue); - - spin_lock_irqsave(&msg_queue->lock, flags); - - while (msg_queue->count) { - msg = &msg_queue->ipi_message[msg_queue->head]; - switch (msg->type) { - case BFIN_IPI_CALL_FUNC: - spin_unlock_irqrestore(&msg_queue->lock, flags); - ipi_call_function(cpu, msg); - spin_lock_irqsave(&msg_queue->lock, flags); - break; - case BFIN_IPI_CPU_STOP: - spin_unlock_irqrestore(&msg_queue->lock, flags); - ipi_cpu_stop(cpu); - spin_lock_irqsave(&msg_queue->lock, flags); - break; - default: - printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n", - cpu, msg->type); - break; - } - msg_queue->head++; - msg_queue->head %= BFIN_IPI_MSGQ_LEN; - msg_queue->count--; + smp_rmb(); + bfin_ipi_data = &__get_cpu_var(bfin_ipi); + while ((pending = atomic_xchg(&bfin_ipi_data->bits, 0)) != 0) { + msg = 0; + do { + msg = find_next_bit(&pending, BITS_PER_LONG, msg + 1); + switch (msg) { + case BFIN_IPI_TIMER: + ipi_timer(); + break; + case BFIN_IPI_RESCHEDULE: + scheduler_ipi(); + break; + case BFIN_IPI_CALL_FUNC: + generic_smp_call_function_interrupt(); + break; + case BFIN_IPI_CPU_STOP: + ipi_cpu_stop(cpu); + break; + default: + goto out; + } + atomic_dec(&bfin_ipi_data->count); + } while (msg < BITS_PER_LONG); + } - spin_unlock_irqrestore(&msg_queue->lock, flags); +out: return IRQ_HANDLED; } -static void ipi_queue_init(void) +static void bfin_ipi_init(void) { unsigned int cpu; - struct ipi_message_queue *msg_queue; + struct ipi_data *bfin_ipi_data; for_each_possible_cpu(cpu) { - msg_queue = &per_cpu(ipi_msg_queue, cpu); - spin_lock_init(&msg_queue->lock); - msg_queue->count = 0; - msg_queue->head = 0; + bfin_ipi_data = &per_cpu(bfin_ipi, cpu); + atomic_set(&bfin_ipi_data->bits, 0); + atomic_set(&bfin_ipi_data->count, 0); } } -static inline void smp_send_message(cpumask_t callmap, unsigned long type, - void (*func) (void *info), void *info, int wait) +void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg) { unsigned int cpu; - struct ipi_message_queue *msg_queue; - struct ipi_message *msg; - unsigned long flags, next_msg; - cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */ - - for_each_cpu_mask(cpu, callmap) { - msg_queue = &per_cpu(ipi_msg_queue, cpu); - spin_lock_irqsave(&msg_queue->lock, flags); - if (msg_queue->count < BFIN_IPI_MSGQ_LEN) { - next_msg = (msg_queue->head + msg_queue->count) - % BFIN_IPI_MSGQ_LEN; - msg = &msg_queue->ipi_message[next_msg]; - msg->type = type; - if (type == BFIN_IPI_CALL_FUNC) { - msg->call_struct.func = func; - msg->call_struct.info = info; - msg->call_struct.wait = wait; - msg->call_struct.waitmask = &waitmask; - } - msg_queue->count++; - } else - panic("IPI message queue overflow\n"); - spin_unlock_irqrestore(&msg_queue->lock, flags); - platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1); - } + struct ipi_data *bfin_ipi_data; + unsigned long flags; - if (wait) { - while (!cpus_empty(waitmask)) - blackfin_dcache_invalidate_range( - (unsigned long)(&waitmask), - (unsigned long)(&waitmask)); -#ifdef __ARCH_SYNC_CORE_DCACHE - /* - * Invalidate D cache in case shared data was changed by - * other processors to ensure cache coherence. - */ - resync_core_dcache(); -#endif + local_irq_save(flags); + for_each_cpu(cpu, cpumask) { + bfin_ipi_data = &per_cpu(bfin_ipi, cpu); + atomic_set_mask((1 << msg), &bfin_ipi_data->bits); + atomic_inc(&bfin_ipi_data->count); } + local_irq_restore(flags); + smp_wmb(); + for_each_cpu(cpu, cpumask) + platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1); } -int smp_call_function(void (*func)(void *info), void *info, int wait) +void arch_send_call_function_single_ipi(int cpu) { - cpumask_t callmap; - - preempt_disable(); - callmap = cpu_online_map; - cpu_clear(smp_processor_id(), callmap); - if (!cpus_empty(callmap)) - smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait); - - preempt_enable(); - - return 0; + send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC); } -EXPORT_SYMBOL_GPL(smp_call_function); -int smp_call_function_single(int cpuid, void (*func) (void *info), void *info, - int wait) +void arch_send_call_function_ipi_mask(const struct cpumask *mask) { - unsigned int cpu = cpuid; - cpumask_t callmap; - - if (cpu_is_offline(cpu)) - return 0; - cpus_clear(callmap); - cpu_set(cpu, callmap); - - smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait); - - return 0; + send_ipi(mask, BFIN_IPI_CALL_FUNC); } -EXPORT_SYMBOL_GPL(smp_call_function_single); void smp_send_reschedule(int cpu) { - /* simply trigger an ipi */ - if (cpu_is_offline(cpu)) - return; - platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); + send_ipi(cpumask_of(cpu), BFIN_IPI_RESCHEDULE); return; } +void smp_send_msg(const struct cpumask *mask, unsigned long type) +{ + send_ipi(mask, type); +} + +void smp_timer_broadcast(const struct cpumask *mask) +{ + smp_send_msg(mask, BFIN_IPI_TIMER); +} + void smp_send_stop(void) { cpumask_t callmap; preempt_disable(); - callmap = cpu_online_map; - cpu_clear(smp_processor_id(), callmap); - if (!cpus_empty(callmap)) - smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0); + cpumask_copy(&callmap, cpu_online_mask); + cpumask_clear_cpu(smp_processor_id(), &callmap); + if (!cpumask_empty(&callmap)) + send_ipi(&callmap, BFIN_IPI_CPU_STOP); preempt_enable(); return; } -int __cpuinit __cpu_up(unsigned int cpu) +int __cpu_up(unsigned int cpu, struct task_struct *idle) { int ret; - static struct task_struct *idle; - - if (idle) - free_task(idle); - - idle = fork_idle(cpu); - if (IS_ERR(idle)) { - printk(KERN_ERR "CPU%u: fork() failed\n", cpu); - return PTR_ERR(idle); - } secondary_stack = task_stack_page(idle) + THREAD_SIZE; @@ -325,7 +259,7 @@ int __cpuinit __cpu_up(unsigned int cpu) return ret; } -static void __cpuinit setup_secondary(unsigned int cpu) +static void setup_secondary(unsigned int cpu) { unsigned long ilat; @@ -343,7 +277,7 @@ static void __cpuinit setup_secondary(unsigned int cpu) IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; } -void __cpuinit secondary_start_kernel(void) +void secondary_start_kernel(void) { unsigned int cpu = smp_processor_id(); struct mm_struct *mm = &init_mm; @@ -351,13 +285,16 @@ void __cpuinit secondary_start_kernel(void) if (_bfin_swrst & SWRST_DBL_FAULT_B) { printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n"); #ifdef CONFIG_DEBUG_DOUBLEFAULT - printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n", - (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb); - printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb); - printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb); + printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n", + initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE, + initial_pda_coreb.retx_doublefault); + printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", + initial_pda_coreb.dcplb_doublefault_addr); + printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", + initial_pda_coreb.icplb_doublefault_addr); #endif printk(KERN_NOTICE " The instruction at %pF caused a double exception\n", - init_retx_coreb); + initial_pda_coreb.retx); } /* @@ -379,7 +316,6 @@ void __cpuinit secondary_start_kernel(void) setup_secondary(cpu); platform_secondary_init(cpu); - /* setup local core timer */ bfin_local_timer_setup(); @@ -387,6 +323,7 @@ void __cpuinit secondary_start_kernel(void) bfin_setup_caches(cpu); + notify_cpu_starting(cpu); /* * Calibrate loops per jiffy value. * IRQs need to be enabled here - D-cache can be invalidated @@ -394,7 +331,9 @@ void __cpuinit secondary_start_kernel(void) */ calibrate_delay(); - cpu_idle(); + /* We are done with local CPU inits, unblock the boot CPU. */ + set_cpu_online(cpu, true); + cpu_startup_entry(CPUHP_ONLINE); } void __init smp_prepare_boot_cpu(void) @@ -404,7 +343,7 @@ void __init smp_prepare_boot_cpu(void) void __init smp_prepare_cpus(unsigned int max_cpus) { platform_prepare_cpus(max_cpus); - ipi_queue_init(); + bfin_ipi_init(); platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0); platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1); } @@ -429,8 +368,10 @@ void smp_icache_flush_range_others(unsigned long start, unsigned long end) smp_flush_data.start = start; smp_flush_data.end = end; - if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0)) + preempt_disable(); + if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1)) printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n"); + preempt_enable(); } EXPORT_SYMBOL_GPL(smp_icache_flush_range_others); @@ -461,7 +402,7 @@ EXPORT_SYMBOL(resync_core_dcache); #endif #ifdef CONFIG_HOTPLUG_CPU -int __cpuexit __cpu_disable(void) +int __cpu_disable(void) { unsigned int cpu = smp_processor_id(); @@ -474,7 +415,7 @@ int __cpuexit __cpu_disable(void) static DECLARE_COMPLETION(cpu_killed); -int __cpuexit __cpu_die(unsigned int cpu) +int __cpu_die(unsigned int cpu) { return wait_for_completion_timeout(&cpu_killed, 5000); } |