diff options
Diffstat (limited to 'arch/blackfin/mach-bf561/ints-priority.c')
| -rw-r--r-- | arch/blackfin/mach-bf561/ints-priority.c | 45 |
1 files changed, 12 insertions, 33 deletions
diff --git a/arch/blackfin/mach-bf561/ints-priority.c b/arch/blackfin/mach-bf561/ints-priority.c index 09b541b0f7c..7ee9262fe13 100644 --- a/arch/blackfin/mach-bf561/ints-priority.c +++ b/arch/blackfin/mach-bf561/ints-priority.c @@ -1,40 +1,19 @@ /* - * File: arch/blackfin/mach-bf561/ints-priority.c - * Based on: arch/blackfin/mach-bf537/ints-priority.c - * Author: Michael Hennerich + * Set up the interrupt priorities * - * Created: - * Description: Set up the interrupt priorities + * Copyright 2005-2009 Analog Devices Inc. * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Licensed under the GPL-2 or later. */ #include <linux/module.h> #include <linux/irq.h> #include <asm/blackfin.h> -void program_IAR(void) +void __init program_IAR(void) { /* Program the IAR0 Register with the configured priority */ - bfin_write_SICA_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | + bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) | ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) | ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) | @@ -43,7 +22,7 @@ void program_IAR(void) ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) | ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS)); - bfin_write_SICA_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) | + bfin_write_SIC_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) | ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) | ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) | ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) | @@ -52,7 +31,7 @@ void program_IAR(void) ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) | ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS)); - bfin_write_SICA_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) | + bfin_write_SIC_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) | ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) | ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) | ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) | @@ -61,7 +40,7 @@ void program_IAR(void) ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) | ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS)); - bfin_write_SICA_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) | + bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) | ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) | ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) | ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) | @@ -70,7 +49,7 @@ void program_IAR(void) ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) | ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS)); - bfin_write_SICA_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) | + bfin_write_SIC_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) | ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) | ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) | ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | @@ -79,7 +58,7 @@ void program_IAR(void) ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS)); - bfin_write_SICA_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | + bfin_write_SIC_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) | ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) | @@ -88,7 +67,7 @@ void program_IAR(void) ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) | ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS)); - bfin_write_SICA_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) | + bfin_write_SIC_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) | ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) | ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) | ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) | @@ -97,7 +76,7 @@ void program_IAR(void) ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) | ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS)); - bfin_write_SICA_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) | + bfin_write_SIC_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) | ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) | ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) | ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) | |