diff options
Diffstat (limited to 'arch/blackfin/mach-bf561/include')
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/anomaly.h | 268 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/bf561.h | 27 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/bfin_serial.h | 14 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h | 164 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/blackfin.h | 86 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/cdefBF561.h | 626 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/defBF561.h | 641 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/gpio.h | 107 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/irq.h | 535 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/mem_map.h | 99 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/pll.h | 56 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/portmux.h | 9 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/smp.h | 18 |
13 files changed, 959 insertions, 1691 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index d0b0b350644..038249c1d0d 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h @@ -1,13 +1,16 @@ /* - * File: include/asm-blackfin/mach-bf561/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. + * Copyright 2004-2011 Analog Devices Inc. + * Licensed under the Clear BSD license. */ -/* This file shoule be up to date with: - * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List +/* This file should be up to date with: + * - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -18,115 +21,63 @@ # error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 #endif -/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) -/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */ -#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) -/* Testset instructions restricted to 32-bit aligned memory locations */ +/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */ #define ANOMALY_05000120 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Erroneous exception when enabling cache */ -#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) -/* Signbits instruction not functional under certain conditions */ +/* SIGNBITS Instruction Not Functional under Certain Conditions */ #define ANOMALY_05000127 (1) -/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ -#define ANOMALY_05000134 (__SILICON_REVISION__ < 3) -/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */ -#define ANOMALY_05000135 (__SILICON_REVISION__ < 3) -/* Stall in multi-unit DMA operations */ -#define ANOMALY_05000136 (__SILICON_REVISION__ < 3) -/* Allowing the SPORT RX FIFO to fill will cause an overflow */ -#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ -#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) -/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ -#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) -/* DMA and TESTSET conflict when both are accessing external memory */ -#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) -/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ -#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) -/* MDMA may lose the first few words of a descriptor chain */ -#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) -/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ -#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) -/* IMDMA S1/D1 channel may stall */ +/* IMDMA S1/D1 Channel May Stall */ #define ANOMALY_05000149 (1) -/* DMA engine may lose data due to incorrect handshaking */ -#define ANOMALY_05000150 (__SILICON_REVISION__ < 3) -/* DMA stalls when all three controllers read data from the same source */ -#define ANOMALY_05000151 (__SILICON_REVISION__ < 3) -/* Execution stall when executing in L2 and doing external accesses */ -#define ANOMALY_05000152 (__SILICON_REVISION__ < 3) -/* Frame Delay in SPORT Multichannel Mode */ -#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) -/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ -#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ #define ANOMALY_05000156 (__SILICON_REVISION__ < 4) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ -#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) -/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ -#define ANOMALY_05000159 (__SILICON_REVISION__ < 3) -/* A read from external memory may return a wrong value with data cache enabled */ -#define ANOMALY_05000160 (__SILICON_REVISION__ < 3) -/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */ -#define ANOMALY_05000161 (__SILICON_REVISION__ < 3) -/* DMEM_CONTROL<12> is not set on Reset */ -#define ANOMALY_05000162 (__SILICON_REVISION__ < 3) -/* SPORT transmit data is not gated by external frame sync in certain conditions */ -#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) -/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ +/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) -/* Turning Serial Ports on with External Frame Syncs */ +/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ #define ANOMALY_05000167 (1) -/* SDRAM auto-refresh and subsequent Power Ups */ +/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ #define ANOMALY_05000168 (__SILICON_REVISION__ < 5) -/* DATA CPLB page miss can result in lost write-through cache data writes */ +/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ #define ANOMALY_05000169 (__SILICON_REVISION__ < 5) -/* Boot-ROM code modifies SICA_IWRx wakeup registers */ +/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */ #define ANOMALY_05000171 (__SILICON_REVISION__ < 5) -/* DSPID register values incorrect */ -#define ANOMALY_05000172 (__SILICON_REVISION__ < 3) -/* DMA vs Core accesses to external memory */ -#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) /* Cache Fill Buffer Data lost */ #define ANOMALY_05000174 (__SILICON_REVISION__ < 5) /* Overlapping Sequencer and Memory Stalls */ #define ANOMALY_05000175 (__SILICON_REVISION__ < 5) -/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ +/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ #define ANOMALY_05000176 (__SILICON_REVISION__ < 5) /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ #define ANOMALY_05000179 (__SILICON_REVISION__ < 5) /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ #define ANOMALY_05000180 (1) -/* Disabling the PPI resets the PPI configuration registers */ +/* Disabling the PPI Resets the PPI Configuration Registers */ #define ANOMALY_05000181 (__SILICON_REVISION__ < 5) -/* IMDMA does not operate to full speed for 600MHz and higher devices */ +/* Internal Memory DMA Does Not Operate at Full Speed */ #define ANOMALY_05000182 (1) -/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */ +/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ #define ANOMALY_05000184 (__SILICON_REVISION__ < 5) -/* PPI TX Mode with 2 External Frame Syncs */ +/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ #define ANOMALY_05000185 (__SILICON_REVISION__ < 5) -/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */ +/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */ #define ANOMALY_05000186 (__SILICON_REVISION__ < 5) /* IMDMA Corrupted Data after a Halt */ #define ANOMALY_05000187 (1) /* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */ #define ANOMALY_05000188 (__SILICON_REVISION__ < 5) -/* False Protection Exceptions */ +/* False Protection Exceptions when Speculative Fetch Is Cancelled */ #define ANOMALY_05000189 (__SILICON_REVISION__ < 5) -/* PPI not functional at core voltage < 1Volt */ +/* PPI Not Functional at Core Voltage < 1Volt */ #define ANOMALY_05000190 (1) -/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ -#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ #define ANOMALY_05000193 (__SILICON_REVISION__ < 5) /* Restarting SPORT in Specific Modes May Cause Data Corruption */ #define ANOMALY_05000194 (__SILICON_REVISION__ < 5) -/* Failing MMR Accesses When Stalled by Preceding Memory Read */ +/* Failing MMR Accesses when Preceding Memory Read Stalls */ #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) /* Current DMA Address Shows Wrong Value During Carry Fix */ #define ANOMALY_05000199 (__SILICON_REVISION__ < 5) @@ -134,9 +85,9 @@ #define ANOMALY_05000200 (__SILICON_REVISION__ < 5) /* Possible Infinite Stall with Specific Dual-DAG Situation */ #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) -/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ +/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ #define ANOMALY_05000204 (__SILICON_REVISION__ < 5) -/* Specific sequence that can cause DMA error or DMA stopping */ +/* Specific Sequence that Can Cause DMA Error or DMA Stopping */ #define ANOMALY_05000205 (__SILICON_REVISION__ < 5) /* Recovery from "Brown-Out" Condition */ #define ANOMALY_05000207 (__SILICON_REVISION__ < 5) @@ -148,8 +99,8 @@ #define ANOMALY_05000215 (__SILICON_REVISION__ < 5) /* NMI Event at Boot Time Results in Unpredictable State */ #define ANOMALY_05000219 (__SILICON_REVISION__ < 5) -/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */ -#define ANOMALY_05000220 (__SILICON_REVISION__ < 5) +/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */ +#define ANOMALY_05000220 (__SILICON_REVISION__ < 4) /* Incorrect Pulse-Width of UART Start Bit */ #define ANOMALY_05000225 (__SILICON_REVISION__ < 5) /* Scratchpad Memory Bank Reads May Return Incorrect Data */ @@ -158,15 +109,15 @@ #define ANOMALY_05000230 (__SILICON_REVISION__ < 5) /* UART STB Bit Incorrectly Affects Receiver Setting */ #define ANOMALY_05000231 (__SILICON_REVISION__ < 5) -/* SPORT data transmit lines are incorrectly driven in multichannel mode */ +/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */ #define ANOMALY_05000232 (__SILICON_REVISION__ < 5) /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) -/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ +/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (__SILICON_REVISION__ < 5) -/* TESTSET operation forces stall on the other core */ +/* TESTSET Operation Forces Stall on the Other Core */ #define ANOMALY_05000248 (__SILICON_REVISION__ < 5) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5) @@ -177,7 +128,11 @@ /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ #define ANOMALY_05000254 (__SILICON_REVISION__ > 3) /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ -#define ANOMALY_05000257 (__SILICON_REVISION__ < 5) +/* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception + * without handling anomaly 05000257 properly on bf561 v0.5. This work around may change + * after the behavior and the root cause are confirmed with hardware team. + */ +#define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP)) /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ #define ANOMALY_05000258 (__SILICON_REVISION__ < 5) /* ICPLB_STATUS MMR Register May Be Corrupted */ @@ -192,9 +147,9 @@ #define ANOMALY_05000264 (__SILICON_REVISION__ < 5) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (__SILICON_REVISION__ < 5) -/* IMDMA destination IRQ status must be read prior to using IMDMA */ +/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */ #define ANOMALY_05000266 (__SILICON_REVISION__ > 3) -/* IMDMA may corrupt data under certain conditions */ +/* IMDMA May Corrupt Data under Certain Conditions */ #define ANOMALY_05000267 (1) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ #define ANOMALY_05000269 (1) @@ -202,27 +157,31 @@ #define ANOMALY_05000270 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* Data cache write back to external synchronous memory may be lost */ +/* Data Cache Write Back to External Synchronous Memory May Be Lost */ #define ANOMALY_05000274 (1) /* PPI Timing and Sampling Information Updates */ #define ANOMALY_05000275 (__SILICON_REVISION__ > 2) /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ #define ANOMALY_05000276 (__SILICON_REVISION__ < 5) -/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */ -#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) +/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ +#define ANOMALY_05000277 (__SILICON_REVISION__ < 5) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) -/* False Hardware Error Exception When ISR Context Is Not Restored */ -#define ANOMALY_05000281 (__SILICON_REVISION__ < 5) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* False Hardware Error when ISR Context Is Not Restored */ +/* Temporarily walk around for bug 5423 till this issue is confirmed by + * official anomaly document. It looks 05000281 still exists on bf561 + * v0.5. + */ +#define ANOMALY_05000281 (__SILICON_REVISION__ <= 5) +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (1) -/* A read will receive incorrect data under certain conditions */ +/* Reads Will Receive Incorrect Data under Certain Conditions */ #define ANOMALY_05000287 (__SILICON_REVISION__ < 5) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 5) /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ #define ANOMALY_05000301 (1) -/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ +/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ #define ANOMALY_05000302 (1) /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) @@ -230,25 +189,25 @@ #define ANOMALY_05000307 (__SILICON_REVISION__ < 5) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (1) -/* PPI Is Level-Sensitive on First Transfer */ +/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (1) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (1) -/* PF2 Output Remains Asserted After SPI Master Boot */ +/* PF2 Output Remains Asserted after SPI Master Boot */ #define ANOMALY_05000320 (__SILICON_REVISION__ > 3) -/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */ +/* Erroneous GPIO Flag Pin Operations under Specific Sequences */ #define ANOMALY_05000323 (1) -/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */ +/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */ #define ANOMALY_05000326 (__SILICON_REVISION__ > 3) -/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */ +/* 24-Bit SPI Boot Mode Is Not Functional */ #define ANOMALY_05000331 (__SILICON_REVISION__ < 5) -/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */ +/* Slave SPI Boot Mode Is Not Functional */ #define ANOMALY_05000332 (__SILICON_REVISION__ < 5) -/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ +/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */ #define ANOMALY_05000333 (__SILICON_REVISION__ < 5) -/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */ +/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000339 (__SILICON_REVISION__ < 5) /* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */ #define ANOMALY_05000343 (__SILICON_REVISION__ < 5) @@ -276,18 +235,119 @@ #define ANOMALY_05000428 (__SILICON_REVISION__ > 3) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) +/* SCKELOW Feature Is Not Functional */ +#define ANOMALY_05000458 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ +#define ANOMALY_05000462 (1) +/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ +#define ANOMALY_05000471 (1) +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ +#define ANOMALY_05000473 (1) +/* Possible Lockup Condition when Modifying PLL from External Memory */ +#define ANOMALY_05000475 (1) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ +#define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) + +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are + * here to show running on older silicon just isn't feasible. + */ + +/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ +#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) +/* Erroneous Exception when Enabling Cache */ +#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) +/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ +#define ANOMALY_05000134 (__SILICON_REVISION__ < 3) +/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */ +#define ANOMALY_05000135 (__SILICON_REVISION__ < 3) +/* Stall in multi-unit DMA operations */ +#define ANOMALY_05000136 (__SILICON_REVISION__ < 3) +/* Allowing the SPORT RX FIFO to fill will cause an overflow */ +#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) +/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ +#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) +/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ +#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) +/* DMA and TESTSET conflict when both are accessing external memory */ +#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) +/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ +#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) +/* MDMA may lose the first few words of a descriptor chain */ +#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) +/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ +#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) +/* DMA engine may lose data due to incorrect handshaking */ +#define ANOMALY_05000150 (__SILICON_REVISION__ < 3) +/* DMA stalls when all three controllers read data from the same source */ +#define ANOMALY_05000151 (__SILICON_REVISION__ < 3) +/* Execution stall when executing in L2 and doing external accesses */ +#define ANOMALY_05000152 (__SILICON_REVISION__ < 3) +/* Frame Delay in SPORT Multichannel Mode */ +#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) +/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ +#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ +#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) +/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ +#define ANOMALY_05000159 (__SILICON_REVISION__ < 3) +/* A read from external memory may return a wrong value with data cache enabled */ +#define ANOMALY_05000160 (__SILICON_REVISION__ < 3) +/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */ +#define ANOMALY_05000161 (__SILICON_REVISION__ < 3) +/* DMEM_CONTROL<12> is not set on Reset */ +#define ANOMALY_05000162 (__SILICON_REVISION__ < 3) +/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ +#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) +/* DSPID register values incorrect */ +#define ANOMALY_05000172 (__SILICON_REVISION__ < 3) +/* DMA vs Core accesses to external memory */ +#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) +/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ +#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) +/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ +#define ANOMALY_05000402 (__SILICON_REVISION__ == 4) /* Anomalies that don't exist on this proc */ +#define ANOMALY_05000119 (0) #define ANOMALY_05000158 (0) #define ANOMALY_05000183 (0) +#define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000353 (1) +#define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000386 (1) +#define ANOMALY_05000389 (0) +#define ANOMALY_05000400 (0) +#define ANOMALY_05000430 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000435 (0) +#define ANOMALY_05000440 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) +#define ANOMALY_05000456 (0) +#define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) +#define ANOMALY_05000474 (0) +#define ANOMALY_05000480 (0) +#define ANOMALY_05000485 (0) +#define ANOMALY_16000030 (0) #endif diff --git a/arch/blackfin/mach-bf561/include/mach/bf561.h b/arch/blackfin/mach-bf561/include/mach/bf561.h index 9968362a2ee..9f9a367e6a2 100644 --- a/arch/blackfin/mach-bf561/include/mach/bf561.h +++ b/arch/blackfin/mach-bf561/include/mach/bf561.h @@ -1,30 +1,9 @@ /* - * File: include/asm-blackfin/mach-bf561/bf561.h - * Based on: - * Author: + * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 * - * Created: - * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 + * Copyright 2005-2008 Analog Devices Inc. * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Licensed under the GPL-2 or later. */ #ifndef __MACH_BF561_H__ diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h new file mode 100644 index 00000000000..08072c86d5d --- /dev/null +++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h @@ -0,0 +1,14 @@ +/* + * mach/bfin_serial.h - Blackfin UART/Serial definitions + * + * Copyright 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MACH_SERIAL_H__ +#define __BFIN_MACH_SERIAL_H__ + +#define BFIN_UART_NR_PORTS 1 + +#endif diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h deleted file mode 100644 index ca8c5f64520..00000000000 --- a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * file: include/asm-blackfin/mach-bf561/bfin_serial_5xx.h - * based on: - * author: - * - * created: - * description: - * blackfin serial driver head file - * rev: - * - * modified: - * - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. - */ - -#include <linux/serial.h> -#include <asm/dma.h> -#include <asm/portmux.h> - -#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) -#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) -#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) -#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) -#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) -#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) -#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) - -#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) -#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) -#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) -#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) -#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) -#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) -#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) -#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) - -#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) -#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) - -#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) -#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) -#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) -#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) -#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) - -#ifdef CONFIG_BFIN_UART0_CTSRTS -# define CONFIG_SERIAL_BFIN_CTSRTS -# ifndef CONFIG_UART0_CTS_PIN -# define CONFIG_UART0_CTS_PIN -1 -# endif -# ifndef CONFIG_UART0_RTS_PIN -# define CONFIG_UART0_RTS_PIN -1 -# endif -#endif - -#define BFIN_UART_TX_FIFO_SIZE 2 - -struct bfin_serial_port { - struct uart_port port; - unsigned int old_status; - unsigned int lsr; -#ifdef CONFIG_SERIAL_BFIN_DMA - int tx_done; - int tx_count; - struct circ_buf rx_dma_buf; - struct timer_list rx_dma_timer; - int rx_dma_nrows; - unsigned int tx_dma_channel; - unsigned int rx_dma_channel; - struct work_struct tx_dma_workqueue; -#else -# if ANOMALY_05000363 - unsigned int anomaly_threshold; -# endif -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - struct timer_list cts_timer; - int cts_pin; - int rts_pin; -#endif -}; - -/* The hardware clears the LSR bits upon read, so we need to cache - * some of the more fun bits in software so they don't get lost - * when checking the LSR in other code paths (TX). - */ -static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart) -{ - unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR); - uart->lsr |= (lsr & (BI|FE|PE|OE)); - return lsr | uart->lsr; -} - -static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) -{ - uart->lsr = 0; - bfin_write16(uart->port.membase + OFFSET_LSR, -1); -} - -struct bfin_serial_res { - unsigned long uart_base_addr; - int uart_irq; -#ifdef CONFIG_SERIAL_BFIN_DMA - unsigned int uart_tx_dma_channel; - unsigned int uart_rx_dma_channel; -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - int uart_cts_pin; - int uart_rts_pin; -#endif -}; - -struct bfin_serial_res bfin_serial_resource[] = { - { - 0xFFC00400, - IRQ_UART_RX, -#ifdef CONFIG_SERIAL_BFIN_DMA - CH_UART_TX, - CH_UART_RX, -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - CONFIG_UART0_CTS_PIN, - CONFIG_UART0_RTS_PIN, -#endif - } -}; - -#define DRIVER_NAME "bfin-uart" - -static void bfin_serial_hw_init(struct bfin_serial_port *uart) -{ - -#ifdef CONFIG_SERIAL_BFIN_UART0 - peripheral_request(P_UART0_TX, DRIVER_NAME); - peripheral_request(P_UART0_RX, DRIVER_NAME); -#endif - -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - if (uart->cts_pin >= 0) { - gpio_request(uart->cts_pin, DRIVER_NAME); - gpio_direction_input(uart->cts_pin); - } - if (uart->rts_pin >= 0) { - gpio_request(uart->rts_pin, DRIVER_NAME); - gpio_direction_output(uart->rts_pin, 0); - } -#endif -} diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h index f79f6626b7e..dc470534c08 100644 --- a/arch/blackfin/mach-bf561/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h @@ -1,31 +1,7 @@ /* - * File: include/asm-blackfin/mach-bf561/blackfin.h - * Based on: - * Author: + * Copyright 2005-2010 Analog Devices Inc. * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Licensed under the GPL-2 or later. */ #ifndef _MACH_BLACKFIN_H_ @@ -34,12 +10,14 @@ #define BF561_FAMILY #include "bf561.h" -#include "mem_map.h" -#include "defBF561.h" #include "anomaly.h" -#if !defined(__ASSEMBLY__) -#include "cdefBF561.h" +#include <asm/def_LPBlackfin.h> +#include "defBF561.h" + +#ifndef __ASSEMBLY__ +# include <asm/cdef_LPBlackfin.h> +# include "cdefBF561.h" #endif #define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D() @@ -49,43 +27,15 @@ #define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() #define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) -#define SIC_IWR0 SICA_IWR0 -#define SIC_IWR1 SICA_IWR1 -#define SIC_IAR0 SICA_IAR0 -#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0 -#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1 -#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0 -#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1 - -#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0 -#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1 -#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0 -#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1 -#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0 -#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1 - -#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2)) -#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val) -#define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2)) -#define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val) -#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) -#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) -#define bfin_read_SICB_ISR(x) bfin_read32(SICB_ISR0 + (x << 2)) -#define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val) - -#define BFIN_UART_NR_PORTS 1 - -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ +/* Weird muxer funcs which pick SIC regs from IMASK base */ +#define __SIC_MUX(base, x) ((base) + ((x) << 2)) +#define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x)) +#define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val) +#define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x)) +#define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val) +#define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x)) +#define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val) +#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x)) +#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val) #endif /* _MACH_BLACKFIN_H_ */ diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h index 95d609f11c9..75333159720 100644 --- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h @@ -1,44 +1,12 @@ /* - * File: include/asm-blackfin/mach-bf561/cdefBF561.h - * Based on: - * Author: + * Copyright 2005-2010 Analog Devices Inc. * - * Created: - * Description: C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Licensed under the GPL-2 or later. */ #ifndef _CDEF_BF561_H #define _CDEF_BF561_H -#include <asm/blackfin.h> - -/* include all Core registers and bit definitions */ -#include "defBF561.h" - -/*include core specific register pointer definitions*/ -#include <asm/cdef_LPBlackfin.h> - /*********************************************************************************** */ /* System MMR Register Map */ /*********************************************************************************** */ @@ -54,49 +22,41 @@ #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) #define bfin_read_CHIPID() bfin_read32(CHIPID) -/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ -#define bfin_read_SWRST() bfin_read_SICA_SWRST() -#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val) -#define bfin_read_SYSCR() bfin_read_SICA_SYSCR() -#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val) - /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ -#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) -#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val) -#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR) -#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val) -#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT) -#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val) -#define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK) -#define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val) -#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0) -#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val) -#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1) -#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val) -#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0) -#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val) -#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1) -#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val) -#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2) -#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val) -#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3) -#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val) -#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4) -#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val) -#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5) -#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val) -#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6) -#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val) -#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7) -#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val) -#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0) -#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val) -#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1) -#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val) -#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0) -#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val) -#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1) -#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val) +#define bfin_read_SWRST() bfin_read16(SWRST) +#define bfin_write_SWRST(val) bfin_write16(SWRST,val) +#define bfin_read_SYSCR() bfin_read16(SYSCR) +#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) +#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) +#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val) +#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) +#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val) +#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) +#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val) +#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) +#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) +#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) +#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val) +#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) +#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val) +#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) +#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val) +#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) +#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val) +#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) +#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val) +#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) +#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val) +#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) +#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val) +#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) +#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val) +#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) +#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val) +#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) +#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val) +#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) +#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val) /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ #define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) @@ -555,14 +515,14 @@ #define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME) #define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val) /*DMA traffic control registers */ -#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER) -#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER,val) -#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT) -#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT,val) -#define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER) -#define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER,val) -#define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT) -#define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT,val) +#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER) +#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER,val) +#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT) +#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT,val) +#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER) +#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER,val) +#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT) +#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT,val) /* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ #define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG) #define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val) @@ -877,110 +837,110 @@ #define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP) #define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val) /* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ -#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG) -#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG,val) -#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_read32(MDMA1_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D0_NEXT_DESC_PTR,val) -#define bfin_read_MDMA1_D0_START_ADDR() bfin_read32(MDMA1_D0_START_ADDR) -#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_write32(MDMA1_D0_START_ADDR,val) -#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT) -#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT,val) -#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT) -#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT,val) -#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY) -#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY,val) -#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY) -#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY,val) -#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_read32(MDMA1_D0_CURR_DESC_PTR) -#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_write32(MDMA1_D0_CURR_DESC_PTR,val) -#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_read32(MDMA1_D0_CURR_ADDR) -#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_write32(MDMA1_D0_CURR_ADDR,val) -#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT) -#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT,val) -#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT) -#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT,val) -#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS) -#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS,val) -#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP,val) -#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG) -#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG,val) -#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_read32(MDMA1_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S0_NEXT_DESC_PTR,val) -#define bfin_read_MDMA1_S0_START_ADDR() bfin_read32(MDMA1_S0_START_ADDR) -#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_write32(MDMA1_S0_START_ADDR,val) -#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT) -#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT,val) -#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT) -#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT,val) -#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY) -#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY,val) -#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY) -#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY,val) -#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_read32(MDMA1_S0_CURR_DESC_PTR) -#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_write32(MDMA1_S0_CURR_DESC_PTR,val) -#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_read32(MDMA1_S0_CURR_ADDR) -#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_write32(MDMA1_S0_CURR_ADDR,val) -#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT) -#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT,val) -#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT) -#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT,val) -#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS) -#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS,val) -#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP,val) -#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG) -#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG,val) -#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_read32(MDMA1_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D1_NEXT_DESC_PTR,val) -#define bfin_read_MDMA1_D1_START_ADDR() bfin_read32(MDMA1_D1_START_ADDR) -#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_write32(MDMA1_D1_START_ADDR,val) -#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT) -#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT,val) -#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT) -#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT,val) -#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY) -#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY,val) -#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY) -#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY,val) -#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_read32(MDMA1_D1_CURR_DESC_PTR) -#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_write32(MDMA1_D1_CURR_DESC_PTR,val) -#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_read32(MDMA1_D1_CURR_ADDR) -#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_write32(MDMA1_D1_CURR_ADDR,val) -#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT) -#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT,val) -#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT) -#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT,val) -#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS) -#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS,val) -#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP,val) -#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG) -#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG,val) -#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_read32(MDMA1_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S1_NEXT_DESC_PTR,val) -#define bfin_read_MDMA1_S1_START_ADDR() bfin_read32(MDMA1_S1_START_ADDR) -#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_write32(MDMA1_S1_START_ADDR,val) -#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT) -#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT,val) -#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT) -#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT,val) -#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY) -#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY,val) -#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY) -#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY,val) -#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_read32(MDMA1_S1_CURR_DESC_PTR) -#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_write32(MDMA1_S1_CURR_DESC_PTR,val) -#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_read32(MDMA1_S1_CURR_ADDR) -#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_write32(MDMA1_S1_CURR_ADDR,val) -#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT) -#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT,val) -#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) -#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT,val) -#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS) -#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS,val) -#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP,val) +#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) +#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG,val) +#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR) +#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR,val) +#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR) +#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR,val) +#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) +#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT,val) +#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) +#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT,val) +#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) +#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY,val) +#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) +#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY,val) +#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR) +#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR,val) +#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR) +#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR,val) +#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) +#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT,val) +#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) +#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT,val) +#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) +#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS,val) +#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) +#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP,val) +#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) +#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG,val) +#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR) +#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR,val) +#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR) +#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR,val) +#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) +#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT,val) +#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) +#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT,val) +#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) +#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY,val) +#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) +#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY,val) +#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR) +#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR,val) +#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR) +#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR,val) +#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) +#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT,val) +#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) +#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT,val) +#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) +#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS,val) +#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) +#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP,val) +#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) +#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG,val) +#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR) +#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR,val) +#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR) +#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR,val) +#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) +#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT,val) +#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) +#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT,val) +#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) +#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY,val) +#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) +#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY,val) +#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR) +#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR,val) +#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR) +#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR,val) +#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) +#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT,val) +#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) +#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT,val) +#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) +#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS,val) +#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) +#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP,val) +#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) +#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG,val) +#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR) +#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR,val) +#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR) +#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR,val) +#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) +#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT,val) +#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) +#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT,val) +#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) +#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY,val) +#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) +#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY,val) +#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR) +#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR,val) +#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR) +#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR,val) +#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) +#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT,val) +#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) +#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT,val) +#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) +#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS,val) +#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) +#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP,val) /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ #define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG) #define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val) @@ -1295,110 +1255,110 @@ #define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP) #define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val) /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ -#define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG) -#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG,val) -#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_read32(MDMA2_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D0_NEXT_DESC_PTR,val) -#define bfin_read_MDMA2_D0_START_ADDR() bfin_read32(MDMA2_D0_START_ADDR) -#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_write32(MDMA2_D0_START_ADDR,val) -#define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT) -#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT,val) -#define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT) -#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT,val) -#define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY) -#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY,val) -#define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY) -#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY,val) -#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_read32(MDMA2_D0_CURR_DESC_PTR) -#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_write32(MDMA2_D0_CURR_DESC_PTR,val) -#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_read32(MDMA2_D0_CURR_ADDR) -#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_write32(MDMA2_D0_CURR_ADDR,val) -#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT) -#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT,val) -#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT) -#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT,val) -#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS) -#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS,val) -#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP,val) -#define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG) -#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG,val) -#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_read32(MDMA2_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S0_NEXT_DESC_PTR,val) -#define bfin_read_MDMA2_S0_START_ADDR() bfin_read32(MDMA2_S0_START_ADDR) -#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_write32(MDMA2_S0_START_ADDR,val) -#define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT) -#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT,val) -#define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT) -#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT,val) -#define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY) -#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY,val) -#define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY) -#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY,val) -#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_read32(MDMA2_S0_CURR_DESC_PTR) -#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_write32(MDMA2_S0_CURR_DESC_PTR,val) -#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_read32(MDMA2_S0_CURR_ADDR) -#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_write32(MDMA2_S0_CURR_ADDR,val) -#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT) -#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT,val) -#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT) -#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT,val) -#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS) -#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS,val) -#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP,val) -#define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG) -#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG,val) -#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_read32(MDMA2_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D1_NEXT_DESC_PTR,val) -#define bfin_read_MDMA2_D1_START_ADDR() bfin_read32(MDMA2_D1_START_ADDR) -#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_write32(MDMA2_D1_START_ADDR,val) -#define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT) -#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT,val) -#define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT) -#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT,val) -#define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY) -#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY,val) -#define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY) -#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY,val) -#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_read32(MDMA2_D1_CURR_DESC_PTR) -#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_write32(MDMA2_D1_CURR_DESC_PTR,val) -#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_read32(MDMA2_D1_CURR_ADDR) -#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_write32(MDMA2_D1_CURR_ADDR,val) -#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT) -#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT,val) -#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT) -#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT,val) -#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS) -#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS,val) -#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP,val) -#define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG) -#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG,val) -#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_read32(MDMA2_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S1_NEXT_DESC_PTR,val) -#define bfin_read_MDMA2_S1_START_ADDR() bfin_read32(MDMA2_S1_START_ADDR) -#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_write32(MDMA2_S1_START_ADDR,val) -#define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT) -#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT,val) -#define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT) -#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT,val) -#define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY) -#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY,val) -#define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY) -#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY,val) -#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_read32(MDMA2_S1_CURR_DESC_PTR) -#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_write32(MDMA2_S1_CURR_DESC_PTR,val) -#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_read32(MDMA2_S1_CURR_ADDR) -#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_write32(MDMA2_S1_CURR_ADDR,val) -#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT) -#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT,val) -#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT) -#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT,val) -#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS) -#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS,val) -#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP,val) +#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) +#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val) +#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val) +#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) +#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val) +#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) +#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val) +#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) +#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val) +#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) +#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val) +#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) +#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val) +#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) +#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val) +#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) +#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val) +#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) +#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val) +#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) +#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val) +#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) +#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val) +#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) +#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val) +#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) +#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val) +#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val) +#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) +#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val) +#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) +#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val) +#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) +#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val) +#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) +#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val) +#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) +#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val) +#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) +#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val) +#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) +#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val) +#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) +#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val) +#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) +#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val) +#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) +#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val) +#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) +#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val) +#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) +#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val) +#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val) +#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) +#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val) +#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) +#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val) +#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) +#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val) +#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) +#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val) +#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) +#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val) +#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) +#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val) +#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) +#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val) +#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) +#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val) +#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) +#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val) +#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) +#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val) +#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) +#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val) +#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) +#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val) +#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val) +#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) +#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val) +#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) +#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val) +#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) +#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val) +#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) +#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val) +#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) +#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val) +#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) +#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val) +#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) +#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val) +#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) +#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val) +#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) +#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val) +#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) +#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val) +#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) +#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val) /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ #define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG) #define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val) @@ -1497,86 +1457,4 @@ #define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS) #define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val) -#define bfin_read_MDMA_S0_CONFIG() bfin_read_MDMA1_S0_CONFIG() -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA1_S0_CONFIG(val) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read_MDMA1_S0_IRQ_STATUS() -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA1_S0_IRQ_STATUS(val) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read_MDMA1_S0_X_MODIFY() -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA1_S0_X_MODIFY(val) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read_MDMA1_S0_Y_MODIFY() -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA1_S0_Y_MODIFY(val) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read_MDMA1_S0_X_COUNT() -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA1_S0_X_COUNT(val) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read_MDMA1_S0_Y_COUNT() -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA1_S0_Y_COUNT(val) -#define bfin_read_MDMA_S0_START_ADDR() bfin_read_MDMA1_S0_START_ADDR() -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA1_S0_START_ADDR(val) -#define bfin_read_MDMA_D0_CONFIG() bfin_read_MDMA1_D0_CONFIG() -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA1_D0_CONFIG(val) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read_MDMA1_D0_IRQ_STATUS() -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA1_D0_IRQ_STATUS(val) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read_MDMA1_D0_X_MODIFY() -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA1_D0_X_MODIFY(val) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read_MDMA1_D0_Y_MODIFY() -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA1_D0_Y_MODIFY(val) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read_MDMA1_D0_X_COUNT() -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA1_D0_X_COUNT(val) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read_MDMA1_D0_Y_COUNT() -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA1_D0_Y_COUNT(val) -#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR() -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val) - -/* These need to be last due to the cdef/linux inter-dependencies */ -#include <asm/irq.h> - -/* Writing to PLL_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_PLL_CTL(unsigned int val) -{ - unsigned long flags, iwr0, iwr1; - - if (val == bfin_read_PLL_CTL()) - return; - - local_irq_save_hw(flags); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SICA_IWR0); - iwr1 = bfin_read32(SICA_IWR1); - /* Only allow PPL Wakeup) */ - bfin_write32(SICA_IWR0, IWR_ENABLE(0)); - bfin_write32(SICA_IWR1, 0); - - bfin_write16(PLL_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SICA_IWR0, iwr0); - bfin_write32(SICA_IWR1, iwr1); - local_irq_restore_hw(flags); -} - -/* Writing to VR_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_VR_CTL(unsigned int val) -{ - unsigned long flags, iwr0, iwr1; - - if (val == bfin_read_VR_CTL()) - return; - - local_irq_save_hw(flags); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SICA_IWR0); - iwr1 = bfin_read32(SICA_IWR1); - /* Only allow PPL Wakeup) */ - bfin_write32(SICA_IWR0, IWR_ENABLE(0)); - bfin_write32(SICA_IWR1, 0); - - bfin_write16(VR_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SICA_IWR0, iwr0); - bfin_write32(SICA_IWR1, iwr1); - local_irq_restore_hw(flags); -} - #endif /* _CDEF_BF561_H */ diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h index cf922295f4c..9f21f768c63 100644 --- a/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h @@ -1,43 +1,11 @@ - /* - * File: include/asm-blackfin/mach-bf561/defBF561.h - * Based on: - * Author: - * - * Created: - * Description: - * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * Copyright 2005-2010 Analog Devices Inc. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF561_H #define _DEF_BF561_H -/* -#if !defined(__ADSPBF561__) -#warning defBF561.h should only be included for BF561 chip. -#endif -*/ -/* include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> /*********************************************************************************** */ /* System MMR Register Map */ @@ -53,32 +21,29 @@ #define CHIPID 0xFFC00014 /* Chip ID Register */ /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ -#define SWRST SICA_SWRST -#define SYSCR SICA_SYSCR #define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) #define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) #define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) #define RESET_SOFTWARE (SWRST_OCCURRED) /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ -#define SICA_SWRST 0xFFC00100 /* Software Reset register */ -#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ -#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ -#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */ -#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ -#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ -#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ -#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ -#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ -#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ -#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ -#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ -#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ -#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ -#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ -#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ -#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ -#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ +#define SWRST 0xFFC00100 /* Software Reset register */ +#define SYSCR 0xFFC00104 /* System Reset Configuration register */ +#define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ +#define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ +#define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ +#define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ +#define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ +#define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ +#define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ +#define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ +#define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ +#define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ +#define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ +#define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ +#define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ #define SICB_SWRST 0xFFC01100 /* reserved */ @@ -339,10 +304,10 @@ #define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */ /*DMA traffic control registers */ -#define DMA1_TC_PER 0xFFC01B0C /* Traffic control periods */ -#define DMA1_TC_CNT 0xFFC01B10 /* Traffic control current counts */ -#define DMA2_TC_PER 0xFFC00B0C /* Traffic control periods */ -#define DMA2_TC_CNT 0xFFC00B10 /* Traffic control current counts */ +#define DMAC0_TC_PER 0xFFC00B0C /* Traffic control periods */ +#define DMAC0_TC_CNT 0xFFC00B10 /* Traffic control current counts */ +#define DMAC1_TC_PER 0xFFC01B0C /* Traffic control periods */ +#define DMAC1_TC_CNT 0xFFC01B10 /* Traffic control current counts */ /* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ #define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */ @@ -514,61 +479,61 @@ #define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */ /* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ -#define MDMA1_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */ -#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */ -#define MDMA1_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */ -#define MDMA1_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */ -#define MDMA1_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */ -#define MDMA1_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */ -#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */ -#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */ -#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */ -#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */ -#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */ -#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */ -#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */ - -#define MDMA1_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */ -#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */ -#define MDMA1_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */ -#define MDMA1_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */ -#define MDMA1_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */ -#define MDMA1_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */ -#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */ -#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */ -#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */ -#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */ -#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */ -#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */ -#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */ - -#define MDMA1_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */ -#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */ -#define MDMA1_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */ -#define MDMA1_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */ -#define MDMA1_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */ -#define MDMA1_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */ -#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */ -#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */ -#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */ -#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */ -#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */ -#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */ -#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */ - -#define MDMA1_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */ -#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */ -#define MDMA1_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */ -#define MDMA1_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */ -#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */ -#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */ -#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */ -#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */ -#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */ -#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */ -#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */ -#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */ -#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */ +#define MDMA_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */ +#define MDMA_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */ +#define MDMA_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */ +#define MDMA_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */ +#define MDMA_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */ +#define MDMA_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */ +#define MDMA_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */ +#define MDMA_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */ +#define MDMA_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */ +#define MDMA_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */ +#define MDMA_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */ +#define MDMA_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */ +#define MDMA_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */ + +#define MDMA_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */ +#define MDMA_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */ +#define MDMA_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */ +#define MDMA_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */ +#define MDMA_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */ +#define MDMA_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */ +#define MDMA_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */ +#define MDMA_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */ +#define MDMA_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */ +#define MDMA_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */ +#define MDMA_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */ +#define MDMA_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */ +#define MDMA_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */ + +#define MDMA_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */ +#define MDMA_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */ +#define MDMA_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */ +#define MDMA_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */ +#define MDMA_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */ +#define MDMA_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */ +#define MDMA_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */ +#define MDMA_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */ +#define MDMA_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */ +#define MDMA_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */ +#define MDMA_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */ +#define MDMA_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */ +#define MDMA_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */ + +#define MDMA_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */ +#define MDMA_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */ +#define MDMA_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */ +#define MDMA_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */ +#define MDMA_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */ +#define MDMA_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */ +#define MDMA_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */ +#define MDMA_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */ +#define MDMA_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */ +#define MDMA_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */ +#define MDMA_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */ +#define MDMA_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */ +#define MDMA_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */ /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ #define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */ @@ -740,61 +705,61 @@ #define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */ /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ -#define MDMA2_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */ -#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */ -#define MDMA2_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */ -#define MDMA2_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */ -#define MDMA2_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */ -#define MDMA2_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */ -#define MDMA2_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */ -#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */ -#define MDMA2_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */ -#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */ -#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */ -#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */ -#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */ - -#define MDMA2_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */ -#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */ -#define MDMA2_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */ -#define MDMA2_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */ -#define MDMA2_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */ -#define MDMA2_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */ -#define MDMA2_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */ -#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */ -#define MDMA2_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */ -#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */ -#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */ -#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */ -#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */ - -#define MDMA2_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */ -#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */ -#define MDMA2_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */ -#define MDMA2_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */ -#define MDMA2_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */ -#define MDMA2_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */ -#define MDMA2_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */ -#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */ -#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */ -#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */ -#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */ -#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */ -#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */ - -#define MDMA2_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */ -#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */ -#define MDMA2_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */ -#define MDMA2_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */ -#define MDMA2_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */ -#define MDMA2_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */ -#define MDMA2_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */ -#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */ -#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */ -#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */ -#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */ -#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ -#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ +#define MDMA_D2_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */ +#define MDMA_D2_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */ +#define MDMA_D2_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */ +#define MDMA_D2_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */ +#define MDMA_D2_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */ +#define MDMA_D2_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */ +#define MDMA_D2_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */ +#define MDMA_D2_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */ +#define MDMA_D2_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */ +#define MDMA_D2_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */ +#define MDMA_D2_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */ +#define MDMA_D2_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */ +#define MDMA_D2_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */ + +#define MDMA_S2_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */ +#define MDMA_S2_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */ +#define MDMA_S2_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */ +#define MDMA_S2_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */ +#define MDMA_S2_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */ +#define MDMA_S2_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */ +#define MDMA_S2_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */ +#define MDMA_S2_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */ +#define MDMA_S2_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */ +#define MDMA_S2_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */ +#define MDMA_S2_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */ +#define MDMA_S2_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */ +#define MDMA_S2_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */ + +#define MDMA_D3_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */ +#define MDMA_D3_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */ +#define MDMA_D3_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */ +#define MDMA_D3_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */ +#define MDMA_D3_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */ +#define MDMA_D3_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */ +#define MDMA_D3_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */ +#define MDMA_D3_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */ +#define MDMA_D3_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */ +#define MDMA_D3_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */ +#define MDMA_D3_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */ +#define MDMA_D3_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */ +#define MDMA_D3_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */ + +#define MDMA_S3_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */ +#define MDMA_S3_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */ +#define MDMA_S3_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */ +#define MDMA_S3_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */ +#define MDMA_S3_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */ +#define MDMA_S3_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */ +#define MDMA_S3_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */ +#define MDMA_S3_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */ +#define MDMA_S3_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */ +#define MDMA_S3_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */ +#define MDMA_S3_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */ +#define MDMA_S3_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ +#define MDMA_S3_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ #define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */ @@ -853,65 +818,11 @@ /* System MMR Register Bits */ /******************************************************************************* */ -/* ********************* PLL AND RESET MASKS ************************ */ - -/* PLL_CTL Masks */ -#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ -#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ -#define PLL_OFF 0x00000002 /* Shut off PLL clocks */ -#define STOPCK_OFF 0x00000008 /* Core clock off */ -#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ -#define BYPASS 0x00000100 /* Bypass the PLL */ - /* CHIPID Masks */ #define CHIPID_VERSION 0xF0000000 #define CHIPID_FAMILY 0x0FFFF000 #define CHIPID_MANUFACTURE 0x00000FFE -/* VR_CTL Masks */ -#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ -#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ -#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ -#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ -#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ - -#define GAIN 0x000C /* Voltage Level Gain */ -#define GAIN_5 0x0000 /* GAIN = 5*/ -#define GAIN_10 0x0004 /* GAIN = 1*/ -#define GAIN_20 0x0008 /* GAIN = 2*/ -#define GAIN_50 0x000C /* GAIN = 5*/ - -#define VLEV 0x00F0 /* Internal Voltage Level */ -#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ -#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ -#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ -#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ -#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ -#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ -#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ -#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ -#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ -#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ - -#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ -#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ - -/* PLL_DIV Masks */ -#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ - -#define CSEL 0x30 /* Core Select */ -#define SSEL 0xf /* System Select */ -#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ -#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ -#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ -#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ - -/* PLL_STAT Masks */ -#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ -#define FULL_ON 0x0002 /* Processor In Full On Mode */ -#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ -#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ - /* SICA_SYSCR Masks */ #define COREB_SRAM_INIT 0x0020 @@ -953,143 +864,6 @@ #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ -/* ***************************** UART CONTROLLER MASKS ********************** */ - -/* UART_LCR Register */ - -#define DLAB 0x80 -#define SB 0x40 -#define STP 0x20 -#define EPS 0x10 -#define PEN 0x08 -#define STB 0x04 -#define WLS(x) ((x-5) & 0x03) - -#define DLAB_P 0x07 -#define SB_P 0x06 -#define STP_P 0x05 -#define EPS_P 0x04 -#define PEN_P 0x03 -#define STB_P 0x02 -#define WLS_P1 0x01 -#define WLS_P0 0x00 - -/* UART_MCR Register */ -#define LOOP_ENA 0x10 -#define LOOP_ENA_P 0x04 - -/* UART_LSR Register */ -#define TEMT 0x40 -#define THRE 0x20 -#define BI 0x10 -#define FE 0x08 -#define PE 0x04 -#define OE 0x02 -#define DR 0x01 - -#define TEMP_P 0x06 -#define THRE_P 0x05 -#define BI_P 0x04 -#define FE_P 0x03 -#define PE_P 0x02 -#define OE_P 0x01 -#define DR_P 0x00 - -/* UART_IER Register */ -#define ELSI 0x04 -#define ETBEI 0x02 -#define ERBFI 0x01 - -#define ELSI_P 0x02 -#define ETBEI_P 0x01 -#define ERBFI_P 0x00 - -/* UART_IIR Register */ -#define STATUS(x) ((x << 1) & 0x06) -#define NINT 0x01 -#define STATUS_P1 0x02 -#define STATUS_P0 0x01 -#define NINT_P 0x00 -#define IIR_TX_READY 0x02 /* UART_THR empty */ -#define IIR_RX_READY 0x04 /* Receive data ready */ -#define IIR_LINE_CHANGE 0x06 /* Receive line status */ -#define IIR_STATUS 0x06 - -/* UART_GCTL Register */ -#define FFE 0x20 -#define FPE 0x10 -#define RPOLC 0x08 -#define TPOLC 0x04 -#define IREN 0x02 -#define UCEN 0x01 - -#define FFE_P 0x05 -#define FPE_P 0x04 -#define RPOLC_P 0x03 -#define TPOLC_P 0x02 -#define IREN_P 0x01 -#define UCEN_P 0x00 - -/* ********** SERIAL PORT MASKS ********************** */ - -/* SPORTx_TCR1 Masks */ -#define TSPEN 0x0001 /* TX enable */ -#define ITCLK 0x0002 /* Internal TX Clock Select */ -#define TDTYPE 0x000C /* TX Data Formatting Select */ -#define TLSBIT 0x0010 /* TX Bit Order */ -#define ITFS 0x0200 /* Internal TX Frame Sync Select */ -#define TFSR 0x0400 /* TX Frame Sync Required Select */ -#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ -#define LTFS 0x1000 /* Low TX Frame Sync Select */ -#define LATFS 0x2000 /* Late TX Frame Sync Select */ -#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ - -/* SPORTx_TCR2 Masks */ -#define SLEN 0x001F /*TX Word Length */ -#define TXSE 0x0100 /*TX Secondary Enable */ -#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ -#define TRFST 0x0400 /*TX Right-First Data Order */ - -/* SPORTx_RCR1 Masks */ -#define RSPEN 0x0001 /* RX enable */ -#define IRCLK 0x0002 /* Internal RX Clock Select */ -#define RDTYPE 0x000C /* RX Data Formatting Select */ -#define RULAW 0x0008 /* u-Law enable */ -#define RALAW 0x000C /* A-Law enable */ -#define RLSBIT 0x0010 /* RX Bit Order */ -#define IRFS 0x0200 /* Internal RX Frame Sync Select */ -#define RFSR 0x0400 /* RX Frame Sync Required Select */ -#define LRFS 0x1000 /* Low RX Frame Sync Select */ -#define LARFS 0x2000 /* Late RX Frame Sync Select */ -#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ - -/* SPORTx_RCR2 Masks */ -#define SLEN 0x001F /*RX Word Length */ -#define RXSE 0x0100 /*RX Secondary Enable */ -#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */ -#define RRFST 0x0400 /*Right-First Data Order */ - -/*SPORTx_STAT Masks */ -#define RXNE 0x0001 /*RX FIFO Not Empty Status */ -#define RUVF 0x0002 /*RX Underflow Status */ -#define ROVF 0x0004 /*RX Overflow Status */ -#define TXF 0x0008 /*TX FIFO Full Status */ -#define TUVF 0x0010 /*TX Underflow Status */ -#define TOVF 0x0020 /*TX Overflow Status */ -#define TXHRE 0x0040 /*TX Hold Register Empty */ - -/*SPORTx_MCMC1 Masks */ -#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */ -#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */ - -/*SPORTx_MCMC2 Masks */ -#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */ -#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */ -#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */ -#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */ -#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */ -#define MFD 0x0000F000 /*Multichannel Frame Delay */ - /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ /* PPI_CONTROL Masks */ @@ -1105,6 +879,13 @@ #define DLENGTH 0x00003800 /* PPI Data Length */ #define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ #define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ +#define DLEN_10 0x00000800 /* Data Length = 10 Bits */ +#define DLEN_11 0x00001000 /* Data Length = 11 Bits */ +#define DLEN_12 0x00001800 /* Data Length = 12 Bits */ +#define DLEN_13 0x00002000 /* Data Length = 13 Bits */ +#define DLEN_14 0x00002800 /* Data Length = 14 Bits */ +#define DLEN_15 0x00003000 /* Data Length = 15 Bits */ +#define DLEN_16 0x00003800 /* Data Length = 16 Bits */ #define POL 0x0000C000 /* PPI Signal Polarities */ #define POLC 0x4000 /* PPI Clock Polarity */ #define POLS 0x8000 /* PPI Frame Sync Polarity */ @@ -1119,53 +900,6 @@ /* ********** DMA CONTROLLER MASKS *********************8 */ -/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */ -#define DMAEN 0x00000001 /* Channel Enable */ -#define WNR 0x00000002 /* Channel Direction (W/R*) */ -#define WDSIZE_8 0x00000000 /* Word Size 8 bits */ -#define WDSIZE_16 0x00000004 /* Word Size 16 bits */ -#define WDSIZE_32 0x00000008 /* Word Size 32 bits */ -#define DMA2D 0x00000010 /* 2D/1D* Mode */ -#define RESTART 0x00000020 /* Restart */ -#define DI_SEL 0x00000040 /* Data Interrupt Select */ -#define DI_EN 0x00000080 /* Data Interrupt Enable */ -#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ -#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ -#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ -#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ -#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ -#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ -#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ -#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ -#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ -#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ -#define NDSIZE 0x00000900 /* Next Descriptor Size */ -#define DMAFLOW 0x00007000 /* Flow Control */ -#define DMAFLOW_STOP 0x0000 /* Stop Mode */ -#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ -#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ -#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ -#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ - -#define DMAEN_P 0 /* Channel Enable */ -#define WNR_P 1 /* Channel Direction (W/R*) */ -#define DMA2D_P 4 /* 2D/1D* Mode */ -#define RESTART_P 5 /* Restart */ -#define DI_SEL_P 6 /* Data Interrupt Select */ -#define DI_EN_P 7 /* Data Interrupt Enable */ - -/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */ - -#define DMA_DONE 0x00000001 /* DMA Done Indicator */ -#define DMA_ERR 0x00000002 /* DMA Error Indicator */ -#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ -#define DMA_RUN 0x00000008 /* DMA Running Indicator */ - -#define DMA_DONE_P 0 /* DMA Done Indicator */ -#define DMA_ERR_P 1 /* DMA Error Indicator */ -#define DFETCH_P 2 /* Descriptor Fetch Indicator */ -#define DMA_RUN_P 3 /* DMA Running Indicator */ - /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */ #define CTYPE 0x00000040 /* DMA Channel Type Indicator */ @@ -1363,101 +1097,6 @@ #define ERR_TYP_P0 0x0E #define ERR_TYP_P1 0x0F -/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */ - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ -#define PF0_P 0 -#define PF1_P 1 -#define PF2_P 2 -#define PF3_P 3 -#define PF4_P 4 -#define PF5_P 5 -#define PF6_P 6 -#define PF7_P 7 -#define PF8_P 8 -#define PF9_P 9 -#define PF10_P 10 -#define PF11_P 11 -#define PF12_P 12 -#define PF13_P 13 -#define PF14_P 14 -#define PF15_P 15 - -/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */ - -/* SPI_CTL Masks */ -#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ -#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ -#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ -#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ -#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ -#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ -#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ -#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ -#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ -#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ -#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ -#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ - -/* SPI_FLG Masks */ -#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_FLG Bit Positions */ -#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_STAT Masks */ -#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ -#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */ -#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ -#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ -#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ -#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ -#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ - /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ /* AMGCTL Masks */ diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h index 7882f79e1ad..f9f8b2adf4b 100644 --- a/arch/blackfin/mach-bf561/include/mach/gpio.h +++ b/arch/blackfin/mach-bf561/include/mach/gpio.h @@ -1,7 +1,4 @@ /* - * File: arch/blackfin/mach-bf561/include/mach/gpio.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * * Copyright (C) 2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ @@ -12,57 +9,59 @@ #define MAX_BLACKFIN_GPIOS 48 -#define GPIO_PF0 0 -#define GPIO_PF1 1 -#define GPIO_PF2 2 -#define GPIO_PF3 3 -#define GPIO_PF4 4 -#define GPIO_PF5 5 -#define GPIO_PF6 6 -#define GPIO_PF7 7 -#define GPIO_PF8 8 -#define GPIO_PF9 9 -#define GPIO_PF10 10 -#define GPIO_PF11 11 -#define GPIO_PF12 12 -#define GPIO_PF13 13 -#define GPIO_PF14 14 -#define GPIO_PF15 15 -#define GPIO_PF16 16 -#define GPIO_PF17 17 -#define GPIO_PF18 18 -#define GPIO_PF19 19 -#define GPIO_PF20 20 -#define GPIO_PF21 21 -#define GPIO_PF22 22 -#define GPIO_PF23 23 -#define GPIO_PF24 24 -#define GPIO_PF25 25 -#define GPIO_PF26 26 -#define GPIO_PF27 27 -#define GPIO_PF28 28 -#define GPIO_PF29 29 -#define GPIO_PF30 30 -#define GPIO_PF31 31 -#define GPIO_PF32 32 -#define GPIO_PF33 33 -#define GPIO_PF34 34 -#define GPIO_PF35 35 -#define GPIO_PF36 36 -#define GPIO_PF37 37 -#define GPIO_PF38 38 -#define GPIO_PF39 39 -#define GPIO_PF40 40 -#define GPIO_PF41 41 -#define GPIO_PF42 42 -#define GPIO_PF43 43 -#define GPIO_PF44 44 -#define GPIO_PF45 45 -#define GPIO_PF46 46 -#define GPIO_PF47 47 +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 +#define GPIO_PF16 16 +#define GPIO_PF17 17 +#define GPIO_PF18 18 +#define GPIO_PF19 19 +#define GPIO_PF20 20 +#define GPIO_PF21 21 +#define GPIO_PF22 22 +#define GPIO_PF23 23 +#define GPIO_PF24 24 +#define GPIO_PF25 25 +#define GPIO_PF26 26 +#define GPIO_PF27 27 +#define GPIO_PF28 28 +#define GPIO_PF29 29 +#define GPIO_PF30 30 +#define GPIO_PF31 31 +#define GPIO_PF32 32 +#define GPIO_PF33 33 +#define GPIO_PF34 34 +#define GPIO_PF35 35 +#define GPIO_PF36 36 +#define GPIO_PF37 37 +#define GPIO_PF38 38 +#define GPIO_PF39 39 +#define GPIO_PF40 40 +#define GPIO_PF41 41 +#define GPIO_PF42 42 +#define GPIO_PF43 43 +#define GPIO_PF44 44 +#define GPIO_PF45 45 +#define GPIO_PF46 46 +#define GPIO_PF47 47 -#define PORT_FIO0 GPIO_0 -#define PORT_FIO1 GPIO_16 -#define PORT_FIO2 GPIO_32 +#define PORT_FIO0 GPIO_PF0 +#define PORT_FIO1 GPIO_PF16 +#define PORT_FIO2 GPIO_PF32 + +#include <mach-common/ports-f.h> #endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf561/include/mach/irq.h b/arch/blackfin/mach-bf561/include/mach/irq.h index 6698389c556..d6998520f70 100644 --- a/arch/blackfin/mach-bf561/include/mach/irq.h +++ b/arch/blackfin/mach-bf561/include/mach/irq.h @@ -1,243 +1,104 @@ - /* - * File: include/asm-blackfin/mach-bf561/irq.h - * Based on: - * Author: - * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * Copyright 2005-2008 Analog Devices Inc. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Licensed under the GPL-2 or later. */ #ifndef _BF561_IRQ_H_ #define _BF561_IRQ_H_ -/*********************************************************************** - * Interrupt source definitions: - Event Source Core Event Name IRQ No - (highest priority) - Emulation Events EMU 0 - Reset RST 1 - NMI NMI 2 - Exception EVX 3 - Reserved -- 4 - Hardware Error IVHW 5 - Core Timer IVTMR 6 * - - PLL Wakeup Interrupt IVG7 7 - DMA1 Error (generic) IVG7 8 - DMA2 Error (generic) IVG7 9 - IMDMA Error (generic) IVG7 10 - PPI1 Error Interrupt IVG7 11 - PPI2 Error Interrupt IVG7 12 - SPORT0 Error Interrupt IVG7 13 - SPORT1 Error Interrupt IVG7 14 - SPI Error Interrupt IVG7 15 - UART Error Interrupt IVG7 16 - Reserved Interrupt IVG7 17 - - DMA1 0 Interrupt(PPI1) IVG8 18 - DMA1 1 Interrupt(PPI2) IVG8 19 - DMA1 2 Interrupt IVG8 20 - DMA1 3 Interrupt IVG8 21 - DMA1 4 Interrupt IVG8 22 - DMA1 5 Interrupt IVG8 23 - DMA1 6 Interrupt IVG8 24 - DMA1 7 Interrupt IVG8 25 - DMA1 8 Interrupt IVG8 26 - DMA1 9 Interrupt IVG8 27 - DMA1 10 Interrupt IVG8 28 - DMA1 11 Interrupt IVG8 29 - - DMA2 0 (SPORT0 RX) IVG9 30 - DMA2 1 (SPORT0 TX) IVG9 31 - DMA2 2 (SPORT1 RX) IVG9 32 - DMA2 3 (SPORT2 TX) IVG9 33 - DMA2 4 (SPI) IVG9 34 - DMA2 5 (UART RX) IVG9 35 - DMA2 6 (UART TX) IVG9 36 - DMA2 7 Interrupt IVG9 37 - DMA2 8 Interrupt IVG9 38 - DMA2 9 Interrupt IVG9 39 - DMA2 10 Interrupt IVG9 40 - DMA2 11 Interrupt IVG9 41 - - TIMER 0 Interrupt IVG10 42 - TIMER 1 Interrupt IVG10 43 - TIMER 2 Interrupt IVG10 44 - TIMER 3 Interrupt IVG10 45 - TIMER 4 Interrupt IVG10 46 - TIMER 5 Interrupt IVG10 47 - TIMER 6 Interrupt IVG10 48 - TIMER 7 Interrupt IVG10 49 - TIMER 8 Interrupt IVG10 50 - TIMER 9 Interrupt IVG10 51 - TIMER 10 Interrupt IVG10 52 - TIMER 11 Interrupt IVG10 53 - - Programmable Flags0 A (8) IVG11 54 - Programmable Flags0 B (8) IVG11 55 - Programmable Flags1 A (8) IVG11 56 - Programmable Flags1 B (8) IVG11 57 - Programmable Flags2 A (8) IVG11 58 - Programmable Flags2 B (8) IVG11 59 - - MDMA1 0 write/read INT IVG8 60 - MDMA1 1 write/read INT IVG8 61 - - MDMA2 0 write/read INT IVG9 62 - MDMA2 1 write/read INT IVG9 63 - - IMDMA 0 write/read INT IVG12 64 - IMDMA 1 write/read INT IVG12 65 - - Watch Dog Timer IVG13 66 - - Reserved interrupt IVG7 67 - Reserved interrupt IVG7 68 - Supplemental interrupt 0 IVG7 69 - supplemental interrupt 1 IVG7 70 - - Softirq IVG14 - System Call -- - (lowest priority) IVG15 - - **********************************************************************/ - -#define SYS_IRQS 71 -#define NR_PERI_INTS 64 - -/* - * The ABSTRACT IRQ definitions - * the first seven of the following are fixed, - * the rest you change if you need to. - */ -/* IVG 0-6*/ -#define IRQ_EMU 0 /* Emulation */ -#define IRQ_RST 1 /* Reset */ -#define IRQ_NMI 2 /* Non Maskable Interrupt */ -#define IRQ_EVX 3 /* Exception */ -#define IRQ_UNUSED 4 /* Reserved interrupt */ -#define IRQ_HWERR 5 /* Hardware Error */ -#define IRQ_CORETMR 6 /* Core timer */ - -#define IVG_BASE 7 -/* IVG 7 */ -#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */ -#define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */ -#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */ -#define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */ -#define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */ -#define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */ -#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */ -#define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */ -#define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */ -#define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */ -#define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */ -#define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */ -#define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed Interrupt */ -/* IVG 8 */ -#define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */ -#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ -#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ -#define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */ -#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */ -#define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */ -#define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */ -#define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */ -#define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */ -#define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */ -#define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */ -#define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */ -#define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */ -#define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */ -#define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */ -/* IVG 9 */ -#define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */ -#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */ -#define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */ -#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */ -#define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */ -#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */ -#define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */ -#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */ -#define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */ -#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */ -#define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */ -#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */ -#define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */ -#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */ -#define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */ -#define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */ -#define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */ -#define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */ -#define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */ -/* IVG 10 */ -#define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */ -#define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */ -#define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */ -#define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */ -#define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */ -#define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */ -#define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */ -#define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */ -#define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */ -#define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */ -#define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */ -#define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */ -/* IVG 11 */ -#define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */ -#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */ -#define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */ -#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */ -#define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */ -#define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */ -#define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */ -#define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */ -/* IVG 8 */ -#define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */ -#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */ +#include <mach-common/irq.h> + +#define NR_PERI_INTS (2 * 32) + +#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ +#define IRQ_DMA1_ERROR BFIN_IRQ(1) /* DMA1 Error (general) */ +#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */ +#define IRQ_DMA2_ERROR BFIN_IRQ(2) /* DMA2 Error (general) */ +#define IRQ_IMDMA_ERROR BFIN_IRQ(3) /* IMDMA Error Interrupt */ +#define IRQ_PPI1_ERROR BFIN_IRQ(4) /* PPI1 Error Interrupt */ +#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */ +#define IRQ_PPI2_ERROR BFIN_IRQ(5) /* PPI2 Error Interrupt */ +#define IRQ_SPORT0_ERROR BFIN_IRQ(6) /* SPORT0 Error Interrupt */ +#define IRQ_SPORT1_ERROR BFIN_IRQ(7) /* SPORT1 Error Interrupt */ +#define IRQ_SPI_ERROR BFIN_IRQ(8) /* SPI Error Interrupt */ +#define IRQ_UART_ERROR BFIN_IRQ(9) /* UART Error Interrupt */ +#define IRQ_RESERVED_ERROR BFIN_IRQ(10) /* Reversed */ +#define IRQ_DMA1_0 BFIN_IRQ(11) /* DMA1 0 Interrupt(PPI1) */ +#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ +#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ +#define IRQ_DMA1_1 BFIN_IRQ(12) /* DMA1 1 Interrupt(PPI2) */ +#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */ +#define IRQ_DMA1_2 BFIN_IRQ(13) /* DMA1 2 Interrupt */ +#define IRQ_DMA1_3 BFIN_IRQ(14) /* DMA1 3 Interrupt */ +#define IRQ_DMA1_4 BFIN_IRQ(15) /* DMA1 4 Interrupt */ +#define IRQ_DMA1_5 BFIN_IRQ(16) /* DMA1 5 Interrupt */ +#define IRQ_DMA1_6 BFIN_IRQ(17) /* DMA1 6 Interrupt */ +#define IRQ_DMA1_7 BFIN_IRQ(18) /* DMA1 7 Interrupt */ +#define IRQ_DMA1_8 BFIN_IRQ(19) /* DMA1 8 Interrupt */ +#define IRQ_DMA1_9 BFIN_IRQ(20) /* DMA1 9 Interrupt */ +#define IRQ_DMA1_10 BFIN_IRQ(21) /* DMA1 10 Interrupt */ +#define IRQ_DMA1_11 BFIN_IRQ(22) /* DMA1 11 Interrupt */ +#define IRQ_DMA2_0 BFIN_IRQ(23) /* DMA2 0 (SPORT0 RX) */ +#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */ +#define IRQ_DMA2_1 BFIN_IRQ(24) /* DMA2 1 (SPORT0 TX) */ +#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */ +#define IRQ_DMA2_2 BFIN_IRQ(25) /* DMA2 2 (SPORT1 RX) */ +#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */ +#define IRQ_DMA2_3 BFIN_IRQ(26) /* DMA2 3 (SPORT2 TX) */ +#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */ +#define IRQ_DMA2_4 BFIN_IRQ(27) /* DMA2 4 (SPI) */ +#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */ +#define IRQ_DMA2_5 BFIN_IRQ(28) /* DMA2 5 (UART RX) */ +#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */ +#define IRQ_DMA2_6 BFIN_IRQ(29) /* DMA2 6 (UART TX) */ +#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */ +#define IRQ_DMA2_7 BFIN_IRQ(30) /* DMA2 7 Interrupt */ +#define IRQ_DMA2_8 BFIN_IRQ(31) /* DMA2 8 Interrupt */ +#define IRQ_DMA2_9 BFIN_IRQ(32) /* DMA2 9 Interrupt */ +#define IRQ_DMA2_10 BFIN_IRQ(33) /* DMA2 10 Interrupt */ +#define IRQ_DMA2_11 BFIN_IRQ(34) /* DMA2 11 Interrupt */ +#define IRQ_TIMER0 BFIN_IRQ(35) /* TIMER 0 Interrupt */ +#define IRQ_TIMER1 BFIN_IRQ(36) /* TIMER 1 Interrupt */ +#define IRQ_TIMER2 BFIN_IRQ(37) /* TIMER 2 Interrupt */ +#define IRQ_TIMER3 BFIN_IRQ(38) /* TIMER 3 Interrupt */ +#define IRQ_TIMER4 BFIN_IRQ(39) /* TIMER 4 Interrupt */ +#define IRQ_TIMER5 BFIN_IRQ(40) /* TIMER 5 Interrupt */ +#define IRQ_TIMER6 BFIN_IRQ(41) /* TIMER 6 Interrupt */ +#define IRQ_TIMER7 BFIN_IRQ(42) /* TIMER 7 Interrupt */ +#define IRQ_TIMER8 BFIN_IRQ(43) /* TIMER 8 Interrupt */ +#define IRQ_TIMER9 BFIN_IRQ(44) /* TIMER 9 Interrupt */ +#define IRQ_TIMER10 BFIN_IRQ(45) /* TIMER 10 Interrupt */ +#define IRQ_TIMER11 BFIN_IRQ(46) /* TIMER 11 Interrupt */ +#define IRQ_PROG0_INTA BFIN_IRQ(47) /* Programmable Flags0 A (8) */ +#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */ +#define IRQ_PROG0_INTB BFIN_IRQ(48) /* Programmable Flags0 B (8) */ +#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */ +#define IRQ_PROG1_INTA BFIN_IRQ(49) /* Programmable Flags1 A (8) */ +#define IRQ_PROG1_INTB BFIN_IRQ(50) /* Programmable Flags1 B (8) */ +#define IRQ_PROG2_INTA BFIN_IRQ(51) /* Programmable Flags2 A (8) */ +#define IRQ_PROG2_INTB BFIN_IRQ(52) /* Programmable Flags2 B (8) */ +#define IRQ_DMA1_WRRD0 BFIN_IRQ(53) /* MDMA1 0 write/read INT */ +#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */ #define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0 -#define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */ -#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */ +#define IRQ_DMA1_WRRD1 BFIN_IRQ(54) /* MDMA1 1 write/read INT */ +#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */ #define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1 -/* IVG 9 */ -#define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */ +#define IRQ_DMA2_WRRD0 BFIN_IRQ(55) /* MDMA2 0 write/read INT */ #define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0 -#define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */ +#define IRQ_DMA2_WRRD1 BFIN_IRQ(56) /* MDMA2 1 write/read INT */ #define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1 -/* IVG 12 */ -#define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */ +#define IRQ_IMDMA_WRRD0 BFIN_IRQ(57) /* IMDMA 0 write/read INT */ #define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0 -#define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */ +#define IRQ_IMDMA_WRRD1 BFIN_IRQ(58) /* IMDMA 1 write/read INT */ #define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1 -/* IVG 13 */ -#define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */ -/* IVG 7 */ -#define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */ -#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */ -#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */ -#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */ +#define IRQ_WATCH BFIN_IRQ(59) /* Watch Dog Timer */ +#define IRQ_RESERVED_1 BFIN_IRQ(60) /* Reserved interrupt */ +#define IRQ_RESERVED_2 BFIN_IRQ(61) /* Reserved interrupt */ +#define IRQ_SUPPLE_0 BFIN_IRQ(62) /* Supplemental interrupt 0 */ +#define IRQ_SUPPLE_1 BFIN_IRQ(63) /* supplemental interrupt 1 */ + +#define SYS_IRQS 71 #define IRQ_PF0 73 #define IRQ_PF1 74 @@ -290,158 +151,86 @@ #define GPIO_IRQ_BASE IRQ_PF0 -#define NR_IRQS (IRQ_PF47 + 1) - -#define IVG7 7 -#define IVG8 8 -#define IVG9 9 -#define IVG10 10 -#define IVG11 11 -#define IVG12 12 -#define IVG13 13 -#define IVG14 14 -#define IVG15 15 - -/* - * DEFAULT PRIORITIES: - */ - -#define CONFIG_DEF_PLL_WAKEUP 7 -#define CONFIG_DEF_DMA1_ERROR 7 -#define CONFIG_DEF_DMA2_ERROR 7 -#define CONFIG_DEF_IMDMA_ERROR 7 -#define CONFIG_DEF_PPI1_ERROR 7 -#define CONFIG_DEF_PPI2_ERROR 7 -#define CONFIG_DEF_SPORT0_ERROR 7 -#define CONFIG_DEF_SPORT1_ERROR 7 -#define CONFIG_DEF_SPI_ERROR 7 -#define CONFIG_DEF_UART_ERROR 7 -#define CONFIG_DEF_RESERVED_ERROR 7 -#define CONFIG_DEF_DMA1_0 8 -#define CONFIG_DEF_DMA1_1 8 -#define CONFIG_DEF_DMA1_2 8 -#define CONFIG_DEF_DMA1_3 8 -#define CONFIG_DEF_DMA1_4 8 -#define CONFIG_DEF_DMA1_5 8 -#define CONFIG_DEF_DMA1_6 8 -#define CONFIG_DEF_DMA1_7 8 -#define CONFIG_DEF_DMA1_8 8 -#define CONFIG_DEF_DMA1_9 8 -#define CONFIG_DEF_DMA1_10 8 -#define CONFIG_DEF_DMA1_11 8 -#define CONFIG_DEF_DMA2_0 9 -#define CONFIG_DEF_DMA2_1 9 -#define CONFIG_DEF_DMA2_2 9 -#define CONFIG_DEF_DMA2_3 9 -#define CONFIG_DEF_DMA2_4 9 -#define CONFIG_DEF_DMA2_5 9 -#define CONFIG_DEF_DMA2_6 9 -#define CONFIG_DEF_DMA2_7 9 -#define CONFIG_DEF_DMA2_8 9 -#define CONFIG_DEF_DMA2_9 9 -#define CONFIG_DEF_DMA2_10 9 -#define CONFIG_DEF_DMA2_11 9 -#define CONFIG_DEF_TIMER0 10 -#define CONFIG_DEF_TIMER1 10 -#define CONFIG_DEF_TIMER2 10 -#define CONFIG_DEF_TIMER3 10 -#define CONFIG_DEF_TIMER4 10 -#define CONFIG_DEF_TIMER5 10 -#define CONFIG_DEF_TIMER6 10 -#define CONFIG_DEF_TIMER7 10 -#define CONFIG_DEF_TIMER8 10 -#define CONFIG_DEF_TIMER9 10 -#define CONFIG_DEF_TIMER10 10 -#define CONFIG_DEF_TIMER11 10 -#define CONFIG_DEF_PROG0_INTA 11 -#define CONFIG_DEF_PROG0_INTB 11 -#define CONFIG_DEF_PROG1_INTA 11 -#define CONFIG_DEF_PROG1_INTB 11 -#define CONFIG_DEF_PROG2_INTA 11 -#define CONFIG_DEF_PROG2_INTB 11 -#define CONFIG_DEF_DMA1_WRRD0 8 -#define CONFIG_DEF_DMA1_WRRD1 8 -#define CONFIG_DEF_DMA2_WRRD0 9 -#define CONFIG_DEF_DMA2_WRRD1 9 -#define CONFIG_DEF_IMDMA_WRRD0 12 -#define CONFIG_DEF_IMDMA_WRRD1 12 -#define CONFIG_DEF_WATCH 13 -#define CONFIG_DEF_RESERVED_1 7 -#define CONFIG_DEF_RESERVED_2 7 -#define CONFIG_DEF_SUPPLE_0 7 -#define CONFIG_DEF_SUPPLE_1 7 +#define NR_MACH_IRQS (IRQ_PF47 + 1) /* IAR0 BIT FIELDS */ -#define IRQ_PLL_WAKEUP_POS 0 -#define IRQ_DMA1_ERROR_POS 4 -#define IRQ_DMA2_ERROR_POS 8 -#define IRQ_IMDMA_ERROR_POS 12 -#define IRQ_PPI0_ERROR_POS 16 -#define IRQ_PPI1_ERROR_POS 20 -#define IRQ_SPORT0_ERROR_POS 24 -#define IRQ_SPORT1_ERROR_POS 28 +#define IRQ_PLL_WAKEUP_POS 0 +#define IRQ_DMA1_ERROR_POS 4 +#define IRQ_DMA2_ERROR_POS 8 +#define IRQ_IMDMA_ERROR_POS 12 +#define IRQ_PPI0_ERROR_POS 16 +#define IRQ_PPI1_ERROR_POS 20 +#define IRQ_SPORT0_ERROR_POS 24 +#define IRQ_SPORT1_ERROR_POS 28 + /* IAR1 BIT FIELDS */ -#define IRQ_SPI_ERROR_POS 0 -#define IRQ_UART_ERROR_POS 4 -#define IRQ_RESERVED_ERROR_POS 8 -#define IRQ_DMA1_0_POS 12 -#define IRQ_DMA1_1_POS 16 -#define IRQ_DMA1_2_POS 20 -#define IRQ_DMA1_3_POS 24 -#define IRQ_DMA1_4_POS 28 +#define IRQ_SPI_ERROR_POS 0 +#define IRQ_UART_ERROR_POS 4 +#define IRQ_RESERVED_ERROR_POS 8 +#define IRQ_DMA1_0_POS 12 +#define IRQ_DMA1_1_POS 16 +#define IRQ_DMA1_2_POS 20 +#define IRQ_DMA1_3_POS 24 +#define IRQ_DMA1_4_POS 28 + /* IAR2 BIT FIELDS */ -#define IRQ_DMA1_5_POS 0 -#define IRQ_DMA1_6_POS 4 -#define IRQ_DMA1_7_POS 8 -#define IRQ_DMA1_8_POS 12 -#define IRQ_DMA1_9_POS 16 -#define IRQ_DMA1_10_POS 20 -#define IRQ_DMA1_11_POS 24 -#define IRQ_DMA2_0_POS 28 +#define IRQ_DMA1_5_POS 0 +#define IRQ_DMA1_6_POS 4 +#define IRQ_DMA1_7_POS 8 +#define IRQ_DMA1_8_POS 12 +#define IRQ_DMA1_9_POS 16 +#define IRQ_DMA1_10_POS 20 +#define IRQ_DMA1_11_POS 24 +#define IRQ_DMA2_0_POS 28 + /* IAR3 BIT FIELDS */ -#define IRQ_DMA2_1_POS 0 -#define IRQ_DMA2_2_POS 4 -#define IRQ_DMA2_3_POS 8 -#define IRQ_DMA2_4_POS 12 -#define IRQ_DMA2_5_POS 16 -#define IRQ_DMA2_6_POS 20 -#define IRQ_DMA2_7_POS 24 -#define IRQ_DMA2_8_POS 28 +#define IRQ_DMA2_1_POS 0 +#define IRQ_DMA2_2_POS 4 +#define IRQ_DMA2_3_POS 8 +#define IRQ_DMA2_4_POS 12 +#define IRQ_DMA2_5_POS 16 +#define IRQ_DMA2_6_POS 20 +#define IRQ_DMA2_7_POS 24 +#define IRQ_DMA2_8_POS 28 + /* IAR4 BIT FIELDS */ -#define IRQ_DMA2_9_POS 0 -#define IRQ_DMA2_10_POS 4 -#define IRQ_DMA2_11_POS 8 -#define IRQ_TIMER0_POS 12 -#define IRQ_TIMER1_POS 16 -#define IRQ_TIMER2_POS 20 -#define IRQ_TIMER3_POS 24 -#define IRQ_TIMER4_POS 28 +#define IRQ_DMA2_9_POS 0 +#define IRQ_DMA2_10_POS 4 +#define IRQ_DMA2_11_POS 8 +#define IRQ_TIMER0_POS 12 +#define IRQ_TIMER1_POS 16 +#define IRQ_TIMER2_POS 20 +#define IRQ_TIMER3_POS 24 +#define IRQ_TIMER4_POS 28 + /* IAR5 BIT FIELDS */ -#define IRQ_TIMER5_POS 0 -#define IRQ_TIMER6_POS 4 -#define IRQ_TIMER7_POS 8 -#define IRQ_TIMER8_POS 12 -#define IRQ_TIMER9_POS 16 -#define IRQ_TIMER10_POS 20 -#define IRQ_TIMER11_POS 24 -#define IRQ_PROG0_INTA_POS 28 +#define IRQ_TIMER5_POS 0 +#define IRQ_TIMER6_POS 4 +#define IRQ_TIMER7_POS 8 +#define IRQ_TIMER8_POS 12 +#define IRQ_TIMER9_POS 16 +#define IRQ_TIMER10_POS 20 +#define IRQ_TIMER11_POS 24 +#define IRQ_PROG0_INTA_POS 28 + /* IAR6 BIT FIELDS */ -#define IRQ_PROG0_INTB_POS 0 -#define IRQ_PROG1_INTA_POS 4 -#define IRQ_PROG1_INTB_POS 8 -#define IRQ_PROG2_INTA_POS 12 -#define IRQ_PROG2_INTB_POS 16 -#define IRQ_DMA1_WRRD0_POS 20 -#define IRQ_DMA1_WRRD1_POS 24 -#define IRQ_DMA2_WRRD0_POS 28 -/* IAR7 BIT FIELDS */ -#define IRQ_DMA2_WRRD1_POS 0 -#define IRQ_IMDMA_WRRD0_POS 4 -#define IRQ_IMDMA_WRRD1_POS 8 -#define IRQ_WDTIMER_POS 12 -#define IRQ_RESERVED_1_POS 16 -#define IRQ_RESERVED_2_POS 20 -#define IRQ_SUPPLE_0_POS 24 -#define IRQ_SUPPLE_1_POS 28 +#define IRQ_PROG0_INTB_POS 0 +#define IRQ_PROG1_INTA_POS 4 +#define IRQ_PROG1_INTB_POS 8 +#define IRQ_PROG2_INTA_POS 12 +#define IRQ_PROG2_INTB_POS 16 +#define IRQ_DMA1_WRRD0_POS 20 +#define IRQ_DMA1_WRRD1_POS 24 +#define IRQ_DMA2_WRRD0_POS 28 -#endif /* _BF561_IRQ_H_ */ +/* IAR7 BIT FIELDS */ +#define IRQ_DMA2_WRRD1_POS 0 +#define IRQ_IMDMA_WRRD0_POS 4 +#define IRQ_IMDMA_WRRD1_POS 8 +#define IRQ_WDTIMER_POS 12 +#define IRQ_RESERVED_1_POS 16 +#define IRQ_RESERVED_2_POS 20 +#define IRQ_SUPPLE_0_POS 24 +#define IRQ_SUPPLE_1_POS 28 + +#endif diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h index 419dffdc96e..4cc91995f78 100644 --- a/arch/blackfin/mach-bf561/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h @@ -1,13 +1,16 @@ /* - * Memory MAP - * Common header file for blackfin BF561 of processors. + * BF561 memory map + * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_561_H_ -#define _MEM_MAP_561_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ @@ -34,7 +37,6 @@ /* Memory Map for ADSP-BF561 processors */ -#ifdef CONFIG_BF561 #define COREA_L1_CODE_START 0xFFA00000 #define COREA_L1_DATA_A_START 0xFF800000 #define COREA_L1_DATA_B_START 0xFF900000 @@ -71,6 +73,28 @@ #define BFIN_DCACHESIZE (0*1024) #define BFIN_DSUPBANKS 0 #endif /*CONFIG_BFIN_DCACHE*/ + +/* + * If we are in SMP mode, then the cache settings of Core B will match + * the settings of Core A. If we aren't, then we assume Core B is not + * using any cache. This allows the rest of the kernel to work with + * the core in either mode as we are only loading user code into it and + * it is the user's problem to make sure they aren't doing something + * stupid there. + * + * Note that we treat the L1 code region as a contiguous blob to make + * the rest of the kernel simpler. Easier to check one region than a + * bunch of small ones. Again, possible misbehavior here is the fault + * of the user -- don't try to use memory that doesn't exist. + */ +#ifdef CONFIG_SMP +# define COREB_L1_CODE_LENGTH L1_CODE_LENGTH +# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH +# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH +#else +# define COREB_L1_CODE_LENGTH 0x14000 +# define COREB_L1_DATA_A_LENGTH 0x8000 +# define COREB_L1_DATA_B_LENGTH 0x8000 #endif /* Level 2 Memory */ @@ -82,10 +106,7 @@ #define COREA_L1_SCRATCH_START 0xFFB00000 #define COREB_L1_SCRATCH_START 0xFF700000 -#define L1_SCRATCH_START COREA_L1_SCRATCH_START -#define L1_SCRATCH_LENGTH 0x1000 - -#ifdef __ASSEMBLY__ +#ifdef CONFIG_SMP /* * The following macros both return the address of the PDA for the @@ -100,8 +121,7 @@ * is allowed to use the specified Dreg for determining the PDA * address to be returned into Preg. */ -#ifdef CONFIG_SMP -#define GET_PDA_SAFE(preg) \ +# define GET_PDA_SAFE(preg) \ preg.l = lo(DSPID); \ preg.h = hi(DSPID); \ preg = [preg]; \ @@ -137,7 +157,7 @@ preg = [preg]; \ 4: -#define GET_PDA(preg, dreg) \ +# define GET_PDA(preg, dreg) \ preg.l = lo(DSPID); \ preg.h = hi(DSPID); \ dreg = [preg]; \ @@ -148,21 +168,52 @@ preg = [preg]; \ 1: \ -#define GET_CPUID(preg, dreg) \ +# define GET_CPUID(preg, dreg) \ preg.l = lo(DSPID); \ preg.h = hi(DSPID); \ dreg = [preg]; \ dreg = ROT dreg BY -1; \ dreg = CC; -#else -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; - -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) +# ifndef __ASSEMBLY__ + +# include <asm/processor.h> + +static inline unsigned long get_l1_scratch_start_cpu(int cpu) +{ + return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; +} +static inline unsigned long get_l1_code_start_cpu(int cpu) +{ + return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START; +} +static inline unsigned long get_l1_data_a_start_cpu(int cpu) +{ + return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START; +} +static inline unsigned long get_l1_data_b_start_cpu(int cpu) +{ + return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START; +} + +static inline unsigned long get_l1_scratch_start(void) +{ + return get_l1_scratch_start_cpu(blackfin_core_id()); +} +static inline unsigned long get_l1_code_start(void) +{ + return get_l1_code_start_cpu(blackfin_core_id()); +} +static inline unsigned long get_l1_data_a_start(void) +{ + return get_l1_data_a_start_cpu(blackfin_core_id()); +} +static inline unsigned long get_l1_data_b_start(void) +{ + return get_l1_data_b_start_cpu(blackfin_core_id()); +} + +# endif /* __ASSEMBLY__ */ #endif /* CONFIG_SMP */ -#endif /* __ASSEMBLY__ */ - -#endif /* _MEM_MAP_533_H_ */ +#endif diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h new file mode 100644 index 00000000000..00bdacee9cc --- /dev/null +++ b/arch/blackfin/mach-bf561/include/mach/pll.h @@ -0,0 +1,56 @@ +/* + * Copyright 2005-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _MACH_PLL_H +#define _MACH_PLL_H + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_SMP + +#include <asm/blackfin.h> +#include <asm/irqflags.h> +#include <mach/irq.h> + +#define SUPPLE_0_WAKEUP ((IRQ_SUPPLE_0 - (IRQ_CORETMR + 1)) % 32) +#define SUPPLE_1_WAKEUP ((IRQ_SUPPLE_1 - (IRQ_CORETMR + 1)) % 32) + +static inline void +bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2) +{ + unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0); + + bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0); + bfin_write32(SIC_IWR1 + SICA_SICB_OFF, iwr1); +} +#define bfin_iwr_restore bfin_iwr_restore + +static inline void +bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2, + unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2) +{ + unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0); + + *iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF); + *iwr1 = bfin_read32(SIC_IWR1 + SICA_SICB_OFF); + bfin_iwr_restore(niwr0, niwr1, niwr2); +} +#define bfin_iwr_save bfin_iwr_save + +static inline void +bfin_iwr_set_sup0(unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2) +{ + bfin_iwr_save(0, IWR_ENABLE(SUPPLE_0_WAKEUP) | + IWR_ENABLE(SUPPLE_1_WAKEUP), 0, iwr0, iwr1, iwr2); +} + +#endif + +#endif + +#include <mach-common/pll.h> + +#endif diff --git a/arch/blackfin/mach-bf561/include/mach/portmux.h b/arch/blackfin/mach-bf561/include/mach/portmux.h index 2e5ad6347de..2339ffd0dde 100644 --- a/arch/blackfin/mach-bf561/include/mach/portmux.h +++ b/arch/blackfin/mach-bf561/include/mach/portmux.h @@ -1,7 +1,13 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + #ifndef _MACH_PORTMUX_H_ #define _MACH_PORTMUX_H_ -#define MAX_RESOURCES MAX_BLACKFIN_GPIOS +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS #define P_PPI0_CLK (P_DONTCARE) #define P_PPI0_FS1 (P_DONTCARE) @@ -85,6 +91,7 @@ #define P_SPI0_MOSI (P_DONTCARE) #define P_SPI0_MISO (P_DONTCARE) #define P_SPI0_SCK (P_DONTCARE) +#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2 #define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 #endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/mach-bf561/include/mach/smp.h b/arch/blackfin/mach-bf561/include/mach/smp.h index f9e65ebe81b..346c60589be 100644 --- a/arch/blackfin/mach-bf561/include/mach/smp.h +++ b/arch/blackfin/mach-bf561/include/mach/smp.h @@ -1,6 +1,14 @@ +/* + * Copyright 2007-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + #ifndef _MACH_BF561_SMP #define _MACH_BF561_SMP +/* This header has to stand alone to avoid circular deps */ + struct task_struct; void platform_init_cpus(void); @@ -11,12 +19,14 @@ int platform_boot_secondary(unsigned int cpu, struct task_struct *idle); void platform_secondary_init(unsigned int cpu); -void platform_request_ipi(int (*handler)(int, void *)); +void platform_request_ipi(int irq, /*irq_handler_t*/ void *handler); + +void platform_send_ipi(cpumask_t callmap, int irq); -void platform_send_ipi(cpumask_t callmap); +void platform_send_ipi_cpu(unsigned int cpu, int irq); -void platform_send_ipi_cpu(unsigned int cpu); +void platform_clear_ipi(unsigned int cpu, int irq); -void platform_clear_ipi(unsigned int cpu); +void bfin_local_timer_setup(void); #endif /* !_MACH_BF561_SMP */ |