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-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h4
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF542.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF544.h32
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF547.h32
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF548.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF549.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h111
-rw-r--r--arch/blackfin/mach-bf548/include/mach/gpio.h10
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/portmux.h2
10 files changed, 11 insertions, 188 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index ac96ee83b00..098fad63e03 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -6,8 +6,7 @@
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
+ * Licensed under the Clear BSD license.
*/
/* This file should be up to date with:
@@ -297,5 +296,6 @@
#define ANOMALY_05000440 (0)
#define ANOMALY_05000475 (0)
#define ANOMALY_05000480 (0)
+#define ANOMALY_16000030 (0)
#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h
index 629bf216e2b..51161575a16 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF542.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF542.h
@@ -1,7 +1,7 @@
/*
* Copyright 2007-2010 Analog Devices Inc.
*
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF542_H
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
index bcccab36629..018ebfc27f5 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -1,7 +1,7 @@
/*
* Copyright 2007-2010 Analog Devices Inc.
*
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF544_H
@@ -601,36 +601,6 @@
#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
-/* Bit masks for HOST_CONTROL */
-
-#define HOST_EN 0x1 /* Host Enable */
-#define HOST_END 0x2 /* Host Endianess */
-#define DATA_SIZE 0x4 /* Data Size */
-#define HOST_RST 0x8 /* Host Reset */
-#define HRDY_OVR 0x20 /* Host Ready Override */
-#define INT_MODE 0x40 /* Interrupt Mode */
-#define BT_EN 0x80 /* Bus Timeout Enable */
-#define EHW 0x100 /* Enable Host Write */
-#define EHR 0x200 /* Enable Host Read */
-#define BDR 0x400 /* Burst DMA Requests */
-
-/* Bit masks for HOST_STATUS */
-
-#define DMA_READY 0x1 /* DMA Ready */
-#define FIFOFULL 0x2 /* FIFO Full */
-#define FIFOEMPTY 0x4 /* FIFO Empty */
-#define DMA_COMPLETE 0x8 /* DMA Complete */
-#define HSHK 0x10 /* Host Handshake */
-#define HSTIMEOUT 0x20 /* Host Timeout */
-#define HIRQ 0x40 /* Host Interrupt Request */
-#define ALLOW_CNFG 0x80 /* Allow New Configuration */
-#define DMA_DIR 0x100 /* DMA Direction */
-#define BTE 0x200 /* Bus Timeout Enabled */
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
-
/* Bit masks for TIMER_ENABLE1 */
#define TIMEN8 0x1 /* Timer 8 Enable */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index 1fa41ec03f3..d55dcc0f532 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -1,7 +1,7 @@
/*
* Copyright 2008-2010 Analog Devices Inc.
*
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF547_H
@@ -581,36 +581,6 @@
#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
-/* Bit masks for HOST_CONTROL */
-
-#define HOST_EN 0x1 /* Host Enable */
-#define HOST_END 0x2 /* Host Endianess */
-#define DATA_SIZE 0x4 /* Data Size */
-#define HOST_RST 0x8 /* Host Reset */
-#define HRDY_OVR 0x20 /* Host Ready Override */
-#define INT_MODE 0x40 /* Interrupt Mode */
-#define BT_EN 0x80 /* Bus Timeout Enable */
-#define EHW 0x100 /* Enable Host Write */
-#define EHR 0x200 /* Enable Host Read */
-#define BDR 0x400 /* Burst DMA Requests */
-
-/* Bit masks for HOST_STATUS */
-
-#define DMA_READY 0x1 /* DMA Ready */
-#define FIFOFULL 0x2 /* FIFO Full */
-#define FIFOEMPTY 0x4 /* FIFO Empty */
-#define DMA_COMPLETE 0x8 /* DMA Complete */
-#define HSHK 0x10 /* Host Handshake */
-#define HSTIMEOUT 0x20 /* Host Timeout */
-#define HIRQ 0x40 /* Host Interrupt Request */
-#define ALLOW_CNFG 0x80 /* Allow New Configuration */
-#define DMA_DIR 0x100 /* DMA Direction */
-#define BTE 0x200 /* Bus Timeout Enabled */
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
-
/* Bit masks for KPAD_CTL */
#define KPAD_EN 0x1 /* Keypad Enable */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h
index 3c7f1b69349..27f29481e28 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF548.h
@@ -1,7 +1,7 @@
/*
* Copyright 2007-2010 Analog Devices Inc.
*
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF548_H
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h
index 9a45cb6b30d..ac569fc1297 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF549.h
@@ -1,7 +1,7 @@
/*
* Copyright 2007-2010 Analog Devices Inc.
*
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF549_H
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 0867c2bedb4..8f6e1925779 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -1,7 +1,7 @@
/*
* Copyright 2007-2010 Analog Devices Inc.
*
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF54X_H
@@ -2062,115 +2062,6 @@
#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */
#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
-/* ************************************************ */
-/* The TWI bit masks fields are from the ADSP-BF538 */
-/* and they have not been verified as the final */
-/* ones for the Moab processors ... bz 1/19/2007 */
-/* ************************************************ */
-
-/* Bit masks for TWIx_CONTROL */
-
-#define PRESCALE 0x7f /* Prescale Value */
-#define TWI_ENA 0x80 /* TWI Enable */
-#define SCCB 0x200 /* Serial Camera Control Bus */
-
-/* Bit maskes for TWIx_CLKDIV */
-
-#define CLKLOW 0xff /* Clock Low */
-#define CLKHI 0xff00 /* Clock High */
-
-/* Bit maskes for TWIx_SLAVE_CTL */
-
-#define SEN 0x1 /* Slave Enable */
-#define STDVAL 0x4 /* Slave Transmit Data Valid */
-#define NAK 0x8 /* Not Acknowledge */
-#define GEN 0x10 /* General Call Enable */
-
-/* Bit maskes for TWIx_SLAVE_ADDR */
-
-#define SADDR 0x7f /* Slave Mode Address */
-
-/* Bit maskes for TWIx_SLAVE_STAT */
-
-#define SDIR 0x1 /* Slave Transfer Direction */
-#define GCALL 0x2 /* General Call */
-
-/* Bit maskes for TWIx_MASTER_CTL */
-
-#define MEN 0x1 /* Master Mode Enable */
-#define MDIR 0x4 /* Master Transfer Direction */
-#define FAST 0x8 /* Fast Mode */
-#define STOP 0x10 /* Issue Stop Condition */
-#define RSTART 0x20 /* Repeat Start */
-#define DCNT 0x3fc0 /* Data Transfer Count */
-#define SDAOVR 0x4000 /* Serial Data Override */
-#define SCLOVR 0x8000 /* Serial Clock Override */
-
-/* Bit maskes for TWIx_MASTER_ADDR */
-
-#define MADDR 0x7f /* Master Mode Address */
-
-/* Bit maskes for TWIx_MASTER_STAT */
-
-#define MPROG 0x1 /* Master Transfer in Progress */
-#define LOSTARB 0x2 /* Lost Arbitration */
-#define ANAK 0x4 /* Address Not Acknowledged */
-#define DNAK 0x8 /* Data Not Acknowledged */
-#define BUFRDERR 0x10 /* Buffer Read Error */
-#define BUFWRERR 0x20 /* Buffer Write Error */
-#define SDASEN 0x40 /* Serial Data Sense */
-#define SCLSEN 0x80 /* Serial Clock Sense */
-#define BUSBUSY 0x100 /* Bus Busy */
-
-/* Bit maskes for TWIx_FIFO_CTL */
-
-#define XMTFLUSH 0x1 /* Transmit Buffer Flush */
-#define RCVFLUSH 0x2 /* Receive Buffer Flush */
-#define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */
-#define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */
-
-/* Bit maskes for TWIx_FIFO_STAT */
-
-#define XMTSTAT 0x3 /* Transmit FIFO Status */
-#define RCVSTAT 0xc /* Receive FIFO Status */
-
-/* Bit maskes for TWIx_INT_MASK */
-
-#define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */
-#define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */
-#define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */
-#define SOVFM 0x8 /* Slave Overflow Interrupt Mask */
-#define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */
-#define MERRM 0x20 /* Master Transfer Error Interrupt Mask */
-#define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */
-#define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */
-
-/* Bit maskes for TWIx_INT_STAT */
-
-#define SINIT 0x1 /* Slave Transfer Initiated */
-#define SCOMP 0x2 /* Slave Transfer Complete */
-#define SERR 0x4 /* Slave Transfer Error */
-#define SOVF 0x8 /* Slave Overflow */
-#define MCOMP 0x10 /* Master Transfer Complete */
-#define MERR 0x20 /* Master Transfer Error */
-#define XMTSERV 0x40 /* Transmit FIFO Service */
-#define RCVSERV 0x80 /* Receive FIFO Service */
-
-/* Bit maskes for TWIx_XMT_DATA8 */
-
-#define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */
-
-/* Bit maskes for TWIx_XMT_DATA16 */
-
-#define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */
-
-/* Bit maskes for TWIx_RCV_DATA8 */
-
-#define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */
-
-/* Bit maskes for TWIx_RCV_DATA16 */
-
-#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
/* ******************************************* */
/* MULTI BIT MACRO ENUMERATIONS */
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
index 35c8ced4615..006da1edcf8 100644
--- a/arch/blackfin/mach-bf548/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf548/include/mach/gpio.h
@@ -171,6 +171,8 @@
#define MAX_BLACKFIN_GPIOS 160
#define BFIN_GPIO_PINT 1
+#define NR_PINT_SYS_IRQS 4
+#define NR_PINTS 160
#ifndef __ASSEMBLY__
@@ -192,14 +194,6 @@ struct gpio_port_t {
unsigned int port_mux;
};
-struct gpio_port_s {
- unsigned short fer;
- unsigned short data;
- unsigned short dir;
- unsigned short inen;
- unsigned int mux;
-};
-
#endif
#include <mach-common/ports-a.h>
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 10dc142c518..cf7cb725cfa 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -433,7 +433,7 @@
#include <linux/types.h>
/*
- * bfin pint registers layout
+ * gpio pint registers layout
*/
struct bfin_pint_regs {
u32 mask_set;
diff --git a/arch/blackfin/mach-bf548/include/mach/portmux.h b/arch/blackfin/mach-bf548/include/mach/portmux.h
index e2224620273..d9f8632d7d0 100644
--- a/arch/blackfin/mach-bf548/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf548/include/mach/portmux.h
@@ -7,8 +7,6 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-12-20 20:41:50 +0000