diff options
Diffstat (limited to 'arch/blackfin/mach-bf548/include/mach/defBF54x_base.h')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF54x_base.h | 1686 |
1 files changed, 12 insertions, 1674 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h index e022e896cb1..8f6e1925779 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h @@ -1,31 +1,7 @@ /* - * File: include/asm-blackfin/mach-bf548/defBF54x_base.h - * Based on: - * Author: + * Copyright 2007-2010 Analog Devices Inc. * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF54X_H @@ -59,6 +35,7 @@ /* SIC Registers */ +#define SIC_RVECT 0xffc00108 #define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */ #define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */ #define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */ @@ -129,15 +106,15 @@ #define TWI0_REGBASE 0xffc00700 #define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ #define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ -#define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */ +#define TWI0_SLAVE_CTL 0xffc00708 /* TWI Slave Mode Control Register */ #define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */ #define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */ -#define TWI0_MASTER_CTRL 0xffc00714 /* TWI Master Mode Control Register */ +#define TWI0_MASTER_CTL 0xffc00714 /* TWI Master Mode Control Register */ #define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */ #define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */ #define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */ #define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */ -#define TWI0_FIFO_CTRL 0xffc00728 /* TWI FIFO Control Register */ +#define TWI0_FIFO_CTL 0xffc00728 /* TWI FIFO Control Register */ #define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */ #define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */ #define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */ @@ -222,8 +199,8 @@ /* DMAC0 Registers */ -#define DMAC0_TCPER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */ -#define DMAC0_TCCNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */ +#define DMAC0_TC_PER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */ +#define DMAC0_TC_CNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */ /* DMA Channel 0 Registers */ @@ -712,8 +689,8 @@ /* DMAC1 Registers */ -#define DMAC1_TCPER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */ -#define DMAC1_TCCNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */ +#define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */ +#define DMAC1_TC_CNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */ /* DMA Channel 12 Registers */ @@ -1633,57 +1610,19 @@ #define PINT2 0x40000000 /* Pin Interrupt 2 */ #define PINT3 0x80000000 /* Pin Interrupt 3 */ -/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */ - -#define DMAEN 0x1 /* DMA Channel Enable */ -#define WNR 0x2 /* DMA Direction */ -#define WDSIZE_8 0x0 /* Transfer Word Size = 8 */ -#define WDSIZE_16 0x4 /* Transfer Word Size = 16 */ -#define WDSIZE_32 0x8 /* Transfer Word Size = 32 */ -#define DMA2D 0x10 /* DMA Mode */ -#define RESTART 0x20 /* Work Unit Transitions */ -#define DI_SEL 0x40 /* Data Interrupt Timing Select */ -#define DI_EN 0x80 /* Data Interrupt Enable */ - -#define NDSIZE 0xf00 /* Flex Descriptor Size */ -#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ -#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ -#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ -#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ -#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ -#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ -#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ -#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ -#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ -#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ - -#define DMAFLOW 0xf000 /* Next Operation */ -#define DMAFLOW_STOP 0x0000 /* Stop Mode */ -#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ -#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ -#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ -#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ - -/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ - -#define DMA_DONE 0x1 /* DMA Completion Interrupt Status */ -#define DMA_ERR 0x2 /* DMA Error Interrupt Status */ -#define DFETCH 0x4 /* DMA Descriptor Fetch */ -#define DMA_RUN 0x8 /* DMA Channel Running */ - /* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ #define CTYPE 0x40 /* DMA Channel Type */ #define PMAP 0xf000 /* Peripheral Mapped To This Channel */ -/* Bit masks for DMACx_TCPER */ +/* Bit masks for DMACx_TC_PER */ #define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */ #define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */ #define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */ #define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */ -/* Bit masks for DMACx_TCCNT */ +/* Bit masks for DMACx_TC_CNT */ #define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */ #define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */ @@ -1839,10 +1778,6 @@ #define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */ #define CORE_MERROR 0x80 /* Core Error (2nd) */ -/* Bit masks for EBIU_ERRADD */ - -#define ERROR_ADDRESS 0xffffffff /* Error Address */ - /* Bit masks for EBIU_RSTCTL */ #define DDRSRESET 0x1 /* DDR soft reset */ @@ -1851,98 +1786,6 @@ #define SRACK 0x10 /* Self-refresh acknowledge */ #define MDDRENABLE 0x20 /* Mobile DDR enable */ -/* Bit masks for EBIU_DDRBRC0 */ - -#define BRC0 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRBRC1 */ - -#define BRC1 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRBRC2 */ - -#define BRC2 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRBRC3 */ - -#define BRC3 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRBRC4 */ - -#define BRC4 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRBRC5 */ - -#define BRC5 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRBRC6 */ - -#define BRC6 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRBRC7 */ - -#define BRC7 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRBWC0 */ - -#define BWC0 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRBWC1 */ - -#define BWC1 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRBWC2 */ - -#define BWC2 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRBWC3 */ - -#define BWC3 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRBWC4 */ - -#define BWC4 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRBWC5 */ - -#define BWC5 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRBWC6 */ - -#define BWC6 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRBWC7 */ - -#define BWC7 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRACCT */ - -#define ACCT 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRTACT */ - -#define TECT 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRARCT */ - -#define ARCT 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRGC0 */ - -#define GC0 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRGC1 */ - -#define GC1 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRGC2 */ - -#define GC2 0xffffffff /* Count */ - -/* Bit masks for EBIU_DDRGC3 */ - -#define GC3 0xffffffff /* Count */ - /* Bit masks for EBIU_DDRMCEN */ #define B0WCENABLE 0x1 /* Bank 0 write count enable */ @@ -2116,138 +1959,6 @@ #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ -/* Bit masks for WDOG_CTL */ - -#define WDEV 0x6 /* Watchdog Event */ -#define WDEN 0xff0 /* Watchdog Enable */ -#define WDRO 0x8000 /* Watchdog Rolled Over */ - -/* Bit masks for CNT_CONFIG */ - -#define CNTE 0x1 /* Counter Enable */ -#define DEBE 0x2 /* Debounce Enable */ -#define CDGINV 0x10 /* CDG Pin Polarity Invert */ -#define CUDINV 0x20 /* CUD Pin Polarity Invert */ -#define CZMINV 0x40 /* CZM Pin Polarity Invert */ -#define CNTMODE 0x700 /* Counter Operating Mode */ -#define ZMZC 0x800 /* CZM Zeroes Counter Enable */ -#define BNDMODE 0x3000 /* Boundary register Mode */ -#define INPDIS 0x8000 /* CUG and CDG Input Disable */ - -/* Bit masks for CNT_IMASK */ - -#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ -#define UCIE 0x2 /* Up count Interrupt Enable */ -#define DCIE 0x4 /* Down count Interrupt Enable */ -#define MINCIE 0x8 /* Min Count Interrupt Enable */ -#define MAXCIE 0x10 /* Max Count Interrupt Enable */ -#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ -#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ -#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ -#define CZMIE 0x100 /* CZM Pin Interrupt Enable */ -#define CZMEIE 0x200 /* CZM Error Interrupt Enable */ -#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ - -/* Bit masks for CNT_STATUS */ - -#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ -#define UCII 0x2 /* Up count Interrupt Identifier */ -#define DCII 0x4 /* Down count Interrupt Identifier */ -#define MINCII 0x8 /* Min Count Interrupt Identifier */ -#define MAXCII 0x10 /* Max Count Interrupt Identifier */ -#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ -#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ -#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ -#define CZMII 0x100 /* CZM Pin Interrupt Identifier */ -#define CZMEII 0x200 /* CZM Error Interrupt Identifier */ -#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ - -/* Bit masks for CNT_COMMAND */ - -#define W1LCNT 0xf /* Load Counter Register */ -#define W1LMIN 0xf0 /* Load Min Register */ -#define W1LMAX 0xf00 /* Load Max Register */ -#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ - -/* Bit masks for CNT_DEBOUNCE */ - -#define DPRESCALE 0xf /* Load Counter Register */ - -/* Bit masks for RTC_STAT */ - -#define SECONDS 0x3f /* Seconds */ -#define MINUTES 0xfc0 /* Minutes */ -#define HOURS 0x1f000 /* Hours */ -#define DAY_COUNTER 0xfffe0000 /* Day Counter */ - -/* Bit masks for RTC_ICTL */ - -#define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */ -#define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */ -#define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */ -#define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */ -#define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */ -#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */ -#define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */ -#define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */ - -/* Bit masks for RTC_ISTAT */ - -#define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */ -#define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */ -#define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */ -#define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */ -#define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */ -#define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */ -#define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */ -#define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */ -#define WRITE_COMPLETE 0x8000 /* Write Complete */ - -/* Bit masks for RTC_SWCNT */ - -#define STOPWATCH_COUNT 0xffff /* Stopwatch Count */ - -/* Bit masks for RTC_ALARM */ - -#define SECONDS 0x3f /* Seconds */ -#define MINUTES 0xfc0 /* Minutes */ -#define HOURS 0x1f000 /* Hours */ -#define DAY 0xfffe0000 /* Day */ - -/* Bit masks for RTC_PREN */ - -#define PREN 0x1 /* Prescaler Enable */ - -/* Bit masks for OTP_CONTROL */ - -#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ -#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ -#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ -#define FWRTEST 0x2000 /* OTP/Fuse Write Test */ -#define FRDEN 0x4000 /* OTP/Fuse Read Enable */ -#define FWREN 0x8000 /* OTP/Fuse Write Enable */ - -/* Bit masks for OTP_BEN */ - -#define FBEN 0xffff /* OTP/Fuse Byte Enable */ - -/* Bit masks for OTP_STATUS */ - -#define FCOMP 0x1 /* OTP/Fuse Access Complete */ -#define FERROR 0x2 /* OTP/Fuse Access Error */ -#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ -#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ -#define FPGMEN 0x40 /* OTP/Fuse Program Enable */ - -/* Bit masks for OTP_TIMING */ - -#define USECDIV 0xff /* Micro Second Divider */ -#define READACC 0x7f00 /* Read Access Time */ -#define CPUMPRL 0x38000 /* Charge Pump Release Time */ -#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */ -#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */ -#define PGMTIME 0xff000000 /* Program Time */ - /* Bit masks for SECURE_SYSSWT */ #define EMUDABL 0x1 /* Emulation Disable. */ @@ -2276,26 +1987,6 @@ #define AFEXIT 0x10 /* Authentication Firmware Exit */ #define SECSTAT 0xe0 /* Secure Status */ -/* Bit masks for PLL_DIV */ - -#define CSEL 0x30 /* Core Select */ -#define SSEL 0xf /* System Select */ -#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ -#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ -#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ -#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ - -/* Bit masks for PLL_CTL */ - -#define MSEL 0x7e00 /* Multiplier Select */ -#define BYPASS 0x100 /* PLL Bypass Enable */ -#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */ -#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */ -#define PDWN 0x20 /* Power Down */ -#define STOPCK 0x8 /* Stop Clock */ -#define PLL_OFF 0x2 /* Disable PLL */ -#define DF 0x1 /* Divide Frequency */ - /* SWRST Masks */ #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ @@ -2303,791 +1994,6 @@ #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ -/* Bit masks for PLL_STAT */ - -#define PLL_LOCKED 0x20 /* PLL Locked Status */ -#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */ -#define FULL_ON 0x2 /* Full-On Mode */ -#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */ -#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */ -#define CANWS 0x800 /* CAN Wake-Up Status */ -#define USBWS 0x2000 /* USB Wake-Up Status */ -#define KPADWS 0x4000 /* Keypad Wake-Up Status */ -#define ROTWS 0x8000 /* Rotary Wake-Up Status */ -#define GPWS 0x1000 /* General-Purpose Wake-Up Status */ - -/* Bit masks for VR_CTL */ - -#define FREQ 0x3 /* Regulator Switching Frequency */ -#define GAIN 0xc /* Voltage Output Level Gain */ -#define VLEV 0xf0 /* Internal Voltage Level */ -#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */ -#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */ -#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */ -#define GPWE 0x400 /* General-Purpose Wake-Up Enable */ -#define USBWE 0x800 /* USB Wake-Up Enable */ -#define KPADWE 0x1000 /* Keypad Wake-Up Enable */ -#define ROTWE 0x2000 /* Rotary Wake-Up Enable */ - -#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ -#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ -#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ - -#define GAIN_5 0x0000 /* GAIN = 5*/ -#define GAIN_10 0x0004 /* GAIN = 1*/ -#define GAIN_20 0x0008 /* GAIN = 2*/ -#define GAIN_50 0x000C /* GAIN = 5*/ - -#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ -#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ -#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ -#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ -#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ -#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ -#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ -#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ -#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ -#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ - -/* Bit masks for NFC_CTL */ - -#define WR_DLY 0xf /* Write Strobe Delay */ -#define RD_DLY 0xf0 /* Read Strobe Delay */ -#define NWIDTH 0x100 /* NAND Data Width */ -#define PG_SIZE 0x200 /* Page Size */ - -/* Bit masks for NFC_STAT */ - -#define NBUSY 0x1 /* Not Busy */ -#define WB_FULL 0x2 /* Write Buffer Full */ -#define PG_WR_STAT 0x4 /* Page Write Pending */ -#define PG_RD_STAT 0x8 /* Page Read Pending */ -#define WB_EMPTY 0x10 /* Write Buffer Empty */ - -/* Bit masks for NFC_IRQSTAT */ - -#define NBUSYIRQ 0x1 /* Not Busy IRQ */ -#define WB_OVF 0x2 /* Write Buffer Overflow */ -#define WB_EDGE 0x4 /* Write Buffer Edge Detect */ -#define RD_RDY 0x8 /* Read Data Ready */ -#define WR_DONE 0x10 /* Page Write Done */ - -/* Bit masks for NFC_IRQMASK */ - -#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */ -#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */ -#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */ -#define MASK_RDRDY 0x8 /* Mask Read Data Ready */ -#define MASK_WRDONE 0x10 /* Mask Write Done */ - -/* Bit masks for NFC_RST */ - -#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */ - -/* Bit masks for NFC_PGCTL */ - -#define PG_RD_START 0x1 /* Page Read Start */ -#define PG_WR_START 0x2 /* Page Write Start */ - -/* Bit masks for NFC_ECC0 */ - -#define ECC0 0x7ff /* Parity Calculation Result0 */ - -/* Bit masks for NFC_ECC1 */ - -#define ECC1 0x7ff /* Parity Calculation Result1 */ - -/* Bit masks for NFC_ECC2 */ - -#define ECC2 0x7ff /* Parity Calculation Result2 */ - -/* Bit masks for NFC_ECC3 */ - -#define ECC3 0x7ff /* Parity Calculation Result3 */ - -/* Bit masks for NFC_COUNT */ - -#define ECCCNT 0x3ff /* Transfer Count */ - -/* Bit masks for CAN0_CONTROL */ - -#define SRS 0x1 /* Software Reset */ -#define DNM 0x2 /* DeviceNet Mode */ -#define ABO 0x4 /* Auto Bus On */ -#define WBA 0x10 /* Wakeup On CAN Bus Activity */ -#define SMR 0x20 /* Sleep Mode Request */ -#define CSR 0x40 /* CAN Suspend Mode Request */ -#define CCR 0x80 /* CAN Configuration Mode Request */ - -/* Bit masks for CAN0_STATUS */ - -#define WT 0x1 /* CAN Transmit Warning Flag */ -#define WR 0x2 /* CAN Receive Warning Flag */ -#define EP 0x4 /* CAN Error Passive Mode */ -#define EBO 0x8 /* CAN Error Bus Off Mode */ -#define CSA 0x40 /* CAN Suspend Mode Acknowledge */ -#define CCA 0x80 /* CAN Configuration Mode Acknowledge */ -#define MBPTR 0x1f00 /* Mailbox Pointer */ -#define TRM 0x4000 /* Transmit Mode Status */ -#define REC 0x8000 /* Receive Mode Status */ - -/* Bit masks for CAN0_DEBUG */ - -#define DEC 0x1 /* Disable Transmit/Receive Error Counters */ -#define DRI 0x2 /* Disable CANRX Input Pin */ -#define DTO 0x4 /* Disable CANTX Output Pin */ -#define DIL 0x8 /* Disable Internal Loop */ -#define MAA 0x10 /* Mode Auto-Acknowledge */ -#define MRB 0x20 /* Mode Read Back */ -#define CDE 0x8000 /* CAN Debug Mode Enable */ - -/* Bit masks for CAN0_CLOCK */ - -#define BRP 0x3ff /* CAN Bit Rate Prescaler */ - -/* Bit masks for CAN0_TIMING */ - -#define SJW 0x300 /* Synchronization Jump Width */ -#define SAM 0x80 /* Sampling */ -#define TSEG2 0x70 /* Time Segment 2 */ -#define TSEG1 0xf /* Time Segment 1 */ - -/* Bit masks for CAN0_INTR */ - -#define CANRX 0x80 /* Serial Input From Transceiver */ -#define CANTX 0x40 /* Serial Output To Transceiver */ -#define SMACK 0x8 /* Sleep Mode Acknowledge */ -#define GIRQ 0x4 /* Global Interrupt Request Status */ -#define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */ -#define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */ - -/* Bit masks for CAN0_GIM */ - -#define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */ -#define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */ -#define EPIM 0x4 /* Error Passive Interrupt Mask */ -#define BOIM 0x8 /* Bus Off Interrupt Mask */ -#define WUIM 0x10 /* Wakeup Interrupt Mask */ -#define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */ -#define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */ -#define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */ -#define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */ -#define ADIM 0x400 /* Access Denied Interrupt Mask */ - -/* Bit masks for CAN0_GIS */ - -#define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */ -#define EWRIS 0x2 /* Error Warning Receive Interrupt Status */ -#define EPIS 0x4 /* Error Passive Interrupt Status */ -#define BOIS 0x8 /* Bus Off Interrupt Status */ -#define WUIS 0x10 /* Wakeup Interrupt Status */ -#define UIAIS 0x20 /* Unimplemented Address Interrupt Status */ -#define AAIS 0x40 /* Abort Acknowledge Interrupt Status */ -#define RMLIS 0x80 /* Receive Message Lost Interrupt Status */ -#define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */ -#define ADIS 0x400 /* Access Denied Interrupt Status */ - -/* Bit masks for CAN0_GIF */ - -#define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */ -#define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */ -#define EPIF 0x4 /* Error Passive Interrupt Flag */ -#define BOIF 0x8 /* Bus Off Interrupt Flag */ -#define WUIF 0x10 /* Wakeup Interrupt Flag */ -#define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */ -#define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */ -#define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */ -#define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */ -#define ADIF 0x400 /* Access Denied Interrupt Flag */ - -/* Bit masks for CAN0_MBTD */ - -#define TDR 0x80 /* Temporary Disable Request */ -#define TDA 0x40 /* Temporary Disable Acknowledge */ -#define TDPTR 0x1f /* Temporary Disable Pointer */ - -/* Bit masks for CAN0_UCCNF */ - -#define UCCNF 0xf /* Universal Counter Configuration */ -#define UCRC 0x20 /* Universal Counter Reload/Clear */ -#define UCCT 0x40 /* Universal Counter CAN Trigger */ -#define UCE 0x80 /* Universal Counter Enable */ - -/* Bit masks for CAN0_UCCNT */ - -#define UCCNT 0xffff /* Universal Counter Count Value */ - -/* Bit masks for CAN0_UCRC */ - -#define UCVAL 0xffff /* Universal Counter Reload/Capture Value */ - -/* Bit masks for CAN0_CEC */ - -#define RXECNT 0xff /* Receive Error Counter */ -#define TXECNT 0xff00 /* Transmit Error Counter */ - -/* Bit masks for CAN0_ESR */ - -#define FER 0x80 /* Form Error */ -#define BEF 0x40 /* Bit Error Flag */ -#define SA0 0x20 /* Stuck At Dominant */ -#define CRCE 0x10 /* CRC Error */ -#define SER 0x8 /* Stuff Bit Error */ -#define ACKE 0x4 /* Acknowledge Error */ - -/* Bit masks for CAN0_EWR */ - -#define EWLTEC 0xff00 /* Transmit Error Warning Limit */ -#define EWLREC 0xff /* Receive Error Warning Limit */ - -/* Bit masks for CAN0_AMxx_H */ - -#define FDF 0x8000 /* Filter On Data Field */ -#define FMD 0x4000 /* Full Mask Data */ -#define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */ -#define BASEID 0x1ffc /* Base Identifier */ -#define EXTID_HI 0x3 /* Extended Identifier High Bits */ - -/* Bit masks for CAN0_AMxx_L */ - -#define EXTID_LO 0xffff /* Extended Identifier Low Bits */ -#define DFM 0xffff /* Data Field Mask */ - -/* Bit masks for CAN0_MBxx_ID1 */ - -#define AME 0x8000 /* Acceptance Mask Enable */ -#define RTR 0x4000 /* Remote Transmission Request */ -#define IDE 0x2000 /* Identifier Extension */ -#define BASEID 0x1ffc /* Base Identifier */ -#define EXTID_HI 0x3 /* Extended Identifier High Bits */ - -/* Bit masks for CAN0_MBxx_ID0 */ - -#define EXTID_LO 0xffff /* Extended Identifier Low Bits */ -#define DFM 0xffff /* Data Field Mask */ - -/* Bit masks for CAN0_MBxx_TIMESTAMP */ - -#define TSV 0xffff /* Time Stamp Value */ - -/* Bit masks for CAN0_MBxx_LENGTH */ - -#define DLC 0xf /* Data Length Code */ - -/* Bit masks for CAN0_MBxx_DATA3 */ - -#define CAN_BYTE0 0xff00 /* Data Field Byte 0 */ -#define CAN_BYTE1 0xff /* Data Field Byte 1 */ - -/* Bit masks for CAN0_MBxx_DATA2 */ - -#define CAN_BYTE2 0xff00 /* Data Field Byte 2 */ -#define CAN_BYTE3 0xff /* Data Field Byte 3 */ - -/* Bit masks for CAN0_MBxx_DATA1 */ - -#define CAN_BYTE4 0xff00 /* Data Field Byte 4 */ -#define CAN_BYTE5 0xff /* Data Field Byte 5 */ - -/* Bit masks for CAN0_MBxx_DATA0 */ - -#define CAN_BYTE6 0xff00 /* Data Field Byte 6 */ -#define CAN_BYTE7 0xff /* Data Field Byte 7 */ - -/* Bit masks for CAN0_MC1 */ - -#define MC0 0x1 /* Mailbox 0 Enable */ -#define MC1 0x2 /* Mailbox 1 Enable */ -#define MC2 0x4 /* Mailbox 2 Enable */ -#define MC3 0x8 /* Mailbox 3 Enable */ -#define MC4 0x10 /* Mailbox 4 Enable */ -#define MC5 0x20 /* Mailbox 5 Enable */ -#define MC6 0x40 /* Mailbox 6 Enable */ -#define MC7 0x80 /* Mailbox 7 Enable */ -#define MC8 0x100 /* Mailbox 8 Enable */ -#define MC9 0x200 /* Mailbox 9 Enable */ -#define MC10 0x400 /* Mailbox 10 Enable */ -#define MC11 0x800 /* Mailbox 11 Enable */ -#define MC12 0x1000 /* Mailbox 12 Enable */ -#define MC13 0x2000 /* Mailbox 13 Enable */ -#define MC14 0x4000 /* Mailbox 14 Enable */ -#define MC15 0x8000 /* Mailbox 15 Enable */ - -/* Bit masks for CAN0_MC2 */ - -#define MC16 0x1 /* Mailbox 16 Enable */ -#define MC17 0x2 /* Mailbox 17 Enable */ -#define MC18 0x4 /* Mailbox 18 Enable */ -#define MC19 0x8 /* Mailbox 19 Enable */ -#define MC20 0x10 /* Mailbox 20 Enable */ -#define MC21 0x20 /* Mailbox 21 Enable */ -#define MC22 0x40 /* Mailbox 22 Enable */ -#define MC23 0x80 /* Mailbox 23 Enable */ -#define MC24 0x100 /* Mailbox 24 Enable */ -#define MC25 0x200 /* Mailbox 25 Enable */ -#define MC26 0x400 /* Mailbox 26 Enable */ -#define MC27 0x800 /* Mailbox 27 Enable */ -#define MC28 0x1000 /* Mailbox 28 Enable */ -#define MC29 0x2000 /* Mailbox 29 Enable */ -#define MC30 0x4000 /* Mailbox 30 Enable */ -#define MC31 0x8000 /* Mailbox 31 Enable */ - -/* Bit masks for CAN0_MD1 */ - -#define MD0 0x1 /* Mailbox 0 Receive Enable */ -#define MD1 0x2 /* Mailbox 1 Receive Enable */ -#define MD2 0x4 /* Mailbox 2 Receive Enable */ -#define MD3 0x8 /* Mailbox 3 Receive Enable */ -#define MD4 0x10 /* Mailbox 4 Receive Enable */ -#define MD5 0x20 /* Mailbox 5 Receive Enable */ -#define MD6 0x40 /* Mailbox 6 Receive Enable */ -#define MD7 0x80 /* Mailbox 7 Receive Enable */ -#define MD8 0x100 /* Mailbox 8 Receive Enable */ -#define MD9 0x200 /* Mailbox 9 Receive Enable */ -#define MD10 0x400 /* Mailbox 10 Receive Enable */ -#define MD11 0x800 /* Mailbox 11 Receive Enable */ -#define MD12 0x1000 /* Mailbox 12 Receive Enable */ -#define MD13 0x2000 /* Mailbox 13 Receive Enable */ -#define MD14 0x4000 /* Mailbox 14 Receive Enable */ -#define MD15 0x8000 /* Mailbox 15 Receive Enable */ - -/* Bit masks for CAN0_MD2 */ - -#define MD16 0x1 /* Mailbox 16 Receive Enable */ -#define MD17 0x2 /* Mailbox 17 Receive Enable */ -#define MD18 0x4 /* Mailbox 18 Receive Enable */ -#define MD19 0x8 /* Mailbox 19 Receive Enable */ -#define MD20 0x10 /* Mailbox 20 Receive Enable */ -#define MD21 0x20 /* Mailbox 21 Receive Enable */ -#define MD22 0x40 /* Mailbox 22 Receive Enable */ -#define MD23 0x80 /* Mailbox 23 Receive Enable */ -#define MD24 0x100 /* Mailbox 24 Receive Enable */ -#define MD25 0x200 /* Mailbox 25 Receive Enable */ -#define MD26 0x400 /* Mailbox 26 Receive Enable */ -#define MD27 0x800 /* Mailbox 27 Receive Enable */ -#define MD28 0x1000 /* Mailbox 28 Receive Enable */ -#define MD29 0x2000 /* Mailbox 29 Receive Enable */ -#define MD30 0x4000 /* Mailbox 30 Receive Enable */ -#define MD31 0x8000 /* Mailbox 31 Receive Enable */ - -/* Bit masks for CAN0_RMP1 */ - -#define RMP0 0x1 /* Mailbox 0 Receive Message Pending */ -#define RMP1 0x2 /* Mailbox 1 Receive Message Pending */ -#define RMP2 0x4 /* Mailbox 2 Receive Message Pending */ -#define RMP3 0x8 /* Mailbox 3 Receive Message Pending */ -#define RMP4 0x10 /* Mailbox 4 Receive Message Pending */ -#define RMP5 0x20 /* Mailbox 5 Receive Message Pending */ -#define RMP6 0x40 /* Mailbox 6 Receive Message Pending */ -#define RMP7 0x80 /* Mailbox 7 Receive Message Pending */ -#define RMP8 0x100 /* Mailbox 8 Receive Message Pending */ -#define RMP9 0x200 /* Mailbox 9 Receive Message Pending */ -#define RMP10 0x400 /* Mailbox 10 Receive Message Pending */ -#define RMP11 0x800 /* Mailbox 11 Receive Message Pending */ -#define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */ -#define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */ -#define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */ -#define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */ - -/* Bit masks for CAN0_RMP2 */ - -#define RMP16 0x1 /* Mailbox 16 Receive Message Pending */ -#define RMP17 0x2 /* Mailbox 17 Receive Message Pending */ -#define RMP18 0x4 /* Mailbox 18 Receive Message Pending */ -#define RMP19 0x8 /* Mailbox 19 Receive Message Pending */ -#define RMP20 0x10 /* Mailbox 20 Receive Message Pending */ -#define RMP21 0x20 /* Mailbox 21 Receive Message Pending */ -#define RMP22 0x40 /* Mailbox 22 Receive Message Pending */ -#define RMP23 0x80 /* Mailbox 23 Receive Message Pending */ -#define RMP24 0x100 /* Mailbox 24 Receive Message Pending */ -#define RMP25 0x200 /* Mailbox 25 Receive Message Pending */ -#define RMP26 0x400 /* Mailbox 26 Receive Message Pending */ -#define RMP27 0x800 /* Mailbox 27 Receive Message Pending */ -#define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */ -#define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */ -#define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */ -#define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */ - -/* Bit masks for CAN0_RML1 */ - -#define RML0 0x1 /* Mailbox 0 Receive Message Lost */ -#define RML1 0x2 /* Mailbox 1 Receive Message Lost */ -#define RML2 0x4 /* Mailbox 2 Receive Message Lost */ -#define RML3 0x8 /* Mailbox 3 Receive Message Lost */ -#define RML4 0x10 /* Mailbox 4 Receive Message Lost */ -#define RML5 0x20 /* Mailbox 5 Receive Message Lost */ -#define RML6 0x40 /* Mailbox 6 Receive Message Lost */ -#define RML7 0x80 /* Mailbox 7 Receive Message Lost */ -#define RML8 0x100 /* Mailbox 8 Receive Message Lost */ -#define RML9 0x200 /* Mailbox 9 Receive Message Lost */ -#define RML10 0x400 /* Mailbox 10 Receive Message Lost */ -#define RML11 0x800 /* Mailbox 11 Receive Message Lost */ -#define RML12 0x1000 /* Mailbox 12 Receive Message Lost */ -#define RML13 0x2000 /* Mailbox 13 Receive Message Lost */ -#define RML14 0x4000 /* Mailbox 14 Receive Message Lost */ -#define RML15 0x8000 /* Mailbox 15 Receive Message Lost */ - -/* Bit masks for CAN0_RML2 */ - -#define RML16 0x1 /* Mailbox 16 Receive Message Lost */ -#define RML17 0x2 /* Mailbox 17 Receive Message Lost */ -#define RML18 0x4 /* Mailbox 18 Receive Message Lost */ -#define RML19 0x8 /* Mailbox 19 Receive Message Lost */ -#define RML20 0x10 /* Mailbox 20 Receive Message Lost */ -#define RML21 0x20 /* Mailbox 21 Receive Message Lost */ -#define RML22 0x40 /* Mailbox 22 Receive Message Lost */ -#define RML23 0x80 /* Mailbox 23 Receive Message Lost */ -#define RML24 0x100 /* Mailbox 24 Receive Message Lost */ -#define RML25 0x200 /* Mailbox 25 Receive Message Lost */ -#define RML26 0x400 /* Mailbox 26 Receive Message Lost */ -#define RML27 0x800 /* Mailbox 27 Receive Message Lost */ -#define RML28 0x1000 /* Mailbox 28 Receive Message Lost */ -#define RML29 0x2000 /* Mailbox 29 Receive Message Lost */ -#define RML30 0x4000 /* Mailbox 30 Receive Message Lost */ -#define RML31 0x8000 /* Mailbox 31 Receive Message Lost */ - -/* Bit masks for CAN0_OPSS1 */ - -#define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */ - -/* Bit masks for CAN0_OPSS2 */ - -#define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */ -#define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */ - -/* Bit masks for CAN0_TRS1 */ - -#define TRS0 0x1 /* Mailbox 0 Transmit Request Set */ -#define TRS1 0x2 /* Mailbox 1 Transmit Request Set */ -#define TRS2 0x4 /* Mailbox 2 Transmit Request Set */ -#define TRS3 0x8 /* Mailbox 3 Transmit Request Set */ -#define TRS4 0x10 /* Mailbox 4 Transmit Request Set */ -#define TRS5 0x20 /* Mailbox 5 Transmit Request Set */ -#define TRS6 0x40 /* Mailbox 6 Transmit Request Set */ -#define TRS7 0x80 /* Mailbox 7 Transmit Request Set */ -#define TRS8 0x100 /* Mailbox 8 Transmit Request Set */ -#define TRS9 0x200 /* Mailbox 9 Transmit Request Set */ -#define TRS10 0x400 /* Mailbox 10 Transmit Request Set */ -#define TRS11 0x800 /* Mailbox 11 Transmit Request Set */ -#define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */ -#define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */ -#define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */ -#define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */ - -/* Bit masks for CAN0_TRS2 */ - -#define TRS16 0x1 /* Mailbox 16 Transmit Request Set */ -#define TRS17 0x2 /* Mailbox 17 Transmit Request Set */ -#define TRS18 0x4 /* Mailbox 18 Transmit Request Set */ -#define TRS19 0x8 /* Mailbox 19 Transmit Request Set */ -#define TRS20 0x10 /* Mailbox 20 Transmit Request Set */ -#define TRS21 0x20 /* Mailbox 21 Transmit Request Set */ -#define TRS22 0x40 /* Mailbox 22 Transmit Request Set */ -#define TRS23 0x80 /* Mailbox 23 Transmit Request Set */ -#define TRS24 0x100 /* Mailbox 24 Transmit Request Set */ -#define TRS25 0x200 /* Mailbox 25 Transmit Request Set */ -#define TRS26 0x400 /* Mailbox 26 Transmit Request Set */ -#define TRS27 0x800 /* Mailbox 27 Transmit Request Set */ -#define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */ -#define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */ -#define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */ -#define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */ - -/* Bit masks for CAN0_TRR1 */ - -#define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */ -#define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */ -#define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */ -#define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */ -#define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */ -#define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */ -#define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */ -#define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */ -#define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */ -#define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */ -#define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */ -#define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */ -#define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */ -#define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */ -#define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */ -#define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */ - -/* Bit masks for CAN0_TRR2 */ - -#define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */ -#define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */ -#define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */ -#define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */ -#define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */ -#define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */ -#define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */ -#define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */ -#define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */ -#define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */ -#define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */ -#define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */ -#define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */ -#define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */ -#define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */ -#define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */ - -/* Bit masks for CAN0_AA1 */ - -#define AA0 0x1 /* Mailbox 0 Abort Acknowledge */ -#define AA1 0x2 /* Mailbox 1 Abort Acknowledge */ -#define AA2 0x4 /* Mailbox 2 Abort Acknowledge */ -#define AA3 0x8 /* Mailbox 3 Abort Acknowledge */ -#define AA4 0x10 /* Mailbox 4 Abort Acknowledge */ -#define AA5 0x20 /* Mailbox 5 Abort Acknowledge */ -#define AA6 0x40 /* Mailbox 6 Abort Acknowledge */ -#define AA7 0x80 /* Mailbox 7 Abort Acknowledge */ -#define AA8 0x100 /* Mailbox 8 Abort Acknowledge */ -#define AA9 0x200 /* Mailbox 9 Abort Acknowledge */ -#define AA10 0x400 /* Mailbox 10 Abort Acknowledge */ -#define AA11 0x800 /* Mailbox 11 Abort Acknowledge */ -#define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */ -#define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */ -#define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */ -#define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */ - -/* Bit masks for CAN0_AA2 */ - -#define AA16 0x1 /* Mailbox 16 Abort Acknowledge */ -#define AA17 0x2 /* Mailbox 17 Abort Acknowledge */ -#define AA18 0x4 /* Mailbox 18 Abort Acknowledge */ -#define AA19 0x8 /* Mailbox 19 Abort Acknowledge */ -#define AA20 0x10 /* Mailbox 20 Abort Acknowledge */ -#define AA21 0x20 /* Mailbox 21 Abort Acknowledge */ -#define AA22 0x40 /* Mailbox 22 Abort Acknowledge */ -#define AA23 0x80 /* Mailbox 23 Abort Acknowledge */ -#define AA24 0x100 /* Mailbox 24 Abort Acknowledge */ -#define AA25 0x200 /* Mailbox 25 Abort Acknowledge */ -#define AA26 0x400 /* Mailbox 26 Abort Acknowledge */ -#define AA27 0x800 /* Mailbox 27 Abort Acknowledge */ -#define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */ -#define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */ -#define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */ -#define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */ - -/* Bit masks for CAN0_TA1 */ - -#define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */ -#define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */ -#define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */ -#define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */ -#define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */ -#define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */ -#define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */ -#define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */ -#define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */ -#define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */ -#define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */ -#define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */ -#define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */ -#define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */ -#define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */ -#define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */ - -/* Bit masks for CAN0_TA2 */ - -#define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */ -#define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */ -#define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */ -#define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */ -#define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */ -#define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */ -#define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */ -#define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */ -#define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */ -#define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */ -#define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */ -#define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */ -#define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */ -#define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */ -#define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */ -#define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */ - -/* Bit masks for CAN0_RFH1 */ - -#define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */ -#define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */ -#define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */ -#define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */ -#define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */ -#define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */ -#define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */ -#define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */ -#define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */ -#define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */ -#define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */ -#define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */ -#define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */ -#define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */ -#define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */ -#define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */ - -/* Bit masks for CAN0_RFH2 */ - -#define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */ -#define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */ -#define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */ -#define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */ -#define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */ -#define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */ -#define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */ -#define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */ -#define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */ -#define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */ -#define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */ -#define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */ -#define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */ -#define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */ -#define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */ -#define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */ - -/* Bit masks for CAN0_MBIM1 */ - -#define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */ -#define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */ -#define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */ -#define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */ -#define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */ -#define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */ -#define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */ -#define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */ -#define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */ -#define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */ -#define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */ -#define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */ -#define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */ -#define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */ -#define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */ -#define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */ - -/* Bit masks for CAN0_MBIM2 */ - -#define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */ -#define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */ -#define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */ -#define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */ -#define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */ -#define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */ -#define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */ -#define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */ -#define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */ -#define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */ -#define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */ -#define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */ -#define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */ -#define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */ -#define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */ -#define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */ - -/* Bit masks for CAN0_MBTIF1 */ - -#define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */ -#define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */ -#define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */ -#define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */ -#define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */ -#define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */ -#define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */ -#define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */ -#define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */ -#define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */ -#define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */ -#define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */ -#define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */ -#define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */ -#define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */ -#define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */ - -/* Bit masks for CAN0_MBTIF2 */ - -#define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */ -#define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */ -#define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */ -#define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */ -#define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */ -#define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */ -#define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */ -#define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */ -#define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */ -#define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */ -#define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */ -#define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */ -#define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */ -#define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */ -#define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */ -#define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */ - -/* Bit masks for CAN0_MBRIF1 */ - -#define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */ -#define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */ -#define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */ -#define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */ -#define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */ -#define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */ -#define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */ -#define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */ -#define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */ -#define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */ -#define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */ -#define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */ -#define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */ -#define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */ -#define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */ -#define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */ - -/* Bit masks for CAN0_MBRIF2 */ - -#define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */ -#define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */ -#define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */ -#define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */ -#define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */ -#define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */ -#define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */ -#define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */ -#define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */ -#define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */ -#define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */ -#define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */ -#define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */ -#define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */ -#define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */ -#define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */ - /* Bit masks for EPPIx_STATUS */ #define CFIFO_ERR 0x1 /* Chroma FIFO Error */ @@ -3156,294 +2062,6 @@ #define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */ #define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */ -/* Bit masks for SPIx_BAUD */ - -#define SPI_BAUD 0xffff /* Baud Rate */ - -/* Bit masks for SPIx_CTL */ - -#define SPE 0x4000 /* SPI Enable */ -#define WOM 0x2000 /* Write Open Drain Master */ -#define MSTR 0x1000 /* Master Mode */ -#define CPOL 0x800 /* Clock Polarity */ -#define CPHA 0x400 /* Clock Phase */ -#define LSBF 0x200 /* LSB First */ -#define SIZE 0x100 /* Size of Words */ -#define EMISO 0x20 /* Enable MISO Output */ -#define PSSE 0x10 /* Slave-Select Enable */ -#define GM 0x8 /* Get More Data */ -#define SZ 0x4 /* Send Zero */ -#define TIMOD 0x3 /* Transfer Initiation Mode */ - -/* Bit masks for SPIx_FLG */ - -#define FLS1 0x2 /* Slave Select Enable 1 */ -#define FLS2 0x4 /* Slave Select Enable 2 */ -#define FLS3 0x8 /* Slave Select Enable 3 */ -#define FLG1 0x200 /* Slave Select Value 1 */ -#define FLG2 0x400 /* Slave Select Value 2 */ -#define FLG3 0x800 /* Slave Select Value 3 */ - -/* Bit masks for SPIx_STAT */ - -#define TXCOL 0x40 /* Transmit Collision Error */ -#define RXS 0x20 /* RDBR Data Buffer Status */ -#define RBSY 0x10 /* Receive Error */ -#define TXS 0x8 /* TDBR Data Buffer Status */ -#define TXE 0x4 /* Transmission Error */ -#define MODF 0x2 /* Mode Fault Error */ -#define SPIF 0x1 /* SPI Finished */ - -/* Bit masks for SPIx_TDBR */ - -#define TDBR 0xffff /* Transmit Data Buffer */ - -/* Bit masks for SPIx_RDBR */ - -#define RDBR 0xffff /* Receive Data Buffer */ - -/* Bit masks for SPIx_SHADOW */ - -#define SHADOW 0xffff /* RDBR Shadow */ - -/* ************************************************ */ -/* The TWI bit masks fields are from the ADSP-BF538 */ -/* and they have not been verified as the final */ -/* ones for the Moab processors ... bz 1/19/2007 */ -/* ************************************************ */ - -/* Bit masks for TWIx_CONTROL */ - -#define PRESCALE 0x7f /* Prescale Value */ -#define TWI_ENA 0x80 /* TWI Enable */ -#define SCCB 0x200 /* Serial Camera Control Bus */ - -/* Bit maskes for TWIx_CLKDIV */ - -#define CLKLOW 0xff /* Clock Low */ -#define CLKHI 0xff00 /* Clock High */ - -/* Bit maskes for TWIx_SLAVE_CTL */ - -#define SEN 0x1 /* Slave Enable */ -#define STDVAL 0x4 /* Slave Transmit Data Valid */ -#define NAK 0x8 /* Not Acknowledge */ -#define GEN 0x10 /* General Call Enable */ - -/* Bit maskes for TWIx_SLAVE_ADDR */ - -#define SADDR 0x7f /* Slave Mode Address */ - -/* Bit maskes for TWIx_SLAVE_STAT */ - -#define SDIR 0x1 /* Slave Transfer Direction */ -#define GCALL 0x2 /* General Call */ - -/* Bit maskes for TWIx_MASTER_CTL */ - -#define MEN 0x1 /* Master Mode Enable */ -#define MDIR 0x4 /* Master Transfer Direction */ -#define FAST 0x8 /* Fast Mode */ -#define STOP 0x10 /* Issue Stop Condition */ -#define RSTART 0x20 /* Repeat Start */ -#define DCNT 0x3fc0 /* Data Transfer Count */ -#define SDAOVR 0x4000 /* Serial Data Override */ -#define SCLOVR 0x8000 /* Serial Clock Override */ - -/* Bit maskes for TWIx_MASTER_ADDR */ - -#define MADDR 0x7f /* Master Mode Address */ - -/* Bit maskes for TWIx_MASTER_STAT */ - -#define MPROG 0x1 /* Master Transfer in Progress */ -#define LOSTARB 0x2 /* Lost Arbitration */ -#define ANAK 0x4 /* Address Not Acknowledged */ -#define DNAK 0x8 /* Data Not Acknowledged */ -#define BUFRDERR 0x10 /* Buffer Read Error */ -#define BUFWRERR 0x20 /* Buffer Write Error */ -#define SDASEN 0x40 /* Serial Data Sense */ -#define SCLSEN 0x80 /* Serial Clock Sense */ -#define BUSBUSY 0x100 /* Bus Busy */ - -/* Bit maskes for TWIx_FIFO_CTL */ - -#define XMTFLUSH 0x1 /* Transmit Buffer Flush */ -#define RCVFLUSH 0x2 /* Receive Buffer Flush */ -#define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */ -#define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */ - -/* Bit maskes for TWIx_FIFO_STAT */ - -#define XMTSTAT 0x3 /* Transmit FIFO Status */ -#define RCVSTAT 0xc /* Receive FIFO Status */ - -/* Bit maskes for TWIx_INT_MASK */ - -#define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */ -#define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */ -#define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */ -#define SOVFM 0x8 /* Slave Overflow Interrupt Mask */ -#define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */ -#define MERRM 0x20 /* Master Transfer Error Interrupt Mask */ -#define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */ -#define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */ - -/* Bit maskes for TWIx_INT_STAT */ - -#define SINIT 0x1 /* Slave Transfer Initiated */ -#define SCOMP 0x2 /* Slave Transfer Complete */ -#define SERR 0x4 /* Slave Transfer Error */ -#define SOVF 0x8 /* Slave Overflow */ -#define MCOMP 0x10 /* Master Transfer Complete */ -#define MERR 0x20 /* Master Transfer Error */ -#define XMTSERV 0x40 /* Transmit FIFO Service */ -#define RCVSERV 0x80 /* Receive FIFO Service */ - -/* Bit maskes for TWIx_XMT_DATA8 */ - -#define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */ - -/* Bit maskes for TWIx_XMT_DATA16 */ - -#define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */ - -/* Bit maskes for TWIx_RCV_DATA8 */ - -#define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */ - -/* Bit maskes for TWIx_RCV_DATA16 */ - -#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */ - -/* Bit masks for SPORTx_TCR1 */ - -#define TCKFE 0x4000 /* Clock Falling Edge Select */ -#define LATFS 0x2000 /* Late Transmit Frame Sync */ -#define LTFS 0x1000 /* Low Transmit Frame Sync Select */ -#define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */ -#define TFSR 0x400 /* Transmit Frame Sync Required Select */ -#define ITFS 0x200 /* Internal Transmit Frame Sync Select */ -#define TLSBIT 0x10 /* Transmit Bit Order */ -#define TDTYPE 0xc /* Data Formatting Type Select */ -#define ITCLK 0x2 /* Internal Transmit Clock Select */ -#define TSPEN 0x1 /* Transmit Enable */ - -/* Bit masks for SPORTx_TCR2 */ - -#define TRFST 0x400 /* Left/Right Order */ -#define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */ -#define TXSE 0x100 /* TxSEC Enable */ -#define SLEN_T 0x1f /* SPORT Word Length */ - -/* Bit masks for SPORTx_RCR1 */ - -#define RCKFE 0x4000 /* Clock Falling Edge Select */ -#define LARFS 0x2000 /* Late Receive Frame Sync */ -#define LRFS 0x1000 /* Low Receive Frame Sync Select */ -#define RFSR 0x400 /* Receive Frame Sync Required Select */ -#define IRFS 0x200 /* Internal Receive Frame Sync Select */ -#define RLSBIT 0x10 /* Receive Bit Order */ -#define RDTYPE 0xc /* Data Formatting Type Select */ -#define IRCLK 0x2 /* Internal Receive Clock Select */ -#define RSPEN 0x1 /* Receive Enable */ - -/* Bit masks for SPORTx_RCR2 */ - -#define RRFST 0x400 /* Left/Right Order */ -#define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */ -#define RXSE 0x100 /* RxSEC Enable */ -#define SLEN_R 0x1f /* SPORT Word Length */ - -/* Bit masks for SPORTx_STAT */ - -#define TXHRE 0x40 /* Transmit Hold Register Empty */ -#define TOVF 0x20 /* Sticky Transmit Overflow Status */ -#define TUVF 0x10 /* Sticky Transmit Underflow Status */ -#define TXF 0x8 /* Transmit FIFO Full Status */ -#define ROVF 0x4 /* Sticky Receive Overflow Status */ -#define RUVF 0x2 /* Sticky Receive Underflow Status */ -#define RXNE 0x1 /* Receive FIFO Not Empty Status */ - -/* Bit masks for SPORTx_MCMC1 */ - -#define SP_WSIZE 0xf000 /* Window Size */ -#define SP_WOFF 0x3ff /* Windows Offset */ - -/* Bit masks for SPORTx_MCMC2 */ - -#define MFD 0xf000 /* Multi channel Frame Delay */ -#define FSDR 0x80 /* Frame Sync to Data Relationship */ -#define MCMEN 0x10 /* Multi channel Frame Mode Enable */ -#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */ -#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */ -#define MCCRM 0x3 /* 2X Clock Recovery Mode */ - -/* Bit masks for SPORTx_CHNL */ - -#define CUR_CHNL 0x3ff /* Current Channel Indicator */ - -/* Bit masks for UARTx_LCR */ - -#if 0 -/* conflicts with legacy one in last section */ -#define WLS 0x3 /* Word Length Select */ -#endif -#define STB 0x4 /* Stop Bits */ -#define PEN 0x8 /* Parity Enable */ -#define EPS 0x10 /* Even Parity Select */ -#define STP 0x20 /* Sticky Parity */ -#define SB 0x40 /* Set Break */ - -/* Bit masks for UARTx_MCR */ - -#define XOFF 0x1 /* Transmitter Off */ -#define MRTS 0x2 /* Manual Request To Send */ -#define RFIT 0x4 /* Receive FIFO IRQ Threshold */ -#define RFRT 0x8 /* Receive FIFO RTS Threshold */ -#define LOOP_ENA 0x10 /* Loopback Mode Enable */ -#define FCPOL 0x20 /* Flow Control Pin Polarity */ -#define ARTS 0x40 /* Automatic Request To Send */ -#define ACTS 0x80 /* Automatic Clear To Send */ - -/* Bit masks for UARTx_LSR */ - -#define DR 0x1 /* Data Ready */ -#define OE 0x2 /* Overrun Error */ -#define PE 0x4 /* Parity Error */ -#define FE 0x8 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* THR Empty */ -#define TEMT 0x40 /* Transmitter Empty */ -#define TFI 0x80 /* Transmission Finished Indicator */ - -/* Bit masks for UARTx_MSR */ - -#define SCTS 0x1 /* Sticky CTS */ -#define CTS 0x10 /* Clear To Send */ -#define RFCS 0x20 /* Receive FIFO Count Status */ - -/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */ - -#define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */ -#define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */ -#define ELSI 0x4 /* Enable Receive Status Interrupt */ -#define EDSSI 0x8 /* Enable Modem Status Interrupt */ -#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */ -#define ETFI 0x20 /* Enable Transmission Finished Interrupt */ -#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ - -/* Bit masks for UARTx_GCTL */ - -#define UCEN 0x1 /* UART Enable */ -#define IREN 0x2 /* IrDA Mode Enable */ -#define TPOLC 0x4 /* IrDA TX Polarity Change */ -#define RPOLC 0x8 /* IrDA RX Polarity Change */ -#define FPE 0x10 /* Force Parity Error */ -#define FFE 0x20 /* Force Framing Error */ -#define EDBO 0x40 /* Enable Divide-by-One */ -#define EGLSI 0x80 /* Enable Global LS Interrupt */ - /* ******************************************* */ /* MULTI BIT MACRO ENUMERATIONS */ @@ -3456,46 +2074,12 @@ #define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */ #define BCODE_NOBOOT 0x0030 /* always perform full boot */ -/* CNT_COMMAND bit field options */ - -#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */ -#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */ -#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */ - -#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */ -#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */ -#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */ - -#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */ -#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */ -#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */ - -/* CNT_CONFIG bit field options */ - -#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */ -#define CNTMODE_BINENC 0x0100 /* binary encoder mode */ -#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */ -#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */ -#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */ - -#define BNDMODE_COMP 0x0000 /* boundary compare mode */ -#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */ -#define BNDMODE_CAPT 0x2000 /* boundary capture mode */ -#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */ - /* TMODE in TIMERx_CONFIG bit field options */ #define PWM_OUT 0x0001 #define WDTH_CAP 0x0002 #define EXT_CLK 0x0003 -/* UARTx_LCR bit field options */ - -#define WLS_5 0x0000 /* 5 data bits */ -#define WLS_6 0x0001 /* 6 data bits */ -#define WLS_7 0x0002 /* 7 data bits */ -#define WLS_8 0x0003 /* 8 data bits */ - /* PINTx Register Bit Definitions */ #define PIQ0 0x00000001 @@ -3538,240 +2122,6 @@ #define PIQ30 0x40000000 #define PIQ31 0x80000000 -/* PORT A Bit Definitions for the registers -PORTA, PORTA_SET, PORTA_CLEAR, -PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN, -PORTA_FER registers -*/ - -#define PA0 0x0001 -#define PA1 0x0002 -#define PA2 0x0004 -#define PA3 0x0008 -#define PA4 0x0010 -#define PA5 0x0020 -#define PA6 0x0040 -#define PA7 0x0080 -#define PA8 0x0100 -#define PA9 0x0200 -#define PA10 0x0400 -#define PA11 0x0800 -#define PA12 0x1000 -#define PA13 0x2000 -#define PA14 0x4000 -#define PA15 0x8000 - -/* PORT B Bit Definitions for the registers -PORTB, PORTB_SET, PORTB_CLEAR, -PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN, -PORTB_FER registers -*/ - -#define PB0 0x0001 -#define PB1 0x0002 -#define PB2 0x0004 -#define PB3 0x0008 -#define PB4 0x0010 -#define PB5 0x0020 -#define PB6 0x0040 -#define PB7 0x0080 -#define PB8 0x0100 -#define PB9 0x0200 -#define PB10 0x0400 -#define PB11 0x0800 -#define PB12 0x1000 -#define PB13 0x2000 -#define PB14 0x4000 - - -/* PORT C Bit Definitions for the registers -PORTC, PORTC_SET, PORTC_CLEAR, -PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN, -PORTC_FER registers -*/ - - -#define PC0 0x0001 -#define PC1 0x0002 -#define PC2 0x0004 -#define PC3 0x0008 -#define PC4 0x0010 -#define PC5 0x0020 -#define PC6 0x0040 -#define PC7 0x0080 -#define PC8 0x0100 -#define PC9 0x0200 -#define PC10 0x0400 -#define PC11 0x0800 -#define PC12 0x1000 -#define PC13 0x2000 - - -/* PORT D Bit Definitions for the registers -PORTD, PORTD_SET, PORTD_CLEAR, -PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN, -PORTD_FER registers -*/ - -#define PD0 0x0001 -#define PD1 0x0002 -#define PD2 0x0004 -#define PD3 0x0008 -#define PD4 0x0010 -#define PD5 0x0020 -#define PD6 0x0040 -#define PD7 0x0080 -#define PD8 0x0100 -#define PD9 0x0200 -#define PD10 0x0400 -#define PD11 0x0800 -#define PD12 0x1000 -#define PD13 0x2000 -#define PD14 0x4000 -#define PD15 0x8000 - -/* PORT E Bit Definitions for the registers -PORTE, PORTE_SET, PORTE_CLEAR, -PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN, -PORTE_FER registers -*/ - - -#define PE0 0x0001 -#define PE1 0x0002 -#define PE2 0x0004 -#define PE3 0x0008 -#define PE4 0x0010 -#define PE5 0x0020 -#define PE6 0x0040 -#define PE7 0x0080 -#define PE8 0x0100 -#define PE9 0x0200 -#define PE10 0x0400 -#define PE11 0x0800 -#define PE12 0x1000 -#define PE13 0x2000 -#define PE14 0x4000 -#define PE15 0x8000 - -/* PORT F Bit Definitions for the registers -PORTF, PORTF_SET, PORTF_CLEAR, -PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN, -PORTF_FER registers -*/ - - -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* PORT G Bit Definitions for the registers -PORTG, PORTG_SET, PORTG_CLEAR, -PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN, -PORTG_FER registers -*/ - - -#define PG0 0x0001 -#define PG1 0x0002 -#define PG2 0x0004 -#define PG3 0x0008 -#define PG4 0x0010 -#define PG5 0x0020 -#define PG6 0x0040 -#define PG7 0x0080 -#define PG8 0x0100 -#define PG9 0x0200 -#define PG10 0x0400 -#define PG11 0x0800 -#define PG12 0x1000 -#define PG13 0x2000 -#define PG14 0x4000 -#define PG15 0x8000 - -/* PORT H Bit Definitions for the registers -PORTH, PORTH_SET, PORTH_CLEAR, -PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN, -PORTH_FER registers -*/ - - -#define PH0 0x0001 -#define PH1 0x0002 -#define PH2 0x0004 -#define PH3 0x0008 -#define PH4 0x0010 -#define PH5 0x0020 -#define PH6 0x0040 -#define PH7 0x0080 -#define PH8 0x0100 -#define PH9 0x0200 -#define PH10 0x0400 -#define PH11 0x0800 -#define PH12 0x1000 -#define PH13 0x2000 - - -/* PORT I Bit Definitions for the registers -PORTI, PORTI_SET, PORTI_CLEAR, -PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN, -PORTI_FER registers -*/ - - -#define PI0 0x0001 -#define PI1 0x0002 -#define PI2 0x0004 -#define PI3 0x0008 -#define PI4 0x0010 -#define PI5 0x0020 -#define PI6 0x0040 -#define PI7 0x0080 -#define PI8 0x0100 -#define PI9 0x0200 -#define PI10 0x0400 -#define PI11 0x0800 -#define PI12 0x1000 -#define PI13 0x2000 -#define PI14 0x4000 -#define PI15 0x8000 - -/* PORT J Bit Definitions for the registers -PORTJ, PORTJ_SET, PORTJ_CLEAR, -PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN, -PORTJ_FER registers -*/ - - -#define PJ0 0x0001 -#define PJ1 0x0002 -#define PJ2 0x0004 -#define PJ3 0x0008 -#define PJ4 0x0010 -#define PJ5 0x0020 -#define PJ6 0x0040 -#define PJ7 0x0080 -#define PJ8 0x0100 -#define PJ9 0x0200 -#define PJ10 0x0400 -#define PJ11 0x0800 -#define PJ12 0x1000 -#define PJ13 0x2000 - - /* Port Muxing Bit Fields for PORTx_MUX Registers */ #define MUX0 0x00000003 @@ -3941,16 +2291,4 @@ PORTJ_FER registers #define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ #define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ - -/* for legacy compatibility */ - -#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ -#define W1LMAX_MAX W1LMAX_MIN -#define EBIU_AMCBCTL0 EBIU_AMBCTL0 -#define EBIU_AMCBCTL1 EBIU_AMBCTL1 -#define PINT0_IRQ PINT0_REQUEST -#define PINT1_IRQ PINT1_REQUEST -#define PINT2_IRQ PINT2_REQUEST -#define PINT3_IRQ PINT3_REQUEST - #endif /* _DEF_BF54X_H */ |