diff options
Diffstat (limited to 'arch/blackfin/mach-bf537')
26 files changed, 5014 insertions, 2861 deletions
diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig index bbc08fd4f12..08b2b343cce 100644 --- a/arch/blackfin/mach-bf537/Kconfig +++ b/arch/blackfin/mach-bf537/Kconfig @@ -14,8 +14,8 @@ config IRQ_DMA_ERROR int "IRQ_DMA_ERROR Generic" default 7 config IRQ_ERROR - int "IRQ_ERROR: CAN MAC SPORT0 SPORT1 SPI UART0 UART1" - default 7 + int "IRQ_ERROR: PPI CAN MAC SPORT0 SPORT1 SPI UART0 UART1" + default 11 config IRQ_RTC int "IRQ_RTC" default 8 @@ -66,6 +66,7 @@ config IRQ_MAC_TX default 11 config IRQ_TIMER0 int "IRQ_TIMER0" + default 7 if TICKSOURCE_GPTMR0 default 8 config IRQ_TIMER1 int "IRQ_TIMER1" diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig index 77c59da87e8..a44bf3a1816 100644 --- a/arch/blackfin/mach-bf537/boards/Kconfig +++ b/arch/blackfin/mach-bf537/boards/Kconfig @@ -9,11 +9,17 @@ config BFIN537_STAMP help BF537-STAMP board support. -config BFIN537_BLUETECHNIX_CM - bool "Bluetechnix CM-BF537" +config BFIN537_BLUETECHNIX_CM_E + bool "Bluetechnix CM-BF537E" depends on (BF537) help - CM-BF537 support for EVAL- and DEV-Board. + CM-BF537E support for EVAL- and DEV-Board. + +config BFIN537_BLUETECHNIX_CM_U + bool "Bluetechnix CM-BF537U" + depends on (BF537) + help + CM-BF537U support for EVAL- and DEV-Board. config BFIN537_BLUETECHNIX_TCM bool "Bluetechnix TCM-BF537" @@ -33,4 +39,10 @@ config CAMSIG_MINOTAUR help Board supply package for CSP Minotaur +config DNP5370 + bool "SSV Dil/NetPC DNP/5370" + depends on (BF537) + help + Board supply package for DNP/5370 DIL64 module + endchoice diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile index 68b98a7af6a..fe42258fe1f 100644 --- a/arch/blackfin/mach-bf537/boards/Makefile +++ b/arch/blackfin/mach-bf537/boards/Makefile @@ -3,7 +3,9 @@ # obj-$(CONFIG_BFIN537_STAMP) += stamp.o -obj-$(CONFIG_BFIN537_BLUETECHNIX_CM) += cm_bf537.o +obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_E) += cm_bf537e.o +obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_U) += cm_bf537u.o obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o obj-$(CONFIG_PNAV10) += pnav10.o obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o +obj-$(CONFIG_DNP5370) += dnp5370.o diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c new file mode 100644 index 00000000000..1e7290ef352 --- /dev/null +++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c @@ -0,0 +1,946 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * 2008-2009 Bluetechnix + * 2005 National ICT Australia (NICTA) + * Aidan Williams <aidan@nicta.com.au> + * + * Licensed under the GPL-2 or later. + */ + +#include <linux/device.h> +#include <linux/export.h> +#include <linux/etherdevice.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) +#include <linux/usb/isp1362.h> +#endif +#include <linux/ata_platform.h> +#include <linux/irq.h> +#include <linux/gpio.h> +#include <asm/dma.h> +#include <asm/bfin5xx_spi.h> +#include <asm/portmux.h> +#include <asm/dpmc.h> +#include <asm/bfin_sport.h> + +/* + * Name the Board for the /proc/cpuinfo + */ +const char bfin_board_name[] = "Bluetechnix CM BF537E"; + +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) +/* all SPI peripherals info goes here */ + +#if IS_ENABLED(CONFIG_MTD_M25P80) +static struct mtd_partition bfin_spi_flash_partitions[] = { + { + .name = "bootloader(spi)", + .size = 0x00020000, + .offset = 0, + .mask_flags = MTD_CAP_ROM + }, { + .name = "linux kernel(spi)", + .size = 0xe0000, + .offset = 0x20000 + }, { + .name = "file system(spi)", + .size = 0x700000, + .offset = 0x00100000, + } +}; + +static struct flash_platform_data bfin_spi_flash_data = { + .name = "m25p80", + .parts = bfin_spi_flash_partitions, + .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), + .type = "m25p64", +}; + +/* SPI flash chip (m25p64) */ +static struct bfin5xx_spi_chip spi_flash_chip_info = { + .enable_dma = 0, /* use dma transfer with this chip*/ +}; +#endif + +#if IS_ENABLED(CONFIG_MMC_SPI) +static struct bfin5xx_spi_chip mmc_spi_chip_info = { + .enable_dma = 0, +}; +#endif + +static struct spi_board_info bfin_spi_board_info[] __initdata = { +#if IS_ENABLED(CONFIG_MTD_M25P80) + { + /* the modalias must be the same as spi device driver name */ + .modalias = "m25p80", /* Name of spi_driver for this device */ + .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, /* Framework bus number */ + .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ + .platform_data = &bfin_spi_flash_data, + .controller_data = &spi_flash_chip_info, + .mode = SPI_MODE_3, + }, +#endif + +#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) + { + .modalias = "ad183x", + .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 4, + }, +#endif + +#if IS_ENABLED(CONFIG_MMC_SPI) + { + .modalias = "mmc_spi", + .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, + .controller_data = &mmc_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif +}; + +/* SPI (0) */ +static struct resource bfin_spi0_resource[] = { + [0] = { + .start = SPI0_REGBASE, + .end = SPI0_REGBASE + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = CH_SPI, + .end = CH_SPI, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = IRQ_SPI, + .end = IRQ_SPI, + .flags = IORESOURCE_IRQ, + }, +}; + +/* SPI controller data */ +static struct bfin5xx_spi_master bfin_spi0_info = { + .num_chipselect = 8, + .enable_dma = 1, /* master has the ability to do dma transfer */ + .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, +}; + +static struct platform_device bfin_spi0_device = { + .name = "bfin-spi", + .id = 0, /* Bus number */ + .num_resources = ARRAY_SIZE(bfin_spi0_resource), + .resource = bfin_spi0_resource, + .dev = { + .platform_data = &bfin_spi0_info, /* Passed to driver */ + }, +}; +#endif /* spi master and devices */ + +#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT) + +/* SPORT SPI controller data */ +static struct bfin5xx_spi_master bfin_sport_spi0_info = { + .num_chipselect = MAX_BLACKFIN_GPIOS, + .enable_dma = 0, /* master don't support DMA */ + .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI, + P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0}, +}; + +static struct resource bfin_sport_spi0_resource[] = { + [0] = { + .start = SPORT0_TCR1, + .end = SPORT0_TCR1 + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SPORT0_ERROR, + .end = IRQ_SPORT0_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_sport_spi0_device = { + .name = "bfin-sport-spi", + .id = 1, /* Bus number */ + .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource), + .resource = bfin_sport_spi0_resource, + .dev = { + .platform_data = &bfin_sport_spi0_info, /* Passed to driver */ + }, +}; + +static struct bfin5xx_spi_master bfin_sport_spi1_info = { + .num_chipselect = MAX_BLACKFIN_GPIOS, + .enable_dma = 0, /* master don't support DMA */ + .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI, + P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0}, +}; + +static struct resource bfin_sport_spi1_resource[] = { + [0] = { + .start = SPORT1_TCR1, + .end = SPORT1_TCR1 + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SPORT1_ERROR, + .end = IRQ_SPORT1_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_sport_spi1_device = { + .name = "bfin-sport-spi", + .id = 2, /* Bus number */ + .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource), + .resource = bfin_sport_spi1_resource, + .dev = { + .platform_data = &bfin_sport_spi1_info, /* Passed to driver */ + }, +}; + +#endif /* sport spi master and devices */ + +#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) +static struct platform_device rtc_device = { + .name = "rtc-bfin", + .id = -1, +}; +#endif + +#if IS_ENABLED(CONFIG_FB_HITACHI_TX09) +static struct platform_device hitachi_fb_device = { + .name = "hitachi-tx09", +}; +#endif + +#if IS_ENABLED(CONFIG_SMC91X) +#include <linux/smc91x.h> + +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, + .leda = RPC_LED_100_10, + .ledb = RPC_LED_TX_RX, +}; + +static struct resource smc91x_resources[] = { + { + .start = 0x20200300, + .end = 0x20200300 + 16, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_PF14, + .end = IRQ_PF14, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, + .dev = { + .platform_data = &smc91x_info, + }, +}; +#endif + +#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) +static struct resource isp1362_hcd_resources[] = { + { + .start = 0x20308000, + .end = 0x20308000, + .flags = IORESOURCE_MEM, + }, { + .start = 0x20308004, + .end = 0x20308004, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_PG15, + .end = IRQ_PG15, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, + }, +}; + +static struct isp1362_platform_data isp1362_priv = { + .sel15Kres = 1, + .clknotstop = 0, + .oc_enable = 0, + .int_act_high = 0, + .int_edge_triggered = 0, + .remote_wakeup_connected = 0, + .no_power_switching = 1, + .power_switching_mode = 0, +}; + +static struct platform_device isp1362_hcd_device = { + .name = "isp1362-hcd", + .id = 0, + .dev = { + .platform_data = &isp1362_priv, + }, + .num_resources = ARRAY_SIZE(isp1362_hcd_resources), + .resource = isp1362_hcd_resources, +}; +#endif + +#if IS_ENABLED(CONFIG_USB_NET2272) +static struct resource net2272_bfin_resources[] = { + { + .start = 0x20300000, + .end = 0x20300000 + 0x100, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_PG13, + .end = IRQ_PG13, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct platform_device net2272_bfin_device = { + .name = "net2272", + .id = -1, + .num_resources = ARRAY_SIZE(net2272_bfin_resources), + .resource = net2272_bfin_resources, +}; +#endif + +#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) +static struct mtd_partition cm_partitions[] = { + { + .name = "bootloader(nor)", + .size = 0x40000, + .offset = 0, + }, { + .name = "linux kernel(nor)", + .size = 0x100000, + .offset = MTDPART_OFS_APPEND, + }, { + .name = "file system(nor)", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct physmap_flash_data cm_flash_data = { + .width = 2, + .parts = cm_partitions, + .nr_parts = ARRAY_SIZE(cm_partitions), +}; + +static unsigned cm_flash_gpios[] = { GPIO_PF4 }; + +static struct resource cm_flash_resource[] = { + { + .name = "cfi_probe", + .start = 0x20000000, + .end = 0x201fffff, + .flags = IORESOURCE_MEM, + }, { + .start = (unsigned long)cm_flash_gpios, + .end = ARRAY_SIZE(cm_flash_gpios), + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device cm_flash_device = { + .name = "gpio-addr-flash", + .id = 0, + .dev = { + .platform_data = &cm_flash_data, + }, + .num_resources = ARRAY_SIZE(cm_flash_resource), + .resource = cm_flash_resource, +}; +#endif + +#if IS_ENABLED(CONFIG_SERIAL_BFIN) +#ifdef CONFIG_SERIAL_BFIN_UART0 +static struct resource bfin_uart0_resources[] = { + { + .start = UART0_THR, + .end = UART0_GCTL+2, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART0_TX, + .end = IRQ_UART0_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_ERROR, + .end = IRQ_UART0_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_TX, + .end = CH_UART0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX, + .flags = IORESOURCE_DMA, + }, +#ifdef CONFIG_BFIN_UART0_CTSRTS + { + /* + * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map. + */ + .start = -1, + .end = -1, + .flags = IORESOURCE_IO, + }, + { + /* + * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map. + */ + .start = -1, + .end = -1, + .flags = IORESOURCE_IO, + }, +#endif +}; + +static unsigned short bfin_uart0_peripherals[] = { + P_UART0_TX, P_UART0_RX, 0 +}; + +static struct platform_device bfin_uart0_device = { + .name = "bfin-uart", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_uart0_resources), + .resource = bfin_uart0_resources, + .dev = { + .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 +static struct resource bfin_uart1_resources[] = { + { + .start = UART1_THR, + .end = UART1_GCTL+2, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART1_TX, + .end = IRQ_UART1_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_ERROR, + .end = IRQ_UART1_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_TX, + .end = CH_UART1_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX, + .flags = IORESOURCE_DMA, + }, +#ifdef CONFIG_BFIN_UART1_CTSRTS + { + /* + * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map. + */ + .start = -1, + .end = -1, + .flags = IORESOURCE_IO, + }, + { + /* + * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map. + */ + .start = -1, + .end = -1, + .flags = IORESOURCE_IO, + }, +#endif +}; + +static unsigned short bfin_uart1_peripherals[] = { + P_UART1_TX, P_UART1_RX, 0 +}; + +static struct platform_device bfin_uart1_device = { + .name = "bfin-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_uart1_resources), + .resource = bfin_uart1_resources, + .dev = { + .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ + }, +}; +#endif +#endif + +#if IS_ENABLED(CONFIG_BFIN_SIR) +#ifdef CONFIG_BFIN_SIR0 +static struct resource bfin_sir0_resources[] = { + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX+1, + .flags = IORESOURCE_DMA, + }, +}; +static struct platform_device bfin_sir0_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir0_resources), + .resource = bfin_sir0_resources, +}; +#endif +#ifdef CONFIG_BFIN_SIR1 +static struct resource bfin_sir1_resources[] = { + { + .start = 0xFFC02000, + .end = 0xFFC020FF, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX+1, + .flags = IORESOURCE_DMA, + }, +}; +static struct platform_device bfin_sir1_device = { + .name = "bfin_sir", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_sir1_resources), + .resource = bfin_sir1_resources, +}; +#endif +#endif + +#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + +static struct resource bfin_twi0_resource[] = { + [0] = { + .start = TWI0_REGBASE, + .end = TWI0_REGBASE, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TWI, + .end = IRQ_TWI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device i2c_bfin_twi_device = { + .name = "i2c-bfin-twi", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_twi0_resource), + .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, +}; +#endif + +#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) \ +|| IS_ENABLED(CONFIG_BFIN_SPORT) +unsigned short bfin_sport0_peripherals[] = { + P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, + P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 +}; +#endif +#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART +static struct resource bfin_sport0_uart_resources[] = { + { + .start = SPORT0_TCR1, + .end = SPORT0_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT0_RX, + .end = IRQ_SPORT0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT0_ERROR, + .end = IRQ_SPORT0_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_sport0_uart_device = { + .name = "bfin-sport-uart", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), + .resource = bfin_sport0_uart_resources, + .dev = { + .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART +static struct resource bfin_sport1_uart_resources[] = { + { + .start = SPORT1_TCR1, + .end = SPORT1_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT1_RX, + .end = IRQ_SPORT1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT1_ERROR, + .end = IRQ_SPORT1_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static unsigned short bfin_sport1_peripherals[] = { + P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 +}; + +static struct platform_device bfin_sport1_uart_device = { + .name = "bfin-sport-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), + .resource = bfin_sport1_uart_resources, + .dev = { + .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ + }, +}; +#endif +#endif +#if IS_ENABLED(CONFIG_BFIN_SPORT) +static struct resource bfin_sport0_resources[] = { + { + .start = SPORT0_TCR1, + .end = SPORT0_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT0_RX, + .end = IRQ_SPORT0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT0_TX, + .end = IRQ_SPORT0_TX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT0_ERROR, + .end = IRQ_SPORT0_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_SPORT0_TX, + .end = CH_SPORT0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_SPORT0_RX, + .end = CH_SPORT0_RX, + .flags = IORESOURCE_DMA, + }, +}; +static struct platform_device bfin_sport0_device = { + .name = "bfin_sport_raw", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sport0_resources), + .resource = bfin_sport0_resources, + .dev = { + .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ + }, +}; +#endif + +#if IS_ENABLED(CONFIG_BFIN_MAC) +#include <linux/bfin_mac.h> +static const unsigned short bfin_mac_peripherals[] = P_MII0; + +static struct bfin_phydev_platform_data bfin_phydev_data[] = { + { + .addr = 1, + .irq = IRQ_MAC_PHYINT, + }, +}; + +static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { + .phydev_number = 1, + .phydev_data = bfin_phydev_data, + .phy_mode = PHY_INTERFACE_MODE_MII, + .mac_peripherals = bfin_mac_peripherals, +}; + +static struct platform_device bfin_mii_bus = { + .name = "bfin_mii_bus", + .dev = { + .platform_data = &bfin_mii_bus_data, + } +}; + +static struct platform_device bfin_mac_device = { + .name = "bfin_mac", + .dev = { + .platform_data = &bfin_mii_bus, + } +}; +#endif + +#if IS_ENABLED(CONFIG_PATA_PLATFORM) +#define PATA_INT IRQ_PF14 + +static struct pata_platform_info bfin_pata_platform_data = { + .ioport_shift = 2, + .irq_type = IRQF_TRIGGER_HIGH, +}; + +static struct resource bfin_pata_resources[] = { + { + .start = 0x2030C000, + .end = 0x2030C01F, + .flags = IORESOURCE_MEM, + }, + { + .start = 0x2030D018, + .end = 0x2030D01B, + .flags = IORESOURCE_MEM, + }, + { + .start = PATA_INT, + .end = PATA_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_pata_device = { + .name = "pata_platform", + .id = -1, + .num_resources = ARRAY_SIZE(bfin_pata_resources), + .resource = bfin_pata_resources, + .dev = { + .platform_data = &bfin_pata_platform_data, + } +}; +#endif + +static const unsigned int cclk_vlev_datasheet[] = +{ + VRPAIR(VLEV_085, 250000000), + VRPAIR(VLEV_090, 376000000), + VRPAIR(VLEV_095, 426000000), + VRPAIR(VLEV_100, 426000000), + VRPAIR(VLEV_105, 476000000), + VRPAIR(VLEV_110, 476000000), + VRPAIR(VLEV_115, 476000000), + VRPAIR(VLEV_120, 500000000), + VRPAIR(VLEV_125, 533000000), + VRPAIR(VLEV_130, 600000000), +}; + +static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { + .tuple_tab = cclk_vlev_datasheet, + .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), + .vr_settling_time = 25 /* us */, +}; + +static struct platform_device bfin_dpmc = { + .name = "bfin dpmc", + .dev = { + .platform_data = &bfin_dmpc_vreg_data, + }, +}; + +static struct platform_device *cm_bf537e_devices[] __initdata = { + + &bfin_dpmc, + +#if IS_ENABLED(CONFIG_BFIN_SPORT) + &bfin_sport0_device, +#endif + +#if IS_ENABLED(CONFIG_FB_HITACHI_TX09) + &hitachi_fb_device, +#endif + +#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) + &rtc_device, +#endif + +#if IS_ENABLED(CONFIG_SERIAL_BFIN) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif +#endif + +#if IS_ENABLED(CONFIG_BFIN_SIR) +#ifdef CONFIG_BFIN_SIR0 + &bfin_sir0_device, +#endif +#ifdef CONFIG_BFIN_SIR1 + &bfin_sir1_device, +#endif +#endif + +#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) + &i2c_bfin_twi_device, +#endif + +#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART + &bfin_sport0_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART + &bfin_sport1_uart_device, +#endif +#endif + +#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) + &isp1362_hcd_device, +#endif + +#if IS_ENABLED(CONFIG_SMC91X) + &smc91x_device, +#endif + +#if IS_ENABLED(CONFIG_BFIN_MAC) + &bfin_mii_bus, + &bfin_mac_device, +#endif + +#if IS_ENABLED(CONFIG_USB_NET2272) + &net2272_bfin_device, +#endif + +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) + &bfin_spi0_device, +#endif + +#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT) + &bfin_sport_spi0_device, + &bfin_sport_spi1_device, +#endif + +#if IS_ENABLED(CONFIG_PATA_PLATFORM) + &bfin_pata_device, +#endif + +#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) + &cm_flash_device, +#endif +}; + +static int __init net2272_init(void) +{ +#if IS_ENABLED(CONFIG_USB_NET2272) + int ret; + + ret = gpio_request(GPIO_PG14, "net2272"); + if (ret) + return ret; + + /* Reset USB Chip, PG14 */ + gpio_direction_output(GPIO_PG14, 0); + mdelay(2); + gpio_set_value(GPIO_PG14, 1); +#endif + + return 0; +} + +static int __init cm_bf537e_init(void) +{ + printk(KERN_INFO "%s(): registering device resources\n", __func__); + platform_add_devices(cm_bf537e_devices, ARRAY_SIZE(cm_bf537e_devices)); +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) + spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); +#endif + +#if IS_ENABLED(CONFIG_PATA_PLATFORM) + irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); +#endif + + if (net2272_init()) + pr_warning("unable to configure net2272; it probably won't work\n"); + + return 0; +} + +arch_initcall(cm_bf537e_init); + +static struct platform_device *cm_bf537e_early_devices[] __initdata = { +#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif +#endif + +#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART + &bfin_sport0_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART + &bfin_sport1_uart_device, +#endif +#endif +}; + +void __init native_machine_early_platform_add_devices(void) +{ + printk(KERN_INFO "register early platform devices\n"); + early_platform_add_devices(cm_bf537e_early_devices, + ARRAY_SIZE(cm_bf537e_early_devices)); +} + +int bfin_get_ether_addr(char *addr) +{ + return 1; +} +EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c index 41c75b9bfac..c7495dc7469 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c @@ -1,60 +1,42 @@ /* - * File: arch/blackfin/mach-bf537/boards/cm_bf537.c - * Based on: arch/blackfin/mach-bf533/boards/ezkit.c - * Author: Aidan Williams <aidan@nicta.com.au> + * Copyright 2004-2009 Analog Devices Inc. + * 2008-2009 Bluetechnix + * 2005 National ICT Australia (NICTA) + * Aidan Williams <aidan@nicta.com.au> * - * Created: 2005 - * Description: Board description file - * - * Modified: - * Copyright 2005 National ICT Australia (NICTA) - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Licensed under the GPL-2 or later. */ #include <linux/device.h> #include <linux/etherdevice.h> +#include <linux/export.h> #include <linux/platform_device.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> #include <linux/spi/spi.h> #include <linux/spi/flash.h> -#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) #include <linux/usb/isp1362.h> #endif #include <linux/ata_platform.h> #include <linux/irq.h> +#include <linux/gpio.h> #include <asm/dma.h> #include <asm/bfin5xx_spi.h> #include <asm/portmux.h> #include <asm/dpmc.h> +#include <linux/spi/mmc_spi.h> /* * Name the Board for the /proc/cpuinfo */ -const char bfin_board_name[] = "Bluetechnix CM BF537"; +const char bfin_board_name[] = "Bluetechnix CM BF537U"; -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) /* all SPI peripherals info goes here */ -#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) +#if IS_ENABLED(CONFIG_MTD_M25P80) static struct mtd_partition bfin_spi_flash_partitions[] = { { .name = "bootloader(spi)", @@ -82,41 +64,17 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, -}; -#endif - -#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) -static struct bfin5xx_spi_chip ad1836_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; -#endif - -#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) -static struct bfin5xx_spi_chip ad9960_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, }; #endif -#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) +#if IS_ENABLED(CONFIG_MMC_SPI) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) +#if IS_ENABLED(CONFIG_MTD_M25P80) { /* the modalias must be the same as spi device driver name */ .modalias = "m25p80", /* Name of spi_driver for this device */ @@ -129,38 +87,16 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) +#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - -#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) - { - .modalias = "ad1836-spi", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, - .controller_data = &ad1836_spi_chip_info, - }, -#endif - -#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) - { - .modalias = "ad9960-spi", - .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - .controller_data = &ad9960_spi_chip_info, + .chip_select = 4, }, #endif -#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) +#if IS_ENABLED(CONFIG_MMC_SPI) { .modalias = "mmc_spi", .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ @@ -182,8 +118,13 @@ static struct resource bfin_spi0_resource[] = { [1] = { .start = CH_SPI, .end = CH_SPI, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = IRQ_SPI, + .end = IRQ_SPI, .flags = IORESOURCE_IRQ, - } + }, }; /* SPI controller data */ @@ -204,20 +145,28 @@ static struct platform_device bfin_spi0_device = { }; #endif /* spi master and devices */ -#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) static struct platform_device rtc_device = { .name = "rtc-bfin", .id = -1, }; #endif -#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) +#if IS_ENABLED(CONFIG_FB_HITACHI_TX09) static struct platform_device hitachi_fb_device = { .name = "hitachi-tx09", }; #endif -#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) +#if IS_ENABLED(CONFIG_SMC91X) +#include <linux/smc91x.h> + +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, + .leda = RPC_LED_100_10, + .ledb = RPC_LED_TX_RX, +}; + static struct resource smc91x_resources[] = { { .start = 0x20200300, @@ -235,10 +184,13 @@ static struct platform_device smc91x_device = { .id = 0, .num_resources = ARRAY_SIZE(smc91x_resources), .resource = smc91x_resources, + .dev = { + .platform_data = &smc91x_info, + }, }; #endif -#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) static struct resource isp1362_hcd_resources[] = { { .start = 0x20308000, @@ -251,7 +203,7 @@ static struct resource isp1362_hcd_resources[] = { }, { .start = IRQ_PG15, .end = IRQ_PG15, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; @@ -277,7 +229,7 @@ static struct platform_device isp1362_hcd_device = { }; #endif -#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) +#if IS_ENABLED(CONFIG_USB_NET2272) static struct resource net2272_bfin_resources[] = { { .start = 0x20200000, @@ -298,20 +250,7 @@ static struct platform_device net2272_bfin_device = { }; #endif -static struct resource bfin_gpios_resources = { - .start = 0, - .end = MAX_BLACKFIN_GPIOS - 1, - .flags = IORESOURCE_IRQ, -}; - -static struct platform_device bfin_gpios_device = { - .name = "simple-gpio", - .id = -1, - .num_resources = 1, - .resource = &bfin_gpios_resources, -}; - -#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) +#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) static struct mtd_partition cm_partitions[] = { { .name = "bootloader(nor)", @@ -319,7 +258,7 @@ static struct mtd_partition cm_partitions[] = { .offset = 0, }, { .name = "linux kernel(nor)", - .size = 0xE0000, + .size = 0x100000, .offset = MTDPART_OFS_APPEND, }, { .name = "file system(nor)", @@ -334,7 +273,7 @@ static struct physmap_flash_data cm_flash_data = { .nr_parts = ARRAY_SIZE(cm_partitions), }; -static unsigned cm_flash_gpios[] = { GPIO_PF4 }; +static unsigned cm_flash_gpios[] = { GPIO_PH0 }; static struct resource cm_flash_resource[] = { { @@ -360,28 +299,106 @@ static struct platform_device cm_flash_device = { }; #endif -#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) -static struct resource bfin_uart_resources[] = { +#if IS_ENABLED(CONFIG_SERIAL_BFIN) +#ifdef CONFIG_SERIAL_BFIN_UART0 +static struct resource bfin_uart0_resources[] = { { - .start = 0xFFC00400, - .end = 0xFFC004FF, + .start = UART0_THR, + .end = UART0_GCTL+2, .flags = IORESOURCE_MEM, - }, { - .start = 0xFFC02000, - .end = 0xFFC020FF, + }, + { + .start = IRQ_UART0_TX, + .end = IRQ_UART0_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_ERROR, + .end = IRQ_UART0_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_TX, + .end = CH_UART0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static unsigned short bfin_uart0_peripherals[] = { + P_UART0_TX, P_UART0_RX, 0 +}; + +static struct platform_device bfin_uart0_device = { + .name = "bfin-uart", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_uart0_resources), + .resource = bfin_uart0_resources, + .dev = { + .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 +static struct resource bfin_uart1_resources[] = { + { + .start = UART1_THR, + .end = UART1_GCTL+2, .flags = IORESOURCE_MEM, }, + { + .start = IRQ_UART1_TX, + .end = IRQ_UART1_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_ERROR, + .end = IRQ_UART1_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_TX, + .end = CH_UART1_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static unsigned short bfin_uart1_peripherals[] = { + P_UART1_TX, P_UART1_RX, 0 }; -static struct platform_device bfin_uart_device = { +static struct platform_device bfin_uart1_device = { .name = "bfin-uart", .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart_resources), - .resource = bfin_uart_resources, + .num_resources = ARRAY_SIZE(bfin_uart1_resources), + .resource = bfin_uart1_resources, + .dev = { + .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ + }, }; #endif +#endif -#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +#if IS_ENABLED(CONFIG_BFIN_SIR) #ifdef CONFIG_BFIN_SIR0 static struct resource bfin_sir0_resources[] = { { @@ -434,7 +451,9 @@ static struct platform_device bfin_sir1_device = { #endif #endif -#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -453,38 +472,122 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif -#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) +#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART +static struct resource bfin_sport0_uart_resources[] = { + { + .start = SPORT0_TCR1, + .end = SPORT0_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT0_RX, + .end = IRQ_SPORT0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT0_ERROR, + .end = IRQ_SPORT0_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static unsigned short bfin_sport0_peripherals[] = { + P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 +}; + static struct platform_device bfin_sport0_uart_device = { .name = "bfin-sport-uart", .id = 0, + .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), + .resource = bfin_sport0_uart_resources, + .dev = { + .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART +static struct resource bfin_sport1_uart_resources[] = { + { + .start = SPORT1_TCR1, + .end = SPORT1_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT1_RX, + .end = IRQ_SPORT1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT1_ERROR, + .end = IRQ_SPORT1_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static unsigned short bfin_sport1_peripherals[] = { + P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { .name = "bfin-sport-uart", .id = 1, + .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), + .resource = bfin_sport1_uart_resources, + .dev = { + .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ + }, }; #endif +#endif + +#if IS_ENABLED(CONFIG_BFIN_MAC) +#include <linux/bfin_mac.h> +static const unsigned short bfin_mac_peripherals[] = P_MII0; + +static struct bfin_phydev_platform_data bfin_phydev_data[] = { + { + .addr = 1, + .irq = IRQ_MAC_PHYINT, + }, +}; + +static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { + .phydev_number = 1, + .phydev_data = bfin_phydev_data, + .phy_mode = PHY_INTERFACE_MODE_MII, + .mac_peripherals = bfin_mac_peripherals, +}; -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) static struct platform_device bfin_mii_bus = { .name = "bfin_mii_bus", + .dev = { + .platform_data = &bfin_mii_bus_data, + } }; static struct platform_device bfin_mac_device = { .name = "bfin_mac", - .dev.platform_data = &bfin_mii_bus, + .dev = { + .platform_data = &bfin_mii_bus, + } }; #endif -#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) +#if IS_ENABLED(CONFIG_PATA_PLATFORM) #define PATA_INT IRQ_PF14 static struct pata_platform_info bfin_pata_platform_data = { .ioport_shift = 2, - .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED, + .irq_type = IRQF_TRIGGER_HIGH, }; static struct resource bfin_pata_resources[] = { @@ -543,23 +646,28 @@ static struct platform_device bfin_dpmc = { }, }; -static struct platform_device *cm_bf537_devices[] __initdata = { +static struct platform_device *cm_bf537u_devices[] __initdata = { &bfin_dpmc, -#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) +#if IS_ENABLED(CONFIG_FB_HITACHI_TX09) &hitachi_fb_device, #endif -#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) &rtc_device, #endif -#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) - &bfin_uart_device, +#if IS_ENABLED(CONFIG_SERIAL_BFIN) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif #endif -#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +#if IS_ENABLED(CONFIG_BFIN_SIR) #ifdef CONFIG_BFIN_SIR0 &bfin_sir0_device, #endif @@ -568,66 +676,128 @@ static struct platform_device *cm_bf537_devices[] __initdata = { #endif #endif -#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) &i2c_bfin_twi_device, #endif -#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) +#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART &bfin_sport0_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART &bfin_sport1_uart_device, #endif +#endif -#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) &isp1362_hcd_device, #endif -#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) +#if IS_ENABLED(CONFIG_SMC91X) &smc91x_device, #endif -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) +#if IS_ENABLED(CONFIG_BFIN_MAC) &bfin_mii_bus, &bfin_mac_device, #endif -#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) +#if IS_ENABLED(CONFIG_USB_NET2272) &net2272_bfin_device, #endif -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) &bfin_spi0_device, #endif -#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) +#if IS_ENABLED(CONFIG_PATA_PLATFORM) &bfin_pata_device, #endif -#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) +#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) &cm_flash_device, #endif - - &bfin_gpios_device, }; -static int __init cm_bf537_init(void) +static int __init net2272_init(void) +{ +#if IS_ENABLED(CONFIG_USB_NET2272) + int ret; + + ret = gpio_request(GPIO_PH15, driver_name); + if (ret) + return ret; + + ret = gpio_request(GPIO_PH13, "net2272"); + if (ret) { + gpio_free(GPIO_PH15); + return ret; + } + + /* Set PH15 Low make /AMS2 work properly */ + gpio_direction_output(GPIO_PH15, 0); + + /* enable CLKBUF output */ + bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); + + /* Reset the USB chip */ + gpio_direction_output(GPIO_PH13, 0); + mdelay(2); + gpio_set_value(GPIO_PH13, 1); +#endif + + return 0; +} + +static int __init cm_bf537u_init(void) { printk(KERN_INFO "%s(): registering device resources\n", __func__); - platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices)); -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) + platform_add_devices(cm_bf537u_devices, ARRAY_SIZE(cm_bf537u_devices)); +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); #endif -#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) - irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; +#if IS_ENABLED(CONFIG_PATA_PLATFORM) + irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); #endif + + if (net2272_init()) + pr_warning("unable to configure net2272; it probably won't work\n"); + return 0; } -arch_initcall(cm_bf537_init); +arch_initcall(cm_bf537u_init); + +static struct platform_device *cm_bf537u_early_devices[] __initdata = { +#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif +#endif + +#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART + &bfin_sport0_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART + &bfin_sport1_uart_device, +#endif +#endif +}; + +void __init native_machine_early_platform_add_devices(void) +{ + printk(KERN_INFO "register early platform devices\n"); + early_platform_add_devices(cm_bf537u_early_devices, + ARRAY_SIZE(cm_bf537u_early_devices)); +} -void bfin_get_ether_addr(char *addr) +int bfin_get_ether_addr(char *addr) { - random_ether_addr(addr); - printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__); + return 1; } EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c new file mode 100644 index 00000000000..e79b3b810c3 --- /dev/null +++ b/arch/blackfin/mach-bf537/boards/dnp5370.c @@ -0,0 +1,413 @@ +/* + * This is the configuration for SSV Dil/NetPC DNP/5370 board. + * + * DIL module: http://www.dilnetpc.com/dnp0086.htm + * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm + * + * Copyright 2010 3ality Digital Systems + * Copyright 2005 National ICT Australia (NICTA) + * Copyright 2004-2006 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <linux/device.h> +#include <linux/export.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/plat-ram.h> +#include <linux/mtd/physmap.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/i2c.h> +#include <linux/spi/mmc_spi.h> +#include <linux/phy.h> +#include <asm/dma.h> +#include <asm/bfin5xx_spi.h> +#include <asm/reboot.h> +#include <asm/portmux.h> +#include <asm/dpmc.h> + +/* + * Name the Board for the /proc/cpuinfo + */ +const char bfin_board_name[] = "DNP/5370"; +#define FLASH_MAC 0x202f0000 +#define CONFIG_MTD_PHYSMAP_LEN 0x300000 + +#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) +static struct platform_device rtc_device = { + .name = "rtc-bfin", + .id = -1, +}; +#endif + +#if IS_ENABLED(CONFIG_BFIN_MAC) +#include <linux/bfin_mac.h> +static const unsigned short bfin_mac_peripherals[] = P_RMII0; + +static struct bfin_phydev_platform_data bfin_phydev_data[] = { + { + .addr = 1, + .irq = PHY_POLL, /* IRQ_MAC_PHYINT */ + }, +}; + +static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { + .phydev_number = 1, + .phydev_data = bfin_phydev_data, + .phy_mode = PHY_INTERFACE_MODE_RMII, + .mac_peripherals = bfin_mac_peripherals, +}; + +static struct platform_device bfin_mii_bus = { + .name = "bfin_mii_bus", + .dev = { + .platform_data = &bfin_mii_bus_data, + } +}; + +static struct platform_device bfin_mac_device = { + .name = "bfin_mac", + .dev = { + .platform_data = &bfin_mii_bus, + } +}; +#endif + +#if IS_ENABLED(CONFIG_MTD_PHYSMAP) +static struct mtd_partition asmb_flash_partitions[] = { + { + .name = "bootloader(nor)", + .size = 0x30000, + .offset = 0, + }, { + .name = "linux kernel and rootfs(nor)", + .size = 0x300000 - 0x30000 - 0x10000, + .offset = MTDPART_OFS_APPEND, + }, { + .name = "MAC address(nor)", + .size = 0x10000, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct physmap_flash_data asmb_flash_data = { + .width = 1, + .parts = asmb_flash_partitions, + .nr_parts = ARRAY_SIZE(asmb_flash_partitions), +}; + +static struct resource asmb_flash_resource = { + .start = 0x20000000, + .end = 0x202fffff, + .flags = IORESOURCE_MEM, +}; + +/* 4 MB NOR flash attached to async memory banks 0-2, + * therefore only 3 MB visible. + */ +static struct platform_device asmb_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &asmb_flash_data, + }, + .num_resources = 1, + .resource = &asmb_flash_resource, +}; +#endif + +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) + +#if IS_ENABLED(CONFIG_MMC_SPI) + +static struct bfin5xx_spi_chip mmc_spi_chip_info = { + .enable_dma = 0, /* use no dma transfer with this chip*/ +}; + +#endif + +#if IS_ENABLED(CONFIG_MTD_DATAFLASH) +/* This mapping is for at45db642 it has 1056 page size, + * partition size and offset should be page aligned + */ +static struct mtd_partition bfin_spi_dataflash_partitions[] = { + { + .name = "JFFS2 dataflash(nor)", +#ifdef CONFIG_MTD_PAGESIZE_1024 + .offset = 0x40000, + .size = 0x7C0000, +#else + .offset = 0x0, + .size = 0x840000, +#endif + } +}; + +static struct flash_platform_data bfin_spi_dataflash_data = { + .name = "mtd_dataflash", + .parts = bfin_spi_dataflash_partitions, + .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions), + .type = "mtd_dataflash", +}; + +static struct bfin5xx_spi_chip spi_dataflash_chip_info = { + .enable_dma = 0, /* use no dma transfer with this chip*/ +}; +#endif + +static struct spi_board_info bfin_spi_board_info[] __initdata = { +/* SD/MMC card reader at SPI bus */ +#if IS_ENABLED(CONFIG_MMC_SPI) + { + .modalias = "mmc_spi", + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 1, + .controller_data = &mmc_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif + +/* 8 Megabyte Atmel NOR flash chip at SPI bus */ +#if IS_ENABLED(CONFIG_MTD_DATAFLASH) + { + .modalias = "mtd_dataflash", + .max_speed_hz = 16700000, + .bus_num = 0, + .chip_select = 2, + .platform_data = &bfin_spi_dataflash_data, + .controller_data = &spi_dataflash_chip_info, + .mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */ + }, +#endif +}; + +/* SPI controller data */ +/* SPI (0) */ +static struct resource bfin_spi0_resource[] = { + [0] = { + .start = SPI0_REGBASE, + .end = SPI0_REGBASE + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = CH_SPI, + .end = CH_SPI, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = IRQ_SPI, + .end = IRQ_SPI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct bfin5xx_spi_master spi_bfin_master_info = { + .num_chipselect = 8, + .enable_dma = 1, /* master has the ability to do dma transfer */ + .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, +}; + +static struct platform_device spi_bfin_master_device = { + .name = "bfin-spi", + .id = 0, /* Bus number */ + .num_resources = ARRAY_SIZE(bfin_spi0_resource), + .resource = bfin_spi0_resource, + .dev = { + .platform_data = &spi_bfin_master_info, /* Passed to driver */ + }, +}; +#endif + +#if IS_ENABLED(CONFIG_SERIAL_BFIN) +#ifdef CONFIG_SERIAL_BFIN_UART0 +static struct resource bfin_uart0_resources[] = { + { + .start = UART0_THR, + .end = UART0_GCTL+2, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART0_TX, + .end = IRQ_UART0_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_ERROR, + .end = IRQ_UART0_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_TX, + .end = CH_UART0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static unsigned short bfin_uart0_peripherals[] = { + P_UART0_TX, P_UART0_RX, 0 +}; + +static struct platform_device bfin_uart0_device = { + .name = "bfin-uart", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_uart0_resources), + .resource = bfin_uart0_resources, + .dev = { + .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ + }, +}; +#endif + +#ifdef CONFIG_SERIAL_BFIN_UART1 +static struct resource bfin_uart1_resources[] = { + { + .start = UART1_THR, + .end = UART1_GCTL+2, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART1_TX, + .end = IRQ_UART1_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_ERROR, + .end = IRQ_UART1_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_TX, + .end = CH_UART1_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static unsigned short bfin_uart1_peripherals[] = { + P_UART1_TX, P_UART1_RX, 0 +}; + +static struct platform_device bfin_uart1_device = { + .name = "bfin-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_uart1_resources), + .resource = bfin_uart1_resources, + .dev = { + .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ + }, +}; +#endif +#endif + +#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + +static struct resource bfin_twi0_resource[] = { + [0] = { + .start = TWI0_REGBASE, + .end = TWI0_REGBASE + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TWI, + .end = IRQ_TWI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device i2c_bfin_twi_device = { + .name = "i2c-bfin-twi", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_twi0_resource), + .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, +}; +#endif + +static struct platform_device *dnp5370_devices[] __initdata = { + +#if IS_ENABLED(CONFIG_SERIAL_BFIN) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif +#endif + +#if IS_ENABLED(CONFIG_MTD_PHYSMAP) + &asmb_flash_device, +#endif + +#if IS_ENABLED(CONFIG_BFIN_MAC) + &bfin_mii_bus, + &bfin_mac_device, +#endif + +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) + &spi_bfin_master_device, +#endif + +#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) + &i2c_bfin_twi_device, +#endif + +#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) + &rtc_device, +#endif + +}; + +static int __init dnp5370_init(void) +{ + printk(KERN_INFO "DNP/5370: registering device resources\n"); + platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices)); + printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n", + ARRAY_SIZE(bfin_spi_board_info)); + spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); + printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC); + return 0; +} +arch_initcall(dnp5370_init); + +/* + * Currently the MAC address is saved in Flash by U-Boot + */ +int bfin_get_ether_addr(char *addr) +{ + *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC); + *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4); + return 0; +} +EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c index 3c159819e55..dd7bda07bf9 100644 --- a/arch/blackfin/mach-bf537/boards/minotaur.c +++ b/arch/blackfin/mach-bf537/boards/minotaur.c @@ -1,4 +1,10 @@ /* + * Copyright 2004-2009 Analog Devices Inc. + * 2008-2009 Cambridge Signal Processing + * 2005 National ICT Australia (NICTA) + * Aidan Williams <aidan@nicta.com.au> + * + * Licensed under the GPL-2 or later. */ #include <linux/device.h> @@ -7,7 +13,7 @@ #include <linux/mtd/partitions.h> #include <linux/spi/spi.h> #include <linux/spi/flash.h> -#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) #include <linux/usb/isp1362.h> #endif #include <linux/ata_platform.h> @@ -17,14 +23,15 @@ #include <asm/dma.h> #include <asm/bfin5xx_spi.h> #include <asm/reboot.h> +#include <asm/portmux.h> #include <linux/spi/ad7877.h> /* * Name the Board for the /proc/cpuinfo */ -char *bfin_board_name = "CamSig Minotaur BF537"; +const char bfin_board_name[] = "CamSig Minotaur BF537"; -#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) +#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA) static struct resource bfin_pcmcia_cf_resources[] = { { .start = 0x20310000, /* IO PORT */ @@ -53,25 +60,47 @@ static struct platform_device bfin_pcmcia_cf_device = { }; #endif -#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) static struct platform_device rtc_device = { .name = "rtc-bfin", .id = -1, }; #endif -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) +#if IS_ENABLED(CONFIG_BFIN_MAC) +#include <linux/bfin_mac.h> +static const unsigned short bfin_mac_peripherals[] = P_MII0; + +static struct bfin_phydev_platform_data bfin_phydev_data[] = { + { + .addr = 1, + .irq = IRQ_MAC_PHYINT, + }, +}; + +static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { + .phydev_number = 1, + .phydev_data = bfin_phydev_data, + .phy_mode = PHY_INTERFACE_MODE_MII, + .mac_peripherals = bfin_mac_peripherals, +}; + static struct platform_device bfin_mii_bus = { .name = "bfin_mii_bus", + .dev = { + .platform_data = &bfin_mii_bus_data, + } }; static struct platform_device bfin_mac_device = { .name = "bfin_mac", - .dev.platform_data = &bfin_mii_bus, + .dev = { + .platform_data = &bfin_mii_bus, + } }; #endif -#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) +#if IS_ENABLED(CONFIG_USB_NET2272) static struct resource net2272_bfin_resources[] = { { .start = 0x20300000, @@ -92,11 +121,10 @@ static struct platform_device net2272_bfin_device = { }; #endif -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) /* all SPI peripherals info goes here */ -#if defined(CONFIG_MTD_M25P80) \ - || defined(CONFIG_MTD_M25P80_MODULE) +#if IS_ENABLED(CONFIG_MTD_M25P80) /* Partition sizes */ #define FLASH_SIZE 0x00400000 @@ -130,20 +158,17 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, }; #endif -#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) +#if IS_ENABLED(CONFIG_MMC_SPI) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if defined(CONFIG_MTD_M25P80) \ - || defined(CONFIG_MTD_M25P80_MODULE) +#if IS_ENABLED(CONFIG_MTD_M25P80) { /* the modalias must be the same as spi device driver name */ .modalias = "m25p80", /* Name of spi_driver for this device */ @@ -156,7 +181,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) +#if IS_ENABLED(CONFIG_MMC_SPI) { .modalias = "mmc_spi", .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ @@ -184,6 +209,11 @@ static struct resource bfin_spi0_resource[] = { [1] = { .start = CH_SPI, .end = CH_SPI, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = IRQ_SPI, + .end = IRQ_SPI, .flags = IORESOURCE_IRQ, }, }; @@ -199,28 +229,106 @@ static struct platform_device bfin_spi0_device = { }; #endif /* spi master and devices */ -#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) -static struct resource bfin_uart_resources[] = { +#if IS_ENABLED(CONFIG_SERIAL_BFIN) +#ifdef CONFIG_SERIAL_BFIN_UART0 +static struct resource bfin_uart0_resources[] = { { - .start = 0xFFC00400, - .end = 0xFFC004FF, + .start = UART0_THR, + .end = UART0_GCTL+2, .flags = IORESOURCE_MEM, - }, { - .start = 0xFFC02000, - .end = 0xFFC020FF, + }, + { + .start = IRQ_UART0_TX, + .end = IRQ_UART0_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_ERROR, + .end = IRQ_UART0_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_TX, + .end = CH_UART0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static unsigned short bfin_uart0_peripherals[] = { + P_UART0_TX, P_UART0_RX, 0 +}; + +static struct platform_device bfin_uart0_device = { + .name = "bfin-uart", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_uart0_resources), + .resource = bfin_uart0_resources, + .dev = { + .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 +static struct resource bfin_uart1_resources[] = { + { + .start = UART1_THR, + .end = UART1_GCTL+2, .flags = IORESOURCE_MEM, }, + { + .start = IRQ_UART1_TX, + .end = IRQ_UART1_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_ERROR, + .end = IRQ_UART1_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_TX, + .end = CH_UART1_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static unsigned short bfin_uart1_peripherals[] = { + P_UART1_TX, P_UART1_RX, 0 }; -static struct platform_device bfin_uart_device = { +static struct platform_device bfin_uart1_device = { .name = "bfin-uart", .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart_resources), - .resource = bfin_uart_resources, + .num_resources = ARRAY_SIZE(bfin_uart1_resources), + .resource = bfin_uart1_resources, + .dev = { + .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ + }, }; #endif +#endif -#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +#if IS_ENABLED(CONFIG_BFIN_SIR) #ifdef CONFIG_BFIN_SIR0 static struct resource bfin_sir0_resources[] = { { @@ -275,7 +383,9 @@ static struct platform_device bfin_sir1_device = { #endif #endif -#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -294,48 +404,115 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif -#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) +#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART +static struct resource bfin_sport0_uart_resources[] = { + { + .start = SPORT0_TCR1, + .end = SPORT0_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT0_RX, + .end = IRQ_SPORT0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT0_ERROR, + .end = IRQ_SPORT0_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static unsigned short bfin_sport0_peripherals[] = { + P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 +}; + static struct platform_device bfin_sport0_uart_device = { .name = "bfin-sport-uart", .id = 0, + .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), + .resource = bfin_sport0_uart_resources, + .dev = { + .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART +static struct resource bfin_sport1_uart_resources[] = { + { + .start = SPORT1_TCR1, + .end = SPORT1_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT1_RX, + .end = IRQ_SPORT1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT1_ERROR, + .end = IRQ_SPORT1_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static unsigned short bfin_sport1_peripherals[] = { + P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { .name = "bfin-sport-uart", .id = 1, + .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), + .resource = bfin_sport1_uart_resources, + .dev = { + .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ + }, }; #endif +#endif static struct platform_device *minotaur_devices[] __initdata = { -#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) +#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA) &bfin_pcmcia_cf_device, #endif -#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) &rtc_device, #endif -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) +#if IS_ENABLED(CONFIG_BFIN_MAC) &bfin_mii_bus, &bfin_mac_device, #endif -#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) +#if IS_ENABLED(CONFIG_USB_NET2272) &net2272_bfin_device, #endif -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) &bfin_spi0_device, #endif -#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) - &bfin_uart_device, +#if IS_ENABLED(CONFIG_SERIAL_BFIN) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif #endif -#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +#if IS_ENABLED(CONFIG_BFIN_SIR) #ifdef CONFIG_BFIN_SIR0 &bfin_sir0_device, #endif @@ -344,14 +521,18 @@ static struct platform_device *minotaur_devices[] __initdata = { #endif #endif -#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) &i2c_bfin_twi_device, #endif -#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) +#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART &bfin_sport0_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART &bfin_sport1_uart_device, #endif +#endif }; @@ -359,7 +540,7 @@ static int __init minotaur_init(void) { printk(KERN_INFO "%s(): registering device resources\n", __func__); platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices)); -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); #endif @@ -369,6 +550,33 @@ static int __init minotaur_init(void) arch_initcall(minotaur_init); +static struct platform_device *minotaur_early_devices[] __initdata = { +#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif +#endif + +#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART + &bfin_sport0_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART + &bfin_sport1_uart_device, +#endif +#endif +}; + +void __init native_machine_early_platform_add_devices(void) +{ + printk(KERN_INFO "register early platform devices\n"); + early_platform_add_devices(minotaur_early_devices, + ARRAY_SIZE(minotaur_early_devices)); +} + void native_machine_restart(char *cmd) { /* workaround reboot hang when booting from SPI */ diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index 4e1de1e53f8..06a50ddb54c 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c @@ -1,48 +1,23 @@ /* - * File: arch/blackfin/mach-bf537/boards/stamp.c - * Based on: arch/blackfin/mach-bf533/boards/ezkit.c - * Author: Aidan Williams <aidan@nicta.com.au> + * Copyright 2004-2009 Analog Devices Inc. + * 2005 National ICT Australia (NICTA) + * Aidan Williams <aidan@nicta.com.au> * - * Created: - * Description: - * - * Modified: - * Copyright 2005 National ICT Australia (NICTA) - * Copyright 2004-2008 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Licensed under the GPL-2 or later. */ #include <linux/device.h> #include <linux/etherdevice.h> +#include <linux/export.h> #include <linux/platform_device.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/spi/spi.h> #include <linux/spi/flash.h> -#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) -#include <linux/usb/isp1362.h> -#endif #include <linux/irq.h> #include <asm/dma.h> #include <asm/bfin5xx_spi.h> #include <asm/portmux.h> -#include <linux/usb/sl811.h> #include <linux/spi/ad7877.h> @@ -55,7 +30,7 @@ const char bfin_board_name[] = "ADI PNAV-1.0"; * Driver needs to know address, irq and flag pin. */ -#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) +#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA) static struct resource bfin_pcmcia_cf_resources[] = { { .start = 0x20310000, /* IO PORT */ @@ -84,14 +59,22 @@ static struct platform_device bfin_pcmcia_cf_device = { }; #endif -#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) static struct platform_device rtc_device = { .name = "rtc-bfin", .id = -1, }; #endif -#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) +#if IS_ENABLED(CONFIG_SMC91X) +#include <linux/smc91x.h> + +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, + .leda = RPC_LED_100_10, + .ledb = RPC_LED_TX_RX, +}; + static struct resource smc91x_resources[] = { { .name = "smc91x-regs", @@ -110,105 +93,46 @@ static struct platform_device smc91x_device = { .id = 0, .num_resources = ARRAY_SIZE(smc91x_resources), .resource = smc91x_resources, -}; -#endif - -#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE) -static struct resource sl811_hcd_resources[] = { - { - .start = 0x20340000, - .end = 0x20340000, - .flags = IORESOURCE_MEM, - }, { - .start = 0x20340004, - .end = 0x20340004, - .flags = IORESOURCE_MEM, - }, { - .start = CONFIG_USB_SL811_BFIN_IRQ, - .end = CONFIG_USB_SL811_BFIN_IRQ, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .dev = { + .platform_data = &smc91x_info, }, }; - -#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS) -void sl811_port_power(struct device *dev, int is_on) -{ - gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS"); - gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on); - -} #endif -static struct sl811_platform_data sl811_priv = { - .potpg = 10, - .power = 250, /* == 500mA */ -#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS) - .port_power = &sl811_port_power, -#endif -}; - -static struct platform_device sl811_hcd_device = { - .name = "sl811-hcd", - .id = 0, - .dev = { - .platform_data = &sl811_priv, - }, - .num_resources = ARRAY_SIZE(sl811_hcd_resources), - .resource = sl811_hcd_resources, -}; -#endif +#if IS_ENABLED(CONFIG_BFIN_MAC) +#include <linux/bfin_mac.h> +static const unsigned short bfin_mac_peripherals[] = P_RMII0; -#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) -static struct resource isp1362_hcd_resources[] = { +static struct bfin_phydev_platform_data bfin_phydev_data[] = { { - .start = 0x20360000, - .end = 0x20360000, - .flags = IORESOURCE_MEM, - }, { - .start = 0x20360004, - .end = 0x20360004, - .flags = IORESOURCE_MEM, - }, { - .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, - .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .addr = 1, + .irq = IRQ_MAC_PHYINT, }, }; -static struct isp1362_platform_data isp1362_priv = { - .sel15Kres = 1, - .clknotstop = 0, - .oc_enable = 0, - .int_act_high = 0, - .int_edge_triggered = 0, - .remote_wakeup_connected = 0, - .no_power_switching = 1, - .power_switching_mode = 0, +static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { + .phydev_number = 1, + .phydev_data = bfin_phydev_data, + .phy_mode = PHY_INTERFACE_MODE_RMII, + .mac_peripherals = bfin_mac_peripherals, }; -static struct platform_device isp1362_hcd_device = { - .name = "isp1362-hcd", - .id = 0, - .dev = { - .platform_data = &isp1362_priv, - }, - .num_resources = ARRAY_SIZE(isp1362_hcd_resources), - .resource = isp1362_hcd_resources, -}; -#endif - -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) static struct platform_device bfin_mii_bus = { .name = "bfin_mii_bus", + .dev = { + .platform_data = &bfin_mii_bus_data, + } }; static struct platform_device bfin_mac_device = { .name = "bfin_mac", - .dev.platform_data = &bfin_mii_bus, + .dev = { + .platform_data = &bfin_mii_bus, + } }; #endif -#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) +#if IS_ENABLED(CONFIG_USB_NET2272) static struct resource net2272_bfin_resources[] = { { .start = 0x20300000, @@ -229,11 +153,10 @@ static struct platform_device net2272_bfin_device = { }; #endif -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) /* all SPI peripherals info goes here */ -#if defined(CONFIG_MTD_M25P80) \ - || defined(CONFIG_MTD_M25P80_MODULE) +#if IS_ENABLED(CONFIG_MTD_M25P80) static struct mtd_partition bfin_spi_flash_partitions[] = { { .name = "bootloader(spi)", @@ -261,48 +184,16 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, }; #endif -#if defined(CONFIG_SPI_ADC_BF533) \ - || defined(CONFIG_SPI_ADC_BF533_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, -}; -#endif - -#if defined(CONFIG_SND_BLACKFIN_AD1836) \ - || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) -static struct bfin5xx_spi_chip ad1836_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; -#endif - -#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) -static struct bfin5xx_spi_chip ad9960_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; -#endif - -#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) +#if IS_ENABLED(CONFIG_MMC_SPI) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif -#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) -static struct bfin5xx_spi_chip spi_ad7877_chip_info = { - .cs_change_per_word = 0, - .enable_dma = 0, - .bits_per_word = 16, -}; - +#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) static const struct ad7877_platform_data bfin_ad7877_ts_info = { .model = 7877, .vref_delay_usecs = 50, /* internal, no capacitor */ @@ -319,8 +210,7 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = { #endif static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if defined(CONFIG_MTD_M25P80) \ - || defined(CONFIG_MTD_M25P80_MODULE) +#if IS_ENABLED(CONFIG_MTD_M25P80) { /* the modalias must be the same as spi device driver name */ .modalias = "m25p80", /* Name of spi_driver for this device */ @@ -333,38 +223,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SPI_ADC_BF533) \ - || defined(CONFIG_SPI_ADC_BF533_MODULE) +#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - -#if defined(CONFIG_SND_BLACKFIN_AD1836) \ - || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) - { - .modalias = "ad1836-spi", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, - .controller_data = &ad1836_spi_chip_info, - }, -#endif -#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) - { - .modalias = "ad9960-spi", - .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - .controller_data = &ad9960_spi_chip_info, + .chip_select = 4, }, #endif -#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) +#if IS_ENABLED(CONFIG_MMC_SPI) { .modalias = "mmc_spi", .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ @@ -374,7 +241,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .mode = SPI_MODE_3, }, #endif -#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) +#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) { .modalias = "ad7877", .platform_data = &bfin_ad7877_ts_info, @@ -382,7 +249,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 5, - .controller_data = &spi_ad7877_chip_info, }, #endif @@ -398,8 +264,13 @@ static struct resource bfin_spi0_resource[] = { [1] = { .start = CH_SPI, .end = CH_SPI, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = IRQ_SPI, + .end = IRQ_SPI, .flags = IORESOURCE_IRQ, - } + }, }; /* SPI controller data */ @@ -420,34 +291,112 @@ static struct platform_device bfin_spi0_device = { }; #endif /* spi master and devices */ -#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) +#if IS_ENABLED(CONFIG_FB_BF537_LQ035) static struct platform_device bfin_fb_device = { .name = "bf537-lq035", }; #endif -#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) -static struct resource bfin_uart_resources[] = { +#if IS_ENABLED(CONFIG_SERIAL_BFIN) +#ifdef CONFIG_SERIAL_BFIN_UART0 +static struct resource bfin_uart0_resources[] = { { - .start = 0xFFC00400, - .end = 0xFFC004FF, + .start = UART0_THR, + .end = UART0_GCTL+2, .flags = IORESOURCE_MEM, - }, { - .start = 0xFFC02000, - .end = 0xFFC020FF, + }, + { + .start = IRQ_UART0_TX, + .end = IRQ_UART0_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_ERROR, + .end = IRQ_UART0_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_TX, + .end = CH_UART0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static unsigned short bfin_uart0_peripherals[] = { + P_UART0_TX, P_UART0_RX, 0 +}; + +static struct platform_device bfin_uart0_device = { + .name = "bfin-uart", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_uart0_resources), + .resource = bfin_uart0_resources, + .dev = { + .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 +static struct resource bfin_uart1_resources[] = { + { + .start = UART1_THR, + .end = UART1_GCTL+2, .flags = IORESOURCE_MEM, }, + { + .start = IRQ_UART1_TX, + .end = IRQ_UART1_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_ERROR, + .end = IRQ_UART1_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_TX, + .end = CH_UART1_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static unsigned short bfin_uart1_peripherals[] = { + P_UART1_TX, P_UART1_RX, 0 }; -static struct platform_device bfin_uart_device = { +static struct platform_device bfin_uart1_device = { .name = "bfin-uart", .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart_resources), - .resource = bfin_uart_resources, + .num_resources = ARRAY_SIZE(bfin_uart1_resources), + .resource = bfin_uart1_resources, + .dev = { + .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ + }, }; #endif +#endif -#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +#if IS_ENABLED(CONFIG_BFIN_SIR) #ifdef CONFIG_BFIN_SIR0 static struct resource bfin_sir0_resources[] = { { @@ -503,48 +452,45 @@ static struct platform_device bfin_sir1_device = { #endif static struct platform_device *stamp_devices[] __initdata = { -#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) +#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA) &bfin_pcmcia_cf_device, #endif -#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) &rtc_device, #endif -#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE) - &sl811_hcd_device, -#endif - -#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) - &isp1362_hcd_device, -#endif - -#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) +#if IS_ENABLED(CONFIG_SMC91X) &smc91x_device, #endif -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) +#if IS_ENABLED(CONFIG_BFIN_MAC) &bfin_mii_bus, &bfin_mac_device, #endif -#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) +#if IS_ENABLED(CONFIG_USB_NET2272) &net2272_bfin_device, #endif -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) &bfin_spi0_device, #endif -#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) +#if IS_ENABLED(CONFIG_FB_BF537_LQ035) &bfin_fb_device, #endif -#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) - &bfin_uart_device, +#if IS_ENABLED(CONFIG_SERIAL_BFIN) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif #endif -#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +#if IS_ENABLED(CONFIG_BFIN_SIR) #ifdef CONFIG_BFIN_SIR0 &bfin_sir0_device, #endif @@ -558,7 +504,7 @@ static int __init pnav_init(void) { printk(KERN_INFO "%s(): registering device resources\n", __func__); platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); #endif @@ -567,9 +513,26 @@ static int __init pnav_init(void) arch_initcall(pnav_init); -void bfin_get_ether_addr(char *addr) +static struct platform_device *stamp_early_devices[] __initdata = { +#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif +#endif +}; + +void __init native_machine_early_platform_add_devices(void) +{ + printk(KERN_INFO "register early platform devices\n"); + early_platform_add_devices(stamp_early_devices, + ARRAY_SIZE(stamp_early_devices)); +} + +int bfin_get_ether_addr(char *addr) { - random_ether_addr(addr); - printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__); + return 1; } EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index cd04c5e4487..de19b8a5600 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -1,36 +1,16 @@ /* - * File: arch/blackfin/mach-bf537/boards/stamp.c - * Based on: arch/blackfin/mach-bf533/boards/ezkit.c - * Author: Aidan Williams <aidan@nicta.com.au> + * Copyright 2004-2009 Analog Devices Inc. + * 2005 National ICT Australia (NICTA) + * Aidan Williams <aidan@nicta.com.au> * - * Created: - * Description: - * - * Modified: - * Copyright 2005 National ICT Australia (NICTA) - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Licensed under the GPL-2 or later. */ #include <linux/device.h> +#include <linux/export.h> #include <linux/kernel.h> #include <linux/platform_device.h> +#include <linux/io.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> @@ -38,20 +18,31 @@ #include <linux/mtd/physmap.h> #include <linux/spi/spi.h> #include <linux/spi/flash.h> -#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) #include <linux/usb/isp1362.h> #endif +#include <linux/i2c.h> +#include <linux/i2c/adp5588.h> +#include <linux/etherdevice.h> #include <linux/ata_platform.h> #include <linux/irq.h> #include <linux/interrupt.h> -#include <linux/i2c.h> #include <linux/usb/sl811.h> #include <linux/spi/mmc_spi.h> +#include <linux/leds.h> +#include <linux/input.h> #include <asm/dma.h> #include <asm/bfin5xx_spi.h> #include <asm/reboot.h> #include <asm/portmux.h> #include <asm/dpmc.h> +#include <asm/bfin_sport.h> +#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE +#include <linux/regulator/fixed.h> +#endif +#include <linux/regulator/machine.h> +#include <linux/regulator/consumer.h> +#include <linux/regulator/userspace-consumer.h> /* * Name the Board for the /proc/cpuinfo @@ -62,7 +53,7 @@ const char bfin_board_name[] = "ADI BF537-STAMP"; * Driver needs to know address, irq and flag pin. */ -#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) #include <linux/usb/isp1760.h> static struct resource bfin_isp1760_resources[] = { [0] = { @@ -79,7 +70,6 @@ static struct resource bfin_isp1760_resources[] = { static struct isp1760_platform_data isp1760_priv = { .is_isp1761 = 0, - .port1_disable = 0, .bus_width_16 = 1, .port1_otg = 0, .analog_oc = 0, @@ -88,7 +78,7 @@ static struct isp1760_platform_data isp1760_priv = { }; static struct platform_device bfin_isp1760_device = { - .name = "isp1760-hcd", + .name = "isp1760", .id = 0, .dev = { .platform_data = &isp1760_priv, @@ -98,8 +88,7 @@ static struct platform_device bfin_isp1760_device = { }; #endif -#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) -#include <linux/input.h> +#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) #include <linux/gpio_keys.h> static struct gpio_keys_button bfin_gpio_keys_table[] = { @@ -122,20 +111,7 @@ static struct platform_device bfin_device_gpiokeys = { }; #endif -static struct resource bfin_gpios_resources = { - .start = 0, - .end = MAX_BLACKFIN_GPIOS - 1, - .flags = IORESOURCE_IRQ, -}; - -static struct platform_device bfin_gpios_device = { - .name = "simple-gpio", - .id = -1, - .num_resources = 1, - .resource = &bfin_gpios_resources, -}; - -#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) +#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA) static struct resource bfin_pcmcia_cf_resources[] = { { .start = 0x20310000, /* IO PORT */ @@ -164,14 +140,22 @@ static struct platform_device bfin_pcmcia_cf_device = { }; #endif -#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) static struct platform_device rtc_device = { .name = "rtc-bfin", .id = -1, }; #endif -#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) +#if IS_ENABLED(CONFIG_SMC91X) +#include <linux/smc91x.h> + +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, + .leda = RPC_LED_100_10, + .ledb = RPC_LED_TX_RX, +}; + static struct resource smc91x_resources[] = { { .name = "smc91x-regs", @@ -190,17 +174,25 @@ static struct platform_device smc91x_device = { .id = 0, .num_resources = ARRAY_SIZE(smc91x_resources), .resource = smc91x_resources, + .dev = { + .platform_data = &smc91x_info, + }, }; #endif -#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) +#if IS_ENABLED(CONFIG_DM9000) static struct resource dm9000_resources[] = { [0] = { .start = 0x203FB800, - .end = 0x203FB800 + 8, + .end = 0x203FB800 + 1, .flags = IORESOURCE_MEM, }, [1] = { + .start = 0x203FB804, + .end = 0x203FB804 + 1, + .flags = IORESOURCE_MEM, + }, + [2] = { .start = IRQ_PF9, .end = IRQ_PF9, .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE), @@ -215,29 +207,7 @@ static struct platform_device dm9000_device = { }; #endif -#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE) -static struct resource ax88180_resources[] = { - [0] = { - .start = 0x20300000, - .end = 0x20300000 + 0x8000, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL), - }, -}; - -static struct platform_device ax88180_device = { - .name = "ax88180", - .id = -1, - .num_resources = ARRAY_SIZE(ax88180_resources), - .resource = ax88180_resources, -}; -#endif - -#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_SL811_HCD) static struct resource sl811_hcd_resources[] = { { .start = 0x20340000, @@ -248,8 +218,8 @@ static struct resource sl811_hcd_resources[] = { .end = 0x20340004, .flags = IORESOURCE_MEM, }, { - .start = CONFIG_USB_SL811_BFIN_IRQ, - .end = CONFIG_USB_SL811_BFIN_IRQ, + .start = IRQ_PF4, + .end = IRQ_PF4, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, }, }; @@ -281,7 +251,7 @@ static struct platform_device sl811_hcd_device = { }; #endif -#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) static struct resource isp1362_hcd_resources[] = { { .start = 0x20360000, @@ -292,9 +262,9 @@ static struct resource isp1362_hcd_resources[] = { .end = 0x20360004, .flags = IORESOURCE_MEM, }, { - .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, - .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .start = IRQ_PF3, + .end = IRQ_PF3, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; @@ -320,24 +290,87 @@ static struct platform_device isp1362_hcd_device = { }; #endif -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) +#if IS_ENABLED(CONFIG_CAN_BFIN) +static unsigned short bfin_can_peripherals[] = { + P_CAN0_RX, P_CAN0_TX, 0 +}; + +static struct resource bfin_can_resources[] = { + { + .start = 0xFFC02A00, + .end = 0xFFC02FFF, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_CAN_RX, + .end = IRQ_CAN_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_CAN_TX, + .end = IRQ_CAN_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_CAN_ERROR, + .end = IRQ_CAN_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_can_device = { + .name = "bfin_can", + .num_resources = ARRAY_SIZE(bfin_can_resources), + .resource = bfin_can_resources, + .dev = { + .platform_data = &bfin_can_peripherals, /* Passed to driver */ + }, +}; +#endif + +#if IS_ENABLED(CONFIG_BFIN_MAC) +#include <linux/bfin_mac.h> +static const unsigned short bfin_mac_peripherals[] = P_MII0; + +static struct bfin_phydev_platform_data bfin_phydev_data[] = { + { + .addr = 1, + .irq = PHY_POLL, /* IRQ_MAC_PHYINT */ + }, +}; + +static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { + .phydev_number = 1, + .phydev_data = bfin_phydev_data, + .phy_mode = PHY_INTERFACE_MODE_MII, + .mac_peripherals = bfin_mac_peripherals, +}; + static struct platform_device bfin_mii_bus = { .name = "bfin_mii_bus", + .dev = { + .platform_data = &bfin_mii_bus_data, + } }; static struct platform_device bfin_mac_device = { .name = "bfin_mac", - .dev.platform_data = &bfin_mii_bus, + .dev = { + .platform_data = &bfin_mii_bus, + } }; #endif -#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) +#if IS_ENABLED(CONFIG_USB_NET2272) static struct resource net2272_bfin_resources[] = { { .start = 0x20300000, .end = 0x20300000 + 0x100, .flags = IORESOURCE_MEM, }, { + .start = 1, + .flags = IORESOURCE_BUS, + }, { .start = IRQ_PF7, .end = IRQ_PF7, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -352,8 +385,7 @@ static struct platform_device net2272_bfin_device = { }; #endif -#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) -#ifdef CONFIG_MTD_PARTITIONS +#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM) const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL }; static struct mtd_partition bfin_plat_nand_partitions[] = { @@ -367,7 +399,6 @@ static struct mtd_partition bfin_plat_nand_partitions[] = { .offset = MTDPART_OFS_APPEND, }, }; -#endif #define BFIN_NAND_PLAT_CLE 2 #define BFIN_NAND_PLAT_ALE 1 @@ -392,12 +423,11 @@ static int bfin_plat_nand_dev_ready(struct mtd_info *mtd) static struct platform_nand_data bfin_plat_nand_data = { .chip = { + .nr_chips = 1, .chip_delay = 30, -#ifdef CONFIG_MTD_PARTITIONS .part_probe_types = part_probes, .partitions = bfin_plat_nand_partitions, .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions), -#endif }, .ctrl = { .cmd_ctrl = bfin_plat_nand_cmd_ctrl, @@ -409,7 +439,7 @@ static struct platform_nand_data bfin_plat_nand_data = { static struct resource bfin_plat_nand_resources = { .start = 0x20212000, .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), - .flags = IORESOURCE_IO, + .flags = IORESOURCE_MEM, }; static struct platform_device bfin_async_nand_device = { @@ -425,12 +455,13 @@ static struct platform_device bfin_async_nand_device = { static void bfin_plat_nand_init(void) { gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat"); + gpio_direction_input(BFIN_NAND_PLAT_READY); } #else static void bfin_plat_nand_init(void) {} #endif -#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) +#if IS_ENABLED(CONFIG_MTD_PHYSMAP) static struct mtd_partition stamp_partitions[] = { { .name = "bootloader(nor)", @@ -456,6 +487,9 @@ static struct physmap_flash_data stamp_flash_data = { .width = 2, .parts = stamp_partitions, .nr_parts = ARRAY_SIZE(stamp_partitions), +#ifdef CONFIG_ROMKERNEL + .probe_type = "map_rom", +#endif }; static struct resource stamp_flash_resource = { @@ -475,8 +509,7 @@ static struct platform_device stamp_flash_device = { }; #endif -#if defined(CONFIG_MTD_M25P80) \ - || defined(CONFIG_MTD_M25P80_MODULE) +#if IS_ENABLED(CONFIG_MTD_M25P80) static struct mtd_partition bfin_spi_flash_partitions[] = { { .name = "bootloader(spi)", @@ -504,35 +537,201 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, }; #endif -#if defined(CONFIG_SPI_ADC_BF533) \ - || defined(CONFIG_SPI_ADC_BF533_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, +#if IS_ENABLED(CONFIG_INPUT_AD714X_SPI) +#include <linux/input/ad714x.h> + +static struct ad714x_slider_plat ad7147_spi_slider_plat[] = { + { + .start_stage = 0, + .end_stage = 7, + .max_coord = 128, + }, +}; + +static struct ad714x_button_plat ad7147_spi_button_plat[] = { + { + .keycode = BTN_FORWARD, + .l_mask = 0, + .h_mask = 0x600, + }, + { + .keycode = BTN_LEFT, + .l_mask = 0, + .h_mask = 0x500, + }, + { + .keycode = BTN_MIDDLE, + .l_mask = 0, + .h_mask = 0x800, + }, + { + .keycode = BTN_RIGHT, + .l_mask = 0x100, + .h_mask = 0x400, + }, + { + .keycode = BTN_BACK, + .l_mask = 0x200, + .h_mask = 0x400, + }, +}; +static struct ad714x_platform_data ad7147_spi_platform_data = { + .slider_num = 1, + .button_num = 5, + .slider = ad7147_spi_slider_plat, + .button = ad7147_spi_button_plat, + .stage_cfg_reg = { + {0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600}, + {0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650}, + {0xFFFF, 0x1FFE, 0, 0x2626, 1650, 1650, 1650, 1650}, + {0xFFFF, 0x1FFB, 0, 0x2626, 1650, 1650, 1650, 1650}, + {0xFFFF, 0x1FEF, 0, 0x2626, 1650, 1650, 1650, 1650}, + {0xFFFF, 0x1FBF, 0, 0x2626, 1650, 1650, 1650, 1650}, + {0xFFFF, 0x1EFF, 0, 0x2626, 1650, 1650, 1650, 1650}, + {0xFFFF, 0x1BFF, 0, 0x2626, 1600, 1600, 1600, 1600}, + {0xFF7B, 0x3FFF, 0x506, 0x2626, 1100, 1100, 1150, 1150}, + {0xFDFE, 0x3FFF, 0x606, 0x2626, 1100, 1100, 1150, 1150}, + {0xFEBA, 0x1FFF, 0x1400, 0x2626, 1200, 1200, 1300, 1300}, + {0xFFEF, 0x1FFF, 0x0, 0x2626, 1100, 1100, 1150, 1150}, + }, + .sys_cfg_reg = {0x2B2, 0x0, 0x3233, 0x819, 0x832, 0xCFF, 0xCFF, 0x0}, }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD1836) \ - || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) -static struct bfin5xx_spi_chip ad1836_spi_chip_info = { +#if IS_ENABLED(CONFIG_INPUT_AD714X_I2C) +#include <linux/input/ad714x.h> +static struct ad714x_button_plat ad7142_i2c_button_plat[] = { + { + .keycode = BTN_1, + .l_mask = 0, + .h_mask = 0x1, + }, + { + .keycode = BTN_2, + .l_mask = 0, + .h_mask = 0x2, + }, + { + .keycode = BTN_3, + .l_mask = 0, + .h_mask = 0x4, + }, + { + .keycode = BTN_4, + .l_mask = 0x0, + .h_mask = 0x8, + }, +}; +static struct ad714x_platform_data ad7142_i2c_platform_data = { + .button_num = 4, + .button = ad7142_i2c_button_plat, + .stage_cfg_reg = { + /* fixme: figure out right setting for all comoponent according + * to hardware feature of EVAL-AD7142EB board */ + {0xE7FF, 0x3FFF, 0x0005, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A}, + {0xFDBF, 0x3FFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A}, + {0xFFFF, 0x2DFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A}, + {0xFFFF, 0x37BF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A}, + {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, + {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, + {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, + {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, + {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, + {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, + {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, + {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, + }, + .sys_cfg_reg = {0x0B2, 0x0, 0x690, 0x664, 0x290F, 0xF, 0xF, 0x0}, +}; +#endif + +#if IS_ENABLED(CONFIG_AD2S90) +static struct bfin5xx_spi_chip ad2s90_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 16, }; #endif -#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) -static struct bfin5xx_spi_chip ad9960_spi_chip_info = { +#if IS_ENABLED(CONFIG_AD2S1200) +static unsigned short ad2s1200_platform_data[] = { + /* used as SAMPLE and RDVEL */ + GPIO_PF5, GPIO_PF6, 0 +}; + +static struct bfin5xx_spi_chip ad2s1200_spi_chip_info = { + .enable_dma = 0, +}; +#endif + +#if IS_ENABLED(CONFIG_AD2S1210) +static unsigned short ad2s1210_platform_data[] = { + /* use as SAMPLE, A0, A1 */ + GPIO_PF7, GPIO_PF8, GPIO_PF9, +# if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT) + /* the RES0 and RES1 pins */ + GPIO_PF4, GPIO_PF5, +# endif + 0, +}; + +static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 16, }; #endif -#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) +#if IS_ENABLED(CONFIG_SENSORS_AD7314) +static struct bfin5xx_spi_chip ad7314_spi_chip_info = { + .enable_dma = 0, +}; +#endif + +#if IS_ENABLED(CONFIG_AD7816) +static unsigned short ad7816_platform_data[] = { + GPIO_PF4, /* rdwr_pin */ + GPIO_PF5, /* convert_pin */ + GPIO_PF7, /* busy_pin */ + 0, +}; + +static struct bfin5xx_spi_chip ad7816_spi_chip_info = { + .enable_dma = 0, +}; +#endif + +#if IS_ENABLED(CONFIG_ADT7310) +static unsigned long adt7310_platform_data[3] = { +/* INT bound temperature alarm event. line 1 */ + IRQ_PG4, IRQF_TRIGGER_LOW, +/* CT bound temperature alarm event irq_flags. line 0 */ + IRQF_TRIGGER_LOW, +}; + +static struct bfin5xx_spi_chip adt7310_spi_chip_info = { + .enable_dma = 0, +}; +#endif + +#if IS_ENABLED(CONFIG_AD7298) +static unsigned short ad7298_platform_data[] = { + GPIO_PF7, /* busy_pin */ + 0, +}; +#endif + +#if IS_ENABLED(CONFIG_ADT7316_SPI) +static unsigned long adt7316_spi_data[2] = { + IRQF_TRIGGER_LOW, /* interrupt flags */ + GPIO_PF7, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */ +}; + +static struct bfin5xx_spi_chip adt7316_spi_chip_info = { + .enable_dma = 0, +}; +#endif + +#if IS_ENABLED(CONFIG_MMC_SPI) #define MMC_SPI_CARD_DETECT_INT IRQ_PF5 static int bfin_mmc_spi_init(struct device *dev, @@ -555,26 +754,12 @@ static struct mmc_spi_platform_data bfin_mmc_spi_pdata = { static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_PBX) -static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { - .ctl_reg = 0x4, /* send zero */ - .enable_dma = 0, - .bits_per_word = 8, - .cs_change_per_word = 1, + .pio_interrupt = 0, }; #endif -#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) +#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) #include <linux/spi/ad7877.h> -static struct bfin5xx_spi_chip spi_ad7877_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; - static const struct ad7877_platform_data bfin_ad7877_ts_info = { .model = 7877, .vref_delay_usecs = 50, /* internal, no capacitor */ @@ -582,62 +767,138 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = { .y_plate_ohms = 486, .pressure_max = 1000, .pressure_min = 0, - .stopacq_polarity = 1, - .first_conversion_delay = 3, - .acquisition_time = 1, - .averaging = 1, - .pen_down_acc_interval = 1, + .stopacq_polarity = 1, + .first_conversion_delay = 3, + .acquisition_time = 1, + .averaging = 1, + .pen_down_acc_interval = 1, }; #endif -#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE) +#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879) #include <linux/spi/ad7879.h> static const struct ad7879_platform_data bfin_ad7879_ts_info = { .model = 7879, /* Model = AD7879 */ .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */ .pressure_max = 10000, .pressure_min = 0, - .first_conversion_delay = 3, /* wait 512us before do a first conversion */ - .acquisition_time = 1, /* 4us acquisition time per sample */ + .first_conversion_delay = 3, /* wait 512us before do a first conversion */ + .acquisition_time = 1, /* 4us acquisition time per sample */ .median = 2, /* do 8 measurements */ - .averaging = 1, /* take the average of 4 middle samples */ - .pen_down_acc_interval = 255, /* 9.4 ms */ - .gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */ - .gpio_default = 1, /* During initialization set GPIO = HIGH */ -}; -#endif - -#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) -static struct bfin5xx_spi_chip spi_ad7879_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, + .averaging = 1, /* take the average of 4 middle samples */ + .pen_down_acc_interval = 255, /* 9.4 ms */ + .gpio_export = 1, /* Export GPIO to gpiolib */ + .gpio_base = -1, /* Dynamic allocation */ +}; +#endif + +#if IS_ENABLED(CONFIG_INPUT_ADXL34X) +#include <linux/input/adxl34x.h> +static const struct adxl34x_platform_data adxl34x_info = { + .x_axis_offset = 0, + .y_axis_offset = 0, + .z_axis_offset = 0, + .tap_threshold = 0x31, + .tap_duration = 0x10, + .tap_latency = 0x60, + .tap_window = 0xF0, + .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN, + .act_axis_control = 0xFF, + .activity_threshold = 5, + .inactivity_threshold = 3, + .inactivity_time = 4, + .free_fall_threshold = 0x7, + .free_fall_time = 0x20, + .data_rate = 0x8, + .data_range = ADXL_FULL_RES, + + .ev_type = EV_ABS, + .ev_code_x = ABS_X, /* EV_REL */ + .ev_code_y = ABS_Y, /* EV_REL */ + .ev_code_z = ABS_Z, /* EV_REL */ + + .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */ + +/* .ev_code_ff = KEY_F,*/ /* EV_KEY */ +/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */ + .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK, + .fifo_mode = ADXL_FIFO_STREAM, + .orientation_enable = ADXL_EN_ORIENTATION_3D, + .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8, + .divisor_length = ADXL_LP_FILTER_DIVISOR_16, + /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */ + .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C}, +}; +#endif + +#if IS_ENABLED(CONFIG_ENC28J60) +static struct bfin5xx_spi_chip enc28j60_spi_chip_info = { + .enable_dma = 1, }; #endif -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; +#if IS_ENABLED(CONFIG_ADF702X) +#include <linux/spi/adf702x.h> +#define TXREG 0x0160A470 +static const u32 adf7021_regs[] = { + 0x09608FA0, + 0x00575011, + 0x00A7F092, + 0x2B141563, + 0x81F29E94, + 0x00003155, + 0x050A4F66, + 0x00000007, + 0x00000008, + 0x000231E9, + 0x3296354A, + 0x891A2B3B, + 0x00000D9C, + 0x0000000D, + 0x0000000E, + 0x0000000F, +}; + +static struct adf702x_platform_data adf7021_platform_data = { + .regs_base = (void *)SPORT1_TCR1, + .dma_ch_rx = CH_SPORT1_RX, + .dma_ch_tx = CH_SPORT1_TX, + .irq_sport_err = IRQ_SPORT1_ERROR, + .gpio_int_rfs = GPIO_PF8, + .pin_req = {P_SPORT1_DTPRI, P_SPORT1_RFS, P_SPORT1_DRPRI, + P_SPORT1_RSCLK, P_SPORT1_TSCLK, 0}, + .adf702x_model = MODEL_ADF7021, + .adf702x_regs = adf7021_regs, + .tx_reg = TXREG, +}; +static inline void adf702x_mac_init(void) +{ + eth_random_addr(adf7021_platform_data.mac_addr); +} +#else +static inline void adf702x_mac_init(void) {} #endif -#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) -static struct bfin5xx_spi_chip lq035q1_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif +#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846) +#include <linux/spi/ads7846.h> +static int ads7873_get_pendown_state(void) +{ + return gpio_get_value(GPIO_PF6); +} -#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) -static struct bfin5xx_spi_chip enc28j60_spi_chip_info = { - .enable_dma = 1, - .bits_per_word = 8, - .cs_gpio = GPIO_PF10, +static struct ads7846_platform_data __initdata ad7873_pdata = { + .model = 7873, /* AD7873 */ + .x_max = 0xfff, + .y_max = 0xfff, + .x_plate_ohms = 620, + .debounce_max = 1, + .debounce_rep = 0, + .debounce_tol = (~0), + .get_pendown_state = ads7873_get_pendown_state, }; #endif -#if defined(CONFIG_MTD_DATAFLASH) \ - || defined(CONFIG_MTD_DATAFLASH_MODULE) +#if IS_ENABLED(CONFIG_MTD_DATAFLASH) static struct mtd_partition bfin_spi_dataflash_partitions[] = { { @@ -665,13 +926,17 @@ static struct flash_platform_data bfin_spi_dataflash_data = { /* DataFlash chip */ static struct bfin5xx_spi_chip data_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, +}; +#endif + +#if IS_ENABLED(CONFIG_AD7476) +static struct bfin5xx_spi_chip spi_ad7476_chip_info = { + .enable_dma = 0, /* use dma transfer with this chip*/ }; #endif static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if defined(CONFIG_MTD_M25P80) \ - || defined(CONFIG_MTD_M25P80_MODULE) +#if IS_ENABLED(CONFIG_MTD_M25P80) { /* the modalias must be the same as spi device driver name */ .modalias = "m25p80", /* Name of spi_driver for this device */ @@ -683,8 +948,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .mode = SPI_MODE_3, }, #endif -#if defined(CONFIG_MTD_DATAFLASH) \ - || defined(CONFIG_MTD_DATAFLASH_MODULE) +#if IS_ENABLED(CONFIG_MTD_DATAFLASH) { /* DataFlash chip */ .modalias = "mtd_dataflash", .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */ @@ -695,67 +959,154 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .mode = SPI_MODE_3, }, #endif -#if defined(CONFIG_SPI_ADC_BF533) \ - || defined(CONFIG_SPI_ADC_BF533_MODULE) + +#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, + .modalias = "ad1836", + .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 4, + .platform_data = "ad1836", /* only includes chip name for the moment */ + .mode = SPI_MODE_3, }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD1836) \ - || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) +#ifdef CONFIG_SND_SOC_AD193X_SPI { - .modalias = "ad1836-spi", + .modalias = "ad193x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, - .controller_data = &ad1836_spi_chip_info, + .chip_select = 5, + .mode = SPI_MODE_3, }, #endif -#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) + +#if IS_ENABLED(CONFIG_SND_SOC_ADAV80X) { - .modalias = "ad9960-spi", - .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */ + .modalias = "adav801", + .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &ad9960_spi_chip_info, + .mode = SPI_MODE_3, }, #endif -#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) + +#if IS_ENABLED(CONFIG_INPUT_AD714X_SPI) { - .modalias = "mmc_spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ + .modalias = "ad714x_captouch", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .irq = IRQ_PF4, .bus_num = 0, - .chip_select = 4, - .platform_data = &bfin_mmc_spi_pdata, - .controller_data = &mmc_spi_chip_info, + .chip_select = 5, .mode = SPI_MODE_3, + .platform_data = &ad7147_spi_platform_data, }, #endif -#if defined(CONFIG_PBX) + +#if IS_ENABLED(CONFIG_AD2S90) { - .modalias = "fxs-spi", - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ + .modalias = "ad2s90", .bus_num = 0, - .chip_select = 8 - CONFIG_J11_JUMPER, - .controller_data = &spi_si3xxx_chip_info, + .chip_select = 3, /* change it for your board */ .mode = SPI_MODE_3, + .platform_data = NULL, + .controller_data = &ad2s90_spi_chip_info, + }, +#endif + +#if IS_ENABLED(CONFIG_AD2S1200) + { + .modalias = "ad2s1200", + .bus_num = 0, + .chip_select = 4, /* CS, change it for your board */ + .platform_data = ad2s1200_platform_data, + .controller_data = &ad2s1200_spi_chip_info, }, +#endif + +#if IS_ENABLED(CONFIG_AD2S1210) { - .modalias = "fxo-spi", - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ + .modalias = "ad2s1210", + .max_speed_hz = 8192000, .bus_num = 0, - .chip_select = 8 - CONFIG_J19_JUMPER, - .controller_data = &spi_si3xxx_chip_info, + .chip_select = 4, /* CS, change it for your board */ + .platform_data = ad2s1210_platform_data, + .controller_data = &ad2s1210_spi_chip_info, + }, +#endif + +#if IS_ENABLED(CONFIG_SENSORS_AD7314) + { + .modalias = "ad7314", + .max_speed_hz = 1000000, + .bus_num = 0, + .chip_select = 4, /* CS, change it for your board */ + .controller_data = &ad7314_spi_chip_info, + .mode = SPI_MODE_1, + }, +#endif + +#if IS_ENABLED(CONFIG_AD7816) + { + .modalias = "ad7818", + .max_speed_hz = 1000000, + .bus_num = 0, + .chip_select = 4, /* CS, change it for your board */ + .platform_data = ad7816_platform_data, + .controller_data = &ad7816_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif + +#if IS_ENABLED(CONFIG_ADT7310) + { + .modalias = "adt7310", + .max_speed_hz = 1000000, + .irq = IRQ_PG5, /* CT alarm event. Line 0 */ + .bus_num = 0, + .chip_select = 4, /* CS, change it for your board */ + .platform_data = adt7310_platform_data, + .controller_data = &adt7310_spi_chip_info, .mode = SPI_MODE_3, }, #endif -#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) + +#if IS_ENABLED(CONFIG_AD7298) + { + .modalias = "ad7298", + .max_speed_hz = 1000000, + .bus_num = 0, + .chip_select = 4, /* CS, change it for your board */ + .platform_data = ad7298_platform_data, + .mode = SPI_MODE_3, + }, +#endif + +#if IS_ENABLED(CONFIG_ADT7316_SPI) + { + .modalias = "adt7316", + .max_speed_hz = 1000000, + .irq = IRQ_PG5, /* interrupt line */ + .bus_num = 0, + .chip_select = 4, /* CS, change it for your board */ + .platform_data = adt7316_spi_data, + .controller_data = &adt7316_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif + +#if IS_ENABLED(CONFIG_MMC_SPI) + { + .modalias = "mmc_spi", + .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 4, + .platform_data = &bfin_mmc_spi_pdata, + .controller_data = &mmc_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif +#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) { .modalias = "ad7877", .platform_data = &bfin_ad7877_ts_info, @@ -763,10 +1114,9 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spi_ad7877_chip_info, }, #endif -#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) +#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI) { .modalias = "ad7879", .platform_data = &bfin_ad7879_ts_info, @@ -774,46 +1124,283 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spi_ad7879_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) +#if IS_ENABLED(CONFIG_SPI_SPIDEV) { .modalias = "spidev", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spidev_chip_info, }, #endif -#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) +#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) { .modalias = "bfin-lq035q1-spi", .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 2, - .controller_data = &lq035q1_spi_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif -#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) +#if IS_ENABLED(CONFIG_ENC28J60) { .modalias = "enc28j60", .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ .irq = IRQ_PF6, .bus_num = 0, - .chip_select = 0, /* GPIO controlled SSEL */ + .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */ .controller_data = &enc28j60_spi_chip_info, .mode = SPI_MODE_0, }, #endif +#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI) + { + .modalias = "adxl34x", + .platform_data = &adxl34x_info, + .irq = IRQ_PF6, + .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 2, + .mode = SPI_MODE_3, + }, +#endif +#if IS_ENABLED(CONFIG_ADF702X) + { + .modalias = "adf702x", + .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */ + .platform_data = &adf7021_platform_data, + .mode = SPI_MODE_0, + }, +#endif +#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846) + { + .modalias = "ads7846", + .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .irq = IRQ_PF6, + .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */ + .platform_data = &ad7873_pdata, + .mode = SPI_MODE_0, + }, +#endif +#if IS_ENABLED(CONFIG_AD7476) + { + .modalias = "ad7476", /* Name of spi_driver for this device */ + .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, /* Framework bus number */ + .chip_select = 1, /* Framework chip select. */ + .platform_data = NULL, /* No spi_driver specific config */ + .controller_data = &spi_ad7476_chip_info, + .mode = SPI_MODE_3, + }, +#endif +#if IS_ENABLED(CONFIG_ADE7753) + { + .modalias = "ade7753", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_1, + }, +#endif +#if IS_ENABLED(CONFIG_ADE7754) + { + .modalias = "ade7754", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_1, + }, +#endif +#if IS_ENABLED(CONFIG_ADE7758) + { + .modalias = "ade7758", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_1, + }, +#endif +#if IS_ENABLED(CONFIG_ADE7759) + { + .modalias = "ade7759", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_1, + }, +#endif +#if IS_ENABLED(CONFIG_ADE7854_SPI) + { + .modalias = "ade7854", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + }, +#endif +#if IS_ENABLED(CONFIG_ADIS16060) + { + .modalias = "adis16060_r", + .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = MAX_CTRL_CS + 1, /* CS for read, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_0, + }, + { + .modalias = "adis16060_w", + .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 2, /* CS for write, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_1, + }, +#endif +#if IS_ENABLED(CONFIG_ADIS16130) + { + .modalias = "adis16130", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS for read, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + }, +#endif +#if IS_ENABLED(CONFIG_ADIS16201) + { + .modalias = "adis16201", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if IS_ENABLED(CONFIG_ADIS16203) + { + .modalias = "adis16203", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if IS_ENABLED(CONFIG_ADIS16204) + { + .modalias = "adis16204", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if IS_ENABLED(CONFIG_ADIS16209) + { + .modalias = "adis16209", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if IS_ENABLED(CONFIG_ADIS16220) + { + .modalias = "adis16220", + .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if IS_ENABLED(CONFIG_ADIS16240) + { + .modalias = "adis16240", + .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if IS_ENABLED(CONFIG_ADIS16260) + { + .modalias = "adis16260", + .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if IS_ENABLED(CONFIG_ADIS16261) + { + .modalias = "adis16261", + .max_speed_hz = 2500000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + }, +#endif +#if IS_ENABLED(CONFIG_ADIS16300) + { + .modalias = "adis16300", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if IS_ENABLED(CONFIG_ADIS16350) + { + .modalias = "adis16364", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if IS_ENABLED(CONFIG_ADIS16400) + { + .modalias = "adis16400", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + }, +#endif }; -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) /* SPI controller data */ static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, + .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, .enable_dma = 1, /* master has the ability to do dma transfer */ .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, }; @@ -828,6 +1415,11 @@ static struct resource bfin_spi0_resource[] = { [1] = { .start = CH_SPI, .end = CH_SPI, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = IRQ_SPI, + .end = IRQ_SPI, .flags = IORESOURCE_IRQ, }, }; @@ -843,25 +1435,85 @@ static struct platform_device bfin_spi0_device = { }; #endif /* spi master and devices */ -#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) -static struct platform_device bfin_fb_device = { - .name = "bf537-lq035", +#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT) + +/* SPORT SPI controller data */ +static struct bfin5xx_spi_master bfin_sport_spi0_info = { + .num_chipselect = MAX_BLACKFIN_GPIOS, + .enable_dma = 0, /* master don't support DMA */ + .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI, + P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0}, }; -#endif -#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE) -static struct platform_device bfin_fb_adv7393_device = { - .name = "bfin-adv7393", +static struct resource bfin_sport_spi0_resource[] = { + [0] = { + .start = SPORT0_TCR1, + .end = SPORT0_TCR1 + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SPORT0_ERROR, + .end = IRQ_SPORT0_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_sport_spi0_device = { + .name = "bfin-sport-spi", + .id = 1, /* Bus number */ + .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource), + .resource = bfin_sport_spi0_resource, + .dev = { + .platform_data = &bfin_sport_spi0_info, /* Passed to driver */ + }, +}; + +static struct bfin5xx_spi_master bfin_sport_spi1_info = { + .num_chipselect = MAX_BLACKFIN_GPIOS, + .enable_dma = 0, /* master don't support DMA */ + .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI, + P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0}, +}; + +static struct resource bfin_sport_spi1_resource[] = { + [0] = { + .start = SPORT1_TCR1, + .end = SPORT1_TCR1 + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SPORT1_ERROR, + .end = IRQ_SPORT1_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_sport_spi1_device = { + .name = "bfin-sport-spi", + .id = 2, /* Bus number */ + .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource), + .resource = bfin_sport_spi1_resource, + .dev = { + .platform_data = &bfin_sport_spi1_info, /* Passed to driver */ + }, +}; + +#endif /* sport spi master and devices */ + +#if IS_ENABLED(CONFIG_FB_BF537_LQ035) +static struct platform_device bfin_fb_device = { + .name = "bf537_lq035", }; #endif -#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) +#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) #include <asm/bfin-lq035q1.h> static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = { - .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB, - .use_bl = 0, /* let something else control the LCD Blacklight */ - .gpio_bl = GPIO_PF7, + .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB, + .ppi_mode = USE_RGB565_16_BIT_PPI, + .use_bl = 0, /* let something else control the LCD Blacklight */ + .gpio_bl = GPIO_PF7, }; static struct resource bfin_lq035q1_resources[] = { @@ -875,41 +1527,189 @@ static struct resource bfin_lq035q1_resources[] = { static struct platform_device bfin_lq035q1_device = { .name = "bfin-lq035q1", .id = -1, - .num_resources = ARRAY_SIZE(bfin_lq035q1_resources), - .resource = bfin_lq035q1_resources, + .num_resources = ARRAY_SIZE(bfin_lq035q1_resources), + .resource = bfin_lq035q1_resources, .dev = { .platform_data = &bfin_lq035q1_data, }, }; #endif -#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) -static struct resource bfin_uart_resources[] = { +#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE) +#include <linux/videodev2.h> +#include <media/blackfin/bfin_capture.h> +#include <media/blackfin/ppi.h> + +static const unsigned short ppi_req[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, + P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, + P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, + 0, +}; + +static const struct ppi_info ppi_info = { + .type = PPI_TYPE_PPI, + .dma_ch = CH_PPI, + .irq_err = IRQ_PPI_ERROR, + .base = (void __iomem *)PPI_CONTROL, + .pin_req = ppi_req, +}; + +#if IS_ENABLED(CONFIG_VIDEO_VS6624) +static struct v4l2_input vs6624_inputs[] = { + { + .index = 0, + .name = "Camera", + .type = V4L2_INPUT_TYPE_CAMERA, + .std = V4L2_STD_UNKNOWN, + }, +}; + +static struct bcap_route vs6624_routes[] = { + { + .input = 0, + .output = 0, + }, +}; + +static const unsigned vs6624_ce_pin = GPIO_PF10; + +static struct bfin_capture_config bfin_capture_data = { + .card_name = "BF537", + .inputs = vs6624_inputs, + .num_inputs = ARRAY_SIZE(vs6624_inputs), + .routes = vs6624_routes, + .i2c_adapter_id = 0, + .board_info = { + .type = "vs6624", + .addr = 0x10, + .platform_data = (void *)&vs6624_ce_pin, + }, + .ppi_info = &ppi_info, + .ppi_control = (PACK_EN | DLEN_8 | XFR_TYPE | 0x0020), +}; +#endif + +static struct platform_device bfin_capture_device = { + .name = "bfin_capture", + .dev = { + .platform_data = &bfin_capture_data, + }, +}; +#endif + +#if IS_ENABLED(CONFIG_SERIAL_BFIN) #ifdef CONFIG_SERIAL_BFIN_UART0 +static struct resource bfin_uart0_resources[] = { { - .start = 0xFFC00400, - .end = 0xFFC004FF, + .start = UART0_THR, + .end = UART0_GCTL+2, .flags = IORESOURCE_MEM, }, + { + .start = IRQ_UART0_TX, + .end = IRQ_UART0_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_ERROR, + .end = IRQ_UART0_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_TX, + .end = CH_UART0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX, + .flags = IORESOURCE_DMA, + }, +#ifdef CONFIG_BFIN_UART0_CTSRTS + { /* CTS pin */ + .start = GPIO_PG7, + .end = GPIO_PG7, + .flags = IORESOURCE_IO, + }, + { /* RTS pin */ + .start = GPIO_PG6, + .end = GPIO_PG6, + .flags = IORESOURCE_IO, + }, +#endif +}; + +static unsigned short bfin_uart0_peripherals[] = { + P_UART0_TX, P_UART0_RX, 0 +}; + +static struct platform_device bfin_uart0_device = { + .name = "bfin-uart", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_uart0_resources), + .resource = bfin_uart0_resources, + .dev = { + .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ + }, +}; #endif #ifdef CONFIG_SERIAL_BFIN_UART1 +static struct resource bfin_uart1_resources[] = { { - .start = 0xFFC02000, - .end = 0xFFC020FF, + .start = UART1_THR, + .end = UART1_GCTL+2, .flags = IORESOURCE_MEM, }, -#endif + { + .start = IRQ_UART1_TX, + .end = IRQ_UART1_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_ERROR, + .end = IRQ_UART1_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_TX, + .end = CH_UART1_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX, + .flags = IORESOURCE_DMA, + }, }; -static struct platform_device bfin_uart_device = { +static unsigned short bfin_uart1_peripherals[] = { + P_UART1_TX, P_UART1_RX, 0 +}; + +static struct platform_device bfin_uart1_device = { .name = "bfin-uart", .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart_resources), - .resource = bfin_uart_resources, + .num_resources = ARRAY_SIZE(bfin_uart1_resources), + .resource = bfin_uart1_resources, + .dev = { + .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ + }, }; #endif +#endif -#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +#if IS_ENABLED(CONFIG_BFIN_SIR) #ifdef CONFIG_BFIN_SIR0 static struct resource bfin_sir0_resources[] = { { @@ -964,7 +1764,9 @@ static struct platform_device bfin_sir1_device = { #endif #endif -#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -983,12 +1785,13 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif -#if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE) -#include <linux/input.h> -#include <linux/i2c/adp5588_keys.h> +#if IS_ENABLED(CONFIG_KEYBOARD_ADP5588) static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = { [0] = KEY_GRAVE, [1] = KEY_1, @@ -1073,58 +1876,593 @@ static struct adp5588_kpad_platform_data adp5588_kpad_data = { }; #endif +#if IS_ENABLED(CONFIG_PMIC_ADP5520) +#include <linux/mfd/adp5520.h> + + /* + * ADP5520/5501 Backlight Data + */ + +static struct adp5520_backlight_platform_data adp5520_backlight_data = { + .fade_in = ADP5520_FADE_T_1200ms, + .fade_out = ADP5520_FADE_T_1200ms, + .fade_led_law = ADP5520_BL_LAW_LINEAR, + .en_ambl_sens = 1, + .abml_filt = ADP5520_BL_AMBL_FILT_640ms, + .l1_daylight_max = ADP5520_BL_CUR_mA(15), + .l1_daylight_dim = ADP5520_BL_CUR_mA(0), + .l2_office_max = ADP5520_BL_CUR_mA(7), + .l2_office_dim = ADP5520_BL_CUR_mA(0), + .l3_dark_max = ADP5520_BL_CUR_mA(3), + .l3_dark_dim = ADP5520_BL_CUR_mA(0), + .l2_trip = ADP5520_L2_COMP_CURR_uA(700), + .l2_hyst = ADP5520_L2_COMP_CURR_uA(50), + .l3_trip = ADP5520_L3_COMP_CURR_uA(80), + .l3_hyst = ADP5520_L3_COMP_CURR_uA(20), +}; + + /* + * ADP5520/5501 LEDs Data + */ + +static struct led_info adp5520_leds[] = { + { + .name = "adp5520-led1", + .default_trigger = "none", + .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms, + }, +#ifdef ADP5520_EN_ALL_LEDS + { + .name = "adp5520-led2", + .default_trigger = "none", + .flags = FLAG_ID_ADP5520_LED2_ADP5501_LED1, + }, + { + .name = "adp5520-led3", + .default_trigger = "none", + .flags = FLAG_ID_ADP5520_LED3_ADP5501_LED2, + }, +#endif +}; + +static struct adp5520_leds_platform_data adp5520_leds_data = { + .num_leds = ARRAY_SIZE(adp5520_leds), + .leds = adp5520_leds, + .fade_in = ADP5520_FADE_T_600ms, + .fade_out = ADP5520_FADE_T_600ms, + .led_on_time = ADP5520_LED_ONT_600ms, +}; + + /* + * ADP5520 GPIO Data + */ + +static struct adp5520_gpio_platform_data adp5520_gpio_data = { + .gpio_start = 50, + .gpio_en_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2, + .gpio_pullup_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2, +}; + + /* + * ADP5520 Keypad Data + */ + +static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = { + [ADP5520_KEY(0, 0)] = KEY_GRAVE, + [ADP5520_KEY(0, 1)] = KEY_1, + [ADP5520_KEY(0, 2)] = KEY_2, + [ADP5520_KEY(0, 3)] = KEY_3, + [ADP5520_KEY(1, 0)] = KEY_4, + [ADP5520_KEY(1, 1)] = KEY_5, + [ADP5520_KEY(1, 2)] = KEY_6, + [ADP5520_KEY(1, 3)] = KEY_7, + [ADP5520_KEY(2, 0)] = KEY_8, + [ADP5520_KEY(2, 1)] = KEY_9, + [ADP5520_KEY(2, 2)] = KEY_0, + [ADP5520_KEY(2, 3)] = KEY_MINUS, + [ADP5520_KEY(3, 0)] = KEY_EQUAL, + [ADP5520_KEY(3, 1)] = KEY_BACKSLASH, + [ADP5520_KEY(3, 2)] = KEY_BACKSPACE, + [ADP5520_KEY(3, 3)] = KEY_ENTER, +}; + +static struct adp5520_keys_platform_data adp5520_keys_data = { + .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0, + .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0, + .keymap = adp5520_keymap, + .keymapsize = ARRAY_SIZE(adp5520_keymap), + .repeat = 0, +}; + + /* + * ADP5520/5501 Multifunction Device Init Data + */ + +static struct adp5520_platform_data adp5520_pdev_data = { + .backlight = &adp5520_backlight_data, + .leds = &adp5520_leds_data, + .gpio = &adp5520_gpio_data, + .keys = &adp5520_keys_data, +}; + +#endif + +#if IS_ENABLED(CONFIG_GPIO_ADP5588) +static struct adp5588_gpio_platform_data adp5588_gpio_data = { + .gpio_start = 50, + .pullup_dis_mask = 0, +}; +#endif + +#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8870) +#include <linux/i2c/adp8870.h> +static struct led_info adp8870_leds[] = { + { + .name = "adp8870-led7", + .default_trigger = "none", + .flags = ADP8870_LED_D7 | ADP8870_LED_OFFT_600ms, + }, +}; + + +static struct adp8870_backlight_platform_data adp8870_pdata = { + .bl_led_assign = ADP8870_BL_D1 | ADP8870_BL_D2 | ADP8870_BL_D3 | + ADP8870_BL_D4 | ADP8870_BL_D5 | ADP8870_BL_D6, /* 1 = Backlight 0 = Individual LED */ + .pwm_assign = 0, /* 1 = Enables PWM mode */ + + .bl_fade_in = ADP8870_FADE_T_1200ms, /* Backlight Fade-In Timer */ + .bl_fade_out = ADP8870_FADE_T_1200ms, /* Backlight Fade-Out Timer */ + .bl_fade_law = ADP8870_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */ + + .en_ambl_sens = 1, /* 1 = enable ambient light sensor */ + .abml_filt = ADP8870_BL_AMBL_FILT_320ms, /* Light sensor filter time */ + + .l1_daylight_max = ADP8870_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ + .l1_daylight_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ + .l2_bright_max = ADP8870_BL_CUR_mA(14), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ + .l2_bright_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ + .l3_office_max = ADP8870_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ + .l3_office_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ + .l4_indoor_max = ADP8870_BL_CUR_mA(3), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ + .l4_indor_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ + .l5_dark_max = ADP8870_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ + .l5_dark_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ + + .l2_trip = ADP8870_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */ + .l2_hyst = ADP8870_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */ + .l3_trip = ADP8870_L3_COMP_CURR_uA(389), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */ + .l3_hyst = ADP8870_L3_COMP_CURR_uA(54), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */ + .l4_trip = ADP8870_L4_COMP_CURR_uA(167), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */ + .l4_hyst = ADP8870_L4_COMP_CURR_uA(16), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */ + .l5_trip = ADP8870_L5_COMP_CURR_uA(43), /* use L5_COMP_CURR_uA(I) 0 <= I <= 138 uA */ + .l5_hyst = ADP8870_L5_COMP_CURR_uA(11), /* use L6_COMP_CURR_uA(I) 0 <= I <= 138 uA */ + + .leds = adp8870_leds, + .num_leds = ARRAY_SIZE(adp8870_leds), + .led_fade_law = ADP8870_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */ + .led_fade_in = ADP8870_FADE_T_600ms, + .led_fade_out = ADP8870_FADE_T_600ms, + .led_on_time = ADP8870_LED_ONT_200ms, +}; +#endif + +#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8860) +#include <linux/i2c/adp8860.h> +static struct led_info adp8860_leds[] = { + { + .name = "adp8860-led7", + .default_trigger = "none", + .flags = ADP8860_LED_D7 | ADP8860_LED_OFFT_600ms, + }, +}; + +static struct adp8860_backlight_platform_data adp8860_pdata = { + .bl_led_assign = ADP8860_BL_D1 | ADP8860_BL_D2 | ADP8860_BL_D3 | + ADP8860_BL_D4 | ADP8860_BL_D5 | ADP8860_BL_D6, /* 1 = Backlight 0 = Individual LED */ + + .bl_fade_in = ADP8860_FADE_T_1200ms, /* Backlight Fade-In Timer */ + .bl_fade_out = ADP8860_FADE_T_1200ms, /* Backlight Fade-Out Timer */ + .bl_fade_law = ADP8860_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */ + + .en_ambl_sens = 1, /* 1 = enable ambient light sensor */ + .abml_filt = ADP8860_BL_AMBL_FILT_320ms, /* Light sensor filter time */ + + .l1_daylight_max = ADP8860_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ + .l1_daylight_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ + .l2_office_max = ADP8860_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ + .l2_office_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ + .l3_dark_max = ADP8860_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ + .l3_dark_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ + + .l2_trip = ADP8860_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */ + .l2_hyst = ADP8860_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */ + .l3_trip = ADP8860_L3_COMP_CURR_uA(43), /* use L3_COMP_CURR_uA(I) 0 <= I <= 138 uA */ + .l3_hyst = ADP8860_L3_COMP_CURR_uA(11), /* use L3_COMP_CURR_uA(I) 0 <= I <= 138 uA */ + + .leds = adp8860_leds, + .num_leds = ARRAY_SIZE(adp8860_leds), + .led_fade_law = ADP8860_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */ + .led_fade_in = ADP8860_FADE_T_600ms, + .led_fade_out = ADP8860_FADE_T_600ms, + .led_on_time = ADP8860_LED_ONT_200ms, +}; +#endif + +#if IS_ENABLED(CONFIG_REGULATOR_AD5398) +static struct regulator_consumer_supply ad5398_consumer = { + .supply = "current", +}; + +static struct regulator_init_data ad5398_regulator_data = { + .constraints = { + .name = "current range", + .max_uA = 120000, + .valid_ops_mask = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &ad5398_consumer, +}; + +#if IS_ENABLED(CONFIG_REGULATOR_VIRTUAL_CONSUMER) +static struct platform_device ad5398_virt_consumer_device = { + .name = "reg-virt-consumer", + .id = 0, + .dev = { + .platform_data = "current", /* Passed to driver */ + }, +}; +#endif +#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER) +static struct regulator_bulk_data ad5398_bulk_data = { + .supply = "current", +}; + +static struct regulator_userspace_consumer_data ad5398_userspace_comsumer_data = { + .name = "ad5398", + .num_supplies = 1, + .supplies = &ad5398_bulk_data, +}; + +static struct platform_device ad5398_userspace_consumer_device = { + .name = "reg-userspace-consumer", + .id = 0, + .dev = { + .platform_data = &ad5398_userspace_comsumer_data, + }, +}; +#endif +#endif + +#if IS_ENABLED(CONFIG_ADT7410) +/* INT bound temperature alarm event. line 1 */ +static unsigned long adt7410_platform_data[2] = { + IRQ_PG4, IRQF_TRIGGER_LOW, +}; +#endif + +#if IS_ENABLED(CONFIG_ADT7316_I2C) +/* INT bound temperature alarm event. line 1 */ +static unsigned long adt7316_i2c_data[2] = { + IRQF_TRIGGER_LOW, /* interrupt flags */ + GPIO_PF4, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */ +}; +#endif + static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -#if defined(CONFIG_JOYSTICK_AD7142) || defined(CONFIG_JOYSTICK_AD7142_MODULE) +#ifdef CONFIG_SND_SOC_AD193X_I2C + { + I2C_BOARD_INFO("ad1937", 0x04), + }, +#endif + +#if IS_ENABLED(CONFIG_SND_SOC_ADAV80X) + { + I2C_BOARD_INFO("adav803", 0x10), + }, +#endif + +#if IS_ENABLED(CONFIG_INPUT_AD714X_I2C) + { + I2C_BOARD_INFO("ad7142_captouch", 0x2C), + .irq = IRQ_PG5, + .platform_data = (void *)&ad7142_i2c_platform_data, + }, +#endif + +#if IS_ENABLED(CONFIG_AD7150) + { + I2C_BOARD_INFO("ad7150", 0x48), + .irq = IRQ_PG5, /* fixme: use real interrupt number */ + }, +#endif + +#if IS_ENABLED(CONFIG_AD7152) + { + I2C_BOARD_INFO("ad7152", 0x48), + }, +#endif + +#if IS_ENABLED(CONFIG_AD774X) { - I2C_BOARD_INFO("ad7142_joystick", 0x2C), - .irq = IRQ_PF5, + I2C_BOARD_INFO("ad774x", 0x48), }, #endif -#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) + +#if IS_ENABLED(CONFIG_ADE7854_I2C) + { + I2C_BOARD_INFO("ade7854", 0x38), + }, +#endif + +#if IS_ENABLED(CONFIG_SENSORS_LM75) + { + I2C_BOARD_INFO("adt75", 0x9), + .irq = IRQ_PG5, + }, +#endif + +#if IS_ENABLED(CONFIG_ADT7410) + { + I2C_BOARD_INFO("adt7410", 0x48), + /* CT critical temperature event. line 0 */ + .irq = IRQ_PG5, + .platform_data = (void *)&adt7410_platform_data, + }, +#endif + +#if IS_ENABLED(CONFIG_AD7291) + { + I2C_BOARD_INFO("ad7291", 0x20), + .irq = IRQ_PG5, + }, +#endif + +#if IS_ENABLED(CONFIG_ADT7316_I2C) + { + I2C_BOARD_INFO("adt7316", 0x48), + .irq = IRQ_PG6, + .platform_data = (void *)&adt7316_i2c_data, + }, +#endif + +#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) { I2C_BOARD_INFO("pcf8574_lcd", 0x22), }, #endif -#if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE) +#if IS_ENABLED(CONFIG_INPUT_PCF8574) { I2C_BOARD_INFO("pcf8574_keypad", 0x27), .irq = IRQ_PG6, }, #endif -#if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE) +#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C) { I2C_BOARD_INFO("ad7879", 0x2F), .irq = IRQ_PG5, .platform_data = (void *)&bfin_ad7879_ts_info, }, #endif -#if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE) +#if IS_ENABLED(CONFIG_KEYBOARD_ADP5588) { I2C_BOARD_INFO("adp5588-keys", 0x34), .irq = IRQ_PG0, .platform_data = (void *)&adp5588_kpad_data, }, #endif +#if IS_ENABLED(CONFIG_PMIC_ADP5520) + { + I2C_BOARD_INFO("pmic-adp5520", 0x32), + .irq = IRQ_PG0, + .platform_data = (void *)&adp5520_pdev_data, + }, +#endif +#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C) + { + I2C_BOARD_INFO("adxl34x", 0x53), + .irq = IRQ_PG3, + .platform_data = (void *)&adxl34x_info, + }, +#endif +#if IS_ENABLED(CONFIG_GPIO_ADP5588) + { + I2C_BOARD_INFO("adp5588-gpio", 0x34), + .platform_data = (void *)&adp5588_gpio_data, + }, +#endif +#if IS_ENABLED(CONFIG_FB_BFIN_7393) + { + I2C_BOARD_INFO("bfin-adv7393", 0x2B), + }, +#endif +#if IS_ENABLED(CONFIG_FB_BF537_LQ035) + { + I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2F), + }, +#endif +#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8870) + { + I2C_BOARD_INFO("adp8870", 0x2B), + .platform_data = (void *)&adp8870_pdata, + }, +#endif +#if IS_ENABLED(CONFIG_SND_SOC_ADAU1371) + { + I2C_BOARD_INFO("adau1371", 0x1A), + }, +#endif +#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761) + { + I2C_BOARD_INFO("adau1761", 0x38), + }, +#endif +#if IS_ENABLED(CONFIG_SND_SOC_ADAU1361) + { + I2C_BOARD_INFO("adau1361", 0x38), + }, +#endif +#if IS_ENABLED(CONFIG_SND_SOC_ADAU1701) + { + I2C_BOARD_INFO("adau1701", 0x34), + }, +#endif +#if IS_ENABLED(CONFIG_AD525X_DPOT) + { + I2C_BOARD_INFO("ad5258", 0x18), + }, +#endif +#if IS_ENABLED(CONFIG_SND_SOC_SSM2602) + { + I2C_BOARD_INFO("ssm2602", 0x1b), + }, +#endif +#if IS_ENABLED(CONFIG_REGULATOR_AD5398) + { + I2C_BOARD_INFO("ad5398", 0xC), + .platform_data = (void *)&ad5398_regulator_data, + }, +#endif +#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8860) + { + I2C_BOARD_INFO("adp8860", 0x2A), + .platform_data = (void *)&adp8860_pdata, + }, +#endif +#if IS_ENABLED(CONFIG_SND_SOC_ADAU1373) + { + I2C_BOARD_INFO("adau1373", 0x1A), + }, +#endif +#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) + { + I2C_BOARD_INFO("ad5252", 0x2e), + }, +#endif +}; +#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) \ +|| IS_ENABLED(CONFIG_BFIN_SPORT) +unsigned short bfin_sport0_peripherals[] = { + P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, + P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 +}; +#endif +#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART +static struct resource bfin_sport0_uart_resources[] = { + { + .start = SPORT0_TCR1, + .end = SPORT0_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT0_RX, + .end = IRQ_SPORT0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT0_ERROR, + .end = IRQ_SPORT0_ERROR, + .flags = IORESOURCE_IRQ, + }, }; -#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) static struct platform_device bfin_sport0_uart_device = { .name = "bfin-sport-uart", .id = 0, + .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), + .resource = bfin_sport0_uart_resources, + .dev = { + .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART +static struct resource bfin_sport1_uart_resources[] = { + { + .start = SPORT1_TCR1, + .end = SPORT1_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT1_RX, + .end = IRQ_SPORT1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT1_ERROR, + .end = IRQ_SPORT1_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static unsigned short bfin_sport1_peripherals[] = { + P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { .name = "bfin-sport-uart", .id = 1, + .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), + .resource = bfin_sport1_uart_resources, + .dev = { + .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ + }, }; #endif +#endif +#if IS_ENABLED(CONFIG_BFIN_SPORT) +static struct resource bfin_sport0_resources[] = { + { + .start = SPORT0_TCR1, + .end = SPORT0_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT0_RX, + .end = IRQ_SPORT0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT0_TX, + .end = IRQ_SPORT0_TX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT0_ERROR, + .end = IRQ_SPORT0_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_SPORT0_TX, + .end = CH_SPORT0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_SPORT0_RX, + .end = CH_SPORT0_RX, + .flags = IORESOURCE_DMA, + }, +}; +static struct platform_device bfin_sport0_device = { + .name = "bfin_sport_raw", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sport0_resources), + .resource = bfin_sport0_resources, + .dev = { + .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ + }, +}; +#endif +#if IS_ENABLED(CONFIG_PATA_PLATFORM) +#define CF_IDE_NAND_CARD_USE_HDD_INTERFACE +/* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */ -#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) +#ifdef CF_IDE_NAND_CARD_USE_HDD_INTERFACE #define PATA_INT IRQ_PF5 - static struct pata_platform_info bfin_pata_platform_data = { .ioport_shift = 1, - .irq_flags = IRQF_TRIGGER_HIGH | IRQF_DISABLED, + .irq_flags = IRQF_TRIGGER_HIGH, }; static struct resource bfin_pata_resources[] = { @@ -1144,6 +2482,26 @@ static struct resource bfin_pata_resources[] = { .flags = IORESOURCE_IRQ, }, }; +#elif defined(CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE) +static struct pata_platform_info bfin_pata_platform_data = { + .ioport_shift = 0, +}; +/* CompactFlash Storage Card Memory Mapped Addressing + * /REG = A11 = 1 + */ +static struct resource bfin_pata_resources[] = { + { + .start = 0x20211800, + .end = 0x20211807, + .flags = IORESOURCE_MEM, + }, + { + .start = 0x2021180E, /* Device Ctl */ + .end = 0x2021180E, + .flags = IORESOURCE_MEM, + }, +}; +#endif static struct platform_device bfin_pata_device = { .name = "pata_platform", @@ -1183,72 +2541,303 @@ static struct platform_device bfin_dpmc = { }, }; +#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \ + IS_ENABLED(CONFIG_SND_BF5XX_AC97) + +#define SPORT_REQ(x) \ + [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \ + P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0} + +static const u16 bfin_snd_pin[][7] = { + SPORT_REQ(0), + SPORT_REQ(1), +}; + +static struct bfin_snd_platform_data bfin_snd_data[] = { + { + .pin_req = &bfin_snd_pin[0][0], + }, + { + .pin_req = &bfin_snd_pin[1][0], + }, +}; + +#define BFIN_SND_RES(x) \ + [x] = { \ + { \ + .start = SPORT##x##_TCR1, \ + .end = SPORT##x##_TCR1, \ + .flags = IORESOURCE_MEM \ + }, \ + { \ + .start = CH_SPORT##x##_RX, \ + .end = CH_SPORT##x##_RX, \ + .flags = IORESOURCE_DMA, \ + }, \ + { \ + .start = CH_SPORT##x##_TX, \ + .end = CH_SPORT##x##_TX, \ + .flags = IORESOURCE_DMA, \ + }, \ + { \ + .start = IRQ_SPORT##x##_ERROR, \ + .end = IRQ_SPORT##x##_ERROR, \ + .flags = IORESOURCE_IRQ, \ + } \ + } + +static struct resource bfin_snd_resources[][4] = { + BFIN_SND_RES(0), + BFIN_SND_RES(1), +}; +#endif + +#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) +static struct platform_device bfin_i2s_pcm = { + .name = "bfin-i2s-pcm-audio", + .id = -1, +}; +#endif + +#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) +static struct platform_device bfin_ac97_pcm = { + .name = "bfin-ac97-pcm-audio", + .id = -1, +}; +#endif + +#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) +static const char * const ad1836_link[] = { + "bfin-i2s.0", + "spi0.4", +}; +static struct platform_device bfin_ad1836_machine = { + .name = "bfin-snd-ad1836", + .id = -1, + .dev = { + .platform_data = (void *)ad1836_link, + }, +}; +#endif + +#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311) +static const unsigned ad73311_gpio[] = { + GPIO_PF4, +}; + +static struct platform_device bfin_ad73311_machine = { + .name = "bfin-snd-ad73311", + .id = 1, + .dev = { + .platform_data = (void *)ad73311_gpio, + }, +}; +#endif + +#if IS_ENABLED(CONFIG_SND_SOC_AD73311) +static struct platform_device bfin_ad73311_codec_device = { + .name = "ad73311", + .id = -1, +}; +#endif + +#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X) +static struct platform_device bfin_eval_adav801_device = { + .name = "bfin-eval-adav801", + .id = -1, +}; +#endif + +#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S) +static struct platform_device bfin_i2s = { + .name = "bfin-i2s", + .id = CONFIG_SND_BF5XX_SPORT_NUM, + .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), + .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], + .dev = { + .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], + }, +}; +#endif + +#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97) +static struct platform_device bfin_ac97 = { + .name = "bfin-ac97", + .id = CONFIG_SND_BF5XX_SPORT_NUM, + .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), + .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], + .dev = { + .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], + }, +}; +#endif + +#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE) +#define REGULATOR_ADP122 "adp122" +#define REGULATOR_ADP122_UV 2500000 + +static struct regulator_consumer_supply adp122_consumers = { + .supply = REGULATOR_ADP122, +}; + +static struct regulator_init_data adp_switch_regulator_data = { + .constraints = { + .name = REGULATOR_ADP122, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .min_uV = REGULATOR_ADP122_UV, + .max_uV = REGULATOR_ADP122_UV, + .min_uA = 0, + .max_uA = 300000, + }, + .num_consumer_supplies = 1, /* only 1 */ + .consumer_supplies = &adp122_consumers, +}; + +static struct fixed_voltage_config adp_switch_pdata = { + .supply_name = REGULATOR_ADP122, + .microvolts = REGULATOR_ADP122_UV, + .gpio = GPIO_PF2, + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &adp_switch_regulator_data, +}; + +static struct platform_device adp_switch_device = { + .name = "reg-fixed-voltage", + .id = 0, + .dev = { + .platform_data = &adp_switch_pdata, + }, +}; + +#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER) +static struct regulator_bulk_data adp122_bulk_data = { + .supply = REGULATOR_ADP122, +}; + +static struct regulator_userspace_consumer_data adp122_userspace_comsumer_data = { + .name = REGULATOR_ADP122, + .num_supplies = 1, + .supplies = &adp122_bulk_data, +}; + +static struct platform_device adp122_userspace_consumer_device = { + .name = "reg-userspace-consumer", + .id = 0, + .dev = { + .platform_data = &adp122_userspace_comsumer_data, + }, +}; +#endif +#endif + +#if IS_ENABLED(CONFIG_IIO_GPIO_TRIGGER) + +static struct resource iio_gpio_trigger_resources[] = { + [0] = { + .start = IRQ_PF5, + .end = IRQ_PF5, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, + }, +}; + +static struct platform_device iio_gpio_trigger = { + .name = "iio_gpio_trigger", + .num_resources = ARRAY_SIZE(iio_gpio_trigger_resources), + .resource = iio_gpio_trigger_resources, +}; +#endif + +#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373) +static struct platform_device bf5xx_adau1373_device = { + .name = "bfin-eval-adau1373", +}; +#endif + +#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701) +static struct platform_device bf5xx_adau1701_device = { + .name = "bfin-eval-adau1701", +}; +#endif + static struct platform_device *stamp_devices[] __initdata = { &bfin_dpmc, - -#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) +#if IS_ENABLED(CONFIG_BFIN_SPORT) + &bfin_sport0_device, +#endif +#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA) &bfin_pcmcia_cf_device, #endif -#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) &rtc_device, #endif -#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_SL811_HCD) &sl811_hcd_device, #endif -#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) &isp1362_hcd_device, #endif -#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) &bfin_isp1760_device, #endif -#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) +#if IS_ENABLED(CONFIG_SMC91X) &smc91x_device, #endif -#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) +#if IS_ENABLED(CONFIG_DM9000) &dm9000_device, #endif -#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE) - &ax88180_device, +#if IS_ENABLED(CONFIG_CAN_BFIN) + &bfin_can_device, #endif -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) +#if IS_ENABLED(CONFIG_BFIN_MAC) &bfin_mii_bus, &bfin_mac_device, #endif -#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) +#if IS_ENABLED(CONFIG_USB_NET2272) &net2272_bfin_device, #endif -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) &bfin_spi0_device, #endif -#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) +#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT) + &bfin_sport_spi0_device, + &bfin_sport_spi1_device, +#endif + +#if IS_ENABLED(CONFIG_FB_BF537_LQ035) &bfin_fb_device, #endif -#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) +#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) &bfin_lq035q1_device, #endif -#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE) - &bfin_fb_adv7393_device, +#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE) + &bfin_capture_device, #endif -#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) - &bfin_uart_device, +#if IS_ENABLED(CONFIG_SERIAL_BFIN) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif #endif -#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +#if IS_ENABLED(CONFIG_BFIN_SIR) #ifdef CONFIG_BFIN_SIR0 &bfin_sir0_device, #endif @@ -1257,52 +2846,160 @@ static struct platform_device *stamp_devices[] __initdata = { #endif #endif -#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) &i2c_bfin_twi_device, #endif -#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) +#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART &bfin_sport0_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART &bfin_sport1_uart_device, #endif +#endif -#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) +#if IS_ENABLED(CONFIG_PATA_PLATFORM) &bfin_pata_device, #endif -#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) &bfin_device_gpiokeys, #endif - &bfin_gpios_device, - -#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) +#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM) &bfin_async_nand_device, #endif -#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) +#if IS_ENABLED(CONFIG_MTD_PHYSMAP) &stamp_flash_device, #endif + +#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) + &bfin_i2s_pcm, +#endif + +#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) + &bfin_ac97_pcm, +#endif + +#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) + &bfin_ad1836_machine, +#endif + +#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311) + &bfin_ad73311_machine, +#endif + +#if IS_ENABLED(CONFIG_SND_SOC_AD73311) + &bfin_ad73311_codec_device, +#endif + +#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S) + &bfin_i2s, +#endif + +#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97) + &bfin_ac97, +#endif + +#if IS_ENABLED(CONFIG_REGULATOR_AD5398) +#if IS_ENABLED(CONFIG_REGULATOR_VIRTUAL_CONSUMER) + &ad5398_virt_consumer_device, +#endif +#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER) + &ad5398_userspace_consumer_device, +#endif +#endif + +#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE) + &adp_switch_device, +#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER) + &adp122_userspace_consumer_device, +#endif +#endif + +#if IS_ENABLED(CONFIG_IIO_GPIO_TRIGGER) + &iio_gpio_trigger, +#endif + +#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373) + &bf5xx_adau1373_device, +#endif + +#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701) + &bf5xx_adau1701_device, +#endif + +#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X) + &bfin_eval_adav801_device, +#endif }; +static int __init net2272_init(void) +{ +#if IS_ENABLED(CONFIG_USB_NET2272) + int ret; + + ret = gpio_request(GPIO_PF6, "net2272"); + if (ret) + return ret; + + /* Reset the USB chip */ + gpio_direction_output(GPIO_PF6, 0); + mdelay(2); + gpio_set_value(GPIO_PF6, 1); +#endif + + return 0; +} + static int __init stamp_init(void) { printk(KERN_INFO "%s(): registering device resources\n", __func__); - i2c_register_board_info(0, bfin_i2c_board_info, - ARRAY_SIZE(bfin_i2c_board_info)); bfin_plat_nand_init(); + adf702x_mac_init(); platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); + i2c_register_board_info(0, bfin_i2c_board_info, + ARRAY_SIZE(bfin_i2c_board_info)); spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); -#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) - irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; -#endif + if (net2272_init()) + pr_warning("unable to configure net2272; it probably won't work\n"); return 0; } arch_initcall(stamp_init); + +static struct platform_device *stamp_early_devices[] __initdata = { +#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif +#endif + +#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART + &bfin_sport0_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART + &bfin_sport1_uart_device, +#endif +#endif +}; + +void __init native_machine_early_platform_add_devices(void) +{ + printk(KERN_INFO "register early platform devices\n"); + early_platform_add_devices(stamp_early_devices, + ARRAY_SIZE(stamp_early_devices)); +} + void native_machine_restart(char *cmd) { /* workaround reboot hang when booting from SPI */ @@ -1314,9 +3011,10 @@ void native_machine_restart(char *cmd) * Currently the MAC address is saved in Flash by U-Boot */ #define FLASH_MAC 0x203f0000 -void bfin_get_ether_addr(char *addr) +int bfin_get_ether_addr(char *addr) { *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC); *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4); + return 0; } EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c index 53ad10f3cd7..6b988ad653d 100644 --- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c @@ -1,60 +1,42 @@ /* - * File: arch/blackfin/mach-bf537/boards/tcm_bf537.c - * Based on: arch/blackfin/mach-bf533/boards/cm_bf537.c - * Author: Aidan Williams <aidan@nicta.com.au> + * Copyright 2004-2009 Analog Devices Inc. + * 2008-2009 Bluetechnix + * 2005 National ICT Australia (NICTA) + * Aidan Williams <aidan@nicta.com.au> * - * Created: 2005 - * Description: Board description file - * - * Modified: - * Copyright 2005 National ICT Australia (NICTA) - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Licensed under the GPL-2 or later. */ #include <linux/device.h> #include <linux/etherdevice.h> +#include <linux/export.h> #include <linux/platform_device.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> #include <linux/spi/spi.h> #include <linux/spi/flash.h> -#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) #include <linux/usb/isp1362.h> #endif #include <linux/ata_platform.h> #include <linux/irq.h> +#include <linux/gpio.h> #include <asm/dma.h> #include <asm/bfin5xx_spi.h> #include <asm/portmux.h> #include <asm/dpmc.h> +#include <linux/spi/mmc_spi.h> /* * Name the Board for the /proc/cpuinfo */ const char bfin_board_name[] = "Bluetechnix TCM BF537"; -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) /* all SPI peripherals info goes here */ -#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) +#if IS_ENABLED(CONFIG_MTD_M25P80) static struct mtd_partition bfin_spi_flash_partitions[] = { { .name = "bootloader(spi)", @@ -82,41 +64,17 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, -}; -#endif - -#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) -static struct bfin5xx_spi_chip ad1836_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; -#endif - -#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) -static struct bfin5xx_spi_chip ad9960_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, }; #endif -#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) +#if IS_ENABLED(CONFIG_MMC_SPI) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) +#if IS_ENABLED(CONFIG_MTD_M25P80) { /* the modalias must be the same as spi device driver name */ .modalias = "m25p80", /* Name of spi_driver for this device */ @@ -129,43 +87,21 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) +#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - -#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) - { - .modalias = "ad1836-spi", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, - .controller_data = &ad1836_spi_chip_info, + .chip_select = 4, }, #endif -#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) - { - .modalias = "ad9960-spi", - .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - .controller_data = &ad9960_spi_chip_info, - }, -#endif - -#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) +#if IS_ENABLED(CONFIG_MMC_SPI) { .modalias = "mmc_spi", .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = 5, + .chip_select = 1, .controller_data = &mmc_spi_chip_info, .mode = SPI_MODE_3, }, @@ -182,6 +118,11 @@ static struct resource bfin_spi0_resource[] = { [1] = { .start = CH_SPI, .end = CH_SPI, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = IRQ_SPI, + .end = IRQ_SPI, .flags = IORESOURCE_IRQ, } }; @@ -204,20 +145,28 @@ static struct platform_device bfin_spi0_device = { }; #endif /* spi master and devices */ -#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) static struct platform_device rtc_device = { .name = "rtc-bfin", .id = -1, }; #endif -#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) +#if IS_ENABLED(CONFIG_FB_HITACHI_TX09) static struct platform_device hitachi_fb_device = { .name = "hitachi-tx09", }; #endif -#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) +#if IS_ENABLED(CONFIG_SMC91X) +#include <linux/smc91x.h> + +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, + .leda = RPC_LED_100_10, + .ledb = RPC_LED_TX_RX, +}; + static struct resource smc91x_resources[] = { { .start = 0x20200300, @@ -235,10 +184,13 @@ static struct platform_device smc91x_device = { .id = 0, .num_resources = ARRAY_SIZE(smc91x_resources), .resource = smc91x_resources, + .dev = { + .platform_data = &smc91x_info, + }, }; #endif -#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) static struct resource isp1362_hcd_resources[] = { { .start = 0x20308000, @@ -251,7 +203,7 @@ static struct resource isp1362_hcd_resources[] = { }, { .start = IRQ_PG15, .end = IRQ_PG15, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; @@ -277,15 +229,15 @@ static struct platform_device isp1362_hcd_device = { }; #endif -#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) +#if IS_ENABLED(CONFIG_USB_NET2272) static struct resource net2272_bfin_resources[] = { { - .start = 0x20200000, - .end = 0x20200000 + 0x100, + .start = 0x20300000, + .end = 0x20300000 + 0x100, .flags = IORESOURCE_MEM, }, { - .start = IRQ_PH14, - .end = IRQ_PH14, + .start = IRQ_PG13, + .end = IRQ_PG13, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, }, }; @@ -298,20 +250,7 @@ static struct platform_device net2272_bfin_device = { }; #endif -static struct resource bfin_gpios_resources = { - .start = 0, - .end = MAX_BLACKFIN_GPIOS - 1, - .flags = IORESOURCE_IRQ, -}; - -static struct platform_device bfin_gpios_device = { - .name = "simple-gpio", - .id = -1, - .num_resources = 1, - .resource = &bfin_gpios_resources, -}; - -#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) +#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) static struct mtd_partition cm_partitions[] = { { .name = "bootloader(nor)", @@ -319,7 +258,7 @@ static struct mtd_partition cm_partitions[] = { .offset = 0, }, { .name = "linux kernel(nor)", - .size = 0xE0000, + .size = 0x100000, .offset = MTDPART_OFS_APPEND, }, { .name = "file system(nor)", @@ -360,28 +299,106 @@ static struct platform_device cm_flash_device = { }; #endif -#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) -static struct resource bfin_uart_resources[] = { +#if IS_ENABLED(CONFIG_SERIAL_BFIN) +#ifdef CONFIG_SERIAL_BFIN_UART0 +static struct resource bfin_uart0_resources[] = { { - .start = 0xFFC00400, - .end = 0xFFC004FF, + .start = UART0_THR, + .end = UART0_GCTL+2, .flags = IORESOURCE_MEM, - }, { - .start = 0xFFC02000, - .end = 0xFFC020FF, + }, + { + .start = IRQ_UART0_TX, + .end = IRQ_UART0_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_ERROR, + .end = IRQ_UART0_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_TX, + .end = CH_UART0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static unsigned short bfin_uart0_peripherals[] = { + P_UART0_TX, P_UART0_RX, 0 +}; + +static struct platform_device bfin_uart0_device = { + .name = "bfin-uart", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_uart0_resources), + .resource = bfin_uart0_resources, + .dev = { + .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 +static struct resource bfin_uart1_resources[] = { + { + .start = UART1_THR, + .end = UART1_GCTL+2, .flags = IORESOURCE_MEM, }, + { + .start = IRQ_UART1_TX, + .end = IRQ_UART1_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_ERROR, + .end = IRQ_UART1_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_TX, + .end = CH_UART1_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX, + .flags = IORESOURCE_DMA, + }, }; -static struct platform_device bfin_uart_device = { +static unsigned short bfin_uart1_peripherals[] = { + P_UART1_TX, P_UART1_RX, 0 +}; + +static struct platform_device bfin_uart1_device = { .name = "bfin-uart", .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart_resources), - .resource = bfin_uart_resources, + .num_resources = ARRAY_SIZE(bfin_uart1_resources), + .resource = bfin_uart1_resources, + .dev = { + .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ + }, }; #endif +#endif -#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +#if IS_ENABLED(CONFIG_BFIN_SIR) #ifdef CONFIG_BFIN_SIR0 static struct resource bfin_sir0_resources[] = { { @@ -436,7 +453,9 @@ static struct platform_device bfin_sir1_device = { #endif #endif -#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) +static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; + static struct resource bfin_twi0_resource[] = { [0] = { .start = TWI0_REGBASE, @@ -455,38 +474,122 @@ static struct platform_device i2c_bfin_twi_device = { .id = 0, .num_resources = ARRAY_SIZE(bfin_twi0_resource), .resource = bfin_twi0_resource, + .dev = { + .platform_data = &bfin_twi0_pins, + }, }; #endif -#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) +#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART +static struct resource bfin_sport0_uart_resources[] = { + { + .start = SPORT0_TCR1, + .end = SPORT0_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT0_RX, + .end = IRQ_SPORT0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT0_ERROR, + .end = IRQ_SPORT0_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static unsigned short bfin_sport0_peripherals[] = { + P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 +}; + static struct platform_device bfin_sport0_uart_device = { .name = "bfin-sport-uart", .id = 0, + .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), + .resource = bfin_sport0_uart_resources, + .dev = { + .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART +static struct resource bfin_sport1_uart_resources[] = { + { + .start = SPORT1_TCR1, + .end = SPORT1_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT1_RX, + .end = IRQ_SPORT1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT1_ERROR, + .end = IRQ_SPORT1_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static unsigned short bfin_sport1_peripherals[] = { + P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 }; static struct platform_device bfin_sport1_uart_device = { .name = "bfin-sport-uart", .id = 1, + .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), + .resource = bfin_sport1_uart_resources, + .dev = { + .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ + }, }; #endif +#endif + +#if IS_ENABLED(CONFIG_BFIN_MAC) +#include <linux/bfin_mac.h> +static const unsigned short bfin_mac_peripherals[] = P_MII0; + +static struct bfin_phydev_platform_data bfin_phydev_data[] = { + { + .addr = 1, + .irq = IRQ_MAC_PHYINT, + }, +}; + +static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { + .phydev_number = 1, + .phydev_data = bfin_phydev_data, + .phy_mode = PHY_INTERFACE_MODE_MII, + .mac_peripherals = bfin_mac_peripherals, +}; -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) static struct platform_device bfin_mii_bus = { .name = "bfin_mii_bus", + .dev = { + .platform_data = &bfin_mii_bus_data, + } }; static struct platform_device bfin_mac_device = { .name = "bfin_mac", - .dev.platform_data = &bfin_mii_bus, + .dev = { + .platform_data = &bfin_mii_bus, + } }; #endif -#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) +#if IS_ENABLED(CONFIG_PATA_PLATFORM) #define PATA_INT IRQ_PF14 static struct pata_platform_info bfin_pata_platform_data = { .ioport_shift = 2, - .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED, + .irq_type = IRQF_TRIGGER_HIGH, }; static struct resource bfin_pata_resources[] = { @@ -549,19 +652,24 @@ static struct platform_device *cm_bf537_devices[] __initdata = { &bfin_dpmc, -#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) +#if IS_ENABLED(CONFIG_FB_HITACHI_TX09) &hitachi_fb_device, #endif -#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) &rtc_device, #endif -#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) - &bfin_uart_device, +#if IS_ENABLED(CONFIG_SERIAL_BFIN) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif #endif -#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +#if IS_ENABLED(CONFIG_BFIN_SIR) #ifdef CONFIG_BFIN_SIR0 &bfin_sir0_device, #endif @@ -570,66 +678,116 @@ static struct platform_device *cm_bf537_devices[] __initdata = { #endif #endif -#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) &i2c_bfin_twi_device, #endif -#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) +#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART &bfin_sport0_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART &bfin_sport1_uart_device, #endif +#endif -#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) &isp1362_hcd_device, #endif -#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) +#if IS_ENABLED(CONFIG_SMC91X) &smc91x_device, #endif -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) +#if IS_ENABLED(CONFIG_BFIN_MAC) &bfin_mii_bus, &bfin_mac_device, #endif -#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) +#if IS_ENABLED(CONFIG_USB_NET2272) &net2272_bfin_device, #endif -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) &bfin_spi0_device, #endif -#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) +#if IS_ENABLED(CONFIG_PATA_PLATFORM) &bfin_pata_device, #endif -#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) +#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) &cm_flash_device, #endif - - &bfin_gpios_device, }; +static int __init net2272_init(void) +{ +#if IS_ENABLED(CONFIG_USB_NET2272) + int ret; + + ret = gpio_request(GPIO_PG14, "net2272"); + if (ret) + return ret; + + /* Reset USB Chip, PG14 */ + gpio_direction_output(GPIO_PG14, 0); + mdelay(2); + gpio_set_value(GPIO_PG14, 1); +#endif + + return 0; +} + static int __init tcm_bf537_init(void) { printk(KERN_INFO "%s(): registering device resources\n", __func__); platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices)); -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +#if IS_ENABLED(CONFIG_SPI_BFIN5XX) spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); #endif -#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) - irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; +#if IS_ENABLED(CONFIG_PATA_PLATFORM) + irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); #endif + + if (net2272_init()) + pr_warning("unable to configure net2272; it probably won't work\n"); + return 0; } arch_initcall(tcm_bf537_init); -void bfin_get_ether_addr(char *addr) +static struct platform_device *cm_bf537_early_devices[] __initdata = { +#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif +#endif + +#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART + &bfin_sport0_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART + &bfin_sport1_uart_device, +#endif +#endif +}; + +void __init native_machine_early_platform_add_devices(void) +{ + printk(KERN_INFO "register early platform devices\n"); + early_platform_add_devices(cm_bf537_early_devices, + ARRAY_SIZE(cm_bf537_early_devices)); +} + +int bfin_get_ether_addr(char *addr) { - random_ether_addr(addr); - printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__); + return 1; } EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c index 81185051de9..5c62e99c9fa 100644 --- a/arch/blackfin/mach-bf537/dma.c +++ b/arch/blackfin/mach-bf537/dma.c @@ -1,37 +1,17 @@ /* - * File: arch/blackfin/mach-bf537/dma.c - * Based on: - * Author: + * Copyright 2007-2009 Analog Devices Inc. * - * Created: - * Description: This file contains the simple DMA Implementation for Blackfin + * Licensed under the GPL-2 or later. * - * Modified: - * Copyright 2004-2007 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * This file contains the simple DMA Implementation for Blackfin */ + #include <linux/module.h> #include <asm/blackfin.h> #include <asm/dma.h> -struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { +struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { (struct dma_register *) DMA0_NEXT_DESC_PTR, (struct dma_register *) DMA1_NEXT_DESC_PTR, (struct dma_register *) DMA2_NEXT_DESC_PTR, @@ -96,12 +76,12 @@ int channel2irq(unsigned int channel) ret_irq = IRQ_SPI; break; - case CH_UART_RX: - ret_irq = IRQ_UART_RX; + case CH_UART0_RX: + ret_irq = IRQ_UART0_RX; break; - case CH_UART_TX: - ret_irq = IRQ_UART_TX; + case CH_UART0_TX: + ret_irq = IRQ_UART0_TX; break; case CH_MEM_STREAM0_SRC: diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h index 1bfd80c26c9..2bc70c5b941 100644 --- a/arch/blackfin/mach-bf537/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h @@ -1,13 +1,16 @@ /* - * File: include/asm-blackfin/mach-bf537/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. + * Copyright 2004-2011 Analog Devices Inc. + * Licensed under the Clear BSD license. */ -/* This file shoule be up to date with: - * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List +/* This file should be up to date with: + * - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -34,79 +37,71 @@ # define ANOMALY_BF537 0 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) -/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */ +/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) -/* Rx.H cannot be used to access 16-bit System MMR registers */ +/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ -#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) -/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ -#define ANOMALY_05000167 (1) -/* PPI_DELAY not functional in PPI modes with 0 frame syncs */ +/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ #define ANOMALY_05000180 (1) -/* Instruction Cache Is Not Functional */ -#define ANOMALY_05000237 (__SILICON_REVISION__ < 2) -/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */ +/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) -/* Spurious Hardware Error from an access in the shadow of a conditional branch */ +/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) -/* CLKIN Buffer Output Enable Reset Behavior Is Changed */ -#define ANOMALY_05000247 (1) -/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */ +/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ < 3) -/* EMAC Tx DMA error after an early frame abort */ +/* EMAC TX DMA Error After an Early Frame Abort */ #define ANOMALY_05000252 (__SILICON_REVISION__ < 3) -/* Maximum external clock speed for Timers */ +/* Maximum External Clock Speed for Timers */ #define ANOMALY_05000253 (__SILICON_REVISION__ < 3) -/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */ +/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ #define ANOMALY_05000254 (__SILICON_REVISION__ > 2) -/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */ +/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ #define ANOMALY_05000255 (__SILICON_REVISION__ < 3) -/* EMAC MDIO input latched on wrong MDC edge */ +/* EMAC MDIO Input Latched on Wrong MDC Edge */ #define ANOMALY_05000256 (__SILICON_REVISION__ < 3) -/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */ +/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ #define ANOMALY_05000257 (__SILICON_REVISION__ < 3) -/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */ +/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ #define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2) -/* ICPLB_STATUS MMR register may be corrupted */ +/* ICPLB_STATUS MMR Register May Be Corrupted */ #define ANOMALY_05000260 (__SILICON_REVISION__ == 2) -/* DCPLB_FAULT_ADDR MMR register may be corrupted */ +/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ #define ANOMALY_05000261 (__SILICON_REVISION__ < 3) -/* Stores to data cache may be lost */ +/* Stores To Data Cache May Be Lost */ #define ANOMALY_05000262 (__SILICON_REVISION__ < 3) -/* Hardware loop corrupted when taking an ICPLB exception */ +/* Hardware Loop Corrupted When Taking an ICPLB Exception */ #define ANOMALY_05000263 (__SILICON_REVISION__ == 2) -/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */ +/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ #define ANOMALY_05000264 (__SILICON_REVISION__ < 3) -/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */ +/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) -/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */ +/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */ #define ANOMALY_05000268 (__SILICON_REVISION__ < 3) -/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */ +/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ #define ANOMALY_05000270 (__SILICON_REVISION__ < 3) -/* Certain data cache write through modes fail for VDDint <=0.9V */ +/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* Writes to Synchronous SDRAM memory may be lost */ +/* Writes to Synchronous SDRAM Memory May Be Lost */ #define ANOMALY_05000273 (__SILICON_REVISION__ < 3) -/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */ +/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) -/* Disabling Peripherals with DMA running may cause DMA system instability */ +/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) -/* SPI Master boot mode does not work well with Atmel Data flash devices */ +/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */ #define ANOMALY_05000280 (1) -/* False Hardware Error Exception when ISR context is not restored */ +/* False Hardware Error when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 3) -/* Memory DMA corruption with 32-bit data and traffic control */ +/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 3) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (__SILICON_REVISION__ < 3) -/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */ +/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */ #define ANOMALY_05000285 (__SILICON_REVISION__ < 3) -/* SPORTs may receive bad data if FIFOs fill up */ +/* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 3) -/* Memory to memory DMA source/destination descriptors must be in same memory space */ +/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ #define ANOMALY_05000301 (1) /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ #define ANOMALY_05000304 (__SILICON_REVISION__ < 3) @@ -114,25 +109,25 @@ #define ANOMALY_05000305 (__SILICON_REVISION__ < 3) /* SCKELOW Bit Does Not Maintain State Through Hibernate */ #define ANOMALY_05000307 (__SILICON_REVISION__ < 3) -/* Writing UART_THR while UART clock is disabled sends erroneous start bit */ +/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */ #define ANOMALY_05000309 (__SILICON_REVISION__ < 3) -/* False hardware errors caused by fetches at the boundary of reserved memory */ +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (1) -/* PPI is level sensitive on first transfer */ +/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (1) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode: collisions occur in Full Duplex mode */ +/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */ #define ANOMALY_05000316 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */ +/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */ #define ANOMALY_05000321 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ +/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */ #define ANOMALY_05000322 (1) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) -/* New Feature: UART Remains Enabled after UART Boot */ +/* UART Gets Disabled after UART Boot */ #define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ #define ANOMALY_05000355 (1) @@ -145,7 +140,7 @@ /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) +#define ANOMALY_05000402 (__SILICON_REVISION__ == 2) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) /* Speculative Fetches Can Cause Undesired External FIFO Operations */ @@ -156,24 +151,91 @@ #define ANOMALY_05000426 (1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ +#define ANOMALY_05000462 (1) +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ +#define ANOMALY_05000473 (1) +/* Possible Lockup Condition when Modifying PLL from External Memory */ +#define ANOMALY_05000475 (1) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */ +#define ANOMALY_05000480 (__SILICON_REVISION__ < 3) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ +#define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) + +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are + * here to show running on older silicon just isn't feasible. + */ + +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ +#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) +/* Instruction Cache Is Not Functional */ +#define ANOMALY_05000237 (__SILICON_REVISION__ < 2) +/* Buffered CLKIN Output Is Disabled by Default */ +#define ANOMALY_05000247 (__SILICON_REVISION__ < 2) /* Anomalies that don't exist on this proc */ +#define ANOMALY_05000099 (0) +#define ANOMALY_05000120 (0) #define ANOMALY_05000125 (0) +#define ANOMALY_05000149 (0) #define ANOMALY_05000158 (0) +#define ANOMALY_05000171 (0) +#define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000183 (0) +#define ANOMALY_05000189 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) +#define ANOMALY_05000215 (0) +#define ANOMALY_05000219 (0) +#define ANOMALY_05000220 (0) +#define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) +#define ANOMALY_05000231 (0) +#define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) +#define ANOMALY_05000242 (0) +#define ANOMALY_05000248 (0) #define ANOMALY_05000266 (0) +#define ANOMALY_05000274 (0) +#define ANOMALY_05000287 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000353 (1) +#define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000386 (1) +#define ANOMALY_05000389 (0) +#define ANOMALY_05000400 (0) #define ANOMALY_05000412 (0) +#define ANOMALY_05000430 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000435 (0) +#define ANOMALY_05000440 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) +#define ANOMALY_05000456 (0) +#define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) +#define ANOMALY_05000474 (0) +#define ANOMALY_05000485 (0) +#define ANOMALY_16000030 (0) #endif diff --git a/arch/blackfin/mach-bf537/include/mach/bf537.h b/arch/blackfin/mach-bf537/include/mach/bf537.h index f194a848ae8..8b291418ca3 100644 --- a/arch/blackfin/mach-bf537/include/mach/bf537.h +++ b/arch/blackfin/mach-bf537/include/mach/bf537.h @@ -1,45 +1,14 @@ /* - * File: include/asm-blackfin/mach-bf537/bf537.h - * Based on: - * Author: + * System MMR Register and memory map for ADSP-BF537 * - * Created: - * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF537 + * Copyright 2005-2008 Analog Devices Inc. * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Licensed under the GPL-2 or later. */ #ifndef __MACH_BF537_H__ #define __MACH_BF537_H__ -/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */ - -#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */ -#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */ -#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */ -#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */ -#define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */ -#define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */ -#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */ - #define OFFSET_(x) ((x) & 0x0000FFFF) /*some misc defines*/ diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h new file mode 100644 index 00000000000..00c603fe821 --- /dev/null +++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h @@ -0,0 +1,14 @@ +/* + * mach/bfin_serial.h - Blackfin UART/Serial definitions + * + * Copyright 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MACH_SERIAL_H__ +#define __BFIN_MACH_SERIAL_H__ + +#define BFIN_UART_NR_PORTS 2 + +#endif diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h deleted file mode 100644 index 9e34700844a..00000000000 --- a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * file: include/asm-blackfin/mach-bf537/bfin_serial_5xx.h - * based on: - * author: - * - * created: - * description: - * blackfin serial driver header files - * rev: - * - * modified: - * - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. - */ - -#include <linux/serial.h> -#include <asm/dma.h> -#include <asm/portmux.h> - -#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) -#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) -#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) -#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) -#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) -#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) -#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) - -#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) -#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) -#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) -#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) -#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) -#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) -#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) -#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) - -#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) -#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) - -#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) -#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) -#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) -#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) -#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) - -#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) -# define CONFIG_SERIAL_BFIN_CTSRTS - -# ifndef CONFIG_UART0_CTS_PIN -# define CONFIG_UART0_CTS_PIN -1 -# endif - -# ifndef CONFIG_UART0_RTS_PIN -# define CONFIG_UART0_RTS_PIN -1 -# endif - -# ifndef CONFIG_UART1_CTS_PIN -# define CONFIG_UART1_CTS_PIN -1 -# endif - -# ifndef CONFIG_UART1_RTS_PIN -# define CONFIG_UART1_RTS_PIN -1 -# endif -#endif - -#define BFIN_UART_TX_FIFO_SIZE 2 - -/* - * The pin configuration is different from schematic - */ -struct bfin_serial_port { - struct uart_port port; - unsigned int old_status; - unsigned int lsr; -#ifdef CONFIG_SERIAL_BFIN_DMA - int tx_done; - int tx_count; - struct circ_buf rx_dma_buf; - struct timer_list rx_dma_timer; - int rx_dma_nrows; - unsigned int tx_dma_channel; - unsigned int rx_dma_channel; - struct work_struct tx_dma_workqueue; -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - struct timer_list cts_timer; - int cts_pin; - int rts_pin; -#endif -}; - -/* The hardware clears the LSR bits upon read, so we need to cache - * some of the more fun bits in software so they don't get lost - * when checking the LSR in other code paths (TX). - */ -static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart) -{ - unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR); - uart->lsr |= (lsr & (BI|FE|PE|OE)); - return lsr | uart->lsr; -} - -static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) -{ - uart->lsr = 0; - bfin_write16(uart->port.membase + OFFSET_LSR, -1); -} - -struct bfin_serial_res { - unsigned long uart_base_addr; - int uart_irq; -#ifdef CONFIG_SERIAL_BFIN_DMA - unsigned int uart_tx_dma_channel; - unsigned int uart_rx_dma_channel; -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - int uart_cts_pin; - int uart_rts_pin; -#endif -}; - -struct bfin_serial_res bfin_serial_resource[] = { -#ifdef CONFIG_SERIAL_BFIN_UART0 - { - 0xFFC00400, - IRQ_UART0_RX, -#ifdef CONFIG_SERIAL_BFIN_DMA - CH_UART0_TX, - CH_UART0_RX, -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - CONFIG_UART0_CTS_PIN, - CONFIG_UART0_RTS_PIN, -#endif - }, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - { - 0xFFC02000, - IRQ_UART1_RX, -#ifdef CONFIG_SERIAL_BFIN_DMA - CH_UART1_TX, - CH_UART1_RX, -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - CONFIG_UART1_CTS_PIN, - CONFIG_UART1_RTS_PIN, -#endif - }, -#endif -}; - -#define DRIVER_NAME "bfin-uart" - -static void bfin_serial_hw_init(struct bfin_serial_port *uart) -{ - -#ifdef CONFIG_SERIAL_BFIN_UART0 - peripheral_request(P_UART0_TX, DRIVER_NAME); - peripheral_request(P_UART0_RX, DRIVER_NAME); -#endif - -#ifdef CONFIG_SERIAL_BFIN_UART1 - peripheral_request(P_UART1_TX, DRIVER_NAME); - peripheral_request(P_UART1_RX, DRIVER_NAME); -#endif - -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - if (uart->cts_pin >= 0) { - gpio_request(uart->cts_pin, DRIVER_NAME); - gpio_direction_input(uart->cts_pin); - } - - if (uart->rts_pin >= 0) { - gpio_request(uart->rts_pin, DRIVER_NAME); - gpio_direction_output(uart->rts_pin, 0); - } -#endif -} diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h index 7d6069c886f..baa096fc724 100644 --- a/arch/blackfin/mach-bf537/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h @@ -1,32 +1,7 @@ /* - * File: include/asm-blackfin/mach-bf537/blackfin.h - * Based on: - * Author: + * Copyright 2005-2010 Analog Devices Inc. * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Licensed under the GPL-2 or later. */ #ifndef _MACH_BLACKFIN_H_ @@ -35,131 +10,24 @@ #define BF537_FAMILY #include "bf537.h" -#include "mem_map.h" -#include "defBF534.h" #include "anomaly.h" +#include <asm/def_LPBlackfin.h> +#ifdef CONFIG_BF534 +# include "defBF534.h" +#endif #if defined(CONFIG_BF537) || defined(CONFIG_BF536) -#include "defBF537.h" +# include "defBF537.h" #endif #if !defined(__ASSEMBLY__) -#include "cdefBF534.h" - -/* UART 0*/ -#define bfin_read_UART_THR() bfin_read_UART0_THR() -#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val) -#define bfin_read_UART_RBR() bfin_read_UART0_RBR() -#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val) -#define bfin_read_UART_DLL() bfin_read_UART0_DLL() -#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val) -#define bfin_read_UART_IER() bfin_read_UART0_IER() -#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val) -#define bfin_read_UART_DLH() bfin_read_UART0_DLH() -#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val) -#define bfin_read_UART_IIR() bfin_read_UART0_IIR() -#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val) -#define bfin_read_UART_LCR() bfin_read_UART0_LCR() -#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val) -#define bfin_read_UART_MCR() bfin_read_UART0_MCR() -#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val) -#define bfin_read_UART_LSR() bfin_read_UART0_LSR() -#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val) -#define bfin_read_UART_SCR() bfin_read_UART0_SCR() -#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val) -#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL() -#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val) - -#if defined(CONFIG_BF537) || defined(CONFIG_BF536) -#include "cdefBF537.h" +# include <asm/cdef_LPBlackfin.h> +# ifdef CONFIG_BF534 +# include "cdefBF534.h" +# endif +# if defined(CONFIG_BF537) || defined(CONFIG_BF536) +# include "cdefBF537.h" +# endif #endif -#endif - -/* MAP used DEFINES from BF533 to BF537 - so we don't need to change them in the driver, kernel, etc. */ - -/* UART_IIR Register */ -#define STATUS(x) ((x << 1) & 0x06) -#define STATUS_P1 0x02 -#define STATUS_P0 0x01 - -/* DMA Channel */ -#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX() -#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val) -#define CH_UART_RX CH_UART0_RX -#define bfin_read_CH_UART_TX() bfin_read_CH_UART0_TX() -#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART0_TX(val) -#define CH_UART_TX CH_UART0_TX - -/* System Interrupt Controller */ -#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART0_RX() -#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART0_RX(val) -#define IRQ_UART_RX IRQ_UART0_RX -#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART0_TX() -#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART0_TX(val) -#define IRQ_UART_TX IRQ_UART0_TX -#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART0_ERROR() -#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART0_ERROR(val) -#define IRQ_UART_ERROR IRQ_UART0_ERROR - -/* MMR Registers*/ -#define bfin_read_UART_THR() bfin_read_UART0_THR() -#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val) -#define BFIN_UART_THR UART0_THR -#define bfin_read_UART_RBR() bfin_read_UART0_RBR() -#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val) -#define BFIN_UART_RBR UART0_RBR -#define bfin_read_UART_DLL() bfin_read_UART0_DLL() -#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val) -#define BFIN_UART_DLL UART0_DLL -#define bfin_read_UART_IER() bfin_read_UART0_IER() -#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val) -#define BFIN_UART_IER UART0_IER -#define bfin_read_UART_DLH() bfin_read_UART0_DLH() -#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val) -#define BFIN_UART_DLH UART0_DLH -#define bfin_read_UART_IIR() bfin_read_UART0_IIR() -#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val) -#define BFIN_UART_IIR UART0_IIR -#define bfin_read_UART_LCR() bfin_read_UART0_LCR() -#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val) -#define BFIN_UART_LCR UART0_LCR -#define bfin_read_UART_MCR() bfin_read_UART0_MCR() -#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val) -#define BFIN_UART_MCR UART0_MCR -#define bfin_read_UART_LSR() bfin_read_UART0_LSR() -#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val) -#define BFIN_UART_LSR UART0_LSR -#define bfin_read_UART_SCR() bfin_read_UART0_SCR() -#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val) -#define BFIN_UART_SCR UART0_SCR -#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL() -#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val) -#define BFIN_UART_GCTL UART0_GCTL - -#define BFIN_UART_NR_PORTS 2 - -#define OFFSET_THR 0x00 /* Transmit Holding register */ -#define OFFSET_RBR 0x00 /* Receive Buffer register */ -#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -#define OFFSET_IER 0x04 /* Interrupt Enable Register */ -#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -#define OFFSET_LCR 0x0C /* Line Control Register */ -#define OFFSET_MCR 0x10 /* Modem Control Register */ -#define OFFSET_LSR 0x14 /* Line Status Register */ -#define OFFSET_MSR 0x18 /* Modem Status Register */ -#define OFFSET_SCR 0x1C /* SCR Scratch Register */ -#define OFFSET_GCTL 0x24 /* Global Control Register */ - -/* DPMC*/ -#define bfin_read_STOPCK_OFF() bfin_read_STOPCK() -#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) -#define STOPCK_OFF STOPCK - -/* PLL_DIV Masks */ -#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ -#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ -#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ -#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ #endif diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h index 5f8b5f845be..563ede90733 100644 --- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h @@ -1,45 +1,12 @@ /* - * File: include/asm-blackfin/mach-bf537/cdefbf534.h - * Based on: - * Author: + * Copyright 2005-2010 Analog Devices Inc. * - * Created: - * Description: system mmr register map - * - * Rev: - * - * Modified: - * - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Licensed under the GPL-2 or later */ #ifndef _CDEF_BF534_H #define _CDEF_BF534_H -#include <asm/blackfin.h> - -/* Include all Core registers and bit definitions */ -#include "defBF534.h" - -/* Include core specific register pointer definitions */ -#include <asm/cdef_LPBlackfin.h> - /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) @@ -380,16 +347,10 @@ #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) /* DMA Traffic Control Registers */ -#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) -#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) -#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) -#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) -#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) -#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) -#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val) +#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) +#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val) +#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) +#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val) /* DMA Controller */ #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) @@ -1772,51 +1733,4 @@ #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val) -/* These need to be last due to the cdef/linux inter-dependencies */ -#include <asm/irq.h> - -/* Writing to PLL_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_PLL_CTL(unsigned int val) -{ - unsigned long flags, iwr; - - if (val == bfin_read_PLL_CTL()) - return; - - local_irq_save_hw(flags); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SIC_IWR); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR, IWR_ENABLE(0)); - - bfin_write16(PLL_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR, iwr); - local_irq_restore_hw(flags); -} - -/* Writing to VR_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_VR_CTL(unsigned int val) -{ - unsigned long flags, iwr; - - if (val == bfin_read_VR_CTL()) - return; - - local_irq_save_hw(flags); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SIC_IWR); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR, IWR_ENABLE(0)); - - bfin_write16(VR_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR, iwr); - local_irq_restore_hw(flags); -} - #endif /* _CDEF_BF534_H */ diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h index b8fc949a991..19ec21ea150 100644 --- a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h +++ b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h @@ -1,32 +1,7 @@ /* - * File: include/asm-blackfin/mach-bf537/cdefBF537.h - * Based on: - * Author: + * Copyright 2005-2010 Analog Devices Inc. * - * Created: - * Description: - * System MMR Register Map - * Rev: - * - * Modified: - * - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Licensed under the GPL-2 or later */ #ifndef _CDEF_BF537_H @@ -35,9 +10,6 @@ /* Include MMRs Common to BF534 */ #include "cdefBF534.h" -/* Include all Core registers and bit definitions */ -#include "defBF537.h" - /* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */ /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ #define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h index a3227f9003f..ef6a98cdfd4 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h @@ -1,39 +1,12 @@ /* - * File: include/asm-blackfin/mach-bf537/cdefBF537.h - * Based on: - * Author: + * Copyright 2005-2010 Analog Devices Inc. * - * Created: - * Description: - * - * Rev: - * - * Modified: - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF534_H #define _DEF_BF534_H -/* Include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> - /************************************************************************************ ** System MMR Register Map *************************************************************************************/ @@ -217,12 +190,8 @@ #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ /* DMA Traffic Control Registers */ -#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ - -/* Alternate deprecated register names (below) provided for backwards code compatibility */ -#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ +#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ +#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ @@ -458,22 +427,22 @@ /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ #define TWI0_REGBASE 0xFFC01400 -#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ -#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ -#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ -#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ -#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ -#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ -#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ -#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ -#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ -#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ -#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ -#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ -#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ -#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ -#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ -#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ +#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ +#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ +#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ +#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ +#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ +#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ +#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ +#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ +#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ +#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ +#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ +#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ +#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ +#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ +#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ +#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ #define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ @@ -958,7 +927,7 @@ #define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ #define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ #define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ -#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ +#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */ #define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ #define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ #define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ @@ -966,7 +935,7 @@ #define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ #define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ #define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ +#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */ #define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ #define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ #define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ @@ -982,67 +951,6 @@ ** modifier UNLESS the lower order bits are saved and ORed back in when ** the macro is used. *************************************************************************************/ -/* -** ********************* PLL AND RESET MASKS ****************************************/ -/* PLL_CTL Masks */ -#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ -#define PLL_OFF 0x0002 /* PLL Not Powered */ -#define STOPCK 0x0008 /* Core Clock Off */ -#define PDWN 0x0020 /* Enter Deep Sleep Mode */ -#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ -#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ -#define BYPASS 0x0100 /* Bypass the PLL */ -#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ -/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ -#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ - -/* PLL_DIV Masks */ -#define SSEL 0x000F /* System Select */ -#define CSEL 0x0030 /* Core Select */ -#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ -#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ -#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ -#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ -/* PLL_DIV Macros */ -#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ - -/* VR_CTL Masks */ -#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ -#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ -#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ -#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ -#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ - -#define GAIN 0x000C /* Voltage Level Gain */ -#define GAIN_5 0x0000 /* GAIN = 5 */ -#define GAIN_10 0x0004 /* GAIN = 10 */ -#define GAIN_20 0x0008 /* GAIN = 20 */ -#define GAIN_50 0x000C /* GAIN = 50 */ - -#define VLEV 0x00F0 /* Internal Voltage Level */ -#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ -#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ -#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ -#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ -#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ -#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ -#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ -#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ -#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ -#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ - -#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ -#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ -#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ -#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ -#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ -#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */ - -/* PLL_STAT Masks */ -#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ -#define FULL_ON 0x0002 /* Processor In Full On Mode */ -#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ -#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ /* CHIPID Masks */ #define CHIPID_VERSION 0xF0000000 @@ -1114,92 +1022,6 @@ #define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ -/* ************** UART CONTROLLER MASKS *************************/ -/* UARTx_LCR Masks */ -#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ -#define STB 0x04 /* Stop Bits */ -#define PEN 0x08 /* Parity Enable */ -#define EPS 0x10 /* Even Parity Select */ -#define STP 0x20 /* Stick Parity */ -#define SB 0x40 /* Set Break */ -#define DLAB 0x80 /* Divisor Latch Access */ - -/* UARTx_MCR Mask */ -#define LOOP_ENA 0x10 /* Loopback Mode Enable */ -#define LOOP_ENA_P 0x04 -/* UARTx_LSR Masks */ -#define DR 0x01 /* Data Ready */ -#define OE 0x02 /* Overrun Error */ -#define PE 0x04 /* Parity Error */ -#define FE 0x08 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* THR Empty */ -#define TEMT 0x40 /* TSR and UART_THR Empty */ - -/* UARTx_IER Masks */ -#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ -#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ -#define ELSI 0x04 /* Enable RX Status Interrupt */ - -/* UARTx_IIR Masks */ -#define NINT 0x01 /* Pending Interrupt */ -#define IIR_TX_READY 0x02 /* UART_THR empty */ -#define IIR_RX_READY 0x04 /* Receive data ready */ -#define IIR_LINE_CHANGE 0x06 /* Receive line status */ -#define IIR_STATUS 0x06 - -/* UARTx_GCTL Masks */ -#define UCEN 0x01 /* Enable UARTx Clocks */ -#define IREN 0x02 /* Enable IrDA Mode */ -#define TPOLC 0x04 /* IrDA TX Polarity Change */ -#define RPOLC 0x08 /* IrDA RX Polarity Change */ -#define FPE 0x10 /* Force Parity Error On Transmit */ -#define FFE 0x20 /* Force Framing Error On Transmit */ - -/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/ -/* SPI_CTL Masks */ -#define TIMOD 0x0003 /* Transfer Initiate Mode */ -#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ -#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ -#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ -#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ -#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ -#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ -#define PSSE 0x0010 /* Slave-Select Input Enable */ -#define EMISO 0x0020 /* Enable MISO As Output */ -#define SIZE 0x0100 /* Size of Words (16/8* Bits) */ -#define LSBF 0x0200 /* LSB First */ -#define CPHA 0x0400 /* Clock Phase */ -#define CPOL 0x0800 /* Clock Polarity */ -#define MSTR 0x1000 /* Master/Slave* */ -#define WOM 0x2000 /* Write Open Drain Master */ -#define SPE 0x4000 /* SPI Enable */ - -/* SPI_FLG Masks */ -#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */ -#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */ -#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */ -#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */ -#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */ -#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */ -#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */ -#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */ -#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */ -#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */ -#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */ -#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */ -#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */ -#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */ - -/* SPI_STAT Masks */ -#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */ -#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */ -#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */ -#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */ -#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */ -#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ -#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ - /* **************** GENERAL PURPOSE TIMER MASKS **********************/ /* TIMER_ENABLE Masks */ #define TIMEN0 0x0001 /* Enable Timer 0 */ @@ -1270,142 +1092,6 @@ #define EMU_RUN 0x0200 /* Emulation Behavior Select */ #define ERR_TYP 0xC000 /* Error Type */ -/* ****************** GPIO PORTS F, G, H MASKS ***********************/ -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ -/* Port F Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* Port G Masks */ -#define PG0 0x0001 -#define PG1 0x0002 -#define PG2 0x0004 -#define PG3 0x0008 -#define PG4 0x0010 -#define PG5 0x0020 -#define PG6 0x0040 -#define PG7 0x0080 -#define PG8 0x0100 -#define PG9 0x0200 -#define PG10 0x0400 -#define PG11 0x0800 -#define PG12 0x1000 -#define PG13 0x2000 -#define PG14 0x4000 -#define PG15 0x8000 - -/* Port H Masks */ -#define PH0 0x0001 -#define PH1 0x0002 -#define PH2 0x0004 -#define PH3 0x0008 -#define PH4 0x0010 -#define PH5 0x0020 -#define PH6 0x0040 -#define PH7 0x0080 -#define PH8 0x0100 -#define PH9 0x0200 -#define PH10 0x0400 -#define PH11 0x0800 -#define PH12 0x1000 -#define PH13 0x2000 -#define PH14 0x4000 -#define PH15 0x8000 - -/* ******************* SERIAL PORT MASKS **************************************/ -/* SPORTx_TCR1 Masks */ -#define TSPEN 0x0001 /* Transmit Enable */ -#define ITCLK 0x0002 /* Internal Transmit Clock Select */ -#define DTYPE_NORM 0x0004 /* Data Format Normal */ -#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ -#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ -#define TLSBIT 0x0010 /* Transmit Bit Order */ -#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */ -#define TFSR 0x0400 /* Transmit Frame Sync Required Select */ -#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */ -#define LTFS 0x1000 /* Low Transmit Frame Sync Select */ -#define LATFS 0x2000 /* Late Transmit Frame Sync Select */ -#define TCKFE 0x4000 /* Clock Falling Edge Select */ - -/* SPORTx_TCR2 Masks and Macro */ -#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */ -#define TXSE 0x0100 /* TX Secondary Enable */ -#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */ -#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */ - -/* SPORTx_RCR1 Masks */ -#define RSPEN 0x0001 /* Receive Enable */ -#define IRCLK 0x0002 /* Internal Receive Clock Select */ -#define DTYPE_NORM 0x0004 /* Data Format Normal */ -#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ -#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ -#define RLSBIT 0x0010 /* Receive Bit Order */ -#define IRFS 0x0200 /* Internal Receive Frame Sync Select */ -#define RFSR 0x0400 /* Receive Frame Sync Required Select */ -#define LRFS 0x1000 /* Low Receive Frame Sync Select */ -#define LARFS 0x2000 /* Late Receive Frame Sync Select */ -#define RCKFE 0x4000 /* Clock Falling Edge Select */ - -/* SPORTx_RCR2 Masks */ -#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */ -#define RXSE 0x0100 /* RX Secondary Enable */ -#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ -#define RRFST 0x0400 /* Right-First Data Order */ - -/* SPORTx_STAT Masks */ -#define RXNE 0x0001 /* Receive FIFO Not Empty Status */ -#define RUVF 0x0002 /* Sticky Receive Underflow Status */ -#define ROVF 0x0004 /* Sticky Receive Overflow Status */ -#define TXF 0x0008 /* Transmit FIFO Full Status */ -#define TUVF 0x0010 /* Sticky Transmit Underflow Status */ -#define TOVF 0x0020 /* Sticky Transmit Overflow Status */ -#define TXHRE 0x0040 /* Transmit Hold Register Empty */ - -/* SPORTx_MCMC1 Macros */ -#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */ - -/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */ -#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */ - -/* SPORTx_MCMC2 Masks */ -#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ -#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ -#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ -#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ -#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ -#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ -#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ -#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ -#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ -#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ -#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ -#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ -#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ -#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ -#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ -#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ -#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ -#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ -#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ -#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ -#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ -#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ -#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ - /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ /* EBIU_AMGCTL Masks */ #define AMCKEN 0x0001 /* Enable CLKOUT */ @@ -1669,34 +1355,6 @@ #define BGSTAT 0x0020 /* Bus Grant Status */ /* ************************** DMA CONTROLLER MASKS ********************************/ -/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ -#define DMAEN 0x0001 /* DMA Channel Enable */ -#define WNR 0x0002 /* Channel Direction (W/R*) */ -#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ -#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ -#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ -#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ -#define RESTART 0x0020 /* DMA Buffer Clear */ -#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ -#define DI_EN 0x0080 /* Data Interrupt Enable */ -#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ -#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ -#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ -#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ -#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ -#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ -#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ -#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ -#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ -#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ -#define NDSIZE 0x0900 /* Next Descriptor Size */ - -#define DMAFLOW 0x7000 /* Flow Control */ -#define DMAFLOW_STOP 0x0000 /* Stop Mode */ -#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ -#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ -#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ -#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ @@ -1714,12 +1372,6 @@ #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ -/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ -#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ -#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ -#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ -#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ - /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ /* PPI_CONTROL Masks */ #define PORT_EN 0x0001 /* PPI Port Enable */ @@ -1751,697 +1403,6 @@ #define ERR_DET 0x4000 /* Error Detected Indicator */ #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ -/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ -/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ -#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ -#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ - -/* TWI_PRESCALE Masks */ -#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ -#define TWI_ENA 0x0080 /* TWI Enable */ -#define SCCB 0x0200 /* SCCB Compatibility Enable */ - -/* TWI_SLAVE_CTRL Masks */ -#define SEN 0x0001 /* Slave Enable */ -#define SADD_LEN 0x0002 /* Slave Address Length */ -#define STDVAL 0x0004 /* Slave Transmit Data Valid */ -#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ -#define GEN 0x0010 /* General Call Adrress Matching Enabled */ - -/* TWI_SLAVE_STAT Masks */ -#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ -#define GCALL 0x0002 /* General Call Indicator */ - -/* TWI_MASTER_CTRL Masks */ -#define MEN 0x0001 /* Master Mode Enable */ -#define MADD_LEN 0x0002 /* Master Address Length */ -#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ -#define FAST 0x0008 /* Use Fast Mode Timing Specs */ -#define STOP 0x0010 /* Issue Stop Condition */ -#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ -#define DCNT 0x3FC0 /* Data Bytes To Transfer */ -#define SDAOVR 0x4000 /* Serial Data Override */ -#define SCLOVR 0x8000 /* Serial Clock Override */ - -/* TWI_MASTER_STAT Masks */ -#define MPROG 0x0001 /* Master Transfer In Progress */ -#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ -#define ANAK 0x0004 /* Address Not Acknowledged */ -#define DNAK 0x0008 /* Data Not Acknowledged */ -#define BUFRDERR 0x0010 /* Buffer Read Error */ -#define BUFWRERR 0x0020 /* Buffer Write Error */ -#define SDASEN 0x0040 /* Serial Data Sense */ -#define SCLSEN 0x0080 /* Serial Clock Sense */ -#define BUSBUSY 0x0100 /* Bus Busy Indicator */ - -/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ -#define SINIT 0x0001 /* Slave Transfer Initiated */ -#define SCOMP 0x0002 /* Slave Transfer Complete */ -#define SERR 0x0004 /* Slave Transfer Error */ -#define SOVF 0x0008 /* Slave Overflow */ -#define MCOMP 0x0010 /* Master Transfer Complete */ -#define MERR 0x0020 /* Master Transfer Error */ -#define XMTSERV 0x0040 /* Transmit FIFO Service */ -#define RCVSERV 0x0080 /* Receive FIFO Service */ - -/* TWI_FIFO_CTRL Masks */ -#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ -#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ -#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ -#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ - -/* TWI_FIFO_STAT Masks */ -#define XMTSTAT 0x0003 /* Transmit FIFO Status */ -#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ -#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ -#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ - -#define RCVSTAT 0x000C /* Receive FIFO Status */ -#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ -#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ -#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ - -/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/ -/* CAN_CONTROL Masks */ -#define SRS 0x0001 /* Software Reset */ -#define DNM 0x0002 /* Device Net Mode */ -#define ABO 0x0004 /* Auto-Bus On Enable */ -#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */ -#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */ -#define SMR 0x0020 /* Sleep Mode Request */ -#define CSR 0x0040 /* CAN Suspend Mode Request */ -#define CCR 0x0080 /* CAN Configuration Mode Request */ - -/* CAN_STATUS Masks */ -#define WT 0x0001 /* TX Warning Flag */ -#define WR 0x0002 /* RX Warning Flag */ -#define EP 0x0004 /* Error Passive Mode */ -#define EBO 0x0008 /* Error Bus Off Mode */ -#define SMA 0x0020 /* Sleep Mode Acknowledge */ -#define CSA 0x0040 /* Suspend Mode Acknowledge */ -#define CCA 0x0080 /* Configuration Mode Acknowledge */ -#define MBPTR 0x1F00 /* Mailbox Pointer */ -#define TRM 0x4000 /* Transmit Mode */ -#define REC 0x8000 /* Receive Mode */ - -/* CAN_CLOCK Masks */ -#define BRP 0x03FF /* Bit-Rate Pre-Scaler */ - -/* CAN_TIMING Masks */ -#define TSEG1 0x000F /* Time Segment 1 */ -#define TSEG2 0x0070 /* Time Segment 2 */ -#define SAM 0x0080 /* Sampling */ -#define SJW 0x0300 /* Synchronization Jump Width */ - -/* CAN_DEBUG Masks */ -#define DEC 0x0001 /* Disable CAN Error Counters */ -#define DRI 0x0002 /* Disable CAN RX Input */ -#define DTO 0x0004 /* Disable CAN TX Output */ -#define DIL 0x0008 /* Disable CAN Internal Loop */ -#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */ -#define MRB 0x0020 /* Mode Read Back Enable */ -#define CDE 0x8000 /* CAN Debug Enable */ - -/* CAN_CEC Masks */ -#define RXECNT 0x00FF /* Receive Error Counter */ -#define TXECNT 0xFF00 /* Transmit Error Counter */ - -/* CAN_INTR Masks */ -#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */ -#define MBRIF MBRIRQ /* legacy */ -#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */ -#define MBTIF MBTIRQ /* legacy */ -#define GIRQ 0x0004 /* Global Interrupt */ -#define SMACK 0x0008 /* Sleep Mode Acknowledge */ -#define CANTX 0x0040 /* CAN TX Bus Value */ -#define CANRX 0x0080 /* CAN RX Bus Value */ - -/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */ -#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */ -#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */ -#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */ -#define BASEID 0x1FFC /* Base Identifier */ -#define IDE 0x2000 /* Identifier Extension */ -#define RTR 0x4000 /* Remote Frame Transmission Request */ -#define AME 0x8000 /* Acceptance Mask Enable */ - -/* CAN_MBxx_TIMESTAMP Masks */ -#define TSV 0xFFFF /* Timestamp */ - -/* CAN_MBxx_LENGTH Masks */ -#define DLC 0x000F /* Data Length Code */ - -/* CAN_AMxxH and CAN_AMxxL Masks */ -#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */ -#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */ -#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */ -#define BASEID 0x1FFC /* Base Identifier */ -#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */ -#define FMD 0x4000 /* Full Mask Data Field Enable */ -#define FDF 0x8000 /* Filter On Data Field Enable */ - -/* CAN_MC1 Masks */ -#define MC0 0x0001 /* Enable Mailbox 0 */ -#define MC1 0x0002 /* Enable Mailbox 1 */ -#define MC2 0x0004 /* Enable Mailbox 2 */ -#define MC3 0x0008 /* Enable Mailbox 3 */ -#define MC4 0x0010 /* Enable Mailbox 4 */ -#define MC5 0x0020 /* Enable Mailbox 5 */ -#define MC6 0x0040 /* Enable Mailbox 6 */ -#define MC7 0x0080 /* Enable Mailbox 7 */ -#define MC8 0x0100 /* Enable Mailbox 8 */ -#define MC9 0x0200 /* Enable Mailbox 9 */ -#define MC10 0x0400 /* Enable Mailbox 10 */ -#define MC11 0x0800 /* Enable Mailbox 11 */ -#define MC12 0x1000 /* Enable Mailbox 12 */ -#define MC13 0x2000 /* Enable Mailbox 13 */ -#define MC14 0x4000 /* Enable Mailbox 14 */ -#define MC15 0x8000 /* Enable Mailbox 15 */ - -/* CAN_MC2 Masks */ -#define MC16 0x0001 /* Enable Mailbox 16 */ -#define MC17 0x0002 /* Enable Mailbox 17 */ -#define MC18 0x0004 /* Enable Mailbox 18 */ -#define MC19 0x0008 /* Enable Mailbox 19 */ -#define MC20 0x0010 /* Enable Mailbox 20 */ -#define MC21 0x0020 /* Enable Mailbox 21 */ -#define MC22 0x0040 /* Enable Mailbox 22 */ -#define MC23 0x0080 /* Enable Mailbox 23 */ -#define MC24 0x0100 /* Enable Mailbox 24 */ -#define MC25 0x0200 /* Enable Mailbox 25 */ -#define MC26 0x0400 /* Enable Mailbox 26 */ -#define MC27 0x0800 /* Enable Mailbox 27 */ -#define MC28 0x1000 /* Enable Mailbox 28 */ -#define MC29 0x2000 /* Enable Mailbox 29 */ -#define MC30 0x4000 /* Enable Mailbox 30 */ -#define MC31 0x8000 /* Enable Mailbox 31 */ - -/* CAN_MD1 Masks */ -#define MD0 0x0001 /* Enable Mailbox 0 For Receive */ -#define MD1 0x0002 /* Enable Mailbox 1 For Receive */ -#define MD2 0x0004 /* Enable Mailbox 2 For Receive */ -#define MD3 0x0008 /* Enable Mailbox 3 For Receive */ -#define MD4 0x0010 /* Enable Mailbox 4 For Receive */ -#define MD5 0x0020 /* Enable Mailbox 5 For Receive */ -#define MD6 0x0040 /* Enable Mailbox 6 For Receive */ -#define MD7 0x0080 /* Enable Mailbox 7 For Receive */ -#define MD8 0x0100 /* Enable Mailbox 8 For Receive */ -#define MD9 0x0200 /* Enable Mailbox 9 For Receive */ -#define MD10 0x0400 /* Enable Mailbox 10 For Receive */ -#define MD11 0x0800 /* Enable Mailbox 11 For Receive */ -#define MD12 0x1000 /* Enable Mailbox 12 For Receive */ -#define MD13 0x2000 /* Enable Mailbox 13 For Receive */ -#define MD14 0x4000 /* Enable Mailbox 14 For Receive */ -#define MD15 0x8000 /* Enable Mailbox 15 For Receive */ - -/* CAN_MD2 Masks */ -#define MD16 0x0001 /* Enable Mailbox 16 For Receive */ -#define MD17 0x0002 /* Enable Mailbox 17 For Receive */ -#define MD18 0x0004 /* Enable Mailbox 18 For Receive */ -#define MD19 0x0008 /* Enable Mailbox 19 For Receive */ -#define MD20 0x0010 /* Enable Mailbox 20 For Receive */ -#define MD21 0x0020 /* Enable Mailbox 21 For Receive */ -#define MD22 0x0040 /* Enable Mailbox 22 For Receive */ -#define MD23 0x0080 /* Enable Mailbox 23 For Receive */ -#define MD24 0x0100 /* Enable Mailbox 24 For Receive */ -#define MD25 0x0200 /* Enable Mailbox 25 For Receive */ -#define MD26 0x0400 /* Enable Mailbox 26 For Receive */ -#define MD27 0x0800 /* Enable Mailbox 27 For Receive */ -#define MD28 0x1000 /* Enable Mailbox 28 For Receive */ -#define MD29 0x2000 /* Enable Mailbox 29 For Receive */ -#define MD30 0x4000 /* Enable Mailbox 30 For Receive */ -#define MD31 0x8000 /* Enable Mailbox 31 For Receive */ - -/* CAN_RMP1 Masks */ -#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */ -#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */ -#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */ -#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */ -#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */ -#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */ -#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */ -#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */ -#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */ -#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */ -#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */ -#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */ -#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */ -#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */ -#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */ -#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */ - -/* CAN_RMP2 Masks */ -#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */ -#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */ -#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */ -#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */ -#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */ -#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */ -#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */ -#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */ -#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */ -#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */ -#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */ -#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */ -#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */ -#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */ -#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */ -#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */ - -/* CAN_RML1 Masks */ -#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */ -#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */ -#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */ -#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */ -#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */ -#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */ -#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */ -#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */ -#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */ -#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */ -#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */ -#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */ -#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */ -#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */ -#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */ -#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */ - -/* CAN_RML2 Masks */ -#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */ -#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */ -#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */ -#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */ -#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */ -#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */ -#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */ -#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */ -#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */ -#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */ -#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */ -#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */ -#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */ -#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */ -#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */ -#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */ - -/* CAN_OPSS1 Masks */ -#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */ -#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */ -#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */ -#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */ -#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */ -#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */ -#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */ -#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */ -#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */ -#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */ -#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */ -#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */ -#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */ -#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */ -#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */ -#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */ - -/* CAN_OPSS2 Masks */ -#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */ -#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */ -#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */ -#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */ -#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */ -#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */ -#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */ -#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */ -#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */ -#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */ -#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */ -#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */ -#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */ -#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */ -#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */ -#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */ - -/* CAN_TRR1 Masks */ -#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */ -#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */ -#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */ -#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */ -#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */ -#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */ -#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */ -#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */ -#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */ -#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */ -#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */ -#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */ -#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */ -#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */ -#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */ -#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */ - -/* CAN_TRR2 Masks */ -#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */ -#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */ -#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */ -#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */ -#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */ -#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */ -#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */ -#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */ -#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */ -#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */ -#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */ -#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */ -#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */ -#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */ -#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */ -#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */ - -/* CAN_TRS1 Masks */ -#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */ -#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */ -#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */ -#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */ -#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */ -#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */ -#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */ -#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */ -#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */ -#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */ -#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */ -#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */ -#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */ -#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */ -#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */ -#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */ - -/* CAN_TRS2 Masks */ -#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */ -#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */ -#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */ -#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */ -#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */ -#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */ -#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */ -#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */ -#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */ -#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */ -#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */ -#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */ -#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */ -#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */ -#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */ -#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */ - -/* CAN_AA1 Masks */ -#define AA0 0x0001 /* Aborted Message In Mailbox 0 */ -#define AA1 0x0002 /* Aborted Message In Mailbox 1 */ -#define AA2 0x0004 /* Aborted Message In Mailbox 2 */ -#define AA3 0x0008 /* Aborted Message In Mailbox 3 */ -#define AA4 0x0010 /* Aborted Message In Mailbox 4 */ -#define AA5 0x0020 /* Aborted Message In Mailbox 5 */ -#define AA6 0x0040 /* Aborted Message In Mailbox 6 */ -#define AA7 0x0080 /* Aborted Message In Mailbox 7 */ -#define AA8 0x0100 /* Aborted Message In Mailbox 8 */ -#define AA9 0x0200 /* Aborted Message In Mailbox 9 */ -#define AA10 0x0400 /* Aborted Message In Mailbox 10 */ -#define AA11 0x0800 /* Aborted Message In Mailbox 11 */ -#define AA12 0x1000 /* Aborted Message In Mailbox 12 */ -#define AA13 0x2000 /* Aborted Message In Mailbox 13 */ -#define AA14 0x4000 /* Aborted Message In Mailbox 14 */ -#define AA15 0x8000 /* Aborted Message In Mailbox 15 */ - -/* CAN_AA2 Masks */ -#define AA16 0x0001 /* Aborted Message In Mailbox 16 */ -#define AA17 0x0002 /* Aborted Message In Mailbox 17 */ -#define AA18 0x0004 /* Aborted Message In Mailbox 18 */ -#define AA19 0x0008 /* Aborted Message In Mailbox 19 */ -#define AA20 0x0010 /* Aborted Message In Mailbox 20 */ -#define AA21 0x0020 /* Aborted Message In Mailbox 21 */ -#define AA22 0x0040 /* Aborted Message In Mailbox 22 */ -#define AA23 0x0080 /* Aborted Message In Mailbox 23 */ -#define AA24 0x0100 /* Aborted Message In Mailbox 24 */ -#define AA25 0x0200 /* Aborted Message In Mailbox 25 */ -#define AA26 0x0400 /* Aborted Message In Mailbox 26 */ -#define AA27 0x0800 /* Aborted Message In Mailbox 27 */ -#define AA28 0x1000 /* Aborted Message In Mailbox 28 */ -#define AA29 0x2000 /* Aborted Message In Mailbox 29 */ -#define AA30 0x4000 /* Aborted Message In Mailbox 30 */ -#define AA31 0x8000 /* Aborted Message In Mailbox 31 */ - -/* CAN_TA1 Masks */ -#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */ -#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */ -#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */ -#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */ -#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */ -#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */ -#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */ -#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */ -#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */ -#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */ -#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */ -#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */ -#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */ -#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */ -#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */ -#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */ - -/* CAN_TA2 Masks */ -#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */ -#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */ -#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */ -#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */ -#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */ -#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */ -#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */ -#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */ -#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */ -#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */ -#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */ -#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */ -#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */ -#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */ -#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */ -#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */ - -/* CAN_MBTD Masks */ -#define TDPTR 0x001F /* Mailbox To Temporarily Disable */ -#define TDA 0x0040 /* Temporary Disable Acknowledge */ -#define TDR 0x0080 /* Temporary Disable Request */ - -/* CAN_RFH1 Masks */ -#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */ -#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */ -#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */ -#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */ -#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */ -#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */ -#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */ -#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */ -#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */ -#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */ -#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */ -#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */ -#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */ -#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */ -#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */ -#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */ - -/* CAN_RFH2 Masks */ -#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */ -#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */ -#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */ -#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */ -#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */ -#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */ -#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */ -#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */ -#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */ -#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */ -#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */ -#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */ -#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */ -#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */ -#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */ -#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */ - -/* CAN_MBTIF1 Masks */ -#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */ -#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */ -#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */ -#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */ -#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */ -#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */ -#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */ -#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */ -#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */ -#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */ -#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */ -#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */ -#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */ -#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */ -#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */ -#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */ - -/* CAN_MBTIF2 Masks */ -#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */ -#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */ -#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */ -#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */ -#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */ -#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */ -#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */ -#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */ -#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */ -#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */ -#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */ -#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */ -#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */ -#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */ -#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */ -#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */ - -/* CAN_MBRIF1 Masks */ -#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */ -#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */ -#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */ -#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */ -#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */ -#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */ -#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */ -#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */ -#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */ -#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */ -#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */ -#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */ -#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */ -#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */ -#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */ -#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */ - -/* CAN_MBRIF2 Masks */ -#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */ -#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */ -#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */ -#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */ -#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */ -#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */ -#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */ -#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */ -#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */ -#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */ -#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */ -#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */ -#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */ -#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */ -#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */ -#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */ - -/* CAN_MBIM1 Masks */ -#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */ -#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */ -#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */ -#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */ -#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */ -#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */ -#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */ -#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */ -#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */ -#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */ -#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */ -#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */ -#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */ -#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */ -#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */ -#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */ - -/* CAN_MBIM2 Masks */ -#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */ -#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */ -#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */ -#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */ -#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */ -#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */ -#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */ -#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */ -#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */ -#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */ -#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */ -#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */ -#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */ -#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */ -#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */ -#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */ - -/* CAN_GIM Masks */ -#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */ -#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */ -#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */ -#define BOIM 0x0008 /* Enable Bus Off Interrupt */ -#define WUIM 0x0010 /* Enable Wake-Up Interrupt */ -#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */ -#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */ -#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */ -#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */ -#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */ -#define ADIM 0x0400 /* Enable Access Denied Interrupt */ - -/* CAN_GIS Masks */ -#define EWTIS 0x0001 /* TX Error Count IRQ Status */ -#define EWRIS 0x0002 /* RX Error Count IRQ Status */ -#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */ -#define BOIS 0x0008 /* Bus Off IRQ Status */ -#define WUIS 0x0010 /* Wake-Up IRQ Status */ -#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */ -#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */ -#define RMLIS 0x0080 /* RX Message Lost IRQ Status */ -#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */ -#define EXTIS 0x0200 /* External Trigger Output IRQ Status */ -#define ADIS 0x0400 /* Access Denied IRQ Status */ - -/* CAN_GIF Masks */ -#define EWTIF 0x0001 /* TX Error Count IRQ Flag */ -#define EWRIF 0x0002 /* RX Error Count IRQ Flag */ -#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */ -#define BOIF 0x0008 /* Bus Off IRQ Flag */ -#define WUIF 0x0010 /* Wake-Up IRQ Flag */ -#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */ -#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */ -#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */ -#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */ -#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */ -#define ADIF 0x0400 /* Access Denied IRQ Flag */ - -/* CAN_UCCNF Masks */ -#define UCCNF 0x000F /* Universal Counter Mode */ -#define UC_STAMP 0x0001 /* Timestamp Mode */ -#define UC_WDOG 0x0002 /* Watchdog Mode */ -#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */ -#define UC_ERROR 0x0006 /* CAN Error Frame Count */ -#define UC_OVER 0x0007 /* CAN Overload Frame Count */ -#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */ -#define UC_AA 0x0009 /* TX Abort Count */ -#define UC_TA 0x000A /* TX Successful Count */ -#define UC_REJECT 0x000B /* RX Message Rejected Count */ -#define UC_RML 0x000C /* RX Message Lost Count */ -#define UC_RX 0x000D /* Total Successful RX Messages Count */ -#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */ -#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */ -#define UCRC 0x0020 /* Universal Counter Reload/Clear */ -#define UCCT 0x0040 /* Universal Counter CAN Trigger */ -#define UCE 0x0080 /* Universal Counter Enable */ - -/* CAN_ESR Masks */ -#define ACKE 0x0004 /* Acknowledge Error */ -#define SER 0x0008 /* Stuff Error */ -#define CRCE 0x0010 /* CRC Error */ -#define SA0 0x0020 /* Stuck At Dominant Error */ -#define BEF 0x0040 /* Bit Error Flag */ -#define FER 0x0080 /* Form Error Flag */ - -/* CAN_EWR Masks */ -#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */ -#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */ /* ******************* PIN CONTROL REGISTER MASKS ************************/ /* PORT_MUX Masks */ @@ -2490,24 +1451,6 @@ #define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ #define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ -/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/ -/* HDMAx_CTL Masks */ -#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */ -#define REP 0x0002 /* HDMA Request Polarity */ -#define UTE 0x0004 /* Urgency Threshold Enable */ -#define OIE 0x0010 /* Overflow Interrupt Enable */ -#define BDIE 0x0020 /* Block Done Interrupt Enable */ -#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */ -#define DRQ 0x0300 /* HDMA Request Type */ -#define DRQ_NONE 0x0000 /* No Request */ -#define DRQ_SINGLE 0x0100 /* Channels Request Single */ -#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */ -#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */ -#define RBC 0x1000 /* Reload BCNT With IBCNT */ -#define PS 0x2000 /* HDMA Pin Status */ -#define OI 0x4000 /* Overflow Interrupt Generated */ -#define BDI 0x8000 /* Block Done Interrupt Generated */ - /* entry addresses of the user-callable Boot ROM functions */ #define _BOOTROM_RESET 0xEF000000 diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h index 3d6c83e31b1..e10332c9f66 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF537.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF537.h @@ -1,40 +1,12 @@ /* - * file: include/asm-blackfin/mach-bf537/defbf537.h - * based on: - * author: + * Copyright 2005-2010 Analog Devices Inc. * - * created: - * description: - * system mmr register map - * rev: - * - * modified: - * - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF537_H #define _DEF_BF537_H -/* Include all Core registers and bit definitions*/ -#include <asm/cdef_LPBlackfin.h> - /* Include all MMR and bit defines common to BF534 */ #include "defBF534.h" diff --git a/arch/blackfin/mach-bf537/include/mach/gpio.h b/arch/blackfin/mach-bf537/include/mach/gpio.h index d77a31e45a3..fba606b699c 100644 --- a/arch/blackfin/mach-bf537/include/mach/gpio.h +++ b/arch/blackfin/mach-bf537/include/mach/gpio.h @@ -1,7 +1,4 @@ /* - * File: arch/blackfin/mach-bf537/include/mach/gpio.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * * Copyright (C) 2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ @@ -12,57 +9,61 @@ #define MAX_BLACKFIN_GPIOS 48 -#define GPIO_PF0 0 -#define GPIO_PF1 1 -#define GPIO_PF2 2 -#define GPIO_PF3 3 -#define GPIO_PF4 4 -#define GPIO_PF5 5 -#define GPIO_PF6 6 -#define GPIO_PF7 7 -#define GPIO_PF8 8 -#define GPIO_PF9 9 -#define GPIO_PF10 10 -#define GPIO_PF11 11 -#define GPIO_PF12 12 -#define GPIO_PF13 13 -#define GPIO_PF14 14 -#define GPIO_PF15 15 -#define GPIO_PG0 16 -#define GPIO_PG1 17 -#define GPIO_PG2 18 -#define GPIO_PG3 19 -#define GPIO_PG4 20 -#define GPIO_PG5 21 -#define GPIO_PG6 22 -#define GPIO_PG7 23 -#define GPIO_PG8 24 -#define GPIO_PG9 25 -#define GPIO_PG10 26 -#define GPIO_PG11 27 -#define GPIO_PG12 28 -#define GPIO_PG13 29 -#define GPIO_PG14 30 -#define GPIO_PG15 31 -#define GPIO_PH0 32 -#define GPIO_PH1 33 -#define GPIO_PH2 34 -#define GPIO_PH3 35 -#define GPIO_PH4 36 -#define GPIO_PH5 37 -#define GPIO_PH6 38 -#define GPIO_PH7 39 -#define GPIO_PH8 40 -#define GPIO_PH9 41 -#define GPIO_PH10 42 -#define GPIO_PH11 43 -#define GPIO_PH12 44 -#define GPIO_PH13 45 -#define GPIO_PH14 46 -#define GPIO_PH15 47 +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 +#define GPIO_PG0 16 +#define GPIO_PG1 17 +#define GPIO_PG2 18 +#define GPIO_PG3 19 +#define GPIO_PG4 20 +#define GPIO_PG5 21 +#define GPIO_PG6 22 +#define GPIO_PG7 23 +#define GPIO_PG8 24 +#define GPIO_PG9 25 +#define GPIO_PG10 26 +#define GPIO_PG11 27 +#define GPIO_PG12 28 +#define GPIO_PG13 29 +#define GPIO_PG14 30 +#define GPIO_PG15 31 +#define GPIO_PH0 32 +#define GPIO_PH1 33 +#define GPIO_PH2 34 +#define GPIO_PH3 35 +#define GPIO_PH4 36 +#define GPIO_PH5 37 +#define GPIO_PH6 38 +#define GPIO_PH7 39 +#define GPIO_PH8 40 +#define GPIO_PH9 41 +#define GPIO_PH10 42 +#define GPIO_PH11 43 +#define GPIO_PH12 44 +#define GPIO_PH13 45 +#define GPIO_PH14 46 +#define GPIO_PH15 47 #define PORT_F GPIO_PF0 #define PORT_G GPIO_PG0 #define PORT_H GPIO_PH0 +#include <mach-common/ports-f.h> +#include <mach-common/ports-g.h> +#include <mach-common/ports-h.h> + #endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h index b2a71d5d4e5..b6ed8235bda 100644 --- a/arch/blackfin/mach-bf537/include/mach/irq.h +++ b/arch/blackfin/mach-bf537/include/mach/irq.h @@ -1,214 +1,184 @@ /* - * file: include/asm-blackfin/mach-bf537/irq.h - * based on: - * author: + * Copyright 2005-2008 Analog Devices Inc. * - * created: - * description: - * system mmr register map - * rev: - * - * modified: - * - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. + * Licensed under the GPL-2 or later */ #ifndef _BF537_IRQ_H_ #define _BF537_IRQ_H_ -/* - * Interrupt source definitions - * Event Source Core Event Name - * Core Emulation ** - * Events (highest priority) EMU 0 - * Reset RST 1 - * NMI NMI 2 - * Exception EVX 3 - * Reserved -- 4 - * Hardware Error IVHW 5 - * Core Timer IVTMR 6 - * ..... - * - * Softirq IVG14 - * System Call -- - * (lowest priority) IVG15 - */ - -#define SYS_IRQS 39 -#define NR_PERI_INTS 32 - -/* The ABSTRACT IRQ definitions */ -/** the first seven of the following are fixed, the rest you change if you need to **/ -#define IRQ_EMU 0 /*Emulation */ -#define IRQ_RST 1 /*reset */ -#define IRQ_NMI 2 /*Non Maskable */ -#define IRQ_EVX 3 /*Exception */ -#define IRQ_UNUSED 4 /*- unused interrupt*/ -#define IRQ_HWERR 5 /*Hardware Error */ -#define IRQ_CORETMR 6 /*Core timer */ - -#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */ -#define IRQ_DMA_ERROR 8 /*DMA Error (general) */ -#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */ -#define IRQ_RTC 10 /*RTC Interrupt */ -#define IRQ_PPI 11 /*DMA0 Interrupt (PPI) */ -#define IRQ_SPORT0_RX 12 /*DMA3 Interrupt (SPORT0 RX) */ -#define IRQ_SPORT0_TX 13 /*DMA4 Interrupt (SPORT0 TX) */ -#define IRQ_SPORT1_RX 14 /*DMA5 Interrupt (SPORT1 RX) */ -#define IRQ_SPORT1_TX 15 /*DMA6 Interrupt (SPORT1 TX) */ -#define IRQ_TWI 16 /*TWI Interrupt */ -#define IRQ_SPI 17 /*DMA7 Interrupt (SPI) */ -#define IRQ_UART0_RX 18 /*DMA8 Interrupt (UART0 RX) */ -#define IRQ_UART0_TX 19 /*DMA9 Interrupt (UART0 TX) */ -#define IRQ_UART1_RX 20 /*DMA10 Interrupt (UART1 RX) */ -#define IRQ_UART1_TX 21 /*DMA11 Interrupt (UART1 TX) */ -#define IRQ_CAN_RX 22 /*CAN Receive Interrupt */ -#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */ -#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */ -#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */ -#define IRQ_TIMER0 26 /*Timer 0 */ -#define IRQ_TIMER1 27 /*Timer 1 */ -#define IRQ_TIMER2 28 /*Timer 2 */ -#define IRQ_TIMER3 29 /*Timer 3 */ -#define IRQ_TIMER4 30 /*Timer 4 */ -#define IRQ_TIMER5 31 /*Timer 5 */ -#define IRQ_TIMER6 32 /*Timer 6 */ -#define IRQ_TIMER7 33 /*Timer 7 */ -#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */ -#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */ -#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */ -#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */ -#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */ -#define IRQ_WATCH 38 /*Watch Dog Timer */ - -#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */ -#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */ -#define IRQ_MAC_ERROR 44 /*PPI Error Interrupt */ -#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */ -#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */ -#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */ -#define IRQ_UART0_ERROR 48 /*UART Error Interrupt */ -#define IRQ_UART1_ERROR 49 /*UART Error Interrupt */ - -#define IRQ_PF0 50 -#define IRQ_PF1 51 -#define IRQ_PF2 52 -#define IRQ_PF3 53 -#define IRQ_PF4 54 -#define IRQ_PF5 55 -#define IRQ_PF6 56 -#define IRQ_PF7 57 -#define IRQ_PF8 58 -#define IRQ_PF9 59 -#define IRQ_PF10 60 -#define IRQ_PF11 61 -#define IRQ_PF12 62 -#define IRQ_PF13 63 -#define IRQ_PF14 64 -#define IRQ_PF15 65 - -#define IRQ_PG0 66 -#define IRQ_PG1 67 -#define IRQ_PG2 68 -#define IRQ_PG3 69 -#define IRQ_PG4 70 -#define IRQ_PG5 71 -#define IRQ_PG6 72 -#define IRQ_PG7 73 -#define IRQ_PG8 74 -#define IRQ_PG9 75 -#define IRQ_PG10 76 -#define IRQ_PG11 77 -#define IRQ_PG12 78 -#define IRQ_PG13 79 -#define IRQ_PG14 80 -#define IRQ_PG15 81 - -#define IRQ_PH0 82 -#define IRQ_PH1 83 -#define IRQ_PH2 84 -#define IRQ_PH3 85 -#define IRQ_PH4 86 -#define IRQ_PH5 87 -#define IRQ_PH6 88 -#define IRQ_PH7 89 -#define IRQ_PH8 90 -#define IRQ_PH9 91 -#define IRQ_PH10 92 -#define IRQ_PH11 93 -#define IRQ_PH12 94 -#define IRQ_PH13 95 -#define IRQ_PH14 96 -#define IRQ_PH15 97 - -#define GPIO_IRQ_BASE IRQ_PF0 - -#define NR_IRQS (IRQ_PH15+1) - -#define IVG7 7 -#define IVG8 8 -#define IVG9 9 -#define IVG10 10 -#define IVG11 11 -#define IVG12 12 -#define IVG13 13 -#define IVG14 14 -#define IVG15 15 - -/* IAR0 BIT FIELDS*/ -#define IRQ_PLL_WAKEUP_POS 0 -#define IRQ_DMA_ERROR_POS 4 -#define IRQ_ERROR_POS 8 -#define IRQ_RTC_POS 12 -#define IRQ_PPI_POS 16 -#define IRQ_SPORT0_RX_POS 20 -#define IRQ_SPORT0_TX_POS 24 -#define IRQ_SPORT1_RX_POS 28 - -/* IAR1 BIT FIELDS*/ -#define IRQ_SPORT1_TX_POS 0 -#define IRQ_TWI_POS 4 -#define IRQ_SPI_POS 8 -#define IRQ_UART0_RX_POS 12 -#define IRQ_UART0_TX_POS 16 -#define IRQ_UART1_RX_POS 20 -#define IRQ_UART1_TX_POS 24 -#define IRQ_CAN_RX_POS 28 - -/* IAR2 BIT FIELDS*/ -#define IRQ_CAN_TX_POS 0 -#define IRQ_MAC_RX_POS 4 -#define IRQ_MAC_TX_POS 8 -#define IRQ_TIMER0_POS 12 -#define IRQ_TIMER1_POS 16 -#define IRQ_TIMER2_POS 20 -#define IRQ_TIMER3_POS 24 -#define IRQ_TIMER4_POS 28 - -/* IAR3 BIT FIELDS*/ -#define IRQ_TIMER5_POS 0 -#define IRQ_TIMER6_POS 4 -#define IRQ_TIMER7_POS 8 -#define IRQ_PROG_INTA_POS 12 -#define IRQ_PORTG_INTB_POS 16 -#define IRQ_MEM_DMA0_POS 20 -#define IRQ_MEM_DMA1_POS 24 -#define IRQ_WATCH_POS 28 - -#endif /* _BF537_IRQ_H_ */ +#include <mach-common/irq.h> + +#define NR_PERI_INTS 32 + +#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ +#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */ +#define IRQ_GENERIC_ERROR BFIN_IRQ(2) /* GENERIC Error Interrupt */ +#define IRQ_RTC BFIN_IRQ(3) /* RTC Interrupt */ +#define IRQ_PPI BFIN_IRQ(4) /* DMA0 Interrupt (PPI) */ +#define IRQ_SPORT0_RX BFIN_IRQ(5) /* DMA3 Interrupt (SPORT0 RX) */ +#define IRQ_SPORT0_TX BFIN_IRQ(6) /* DMA4 Interrupt (SPORT0 TX) */ +#define IRQ_SPORT1_RX BFIN_IRQ(7) /* DMA5 Interrupt (SPORT1 RX) */ +#define IRQ_SPORT1_TX BFIN_IRQ(8) /* DMA6 Interrupt (SPORT1 TX) */ +#define IRQ_TWI BFIN_IRQ(9) /* TWI Interrupt */ +#define IRQ_SPI BFIN_IRQ(10) /* DMA7 Interrupt (SPI) */ +#define IRQ_UART0_RX BFIN_IRQ(11) /* DMA8 Interrupt (UART0 RX) */ +#define IRQ_UART0_TX BFIN_IRQ(12) /* DMA9 Interrupt (UART0 TX) */ +#define IRQ_UART1_RX BFIN_IRQ(13) /* DMA10 Interrupt (UART1 RX) */ +#define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */ +#define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */ +#define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */ +#define IRQ_PH_INTA_MAC_RX BFIN_IRQ(17) /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */ +#define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */ +#define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */ +#define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */ +#define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */ +#define IRQ_TIMER3 BFIN_IRQ(22) /* Timer 3 */ +#define IRQ_TIMER4 BFIN_IRQ(23) /* Timer 4 */ +#define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */ +#define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */ +#define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */ +#define IRQ_PF_INTA_PG_INTA BFIN_IRQ(27) /* Ports F&G Interrupt A */ +#define IRQ_PORTG_INTB BFIN_IRQ(28) /* Port G Interrupt B */ +#define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */ +#define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */ +#define IRQ_PF_INTB_WATCH BFIN_IRQ(31) /* Watchdog & Port F Interrupt B */ + +#define SYS_IRQS 39 + +#define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */ +#define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */ +#define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */ +#define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */ +#define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */ +#define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */ +#define IRQ_UART0_ERROR 48 /* UART Error Interrupt */ +#define IRQ_UART1_ERROR 49 /* UART Error Interrupt */ + +#define IRQ_PF0 50 +#define IRQ_PF1 51 +#define IRQ_PF2 52 +#define IRQ_PF3 53 +#define IRQ_PF4 54 +#define IRQ_PF5 55 +#define IRQ_PF6 56 +#define IRQ_PF7 57 +#define IRQ_PF8 58 +#define IRQ_PF9 59 +#define IRQ_PF10 60 +#define IRQ_PF11 61 +#define IRQ_PF12 62 +#define IRQ_PF13 63 +#define IRQ_PF14 64 +#define IRQ_PF15 65 + +#define IRQ_PG0 66 +#define IRQ_PG1 67 +#define IRQ_PG2 68 +#define IRQ_PG3 69 +#define IRQ_PG4 70 +#define IRQ_PG5 71 +#define IRQ_PG6 72 +#define IRQ_PG7 73 +#define IRQ_PG8 74 +#define IRQ_PG9 75 +#define IRQ_PG10 76 +#define IRQ_PG11 77 +#define IRQ_PG12 78 +#define IRQ_PG13 79 +#define IRQ_PG14 80 +#define IRQ_PG15 81 + +#define IRQ_PH0 82 +#define IRQ_PH1 83 +#define IRQ_PH2 84 +#define IRQ_PH3 85 +#define IRQ_PH4 86 +#define IRQ_PH5 87 +#define IRQ_PH6 88 +#define IRQ_PH7 89 +#define IRQ_PH8 90 +#define IRQ_PH9 91 +#define IRQ_PH10 92 +#define IRQ_PH11 93 +#define IRQ_PH12 94 +#define IRQ_PH13 95 +#define IRQ_PH14 96 +#define IRQ_PH15 97 + +#define GPIO_IRQ_BASE IRQ_PF0 + +#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */ +#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */ +#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */ +#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */ +#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */ +#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */ +#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */ +#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */ + +#define IRQ_MAC_RX 106 /* DMA1 Interrupt (Ethernet RX) */ +#define IRQ_PORTH_INTA 107 /* Port H Interrupt A */ + +#if 0 /* No Interrupt B support (yet) */ +#define IRQ_MAC_TX 108 /* DMA2 Interrupt (Ethernet TX) */ +#define IRQ_PORTH_INTB 109 /* Port H Interrupt B */ +#else +#define IRQ_MAC_TX IRQ_PH_INTB_MAC_TX +#endif + +#define IRQ_PORTF_INTA 110 /* Port F Interrupt A */ +#define IRQ_PORTG_INTA 111 /* Port G Interrupt A */ + +#if 0 /* No Interrupt B support (yet) */ +#define IRQ_WATCH 112 /* Watchdog Timer */ +#define IRQ_PORTF_INTB 113 /* Port F Interrupt B */ +#else +#define IRQ_WATCH IRQ_PF_INTB_WATCH +#endif + +#define NR_MACH_IRQS (113 + 1) + +/* IAR0 BIT FIELDS */ +#define IRQ_PLL_WAKEUP_POS 0 +#define IRQ_DMA_ERROR_POS 4 +#define IRQ_ERROR_POS 8 +#define IRQ_RTC_POS 12 +#define IRQ_PPI_POS 16 +#define IRQ_SPORT0_RX_POS 20 +#define IRQ_SPORT0_TX_POS 24 +#define IRQ_SPORT1_RX_POS 28 + +/* IAR1 BIT FIELDS */ +#define IRQ_SPORT1_TX_POS 0 +#define IRQ_TWI_POS 4 +#define IRQ_SPI_POS 8 +#define IRQ_UART0_RX_POS 12 +#define IRQ_UART0_TX_POS 16 +#define IRQ_UART1_RX_POS 20 +#define IRQ_UART1_TX_POS 24 +#define IRQ_CAN_RX_POS 28 + +/* IAR2 BIT FIELDS */ +#define IRQ_CAN_TX_POS 0 +#define IRQ_MAC_RX_POS 4 +#define IRQ_MAC_TX_POS 8 +#define IRQ_TIMER0_POS 12 +#define IRQ_TIMER1_POS 16 +#define IRQ_TIMER2_POS 20 +#define IRQ_TIMER3_POS 24 +#define IRQ_TIMER4_POS 28 + +/* IAR3 BIT FIELDS */ +#define IRQ_TIMER5_POS 0 +#define IRQ_TIMER6_POS 4 +#define IRQ_TIMER7_POS 8 +#define IRQ_PROG_INTA_POS 12 +#define IRQ_PORTG_INTB_POS 16 +#define IRQ_MEM_DMA0_POS 20 +#define IRQ_MEM_DMA1_POS 24 +#define IRQ_WATCH_POS 28 + +#define init_mach_irq init_mach_irq + +#endif diff --git a/arch/blackfin/mach-bf537/include/mach/mem_map.h b/arch/blackfin/mach-bf537/include/mach/mem_map.h index f9010c4b4bf..942f08de306 100644 --- a/arch/blackfin/mach-bf537/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf537/include/mach/mem_map.h @@ -1,38 +1,16 @@ /* - * file: include/asm-blackfin/mach-bf537/mem_map.h - * based on: - * author: + * BF537 memory map * - * created: - * description: - * Memory MAP Common header file for blackfin BF537/6/4 of processors. - * rev: - * - * modified: - * - * bugs: enter bugs at http://blackfin.uclinux.org/ - * - * this program is free software; you can redistribute it and/or modify - * it under the terms of the gnu general public license as published by - * the free software foundation; either version 2, or (at your option) - * any later version. - * - * this program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * merchantability or fitness for a particular purpose. see the - * gnu general public license for more details. - * - * you should have received a copy of the gnu general public license - * along with this program; see the file copying. - * if not, write to the free software foundation, - * 59 temple place - suite 330, boston, ma 02111-1307, usa. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ -#ifndef _MEM_MAP_537_H_ -#define _MEM_MAP_537_H_ +#ifndef __BFIN_MACH_MEM_MAP_H__ +#define __BFIN_MACH_MEM_MAP_H__ -#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ -#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ +#ifndef __BFIN_MEM_MAP_H__ +# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" +#endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ @@ -166,20 +144,4 @@ #endif -/* Level 2 Memory - none */ - -#define L2_START 0 -#define L2_LENGTH 0 - -/* Scratch Pad Memory */ - -#define L1_SCRATCH_START 0xFFB00000 -#define L1_SCRATCH_LENGTH 0x1000 - -#define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; - -#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) - -#endif /* _MEM_MAP_537_H_ */ +#endif diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h new file mode 100644 index 00000000000..94cca674d83 --- /dev/null +++ b/arch/blackfin/mach-bf537/include/mach/pll.h @@ -0,0 +1 @@ +#include <mach-common/pll.h> diff --git a/arch/blackfin/mach-bf537/include/mach/portmux.h b/arch/blackfin/mach-bf537/include/mach/portmux.h index 87285e75e90..71d9eaeb579 100644 --- a/arch/blackfin/mach-bf537/include/mach/portmux.h +++ b/arch/blackfin/mach-bf537/include/mach/portmux.h @@ -1,7 +1,13 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + #ifndef _MACH_PORTMUX_H_ #define _MACH_PORTMUX_H_ -#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */ +#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */ #define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) #define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) @@ -31,6 +37,7 @@ #define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) #define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) #define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) +#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10 #define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 #define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) @@ -129,7 +136,6 @@ P_MDC, \ P_MDIO, 0} - #define P_RMII0 {\ P_MII0_ETxD0, \ P_MII0_ETxD1, \ @@ -142,4 +148,5 @@ P_RMII0_CRS_DV, \ P_MDC, \ P_MDIO, 0} -#endif /* _MACH_PORTMUX_H_ */ + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c index 51c48087e03..2137a209a22 100644 --- a/arch/blackfin/mach-bf537/ints-priority.c +++ b/arch/blackfin/mach-bf537/ints-priority.c @@ -1,36 +1,22 @@ /* - * File: arch/blackfin/mach-bf537/ints-priority.c - * Based on: arch/blackfin/mach-bf533/ints-priority.c - * Author: Michael Hennerich + * Copyright 2005-2009 Analog Devices Inc. * - * Created: - * Description: Set up the interrupt priorities + * Licensed under the GPL-2 or later. * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Set up the interrupt priorities */ #include <linux/module.h> #include <linux/irq.h> #include <asm/blackfin.h> +#include <asm/irq_handler.h> +#include <asm/bfin5xx_spi.h> +#include <asm/bfin_sport.h> +#include <asm/bfin_can.h> +#include <asm/bfin_dma.h> +#include <asm/dpmc.h> + void __init program_IAR(void) { /* Program the IAR0 Register with the configured priority */ @@ -72,3 +58,159 @@ void __init program_IAR(void) SSYNC(); } + +#define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */ +#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */ +#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */ +#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */ +#define UART_ERR_MASK (0x6) /* UART_IIR */ +#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */ + +static int error_int_mask; + +static void bf537_generic_error_mask_irq(struct irq_data *d) +{ + error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR)); + if (!error_int_mask) + bfin_internal_mask_irq(IRQ_GENERIC_ERROR); +} + +static void bf537_generic_error_unmask_irq(struct irq_data *d) +{ + bfin_internal_unmask_irq(IRQ_GENERIC_ERROR); + error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR); +} + +static struct irq_chip bf537_generic_error_irqchip = { + .name = "ERROR", + .irq_ack = bfin_ack_noop, + .irq_mask_ack = bf537_generic_error_mask_irq, + .irq_mask = bf537_generic_error_mask_irq, + .irq_unmask = bf537_generic_error_unmask_irq, +}; + +static void bf537_demux_error_irq(unsigned int int_err_irq, + struct irq_desc *inta_desc) +{ + int irq = 0; + +#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) + if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK) + irq = IRQ_MAC_ERROR; + else +#endif + if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK) + irq = IRQ_SPORT0_ERROR; + else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK) + irq = IRQ_SPORT1_ERROR; + else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK) + irq = IRQ_PPI_ERROR; + else if (bfin_read_CAN_GIF() & CAN_ERR_MASK) + irq = IRQ_CAN_ERROR; + else if (bfin_read_SPI_STAT() & SPI_ERR_MASK) + irq = IRQ_SPI_ERROR; + else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK) + irq = IRQ_UART0_ERROR; + else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK) + irq = IRQ_UART1_ERROR; + + if (irq) { + if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) + bfin_handle_irq(irq); + else { + + switch (irq) { + case IRQ_PPI_ERROR: + bfin_write_PPI_STATUS(PPI_ERR_MASK); + break; +#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) + case IRQ_MAC_ERROR: + bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK); + break; +#endif + case IRQ_SPORT0_ERROR: + bfin_write_SPORT0_STAT(SPORT_ERR_MASK); + break; + + case IRQ_SPORT1_ERROR: + bfin_write_SPORT1_STAT(SPORT_ERR_MASK); + break; + + case IRQ_CAN_ERROR: + bfin_write_CAN_GIS(CAN_ERR_MASK); + break; + + case IRQ_SPI_ERROR: + bfin_write_SPI_STAT(SPI_ERR_MASK); + break; + + default: + break; + } + + pr_debug("IRQ %d:" + " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n", + irq); + } + } else + pr_err("%s: IRQ ?: PERIPHERAL ERROR INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", + __func__); + +} + +#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) +static int mac_rx_int_mask; + +static void bf537_mac_rx_mask_irq(struct irq_data *d) +{ + mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX)); + if (!mac_rx_int_mask) + bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX); +} + +static void bf537_mac_rx_unmask_irq(struct irq_data *d) +{ + bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX); + mac_rx_int_mask |= 1L << (d->irq - IRQ_MAC_RX); +} + +static struct irq_chip bf537_mac_rx_irqchip = { + .name = "ERROR", + .irq_ack = bfin_ack_noop, + .irq_mask_ack = bf537_mac_rx_mask_irq, + .irq_mask = bf537_mac_rx_mask_irq, + .irq_unmask = bf537_mac_rx_unmask_irq, +}; + +static void bf537_demux_mac_rx_irq(unsigned int int_irq, + struct irq_desc *desc) +{ + if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR)) + bfin_handle_irq(IRQ_MAC_RX); + else + bfin_demux_gpio_irq(int_irq, desc); +} +#endif + +void __init init_mach_irq(void) +{ + int irq; + +#if defined(CONFIG_BF537) || defined(CONFIG_BF536) + /* Clear EMAC Interrupt Status bits so we can demux it later */ + bfin_write_EMAC_SYSTAT(-1); +#endif + + irq_set_chained_handler(IRQ_GENERIC_ERROR, bf537_demux_error_irq); + for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) + irq_set_chip_and_handler(irq, &bf537_generic_error_irqchip, + handle_level_irq); + +#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) + irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq); + irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq); + irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq); + + irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq); +#endif +} |