diff options
Diffstat (limited to 'arch/blackfin/mach-bf527/include/mach')
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/anomaly.h | 44 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h | 79 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/cdefBF522.h | 16 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/defBF522.h | 81 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/defBF525.h | 6 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/defBF527.h | 2 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/irq.h | 266 |
7 files changed, 158 insertions, 336 deletions
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h index 9358afa05c9..2f9cc33deec 100644 --- a/arch/blackfin/mach-bf527/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h @@ -5,14 +5,13 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. - * Licensed under the ADI BSD license. - * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd + * Copyright 2004-2011 Analog Devices Inc. + * Licensed under the Clear BSD license. */ /* This file should be up to date with: - * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List - * - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List + * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List + * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -57,7 +56,7 @@ /* Incorrect Access of OTP_STATUS During otp_write() Function */ #define ANOMALY_05000328 (_ANOMALY_BF527(< 2)) /* Host DMA Boot Modes Are Not Functional */ -#define ANOMALY_05000330 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000330 (_ANOMALY_BF527(< 2)) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ #define ANOMALY_05000337 (_ANOMALY_BF527(< 2)) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ @@ -135,7 +134,7 @@ /* Incorrect Default Internal Voltage Regulator Setting */ #define ANOMALY_05000410 (_ANOMALY_BF527(< 2)) /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ -#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2)) +#define ANOMALY_05000411 (_ANOMALY_BF526(< 1)) /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ #define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2)) /* DEB2_URGENT Bit Not Functional */ @@ -181,11 +180,11 @@ /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) /* The WURESET Bit in the SYSCR Register is not Functional */ -#define ANOMALY_05000445 (1) -/* USB DMA Mode 1 Short Packet Data Corruption */ +#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0)) +/* USB DMA Short Packet Data Corruption */ #define ANOMALY_05000450 (1) /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ -#define ANOMALY_05000451 (1) +#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0)) /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ #define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0)) /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ @@ -198,19 +197,19 @@ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ #define ANOMALY_05000462 (1) -/* USB Rx DMA hang */ +/* USB Rx DMA Hang */ #define ANOMALY_05000465 (1) /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ #define ANOMALY_05000466 (1) -/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ +/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */ #define ANOMALY_05000467 (1) /* PLL Latches Incorrect Settings During Reset */ #define ANOMALY_05000469 (1) /* Incorrect Default MSEL Value in PLL_CTL */ #define ANOMALY_05000472 (_ANOMALY_BF526(>= 0)) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) @@ -219,9 +218,19 @@ /* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ #define ANOMALY_05000483 (1) /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ -#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3)) -/* IFLUSH sucks at life */ +#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0)) +/* The CODEC Zero-Cross Detect Feature is not Functional */ +#define ANOMALY_05000487 (1) +/* SPI Master Boot Can Fail Under Certain Conditions */ +#define ANOMALY_05000490 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */ +#define ANOMALY_05000498 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -268,11 +277,14 @@ #define ANOMALY_05000323 (0) #define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000400 (0) #define ANOMALY_05000402 (0) #define ANOMALY_05000412 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) #define ANOMALY_05000474 (0) +#define ANOMALY_05000480 (0) +#define ANOMALY_16000030 (0) #endif diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h deleted file mode 100644 index 960e08919de..00000000000 --- a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include <asm/dma.h> -#include <asm/portmux.h> - -#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) -# define CONFIG_SERIAL_BFIN_CTSRTS - -# ifndef CONFIG_UART0_CTS_PIN -# define CONFIG_UART0_CTS_PIN -1 -# endif - -# ifndef CONFIG_UART0_RTS_PIN -# define CONFIG_UART0_RTS_PIN -1 -# endif - -# ifndef CONFIG_UART1_CTS_PIN -# define CONFIG_UART1_CTS_PIN -1 -# endif - -# ifndef CONFIG_UART1_RTS_PIN -# define CONFIG_UART1_RTS_PIN -1 -# endif -#endif - -struct bfin_serial_res { - unsigned long uart_base_addr; - int uart_irq; - int uart_status_irq; -#ifdef CONFIG_SERIAL_BFIN_DMA - unsigned int uart_tx_dma_channel; - unsigned int uart_rx_dma_channel; -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - int uart_cts_pin; - int uart_rts_pin; -#endif -}; - -struct bfin_serial_res bfin_serial_resource[] = { -#ifdef CONFIG_SERIAL_BFIN_UART0 - { - 0xFFC00400, - IRQ_UART0_RX, - IRQ_UART0_ERROR, -#ifdef CONFIG_SERIAL_BFIN_DMA - CH_UART0_TX, - CH_UART0_RX, -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - CONFIG_UART0_CTS_PIN, - CONFIG_UART0_RTS_PIN, -#endif - }, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - { - 0xFFC02000, - IRQ_UART1_RX, - IRQ_UART1_ERROR, -#ifdef CONFIG_SERIAL_BFIN_DMA - CH_UART1_TX, - CH_UART1_RX, -#endif -#ifdef CONFIG_SERIAL_BFIN_CTSRTS - CONFIG_UART1_CTS_PIN, - CONFIG_UART1_RTS_PIN, -#endif - }, -#endif -}; - -#define DRIVER_NAME "bfin-uart" - -#include <asm/bfin_serial.h> diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h index 618dfcdfa91..2c12e879aa4 100644 --- a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h +++ b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h @@ -1007,18 +1007,18 @@ #define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) #define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) #define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) -#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS) -#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val) -#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS) -#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val) -#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS) -#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val) +#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS) +#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val) +#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS) +#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val) +#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS) +#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val) #define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE) #define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val) #define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW) #define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val) -#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS) -#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val) +#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS) +#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val) /* HOST Port Registers */ diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h index 84ef11e5264..e007017cf95 100644 --- a/arch/blackfin/mach-bf527/include/mach/defBF522.h +++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h @@ -1,7 +1,7 @@ /* * Copyright 2007-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF522_H @@ -562,12 +562,12 @@ #define PORTF_SLEW 0xFFC03230 /* Port F slew control */ #define PORTG_SLEW 0xFFC03234 /* Port G slew control */ #define PORTH_SLEW 0xFFC03238 /* Port H slew control */ -#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */ -#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */ -#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */ +#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */ +#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */ +#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */ #define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */ #define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */ -#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */ +#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */ /*********************************************************************************** @@ -1084,77 +1084,6 @@ #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ -/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ -/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ -#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ -#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ - -/* TWI_PRESCALE Masks */ -#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ -#define TWI_ENA 0x0080 /* TWI Enable */ -#define SCCB 0x0200 /* SCCB Compatibility Enable */ - -/* TWI_SLAVE_CTL Masks */ -#define SEN 0x0001 /* Slave Enable */ -#define SADD_LEN 0x0002 /* Slave Address Length */ -#define STDVAL 0x0004 /* Slave Transmit Data Valid */ -#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ -#define GEN 0x0010 /* General Call Adrress Matching Enabled */ - -/* TWI_SLAVE_STAT Masks */ -#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ -#define GCALL 0x0002 /* General Call Indicator */ - -/* TWI_MASTER_CTL Masks */ -#define MEN 0x0001 /* Master Mode Enable */ -#define MADD_LEN 0x0002 /* Master Address Length */ -#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ -#define FAST 0x0008 /* Use Fast Mode Timing Specs */ -#define STOP 0x0010 /* Issue Stop Condition */ -#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ -#define DCNT 0x3FC0 /* Data Bytes To Transfer */ -#define SDAOVR 0x4000 /* Serial Data Override */ -#define SCLOVR 0x8000 /* Serial Clock Override */ - -/* TWI_MASTER_STAT Masks */ -#define MPROG 0x0001 /* Master Transfer In Progress */ -#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ -#define ANAK 0x0004 /* Address Not Acknowledged */ -#define DNAK 0x0008 /* Data Not Acknowledged */ -#define BUFRDERR 0x0010 /* Buffer Read Error */ -#define BUFWRERR 0x0020 /* Buffer Write Error */ -#define SDASEN 0x0040 /* Serial Data Sense */ -#define SCLSEN 0x0080 /* Serial Clock Sense */ -#define BUSBUSY 0x0100 /* Bus Busy Indicator */ - -/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ -#define SINIT 0x0001 /* Slave Transfer Initiated */ -#define SCOMP 0x0002 /* Slave Transfer Complete */ -#define SERR 0x0004 /* Slave Transfer Error */ -#define SOVF 0x0008 /* Slave Overflow */ -#define MCOMP 0x0010 /* Master Transfer Complete */ -#define MERR 0x0020 /* Master Transfer Error */ -#define XMTSERV 0x0040 /* Transmit FIFO Service */ -#define RCVSERV 0x0080 /* Receive FIFO Service */ - -/* TWI_FIFO_CTRL Masks */ -#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ -#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ -#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ -#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ - -/* TWI_FIFO_STAT Masks */ -#define XMTSTAT 0x0003 /* Transmit FIFO Status */ -#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ -#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ -#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ - -#define RCVSTAT 0x000C /* Receive FIFO Status */ -#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ -#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ -#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ - - /* Omit CAN masks from defBF534.h */ /* ******************* PIN CONTROL REGISTER MASKS ************************/ diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h index cc383adfdff..71578d964d0 100644 --- a/arch/blackfin/mach-bf527/include/mach/defBF525.h +++ b/arch/blackfin/mach-bf527/include/mach/defBF525.h @@ -1,7 +1,7 @@ /* * Copyright 2007-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF525_H @@ -185,8 +185,8 @@ #define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ #define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */ #define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ +#define USB_EP_NI7_RXINTERVAL 0xffc03be0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ +#define USB_EP_NI7_TXCOUNT 0xffc03be8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ #define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */ diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h index 05369a92fbc..aeb84795b35 100644 --- a/arch/blackfin/mach-bf527/include/mach/defBF527.h +++ b/arch/blackfin/mach-bf527/include/mach/defBF527.h @@ -1,7 +1,7 @@ /* * Copyright 2007-2010 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the Clear BSD license or the GPL-2 (or later) */ #ifndef _DEF_BF527_H diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h index 704d9253e41..ed7310ff819 100644 --- a/arch/blackfin/mach-bf527/include/mach/irq.h +++ b/arch/blackfin/mach-bf527/include/mach/irq.h @@ -7,38 +7,9 @@ #ifndef _BF527_IRQ_H_ #define _BF527_IRQ_H_ -/* - * Interrupt source definitions - Event Source Core Event Name - Core Emulation ** - Events (highest priority) EMU 0 - Reset RST 1 - NMI NMI 2 - Exception EVX 3 - Reserved -- 4 - Hardware Error IVHW 5 - Core Timer IVTMR 6 * - - ..... - - Software Interrupt 1 IVG14 31 - Software Interrupt 2 -- - (lowest priority) IVG15 32 * -*/ - -#define NR_PERI_INTS (2 * 32) - -/* The ABSTRACT IRQ definitions */ -/** the first seven of the following are fixed, the rest you change if you need to **/ -#define IRQ_EMU 0 /* Emulation */ -#define IRQ_RST 1 /* reset */ -#define IRQ_NMI 2 /* Non Maskable */ -#define IRQ_EVX 3 /* Exception */ -#define IRQ_UNUSED 4 /* - unused interrupt */ -#define IRQ_HWERR 5 /* Hardware Error */ -#define IRQ_CORETMR 6 /* Core timer */ - -#define BFIN_IRQ(x) ((x) + 7) +#include <mach-common/irq.h> + +#define NR_PERI_INTS (2 * 32) #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ #define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ @@ -53,21 +24,21 @@ #define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */ #define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */ #define IRQ_RTC BFIN_IRQ(14) /* RTC */ -#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */ +#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */ #define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */ #define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */ #define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */ #define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */ -#define IRQ_TWI BFIN_IRQ(20) /* TWI */ -#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */ -#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */ -#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */ -#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */ -#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */ -#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */ -#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */ -#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */ -#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */ +#define IRQ_TWI BFIN_IRQ(20) /* TWI */ +#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */ +#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */ +#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */ +#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */ +#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */ +#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */ +#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */ +#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */ +#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */ #define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ #define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ #define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ @@ -96,119 +67,108 @@ #define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */ #define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */ -#define SYS_IRQS BFIN_IRQ(63) /* 70 */ - -#define IRQ_PF0 71 -#define IRQ_PF1 72 -#define IRQ_PF2 73 -#define IRQ_PF3 74 -#define IRQ_PF4 75 -#define IRQ_PF5 76 -#define IRQ_PF6 77 -#define IRQ_PF7 78 -#define IRQ_PF8 79 -#define IRQ_PF9 80 -#define IRQ_PF10 81 -#define IRQ_PF11 82 -#define IRQ_PF12 83 -#define IRQ_PF13 84 -#define IRQ_PF14 85 -#define IRQ_PF15 86 - -#define IRQ_PG0 87 -#define IRQ_PG1 88 -#define IRQ_PG2 89 -#define IRQ_PG3 90 -#define IRQ_PG4 91 -#define IRQ_PG5 92 -#define IRQ_PG6 93 -#define IRQ_PG7 94 -#define IRQ_PG8 95 -#define IRQ_PG9 96 -#define IRQ_PG10 97 -#define IRQ_PG11 98 -#define IRQ_PG12 99 -#define IRQ_PG13 100 -#define IRQ_PG14 101 -#define IRQ_PG15 102 - -#define IRQ_PH0 103 -#define IRQ_PH1 104 -#define IRQ_PH2 105 -#define IRQ_PH3 106 -#define IRQ_PH4 107 -#define IRQ_PH5 108 -#define IRQ_PH6 109 -#define IRQ_PH7 110 -#define IRQ_PH8 111 -#define IRQ_PH9 112 -#define IRQ_PH10 113 -#define IRQ_PH11 114 -#define IRQ_PH12 115 -#define IRQ_PH13 116 -#define IRQ_PH14 117 -#define IRQ_PH15 118 - -#define GPIO_IRQ_BASE IRQ_PF0 - -#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */ -#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */ -#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */ -#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */ -#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */ -#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */ -#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */ -#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */ - -#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) -#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS) - -#define IVG7 7 -#define IVG8 8 -#define IVG9 9 -#define IVG10 10 -#define IVG11 11 -#define IVG12 12 -#define IVG13 13 -#define IVG14 14 -#define IVG15 15 +#define SYS_IRQS BFIN_IRQ(63) /* 70 */ + +#define IRQ_PF0 71 +#define IRQ_PF1 72 +#define IRQ_PF2 73 +#define IRQ_PF3 74 +#define IRQ_PF4 75 +#define IRQ_PF5 76 +#define IRQ_PF6 77 +#define IRQ_PF7 78 +#define IRQ_PF8 79 +#define IRQ_PF9 80 +#define IRQ_PF10 81 +#define IRQ_PF11 82 +#define IRQ_PF12 83 +#define IRQ_PF13 84 +#define IRQ_PF14 85 +#define IRQ_PF15 86 + +#define IRQ_PG0 87 +#define IRQ_PG1 88 +#define IRQ_PG2 89 +#define IRQ_PG3 90 +#define IRQ_PG4 91 +#define IRQ_PG5 92 +#define IRQ_PG6 93 +#define IRQ_PG7 94 +#define IRQ_PG8 95 +#define IRQ_PG9 96 +#define IRQ_PG10 97 +#define IRQ_PG11 98 +#define IRQ_PG12 99 +#define IRQ_PG13 100 +#define IRQ_PG14 101 +#define IRQ_PG15 102 + +#define IRQ_PH0 103 +#define IRQ_PH1 104 +#define IRQ_PH2 105 +#define IRQ_PH3 106 +#define IRQ_PH4 107 +#define IRQ_PH5 108 +#define IRQ_PH6 109 +#define IRQ_PH7 110 +#define IRQ_PH8 111 +#define IRQ_PH9 112 +#define IRQ_PH10 113 +#define IRQ_PH11 114 +#define IRQ_PH12 115 +#define IRQ_PH13 116 +#define IRQ_PH14 117 +#define IRQ_PH15 118 + +#define GPIO_IRQ_BASE IRQ_PF0 + +#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */ +#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */ +#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */ +#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */ +#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */ +#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */ +#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */ +#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */ + +#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) /* IAR0 BIT FIELDS */ #define IRQ_PLL_WAKEUP_POS 0 #define IRQ_DMA0_ERROR_POS 4 -#define IRQ_DMAR0_BLK_POS 8 -#define IRQ_DMAR1_BLK_POS 12 -#define IRQ_DMAR0_OVR_POS 16 -#define IRQ_DMAR1_OVR_POS 20 -#define IRQ_PPI_ERROR_POS 24 -#define IRQ_MAC_ERROR_POS 28 +#define IRQ_DMAR0_BLK_POS 8 +#define IRQ_DMAR1_BLK_POS 12 +#define IRQ_DMAR0_OVR_POS 16 +#define IRQ_DMAR1_OVR_POS 20 +#define IRQ_PPI_ERROR_POS 24 +#define IRQ_MAC_ERROR_POS 28 /* IAR1 BIT FIELDS */ #define IRQ_SPORT0_ERROR_POS 0 #define IRQ_SPORT1_ERROR_POS 4 -#define IRQ_UART0_ERROR_POS 16 -#define IRQ_UART1_ERROR_POS 20 -#define IRQ_RTC_POS 24 -#define IRQ_PPI_POS 28 +#define IRQ_UART0_ERROR_POS 16 +#define IRQ_UART1_ERROR_POS 20 +#define IRQ_RTC_POS 24 +#define IRQ_PPI_POS 28 /* IAR2 BIT FIELDS */ #define IRQ_SPORT0_RX_POS 0 #define IRQ_SPORT0_TX_POS 4 #define IRQ_SPORT1_RX_POS 8 #define IRQ_SPORT1_TX_POS 12 -#define IRQ_TWI_POS 16 -#define IRQ_SPI_POS 20 -#define IRQ_UART0_RX_POS 24 -#define IRQ_UART0_TX_POS 28 +#define IRQ_TWI_POS 16 +#define IRQ_SPI_POS 20 +#define IRQ_UART0_RX_POS 24 +#define IRQ_UART0_TX_POS 28 /* IAR3 BIT FIELDS */ -#define IRQ_UART1_RX_POS 0 -#define IRQ_UART1_TX_POS 4 -#define IRQ_OPTSEC_POS 8 -#define IRQ_CNT_POS 12 -#define IRQ_MAC_RX_POS 16 +#define IRQ_UART1_RX_POS 0 +#define IRQ_UART1_TX_POS 4 +#define IRQ_OPTSEC_POS 8 +#define IRQ_CNT_POS 12 +#define IRQ_MAC_RX_POS 16 #define IRQ_PORTH_INTA_POS 20 -#define IRQ_MAC_TX_POS 24 +#define IRQ_MAC_TX_POS 24 #define IRQ_PORTH_INTB_POS 28 /* IAR4 BIT FIELDS */ @@ -224,21 +184,21 @@ /* IAR5 BIT FIELDS */ #define IRQ_PORTG_INTA_POS 0 #define IRQ_PORTG_INTB_POS 4 -#define IRQ_MEM_DMA0_POS 8 -#define IRQ_MEM_DMA1_POS 12 -#define IRQ_WATCH_POS 16 +#define IRQ_MEM_DMA0_POS 8 +#define IRQ_MEM_DMA1_POS 12 +#define IRQ_WATCH_POS 16 #define IRQ_PORTF_INTA_POS 20 #define IRQ_PORTF_INTB_POS 24 -#define IRQ_SPI_ERROR_POS 28 +#define IRQ_SPI_ERROR_POS 28 /* IAR6 BIT FIELDS */ -#define IRQ_NFC_ERROR_POS 0 -#define IRQ_HDMA_ERROR_POS 4 -#define IRQ_HDMA_POS 8 -#define IRQ_USB_EINT_POS 12 -#define IRQ_USB_INT0_POS 16 -#define IRQ_USB_INT1_POS 20 -#define IRQ_USB_INT2_POS 24 -#define IRQ_USB_DMA_POS 28 - -#endif /* _BF527_IRQ_H_ */ +#define IRQ_NFC_ERROR_POS 0 +#define IRQ_HDMA_ERROR_POS 4 +#define IRQ_HDMA_POS 8 +#define IRQ_USB_EINT_POS 12 +#define IRQ_USB_INT0_POS 16 +#define IRQ_USB_INT1_POS 20 +#define IRQ_USB_INT2_POS 24 +#define IRQ_USB_DMA_POS 28 + +#endif |