diff options
Diffstat (limited to 'arch/blackfin/include/asm/def_LPBlackfin.h')
| -rw-r--r-- | arch/blackfin/include/asm/def_LPBlackfin.h | 39 |
1 files changed, 38 insertions, 1 deletions
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h index f342ff0319d..c5c8d8a3a5f 100644 --- a/arch/blackfin/include/asm/def_LPBlackfin.h +++ b/arch/blackfin/include/asm/def_LPBlackfin.h @@ -3,7 +3,7 @@ * * Copyright 2005-2008 Analog Devices Inc. * - * Licensed under the ADI BSD license or GPL-2 (or later). + * Licensed under the Clear BSD license or GPL-2 (or later). */ #ifndef _DEF_LPBLACKFIN_H @@ -50,6 +50,35 @@ #define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w) #define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, ) +#define bfin_read(addr) \ +({ \ + sizeof(*(addr)) == 1 ? bfin_read8(addr) : \ + sizeof(*(addr)) == 2 ? bfin_read16(addr) : \ + sizeof(*(addr)) == 4 ? bfin_read32(addr) : \ + ({ BUG(); 0; }); \ +}) +#define bfin_write(addr, val) \ +do { \ + switch (sizeof(*(addr))) { \ + case 1: bfin_write8(addr, val); break; \ + case 2: bfin_write16(addr, val); break; \ + case 4: bfin_write32(addr, val); break; \ + default: BUG(); \ + } \ +} while (0) + +#define bfin_write_or(addr, bits) \ +do { \ + typeof(addr) __addr = (addr); \ + bfin_write(__addr, bfin_read(__addr) | (bits)); \ +} while (0) + +#define bfin_write_and(addr, bits) \ +do { \ + typeof(addr) __addr = (addr); \ + bfin_write(__addr, bfin_read(__addr) & (bits)); \ +} while (0) + #endif /* __ASSEMBLY__ */ /************************************************** @@ -377,6 +406,7 @@ #define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ #define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ #define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ +#define EVT_OVERRIDE 0xFFE02100 /* Event Vector Override Register */ #define IMASK 0xFFE02104 /* Interrupt Mask Register */ #define IPEND 0xFFE02108 /* Interrupt Pending Register */ #define ILAT 0xFFE0210C /* Interrupt Latch Register */ @@ -514,6 +544,7 @@ #define DCBS_P 0x04 /* L1 Data Cache Bank Select */ #define PORT_PREF0_P 0x12 /* DAG0 Port Preference */ #define PORT_PREF1_P 0x13 /* DAG1 Port Preference */ +#define RDCHK 0x9 /* Enable L1 Parity Check */ /* Masks */ #define ENDM 0x00000001 /* (doesn't really exist) Enable @@ -592,6 +623,12 @@ #define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ #define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ #define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ +#ifdef CONFIG_BF60x +#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */ +#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */ +#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */ +#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */ +#endif #define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not * mapped to L1 */ |