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-rw-r--r--arch/blackfin/Kconfig20
1 files changed, 9 insertions, 11 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 3b6abc54b01..f81e7b989ff 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -32,10 +32,9 @@ config BLACKFIN
select HAVE_UNDERSCORE_SYMBOL_PREFIX
select VIRT_TO_BUS
select ARCH_WANT_IPC_PARSE_VERSION
- select HAVE_GENERIC_HARDIRQS
select GENERIC_ATOMIC64
select GENERIC_IRQ_PROBE
- select USE_GENERIC_SMP_HELPERS if SMP
+ select GENERIC_IRQ_SHOW
select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
select GENERIC_SMP_IDLE_THREAD
select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
@@ -318,6 +317,14 @@ config BF53x
depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
default y
+config GPIO_ADI
+ def_bool y
+ depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
+
+config PINCTRL
+ def_bool y
+ depends on BF54x || BF60x
+
config MEM_MT48LC64M4A2FB_7E
bool
depends on (BFIN533_STAMP)
@@ -861,14 +868,6 @@ config SYS_BFIN_SPINLOCK_L1
If enabled, sys_bfin_spinlock function is linked
into L1 instruction memory. (less latency)
-config IP_CHECKSUM_L1
- bool "Locate IP Checksum function in L1 Memory"
- default n
- depends on !SMP
- help
- If enabled, the IP Checksum function is linked
- into L1 instruction memory. (less latency)
-
config CACHELINE_ALIGNED_L1
bool "Locate cacheline_aligned data to L1 Data Memory"
default y if !BF54x
@@ -1430,7 +1429,6 @@ source "drivers/cpufreq/Kconfig"
config BFIN_CPU_FREQ
bool
depends on CPU_FREQ
- select CPU_FREQ_TABLE
default y
config CPU_VOLTAGE