diff options
Diffstat (limited to 'arch/arm/plat-samsung')
73 files changed, 784 insertions, 3934 deletions
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index a9d52167e16..301b892d97d 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -6,61 +6,44 @@ config PLAT_SAMSUNG bool - depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P + depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P || ARCH_EXYNOS default y select GENERIC_IRQ_CHIP - select NO_IOPORT + select NO_IOPORT_MAP help Base platform code for all Samsung SoC based systems config PLAT_S5P bool - depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) + depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) default y select ARCH_REQUIRE_GPIOLIB - select ARM_GIC if ARCH_EXYNOS - select ARM_VIC if !ARCH_EXYNOS - select GIC_NON_BANKED if ARCH_EXYNOS4 - select NO_IOPORT + select ARM_VIC + select NO_IOPORT_MAP select PLAT_SAMSUNG select S3C_GPIO_TRACK select S5P_GPIO_DRVSTR - select SAMSUNG_CLKSRC - select SAMSUNG_GPIOLIB_4BIT - select SAMSUNG_IRQ_VIC_TIMER + select SAMSUNG_CLKSRC if !COMMON_CLK help Base platform code for Samsung's S5P series SoC. +config SAMSUNG_PM + bool + depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || S5P_PM) + default y + help + Base platform power management code for samsung code + if PLAT_SAMSUNG +menu "Samsung Common options" # boot configurations comment "Boot options" -config S3C_BOOT_WATCHDOG - bool "S3C Initialisation watchdog" - depends on S3C2410_WATCHDOG - help - Say y to enable the watchdog during the kernel decompression - stage. If the kernel fails to uncompress, then the watchdog - will trigger a reset and the system should restart. - -config S3C_BOOT_ERROR_RESET - bool "S3C Reboot on decompression error" - help - Say y here to use the watchdog to reset the system if the - kernel decompressor detects an error during decompression. - -config S3C_BOOT_UART_FORCE_FIFO - bool "Force UART FIFO on during boot process" - default y - help - Say Y here to force the UART FIFOs on during the kernel - uncompressor - - config S3C_LOWLEVEL_UART_PORT int "S3C UART to use for low-level messages" + depends on ARCH_S3C64XX default 0 help Choice of which UART port to use for the low-level messages, @@ -68,13 +51,19 @@ config S3C_LOWLEVEL_UART_PORT this configuration should be between zero and two. The port must have been initialised by the boot-loader before use. -# timer options - -config S5P_HRT - bool - select SAMSUNG_DEV_PWM +config SAMSUNG_ATAGS + def_bool n + depends on !ARCH_MULTIPLATFORM + depends on ATAGS help - Use the High Resolution timer support + This option enables ATAGS based boot support code for + Samsung platforms, including static platform devices, legacy + clock, timer and interrupt initialization, etc. + + Platforms that support only DT based boot need not to select + this option. + +if SAMSUNG_ATAGS # clock options @@ -89,21 +78,16 @@ config SAMSUNG_CLKSRC used by newer systems such as the S3C64XX. config S5P_CLOCK - def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) + def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) help Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs # options for IRQ support -config SAMSUNG_IRQ_VIC_TIMER - bool - help - Internal configuration to build the VIC timer interrupt code. - config S5P_IRQ - def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) + def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) help - Support common interrup part for ARCH_S5P and ARCH_EXYNOS SoCs + Support common interrupt part for ARCH_S5P SoCs config S5P_EXT_INT bool @@ -118,19 +102,6 @@ config S5P_GPIO_INT # options for gpio configuration support -config SAMSUNG_GPIOLIB_4BIT - bool - help - GPIOlib file contains the 4 bit modification functions for gpio - configuration. GPIOlib shall be compiled only for S3C64XX and S5P - series of processors. - -config S3C_GPIO_CFG_S3C64XX - bool - help - Internal configuration to enable S3C64XX style GPIO configuration - functions. - config S5P_GPIO_DRVSTR bool help @@ -381,11 +352,6 @@ config S5P_DEV_JPEG help Compile in platform device definitions for JPEG codec -config S5P_DEV_MFC - bool - help - Compile in setup memory (init) code for MFC - config S5P_DEV_ONENAND bool help @@ -396,11 +362,6 @@ config S5P_DEV_TV help Compile in platform device definition for TV interface -config S5P_DEV_USB_EHCI - bool - help - Compile in platform device definition for USB EHCI - config S3C24XX_PWM bool "PWM device support" select PWM @@ -409,11 +370,6 @@ config S3C24XX_PWM Support for exporting the PWM timer blocks via the pwm device system -config S5P_SETUP_MIPIPHY - bool - help - Compile in common setup code for MIPI-CSIS and MIPI-DSIM devices - config S3C_SETUP_CAMIF bool help @@ -426,21 +382,39 @@ config S3C_DMA help Internal configuration for S3C DMA core -config SAMSUNG_DMADEV +config S5P_IRQ_PM + bool + default y if S5P_PM + help + Legacy IRQ power management for S5P platforms + +config SAMSUNG_PM_GPIO bool - select ARM_AMBA + default y if GPIO_SAMSUNG && PM + help + Include legacy GPIO power management code for platforms not using + pinctrl-samsung driver. + +config SAMSUNG_DMADEV + bool "Use legacy Samsung DMA abstraction" + depends on CPU_S5PV210 || CPU_S5PC100 || ARCH_S5P64X0 || ARCH_S3C64XX select DMADEVICES - select PL330_DMA if (ARCH_EXYNOS5 || ARCH_EXYNOS4 || CPU_S5PV210 || CPU_S5PC100 || \ - CPU_S5P6450 || CPU_S5P6440) + default y help Use DMA device engine for PL330 DMAC. +endif + +config S5P_DEV_MFC + bool + help + Compile in setup memory (init) code for MFC + comment "Power management" config SAMSUNG_PM_DEBUG bool "S3C2410 PM Suspend debug" - depends on PM - select DEBUG_LL + depends on PM && DEBUG_KERNEL && DEBUG_S3C_UART help Say Y here if you want verbose debugging from the PM Suspend and Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> @@ -457,7 +431,8 @@ config S3C_PM_DEBUG_LED_SMDK config SAMSUNG_PM_CHECK bool "S3C2410 PM Suspend Memory CRC" - depends on PM && CRC32 + depends on PM + select CRC32 help Enable the PM code's memory area checksum over sleep. This option will generate CRCs of all blocks of memory, and store them before @@ -489,6 +464,12 @@ config SAMSUNG_WAKEMASK and above. This code allows a set of interrupt to wakeup-mask mappings. See <plat/wakeup-mask.h> +config SAMSUNG_WDT_RESET + bool + help + Compile support for system restart by triggering watchdog reset. + Used on SoCs that do not provide dedicated reset control. + config S5P_PM bool help @@ -509,4 +490,5 @@ config DEBUG_S3C_UART default "2" if DEBUG_S3C_UART2 default "3" if DEBUG_S3C_UART3 +endmenu endif diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 3a7c64d1814..5e5beaa9ae1 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -4,6 +4,9 @@ # # Licensed under GPLv2 +ccflags-$(CONFIG_ARCH_MULTI_V7) += -I$(srctree)/$(src)/include +ccflags-$(CONFIG_ARCH_EXYNOS) += -I$(srctree)/arch/arm/mach-exynos/include + obj-y := obj-m := obj-n := dummy.o @@ -12,16 +15,12 @@ obj- := # Objects we always build independent of SoC choice obj-y += init.o cpu.o -obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o -obj-$(CONFIG_S5P_HRT) += s5p-time.o obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o -obj-$(CONFIG_SAMSUNG_CLOCK) += pwm-clock.o obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o -obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o obj-$(CONFIG_S5P_IRQ) += s5p-irq.o obj-$(CONFIG_S5P_EXT_INT) += s5p-irq-eint.o obj-$(CONFIG_S5P_GPIO_INT) += s5p-irq-gpioint.o @@ -32,17 +31,16 @@ obj-$(CONFIG_S3C_ADC) += adc.o # devices -obj-y += platformdata.o +obj-$(CONFIG_SAMSUNG_ATAGS) += platformdata.o -obj-y += devs.o -obj-y += dev-uart.o +obj-$(CONFIG_SAMSUNG_ATAGS) += devs.o +obj-$(CONFIG_SAMSUNG_ATAGS) += dev-uart.o obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o obj-$(CONFIG_S5P_DEV_UART) += s5p-dev-uart.o obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o obj-$(CONFIG_S3C_SETUP_CAMIF) += setup-camif.o -obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o # DMA support @@ -52,11 +50,15 @@ obj-$(CONFIG_SAMSUNG_DMADEV) += dma-ops.o # PM support -obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_PM) += pm-gpio.o +obj-$(CONFIG_PM_SLEEP) += pm-common.o +obj-$(CONFIG_SAMSUNG_PM) += pm.o +obj-$(CONFIG_SAMSUNG_PM_GPIO) += pm-gpio.o obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o +obj-$(CONFIG_SAMSUNG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o +obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o -obj-$(CONFIG_S5P_PM) += s5p-pm.o s5p-irq-pm.o +obj-$(CONFIG_S5P_PM) += s5p-pm.o +obj-$(CONFIG_S5P_IRQ_PM) += s5p-irq-pm.o obj-$(CONFIG_S5P_SLEEP) += s5p-sleep.o diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index ca07cb1b155..79690f2f6d3 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c @@ -381,11 +381,6 @@ static int s3c_adc_probe(struct platform_device *pdev) } regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!regs) { - dev_err(dev, "failed to find registers\n"); - return -ENXIO; - } - adc->regs = devm_ioremap_resource(dev, regs); if (IS_ERR(adc->regs)) return PTR_ERR(adc->regs); diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c index 47c9fad43f0..d103ac1a52a 100644 --- a/arch/arm/plat-samsung/clock.c +++ b/arch/arm/plat-samsung/clock.c @@ -43,7 +43,6 @@ #include <linux/debugfs.h> #endif -#include <mach/hardware.h> #include <asm/irq.h> #include <plat/cpu-freq.h> @@ -52,7 +51,7 @@ #include <plat/cpu.h> #include <linux/serial_core.h> -#include <plat/regs-serial.h> /* for s3c24xx_uart_devs */ +#include <linux/serial_s3c.h> /* for s3c24xx_uart_devs */ /* clock information */ diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/plat-samsung/cpu.c index 46b426e8aff..364963a0a34 100644 --- a/arch/arm/plat-samsung/cpu.c +++ b/arch/arm/plat-samsung/cpu.c @@ -28,13 +28,6 @@ unsigned int samsung_rev(void) } EXPORT_SYMBOL(samsung_rev); -void __init s3c24xx_init_cpu(void) -{ - /* nothing here yet */ - - samsung_cpu_rev = 0; -} - void __init s3c64xx_init_cpu(void) { samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0x118); diff --git a/arch/arm/plat-samsung/dev-backlight.c b/arch/arm/plat-samsung/dev-backlight.c index 5f197dcaf10..2157c5b539e 100644 --- a/arch/arm/plat-samsung/dev-backlight.c +++ b/arch/arm/plat-samsung/dev-backlight.c @@ -20,13 +20,18 @@ #include <plat/gpio-cfg.h> #include <plat/backlight.h> +struct samsung_bl_drvdata { + struct platform_pwm_backlight_data plat_data; + struct samsung_bl_gpio_info *gpio_info; +}; + static int samsung_bl_init(struct device *dev) { int ret = 0; - struct platform_device *timer_dev = - container_of(dev->parent, struct platform_device, dev); - struct samsung_bl_gpio_info *bl_gpio_info = - timer_dev->dev.platform_data; + struct platform_pwm_backlight_data *pdata = dev->platform_data; + struct samsung_bl_drvdata *drvdata = container_of(pdata, + struct samsung_bl_drvdata, plat_data); + struct samsung_bl_gpio_info *bl_gpio_info = drvdata->gpio_info; ret = gpio_request(bl_gpio_info->no, "Backlight"); if (ret) { @@ -42,10 +47,10 @@ static int samsung_bl_init(struct device *dev) static void samsung_bl_exit(struct device *dev) { - struct platform_device *timer_dev = - container_of(dev->parent, struct platform_device, dev); - struct samsung_bl_gpio_info *bl_gpio_info = - timer_dev->dev.platform_data; + struct platform_pwm_backlight_data *pdata = dev->platform_data; + struct samsung_bl_drvdata *drvdata = container_of(pdata, + struct samsung_bl_drvdata, plat_data); + struct samsung_bl_gpio_info *bl_gpio_info = drvdata->gpio_info; s3c_gpio_cfgpin(bl_gpio_info->no, S3C_GPIO_OUTPUT); gpio_free(bl_gpio_info->no); @@ -60,12 +65,15 @@ static void samsung_bl_exit(struct device *dev) * for their specific boards */ -static struct platform_pwm_backlight_data samsung_dfl_bl_data __initdata = { - .max_brightness = 255, - .dft_brightness = 255, - .pwm_period_ns = 78770, - .init = samsung_bl_init, - .exit = samsung_bl_exit, +static struct samsung_bl_drvdata samsung_dfl_bl_data __initdata = { + .plat_data = { + .max_brightness = 255, + .dft_brightness = 255, + .pwm_period_ns = 78770, + .enable_gpio = -1, + .init = samsung_bl_init, + .exit = samsung_bl_exit, + }, }; static struct platform_device samsung_dfl_bl_device __initdata = { @@ -82,6 +90,7 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, { int ret = 0; struct platform_device *samsung_bl_device; + struct samsung_bl_drvdata *samsung_bl_drvdata; struct platform_pwm_backlight_data *samsung_bl_data; samsung_bl_device = kmemdup(&samsung_dfl_bl_device, @@ -91,17 +100,19 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, return; } - samsung_bl_data = s3c_set_platdata(&samsung_dfl_bl_data, - sizeof(struct platform_pwm_backlight_data), samsung_bl_device); - if (!samsung_bl_data) { + samsung_bl_drvdata = kmemdup(&samsung_dfl_bl_data, + sizeof(samsung_dfl_bl_data), GFP_KERNEL); + if (!samsung_bl_drvdata) { printk(KERN_ERR "%s: no memory for platform dev\n", __func__); goto err_data; } + samsung_bl_device->dev.platform_data = &samsung_bl_drvdata->plat_data; + samsung_bl_drvdata->gpio_info = gpio_info; + samsung_bl_data = &samsung_bl_drvdata->plat_data; /* Copy board specific data provided by user */ samsung_bl_data->pwm_id = bl_data->pwm_id; - samsung_bl_device->dev.parent = - &s3c_device_timer[samsung_bl_data->pwm_id].dev; + samsung_bl_device->dev.parent = &samsung_device_pwm.dev; if (bl_data->max_brightness) samsung_bl_data->max_brightness = bl_data->max_brightness; @@ -111,6 +122,8 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, samsung_bl_data->lth_brightness = bl_data->lth_brightness; if (bl_data->pwm_period_ns) samsung_bl_data->pwm_period_ns = bl_data->pwm_period_ns; + if (bl_data->enable_gpio >= 0) + samsung_bl_data->enable_gpio = bl_data->enable_gpio; if (bl_data->init) samsung_bl_data->init = bl_data->init; if (bl_data->notify) @@ -122,17 +135,6 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, if (bl_data->check_fb) samsung_bl_data->check_fb = bl_data->check_fb; - /* Keep the GPIO info for future use */ - s3c_device_timer[samsung_bl_data->pwm_id].dev.platform_data = gpio_info; - - /* Register the specific PWM timer dev for Backlight control */ - ret = platform_device_register( - &s3c_device_timer[samsung_bl_data->pwm_id]); - if (ret) { - printk(KERN_ERR "failed to register pwm timer for backlight: %d\n", ret); - goto err_plat_reg1; - } - /* Register the Backlight dev */ ret = platform_device_register(samsung_bl_device); if (ret) { @@ -143,8 +145,6 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, return; err_plat_reg2: - platform_device_unregister(&s3c_device_timer[samsung_bl_data->pwm_id]); -err_plat_reg1: kfree(samsung_bl_data); err_data: kfree(samsung_bl_device); diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 51afedda9ab..ead4f1c9405 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -10,6 +10,7 @@ * published by the Free Software Foundation. */ +#include <linux/amba/pl330.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/interrupt.h> @@ -17,6 +18,7 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/slab.h> @@ -29,8 +31,10 @@ #include <linux/mtd/partitions.h> #include <linux/mmc/host.h> #include <linux/ioport.h> +#include <linux/sizes.h> #include <linux/platform_data/s3c-hsudc.h> #include <linux/platform_data/s3c-hsotg.h> +#include <linux/platform_data/dma-s3c24xx.h> #include <media/s5p_hdmi.h> @@ -39,7 +43,6 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> #include <mach/dma.h> #include <mach/irqs.h> #include <mach/map.h> @@ -48,7 +51,6 @@ #include <plat/devs.h> #include <plat/adc.h> #include <linux/platform_data/ata-samsung_cf.h> -#include <linux/platform_data/usb-ehci-s5p.h> #include <plat/fb.h> #include <plat/fb-s3c2410.h> #include <plat/hdmi.h> @@ -57,13 +59,12 @@ #include <plat/keypad.h> #include <linux/platform_data/mmc-s3cmci.h> #include <linux/platform_data/mtd-nand-s3c2410.h> +#include <plat/pwm-core.h> #include <plat/sdhci.h> #include <linux/platform_data/touchscreen-s3c2410.h> #include <linux/platform_data/usb-s3c2410_udc.h> #include <linux/platform_data/usb-ohci-s3c2410.h> #include <plat/usb-phy.h> -#include <plat/regs-iic.h> -#include <plat/regs-serial.h> #include <plat/regs-spi.h> #include <linux/platform_data/spi-s3c64xx.h> @@ -146,14 +147,20 @@ struct platform_device s3c_device_camif = { /* ASOC DMA */ +#ifdef CONFIG_PLAT_S5P +static struct resource samsung_asoc_idma_resource = DEFINE_RES_IRQ(IRQ_I2S0); + struct platform_device samsung_asoc_idma = { .name = "samsung-idma", .id = -1, + .num_resources = 1, + .resource = &samsung_asoc_idma_resource, .dev = { .dma_mask = &samsung_device_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), } }; +#endif /* FB */ @@ -305,9 +312,9 @@ struct platform_device s5p_device_jpeg = { #ifdef CONFIG_S5P_DEV_FIMD0 static struct resource s5p_fimd0_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K), - [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC), - [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO), - [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM), + [1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, "vsync"), + [2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, "fifo"), + [3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, "lcd_sys"), }; struct platform_device s5p_device_fimd0 = { @@ -737,10 +744,7 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd) if (!pd) { pd = &default_i2c_data; - if (soc_is_exynos4210() || - soc_is_exynos4212() || soc_is_exynos4412()) - pd->bus_num = 8; - else if (soc_is_s5pv210()) + if (soc_is_s5pv210()) pd->bus_num = 3; else pd->bus_num = 0; @@ -757,10 +761,7 @@ void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info, { struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata; - if (soc_is_exynos4210() || - soc_is_exynos4212() || soc_is_exynos4412()) - pd->hdmiphy_bus = 8; - else if (soc_is_s5pv210()) + if (soc_is_s5pv210()) pd->hdmiphy_bus = 3; else pd->hdmiphy_bus = 0; @@ -878,51 +879,6 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) } #endif /* CONFIG_PLAT_S3C24XX */ -/* MFC */ - -#ifdef CONFIG_S5P_DEV_MFC -static struct resource s5p_mfc_resource[] = { - [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K), - [1] = DEFINE_RES_IRQ(IRQ_MFC), -}; - -struct platform_device s5p_device_mfc = { - .name = "s5p-mfc", - .id = -1, - .num_resources = ARRAY_SIZE(s5p_mfc_resource), - .resource = s5p_mfc_resource, -}; - -/* - * MFC hardware has 2 memory interfaces which are modelled as two separate - * platform devices to let dma-mapping distinguish between them. - * - * MFC parent device (s5p_device_mfc) must be registered before memory - * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r). - */ - -struct platform_device s5p_device_mfc_l = { - .name = "s5p-mfc-l", - .id = -1, - .dev = { - .parent = &s5p_device_mfc.dev, - .dma_mask = &samsung_device_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -struct platform_device s5p_device_mfc_r = { - .name = "s5p-mfc-r", - .id = -1, - .dev = { - .parent = &s5p_device_mfc.dev, - .dma_mask = &samsung_device_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -#endif /* CONFIG_S5P_DEV_MFC */ - /* MIPI CSIS */ #ifdef CONFIG_S5P_DEV_CSIS0 @@ -1113,7 +1069,7 @@ struct platform_device s5p_device_onenand = { /* PMU */ -#ifdef CONFIG_PLAT_S5P +#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS) static struct resource s5p_pmu_resource[] = { DEFINE_RES_IRQ(IRQ_PMU) }; @@ -1136,36 +1092,21 @@ arch_initcall(s5p_pmu_init); /* PWM Timer */ #ifdef CONFIG_SAMSUNG_DEV_PWM +static struct resource samsung_pwm_resource[] = { + DEFINE_RES_MEM(SAMSUNG_PA_TIMER, SZ_4K), +}; -#define TIMER_RESOURCE_SIZE (1) - -#define TIMER_RESOURCE(_tmr, _irq) \ - (struct resource [TIMER_RESOURCE_SIZE]) { \ - [0] = { \ - .start = _irq, \ - .end = _irq, \ - .flags = IORESOURCE_IRQ \ - } \ - } - -#define DEFINE_S3C_TIMER(_tmr_no, _irq) \ - .name = "s3c24xx-pwm", \ - .id = _tmr_no, \ - .num_resources = TIMER_RESOURCE_SIZE, \ - .resource = TIMER_RESOURCE(_tmr_no, _irq), \ - -/* - * since we already have an static mapping for the timer, - * we do not bother setting any IO resource for the base. - */ - -struct platform_device s3c_device_timer[] = { - [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) }, - [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) }, - [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) }, - [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) }, - [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) }, +struct platform_device samsung_device_pwm = { + .name = "samsung-pwm", + .id = -1, + .num_resources = ARRAY_SIZE(samsung_pwm_resource), + .resource = samsung_pwm_resource, }; + +void __init samsung_pwm_set_platdata(struct samsung_pwm_variant *pd) +{ + samsung_device_pwm.dev.platform_data = pd; +} #endif /* CONFIG_SAMSUNG_DEV_PWM */ /* RTC */ @@ -1412,39 +1353,6 @@ void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd) } #endif /* CONFIG_PLAT_S3C24XX */ -/* USB EHCI Host Controller */ - -#ifdef CONFIG_S5P_DEV_USB_EHCI -static struct resource s5p_ehci_resource[] = { - [0] = DEFINE_RES_MEM(S5P_PA_EHCI, SZ_256), - [1] = DEFINE_RES_IRQ(IRQ_USB_HOST), -}; - -struct platform_device s5p_device_ehci = { - .name = "s5p-ehci", - .id = -1, - .num_resources = ARRAY_SIZE(s5p_ehci_resource), - .resource = s5p_ehci_resource, - .dev = { - .dma_mask = &samsung_device_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - } -}; - -void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd) -{ - struct s5p_ehci_platdata *npd; - - npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata), - &s5p_device_ehci); - - if (!npd->phy_init) - npd->phy_init = s5p_usb_phy_init; - if (!npd->phy_exit) - npd->phy_exit = s5p_usb_phy_exit; -} -#endif /* CONFIG_S5P_DEV_USB_EHCI */ - /* USB HSOTG */ #ifdef CONFIG_S3C_DEV_USB_HSOTG @@ -1552,6 +1460,13 @@ void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, pd.num_cs = num_cs; pd.src_clk_nr = src_clk_nr; pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio; +#if defined(CONFIG_PL330_DMA) + pd.filter = pl330_filter; +#elif defined(CONFIG_S3C64XX_PL080) + pd.filter = pl08x_filter_id; +#elif defined(CONFIG_S3C24XX_DMAC) + pd.filter = s3c24xx_dma_filter; +#endif s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0); } @@ -1590,6 +1505,11 @@ void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, pd.num_cs = num_cs; pd.src_clk_nr = src_clk_nr; pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio; +#if defined(CONFIG_PL330_DMA) + pd.filter = pl330_filter; +#elif defined(CONFIG_S3C64XX_PL080) + pd.filter = pl08x_filter_id; +#endif s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1); } @@ -1628,6 +1548,11 @@ void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, pd.num_cs = num_cs; pd.src_clk_nr = src_clk_nr; pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio; +#if defined(CONFIG_PL330_DMA) + pd.filter = pl330_filter; +#elif defined(CONFIG_S3C64XX_PL080) + pd.filter = pl08x_filter_id; +#endif s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2); } diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c index 71d58ddea9c..886326ee6f6 100644 --- a/arch/arm/plat-samsung/dma-ops.c +++ b/arch/arm/plat-samsung/dma-ops.c @@ -18,28 +18,26 @@ #include <mach/dma.h> +#if defined(CONFIG_PL330_DMA) +#define dma_filter pl330_filter +#elif defined(CONFIG_S3C64XX_PL080) +#define dma_filter pl08x_filter_id +#endif + static unsigned samsung_dmadev_request(enum dma_ch dma_ch, struct samsung_dma_req *param, struct device *dev, char *ch_name) { dma_cap_mask_t mask; - void *filter_param; dma_cap_zero(mask); dma_cap_set(param->cap, mask); - /* - * If a dma channel property of a device node from device tree is - * specified, use that as the fliter parameter. - */ - filter_param = (dma_ch == DMACH_DT_PROP) ? - (void *)param->dt_dmach_prop : (void *)dma_ch; - if (dev->of_node) return (unsigned)dma_request_slave_channel(dev, ch_name); else - return (unsigned)dma_request_channel(mask, pl330_filter, - filter_param); + return (unsigned)dma_request_channel(mask, dma_filter, + (void *)dma_ch); } static int samsung_dmadev_release(unsigned ch, void *param) diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index a62753dc15b..63239f40980 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h @@ -83,6 +83,11 @@ extern struct clk clk_ext; extern struct clksrc_clk clk_epllref; extern struct clksrc_clk clk_esysclk; +/* S3C24XX UART clocks */ +extern struct clk s3c24xx_clk_uart0; +extern struct clk s3c24xx_clk_uart1; +extern struct clk s3c24xx_clk_uart2; + /* S3C64XX specific clocks */ extern struct clk clk_h2; extern struct clk clk_27m; @@ -140,10 +145,6 @@ extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable); extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable); -/* Init for pwm clock code */ - -extern void s3c_pwmclk_init(void); - /* Global watchdog clock used by arch_wtd_reset() callback */ extern struct clk *s3c2410_wdtclk; diff --git a/arch/arm/plat-samsung/include/plat/common-smdk.h b/arch/arm/plat-samsung/include/plat/common-smdk.h deleted file mode 100644 index ba028f1ed30..00000000000 --- a/arch/arm/plat-samsung/include/plat/common-smdk.h +++ /dev/null @@ -1,15 +0,0 @@ -/* linux/arch/arm/plat-samsung/include/plat/common-smdk.h - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Common code for SMDK2410 and SMDK2440 boards - * - * http://www.fluff.org/ben/smdk2440/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -extern void smdk_machine_init(void); diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h index 95509d8eb14..72d4178ad23 100644 --- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h +++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h @@ -119,6 +119,7 @@ struct s3c_plltab { struct s3c_cpufreq_config { struct s3c_freq freq; struct s3c_freq max; + struct clk *mpll; struct cpufreq_frequency_table pll; struct s3c_clkdivs divs; struct s3c_cpufreq_info *info; /* for core, not drivers */ @@ -202,7 +203,7 @@ extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void); extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void); -#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS +#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS #define s3c_cpufreq_debugfs_call(x) x #else #define s3c_cpufreq_debugfs_call(x) NULL @@ -259,17 +260,17 @@ extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg, #define s3c2412_iotiming_set NULL #endif /* CONFIG_S3C2412_IOTIMING */ -#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG +#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG #define s3c_freq_dbg(x...) printk(KERN_INFO x) #else #define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0) -#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */ +#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG */ -#ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG +#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG #define s3c_freq_iodbg(x...) printk(KERN_INFO x) #else #define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0) -#endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */ +#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG */ static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table, int index, size_t table_size, @@ -285,7 +286,7 @@ static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table, s3c_freq_dbg("%s: { %d = %u kHz }\n", __func__, index, freq); - table[index].index = index; + table[index].driver_data = index; table[index].frequency = freq; } diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq.h b/arch/arm/plat-samsung/include/plat/cpu-freq.h index 80c4a809c72..85517ab962a 100644 --- a/arch/arm/plat-samsung/include/plat/cpu-freq.h +++ b/arch/arm/plat-samsung/include/plat/cpu-freq.h @@ -126,7 +126,7 @@ struct s3c_cpufreq_board { }; /* Things depending on frequency scaling. */ -#ifdef CONFIG_CPU_FREQ_S3C +#ifdef CONFIG_ARM_S3C_CPUFREQ #define __init_or_cpufreq #else #define __init_or_cpufreq __init @@ -134,7 +134,7 @@ struct s3c_cpufreq_board { /* Board functions */ -#ifdef CONFIG_CPU_FREQ_S3C +#ifdef CONFIG_ARM_S3C_CPUFREQ extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board); #else @@ -142,4 +142,4 @@ static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) { return 0; } -#endif /* CONFIG_CPU_FREQ_S3C */ +#endif /* CONFIG_ARM_S3C_CPUFREQ */ diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 37703ef6dfc..5a237db9f9e 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -20,9 +20,15 @@ extern unsigned long samsung_cpu_id; +#define S3C2410_CPU_ID 0x32410000 +#define S3C2410_CPU_MASK 0xFFFFFFFF + #define S3C24XX_CPU_ID 0x32400000 #define S3C24XX_CPU_MASK 0xFFF00000 +#define S3C2412_CPU_ID 0x32412000 +#define S3C2412_CPU_MASK 0xFFFFF000 + #define S3C6400_CPU_ID 0x36400000 #define S3C6410_CPU_ID 0x36410000 #define S3C64XX_CPU_MASK 0xFFFFF000 @@ -37,46 +43,46 @@ extern unsigned long samsung_cpu_id; #define S5PV210_CPU_ID 0x43110000 #define S5PV210_CPU_MASK 0xFFFFF000 -#define EXYNOS4210_CPU_ID 0x43210000 -#define EXYNOS4212_CPU_ID 0x43220000 -#define EXYNOS4412_CPU_ID 0xE4412200 -#define EXYNOS4_CPU_MASK 0xFFFE0000 - -#define EXYNOS5250_SOC_ID 0x43520000 -#define EXYNOS5440_SOC_ID 0xE5440000 -#define EXYNOS5_SOC_MASK 0xFFFFF000 - #define IS_SAMSUNG_CPU(name, id, mask) \ static inline int is_samsung_##name(void) \ { \ return ((samsung_cpu_id & mask) == (id & mask)); \ } +IS_SAMSUNG_CPU(s3c2410, S3C2410_CPU_ID, S3C2410_CPU_MASK) IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK) +IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK) IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK) IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK) IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK) IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK) IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK) IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK) -IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) -IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) -IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) -IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) -IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \ defined(CONFIG_CPU_S3C2442) || defined(CONFIG_CPU_S3C244X) || \ defined(CONFIG_CPU_S3C2443) # define soc_is_s3c24xx() is_samsung_s3c24xx() +# define soc_is_s3c2410() is_samsung_s3c2410() #else # define soc_is_s3c24xx() 0 +# define soc_is_s3c2410() 0 +#endif + +#if defined(CONFIG_CPU_S3C2412) +# define soc_is_s3c2412() is_samsung_s3c2412() +#else +# define soc_is_s3c2412() 0 #endif #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) +# define soc_is_s3c6400() is_samsung_s3c6400() +# define soc_is_s3c6410() is_samsung_s3c6410() # define soc_is_s3c64xx() (is_samsung_s3c6400() || is_samsung_s3c6410()) #else +# define soc_is_s3c6400() 0 +# define soc_is_s3c6410() 0 # define soc_is_s3c64xx() 0 #endif @@ -104,40 +110,6 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_s5pv210() 0 #endif -#if defined(CONFIG_CPU_EXYNOS4210) -# define soc_is_exynos4210() is_samsung_exynos4210() -#else -# define soc_is_exynos4210() 0 -#endif - -#if defined(CONFIG_SOC_EXYNOS4212) -# define soc_is_exynos4212() is_samsung_exynos4212() -#else -# define soc_is_exynos4212() 0 -#endif - -#if defined(CONFIG_SOC_EXYNOS4412) -# define soc_is_exynos4412() is_samsung_exynos4412() -#else -# define soc_is_exynos4412() 0 -#endif - -#define EXYNOS4210_REV_0 (0x0) -#define EXYNOS4210_REV_1_0 (0x10) -#define EXYNOS4210_REV_1_1 (0x11) - -#if defined(CONFIG_SOC_EXYNOS5250) -# define soc_is_exynos5250() is_samsung_exynos5250() -#else -# define soc_is_exynos5250() 0 -#endif - -#if defined(CONFIG_SOC_EXYNOS5440) -# define soc_is_exynos5440() is_samsung_exynos5440() -#else -# define soc_is_exynos5440() 0 -#endif - #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } #ifndef KHZ @@ -173,12 +145,10 @@ extern void s3c_init_cpu(unsigned long idcode, /* core initialisation functions */ -extern void s3c24xx_init_irq(void); extern void s5p_init_irq(u32 *vic, u32 num_vic); extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); -extern void s3c24xx_init_cpu(void); extern void s3c64xx_init_cpu(void); extern void s5p_init_cpu(void __iomem *cpuid_addr); @@ -192,10 +162,6 @@ extern void s3c24xx_init_uartdevs(char *name, struct s3c24xx_uart_resources *res, struct s3c2410_uartcfg *cfg, int no); -/* timer for 2410/2440 */ - -extern void s3c24xx_timer_init(void); - extern struct syscore_ops s3c2410_pm_syscore_ops; extern struct syscore_ops s3c2412_pm_syscore_ops; extern struct syscore_ops s3c2416_pm_syscore_ops; @@ -213,7 +179,6 @@ extern struct bus_type s3c2443_subsys; extern struct bus_type s3c6410_subsys; extern struct bus_type s5p64x0_subsys; extern struct bus_type s5pv210_subsys; -extern struct bus_type exynos_subsys; extern void (*s5pc1xx_idle)(void); diff --git a/arch/arm/plat-samsung/include/plat/debug-macro.S b/arch/arm/plat-samsung/include/plat/debug-macro.S deleted file mode 100644 index f3a9cff6d5d..00000000000 --- a/arch/arm/plat-samsung/include/plat/debug-macro.S +++ /dev/null @@ -1,87 +0,0 @@ -/* arch/arm/plat-samsung/include/plat/debug-macro.S - * - * Copyright 2005, 2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <plat/regs-serial.h> - -/* The S5PV210/S5PC110 implementations are as belows. */ - - .macro fifo_level_s5pv210 rd, rx - ldr \rd, [\rx, # S3C2410_UFSTAT] - and \rd, \rd, #S5PV210_UFSTAT_TXMASK - .endm - - .macro fifo_full_s5pv210 rd, rx - ldr \rd, [\rx, # S3C2410_UFSTAT] - tst \rd, #S5PV210_UFSTAT_TXFULL - .endm - -/* The S3C2440 implementations are used by default as they are the - * most widely re-used */ - - .macro fifo_level_s3c2440 rd, rx - ldr \rd, [\rx, # S3C2410_UFSTAT] - and \rd, \rd, #S3C2440_UFSTAT_TXMASK - .endm - -#ifndef fifo_level -#define fifo_level fifo_level_s3c2440 -#endif - - .macro fifo_full_s3c2440 rd, rx - ldr \rd, [\rx, # S3C2410_UFSTAT] - tst \rd, #S3C2440_UFSTAT_TXFULL - .endm - -#ifndef fifo_full -#define fifo_full fifo_full_s3c2440 -#endif - - .macro senduart,rd,rx - strb \rd, [\rx, # S3C2410_UTXH] - .endm - - .macro busyuart, rd, rx - ldr \rd, [\rx, # S3C2410_UFCON] - tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? - beq 1001f @ - @ FIFO enabled... -1003: - fifo_full \rd, \rx - bne 1003b - b 1002f - -1001: - @ busy waiting for non fifo - ldr \rd, [\rx, # S3C2410_UTRSTAT] - tst \rd, #S3C2410_UTRSTAT_TXFE - beq 1001b - -1002: @ exit busyuart - .endm - - .macro waituart,rd,rx - ldr \rd, [\rx, # S3C2410_UFCON] - tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? - beq 1001f @ - @ FIFO enabled... -1003: - fifo_level \rd, \rx - teq \rd, #0 - bne 1003b - b 1002f -1001: - @ idle waiting for non fifo - ldr \rd, [\rx, # S3C2410_UTRSTAT] - tst \rd, #S3C2410_UTRSTAT_TXFE - beq 1001b - -1002: @ exit busyuart - .endm diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index 87d501ff332..eece188ed18 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -75,7 +75,6 @@ extern struct platform_device s3c_device_usb_hsotg; extern struct platform_device s3c_device_usb_hsudc; extern struct platform_device s3c_device_wdt; -extern struct platform_device s5p_device_ehci; extern struct platform_device s5p_device_fimc0; extern struct platform_device s5p_device_fimc1; extern struct platform_device s5p_device_fimc2; @@ -134,6 +133,7 @@ extern struct platform_device exynos4_device_spdif; extern struct platform_device samsung_asoc_idma; extern struct platform_device samsung_device_keypad; +extern struct platform_device samsung_device_pwm; /* s3c2440 specific devices */ diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h index 114178268b7..ce6d7634b6c 100644 --- a/arch/arm/plat-samsung/include/plat/dma-ops.h +++ b/arch/arm/plat-samsung/include/plat/dma-ops.h @@ -18,7 +18,6 @@ struct samsung_dma_req { enum dma_transaction_type cap; - struct property *dt_dmach_prop; struct s3c2410_dma_client *client; }; diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h index d384a8016b4..abe07fae71d 100644 --- a/arch/arm/plat-samsung/include/plat/dma-pl330.h +++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h @@ -21,7 +21,6 @@ * use these just as IDs. */ enum dma_ch { - DMACH_DT_PROP = -1, DMACH_UART0_RX = 0, DMACH_UART0_TX, DMACH_UART1_RX, diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h index d01576318b2..bd3a6db14cb 100644 --- a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h +++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h @@ -28,7 +28,6 @@ struct s3c24xx_dma_map { const char *name; unsigned long channels[S3C_DMA_CHANNELS]; - unsigned long channels_rx[S3C_DMA_CHANNELS]; }; struct s3c24xx_dma_selection { @@ -38,10 +37,6 @@ struct s3c24xx_dma_selection { void (*select)(struct s3c2410_dma_chan *chan, struct s3c24xx_dma_map *map); - - void (*direction)(struct s3c2410_dma_chan *chan, - struct s3c24xx_dma_map *map, - enum dma_data_direction dir); }; extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel); diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h index b885322717a..9ae50727078 100644 --- a/arch/arm/plat-samsung/include/plat/fb.h +++ b/arch/arm/plat-samsung/include/plat/fb.h @@ -15,55 +15,7 @@ #ifndef __PLAT_S3C_FB_H #define __PLAT_S3C_FB_H __FILE__ -/* S3C_FB_MAX_WIN - * Set to the maximum number of windows that any of the supported hardware - * can use. Since the platform data uses this for an array size, having it - * set to the maximum of any version of the hardware can do is safe. - */ -#define S3C_FB_MAX_WIN (5) - -/** - * struct s3c_fb_pd_win - per window setup data - * @xres : The window X size. - * @yres : The window Y size. - * @virtual_x: The virtual X size. - * @virtual_y: The virtual Y size. - */ -struct s3c_fb_pd_win { - unsigned short default_bpp; - unsigned short max_bpp; - unsigned short xres; - unsigned short yres; - unsigned short virtual_x; - unsigned short virtual_y; -}; - -/** - * struct s3c_fb_platdata - S3C driver platform specific information - * @setup_gpio: Setup the external GPIO pins to the right state to transfer - * the data from the display system to the connected display - * device. - * @vidcon0: The base vidcon0 values to control the panel data format. - * @vidcon1: The base vidcon1 values to control the panel data output. - * @vtiming: Video timing when connected to a RGB type panel. - * @win: The setup data for each hardware window, or NULL for unused. - * @display_mode: The LCD output display mode. - * - * The platform data supplies the video driver with all the information - * it requires to work with the display(s) attached to the machine. It - * controls the initial mode, the number of display windows (0 is always - * the base framebuffer) that are initialised etc. - * - */ -struct s3c_fb_platdata { - void (*setup_gpio)(void); - - struct s3c_fb_pd_win *win[S3C_FB_MAX_WIN]; - struct fb_videomode *vtiming; - - u32 vidcon0; - u32 vidcon1; -}; +#include <linux/platform_data/video_s3c.h> /** * s3c_fb_set_platdata() - Setup the FB device with platform data. diff --git a/arch/arm/plat-samsung/include/plat/fiq.h b/arch/arm/plat-samsung/include/plat/fiq.h deleted file mode 100644 index 535d06a3562..00000000000 --- a/arch/arm/plat-samsung/include/plat/fiq.h +++ /dev/null @@ -1,13 +0,0 @@ -/* linux/arch/arm/plat-samsung/include/plat/fiq.h - * - * Copyright (c) 2009 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Header file for S3C24XX CPU FIQ support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -extern int s3c24xx_set_fiq(unsigned int irq, bool on); diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h deleted file mode 100644 index 5b9c42fd32d..00000000000 --- a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h +++ /dev/null @@ -1,13 +0,0 @@ -/* arch/arm/plat-samsung/include/plat/irq-vic-timer.h - * - * Copyright (c) 2010 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Header file for Samsung SoC IRQ VIC timer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -extern void s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq); diff --git a/arch/arm/plat-samsung/include/plat/irq.h b/arch/arm/plat-samsung/include/plat/irq.h deleted file mode 100644 index e21a89bc26c..00000000000 --- a/arch/arm/plat-samsung/include/plat/irq.h +++ /dev/null @@ -1,116 +0,0 @@ -/* linux/arch/arm/plat-samsung/include/plat/irq.h - * - * Copyright (c) 2004-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Header file for S3C24XX CPU IRQ support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/regs-irq.h> -#include <mach/regs-gpio.h> - -#define irqdbf(x...) -#define irqdbf2(x...) - -#define EXTINT_OFF (IRQ_EINT4 - 4) - -/* these are exported for arch/arm/mach-* usage */ -extern struct irq_chip s3c_irq_level_chip; -extern struct irq_chip s3c_irq_chip; - -static inline void s3c_irqsub_mask(unsigned int irqno, - unsigned int parentbit, - int subcheck) -{ - unsigned long mask; - unsigned long submask; - - submask = __raw_readl(S3C2410_INTSUBMSK); - mask = __raw_readl(S3C2410_INTMSK); - - submask |= (1UL << (irqno - IRQ_S3CUART_RX0)); - - /* check to see if we need to mask the parent IRQ */ - - if ((submask & subcheck) == subcheck) - __raw_writel(mask | parentbit, S3C2410_INTMSK); - - /* write back masks */ - __raw_writel(submask, S3C2410_INTSUBMSK); - -} - -static inline void s3c_irqsub_unmask(unsigned int irqno, - unsigned int parentbit) -{ - unsigned long mask; - unsigned long submask; - - submask = __raw_readl(S3C2410_INTSUBMSK); - mask = __raw_readl(S3C2410_INTMSK); - - submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0)); - mask &= ~parentbit; - - /* write back masks */ - __raw_writel(submask, S3C2410_INTSUBMSK); - __raw_writel(mask, S3C2410_INTMSK); -} - - -static inline void s3c_irqsub_maskack(unsigned int irqno, - unsigned int parentmask, - unsigned int group) -{ - unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); - - s3c_irqsub_mask(irqno, parentmask, group); - - __raw_writel(bit, S3C2410_SUBSRCPND); - - /* only ack parent if we've got all the irqs (seems we must - * ack, all and hope that the irq system retriggers ok when - * the interrupt goes off again) - */ - - if (1) { - __raw_writel(parentmask, S3C2410_SRCPND); - __raw_writel(parentmask, S3C2410_INTPND); - } -} - -static inline void s3c_irqsub_ack(unsigned int irqno, - unsigned int parentmask, - unsigned int group) -{ - unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); - - __raw_writel(bit, S3C2410_SUBSRCPND); - - /* only ack parent if we've got all the irqs (seems we must - * ack, all and hope that the irq system retriggers ok when - * the interrupt goes off again) - */ - - if (1) { - __raw_writel(parentmask, S3C2410_SRCPND); - __raw_writel(parentmask, S3C2410_INTPND); - } -} - -/* exported for use in arch/arm/mach-s3c2410 */ - -#ifdef CONFIG_PM -extern int s3c_irq_wake(struct irq_data *data, unsigned int state); -#else -#define s3c_irq_wake NULL -#endif - -extern int s3c_irqext_type(struct irq_data *d, unsigned int type); diff --git a/arch/arm/plat-samsung/include/plat/irqs.h b/arch/arm/plat-samsung/include/plat/irqs.h index df46b776976..039001c0ef0 100644 --- a/arch/arm/plat-samsung/include/plat/irqs.h +++ b/arch/arm/plat-samsung/include/plat/irqs.h @@ -44,15 +44,6 @@ #define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x)) #define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x)) -#define S5P_TIMER_IRQ(x) (IRQ_TIMER_BASE + (x)) - -#define IRQ_TIMER0 S5P_TIMER_IRQ(0) -#define IRQ_TIMER1 S5P_TIMER_IRQ(1) -#define IRQ_TIMER2 S5P_TIMER_IRQ(2) -#define IRQ_TIMER3 S5P_TIMER_IRQ(3) -#define IRQ_TIMER4 S5P_TIMER_IRQ(4) -#define IRQ_TIMER_COUNT (5) - #define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \ : ((x) - 16 + S5P_EINT_BASE2)) diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h index c2d7bdae589..c18678610bc 100644 --- a/arch/arm/plat-samsung/include/plat/map-s5p.h +++ b/arch/arm/plat-samsung/include/plat/map-s5p.h @@ -22,6 +22,7 @@ #define S5P_VA_GPIO3 S3C_ADDR(0x02280000) #define S5P_VA_SYSRAM S3C_ADDR(0x02400000) +#define S5P_VA_SYSRAM_NS S3C_ADDR(0x02410000) #define S5P_VA_DMC0 S3C_ADDR(0x02440000) #define S5P_VA_DMC1 S3C_ADDR(0x02480000) #define S5P_VA_SROMC S3C_ADDR(0x024C0000) diff --git a/arch/arm/plat-samsung/include/plat/mfc.h b/arch/arm/plat-samsung/include/plat/mfc.h index e6d7c42d68b..033654e91e2 100644 --- a/arch/arm/plat-samsung/include/plat/mfc.h +++ b/arch/arm/plat-samsung/include/plat/mfc.h @@ -32,7 +32,4 @@ struct s5p_mfc_dt_meminfo { void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, phys_addr_t lbase, unsigned int lsize); -int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname, - int depth, void *data); - #endif /* __PLAT_SAMSUNG_MFC_H */ diff --git a/arch/arm/plat-samsung/include/plat/pm-common.h b/arch/arm/plat-samsung/include/plat/pm-common.h new file mode 100644 index 00000000000..8705f9e0e28 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/pm-common.h @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Tomasz Figa <t.figa@samsung.com> + * Copyright (c) 2004 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Written by Ben Dooks, <ben@simtec.co.uk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_SAMSUNG_PM_COMMON_H +#define __PLAT_SAMSUNG_PM_COMMON_H __FILE__ + +#include <linux/irq.h> + +/* sleep save info */ + +/** + * struct sleep_save - save information for shared peripherals. + * @reg: Pointer to the register to save. + * @val: Holder for the value saved from reg. + * + * This describes a list of registers which is used by the pm core and + * other subsystem to save and restore register values over suspend. + */ +struct sleep_save { + void __iomem *reg; + unsigned long val; +}; + +#define SAVE_ITEM(x) \ + { .reg = (x) } + +/* helper functions to save/restore lists of registers. */ + +extern void s3c_pm_do_save(struct sleep_save *ptr, int count); +extern void s3c_pm_do_restore(const struct sleep_save *ptr, int count); +extern void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count); + +/* PM debug functions */ + +/** + * struct pm_uart_save - save block for core UART + * @ulcon: Save value for S3C2410_ULCON + * @ucon: Save value for S3C2410_UCON + * @ufcon: Save value for S3C2410_UFCON + * @umcon: Save value for S3C2410_UMCON + * @ubrdiv: Save value for S3C2410_UBRDIV + * + * Save block for UART registers to be held over sleep and restored if they + * are needed (say by debug). +*/ +struct pm_uart_save { + u32 ulcon; + u32 ucon; + u32 ufcon; + u32 umcon; + u32 ubrdiv; + u32 udivslot; +}; + +#ifdef CONFIG_SAMSUNG_PM_DEBUG +/** + * s3c_pm_dbg() - low level debug function for use in suspend/resume. + * @msg: The message to print. + * + * This function is used mainly to debug the resume process before the system + * can rely on printk/console output. It uses the low-level debugging output + * routine printascii() to do its work. + */ +extern void s3c_pm_dbg(const char *msg, ...); + +/** + * s3c_pm_debug_init() - suspend/resume low level debug initialization. + * @base: Virtual base of UART to use for suspend/resume debugging. + * + * This function needs to be called before S3C_PMDBG() can be used, to set up + * UART port base address and configuration. + */ +extern void s3c_pm_debug_init(void); + +#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt) + +extern void s3c_pm_save_uarts(void); +extern void s3c_pm_restore_uarts(void); +#else +#define S3C_PMDBG(fmt...) pr_debug(fmt) +#define s3c_pm_debug_init() do { } while (0) + +static inline void s3c_pm_save_uarts(void) { } +static inline void s3c_pm_restore_uarts(void) { } +#endif + +/* suspend memory checking */ + +#ifdef CONFIG_SAMSUNG_PM_CHECK +extern void s3c_pm_check_prepare(void); +extern void s3c_pm_check_restore(void); +extern void s3c_pm_check_cleanup(void); +extern void s3c_pm_check_store(void); +#else +#define s3c_pm_check_prepare() do { } while (0) +#define s3c_pm_check_restore() do { } while (0) +#define s3c_pm_check_cleanup() do { } while (0) +#define s3c_pm_check_store() do { } while (0) +#endif + +#endif diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index f6fcadeee96..e17d871b934 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -15,11 +15,11 @@ * management */ -#include <linux/irq.h> +#include <plat/pm-common.h> struct device; -#ifdef CONFIG_PM +#ifdef CONFIG_SAMSUNG_PM extern __init int s3c_pm_init(void); extern __init int s3c64xx_pm_init(void); @@ -54,82 +54,18 @@ extern int (*pm_cpu_sleep)(unsigned long); extern unsigned long s3c_pm_flags; -extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */ - /* from sleep.S */ -extern void s3c_cpu_resume(void); - extern int s3c2410_cpu_suspend(unsigned long); -/* sleep save info */ - -/** - * struct sleep_save - save information for shared peripherals. - * @reg: Pointer to the register to save. - * @val: Holder for the value saved from reg. - * - * This describes a list of registers which is used by the pm core and - * other subsystem to save and restore register values over suspend. - */ -struct sleep_save { - void __iomem *reg; - unsigned long val; -}; - -#define SAVE_ITEM(x) \ - { .reg = (x) } - -/** - * struct pm_uart_save - save block for core UART - * @ulcon: Save value for S3C2410_ULCON - * @ucon: Save value for S3C2410_UCON - * @ufcon: Save value for S3C2410_UFCON - * @umcon: Save value for S3C2410_UMCON - * @ubrdiv: Save value for S3C2410_UBRDIV - * - * Save block for UART registers to be held over sleep and restored if they - * are needed (say by debug). -*/ -struct pm_uart_save { - u32 ulcon; - u32 ucon; - u32 ufcon; - u32 umcon; - u32 ubrdiv; - u32 udivslot; -}; - -/* helper functions to save/restore lists of registers. */ - -extern void s3c_pm_do_save(struct sleep_save *ptr, int count); -extern void s3c_pm_do_restore(struct sleep_save *ptr, int count); -extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count); - -#ifdef CONFIG_PM +#ifdef CONFIG_SAMSUNG_PM extern int s3c_irq_wake(struct irq_data *data, unsigned int state); extern int s3c_irqext_wake(struct irq_data *data, unsigned int state); +extern void s3c_cpu_resume(void); #else #define s3c_irq_wake NULL #define s3c_irqext_wake NULL -#endif - -/* PM debug functions */ - -#ifdef CONFIG_SAMSUNG_PM_DEBUG -/** - * s3c_pm_dbg() - low level debug function for use in suspend/resume. - * @msg: The message to print. - * - * This function is used mainly to debug the resume process before the system - * can rely on printk/console output. It uses the low-level debugging output - * routine printascii() to do its work. - */ -extern void s3c_pm_dbg(const char *msg, ...); - -#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt) -#else -#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt) +#define s3c_cpu_resume NULL #endif #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK @@ -144,20 +80,6 @@ extern void s3c_pm_debug_smdkled(u32 set, u32 clear); static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { } #endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */ -/* suspend memory checking */ - -#ifdef CONFIG_SAMSUNG_PM_CHECK -extern void s3c_pm_check_prepare(void); -extern void s3c_pm_check_restore(void); -extern void s3c_pm_check_cleanup(void); -extern void s3c_pm_check_store(void); -#else -#define s3c_pm_check_prepare() do { } while(0) -#define s3c_pm_check_restore() do { } while(0) -#define s3c_pm_check_cleanup() do { } while(0) -#define s3c_pm_check_store() do { } while(0) -#endif - /** * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ * @@ -166,6 +88,7 @@ extern void s3c_pm_check_store(void); */ extern void s3c_pm_configure_extint(void); +#ifdef CONFIG_GPIO_SAMSUNG /** * samsung_pm_restore_gpios() - restore the state of the gpios after sleep. * @@ -181,6 +104,10 @@ extern void samsung_pm_restore_gpios(void); * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios(). */ extern void samsung_pm_save_gpios(void); +#else +static inline void samsung_pm_restore_gpios(void) {} +static inline void samsung_pm_save_gpios(void) {} +#endif extern void s3c_pm_save_core(void); extern void s3c_pm_restore_core(void); diff --git a/arch/arm/plat-samsung/include/plat/pwm-clock.h b/arch/arm/plat-samsung/include/plat/pwm-clock.h deleted file mode 100644 index bf6a60eb623..00000000000 --- a/arch/arm/plat-samsung/include/plat/pwm-clock.h +++ /dev/null @@ -1,81 +0,0 @@ -/* linux/arch/arm/plat-samsung/include/plat/pwm-clock.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * SAMSUNG - pwm clock and timer support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_PLAT_PWM_CLOCK_H -#define __ASM_PLAT_PWM_CLOCK_H __FILE__ - -/** - * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk - * @tcfg: The timer TCFG1 register bits shifted down to 0. - * - * Return true if the given configuration from TCFG1 is a TCLK instead - * any of the TDIV clocks. - */ -static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) -{ - if (soc_is_s3c24xx()) - return tcfg == S3C2410_TCFG1_MUX_TCLK; - else if (soc_is_s3c64xx() || soc_is_s5pc100()) - return tcfg >= S3C64XX_TCFG1_MUX_TCLK; - else if (soc_is_s5p6440() || soc_is_s5p6450()) - return 0; - else - return tcfg == S3C64XX_TCFG1_MUX_TCLK; -} - -/** - * tcfg_to_divisor() - convert tcfg1 setting to a divisor - * @tcfg1: The tcfg1 setting, shifted down. - * - * Get the divisor value for the given tcfg1 setting. We assume the - * caller has already checked to see if this is not a TCLK source. - */ -static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) -{ - if (soc_is_s3c24xx()) - return 1 << (tcfg1 + 1); - else - return 1 << tcfg1; -} - -/** - * pwm_tdiv_has_div1() - does the tdiv setting have a /1 - * - * Return true if we have a /1 in the tdiv setting. - */ -static inline unsigned int pwm_tdiv_has_div1(void) -{ - if (soc_is_s3c24xx()) - return 0; - else - return 1; -} - -/** - * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. - * @div: The divisor to calculate the bit information for. - * - * Turn a divisor into the necessary bit field for TCFG1. - */ -static inline unsigned long pwm_tdiv_div_bits(unsigned int div) -{ - if (soc_is_s3c24xx()) - return ilog2(div) - 1; - else - return ilog2(div); -} -#endif /* __ASM_PLAT_PWM_CLOCK_H */ diff --git a/arch/arm/plat-samsung/include/plat/pwm-core.h b/arch/arm/plat-samsung/include/plat/pwm-core.h new file mode 100644 index 00000000000..5bff1facb67 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/pwm-core.h @@ -0,0 +1,22 @@ +/* + * Copyright 2013 Tomasz Figa <tomasz.figa@gmail.com> + * + * Samsung PWM controller platform data helpers. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_PWM_CORE_H +#define __ASM_ARCH_PWM_CORE_H __FILE__ + +#include <clocksource/samsung_pwm.h> + +#ifdef CONFIG_SAMSUNG_DEV_PWM +extern void samsung_pwm_set_platdata(struct samsung_pwm_variant *pd); +#else +static inline void samsung_pwm_set_platdata(struct samsung_pwm_variant *pd) { } +#endif + +#endif /* __ASM_ARCH_PWM_CORE_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-ac97.h b/arch/arm/plat-samsung/include/plat/regs-ac97.h deleted file mode 100644 index c3878f7acb8..00000000000 --- a/arch/arm/plat-samsung/include/plat/regs-ac97.h +++ /dev/null @@ -1,67 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-ac97.h - * - * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2440 AC97 Controller -*/ - -#ifndef __ASM_ARCH_REGS_AC97_H -#define __ASM_ARCH_REGS_AC97_H __FILE__ - -#define S3C_AC97_GLBCTRL (0x00) - -#define S3C_AC97_GLBCTRL_CODECREADYIE (1<<22) -#define S3C_AC97_GLBCTRL_PCMOUTURIE (1<<21) -#define S3C_AC97_GLBCTRL_PCMINORIE (1<<20) -#define S3C_AC97_GLBCTRL_MICINORIE (1<<19) -#define S3C_AC97_GLBCTRL_PCMOUTTIE (1<<18) -#define S3C_AC97_GLBCTRL_PCMINTIE (1<<17) -#define S3C_AC97_GLBCTRL_MICINTIE (1<<16) -#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF (0<<12) -#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO (1<<12) -#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA (2<<12) -#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK (3<<12) -#define S3C_AC97_GLBCTRL_PCMINTM_OFF (0<<10) -#define S3C_AC97_GLBCTRL_PCMINTM_PIO (1<<10) -#define S3C_AC97_GLBCTRL_PCMINTM_DMA (2<<10) -#define S3C_AC97_GLBCTRL_PCMINTM_MASK (3<<10) -#define S3C_AC97_GLBCTRL_MICINTM_OFF (0<<8) -#define S3C_AC97_GLBCTRL_MICINTM_PIO (1<<8) -#define S3C_AC97_GLBCTRL_MICINTM_DMA (2<<8) -#define S3C_AC97_GLBCTRL_MICINTM_MASK (3<<8) -#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE (1<<3) -#define S3C_AC97_GLBCTRL_ACLINKON (1<<2) -#define S3C_AC97_GLBCTRL_WARMRESET (1<<1) -#define S3C_AC97_GLBCTRL_COLDRESET (1<<0) - -#define S3C_AC97_GLBSTAT (0x04) - -#define S3C_AC97_GLBSTAT_CODECREADY (1<<22) -#define S3C_AC97_GLBSTAT_PCMOUTUR (1<<21) -#define S3C_AC97_GLBSTAT_PCMINORI (1<<20) -#define S3C_AC97_GLBSTAT_MICINORI (1<<19) -#define S3C_AC97_GLBSTAT_PCMOUTTI (1<<18) -#define S3C_AC97_GLBSTAT_PCMINTI (1<<17) -#define S3C_AC97_GLBSTAT_MICINTI (1<<16) -#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE (0<<0) -#define S3C_AC97_GLBSTAT_MAINSTATE_INIT (1<<0) -#define S3C_AC97_GLBSTAT_MAINSTATE_READY (2<<0) -#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE (3<<0) -#define S3C_AC97_GLBSTAT_MAINSTATE_LP (4<<0) -#define S3C_AC97_GLBSTAT_MAINSTATE_WARM (5<<0) - -#define S3C_AC97_CODEC_CMD (0x08) - -#define S3C_AC97_CODEC_CMD_READ (1<<23) - -#define S3C_AC97_STAT (0x0c) -#define S3C_AC97_PCM_ADDR (0x10) -#define S3C_AC97_PCM_DATA (0x18) -#define S3C_AC97_MIC_DATA (0x1C) - -#endif /* __ASM_ARCH_REGS_AC97_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-ata.h b/arch/arm/plat-samsung/include/plat/regs-ata.h deleted file mode 100644 index f5df92fdae2..00000000000 --- a/arch/arm/plat-samsung/include/plat/regs-ata.h +++ /dev/null @@ -1,56 +0,0 @@ -/* linux/arch/arm/plat-samsung/include/plat/regs-ata.h - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung CF-ATA register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_PLAT_REGS_ATA_H -#define __ASM_PLAT_REGS_ATA_H __FILE__ - -#define S3C_CFATA_REG(x) (x) - -#define S3C_CFATA_MUX S3C_CFATA_REG(0x0) - -#define S3C_ATA_CTRL S3C_CFATA_REG(0x0) -#define S3C_ATA_STATUS S3C_CFATA_REG(0x4) -#define S3C_ATA_CMD S3C_CFATA_REG(0x8) -#define S3C_ATA_SWRST S3C_CFATA_REG(0xc) -#define S3C_ATA_IRQ S3C_CFATA_REG(0x10) -#define S3C_ATA_IRQ_MSK S3C_CFATA_REG(0x14) -#define S3C_ATA_CFG S3C_CFATA_REG(0x18) - -#define S3C_ATA_MDMA_TIME S3C_CFATA_REG(0x28) -#define S3C_ATA_PIO_TIME S3C_CFATA_REG(0x2c) -#define S3C_ATA_UDMA_TIME S3C_CFATA_REG(0x30) -#define S3C_ATA_XFR_NUM S3C_CFATA_REG(0x34) -#define S3C_ATA_XFR_CNT S3C_CFATA_REG(0x38) -#define S3C_ATA_TBUF_START S3C_CFATA_REG(0x3c) -#define S3C_ATA_TBUF_SIZE S3C_CFATA_REG(0x40) -#define S3C_ATA_SBUF_START S3C_CFATA_REG(0x44) -#define S3C_ATA_SBUF_SIZE S3C_CFATA_REG(0x48) -#define S3C_ATA_CADR_TBUF S3C_CFATA_REG(0x4c) -#define S3C_ATA_CADR_SBUF S3C_CFATA_REG(0x50) -#define S3C_ATA_PIO_DTR S3C_CFATA_REG(0x54) -#define S3C_ATA_PIO_FED S3C_CFATA_REG(0x58) -#define S3C_ATA_PIO_SCR S3C_CFATA_REG(0x5c) -#define S3C_ATA_PIO_LLR S3C_CFATA_REG(0x60) -#define S3C_ATA_PIO_LMR S3C_CFATA_REG(0x64) -#define S3C_ATA_PIO_LHR S3C_CFATA_REG(0x68) -#define S3C_ATA_PIO_DVR S3C_CFATA_REG(0x6c) -#define S3C_ATA_PIO_CSD S3C_CFATA_REG(0x70) -#define S3C_ATA_PIO_DAD S3C_CFATA_REG(0x74) -#define S3C_ATA_PIO_READY S3C_CFATA_REG(0x78) -#define S3C_ATA_PIO_RDATA S3C_CFATA_REG(0x7c) - -#define S3C_CFATA_MUX_TRUEIDE 0x01 - -#define S3C_ATA_CFG_SWAP 0x40 -#define S3C_ATA_CFG_IORDYEN 0x02 - -#endif /* __ASM_PLAT_REGS_ATA_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-iic.h b/arch/arm/plat-samsung/include/plat/regs-iic.h deleted file mode 100644 index 2f7c17de8ac..00000000000 --- a/arch/arm/plat-samsung/include/plat/regs-iic.h +++ /dev/null @@ -1,56 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-iic.h - * - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 I2C Controller -*/ - -#ifndef __ASM_ARCH_REGS_IIC_H -#define __ASM_ARCH_REGS_IIC_H __FILE__ - -/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */ - -#define S3C2410_IICREG(x) (x) - -#define S3C2410_IICCON S3C2410_IICREG(0x00) -#define S3C2410_IICSTAT S3C2410_IICREG(0x04) -#define S3C2410_IICADD S3C2410_IICREG(0x08) -#define S3C2410_IICDS S3C2410_IICREG(0x0C) -#define S3C2440_IICLC S3C2410_IICREG(0x10) - -#define S3C2410_IICCON_ACKEN (1<<7) -#define S3C2410_IICCON_TXDIV_16 (0<<6) -#define S3C2410_IICCON_TXDIV_512 (1<<6) -#define S3C2410_IICCON_IRQEN (1<<5) -#define S3C2410_IICCON_IRQPEND (1<<4) -#define S3C2410_IICCON_SCALE(x) ((x)&15) -#define S3C2410_IICCON_SCALEMASK (0xf) - -#define S3C2410_IICSTAT_MASTER_RX (2<<6) -#define S3C2410_IICSTAT_MASTER_TX (3<<6) -#define S3C2410_IICSTAT_SLAVE_RX (0<<6) -#define S3C2410_IICSTAT_SLAVE_TX (1<<6) -#define S3C2410_IICSTAT_MODEMASK (3<<6) - -#define S3C2410_IICSTAT_START (1<<5) -#define S3C2410_IICSTAT_BUSBUSY (1<<5) -#define S3C2410_IICSTAT_TXRXEN (1<<4) -#define S3C2410_IICSTAT_ARBITR (1<<3) -#define S3C2410_IICSTAT_ASSLAVE (1<<2) -#define S3C2410_IICSTAT_ADDR0 (1<<1) -#define S3C2410_IICSTAT_LASTBIT (1<<0) - -#define S3C2410_IICLC_SDA_DELAY0 (0 << 0) -#define S3C2410_IICLC_SDA_DELAY5 (1 << 0) -#define S3C2410_IICLC_SDA_DELAY10 (2 << 0) -#define S3C2410_IICLC_SDA_DELAY15 (3 << 0) -#define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0) - -#define S3C2410_IICLC_FILTER_ON (1<<2) - -#endif /* __ASM_ARCH_REGS_IIC_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-iis.h b/arch/arm/plat-samsung/include/plat/regs-iis.h deleted file mode 100644 index a18d35e7a73..00000000000 --- a/arch/arm/plat-samsung/include/plat/regs-iis.h +++ /dev/null @@ -1,70 +0,0 @@ -/* arch/arm/plat-samsung/include/plat/regs-iis.h - * - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 IIS register definition -*/ - -#ifndef __ASM_ARCH_REGS_IIS_H -#define __ASM_ARCH_REGS_IIS_H - -#define S3C2410_IISCON (0x00) - -#define S3C2410_IISCON_LRINDEX (1 << 8) -#define S3C2410_IISCON_TXFIFORDY (1 << 7) -#define S3C2410_IISCON_RXFIFORDY (1 << 6) -#define S3C2410_IISCON_TXDMAEN (1 << 5) -#define S3C2410_IISCON_RXDMAEN (1 << 4) -#define S3C2410_IISCON_TXIDLE (1 << 3) -#define S3C2410_IISCON_RXIDLE (1 << 2) -#define S3C2410_IISCON_PSCEN (1 << 1) -#define S3C2410_IISCON_IISEN (1 << 0) - -#define S3C2410_IISMOD (0x04) - -#define S3C2440_IISMOD_MPLL (1 << 9) -#define S3C2410_IISMOD_SLAVE (1 << 8) -#define S3C2410_IISMOD_NOXFER (0 << 6) -#define S3C2410_IISMOD_RXMODE (1 << 6) -#define S3C2410_IISMOD_TXMODE (2 << 6) -#define S3C2410_IISMOD_TXRXMODE (3 << 6) -#define S3C2410_IISMOD_LR_LLOW (0 << 5) -#define S3C2410_IISMOD_LR_RLOW (1 << 5) -#define S3C2410_IISMOD_IIS (0 << 4) -#define S3C2410_IISMOD_MSB (1 << 4) -#define S3C2410_IISMOD_8BIT (0 << 3) -#define S3C2410_IISMOD_16BIT (1 << 3) -#define S3C2410_IISMOD_BITMASK (1 << 3) -#define S3C2410_IISMOD_256FS (0 << 2) -#define S3C2410_IISMOD_384FS (1 << 2) -#define S3C2410_IISMOD_16FS (0 << 0) -#define S3C2410_IISMOD_32FS (1 << 0) -#define S3C2410_IISMOD_48FS (2 << 0) -#define S3C2410_IISMOD_FS_MASK (3 << 0) - -#define S3C2410_IISPSR (0x08) - -#define S3C2410_IISPSR_INTMASK (31 << 5) -#define S3C2410_IISPSR_INTSHIFT (5) -#define S3C2410_IISPSR_EXTMASK (31 << 0) -#define S3C2410_IISPSR_EXTSHFIT (0) - -#define S3C2410_IISFCON (0x0c) - -#define S3C2410_IISFCON_TXDMA (1 << 15) -#define S3C2410_IISFCON_RXDMA (1 << 14) -#define S3C2410_IISFCON_TXENABLE (1 << 13) -#define S3C2410_IISFCON_RXENABLE (1 << 12) -#define S3C2410_IISFCON_TXMASK (0x3f << 6) -#define S3C2410_IISFCON_TXSHIFT (6) -#define S3C2410_IISFCON_RXMASK (0x3f) -#define S3C2410_IISFCON_RXSHIFT (0) - -#define S3C2410_IISFIFO (0x10) - -#endif /* __ASM_ARCH_REGS_IIS_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-nand.h b/arch/arm/plat-samsung/include/plat/regs-nand.h deleted file mode 100644 index 238efea7b9e..00000000000 --- a/arch/arm/plat-samsung/include/plat/regs-nand.h +++ /dev/null @@ -1,123 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-nand.h - * - * Copyright (c) 2004-2005 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 NAND register definitions -*/ - -#ifndef __ASM_ARM_REGS_NAND -#define __ASM_ARM_REGS_NAND - - -#define S3C2410_NFREG(x) (x) - -#define S3C2410_NFCONF S3C2410_NFREG(0x00) -#define S3C2410_NFCMD S3C2410_NFREG(0x04) -#define S3C2410_NFADDR S3C2410_NFREG(0x08) -#define S3C2410_NFDATA S3C2410_NFREG(0x0C) -#define S3C2410_NFSTAT S3C2410_NFREG(0x10) -#define S3C2410_NFECC S3C2410_NFREG(0x14) - -#define S3C2440_NFCONT S3C2410_NFREG(0x04) -#define S3C2440_NFCMD S3C2410_NFREG(0x08) -#define S3C2440_NFADDR S3C2410_NFREG(0x0C) -#define S3C2440_NFDATA S3C2410_NFREG(0x10) -#define S3C2440_NFECCD0 S3C2410_NFREG(0x14) -#define S3C2440_NFECCD1 S3C2410_NFREG(0x18) -#define S3C2440_NFECCD S3C2410_NFREG(0x1C) -#define S3C2440_NFSTAT S3C2410_NFREG(0x20) -#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24) -#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28) -#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C) -#define S3C2440_NFMECC1 S3C2410_NFREG(0x30) -#define S3C2440_NFSECC S3C2410_NFREG(0x34) -#define S3C2440_NFSBLK S3C2410_NFREG(0x38) -#define S3C2440_NFEBLK S3C2410_NFREG(0x3C) - -#define S3C2412_NFSBLK S3C2410_NFREG(0x20) -#define S3C2412_NFEBLK S3C2410_NFREG(0x24) -#define S3C2412_NFSTAT S3C2410_NFREG(0x28) -#define S3C2412_NFMECC_ERR0 S3C2410_NFREG(0x2C) -#define S3C2412_NFMECC_ERR1 S3C2410_NFREG(0x30) -#define S3C2412_NFMECC0 S3C2410_NFREG(0x34) -#define S3C2412_NFMECC1 S3C2410_NFREG(0x38) -#define S3C2412_NFSECC S3C2410_NFREG(0x3C) - -#define S3C2410_NFCONF_EN (1<<15) -#define S3C2410_NFCONF_512BYTE (1<<14) -#define S3C2410_NFCONF_4STEP (1<<13) -#define S3C2410_NFCONF_INITECC (1<<12) -#define S3C2410_NFCONF_nFCE (1<<11) -#define S3C2410_NFCONF_TACLS(x) ((x)<<8) -#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) -#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) - -#define S3C2410_NFSTAT_BUSY (1<<0) - -#define S3C2440_NFCONF_BUSWIDTH_8 (0<<0) -#define S3C2440_NFCONF_BUSWIDTH_16 (1<<0) -#define S3C2440_NFCONF_ADVFLASH (1<<3) -#define S3C2440_NFCONF_TACLS(x) ((x)<<12) -#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8) -#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4) - -#define S3C2440_NFCONT_LOCKTIGHT (1<<13) -#define S3C2440_NFCONT_SOFTLOCK (1<<12) -#define S3C2440_NFCONT_ILLEGALACC_EN (1<<10) -#define S3C2440_NFCONT_RNBINT_EN (1<<9) -#define S3C2440_NFCONT_RN_FALLING (1<<8) -#define S3C2440_NFCONT_SPARE_ECCLOCK (1<<6) -#define S3C2440_NFCONT_MAIN_ECCLOCK (1<<5) -#define S3C2440_NFCONT_INITECC (1<<4) -#define S3C2440_NFCONT_nFCE (1<<1) -#define S3C2440_NFCONT_ENABLE (1<<0) - -#define S3C2440_NFSTAT_READY (1<<0) -#define S3C2440_NFSTAT_nCE (1<<1) -#define S3C2440_NFSTAT_RnB_CHANGE (1<<2) -#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3) - -#define S3C2412_NFCONF_NANDBOOT (1<<31) -#define S3C2412_NFCONF_ECCCLKCON (1<<30) -#define S3C2412_NFCONF_ECC_MLC (1<<24) -#define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */ - -#define S3C2412_NFCONT_ECC4_DIRWR (1<<18) -#define S3C2412_NFCONT_LOCKTIGHT (1<<17) -#define S3C2412_NFCONT_SOFTLOCK (1<<16) -#define S3C2412_NFCONT_ECC4_ENCINT (1<<13) -#define S3C2412_NFCONT_ECC4_DECINT (1<<12) -#define S3C2412_NFCONT_MAIN_ECC_LOCK (1<<7) -#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5) -#define S3C2412_NFCONT_nFCE1 (1<<2) -#define S3C2412_NFCONT_nFCE0 (1<<1) - -#define S3C2412_NFSTAT_ECC_ENCDONE (1<<7) -#define S3C2412_NFSTAT_ECC_DECDONE (1<<6) -#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1<<5) -#define S3C2412_NFSTAT_RnB_CHANGE (1<<4) -#define S3C2412_NFSTAT_nFCE1 (1<<3) -#define S3C2412_NFSTAT_nFCE0 (1<<2) -#define S3C2412_NFSTAT_Res1 (1<<1) -#define S3C2412_NFSTAT_READY (1<<0) - -#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf) -#define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7) -#define S3C2412_NFECCERR_MERRDATA(x) (((x) >> 7) & 0x3ff) -#define S3C2412_NFECCERR_MERRBIT(x) (((x) >> 4) & 0x7) -#define S3C2412_NFECCERR_SPARE_ERR(x) (((x) >> 2) & 0x3) -#define S3C2412_NFECCERR_MAIN_ERR(x) (((x) >> 2) & 0x3) -#define S3C2412_NFECCERR_NONE (0) -#define S3C2412_NFECCERR_1BIT (1) -#define S3C2412_NFECCERR_MULTIBIT (2) -#define S3C2412_NFECCERR_ECCAREA (3) - - - -#endif /* __ASM_ARM_REGS_NAND */ - diff --git a/arch/arm/plat-samsung/include/plat/regs-onenand.h b/arch/arm/plat-samsung/include/plat/regs-onenand.h deleted file mode 100644 index 930ea8b88ed..00000000000 --- a/arch/arm/plat-samsung/include/plat/regs-onenand.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * linux/arch/arm/plat-s3c/include/plat/regs-onenand.h - * - * Copyright (C) 2008-2010 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __SAMSUNG_ONENAND_H__ -#define __SAMSUNG_ONENAND_H__ - -#include <mach/hardware.h> - -/* - * OneNAND Controller - */ -#define MEM_CFG_OFFSET 0x0000 -#define BURST_LEN_OFFSET 0x0010 -#define MEM_RESET_OFFSET 0x0020 -#define INT_ERR_STAT_OFFSET 0x0030 -#define INT_ERR_MASK_OFFSET 0x0040 -#define INT_ERR_ACK_OFFSET 0x0050 -#define ECC_ERR_STAT_OFFSET 0x0060 -#define MANUFACT_ID_OFFSET 0x0070 -#define DEVICE_ID_OFFSET 0x0080 -#define DATA_BUF_SIZE_OFFSET 0x0090 -#define BOOT_BUF_SIZE_OFFSET 0x00A0 -#define BUF_AMOUNT_OFFSET 0x00B0 -#define TECH_OFFSET 0x00C0 -#define FBA_WIDTH_OFFSET 0x00D0 -#define FPA_WIDTH_OFFSET 0x00E0 -#define FSA_WIDTH_OFFSET 0x00F0 -#define TRANS_SPARE_OFFSET 0x0140 -#define DBS_DFS_WIDTH_OFFSET 0x0160 -#define INT_PIN_ENABLE_OFFSET 0x01A0 -#define ACC_CLOCK_OFFSET 0x01C0 -#define FLASH_VER_ID_OFFSET 0x01F0 -#define FLASH_AUX_CNTRL_OFFSET 0x0300 /* s3c64xx only */ - -#define ONENAND_MEM_RESET_HOT 0x3 -#define ONENAND_MEM_RESET_COLD 0x2 -#define ONENAND_MEM_RESET_WARM 0x1 - -#define CACHE_OP_ERR (1 << 13) -#define RST_CMP (1 << 12) -#define RDY_ACT (1 << 11) -#define INT_ACT (1 << 10) -#define UNSUP_CMD (1 << 9) -#define LOCKED_BLK (1 << 8) -#define BLK_RW_CMP (1 << 7) -#define ERS_CMP (1 << 6) -#define PGM_CMP (1 << 5) -#define LOAD_CMP (1 << 4) -#define ERS_FAIL (1 << 3) -#define PGM_FAIL (1 << 2) -#define INT_TO (1 << 1) -#define LD_FAIL_ECC_ERR (1 << 0) - -#define TSRF (1 << 0) - -#endif diff --git a/arch/arm/plat-samsung/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h deleted file mode 100644 index 0f8263e93ee..00000000000 --- a/arch/arm/plat-samsung/include/plat/regs-rtc.h +++ /dev/null @@ -1,71 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h - * - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 Internal RTC register definition -*/ - -#ifndef __ASM_ARCH_REGS_RTC_H -#define __ASM_ARCH_REGS_RTC_H __FILE__ - -#define S3C2410_RTCREG(x) (x) -#define S3C2410_INTP S3C2410_RTCREG(0x30) -#define S3C2410_INTP_ALM (1 << 1) -#define S3C2410_INTP_TIC (1 << 0) - -#define S3C2410_RTCCON S3C2410_RTCREG(0x40) -#define S3C2410_RTCCON_RTCEN (1 << 0) -#define S3C2410_RTCCON_CNTSEL (1 << 2) -#define S3C2410_RTCCON_CLKRST (1 << 3) -#define S3C2443_RTCCON_TICSEL (1 << 4) -#define S3C64XX_RTCCON_TICEN (1 << 8) - -#define S3C2410_TICNT S3C2410_RTCREG(0x44) -#define S3C2410_TICNT_ENABLE (1 << 7) - -/* S3C2443: tick count is 15 bit wide - * TICNT[6:0] contains upper 7 bits - * TICNT1[7:0] contains lower 8 bits - */ -#define S3C2443_TICNT_PART(x) ((x & 0x7f00) >> 8) -#define S3C2443_TICNT1 S3C2410_RTCREG(0x4C) -#define S3C2443_TICNT1_PART(x) (x & 0xff) - -/* S3C2416: tick count is 32 bit wide - * TICNT[6:0] contains bits [14:8] - * TICNT1[7:0] contains lower 8 bits - * TICNT2[16:0] contains upper 17 bits - */ -#define S3C2416_TICNT2 S3C2410_RTCREG(0x48) -#define S3C2416_TICNT2_PART(x) ((x & 0xffff8000) >> 15) - -#define S3C2410_RTCALM S3C2410_RTCREG(0x50) -#define S3C2410_RTCALM_ALMEN (1 << 6) -#define S3C2410_RTCALM_YEAREN (1 << 5) -#define S3C2410_RTCALM_MONEN (1 << 4) -#define S3C2410_RTCALM_DAYEN (1 << 3) -#define S3C2410_RTCALM_HOUREN (1 << 2) -#define S3C2410_RTCALM_MINEN (1 << 1) -#define S3C2410_RTCALM_SECEN (1 << 0) - -#define S3C2410_ALMSEC S3C2410_RTCREG(0x54) -#define S3C2410_ALMMIN S3C2410_RTCREG(0x58) -#define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c) - -#define S3C2410_ALMDATE S3C2410_RTCREG(0x60) -#define S3C2410_ALMMON S3C2410_RTCREG(0x64) -#define S3C2410_ALMYEAR S3C2410_RTCREG(0x68) - -#define S3C2410_RTCSEC S3C2410_RTCREG(0x70) -#define S3C2410_RTCMIN S3C2410_RTCREG(0x74) -#define S3C2410_RTCHOUR S3C2410_RTCREG(0x78) -#define S3C2410_RTCDATE S3C2410_RTCREG(0x7c) -#define S3C2410_RTCMON S3C2410_RTCREG(0x84) -#define S3C2410_RTCYEAR S3C2410_RTCREG(0x88) - -#endif /* __ASM_ARCH_REGS_RTC_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-sdhci.h b/arch/arm/plat-samsung/include/plat/regs-sdhci.h deleted file mode 100644 index e34049ad44c..00000000000 --- a/arch/arm/plat-samsung/include/plat/regs-sdhci.h +++ /dev/null @@ -1,87 +0,0 @@ -/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C Platform - SDHCI (HSMMC) register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_S3C_SDHCI_REGS_H -#define __PLAT_S3C_SDHCI_REGS_H __FILE__ - -#define S3C_SDHCI_CONTROL2 (0x80) -#define S3C_SDHCI_CONTROL3 (0x84) -#define S3C64XX_SDHCI_CONTROL4 (0x8C) - -#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31) -#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK (1 << 30) -#define S3C_SDHCI_CTRL2_CDINVRXD3 (1 << 29) -#define S3C_SDHCI_CTRL2_SLCARDOUT (1 << 28) - -#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) -#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) -#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24) - -#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16) -#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16) -#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) - -#define S3C_SDHCI_CTRL2_ENFBCLKTX (1 << 15) -#define S3C_SDHCI_CTRL2_ENFBCLKRX (1 << 14) -#define S3C_SDHCI_CTRL2_SDCDSEL (1 << 13) -#define S3C_SDHCI_CTRL2_SDSIGPC (1 << 12) -#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11) - -#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9) -#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9) -#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9) -#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9) -#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9) -#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9) - -#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8) -#define S3C_SDHCI_CTRL2_RWAITMODE (1 << 7) -#define S3C_SDHCI_CTRL2_DISBUFRD (1 << 6) -#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4) -#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4) -#define S3C_SDHCI_CTRL2_PWRSYNC (1 << 3) -#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1) -#define S3C_SDHCI_CTRL2_HWINITFIN (1 << 0) - -#define S3C_SDHCI_CTRL3_FCSEL3 (1 << 31) -#define S3C_SDHCI_CTRL3_FCSEL2 (1 << 23) -#define S3C_SDHCI_CTRL3_FCSEL1 (1 << 15) -#define S3C_SDHCI_CTRL3_FCSEL0 (1 << 7) - -#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24) -#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24) -#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24) - -#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16) -#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16) -#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16) - -#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8) -#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8) -#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8) - -#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0) -#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0) -#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0) - -#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16) -#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16) -#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16) -#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16) -#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16) -#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16) - -#define S3C64XX_SDHCI_CONTROL4_BUSY (1) - -#endif /* __PLAT_S3C_SDHCI_REGS_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h deleted file mode 100644 index 29c26a81884..00000000000 --- a/arch/arm/plat-samsung/include/plat/regs-serial.h +++ /dev/null @@ -1,281 +0,0 @@ -/* arch/arm/plat-samsung/include/plat/regs-serial.h - * - * From linux/include/asm-arm/hardware/serial_s3c2410.h - * - * Internal header file for Samsung S3C2410 serial ports (UART0-2) - * - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * - * Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk) - * - * Adapted from: - * - * Internal header file for MX1ADS serial ports (UART1 & 2) - * - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#ifndef __ASM_ARM_REGS_SERIAL_H -#define __ASM_ARM_REGS_SERIAL_H - -#define S3C24XX_VA_UART0 (S3C_VA_UART) -#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 ) -#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 ) -#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 ) - -#define S3C2410_PA_UART0 (S3C24XX_PA_UART) -#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 ) -#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 ) -#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 ) - -#define S3C2410_URXH (0x24) -#define S3C2410_UTXH (0x20) -#define S3C2410_ULCON (0x00) -#define S3C2410_UCON (0x04) -#define S3C2410_UFCON (0x08) -#define S3C2410_UMCON (0x0C) -#define S3C2410_UBRDIV (0x28) -#define S3C2410_UTRSTAT (0x10) -#define S3C2410_UERSTAT (0x14) -#define S3C2410_UFSTAT (0x18) -#define S3C2410_UMSTAT (0x1C) - -#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3)) - -#define S3C2410_LCON_CS5 (0x0) -#define S3C2410_LCON_CS6 (0x1) -#define S3C2410_LCON_CS7 (0x2) -#define S3C2410_LCON_CS8 (0x3) -#define S3C2410_LCON_CSMASK (0x3) - -#define S3C2410_LCON_PNONE (0x0) -#define S3C2410_LCON_PEVEN (0x5 << 3) -#define S3C2410_LCON_PODD (0x4 << 3) -#define S3C2410_LCON_PMASK (0x7 << 3) - -#define S3C2410_LCON_STOPB (1<<2) -#define S3C2410_LCON_IRM (1<<6) - -#define S3C2440_UCON_CLKMASK (3<<10) -#define S3C2440_UCON_CLKSHIFT (10) -#define S3C2440_UCON_PCLK (0<<10) -#define S3C2440_UCON_UCLK (1<<10) -#define S3C2440_UCON_PCLK2 (2<<10) -#define S3C2440_UCON_FCLK (3<<10) -#define S3C2443_UCON_EPLL (3<<10) - -#define S3C6400_UCON_CLKMASK (3<<10) -#define S3C6400_UCON_CLKSHIFT (10) -#define S3C6400_UCON_PCLK (0<<10) -#define S3C6400_UCON_PCLK2 (2<<10) -#define S3C6400_UCON_UCLK0 (1<<10) -#define S3C6400_UCON_UCLK1 (3<<10) - -#define S3C2440_UCON2_FCLK_EN (1<<15) -#define S3C2440_UCON0_DIVMASK (15 << 12) -#define S3C2440_UCON1_DIVMASK (15 << 12) -#define S3C2440_UCON2_DIVMASK (7 << 12) -#define S3C2440_UCON_DIVSHIFT (12) - -#define S3C2412_UCON_CLKMASK (3<<10) -#define S3C2412_UCON_CLKSHIFT (10) -#define S3C2412_UCON_UCLK (1<<10) -#define S3C2412_UCON_USYSCLK (3<<10) -#define S3C2412_UCON_PCLK (0<<10) -#define S3C2412_UCON_PCLK2 (2<<10) - -#define S3C2410_UCON_CLKMASK (1 << 10) -#define S3C2410_UCON_CLKSHIFT (10) -#define S3C2410_UCON_UCLK (1<<10) -#define S3C2410_UCON_SBREAK (1<<4) - -#define S3C2410_UCON_TXILEVEL (1<<9) -#define S3C2410_UCON_RXILEVEL (1<<8) -#define S3C2410_UCON_TXIRQMODE (1<<2) -#define S3C2410_UCON_RXIRQMODE (1<<0) -#define S3C2410_UCON_RXFIFO_TOI (1<<7) -#define S3C2443_UCON_RXERR_IRQEN (1<<6) -#define S3C2443_UCON_LOOPBACK (1<<5) - -#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI) - -#define S3C2410_UFCON_FIFOMODE (1<<0) -#define S3C2410_UFCON_TXTRIG0 (0<<6) -#define S3C2410_UFCON_RXTRIG8 (1<<4) -#define S3C2410_UFCON_RXTRIG12 (2<<4) - -/* S3C2440 FIFO trigger levels */ -#define S3C2440_UFCON_RXTRIG1 (0<<4) -#define S3C2440_UFCON_RXTRIG8 (1<<4) -#define S3C2440_UFCON_RXTRIG16 (2<<4) -#define S3C2440_UFCON_RXTRIG32 (3<<4) - -#define S3C2440_UFCON_TXTRIG0 (0<<6) -#define S3C2440_UFCON_TXTRIG16 (1<<6) -#define S3C2440_UFCON_TXTRIG32 (2<<6) -#define S3C2440_UFCON_TXTRIG48 (3<<6) - -#define S3C2410_UFCON_RESETBOTH (3<<1) -#define S3C2410_UFCON_RESETTX (1<<2) -#define S3C2410_UFCON_RESETRX (1<<1) - -#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S3C2410_UFCON_TXTRIG0 | \ - S3C2410_UFCON_RXTRIG8 ) - -#define S3C2410_UMCOM_AFC (1<<4) -#define S3C2410_UMCOM_RTS_LOW (1<<0) - -#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */ -#define S3C2412_UMCON_AFC_56 (1<<5) -#define S3C2412_UMCON_AFC_48 (2<<5) -#define S3C2412_UMCON_AFC_40 (3<<5) -#define S3C2412_UMCON_AFC_32 (4<<5) -#define S3C2412_UMCON_AFC_24 (5<<5) -#define S3C2412_UMCON_AFC_16 (6<<5) -#define S3C2412_UMCON_AFC_8 (7<<5) - -#define S3C2410_UFSTAT_TXFULL (1<<9) -#define S3C2410_UFSTAT_RXFULL (1<<8) -#define S3C2410_UFSTAT_TXMASK (15<<4) -#define S3C2410_UFSTAT_TXSHIFT (4) -#define S3C2410_UFSTAT_RXMASK (15<<0) -#define S3C2410_UFSTAT_RXSHIFT (0) - -/* UFSTAT S3C2443 same as S3C2440 */ -#define S3C2440_UFSTAT_TXFULL (1<<14) -#define S3C2440_UFSTAT_RXFULL (1<<6) -#define S3C2440_UFSTAT_TXSHIFT (8) -#define S3C2440_UFSTAT_RXSHIFT (0) -#define S3C2440_UFSTAT_TXMASK (63<<8) -#define S3C2440_UFSTAT_RXMASK (63) - -#define S3C2410_UTRSTAT_TXE (1<<2) -#define S3C2410_UTRSTAT_TXFE (1<<1) -#define S3C2410_UTRSTAT_RXDR (1<<0) - -#define S3C2410_UERSTAT_OVERRUN (1<<0) -#define S3C2410_UERSTAT_FRAME (1<<2) -#define S3C2410_UERSTAT_BREAK (1<<3) -#define S3C2443_UERSTAT_PARITY (1<<1) - -#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \ - S3C2410_UERSTAT_FRAME | \ - S3C2410_UERSTAT_BREAK) - -#define S3C2410_UMSTAT_CTS (1<<0) -#define S3C2410_UMSTAT_DeltaCTS (1<<2) - -#define S3C2443_DIVSLOT (0x2C) - -/* S3C64XX interrupt registers. */ -#define S3C64XX_UINTP 0x30 -#define S3C64XX_UINTSP 0x34 -#define S3C64XX_UINTM 0x38 - -#define S3C64XX_UINTM_RXD (0) -#define S3C64XX_UINTM_TXD (2) -#define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD) -#define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD) - -/* Following are specific to S5PV210 */ -#define S5PV210_UCON_CLKMASK (1<<10) -#define S5PV210_UCON_CLKSHIFT (10) -#define S5PV210_UCON_PCLK (0<<10) -#define S5PV210_UCON_UCLK (1<<10) - -#define S5PV210_UFCON_TXTRIG0 (0<<8) -#define S5PV210_UFCON_TXTRIG4 (1<<8) -#define S5PV210_UFCON_TXTRIG8 (2<<8) -#define S5PV210_UFCON_TXTRIG16 (3<<8) -#define S5PV210_UFCON_TXTRIG32 (4<<8) -#define S5PV210_UFCON_TXTRIG64 (5<<8) -#define S5PV210_UFCON_TXTRIG128 (6<<8) -#define S5PV210_UFCON_TXTRIG256 (7<<8) - -#define S5PV210_UFCON_RXTRIG1 (0<<4) -#define S5PV210_UFCON_RXTRIG4 (1<<4) -#define S5PV210_UFCON_RXTRIG8 (2<<4) -#define S5PV210_UFCON_RXTRIG16 (3<<4) -#define S5PV210_UFCON_RXTRIG32 (4<<4) -#define S5PV210_UFCON_RXTRIG64 (5<<4) -#define S5PV210_UFCON_RXTRIG128 (6<<4) -#define S5PV210_UFCON_RXTRIG256 (7<<4) - -#define S5PV210_UFSTAT_TXFULL (1<<24) -#define S5PV210_UFSTAT_RXFULL (1<<8) -#define S5PV210_UFSTAT_TXMASK (255<<16) -#define S5PV210_UFSTAT_TXSHIFT (16) -#define S5PV210_UFSTAT_RXMASK (255<<0) -#define S5PV210_UFSTAT_RXSHIFT (0) - -#define S3C2410_UCON_CLKSEL0 (1 << 0) -#define S3C2410_UCON_CLKSEL1 (1 << 1) -#define S3C2410_UCON_CLKSEL2 (1 << 2) -#define S3C2410_UCON_CLKSEL3 (1 << 3) - -/* Default values for s5pv210 UCON and UFCON uart registers */ -#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) - -#ifndef __ASSEMBLY__ - -/* configuration structure for per-machine configurations for the - * serial port - * - * the pointer is setup by the machine specific initialisation from the - * arch/arm/mach-s3c2410/ directory. -*/ - -struct s3c2410_uartcfg { - unsigned char hwport; /* hardware port number */ - unsigned char unused; - unsigned short flags; - upf_t uart_flags; /* default uart flags */ - unsigned int clk_sel; - - unsigned int has_fracval; - - unsigned long ucon; /* value of ucon for port */ - unsigned long ulcon; /* value of ulcon for port */ - unsigned long ufcon; /* value of ufcon for port */ -}; - -/* s3c24xx_uart_devs - * - * this is exported from the core as we cannot use driver_register(), - * or platform_add_device() before the console_initcall() -*/ - -extern struct platform_device *s3c24xx_uart_devs[4]; - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_ARM_REGS_SERIAL_H */ - diff --git a/arch/arm/plat-samsung/include/plat/regs-timer.h b/arch/arm/plat-samsung/include/plat/regs-timer.h deleted file mode 100644 index d097d92f8cc..00000000000 --- a/arch/arm/plat-samsung/include/plat/regs-timer.h +++ /dev/null @@ -1,124 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-timer.h - * - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 Timer configuration -*/ - -#ifndef __ASM_ARCH_REGS_TIMER_H -#define __ASM_ARCH_REGS_TIMER_H - -#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x)) -#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c)) - -#define S3C2410_TCFG0 S3C_TIMERREG(0x00) -#define S3C2410_TCFG1 S3C_TIMERREG(0x04) -#define S3C2410_TCON S3C_TIMERREG(0x08) - -#define S3C64XX_TINT_CSTAT S3C_TIMERREG(0x44) - -#define S3C2410_TCFG_PRESCALER0_MASK (255<<0) -#define S3C2410_TCFG_PRESCALER1_MASK (255<<8) -#define S3C2410_TCFG_PRESCALER1_SHIFT (8) -#define S3C2410_TCFG_DEADZONE_MASK (255<<16) -#define S3C2410_TCFG_DEADZONE_SHIFT (16) - -#define S3C2410_TCFG1_MUX4_DIV2 (0<<16) -#define S3C2410_TCFG1_MUX4_DIV4 (1<<16) -#define S3C2410_TCFG1_MUX4_DIV8 (2<<16) -#define S3C2410_TCFG1_MUX4_DIV16 (3<<16) -#define S3C2410_TCFG1_MUX4_TCLK1 (4<<16) -#define S3C2410_TCFG1_MUX4_MASK (15<<16) -#define S3C2410_TCFG1_MUX4_SHIFT (16) - -#define S3C2410_TCFG1_MUX3_DIV2 (0<<12) -#define S3C2410_TCFG1_MUX3_DIV4 (1<<12) -#define S3C2410_TCFG1_MUX3_DIV8 (2<<12) -#define S3C2410_TCFG1_MUX3_DIV16 (3<<12) -#define S3C2410_TCFG1_MUX3_TCLK1 (4<<12) -#define S3C2410_TCFG1_MUX3_MASK (15<<12) - - -#define S3C2410_TCFG1_MUX2_DIV2 (0<<8) -#define S3C2410_TCFG1_MUX2_DIV4 (1<<8) -#define S3C2410_TCFG1_MUX2_DIV8 (2<<8) -#define S3C2410_TCFG1_MUX2_DIV16 (3<<8) -#define S3C2410_TCFG1_MUX2_TCLK1 (4<<8) -#define S3C2410_TCFG1_MUX2_MASK (15<<8) - - -#define S3C2410_TCFG1_MUX1_DIV2 (0<<4) -#define S3C2410_TCFG1_MUX1_DIV4 (1<<4) -#define S3C2410_TCFG1_MUX1_DIV8 (2<<4) -#define S3C2410_TCFG1_MUX1_DIV16 (3<<4) -#define S3C2410_TCFG1_MUX1_TCLK0 (4<<4) -#define S3C2410_TCFG1_MUX1_MASK (15<<4) - -#define S3C2410_TCFG1_MUX0_DIV2 (0<<0) -#define S3C2410_TCFG1_MUX0_DIV4 (1<<0) -#define S3C2410_TCFG1_MUX0_DIV8 (2<<0) -#define S3C2410_TCFG1_MUX0_DIV16 (3<<0) -#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0) -#define S3C2410_TCFG1_MUX0_MASK (15<<0) - -#define S3C2410_TCFG1_MUX_DIV2 (0<<0) -#define S3C2410_TCFG1_MUX_DIV4 (1<<0) -#define S3C2410_TCFG1_MUX_DIV8 (2<<0) -#define S3C2410_TCFG1_MUX_DIV16 (3<<0) -#define S3C2410_TCFG1_MUX_TCLK (4<<0) -#define S3C2410_TCFG1_MUX_MASK (15<<0) - -#define S3C64XX_TCFG1_MUX_DIV1 (0<<0) -#define S3C64XX_TCFG1_MUX_DIV2 (1<<0) -#define S3C64XX_TCFG1_MUX_DIV4 (2<<0) -#define S3C64XX_TCFG1_MUX_DIV8 (3<<0) -#define S3C64XX_TCFG1_MUX_DIV16 (4<<0) -#define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */ -#define S3C64XX_TCFG1_MUX_MASK (15<<0) - -#define S3C2410_TCFG1_SHIFT(x) ((x) * 4) - -/* for each timer, we have an count buffer, an compare buffer and - * an observation buffer -*/ - -/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */ - -#define S3C2410_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00) -#define S3C2410_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04) -#define S3C2410_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08)) - -#define S3C2410_TCON_T4RELOAD (1<<22) -#define S3C2410_TCON_T4MANUALUPD (1<<21) -#define S3C2410_TCON_T4START (1<<20) - -#define S3C2410_TCON_T3RELOAD (1<<19) -#define S3C2410_TCON_T3INVERT (1<<18) -#define S3C2410_TCON_T3MANUALUPD (1<<17) -#define S3C2410_TCON_T3START (1<<16) - -#define S3C2410_TCON_T2RELOAD (1<<15) -#define S3C2410_TCON_T2INVERT (1<<14) -#define S3C2410_TCON_T2MANUALUPD (1<<13) -#define S3C2410_TCON_T2START (1<<12) - -#define S3C2410_TCON_T1RELOAD (1<<11) -#define S3C2410_TCON_T1INVERT (1<<10) -#define S3C2410_TCON_T1MANUALUPD (1<<9) -#define S3C2410_TCON_T1START (1<<8) - -#define S3C2410_TCON_T0DEADZONE (1<<4) -#define S3C2410_TCON_T0RELOAD (1<<3) -#define S3C2410_TCON_T0INVERT (1<<2) -#define S3C2410_TCON_T0MANUALUPD (1<<1) -#define S3C2410_TCON_T0START (1<<0) - -#endif /* __ASM_ARCH_REGS_TIMER_H */ - - - diff --git a/arch/arm/plat-samsung/include/plat/regs-watchdog.h b/arch/arm/plat-samsung/include/plat/regs-watchdog.h deleted file mode 100644 index 4938492470f..00000000000 --- a/arch/arm/plat-samsung/include/plat/regs-watchdog.h +++ /dev/null @@ -1,41 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h - * - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 Watchdog timer control -*/ - - -#ifndef __ASM_ARCH_REGS_WATCHDOG_H -#define __ASM_ARCH_REGS_WATCHDOG_H - -#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG) - -#define S3C2410_WTCON S3C_WDOGREG(0x00) -#define S3C2410_WTDAT S3C_WDOGREG(0x04) -#define S3C2410_WTCNT S3C_WDOGREG(0x08) - -/* the watchdog can either generate a reset pulse, or an - * interrupt. - */ - -#define S3C2410_WTCON_RSTEN (0x01) -#define S3C2410_WTCON_INTEN (1<<2) -#define S3C2410_WTCON_ENABLE (1<<5) - -#define S3C2410_WTCON_DIV16 (0<<3) -#define S3C2410_WTCON_DIV32 (1<<3) -#define S3C2410_WTCON_DIV64 (2<<3) -#define S3C2410_WTCON_DIV128 (3<<3) - -#define S3C2410_WTCON_PRESCALE(x) ((x) << 8) -#define S3C2410_WTCON_PRESCALE_MASK (0xff00) - -#endif /* __ASM_ARCH_REGS_WATCHDOG_H */ - - diff --git a/arch/arm/plat-samsung/include/plat/rtc-core.h b/arch/arm/plat-samsung/include/plat/rtc-core.h deleted file mode 100644 index 21d8594d37c..00000000000 --- a/arch/arm/plat-samsung/include/plat/rtc-core.h +++ /dev/null @@ -1,27 +0,0 @@ -/* linux/arch/arm/plat-samsung/include/plat/rtc-core.h - * - * Copyright (c) 2011 Heiko Stuebner <heiko@sntech.de> - * - * Samsung RTC Controller core functions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_PLAT_RTC_CORE_H -#define __ASM_PLAT_RTC_CORE_H __FILE__ - -/* These functions are only for use with the core support code, such as - * the cpu specific initialisation code - */ - -/* re-define device name depending on support. */ -static inline void s3c_rtc_setname(char *name) -{ -#if defined(CONFIG_SAMSUNG_DEV_RTC) || defined(CONFIG_PLAT_S3C24XX) - s3c_device_rtc.name = name; -#endif -} - -#endif /* __ASM_PLAT_RTC_CORE_H */ diff --git a/arch/arm/plat-samsung/include/plat/s3c2410.h b/arch/arm/plat-samsung/include/plat/s3c2410.h deleted file mode 100644 index 55b0e5f51e9..00000000000 --- a/arch/arm/plat-samsung/include/plat/s3c2410.h +++ /dev/null @@ -1,31 +0,0 @@ -/* linux/arch/arm/plat-samsung/include/plat/s3c2410.h - * - * Copyright (c) 2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Header file for s3c2410 machine directory - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#ifdef CONFIG_CPU_S3C2410 - -extern int s3c2410_init(void); -extern int s3c2410a_init(void); - -extern void s3c2410_map_io(void); - -extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); - -extern void s3c2410_init_clocks(int xtal); - -#else -#define s3c2410_init_clocks NULL -#define s3c2410_init_uarts NULL -#define s3c2410_map_io NULL -#define s3c2410_init NULL -#define s3c2410a_init NULL -#endif diff --git a/arch/arm/plat-samsung/include/plat/s3c2412.h b/arch/arm/plat-samsung/include/plat/s3c2412.h deleted file mode 100644 index cbae50ddacc..00000000000 --- a/arch/arm/plat-samsung/include/plat/s3c2412.h +++ /dev/null @@ -1,32 +0,0 @@ -/* linux/arch/arm/plat-samsung/include/plat/s3c2412.h - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Header file for s3c2412 cpu support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifdef CONFIG_CPU_S3C2412 - -extern int s3c2412_init(void); - -extern void s3c2412_map_io(void); - -extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); - -extern void s3c2412_init_clocks(int xtal); - -extern int s3c2412_baseclk_add(void); - -extern void s3c2412_restart(char mode, const char *cmd); -#else -#define s3c2412_init_clocks NULL -#define s3c2412_init_uarts NULL -#define s3c2412_map_io NULL -#define s3c2412_init NULL -#define s3c2412_restart NULL -#endif diff --git a/arch/arm/plat-samsung/include/plat/s3c2416.h b/arch/arm/plat-samsung/include/plat/s3c2416.h deleted file mode 100644 index f27399a3c68..00000000000 --- a/arch/arm/plat-samsung/include/plat/s3c2416.h +++ /dev/null @@ -1,37 +0,0 @@ -/* linux/arch/arm/plat-samsung/include/plat/s3c2416.h - * - * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com> - * - * Header file for s3c2416 cpu support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifdef CONFIG_CPU_S3C2416 - -struct s3c2410_uartcfg; - -extern int s3c2416_init(void); - -extern void s3c2416_map_io(void); - -extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no); - -extern void s3c2416_init_clocks(int xtal); - -extern int s3c2416_baseclk_add(void); - -extern void s3c2416_restart(char mode, const char *cmd); - -extern void s3c2416_init_irq(void); -extern struct syscore_ops s3c2416_irq_syscore_ops; - -#else -#define s3c2416_init_clocks NULL -#define s3c2416_init_uarts NULL -#define s3c2416_map_io NULL -#define s3c2416_init NULL -#define s3c2416_restart NULL -#endif diff --git a/arch/arm/plat-samsung/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h deleted file mode 100644 index 71b88ec4895..00000000000 --- a/arch/arm/plat-samsung/include/plat/s3c2443.h +++ /dev/null @@ -1,36 +0,0 @@ -/* linux/arch/arm/plat-samsung/include/plat/s3c2443.h - * - * Copyright (c) 2004-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Header file for s3c2443 cpu support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifdef CONFIG_CPU_S3C2443 - -struct s3c2410_uartcfg; - -extern int s3c2443_init(void); - -extern void s3c2443_map_io(void); - -extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no); - -extern void s3c2443_init_clocks(int xtal); - -extern int s3c2443_baseclk_add(void); - -extern void s3c2443_restart(char mode, const char *cmd); - -extern void s3c2443_init_irq(void); -#else -#define s3c2443_init_clocks NULL -#define s3c2443_init_uarts NULL -#define s3c2443_map_io NULL -#define s3c2443_init NULL -#define s3c2443_restart NULL -#endif diff --git a/arch/arm/plat-samsung/include/plat/s3c244x.h b/arch/arm/plat-samsung/include/plat/s3c244x.h deleted file mode 100644 index ea0c961b760..00000000000 --- a/arch/arm/plat-samsung/include/plat/s3c244x.h +++ /dev/null @@ -1,42 +0,0 @@ -/* linux/arch/arm/plat-samsung/include/plat/s3c244x.h - * - * Copyright (c) 2004-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Header file for S3C2440 and S3C2442 cpu support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) - -extern void s3c244x_map_io(void); - -extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); - -extern void s3c244x_init_clocks(int xtal); - -#else -#define s3c244x_init_clocks NULL -#define s3c244x_init_uarts NULL -#endif - -#ifdef CONFIG_CPU_S3C2440 -extern int s3c2440_init(void); - -extern void s3c2440_map_io(void); -#else -#define s3c2440_init NULL -#define s3c2440_map_io NULL -#endif - -#ifdef CONFIG_CPU_S3C2442 -extern int s3c2442_init(void); - -extern void s3c2442_map_io(void); -#else -#define s3c2442_init NULL -#define s3c2442_map_io NULL -#endif diff --git a/arch/arm/plat-samsung/include/plat/s5p-time.h b/arch/arm/plat-samsung/include/plat/s5p-time.h deleted file mode 100644 index 9c96f3586ce..00000000000 --- a/arch/arm/plat-samsung/include/plat/s5p-time.h +++ /dev/null @@ -1,40 +0,0 @@ -/* linux/arch/arm/plat-samsung/include/plat/s5p-time.h - * - * Copyright 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Header file for s5p time support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_PLAT_S5P_TIME_H -#define __ASM_PLAT_S5P_TIME_H __FILE__ - -/* S5P HR-Timer Clock mode */ -enum s5p_timer_mode { - S5P_PWM0, - S5P_PWM1, - S5P_PWM2, - S5P_PWM3, - S5P_PWM4, -}; - -struct s5p_timer_source { - unsigned int event_id; - unsigned int source_id; -}; - -/* Be able to sleep for atleast 4 seconds (usually more) */ -#define S5PTIMER_MIN_RANGE 4 - -#define TCNT_MAX 0xffffffff -#define NON_PERIODIC 0 -#define PERIODIC 1 - -extern void __init s5p_set_timer_source(enum s5p_timer_mode event, - enum s5p_timer_mode source); -extern void s5p_timer_init(void); -#endif /* __ASM_PLAT_S5P_TIME_H */ diff --git a/arch/arm/plat-samsung/include/plat/samsung-time.h b/arch/arm/plat-samsung/include/plat/samsung-time.h new file mode 100644 index 00000000000..209464adef9 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/samsung-time.h @@ -0,0 +1,30 @@ +/* linux/arch/arm/plat-samsung/include/plat/samsung-time.h + * + * Copyright 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Header file for samsung s3c and s5p time support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_SAMSUNG_TIME_H +#define __ASM_PLAT_SAMSUNG_TIME_H __FILE__ + +/* SAMSUNG HR-Timer Clock mode */ +enum samsung_timer_mode { + SAMSUNG_PWM0, + SAMSUNG_PWM1, + SAMSUNG_PWM2, + SAMSUNG_PWM3, + SAMSUNG_PWM4, +}; + +extern void __init samsung_set_timer_source(enum samsung_timer_mode event, + enum samsung_timer_mode source); + +extern void __init samsung_timer_init(void); + +#endif /* __ASM_PLAT_SAMSUNG_TIME_H */ diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 9b87f38fc4f..bf650218b40 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -18,62 +18,9 @@ #ifndef __PLAT_S3C_SDHCI_H #define __PLAT_S3C_SDHCI_H __FILE__ +#include <linux/platform_data/mmc-sdhci-s3c.h> #include <plat/devs.h> -struct platform_device; -struct mmc_host; -struct mmc_card; -struct mmc_ios; - -enum cd_types { - S3C_SDHCI_CD_INTERNAL, /* use mmc internal CD line */ - S3C_SDHCI_CD_EXTERNAL, /* use external callback */ - S3C_SDHCI_CD_GPIO, /* use external gpio pin for CD line */ - S3C_SDHCI_CD_NONE, /* no CD line, use polling to detect card */ - S3C_SDHCI_CD_PERMANENT, /* no CD line, card permanently wired to host */ -}; - -/** - * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI - * @max_width: The maximum number of data bits supported. - * @host_caps: Standard MMC host capabilities bit field. - * @host_caps2: The second standard MMC host capabilities bit field. - * @cd_type: Type of Card Detection method (see cd_types enum above) - * @ext_cd_init: Initialize external card detect subsystem. Called on - * sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL. - * notify_func argument is a callback to the sdhci-s3c driver - * that triggers the card detection event. Callback arguments: - * dev is pointer to platform device of the host controller, - * state is new state of the card (0 - removed, 1 - inserted). - * @ext_cd_cleanup: Cleanup external card detect subsystem. Called on - * sdhci-s3c driver remove when cd_type == S3C_SDHCI_CD_EXTERNAL. - * notify_func argument is the same callback as for ext_cd_init. - * @ext_cd_gpio: gpio pin used for external CD line, valid only if - * cd_type == S3C_SDHCI_CD_GPIO - * @ext_cd_gpio_invert: invert values for external CD gpio line - * @cfg_gpio: Configure the GPIO for a specific card bit-width - * - * Initialisation data specific to either the machine or the platform - * for the device driver to use or call-back when configuring gpio or - * card speed information. -*/ -struct s3c_sdhci_platdata { - unsigned int max_width; - unsigned int host_caps; - unsigned int host_caps2; - unsigned int pm_caps; - enum cd_types cd_type; - - int ext_cd_gpio; - bool ext_cd_gpio_invert; - int (*ext_cd_init)(void (*notify_func)(struct platform_device *, - int state)); - int (*ext_cd_cleanup)(void (*notify_func)(struct platform_device *, - int state)); - - void (*cfg_gpio)(struct platform_device *dev, int width); -}; - /* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data * @pd: The default platform data for this device. * @set: Pointer to the platform data to fill in. @@ -206,7 +153,7 @@ static inline void s3c6400_default_sdhci2(void) { } /* S5P64X0 SDHCI setup */ -#ifdef CONFIG_S5P64X0_SETUP_SDHCI +#ifdef CONFIG_S5P64X0_SETUP_SDHCI_GPIO static inline void s5p64x0_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC @@ -241,7 +188,7 @@ static inline void s5p64x0_default_sdhci1(void) { } static inline void s5p6440_default_sdhci2(void) { } static inline void s5p6450_default_sdhci2(void) { } -#endif /* CONFIG_S5P64X0_SETUP_SDHCI */ +#endif /* CONFIG_S5P64X0_SETUP_SDHCI_GPIO */ /* S5PC100 SDHCI setup */ @@ -313,44 +260,6 @@ static inline void s5pv210_default_sdhci3(void) { } #endif /* CONFIG_S5PV210_SETUP_SDHCI */ -/* EXYNOS4 SDHCI setup */ -#ifdef CONFIG_EXYNOS4_SETUP_SDHCI -static inline void exynos4_default_sdhci0(void) -{ -#ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio; -#endif -} - -static inline void exynos4_default_sdhci1(void) -{ -#ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio; -#endif -} - -static inline void exynos4_default_sdhci2(void) -{ -#ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio; -#endif -} - -static inline void exynos4_default_sdhci3(void) -{ -#ifdef CONFIG_S3C_DEV_HSMMC3 - s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio; -#endif -} - -#else -static inline void exynos4_default_sdhci0(void) { } -static inline void exynos4_default_sdhci1(void) { } -static inline void exynos4_default_sdhci2(void) { } -static inline void exynos4_default_sdhci3(void) { } - -#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */ - static inline void s3c_sdhci_setname(int id, char *name) { switch (id) { @@ -378,5 +287,4 @@ static inline void s3c_sdhci_setname(int id, char *name) break; } } - #endif /* __PLAT_S3C_SDHCI_H */ diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h deleted file mode 100644 index 438b24846e7..00000000000 --- a/arch/arm/plat-samsung/include/plat/uncompress.h +++ /dev/null @@ -1,158 +0,0 @@ -/* arch/arm/plat-samsung/include/plat/uncompress.h - * - * Copyright 2003, 2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C - uncompress code - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_PLAT_UNCOMPRESS_H -#define __ASM_PLAT_UNCOMPRESS_H - -typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ - -/* uart setup */ - -unsigned int fifo_mask; -unsigned int fifo_max; - -/* forward declerations */ - -static void arch_detect_cpu(void); - -/* defines for UART registers */ - -#include <plat/regs-serial.h> -#include <plat/regs-watchdog.h> - -/* working in physical space... */ -#undef S3C2410_WDOGREG -#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x))) - -/* how many bytes we allow into the FIFO at a time in FIFO mode */ -#define FIFO_MAX (14) - -#ifdef S3C_PA_UART -#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT) -#endif - -static __inline__ void -uart_wr(unsigned int reg, unsigned int val) -{ - volatile unsigned int *ptr; - - ptr = (volatile unsigned int *)(reg + uart_base); - *ptr = val; -} - -static __inline__ unsigned int -uart_rd(unsigned int reg) -{ - volatile unsigned int *ptr; - - ptr = (volatile unsigned int *)(reg + uart_base); - return *ptr; -} - -/* we can deal with the case the UARTs are being run - * in FIFO mode, so that we don't hold up our execution - * waiting for tx to happen... -*/ - -static void putc(int ch) -{ - if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) { - int level; - - while (1) { - level = uart_rd(S3C2410_UFSTAT); - level &= fifo_mask; - - if (level < fifo_max) - break; - } - - } else { - /* not using fifos */ - - while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE) - barrier(); - } - - /* write byte to transmission register */ - uart_wr(S3C2410_UTXH, ch); -} - -static inline void flush(void) -{ -} - -#define __raw_writel(d, ad) \ - do { \ - *((volatile unsigned int __force *)(ad)) = (d); \ - } while (0) - -#ifdef CONFIG_S3C_BOOT_ERROR_RESET - -static void arch_decomp_error(const char *x) -{ - putstr("\n\n"); - putstr(x); - putstr("\n\n -- System resetting\n"); - - __raw_writel(0x4000, S3C2410_WTDAT); - __raw_writel(0x4000, S3C2410_WTCNT); - __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON); - - while(1); -} - -#define arch_error arch_decomp_error -#endif - -#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO -static inline void arch_enable_uart_fifo(void) -{ - u32 fifocon = uart_rd(S3C2410_UFCON); - - if (!(fifocon & S3C2410_UFCON_FIFOMODE)) { - fifocon |= S3C2410_UFCON_RESETBOTH; - uart_wr(S3C2410_UFCON, fifocon); - - /* wait for fifo reset to complete */ - while (1) { - fifocon = uart_rd(S3C2410_UFCON); - if (!(fifocon & S3C2410_UFCON_RESETBOTH)) - break; - } - } -} -#else -#define arch_enable_uart_fifo() do { } while(0) -#endif - - -static void -arch_decomp_setup(void) -{ - /* we may need to setup the uart(s) here if we are not running - * on an BAST... the BAST will have left the uarts configured - * after calling linux. - */ - - arch_detect_cpu(); - - /* Enable the UART FIFOs if they where not enabled and our - * configuration says we should turn them on. - */ - - arch_enable_uart_fifo(); -} - - -#endif /* __ASM_PLAT_UNCOMPRESS_H */ diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h index 959bcdb03a2..ab34dfadb7f 100644 --- a/arch/arm/plat-samsung/include/plat/usb-phy.h +++ b/arch/arm/plat-samsung/include/plat/usb-phy.h @@ -11,10 +11,7 @@ #ifndef __PLAT_SAMSUNG_USB_PHY_H #define __PLAT_SAMSUNG_USB_PHY_H __FILE__ -enum s5p_usb_phy_type { - S5P_USB_PHY_DEVICE, - S5P_USB_PHY_HOST, -}; +#include <linux/usb/samsung_usb_phy.h> extern int s5p_usb_phy_init(struct platform_device *pdev, int type); extern int s5p_usb_phy_exit(struct platform_device *pdev, int type); diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h index bc4db9b04e3..0386b8f7662 100644 --- a/arch/arm/plat-samsung/include/plat/watchdog-reset.h +++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h @@ -10,37 +10,11 @@ * published by the Free Software Foundation. */ -#include <plat/clock.h> -#include <plat/regs-watchdog.h> -#include <mach/map.h> +#ifndef __PLAT_SAMSUNG_WATCHDOG_RESET_H +#define __PLAT_SAMSUNG_WATCHDOG_RESET_H -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/delay.h> +extern void samsung_wdt_reset(void); +extern void samsung_wdt_reset_of_init(void); +extern void samsung_wdt_reset_init(void __iomem *base); -static inline void arch_wdt_reset(void) -{ - printk("arch_reset: attempting watchdog reset\n"); - - __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ - - if (!IS_ERR(s3c2410_wdtclk)) - clk_enable(s3c2410_wdtclk); - - /* put initial values into count and data */ - __raw_writel(0x80, S3C2410_WTCNT); - __raw_writel(0x80, S3C2410_WTDAT); - - /* set the watchdog to go and reset... */ - __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | - S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); - - /* wait for reset to assert... */ - mdelay(500); - - printk(KERN_ERR "Watchdog reset failed to assert reset\n"); - - /* delay to allow the serial port to show the message */ - mdelay(50); -} +#endif /* __PLAT_SAMSUNG_WATCHDOG_RESET_H */ diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c index 79d10fca909..a1f925f3121 100644 --- a/arch/arm/plat-samsung/init.c +++ b/arch/arm/plat-samsung/init.c @@ -11,14 +11,19 @@ * published by the Free Software Foundation. */ +/* + * NOTE: Code in this file is not used on S3C64xx when booting with + * Device Tree support. + */ + #include <linux/init.h> #include <linux/module.h> #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> - -#include <mach/hardware.h> +#include <linux/of.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -27,8 +32,6 @@ #include <plat/devs.h> #include <plat/clock.h> -#include <plat/regs-serial.h> - static struct cpu_table *cpu; static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode, @@ -55,12 +58,13 @@ void __init s3c_init_cpu(unsigned long idcode, printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode); - if (cpu->map_io == NULL || cpu->init == NULL) { + if (cpu->init == NULL) { printk(KERN_ERR "CPU %s support not enabled\n", cpu->name); panic("Unsupported Samsung CPU"); } - cpu->map_io(); + if (cpu->map_io) + cpu->map_io(); } /* s3c24xx_init_clocks @@ -87,10 +91,12 @@ void __init s3c24xx_init_clocks(int xtal) } /* uart management */ - +#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS) static int nr_uarts __initdata = 0; +#ifdef CONFIG_SERIAL_SAMSUNG_UARTS static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS]; +#endif /* s3c24xx_init_uartdevs * @@ -105,6 +111,7 @@ void __init s3c24xx_init_uartdevs(char *name, struct s3c24xx_uart_resources *res, struct s3c2410_uartcfg *cfg, int no) { +#ifdef CONFIG_SERIAL_SAMSUNG_UARTS struct platform_device *platdev; struct s3c2410_uartcfg *cfgptr = uart_cfgs; struct s3c24xx_uart_resources *resp; @@ -127,6 +134,7 @@ void __init s3c24xx_init_uartdevs(char *name, } nr_uarts = no; +#endif } void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) @@ -134,11 +142,12 @@ void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) if (cpu == NULL) return; - if (cpu->init_uarts == NULL) { + if (cpu->init_uarts == NULL && IS_ENABLED(CONFIG_SAMSUNG_ATAGS)) { printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n"); } else (cpu->init_uarts)(cfg, no); } +#endif static int __init s3c_arch_init(void) { @@ -146,14 +155,19 @@ static int __init s3c_arch_init(void) // do the correct init for cpu - if (cpu == NULL) + if (cpu == NULL) { + /* Not needed when booting with device tree. */ + if (of_have_populated_dt()) + return 0; panic("s3c_arch_init: NULL cpu\n"); + } ret = (cpu->init)(); if (ret != 0) return ret; - +#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS) ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts); +#endif return ret; } diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c deleted file mode 100644 index f980cf3d2ba..00000000000 --- a/arch/arm/plat-samsung/irq-vic-timer.c +++ /dev/null @@ -1,98 +0,0 @@ -/* arch/arm/plat-samsung/irq-vic-timer.c - * originally part of arch/arm/plat-s3c64xx/irq.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - Interrupt handling - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/io.h> - -#include <mach/map.h> -#include <plat/cpu.h> -#include <plat/irq-vic-timer.h> -#include <plat/regs-timer.h> - -#include <asm/mach/irq.h> - -static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) -{ - struct irq_chip *chip = irq_get_chip(irq); - chained_irq_enter(chip, desc); - generic_handle_irq((int)desc->irq_data.handler_data); - chained_irq_exit(chip, desc); -} - -/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ -static void s3c_irq_timer_ack(struct irq_data *d) -{ - struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 mask = (1 << 5) << (d->irq - gc->irq_base); - - irq_reg_writel(mask | gc->mask_cache, gc->reg_base); -} - -/** - * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\ - * @num: Number of timers to initialize - * @timer_irq: Base IRQ number to be used for the timers. - * - * Register the necessary IRQ chaining and support for the timer IRQs - * chained of the VIC. - */ -void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq) -{ - unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, - IRQ_TIMER3_VIC, IRQ_TIMER4_VIC }; - struct irq_chip_generic *s3c_tgc; - struct irq_chip_type *ct; - unsigned int i; - -#ifdef CONFIG_ARCH_EXYNOS - if (soc_is_exynos5250()) { - pirq[0] = EXYNOS5_IRQ_TIMER0_VIC; - pirq[1] = EXYNOS5_IRQ_TIMER1_VIC; - pirq[2] = EXYNOS5_IRQ_TIMER2_VIC; - pirq[3] = EXYNOS5_IRQ_TIMER3_VIC; - pirq[4] = EXYNOS5_IRQ_TIMER4_VIC; - } else { - pirq[0] = EXYNOS4_IRQ_TIMER0_VIC; - pirq[1] = EXYNOS4_IRQ_TIMER1_VIC; - pirq[2] = EXYNOS4_IRQ_TIMER2_VIC; - pirq[3] = EXYNOS4_IRQ_TIMER3_VIC; - pirq[4] = EXYNOS4_IRQ_TIMER4_VIC; - } -#endif - s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq, - S3C64XX_TINT_CSTAT, handle_level_irq); - - if (!s3c_tgc) { - pr_err("%s: irq_alloc_generic_chip for IRQ %d failed\n", - __func__, timer_irq); - return; - } - - ct = s3c_tgc->chip_types; - ct->chip.irq_mask = irq_gc_mask_clr_bit; - ct->chip.irq_unmask = irq_gc_mask_set_bit; - ct->chip.irq_ack = s3c_irq_timer_ack; - irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, - IRQ_NOREQUEST | IRQ_NOPROBE, 0); - /* Clear the upper bits of the mask_cache*/ - s3c_tgc->mask_cache &= 0x1f; - - for (i = 0; i < num; i++, timer_irq++) { - irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer); - irq_set_handler_data(pirq[i], (void *)timer_irq); - } -} diff --git a/arch/arm/plat-samsung/pm-check.c b/arch/arm/plat-samsung/pm-check.c index 3cbd62666b1..04aff2c31b4 100644 --- a/arch/arm/plat-samsung/pm-check.c +++ b/arch/arm/plat-samsung/pm-check.c @@ -19,7 +19,7 @@ #include <linux/ioport.h> #include <linux/slab.h> -#include <plat/pm.h> +#include <plat/pm-common.h> #if CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE < 1 #error CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE must be a positive non-zero value diff --git a/arch/arm/plat-samsung/pm-common.c b/arch/arm/plat-samsung/pm-common.c new file mode 100644 index 00000000000..515cd53372b --- /dev/null +++ b/arch/arm/plat-samsung/pm-common.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Tomasz Figa <t.figa@samsung.com> + * Copyright (C) 2008 Openmoko, Inc. + * Copyright (C) 2004-2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Samsung common power management helper functions. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/io.h> +#include <linux/kernel.h> + +#include <plat/pm-common.h> + +/* helper functions to save and restore register state */ + +/** + * s3c_pm_do_save() - save a set of registers for restoration on resume. + * @ptr: Pointer to an array of registers. + * @count: Size of the ptr array. + * + * Run through the list of registers given, saving their contents in the + * array for later restoration when we wakeup. + */ +void s3c_pm_do_save(struct sleep_save *ptr, int count) +{ + for (; count > 0; count--, ptr++) { + ptr->val = __raw_readl(ptr->reg); + S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val); + } +} + +/** + * s3c_pm_do_restore() - restore register values from the save list. + * @ptr: Pointer to an array of registers. + * @count: Size of the ptr array. + * + * Restore the register values saved from s3c_pm_do_save(). + * + * Note, we do not use S3C_PMDBG() in here, as the system may not have + * restore the UARTs state yet +*/ + +void s3c_pm_do_restore(const struct sleep_save *ptr, int count) +{ + for (; count > 0; count--, ptr++) { + pr_debug("restore %p (restore %08lx, was %08x)\n", + ptr->reg, ptr->val, __raw_readl(ptr->reg)); + + __raw_writel(ptr->val, ptr->reg); + } +} + +/** + * s3c_pm_do_restore_core() - early restore register values from save list. + * + * This is similar to s3c_pm_do_restore() except we try and minimise the + * side effects of the function in case registers that hardware might need + * to work has been restored. + * + * WARNING: Do not put any debug in here that may effect memory or use + * peripherals, as things may be changing! +*/ + +void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count) +{ + for (; count > 0; count--, ptr++) + __raw_writel(ptr->val, ptr->reg); +} diff --git a/arch/arm/plat-samsung/pm-debug.c b/arch/arm/plat-samsung/pm-debug.c new file mode 100644 index 00000000000..8f19f66388d --- /dev/null +++ b/arch/arm/plat-samsung/pm-debug.c @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Tomasz Figa <t.figa@samsung.com> + * Copyright (C) 2008 Openmoko, Inc. + * Copyright (C) 2004-2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Samsung common power management (suspend to RAM) debug support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/serial_core.h> +#include <linux/io.h> + +#include <asm/mach/map.h> + +#include <plat/cpu.h> +#include <plat/pm-common.h> + +#ifdef CONFIG_SAMSUNG_ATAGS +#include <mach/pm-core.h> +#else +static inline void s3c_pm_debug_init_uart(void) {} +static inline void s3c_pm_arch_update_uart(void __iomem *regs, + struct pm_uart_save *save) {} +#endif + +static struct pm_uart_save uart_save; + +extern void printascii(const char *); + +void s3c_pm_dbg(const char *fmt, ...) +{ + va_list va; + char buff[256]; + + va_start(va, fmt); + vsnprintf(buff, sizeof(buff), fmt, va); + va_end(va); + + printascii(buff); +} + +void s3c_pm_debug_init(void) +{ + /* restart uart clocks so we can use them to output */ + s3c_pm_debug_init_uart(); +} + +static inline void __iomem *s3c_pm_uart_base(void) +{ + unsigned long paddr; + unsigned long vaddr; + + debug_ll_addr(&paddr, &vaddr); + + return (void __iomem *)vaddr; +} + +void s3c_pm_save_uarts(void) +{ + void __iomem *regs = s3c_pm_uart_base(); + struct pm_uart_save *save = &uart_save; + + save->ulcon = __raw_readl(regs + S3C2410_ULCON); + save->ucon = __raw_readl(regs + S3C2410_UCON); + save->ufcon = __raw_readl(regs + S3C2410_UFCON); + save->umcon = __raw_readl(regs + S3C2410_UMCON); + save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); + + if (!soc_is_s3c2410()) + save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); + + S3C_PMDBG("UART[%p]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n", + regs, save->ulcon, save->ucon, save->ufcon, save->ubrdiv); +} + +void s3c_pm_restore_uarts(void) +{ + void __iomem *regs = s3c_pm_uart_base(); + struct pm_uart_save *save = &uart_save; + + s3c_pm_arch_update_uart(regs, save); + + __raw_writel(save->ulcon, regs + S3C2410_ULCON); + __raw_writel(save->ucon, regs + S3C2410_UCON); + __raw_writel(save->ufcon, regs + S3C2410_UFCON); + __raw_writel(save->umcon, regs + S3C2410_UMCON); + __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV); + + if (!soc_is_s3c2410()) + __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT); +} diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index c2ff92c30bd..da268813901 100644 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c @@ -19,6 +19,10 @@ #include <linux/io.h> #include <linux/gpio.h> +#if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX) +#include <mach/gpio-samsung.h> +#endif + #include <plat/gpio-core.h> #include <plat/pm.h> diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 002b1472293..f8c0f9797dc 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -16,17 +16,22 @@ #include <linux/suspend.h> #include <linux/errno.h> #include <linux/delay.h> -#include <linux/serial_core.h> +#include <linux/of.h> +#include <linux/serial_s3c.h> #include <linux/io.h> #include <asm/cacheflush.h> #include <asm/suspend.h> -#include <mach/hardware.h> -#include <mach/map.h> -#include <plat/regs-serial.h> +#ifdef CONFIG_SAMSUNG_ATAGS +#include <mach/map.h> +#ifndef CONFIG_ARCH_EXYNOS #include <mach/regs-clock.h> #include <mach/regs-irq.h> +#endif +#include <mach/irqs.h> +#endif + #include <asm/irq.h> #include <plat/pm.h> @@ -36,101 +41,6 @@ unsigned long s3c_pm_flags; -/* Debug code: - * - * This code supports debug output to the low level UARTs for use on - * resume before the console layer is available. -*/ - -#ifdef CONFIG_SAMSUNG_PM_DEBUG -extern void printascii(const char *); - -void s3c_pm_dbg(const char *fmt, ...) -{ - va_list va; - char buff[256]; - - va_start(va, fmt); - vsnprintf(buff, sizeof(buff), fmt, va); - va_end(va); - - printascii(buff); -} - -static inline void s3c_pm_debug_init(void) -{ - /* restart uart clocks so we can use them to output */ - s3c_pm_debug_init_uart(); -} - -#else -#define s3c_pm_debug_init() do { } while(0) - -#endif /* CONFIG_SAMSUNG_PM_DEBUG */ - -/* Save the UART configurations if we are configured for debug. */ - -unsigned char pm_uart_udivslot; - -#ifdef CONFIG_SAMSUNG_PM_DEBUG - -static struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; - -static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save) -{ - void __iomem *regs = S3C_VA_UARTx(uart); - - save->ulcon = __raw_readl(regs + S3C2410_ULCON); - save->ucon = __raw_readl(regs + S3C2410_UCON); - save->ufcon = __raw_readl(regs + S3C2410_UFCON); - save->umcon = __raw_readl(regs + S3C2410_UMCON); - save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); - - if (pm_uart_udivslot) - save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); - - S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n", - uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv); -} - -static void s3c_pm_save_uarts(void) -{ - struct pm_uart_save *save = uart_save; - unsigned int uart; - - for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++) - s3c_pm_save_uart(uart, save); -} - -static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save) -{ - void __iomem *regs = S3C_VA_UARTx(uart); - - s3c_pm_arch_update_uart(regs, save); - - __raw_writel(save->ulcon, regs + S3C2410_ULCON); - __raw_writel(save->ucon, regs + S3C2410_UCON); - __raw_writel(save->ufcon, regs + S3C2410_UFCON); - __raw_writel(save->umcon, regs + S3C2410_UMCON); - __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV); - - if (pm_uart_udivslot) - __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT); -} - -static void s3c_pm_restore_uarts(void) -{ - struct pm_uart_save *save = uart_save; - unsigned int uart; - - for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++) - s3c_pm_restore_uart(uart, save); -} -#else -static void s3c_pm_save_uarts(void) { } -static void s3c_pm_restore_uarts(void) { } -#endif - /* The IRQ ext-int code goes here, it is too small to currently bother * with its own file. */ @@ -155,62 +65,6 @@ int s3c_irqext_wake(struct irq_data *data, unsigned int state) return 0; } -/* helper functions to save and restore register state */ - -/** - * s3c_pm_do_save() - save a set of registers for restoration on resume. - * @ptr: Pointer to an array of registers. - * @count: Size of the ptr array. - * - * Run through the list of registers given, saving their contents in the - * array for later restoration when we wakeup. - */ -void s3c_pm_do_save(struct sleep_save *ptr, int count) -{ - for (; count > 0; count--, ptr++) { - ptr->val = __raw_readl(ptr->reg); - S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val); - } -} - -/** - * s3c_pm_do_restore() - restore register values from the save list. - * @ptr: Pointer to an array of registers. - * @count: Size of the ptr array. - * - * Restore the register values saved from s3c_pm_do_save(). - * - * Note, we do not use S3C_PMDBG() in here, as the system may not have - * restore the UARTs state yet -*/ - -void s3c_pm_do_restore(struct sleep_save *ptr, int count) -{ - for (; count > 0; count--, ptr++) { - printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", - ptr->reg, ptr->val, __raw_readl(ptr->reg)); - - __raw_writel(ptr->val, ptr->reg); - } -} - -/** - * s3c_pm_do_restore_core() - early restore register values from save list. - * - * This is similar to s3c_pm_do_restore() except we try and minimise the - * side effects of the function in case registers that hardware might need - * to work has been restored. - * - * WARNING: Do not put any debug in here that may effect memory or use - * peripherals, as things may be changing! -*/ - -void s3c_pm_do_restore_core(struct sleep_save *ptr, int count) -{ - for (; count > 0; count--, ptr++) - __raw_writel(ptr->val, ptr->reg); -} - /* s3c2410_pm_show_resume_irqs * * print any IRQs asserted at resume time (ie, we woke from) @@ -260,7 +114,8 @@ static int s3c_pm_enter(suspend_state_t state) * require a full power-cycle) */ - if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && + if (!of_have_populated_dt() && + !any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) { printk(KERN_ERR "%s: No wake-up sources!\n", __func__); printk(KERN_ERR "%s: Aborting sleep\n", __func__); @@ -269,8 +124,11 @@ static int s3c_pm_enter(suspend_state_t state) /* save all necessary core registers not covered by the drivers */ - samsung_pm_save_gpios(); - samsung_pm_saved_gpios(); + if (!of_have_populated_dt()) { + samsung_pm_save_gpios(); + samsung_pm_saved_gpios(); + } + s3c_pm_save_uarts(); s3c_pm_save_core(); @@ -309,8 +167,11 @@ static int s3c_pm_enter(suspend_state_t state) s3c_pm_restore_core(); s3c_pm_restore_uarts(); - samsung_pm_restore_gpios(); - s3c_pm_restored_gpios(); + + if (!of_have_populated_dt()) { + samsung_pm_restore_gpios(); + s3c_pm_restored_gpios(); + } s3c_pm_debug_init(); diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c deleted file mode 100644 index a35ff3bcffe..00000000000 --- a/arch/arm/plat-samsung/pwm-clock.c +++ /dev/null @@ -1,474 +0,0 @@ -/* linux/arch/arm/plat-s3c24xx/pwm-clock.c - * - * Copyright (c) 2007 Simtec Electronics - * Copyright (c) 2007, 2008 Ben Dooks - * Ben Dooks <ben-linux@fluff.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/log2.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/map.h> -#include <asm/irq.h> - -#include <plat/clock.h> -#include <plat/cpu.h> - -#include <plat/regs-timer.h> -#include <plat/pwm-clock.h> - -/* Each of the timers 0 through 5 go through the following - * clock tree, with the inputs depending on the timers. - * - * pclk ---- [ prescaler 0 ] -+---> timer 0 - * +---> timer 1 - * - * pclk ---- [ prescaler 1 ] -+---> timer 2 - * +---> timer 3 - * \---> timer 4 - * - * Which are fed into the timers as so: - * - * prescaled 0 ---- [ div 2,4,8,16 ] ---\ - * [mux] -> timer 0 - * tclk 0 ------------------------------/ - * - * prescaled 0 ---- [ div 2,4,8,16 ] ---\ - * [mux] -> timer 1 - * tclk 0 ------------------------------/ - * - * - * prescaled 1 ---- [ div 2,4,8,16 ] ---\ - * [mux] -> timer 2 - * tclk 1 ------------------------------/ - * - * prescaled 1 ---- [ div 2,4,8,16 ] ---\ - * [mux] -> timer 3 - * tclk 1 ------------------------------/ - * - * prescaled 1 ---- [ div 2,4,8, 16 ] --\ - * [mux] -> timer 4 - * tclk 1 ------------------------------/ - * - * Since the mux and the divider are tied together in the - * same register space, it is impossible to set the parent - * and the rate at the same time. To avoid this, we add an - * intermediate 'prescaled-and-divided' clock to select - * as the parent for the timer input clock called tdiv. - * - * prescaled clk --> pwm-tdiv ---\ - * [ mux ] --> timer X - * tclk -------------------------/ -*/ - -static struct clk clk_timer_scaler[]; - -static unsigned long clk_pwm_scaler_get_rate(struct clk *clk) -{ - unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0); - - if (clk == &clk_timer_scaler[1]) { - tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK; - tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT; - } else { - tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK; - } - - return clk_get_rate(clk->parent) / (tcfg0 + 1); -} - -static unsigned long clk_pwm_scaler_round_rate(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long divisor = parent_rate / rate; - - if (divisor > 256) - divisor = 256; - else if (divisor < 2) - divisor = 2; - - return parent_rate / divisor; -} - -static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long round = clk_pwm_scaler_round_rate(clk, rate); - unsigned long tcfg0; - unsigned long divisor; - unsigned long flags; - - divisor = clk_get_rate(clk->parent) / round; - divisor--; - - local_irq_save(flags); - tcfg0 = __raw_readl(S3C2410_TCFG0); - - if (clk == &clk_timer_scaler[1]) { - tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK; - tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT; - } else { - tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK; - tcfg0 |= divisor; - } - - __raw_writel(tcfg0, S3C2410_TCFG0); - local_irq_restore(flags); - - return 0; -} - -static struct clk_ops clk_pwm_scaler_ops = { - .get_rate = clk_pwm_scaler_get_rate, - .set_rate = clk_pwm_scaler_set_rate, - .round_rate = clk_pwm_scaler_round_rate, -}; - -static struct clk clk_timer_scaler[] = { - [0] = { - .name = "pwm-scaler0", - .id = -1, - .ops = &clk_pwm_scaler_ops, - }, - [1] = { - .name = "pwm-scaler1", - .id = -1, - .ops = &clk_pwm_scaler_ops, - }, -}; - -static struct clk clk_timer_tclk[] = { - [0] = { - .name = "pwm-tclk0", - .id = -1, - }, - [1] = { - .name = "pwm-tclk1", - .id = -1, - }, -}; - -struct pwm_tdiv_clk { - struct clk clk; - unsigned int divisor; -}; - -static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk) -{ - return container_of(clk, struct pwm_tdiv_clk, clk); -} - -static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk) -{ - unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); - unsigned int divisor; - - tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id); - tcfg1 &= S3C2410_TCFG1_MUX_MASK; - - if (pwm_cfg_src_is_tclk(tcfg1)) - divisor = to_tdiv(clk)->divisor; - else - divisor = tcfg_to_divisor(tcfg1); - - return clk_get_rate(clk->parent) / divisor; -} - -static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate; - unsigned long divisor; - - parent_rate = clk_get_rate(clk->parent); - divisor = parent_rate / rate; - - if (divisor <= 1 && pwm_tdiv_has_div1()) - divisor = 1; - else if (divisor <= 2) - divisor = 2; - else if (divisor <= 4) - divisor = 4; - else if (divisor <= 8) - divisor = 8; - else - divisor = 16; - - return parent_rate / divisor; -} - -static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk) -{ - return pwm_tdiv_div_bits(divclk->divisor); -} - -static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk) -{ - unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); - unsigned long bits = clk_pwm_tdiv_bits(divclk); - unsigned long flags; - unsigned long shift = S3C2410_TCFG1_SHIFT(divclk->clk.id); - - local_irq_save(flags); - - tcfg1 = __raw_readl(S3C2410_TCFG1); - tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift); - tcfg1 |= bits << shift; - __raw_writel(tcfg1, S3C2410_TCFG1); - - local_irq_restore(flags); -} - -static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate) -{ - struct pwm_tdiv_clk *divclk = to_tdiv(clk); - unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long divisor; - - tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id); - tcfg1 &= S3C2410_TCFG1_MUX_MASK; - - rate = clk_round_rate(clk, rate); - divisor = parent_rate / rate; - - if (divisor > 16) - return -EINVAL; - - divclk->divisor = divisor; - - /* Update the current MUX settings if we are currently - * selected as the clock source for this clock. */ - - if (!pwm_cfg_src_is_tclk(tcfg1)) - clk_pwm_tdiv_update(divclk); - - return 0; -} - -static struct clk_ops clk_tdiv_ops = { - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, -}; - -static struct pwm_tdiv_clk clk_timer_tdiv[] = { - [0] = { - .clk = { - .name = "pwm-tdiv", - .devname = "s3c24xx-pwm.0", - .ops = &clk_tdiv_ops, - .parent = &clk_timer_scaler[0], - }, - }, - [1] = { - .clk = { - .name = "pwm-tdiv", - .devname = "s3c24xx-pwm.1", - .ops = &clk_tdiv_ops, - .parent = &clk_timer_scaler[0], - } - }, - [2] = { - .clk = { - .name = "pwm-tdiv", - .devname = "s3c24xx-pwm.2", - .ops = &clk_tdiv_ops, - .parent = &clk_timer_scaler[1], - }, - }, - [3] = { - .clk = { - .name = "pwm-tdiv", - .devname = "s3c24xx-pwm.3", - .ops = &clk_tdiv_ops, - .parent = &clk_timer_scaler[1], - }, - }, - [4] = { - .clk = { - .name = "pwm-tdiv", - .devname = "s3c24xx-pwm.4", - .ops = &clk_tdiv_ops, - .parent = &clk_timer_scaler[1], - }, - }, -}; - -static int __init clk_pwm_tdiv_register(unsigned int id) -{ - struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id]; - unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); - - tcfg1 >>= S3C2410_TCFG1_SHIFT(id); - tcfg1 &= S3C2410_TCFG1_MUX_MASK; - - divclk->clk.id = id; - divclk->divisor = tcfg_to_divisor(tcfg1); - - return s3c24xx_register_clock(&divclk->clk); -} - -static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id) -{ - return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0]; -} - -static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id) -{ - return &clk_timer_tdiv[id].clk; -} - -static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent) -{ - unsigned int id = clk->id; - unsigned long tcfg1; - unsigned long flags; - unsigned long bits; - unsigned long shift = S3C2410_TCFG1_SHIFT(id); - - unsigned long mux_tclk; - - if (soc_is_s3c24xx()) - mux_tclk = S3C2410_TCFG1_MUX_TCLK; - else if (soc_is_s5p6440() || soc_is_s5p6450()) - mux_tclk = 0; - else - mux_tclk = S3C64XX_TCFG1_MUX_TCLK; - - if (parent == s3c24xx_pwmclk_tclk(id)) - bits = mux_tclk << shift; - else if (parent == s3c24xx_pwmclk_tdiv(id)) - bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift; - else - return -EINVAL; - - clk->parent = parent; - - local_irq_save(flags); - - tcfg1 = __raw_readl(S3C2410_TCFG1); - tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift); - __raw_writel(tcfg1 | bits, S3C2410_TCFG1); - - local_irq_restore(flags); - - return 0; -} - -static struct clk_ops clk_tin_ops = { - .set_parent = clk_pwm_tin_set_parent, -}; - -static struct clk clk_tin[] = { - [0] = { - .name = "pwm-tin", - .devname = "s3c24xx-pwm.0", - .id = 0, - .ops = &clk_tin_ops, - }, - [1] = { - .name = "pwm-tin", - .devname = "s3c24xx-pwm.1", - .id = 1, - .ops = &clk_tin_ops, - }, - [2] = { - .name = "pwm-tin", - .devname = "s3c24xx-pwm.2", - .id = 2, - .ops = &clk_tin_ops, - }, - [3] = { - .name = "pwm-tin", - .devname = "s3c24xx-pwm.3", - .id = 3, - .ops = &clk_tin_ops, - }, - [4] = { - .name = "pwm-tin", - .devname = "s3c24xx-pwm.4", - .id = 4, - .ops = &clk_tin_ops, - }, -}; - -static __init int clk_pwm_tin_register(struct clk *pwm) -{ - unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); - unsigned int id = pwm->id; - - struct clk *parent; - int ret; - - ret = s3c24xx_register_clock(pwm); - if (ret < 0) - return ret; - - tcfg1 >>= S3C2410_TCFG1_SHIFT(id); - tcfg1 &= S3C2410_TCFG1_MUX_MASK; - - if (pwm_cfg_src_is_tclk(tcfg1)) - parent = s3c24xx_pwmclk_tclk(id); - else - parent = s3c24xx_pwmclk_tdiv(id); - - return clk_set_parent(pwm, parent); -} - -/** - * s3c_pwmclk_init() - initialise pwm clocks - * - * Initialise and register the clocks which provide the inputs for the - * pwm timer blocks. - * - * Note, this call is required by the time core, so must be called after - * the base clocks are added and before any of the initcalls are run. - */ -__init void s3c_pwmclk_init(void) -{ - struct clk *clk_timers; - unsigned int clk; - int ret; - - clk_timers = clk_get(NULL, "timers"); - if (IS_ERR(clk_timers)) { - printk(KERN_ERR "%s: no parent clock\n", __func__); - return; - } - - for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) - clk_timer_scaler[clk].parent = clk_timers; - - s3c_register_clocks(clk_timer_scaler, ARRAY_SIZE(clk_timer_scaler)); - s3c_register_clocks(clk_timer_tclk, ARRAY_SIZE(clk_timer_tclk)); - - for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) { - ret = clk_pwm_tdiv_register(clk); - - if (ret < 0) { - printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk); - return; - } - } - - for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) { - ret = clk_pwm_tin_register(&clk_tin[clk]); - if (ret < 0) { - printk(KERN_ERR "error adding pwm%d tin clock\n", clk); - return; - } - } -} diff --git a/arch/arm/plat-samsung/s3c-dma-ops.c b/arch/arm/plat-samsung/s3c-dma-ops.c index 0cc40aea3f5..98b10ba67dc 100644 --- a/arch/arm/plat-samsung/s3c-dma-ops.c +++ b/arch/arm/plat-samsung/s3c-dma-ops.c @@ -82,7 +82,8 @@ static int s3c_dma_config(unsigned ch, struct samsung_dma_config *param) static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep *param) { struct cb_data *data; - int len = (param->cap == DMA_CYCLIC) ? param->period : param->len; + dma_addr_t pos = param->buf; + dma_addr_t end = param->buf + param->len; list_for_each_entry(data, &dma_list, node) if (data->ch == ch) @@ -94,7 +95,15 @@ static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep *param) data->fp_param = param->fp_param; } - s3c2410_dma_enqueue(ch, (void *)data, param->buf, len); + if (param->cap != DMA_CYCLIC) { + s3c2410_dma_enqueue(ch, (void *)data, param->buf, param->len); + return 0; + } + + while (pos < end) { + s3c2410_dma_enqueue(ch, (void *)data, pos, param->period); + pos += param->period; + } return 0; } diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c index 5ec104b5408..469b86260fe 100644 --- a/arch/arm/plat-samsung/s5p-dev-mfc.c +++ b/arch/arm/plat-samsung/s5p-dev-mfc.c @@ -17,10 +17,56 @@ #include <linux/of_fdt.h> #include <linux/of.h> +#include <plat/mfc.h> + +#ifdef CONFIG_SAMSUNG_ATAGS #include <mach/map.h> +#include <mach/irqs.h> #include <plat/devs.h> -#include <plat/irqs.h> -#include <plat/mfc.h> + +static struct resource s5p_mfc_resource[] = { + [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K), + [1] = DEFINE_RES_IRQ(IRQ_MFC), +}; + +struct platform_device s5p_device_mfc = { + .name = "s5p-mfc", + .id = -1, + .num_resources = ARRAY_SIZE(s5p_mfc_resource), + .resource = s5p_mfc_resource, +}; + +/* + * MFC hardware has 2 memory interfaces which are modelled as two separate + * platform devices to let dma-mapping distinguish between them. + * + * MFC parent device (s5p_device_mfc) must be registered before memory + * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r). + */ + +struct platform_device s5p_device_mfc_l = { + .name = "s5p-mfc-l", + .id = -1, + .dev = { + .parent = &s5p_device_mfc.dev, + .dma_mask = &s5p_device_mfc_l.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct platform_device s5p_device_mfc_r = { + .name = "s5p-mfc-r", + .id = -1, + .dev = { + .parent = &s5p_device_mfc.dev, + .dma_mask = &s5p_device_mfc_r.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; +#else +static struct platform_device s5p_device_mfc_l; +static struct platform_device s5p_device_mfc_r; +#endif struct s5p_mfc_reserved_mem { phys_addr_t base; @@ -30,6 +76,7 @@ struct s5p_mfc_reserved_mem { static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata; + void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, phys_addr_t lbase, unsigned int lsize) { @@ -53,6 +100,7 @@ void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, } } +#ifdef CONFIG_SAMSUNG_ATAGS static int __init s5p_mfc_memory_init(void) { int i; @@ -71,34 +119,38 @@ static int __init s5p_mfc_memory_init(void) return 0; } device_initcall(s5p_mfc_memory_init); +#endif #ifdef CONFIG_OF -int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname, +int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname, int depth, void *data) { - __be32 *prop; - unsigned long len; - struct s5p_mfc_dt_meminfo *mfc_mem = data; + const __be32 *prop; + int len; + struct s5p_mfc_dt_meminfo mfc_mem; if (!data) return 0; - if (!of_flat_dt_is_compatible(node, mfc_mem->compatible)) + if (!of_flat_dt_is_compatible(node, data)) return 0; prop = of_get_flat_dt_prop(node, "samsung,mfc-l", &len); if (!prop || (len != 2 * sizeof(unsigned long))) return 0; - mfc_mem->loff = be32_to_cpu(prop[0]); - mfc_mem->lsize = be32_to_cpu(prop[1]); + mfc_mem.loff = be32_to_cpu(prop[0]); + mfc_mem.lsize = be32_to_cpu(prop[1]); prop = of_get_flat_dt_prop(node, "samsung,mfc-r", &len); if (!prop || (len != 2 * sizeof(unsigned long))) return 0; - mfc_mem->roff = be32_to_cpu(prop[0]); - mfc_mem->rsize = be32_to_cpu(prop[1]); + mfc_mem.roff = be32_to_cpu(prop[0]); + mfc_mem.rsize = be32_to_cpu(prop[1]); + + s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, + mfc_mem.loff, mfc_mem.lsize); return 1; } diff --git a/arch/arm/plat-samsung/s5p-dev-uart.c b/arch/arm/plat-samsung/s5p-dev-uart.c index cafa3deddcc..8c4487af98c 100644 --- a/arch/arm/plat-samsung/s5p-dev-uart.c +++ b/arch/arm/plat-samsung/s5p-dev-uart.c @@ -18,7 +18,6 @@ #include <asm/mach/arch.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> #include <mach/map.h> #include <plat/devs.h> diff --git a/arch/arm/plat-samsung/s5p-irq-eint.c b/arch/arm/plat-samsung/s5p-irq-eint.c index faa65160278..ebee4dc11a9 100644 --- a/arch/arm/plat-samsung/s5p-irq-eint.c +++ b/arch/arm/plat-samsung/s5p-irq-eint.c @@ -16,6 +16,7 @@ #include <linux/device.h> #include <linux/gpio.h> #include <linux/irqchip/arm-vic.h> +#include <linux/of.h> #include <plat/regs-irqtype.h> @@ -202,6 +203,9 @@ static int __init s5p_init_irq_eint(void) { int irq; + if (of_have_populated_dt()) + return -ENODEV; + for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) irq_set_chip(irq, &s5p_irq_vic_eint); diff --git a/arch/arm/plat-samsung/s5p-irq-gpioint.c b/arch/arm/plat-samsung/s5p-irq-gpioint.c index bae56131a50..fafdb059043 100644 --- a/arch/arm/plat-samsung/s5p-irq-gpioint.c +++ b/arch/arm/plat-samsung/s5p-irq-gpioint.c @@ -14,6 +14,7 @@ #include <linux/kernel.h> #include <linux/interrupt.h> #include <linux/irq.h> +#include <linux/irqchip/chained_irq.h> #include <linux/io.h> #include <linux/gpio.h> #include <linux/slab.h> @@ -22,8 +23,6 @@ #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> -#include <asm/mach/irq.h> - #define GPIO_BASE(chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u)) #define CON_OFFSET 0x700 diff --git a/arch/arm/plat-samsung/s5p-irq-pm.c b/arch/arm/plat-samsung/s5p-irq-pm.c index 7c1e3b7072f..52b16943617 100644 --- a/arch/arm/plat-samsung/s5p-irq-pm.c +++ b/arch/arm/plat-samsung/s5p-irq-pm.c @@ -40,18 +40,8 @@ int s3c_irq_wake(struct irq_data *data, unsigned int state) unsigned long irqbit; unsigned int irq_rtc_tic, irq_rtc_alarm; -#ifdef CONFIG_ARCH_EXYNOS - if (soc_is_exynos5250()) { - irq_rtc_tic = EXYNOS5_IRQ_RTC_TIC; - irq_rtc_alarm = EXYNOS5_IRQ_RTC_ALARM; - } else { - irq_rtc_tic = EXYNOS4_IRQ_RTC_TIC; - irq_rtc_alarm = EXYNOS4_IRQ_RTC_ALARM; - } -#else irq_rtc_tic = IRQ_RTC_TIC; irq_rtc_alarm = IRQ_RTC_ALARM; -#endif if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) { irqbit = 1 << (data->irq + 1 - irq_rtc_alarm); diff --git a/arch/arm/plat-samsung/s5p-irq.c b/arch/arm/plat-samsung/s5p-irq.c index 103e371f5e3..ddfaca9c79d 100644 --- a/arch/arm/plat-samsung/s5p-irq.c +++ b/arch/arm/plat-samsung/s5p-irq.c @@ -15,10 +15,9 @@ #include <linux/io.h> #include <linux/irqchip/arm-vic.h> +#include <mach/irqs.h> #include <mach/map.h> -#include <plat/regs-timer.h> #include <plat/cpu.h> -#include <plat/irq-vic-timer.h> void __init s5p_init_irq(u32 *vic, u32 num_vic) { @@ -29,6 +28,4 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic) for (irq = 0; irq < num_vic; irq++) vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0); #endif - - s3c_init_vic_timer_irq(5, IRQ_TIMER0); } diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S index bdf6dadf879..25c68ceb9e2 100644 --- a/arch/arm/plat-samsung/s5p-sleep.S +++ b/arch/arm/plat-samsung/s5p-sleep.S @@ -22,16 +22,7 @@ */ #include <linux/linkage.h> -#include <asm/asm-offsets.h> -#include <asm/hardware/cache-l2x0.h> -/* - * The following code is located into the .data section. This is to - * allow l2x0_regs_phys to be accessed with a relative load while we - * can't rely on any MMU translation. We could have put l2x0_regs_phys - * in the .text section as well, but some setups might insist on it to - * be truly read-only. (Reference from: arch/arm/kernel/sleep.S) - */ .data .align @@ -50,31 +41,5 @@ */ ENTRY(s3c_cpu_resume) -#ifdef CONFIG_CACHE_L2X0 - adr r0, l2x0_regs_phys - ldr r0, [r0] - ldr r1, [r0, #L2X0_R_PHY_BASE] - ldr r2, [r1, #L2X0_CTRL] - tst r2, #0x1 - bne resume_l2on - ldr r2, [r0, #L2X0_R_AUX_CTRL] - str r2, [r1, #L2X0_AUX_CTRL] - ldr r2, [r0, #L2X0_R_TAG_LATENCY] - str r2, [r1, #L2X0_TAG_LATENCY_CTRL] - ldr r2, [r0, #L2X0_R_DATA_LATENCY] - str r2, [r1, #L2X0_DATA_LATENCY_CTRL] - ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] - str r2, [r1, #L2X0_PREFETCH_CTRL] - ldr r2, [r0, #L2X0_R_PWR_CTRL] - str r2, [r1, #L2X0_POWER_CTRL] - mov r2, #1 - str r2, [r1, #L2X0_CTRL] -resume_l2on: -#endif b cpu_resume ENDPROC(s3c_cpu_resume) -#ifdef CONFIG_CACHE_L2X0 - .globl l2x0_regs_phys -l2x0_regs_phys: - .long 0 -#endif diff --git a/arch/arm/plat-samsung/s5p-time.c b/arch/arm/plat-samsung/s5p-time.c deleted file mode 100644 index e92510cf82e..00000000000 --- a/arch/arm/plat-samsung/s5p-time.c +++ /dev/null @@ -1,394 +0,0 @@ -/* - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5P - Common hr-timer support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/clockchips.h> -#include <linux/platform_device.h> - -#include <asm/smp_twd.h> -#include <asm/mach/time.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/sched_clock.h> - -#include <mach/map.h> -#include <plat/devs.h> -#include <plat/regs-timer.h> -#include <plat/s5p-time.h> - -static struct clk *tin_event; -static struct clk *tin_source; -static struct clk *tdiv_event; -static struct clk *tdiv_source; -static struct clk *timerclk; -static struct s5p_timer_source timer_source; -static unsigned long clock_count_per_tick; -static void s5p_timer_resume(void); - -static void s5p_time_stop(enum s5p_timer_mode mode) -{ - unsigned long tcon; - - tcon = __raw_readl(S3C2410_TCON); - - switch (mode) { - case S5P_PWM0: - tcon &= ~S3C2410_TCON_T0START; - break; - - case S5P_PWM1: - tcon &= ~S3C2410_TCON_T1START; - break; - - case S5P_PWM2: - tcon &= ~S3C2410_TCON_T2START; - break; - - case S5P_PWM3: - tcon &= ~S3C2410_TCON_T3START; - break; - - case S5P_PWM4: - tcon &= ~S3C2410_TCON_T4START; - break; - - default: - printk(KERN_ERR "Invalid Timer %d\n", mode); - break; - } - __raw_writel(tcon, S3C2410_TCON); -} - -static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt) -{ - unsigned long tcon; - - tcon = __raw_readl(S3C2410_TCON); - - tcnt--; - - switch (mode) { - case S5P_PWM0: - tcon &= ~(0x0f << 0); - tcon |= S3C2410_TCON_T0MANUALUPD; - break; - - case S5P_PWM1: - tcon &= ~(0x0f << 8); - tcon |= S3C2410_TCON_T1MANUALUPD; - break; - - case S5P_PWM2: - tcon &= ~(0x0f << 12); - tcon |= S3C2410_TCON_T2MANUALUPD; - break; - - case S5P_PWM3: - tcon &= ~(0x0f << 16); - tcon |= S3C2410_TCON_T3MANUALUPD; - break; - - case S5P_PWM4: - tcon &= ~(0x07 << 20); - tcon |= S3C2410_TCON_T4MANUALUPD; - break; - - default: - printk(KERN_ERR "Invalid Timer %d\n", mode); - break; - } - - __raw_writel(tcnt, S3C2410_TCNTB(mode)); - __raw_writel(tcnt, S3C2410_TCMPB(mode)); - __raw_writel(tcon, S3C2410_TCON); -} - -static void s5p_time_start(enum s5p_timer_mode mode, bool periodic) -{ - unsigned long tcon; - - tcon = __raw_readl(S3C2410_TCON); - - switch (mode) { - case S5P_PWM0: - tcon |= S3C2410_TCON_T0START; - tcon &= ~S3C2410_TCON_T0MANUALUPD; - - if (periodic) - tcon |= S3C2410_TCON_T0RELOAD; - else - tcon &= ~S3C2410_TCON_T0RELOAD; - break; - - case S5P_PWM1: - tcon |= S3C2410_TCON_T1START; - tcon &= ~S3C2410_TCON_T1MANUALUPD; - - if (periodic) - tcon |= S3C2410_TCON_T1RELOAD; - else - tcon &= ~S3C2410_TCON_T1RELOAD; - break; - - case S5P_PWM2: - tcon |= S3C2410_TCON_T2START; - tcon &= ~S3C2410_TCON_T2MANUALUPD; - - if (periodic) - tcon |= S3C2410_TCON_T2RELOAD; - else - tcon &= ~S3C2410_TCON_T2RELOAD; - break; - - case S5P_PWM3: - tcon |= S3C2410_TCON_T3START; - tcon &= ~S3C2410_TCON_T3MANUALUPD; - - if (periodic) - tcon |= S3C2410_TCON_T3RELOAD; - else - tcon &= ~S3C2410_TCON_T3RELOAD; - break; - - case S5P_PWM4: - tcon |= S3C2410_TCON_T4START; - tcon &= ~S3C2410_TCON_T4MANUALUPD; - - if (periodic) - tcon |= S3C2410_TCON_T4RELOAD; - else - tcon &= ~S3C2410_TCON_T4RELOAD; - break; - - default: - printk(KERN_ERR "Invalid Timer %d\n", mode); - break; - } - __raw_writel(tcon, S3C2410_TCON); -} - -static int s5p_set_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - s5p_time_setup(timer_source.event_id, cycles); - s5p_time_start(timer_source.event_id, NON_PERIODIC); - - return 0; -} - -static void s5p_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - s5p_time_stop(timer_source.event_id); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - s5p_time_setup(timer_source.event_id, clock_count_per_tick); - s5p_time_start(timer_source.event_id, PERIODIC); - break; - - case CLOCK_EVT_MODE_ONESHOT: - break; - - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - break; - - case CLOCK_EVT_MODE_RESUME: - s5p_timer_resume(); - break; - } -} - -static void s5p_timer_resume(void) -{ - /* event timer restart */ - s5p_time_setup(timer_source.event_id, clock_count_per_tick); - s5p_time_start(timer_source.event_id, PERIODIC); - - /* source timer restart */ - s5p_time_setup(timer_source.source_id, TCNT_MAX); - s5p_time_start(timer_source.source_id, PERIODIC); -} - -void __init s5p_set_timer_source(enum s5p_timer_mode event, - enum s5p_timer_mode source) -{ - s3c_device_timer[event].dev.bus = &platform_bus_type; - s3c_device_timer[source].dev.bus = &platform_bus_type; - - timer_source.event_id = event; - timer_source.source_id = source; -} - -static struct clock_event_device time_event_device = { - .name = "s5p_event_timer", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .rating = 200, - .set_next_event = s5p_set_next_event, - .set_mode = s5p_set_mode, -}; - -static irqreturn_t s5p_clock_event_isr(int irq, void *dev_id) -{ - struct clock_event_device *evt = dev_id; - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction s5p_clock_event_irq = { - .name = "s5p_time_irq", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = s5p_clock_event_isr, - .dev_id = &time_event_device, -}; - -static void __init s5p_clockevent_init(void) -{ - unsigned long pclk; - unsigned long clock_rate; - unsigned int irq_number; - struct clk *tscaler; - - pclk = clk_get_rate(timerclk); - - tscaler = clk_get_parent(tdiv_event); - - clk_set_rate(tscaler, pclk / 2); - clk_set_rate(tdiv_event, pclk / 2); - clk_set_parent(tin_event, tdiv_event); - - clock_rate = clk_get_rate(tin_event); - clock_count_per_tick = clock_rate / HZ; - - time_event_device.cpumask = cpumask_of(0); - clockevents_config_and_register(&time_event_device, clock_rate, 1, -1); - - irq_number = timer_source.event_id + IRQ_TIMER0; - setup_irq(irq_number, &s5p_clock_event_irq); -} - -static void __iomem *s5p_timer_reg(void) -{ - unsigned long offset = 0; - - switch (timer_source.source_id) { - case S5P_PWM0: - case S5P_PWM1: - case S5P_PWM2: - case S5P_PWM3: - offset = (timer_source.source_id * 0x0c) + 0x14; - break; - - case S5P_PWM4: - offset = 0x40; - break; - - default: - printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id); - return NULL; - } - - return S3C_TIMERREG(offset); -} - -/* - * Override the global weak sched_clock symbol with this - * local implementation which uses the clocksource to get some - * better resolution when scheduling the kernel. We accept that - * this wraps around for now, since it is just a relative time - * stamp. (Inspired by U300 implementation.) - */ -static u32 notrace s5p_read_sched_clock(void) -{ - void __iomem *reg = s5p_timer_reg(); - - if (!reg) - return 0; - - return ~__raw_readl(reg); -} - -static void __init s5p_clocksource_init(void) -{ - unsigned long pclk; - unsigned long clock_rate; - - pclk = clk_get_rate(timerclk); - - clk_set_rate(tdiv_source, pclk / 2); - clk_set_parent(tin_source, tdiv_source); - - clock_rate = clk_get_rate(tin_source); - - s5p_time_setup(timer_source.source_id, TCNT_MAX); - s5p_time_start(timer_source.source_id, PERIODIC); - - setup_sched_clock(s5p_read_sched_clock, 32, clock_rate); - - if (clocksource_mmio_init(s5p_timer_reg(), "s5p_clocksource_timer", - clock_rate, 250, 32, clocksource_mmio_readl_down)) - panic("s5p_clocksource_timer: can't register clocksource\n"); -} - -static void __init s5p_timer_resources(void) -{ - - unsigned long event_id = timer_source.event_id; - unsigned long source_id = timer_source.source_id; - char devname[15]; - - timerclk = clk_get(NULL, "timers"); - if (IS_ERR(timerclk)) - panic("failed to get timers clock for timer"); - - clk_enable(timerclk); - - sprintf(devname, "s3c24xx-pwm.%lu", event_id); - s3c_device_timer[event_id].id = event_id; - s3c_device_timer[event_id].dev.init_name = devname; - - tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin"); - if (IS_ERR(tin_event)) - panic("failed to get pwm-tin clock for event timer"); - - tdiv_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tdiv"); - if (IS_ERR(tdiv_event)) - panic("failed to get pwm-tdiv clock for event timer"); - - clk_enable(tin_event); - - sprintf(devname, "s3c24xx-pwm.%lu", source_id); - s3c_device_timer[source_id].id = source_id; - s3c_device_timer[source_id].dev.init_name = devname; - - tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin"); - if (IS_ERR(tin_source)) - panic("failed to get pwm-tin clock for source timer"); - - tdiv_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tdiv"); - if (IS_ERR(tdiv_source)) - panic("failed to get pwm-tdiv clock for source timer"); - - clk_enable(tin_source); -} - -void __init s5p_timer_init(void) -{ - s5p_timer_resources(); - s5p_clockevent_init(); - s5p_clocksource_init(); -} diff --git a/arch/arm/plat-samsung/setup-camif.c b/arch/arm/plat-samsung/setup-camif.c index e01bf760af2..72d8edb8927 100644 --- a/arch/arm/plat-samsung/setup-camif.c +++ b/arch/arm/plat-samsung/setup-camif.c @@ -10,6 +10,7 @@ #include <linux/gpio.h> #include <plat/gpio-cfg.h> +#include <mach/gpio-samsung.h> /* Number of camera port pins, without FIELD */ #define S3C_CAMIF_NUM_GPIOS 13 diff --git a/arch/arm/plat-samsung/setup-mipiphy.c b/arch/arm/plat-samsung/setup-mipiphy.c deleted file mode 100644 index 14745932760..00000000000 --- a/arch/arm/plat-samsung/setup-mipiphy.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics Co., Ltd. - * - * S5P - Helper functions for MIPI-CSIS and MIPI-DSIM D-PHY control - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/spinlock.h> -#include <mach/regs-clock.h> - -static int __s5p_mipi_phy_control(int id, bool on, u32 reset) -{ - static DEFINE_SPINLOCK(lock); - void __iomem *addr; - unsigned long flags; - u32 cfg; - - id = max(0, id); - if (id > 1) - return -EINVAL; - - addr = S5P_MIPI_DPHY_CONTROL(id); - - spin_lock_irqsave(&lock, flags); - - cfg = __raw_readl(addr); - cfg = on ? (cfg | reset) : (cfg & ~reset); - __raw_writel(cfg, addr); - - if (on) { - cfg |= S5P_MIPI_DPHY_ENABLE; - } else if (!(cfg & (S5P_MIPI_DPHY_SRESETN | - S5P_MIPI_DPHY_MRESETN) & ~reset)) { - cfg &= ~S5P_MIPI_DPHY_ENABLE; - } - - __raw_writel(cfg, addr); - spin_unlock_irqrestore(&lock, flags); - - return 0; -} - -int s5p_csis_phy_enable(int id, bool on) -{ - return __s5p_mipi_phy_control(id, on, S5P_MIPI_DPHY_SRESETN); -} - -int s5p_dsim_phy_enable(struct platform_device *pdev, bool on) -{ - return __s5p_mipi_phy_control(pdev->id, on, S5P_MIPI_DPHY_MRESETN); -} diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c deleted file mode 100644 index 73defd00c3e..00000000000 --- a/arch/arm/plat-samsung/time.c +++ /dev/null @@ -1,287 +0,0 @@ -/* linux/arch/arm/plat-samsung/time.c - * - * Copyright (C) 2003-2005 Simtec Electronics - * Ben Dooks, <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/platform_device.h> -#include <linux/syscore_ops.h> - -#include <asm/mach-types.h> - -#include <asm/irq.h> -#include <mach/map.h> -#include <plat/regs-timer.h> -#include <mach/regs-irq.h> -#include <asm/mach/time.h> -#include <mach/tick.h> - -#include <plat/clock.h> -#include <plat/cpu.h> - -static unsigned long timer_startval; -static unsigned long timer_usec_ticks; - -#ifndef TICK_MAX -#define TICK_MAX (0xffff) -#endif - -#define TIMER_USEC_SHIFT 16 - -/* we use the shifted arithmetic to work out the ratio of timer ticks - * to usecs, as often the peripheral clock is not a nice even multiple - * of 1MHz. - * - * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok - * for the current HZ value of 200 without producing overflows. - * - * Original patch by Dimitry Andric, updated by Ben Dooks -*/ - - -/* timer_mask_usec_ticks - * - * given a clock and divisor, make the value to pass into timer_ticks_to_usec - * to scale the ticks into usecs -*/ - -static inline unsigned long -timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk) -{ - unsigned long den = pclk / 1000; - - return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den; -} - -/* timer_ticks_to_usec - * - * convert timer ticks to usec. -*/ - -static inline unsigned long timer_ticks_to_usec(unsigned long ticks) -{ - unsigned long res; - - res = ticks * timer_usec_ticks; - res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */ - - return res >> TIMER_USEC_SHIFT; -} - -/*** - * Returns microsecond since last clock interrupt. Note that interrupts - * will have been disabled by do_gettimeoffset() - * IRQs are disabled before entering here from do_gettimeofday() - */ - -static u32 s3c2410_gettimeoffset(void) -{ - unsigned long tdone; - unsigned long tval; - - /* work out how many ticks have gone since last timer interrupt */ - - tval = __raw_readl(S3C2410_TCNTO(4)); - tdone = timer_startval - tval; - - /* check to see if there is an interrupt pending */ - - if (s3c24xx_ostimer_pending()) { - /* re-read the timer, and try and fix up for the missed - * interrupt. Note, the interrupt may go off before the - * timer has re-loaded from wrapping. - */ - - tval = __raw_readl(S3C2410_TCNTO(4)); - tdone = timer_startval - tval; - - if (tval != 0) - tdone += timer_startval; - } - - return timer_ticks_to_usec(tdone) * 1000; -} - - -/* - * IRQ handler for the timer - */ -static irqreturn_t -s3c2410_timer_interrupt(int irq, void *dev_id) -{ - timer_tick(); - return IRQ_HANDLED; -} - -static struct irqaction s3c2410_timer_irq = { - .name = "S3C2410 Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = s3c2410_timer_interrupt, -}; - -#define use_tclk1_12() ( \ - machine_is_bast() || \ - machine_is_vr1000() || \ - machine_is_anubis() || \ - machine_is_osiris()) - -static struct clk *tin; -static struct clk *tdiv; -static struct clk *timerclk; - -/* - * Set up timer interrupt, and return the current time in seconds. - * - * Currently we only use timer4, as it is the only timer which has no - * other function that can be exploited externally - */ -static void s3c2410_timer_setup (void) -{ - unsigned long tcon; - unsigned long tcnt; - unsigned long tcfg1; - unsigned long tcfg0; - - tcnt = TICK_MAX; /* default value for tcnt */ - - /* configure the system for whichever machine is in use */ - - if (use_tclk1_12()) { - /* timer is at 12MHz, scaler is 1 */ - timer_usec_ticks = timer_mask_usec_ticks(1, 12000000); - tcnt = 12000000 / HZ; - - tcfg1 = __raw_readl(S3C2410_TCFG1); - tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; - tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1; - __raw_writel(tcfg1, S3C2410_TCFG1); - } else { - unsigned long pclk; - struct clk *tscaler; - - /* for the h1940 (and others), we use the pclk from the core - * to generate the timer values. since values around 50 to - * 70MHz are not values we can directly generate the timer - * value from, we need to pre-scale and divide before using it. - * - * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz - * (8.45 ticks per usec) - */ - - pclk = clk_get_rate(timerclk); - - /* configure clock tick */ - - timer_usec_ticks = timer_mask_usec_ticks(6, pclk); - - tscaler = clk_get_parent(tdiv); - - clk_set_rate(tscaler, pclk / 3); - clk_set_rate(tdiv, pclk / 6); - clk_set_parent(tin, tdiv); - - tcnt = clk_get_rate(tin) / HZ; - } - - tcon = __raw_readl(S3C2410_TCON); - tcfg0 = __raw_readl(S3C2410_TCFG0); - tcfg1 = __raw_readl(S3C2410_TCFG1); - - /* timers reload after counting zero, so reduce the count by 1 */ - - tcnt--; - - printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n", - tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks); - - /* check to see if timer is within 16bit range... */ - if (tcnt > TICK_MAX) { - panic("setup_timer: HZ is too small, cannot configure timer!"); - return; - } - - __raw_writel(tcfg1, S3C2410_TCFG1); - __raw_writel(tcfg0, S3C2410_TCFG0); - - timer_startval = tcnt; - __raw_writel(tcnt, S3C2410_TCNTB(4)); - - /* ensure timer is stopped... */ - - tcon &= ~(7<<20); - tcon |= S3C2410_TCON_T4RELOAD; - tcon |= S3C2410_TCON_T4MANUALUPD; - - __raw_writel(tcon, S3C2410_TCON); - __raw_writel(tcnt, S3C2410_TCNTB(4)); - __raw_writel(tcnt, S3C2410_TCMPB(4)); - - /* start the timer running */ - tcon |= S3C2410_TCON_T4START; - tcon &= ~S3C2410_TCON_T4MANUALUPD; - __raw_writel(tcon, S3C2410_TCON); -} - -static void __init s3c2410_timer_resources(void) -{ - struct platform_device tmpdev; - - tmpdev.dev.bus = &platform_bus_type; - tmpdev.id = 4; - - timerclk = clk_get(NULL, "timers"); - if (IS_ERR(timerclk)) - panic("failed to get clock for system timer"); - - clk_enable(timerclk); - - if (!use_tclk1_12()) { - tmpdev.id = 4; - tmpdev.dev.init_name = "s3c24xx-pwm.4"; - tin = clk_get(&tmpdev.dev, "pwm-tin"); - if (IS_ERR(tin)) - panic("failed to get pwm-tin clock for system timer"); - - tdiv = clk_get(&tmpdev.dev, "pwm-tdiv"); - if (IS_ERR(tdiv)) - panic("failed to get pwm-tdiv clock for system timer"); - } - - clk_enable(tin); -} - -static struct syscore_ops s3c24xx_syscore_ops = { - .resume = s3c2410_timer_setup, -}; - -void __init s3c24xx_timer_init(void) -{ - arch_gettimeoffset = s3c2410_gettimeoffset; - - s3c2410_timer_resources(); - s3c2410_timer_setup(); - setup_irq(IRQ_TIMER4, &s3c2410_timer_irq); - register_syscore_ops(&s3c24xx_syscore_ops); -} diff --git a/arch/arm/plat-samsung/watchdog-reset.c b/arch/arm/plat-samsung/watchdog-reset.c new file mode 100644 index 00000000000..2ecb50bea04 --- /dev/null +++ b/arch/arm/plat-samsung/watchdog-reset.c @@ -0,0 +1,97 @@ +/* arch/arm/plat-samsung/watchdog-reset.c + * + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * Coyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> + * + * Watchdog reset support for Samsung SoCs. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/of.h> +#include <linux/of_address.h> + +#define S3C2410_WTCON 0x00 +#define S3C2410_WTDAT 0x04 +#define S3C2410_WTCNT 0x08 + +#define S3C2410_WTCON_ENABLE (1 << 5) +#define S3C2410_WTCON_DIV16 (0 << 3) +#define S3C2410_WTCON_RSTEN (1 << 0) +#define S3C2410_WTCON_PRESCALE(x) ((x) << 8) + +static void __iomem *wdt_base; +static struct clk *wdt_clock; + +void samsung_wdt_reset(void) +{ + if (!wdt_base) { + pr_err("%s: wdt reset not initialized\n", __func__); + /* delay to allow the serial port to show the message */ + mdelay(50); + return; + } + + if (!IS_ERR(wdt_clock)) + clk_prepare_enable(wdt_clock); + + /* disable watchdog, to be safe */ + __raw_writel(0, wdt_base + S3C2410_WTCON); + + /* put initial values into count and data */ + __raw_writel(0x80, wdt_base + S3C2410_WTCNT); + __raw_writel(0x80, wdt_base + S3C2410_WTDAT); + + /* set the watchdog to go and reset... */ + __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 | + S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20), + wdt_base + S3C2410_WTCON); + + /* wait for reset to assert... */ + mdelay(500); + + pr_err("Watchdog reset failed to assert reset\n"); + + /* delay to allow the serial port to show the message */ + mdelay(50); +} + +#ifdef CONFIG_OF +static const struct of_device_id s3c2410_wdt_match[] = { + { .compatible = "samsung,s3c2410-wdt" }, + {}, +}; + +void __init samsung_wdt_reset_of_init(void) +{ + struct device_node *np; + + np = of_find_matching_node(NULL, s3c2410_wdt_match); + if (!np) { + pr_err("%s: failed to find watchdog node\n", __func__); + return; + } + + wdt_base = of_iomap(np, 0); + if (!wdt_base) { + pr_err("%s: failed to map watchdog registers\n", __func__); + return; + } + + wdt_clock = of_clk_get(np, 0); +} +#endif + +void __init samsung_wdt_reset_init(void __iomem *base) +{ + wdt_base = base; + wdt_clock = clk_get(NULL, "watchdog"); +} |