diff options
Diffstat (limited to 'arch/arm/plat-s3c')
43 files changed, 0 insertions, 4774 deletions
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig deleted file mode 100644 index de9383814e5..00000000000 --- a/arch/arm/plat-s3c/Kconfig +++ /dev/null @@ -1,175 +0,0 @@ -# arch/arm/plat-s3c/Kconfig -# -# Copyright 2007 Simtec Electronics -# -# Licensed under GPLv2 - -config PLAT_S3C - bool - depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX - default y - select NO_IOPORT - help - Base platform code for any Samsung S3C device - -# low-level serial option nodes - -if PLAT_S3C - -config CPU_LLSERIAL_S3C2410_ONLY - bool - default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440 - -config CPU_LLSERIAL_S3C2440_ONLY - bool - default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410 - -config CPU_LLSERIAL_S3C2410 - bool - help - Selected if there is an S3C2410 (or register compatible) serial - low-level implementation needed - -config CPU_LLSERIAL_S3C2440 - bool - help - Selected if there is an S3C2440 (or register compatible) serial - low-level implementation needed - -# boot configurations - -comment "Boot options" - -config S3C_BOOT_WATCHDOG - bool "S3C Initialisation watchdog" - depends on S3C2410_WATCHDOG - help - Say y to enable the watchdog during the kernel decompression - stage. If the kernel fails to uncompress, then the watchdog - will trigger a reset and the system should restart. - -config S3C_BOOT_ERROR_RESET - bool "S3C Reboot on decompression error" - help - Say y here to use the watchdog to reset the system if the - kernel decompressor detects an error during decompression. - -config S3C_BOOT_UART_FORCE_FIFO - bool "Force UART FIFO on during boot process" - default y - help - Say Y here to force the UART FIFOs on during the kernel - uncompressor - -comment "Power management" - -config S3C2410_PM_DEBUG - bool "S3C2410 PM Suspend debug" - depends on PM - help - Say Y here if you want verbose debugging from the PM Suspend and - Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> - for more information. - -config S3C2410_PM_CHECK - bool "S3C2410 PM Suspend Memory CRC" - depends on PM && CRC32 - help - Enable the PM code's memory area checksum over sleep. This option - will generate CRCs of all blocks of memory, and store them before - going to sleep. The blocks are then checked on resume for any - errors. - - Note, this can take several seconds depending on memory size - and CPU speed. - - See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> - -config S3C2410_PM_CHECK_CHUNKSIZE - int "S3C2410 PM Suspend CRC Chunksize (KiB)" - depends on PM && S3C2410_PM_CHECK - default 64 - help - Set the chunksize in Kilobytes of the CRC for checking memory - corruption over suspend and resume. A smaller value will mean that - the CRC data block will take more memory, but wil identify any - faults with better precision. - - See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> - -config S3C_LOWLEVEL_UART_PORT - int "S3C UART to use for low-level messages" - default 0 - help - Choice of which UART port to use for the low-level messages, - such as the `Uncompressing...` at start time. The value of - this configuration should be between zero and two. The port - must have been initialised by the boot-loader before use. - -# options for gpiolib support - -config S3C_GPIO_SPACE - int "Space between gpio banks" - default 0 - help - Add a number of spare GPIO entries between each bank for debugging - purposes. This allows any problems where an counter overflows from - one bank to another to be caught, at the expense of using a little - more memory. - -config S3C_GPIO_TRACK - bool - help - Internal configuration option to enable the s3c specific gpio - chip tracking if the platform requires it. - -config S3C_GPIO_PULL_UPDOWN - bool - help - Internal configuration to enable the correct GPIO pull helper - -config S3C_GPIO_PULL_DOWN - bool - help - Internal configuration to enable the correct GPIO pull helper - -config S3C_GPIO_PULL_UP - bool - help - Internal configuration to enable the correct GPIO pull helper - -config S3C_GPIO_CFG_S3C24XX - bool - help - Internal configuration to enable S3C24XX style GPIO configuration - functions. - -config S3C_GPIO_CFG_S3C64XX - bool - help - Internal configuration to enable S3C64XX style GPIO configuration - functions. - -# device definitions to compile in - -config S3C_DEV_HSMMC - bool - help - Compile in platform device definitions for HSMMC code - -config S3C_DEV_HSMMC1 - bool - help - Compile in platform device definitions for HSMMC channel 1 - -config S3C_DEV_I2C1 - bool - help - Compile in platform device definitions for I2C channel 1 - -config S3C_DEV_FB - bool - help - Compile in platform device definition for framebuffer - -endif diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile deleted file mode 100644 index 39195f972d5..00000000000 --- a/arch/arm/plat-s3c/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -# arch/arm/plat-s3c/Makefile -# -# Copyright 2008 Simtec Electronics -# -# Licensed under GPLv2 - -obj-y := -obj-m := -obj-n := -obj- := - -# Core support for all Samsung SoCs - -obj-y += init.o -obj-y += time.o -obj-y += clock.o -obj-y += pwm-clock.o -obj-y += gpio.o -obj-y += gpio-config.o - -# devices - -obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o -obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o -obj-y += dev-i2c0.o -obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o -obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-s3c/clock.c deleted file mode 100644 index b6be76e2fe5..00000000000 --- a/arch/arm/plat-s3c/clock.c +++ /dev/null @@ -1,368 +0,0 @@ -/* linux/arch/arm/plat-s3c24xx/clock.c - * - * Copyright (c) 2004-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C24XX Core clock control support - * - * Based on, and code from linux/arch/arm/mach-versatile/clock.c - ** - ** Copyright (C) 2004 ARM Limited. - ** Written by Deep Blue Solutions Limited. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/platform_device.h> -#include <linux/sysdev.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/clk.h> -#include <linux/spinlock.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <asm/irq.h> - -#include <plat/cpu-freq.h> - -#include <plat/clock.h> -#include <plat/cpu.h> - -/* clock information */ - -static LIST_HEAD(clocks); - -/* We originally used an mutex here, but some contexts (see resume) - * are calling functions such as clk_set_parent() with IRQs disabled - * causing an BUG to be triggered. - */ -DEFINE_SPINLOCK(clocks_lock); - -/* enable and disable calls for use with the clk struct */ - -static int clk_null_enable(struct clk *clk, int enable) -{ - return 0; -} - -/* Clock API calls */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *p; - struct clk *clk = ERR_PTR(-ENOENT); - int idno; - - if (dev == NULL || dev->bus != &platform_bus_type) - idno = -1; - else - idno = to_platform_device(dev)->id; - - spin_lock(&clocks_lock); - - list_for_each_entry(p, &clocks, list) { - if (p->id == idno && - strcmp(id, p->name) == 0 && - try_module_get(p->owner)) { - clk = p; - break; - } - } - - /* check for the case where a device was supplied, but the - * clock that was being searched for is not device specific */ - - if (IS_ERR(clk)) { - list_for_each_entry(p, &clocks, list) { - if (p->id == -1 && strcmp(id, p->name) == 0 && - try_module_get(p->owner)) { - clk = p; - break; - } - } - } - - spin_unlock(&clocks_lock); - return clk; -} - -void clk_put(struct clk *clk) -{ - module_put(clk->owner); -} - -int clk_enable(struct clk *clk) -{ - if (IS_ERR(clk) || clk == NULL) - return -EINVAL; - - clk_enable(clk->parent); - - spin_lock(&clocks_lock); - - if ((clk->usage++) == 0) - (clk->enable)(clk, 1); - - spin_unlock(&clocks_lock); - return 0; -} - -void clk_disable(struct clk *clk) -{ - if (IS_ERR(clk) || clk == NULL) - return; - - spin_lock(&clocks_lock); - - if ((--clk->usage) == 0) - (clk->enable)(clk, 0); - - spin_unlock(&clocks_lock); - clk_disable(clk->parent); -} - - -unsigned long clk_get_rate(struct clk *clk) -{ - if (IS_ERR(clk)) - return 0; - - if (clk->rate != 0) - return clk->rate; - - if (clk->get_rate != NULL) - return (clk->get_rate)(clk); - - if (clk->parent != NULL) - return clk_get_rate(clk->parent); - - return clk->rate; -} - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (!IS_ERR(clk) && clk->round_rate) - return (clk->round_rate)(clk, rate); - - return rate; -} - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret; - - if (IS_ERR(clk)) - return -EINVAL; - - /* We do not default just do a clk->rate = rate as - * the clock may have been made this way by choice. - */ - - WARN_ON(clk->set_rate == NULL); - - if (clk->set_rate == NULL) - return -EINVAL; - - spin_lock(&clocks_lock); - ret = (clk->set_rate)(clk, rate); - spin_unlock(&clocks_lock); - - return ret; -} - -struct clk *clk_get_parent(struct clk *clk) -{ - return clk->parent; -} - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - int ret = 0; - - if (IS_ERR(clk)) - return -EINVAL; - - spin_lock(&clocks_lock); - - if (clk->set_parent) - ret = (clk->set_parent)(clk, parent); - - spin_unlock(&clocks_lock); - - return ret; -} - -EXPORT_SYMBOL(clk_get); -EXPORT_SYMBOL(clk_put); -EXPORT_SYMBOL(clk_enable); -EXPORT_SYMBOL(clk_disable); -EXPORT_SYMBOL(clk_get_rate); -EXPORT_SYMBOL(clk_round_rate); -EXPORT_SYMBOL(clk_set_rate); -EXPORT_SYMBOL(clk_get_parent); -EXPORT_SYMBOL(clk_set_parent); - -/* base clocks */ - -static int clk_default_setrate(struct clk *clk, unsigned long rate) -{ - clk->rate = rate; - return 0; -} - -struct clk clk_xtal = { - .name = "xtal", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, -}; - -struct clk clk_ext = { - .name = "ext", - .id = -1, -}; - -struct clk clk_epll = { - .name = "epll", - .id = -1, -}; - -struct clk clk_mpll = { - .name = "mpll", - .id = -1, - .set_rate = clk_default_setrate, -}; - -struct clk clk_upll = { - .name = "upll", - .id = -1, - .parent = NULL, - .ctrlbit = 0, -}; - -struct clk clk_f = { - .name = "fclk", - .id = -1, - .rate = 0, - .parent = &clk_mpll, - .ctrlbit = 0, - .set_rate = clk_default_setrate, -}; - -struct clk clk_h = { - .name = "hclk", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, - .set_rate = clk_default_setrate, -}; - -struct clk clk_p = { - .name = "pclk", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, - .set_rate = clk_default_setrate, -}; - -struct clk clk_usb_bus = { - .name = "usb-bus", - .id = -1, - .rate = 0, - .parent = &clk_upll, -}; - - - -struct clk s3c24xx_uclk = { - .name = "uclk", - .id = -1, -}; - -/* initialise the clock system */ - -int s3c24xx_register_clock(struct clk *clk) -{ - clk->owner = THIS_MODULE; - - if (clk->enable == NULL) - clk->enable = clk_null_enable; - - /* add to the list of available clocks */ - - /* Quick check to see if this clock has already been registered. */ - BUG_ON(clk->list.prev != clk->list.next); - - spin_lock(&clocks_lock); - list_add(&clk->list, &clocks); - spin_unlock(&clocks_lock); - - return 0; -} - -int s3c24xx_register_clocks(struct clk **clks, int nr_clks) -{ - int fails = 0; - - for (; nr_clks > 0; nr_clks--, clks++) { - if (s3c24xx_register_clock(*clks) < 0) - fails++; - } - - return fails; -} - -/* initalise all the clocks */ - -int __init s3c24xx_register_baseclocks(unsigned long xtal) -{ - printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); - - clk_xtal.rate = xtal; - - /* register our clocks */ - - if (s3c24xx_register_clock(&clk_xtal) < 0) - printk(KERN_ERR "failed to register master xtal\n"); - - if (s3c24xx_register_clock(&clk_mpll) < 0) - printk(KERN_ERR "failed to register mpll clock\n"); - - if (s3c24xx_register_clock(&clk_upll) < 0) - printk(KERN_ERR "failed to register upll clock\n"); - - if (s3c24xx_register_clock(&clk_f) < 0) - printk(KERN_ERR "failed to register cpu fclk\n"); - - if (s3c24xx_register_clock(&clk_h) < 0) - printk(KERN_ERR "failed to register cpu hclk\n"); - - if (s3c24xx_register_clock(&clk_p) < 0) - printk(KERN_ERR "failed to register cpu pclk\n"); - - return 0; -} - diff --git a/arch/arm/plat-s3c/dev-fb.c b/arch/arm/plat-s3c/dev-fb.c deleted file mode 100644 index a90198fc4b0..00000000000 --- a/arch/arm/plat-s3c/dev-fb.c +++ /dev/null @@ -1,73 +0,0 @@ -/* linux/arch/arm/plat-s3c/dev-fb.c - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series device definition for framebuffer device - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> -#include <linux/fb.h> - -#include <mach/irqs.h> -#include <mach/map.h> -#include <mach/regs-fb.h> - -#include <plat/fb.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -static struct resource s3c_fb_resource[] = { - [0] = { - .start = S3C_PA_FB, - .end = S3C_PA_FB + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_LCD_VSYNC, - .end = IRQ_LCD_VSYNC, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_LCD_FIFO, - .end = IRQ_LCD_FIFO, - .flags = IORESOURCE_IRQ, - }, - [3] = { - .start = IRQ_LCD_SYSTEM, - .end = IRQ_LCD_SYSTEM, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c_device_fb = { - .name = "s3c-fb", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_fb_resource), - .resource = s3c_fb_resource, - .dev.dma_mask = &s3c_device_fb.dev.coherent_dma_mask, - .dev.coherent_dma_mask = 0xffffffffUL, -}; - -void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd) -{ - struct s3c_fb_platdata *npd; - - if (!pd) { - printk(KERN_ERR "%s: no platform data\n", __func__); - return; - } - - npd = kmemdup(pd, sizeof(struct s3c_fb_platdata), GFP_KERNEL); - if (!npd) - printk(KERN_ERR "%s: no memory for platform data\n", __func__); - - s3c_device_fb.dev.platform_data = npd; -} diff --git a/arch/arm/plat-s3c/dev-hsmmc.c b/arch/arm/plat-s3c/dev-hsmmc.c deleted file mode 100644 index 4c05b39810e..00000000000 --- a/arch/arm/plat-s3c/dev-hsmmc.c +++ /dev/null @@ -1,68 +0,0 @@ -/* linux/arch/arm/plat-s3c/dev-hsmmc.c - * - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series device definition for hsmmc devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/mmc/host.h> - -#include <mach/map.h> -#include <plat/sdhci.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -#define S3C_SZ_HSMMC (0x1000) - -static struct resource s3c_hsmmc_resource[] = { - [0] = { - .start = S3C_PA_HSMMC0, - .end = S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_HSMMC0, - .end = IRQ_HSMMC0, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL; - -struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = { - .max_width = 4, - .host_caps = (MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), -}; - -struct platform_device s3c_device_hsmmc0 = { - .name = "s3c-sdhci", - .id = 0, - .num_resources = ARRAY_SIZE(s3c_hsmmc_resource), - .resource = s3c_hsmmc_resource, - .dev = { - .dma_mask = &s3c_device_hsmmc_dmamask, - .coherent_dma_mask = 0xffffffffUL, - .platform_data = &s3c_hsmmc0_def_platdata, - }, -}; - -void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd) -{ - struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata; - - set->max_width = pd->max_width; - - if (pd->cfg_gpio) - set->cfg_gpio = pd->cfg_gpio; - if (pd->cfg_card) - set->cfg_card = pd->cfg_card; -} diff --git a/arch/arm/plat-s3c/dev-hsmmc1.c b/arch/arm/plat-s3c/dev-hsmmc1.c deleted file mode 100644 index e49bc4cd0ee..00000000000 --- a/arch/arm/plat-s3c/dev-hsmmc1.c +++ /dev/null @@ -1,68 +0,0 @@ -/* linux/arch/arm/plat-s3c/dev-hsmmc1.c - * - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series device definition for hsmmc device 1 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/mmc/host.h> - -#include <mach/map.h> -#include <plat/sdhci.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -#define S3C_SZ_HSMMC (0x1000) - -static struct resource s3c_hsmmc1_resource[] = { - [0] = { - .start = S3C_PA_HSMMC1, - .end = S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_HSMMC1, - .end = IRQ_HSMMC1, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 s3c_device_hsmmc1_dmamask = 0xffffffffUL; - -struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = { - .max_width = 4, - .host_caps = (MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), -}; - -struct platform_device s3c_device_hsmmc1 = { - .name = "s3c-sdhci", - .id = 1, - .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource), - .resource = s3c_hsmmc1_resource, - .dev = { - .dma_mask = &s3c_device_hsmmc1_dmamask, - .coherent_dma_mask = 0xffffffffUL, - .platform_data = &s3c_hsmmc1_def_platdata, - }, -}; - -void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd) -{ - struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata; - - set->max_width = pd->max_width; - - if (pd->cfg_gpio) - set->cfg_gpio = pd->cfg_gpio; - if (pd->cfg_card) - set->cfg_card = pd->cfg_card; -} diff --git a/arch/arm/plat-s3c/dev-i2c0.c b/arch/arm/plat-s3c/dev-i2c0.c deleted file mode 100644 index fe327074037..00000000000 --- a/arch/arm/plat-s3c/dev-i2c0.c +++ /dev/null @@ -1,72 +0,0 @@ -/* linux/arch/arm/plat-s3c/dev-i2c0.c - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series device definition for i2c device 0 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/regs-iic.h> -#include <plat/iic.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -static struct resource s3c_i2c_resource[] = { - [0] = { - .start = S3C_PA_IIC, - .end = S3C_PA_IIC + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IIC, - .end = IRQ_IIC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c_device_i2c0 = { - .name = "s3c2410-i2c", -#ifdef CONFIG_S3C_DEV_I2C1 - .id = 0, -#else - .id = -1, -#endif - .num_resources = ARRAY_SIZE(s3c_i2c_resource), - .resource = s3c_i2c_resource, -}; - -static struct s3c2410_platform_i2c default_i2c_data0 __initdata = { - .flags = 0, - .slave_addr = 0x10, - .bus_freq = 100*1000, - .max_freq = 400*1000, - .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON, -}; - -void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd) -{ - struct s3c2410_platform_i2c *npd; - - if (!pd) - pd = &default_i2c_data0; - - npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); - if (!npd) - printk(KERN_ERR "%s: no memory for platform data\n", __func__); - else if (!npd->cfg_gpio) - npd->cfg_gpio = s3c_i2c0_cfg_gpio; - - s3c_device_i2c0.dev.platform_data = npd; -} diff --git a/arch/arm/plat-s3c/dev-i2c1.c b/arch/arm/plat-s3c/dev-i2c1.c deleted file mode 100644 index 2387fbf57af..00000000000 --- a/arch/arm/plat-s3c/dev-i2c1.c +++ /dev/null @@ -1,69 +0,0 @@ -/* linux/arch/arm/plat-s3c/dev-i2c1.c - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series device definition for i2c device 1 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/regs-iic.h> -#include <plat/iic.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -static struct resource s3c_i2c_resource[] = { - [0] = { - .start = S3C_PA_IIC1, - .end = S3C_PA_IIC1 + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IIC1, - .end = IRQ_IIC1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c_device_i2c1 = { - .name = "s3c2410-i2c", - .id = 1, - .num_resources = ARRAY_SIZE(s3c_i2c_resource), - .resource = s3c_i2c_resource, -}; - -static struct s3c2410_platform_i2c default_i2c_data1 __initdata = { - .flags = 0, - .bus_num = 1, - .slave_addr = 0x10, - .bus_freq = 100*1000, - .max_freq = 400*1000, - .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON, -}; - -void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd) -{ - struct s3c2410_platform_i2c *npd; - - if (!pd) - pd = &default_i2c_data1; - - npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); - if (!npd) - printk(KERN_ERR "%s: no memory for platform data\n", __func__); - else if (!npd->cfg_gpio) - npd->cfg_gpio = s3c_i2c1_cfg_gpio; - - s3c_device_i2c1.dev.platform_data = npd; -} diff --git a/arch/arm/plat-s3c/gpio-config.c b/arch/arm/plat-s3c/gpio-config.c deleted file mode 100644 index 7642b975a99..00000000000 --- a/arch/arm/plat-s3c/gpio-config.c +++ /dev/null @@ -1,163 +0,0 @@ -/* linux/arch/arm/plat-s3c/gpio-config.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series GPIO configuration core - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/gpio.h> -#include <linux/io.h> - -#include <mach/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> - -int s3c_gpio_cfgpin(unsigned int pin, unsigned int config) -{ - struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); - unsigned long flags; - int offset; - int ret; - - if (!chip) - return -EINVAL; - - offset = pin - chip->chip.base; - - local_irq_save(flags); - ret = s3c_gpio_do_setcfg(chip, offset, config); - local_irq_restore(flags); - - return ret; -} - -int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull) -{ - struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); - unsigned long flags; - int offset, ret; - - if (!chip) - return -EINVAL; - - offset = pin - chip->chip.base; - - local_irq_save(flags); - ret = s3c_gpio_do_setpull(chip, offset, pull); - local_irq_restore(flags); - - return ret; -} - -#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX -int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip, - unsigned int off, unsigned int cfg) -{ - void __iomem *reg = chip->base; - unsigned int shift = off; - u32 con; - - if (s3c_gpio_is_cfg_special(cfg)) { - cfg &= 0xf; - - /* Map output to 0, and SFN2 to 1 */ - cfg -= 1; - if (cfg > 1) - return -EINVAL; - - cfg <<= shift; - } - - con = __raw_readl(reg); - con &= ~(0x1 << shift); - con |= cfg; - __raw_writel(con, reg); - - return 0; -} - -int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, - unsigned int off, unsigned int cfg) -{ - void __iomem *reg = chip->base; - unsigned int shift = off * 2; - u32 con; - - if (s3c_gpio_is_cfg_special(cfg)) { - cfg &= 0xf; - if (cfg > 3) - return -EINVAL; - - cfg <<= shift; - } - - con = __raw_readl(reg); - con &= ~(0x3 << shift); - con |= cfg; - __raw_writel(con, reg); - - return 0; -} -#endif - -#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX -int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, - unsigned int off, unsigned int cfg) -{ - void __iomem *reg = chip->base; - unsigned int shift = (off & 7) * 4; - u32 con; - - if (off < 8 && chip->chip.ngpio >= 8) - reg -= 4; - - if (s3c_gpio_is_cfg_special(cfg)) { - cfg &= 0xf; - cfg <<= shift; - } - - con = __raw_readl(reg); - con &= ~(0xf << shift); - con |= cfg; - __raw_writel(con, reg); - - return 0; -} -#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */ - -#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN -int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull) -{ - void __iomem *reg = chip->base + 0x08; - int shift = off * 2; - u32 pup; - - pup = __raw_readl(reg); - pup &= ~(3 << shift); - pup |= pull << shift; - __raw_writel(pup, reg); - - return 0; -} - -s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, - unsigned int off) -{ - void __iomem *reg = chip->base + 0x08; - int shift = off * 2; - u32 pup = __raw_readl(reg); - - pup >>= shift; - pup &= 0x3; - return (__force s3c_gpio_pull_t)pup; -} -#endif diff --git a/arch/arm/plat-s3c/gpio.c b/arch/arm/plat-s3c/gpio.c deleted file mode 100644 index d71dd6d9ce5..00000000000 --- a/arch/arm/plat-s3c/gpio.c +++ /dev/null @@ -1,147 +0,0 @@ -/* linux/arch/arm/plat-s3c/gpio.c - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series GPIO core - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/gpio.h> - -#include <plat/gpio-core.h> - -#ifdef CONFIG_S3C_GPIO_TRACK -struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; - -static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip) -{ - unsigned int gpn; - int i; - - gpn = chip->chip.base; - for (i = 0; i < chip->chip.ngpio; i++, gpn++) { - BUG_ON(gpn > ARRAY_SIZE(s3c_gpios)); - s3c_gpios[gpn] = chip; - } -} -#endif /* CONFIG_S3C_GPIO_TRACK */ - -/* Default routines for controlling GPIO, based on the original S3C24XX - * GPIO functions which deal with the case where each gpio bank of the - * chip is as following: - * - * base + 0x00: Control register, 2 bits per gpio - * gpio n: 2 bits starting at (2*n) - * 00 = input, 01 = output, others mean special-function - * base + 0x04: Data register, 1 bit per gpio - * bit n: data bit n -*/ - -static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long flags; - unsigned long con; - - local_irq_save(flags); - - con = __raw_readl(base + 0x00); - con &= ~(3 << (offset * 2)); - - __raw_writel(con, base + 0x00); - - local_irq_restore(flags); - return 0; -} - -static int s3c_gpiolib_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long flags; - unsigned long dat; - unsigned long con; - - local_irq_save(flags); - - dat = __raw_readl(base + 0x04); - dat &= ~(1 << offset); - if (value) - dat |= 1 << offset; - __raw_writel(dat, base + 0x04); - - con = __raw_readl(base + 0x00); - con &= ~(3 << (offset * 2)); - con |= 1 << (offset * 2); - - __raw_writel(con, base + 0x00); - __raw_writel(dat, base + 0x04); - - local_irq_restore(flags); - return 0; -} - -static void s3c_gpiolib_set(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long flags; - unsigned long dat; - - local_irq_save(flags); - - dat = __raw_readl(base + 0x04); - dat &= ~(1 << offset); - if (value) - dat |= 1 << offset; - __raw_writel(dat, base + 0x04); - - local_irq_restore(flags); -} - -static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - unsigned long val; - - val = __raw_readl(ourchip->base + 0x04); - val >>= offset; - val &= 1; - - return val; -} - -__init void s3c_gpiolib_add(struct s3c_gpio_chip *chip) -{ - struct gpio_chip *gc = &chip->chip; - int ret; - - BUG_ON(!chip->base); - BUG_ON(!gc->label); - BUG_ON(!gc->ngpio); - - if (!gc->direction_input) - gc->direction_input = s3c_gpiolib_input; - if (!gc->direction_output) - gc->direction_output = s3c_gpiolib_output; - if (!gc->set) - gc->set = s3c_gpiolib_set; - if (!gc->get) - gc->get = s3c_gpiolib_get; - - /* gpiochip_add() prints own failure message on error. */ - ret = gpiochip_add(gc); - if (ret >= 0) - s3c_gpiolib_track(chip); -} diff --git a/arch/arm/plat-s3c/include/mach/io.h b/arch/arm/plat-s3c/include/mach/io.h deleted file mode 100644 index f6a53631b66..00000000000 --- a/arch/arm/plat-s3c/include/mach/io.h +++ /dev/null @@ -1,18 +0,0 @@ -/* arch/arm/plat-s3c/include/mach/io.h - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben-linux@fluff.org> - * - * Default IO routines for plat-s3c based systems, such as S3C24A0 - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -/* No current ISA/PCI bus support. */ -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) - -#define IO_SPACE_LIMIT (0xFFFFFFFF) - -#endif diff --git a/arch/arm/plat-s3c/include/mach/timex.h b/arch/arm/plat-s3c/include/mach/timex.h deleted file mode 100644 index 2a425ed0a7e..00000000000 --- a/arch/arm/plat-s3c/include/mach/timex.h +++ /dev/null @@ -1,26 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/timex.h - * - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - time parameters - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it - * a variable is useless. It seems as long as we make our timers an - * exact multiple of HZ, any value that makes a 1->1 correspondence - * for the time conversion functions to/from jiffies is acceptable. -*/ - - -#define CLOCK_TICK_RATE 12000000 - - -#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/plat-s3c/include/mach/vmalloc.h b/arch/arm/plat-s3c/include/mach/vmalloc.h deleted file mode 100644 index bfd2ca6e307..00000000000 --- a/arch/arm/plat-s3c/include/mach/vmalloc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* arch/arm/plat-s3c/include/mach/vmalloc.h - * - * from arch/arm/mach-iop3xx/include/mach/vmalloc.h - * - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 vmalloc definition -*/ - -#ifndef __ASM_ARCH_VMALLOC_H -#define __ASM_ARCH_VMALLOC_H - -#define VMALLOC_END (0xE0000000) - -#endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/plat-s3c/include/plat/adc.h b/arch/arm/plat-s3c/include/plat/adc.h deleted file mode 100644 index 43df2a404b0..00000000000 --- a/arch/arm/plat-s3c/include/plat/adc.h +++ /dev/null @@ -1,29 +0,0 @@ -/* arch/arm/plat-s3c/include/plat/adc.h - * - * Copyright (c) 2008 Simtec Electronics - * http://armlinux.simnte.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C24XX ADC driver information - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_PLAT_ADC_H -#define __ASM_PLAT_ADC_H __FILE__ - -struct s3c_adc_client; - -extern int s3c_adc_start(struct s3c_adc_client *client, - unsigned int channel, unsigned int nr_samples); - -extern struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev, - void (*select)(unsigned selected), - void (*conv)(unsigned d0, unsigned d1), - unsigned int is_ts); - -extern void s3c_adc_release(struct s3c_adc_client *client); - -#endif /* __ASM_PLAT_ADC_H */ diff --git a/arch/arm/plat-s3c/include/plat/clock.h b/arch/arm/plat-s3c/include/plat/clock.h deleted file mode 100644 index a10622eed43..00000000000 --- a/arch/arm/plat-s3c/include/plat/clock.h +++ /dev/null @@ -1,88 +0,0 @@ -/* linux/arch/arm/plat-s3c/include/plat/clock.h - * - * Copyright (c) 2004-2005 Simtec Electronics - * http://www.simtec.co.uk/products/SWLINUX/ - * Written by Ben Dooks, <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/spinlock.h> - -struct clk { - struct list_head list; - struct module *owner; - struct clk *parent; - const char *name; - int id; - int usage; - unsigned long rate; - unsigned long ctrlbit; - - int (*enable)(struct clk *, int enable); - int (*set_rate)(struct clk *c, unsigned long rate); - unsigned long (*get_rate)(struct clk *c); - unsigned long (*round_rate)(struct clk *c, unsigned long rate); - int (*set_parent)(struct clk *c, struct clk *parent); -}; - -/* other clocks which may be registered by board support */ - -extern struct clk s3c24xx_dclk0; -extern struct clk s3c24xx_dclk1; -extern struct clk s3c24xx_clkout0; -extern struct clk s3c24xx_clkout1; -extern struct clk s3c24xx_uclk; - -extern struct clk clk_usb_bus; - -/* core clock support */ - -extern struct clk clk_f; -extern struct clk clk_h; -extern struct clk clk_p; -extern struct clk clk_mpll; -extern struct clk clk_upll; -extern struct clk clk_epll; -extern struct clk clk_xtal; -extern struct clk clk_ext; - -/* S3C64XX specific clocks */ -extern struct clk clk_27m; -extern struct clk clk_48m; - -/* exports for arch/arm/mach-s3c2410 - * - * Please DO NOT use these outside of arch/arm/mach-s3c2410 -*/ - -extern spinlock_t clocks_lock; - -extern int s3c2410_clkcon_enable(struct clk *clk, int enable); - -extern int s3c24xx_register_clock(struct clk *clk); -extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); - -extern int s3c24xx_register_baseclocks(unsigned long xtal); - -extern void s3c64xx_register_clocks(void); - -extern void s3c24xx_setup_clocks(unsigned long fclk, - unsigned long hclk, - unsigned long pclk); - -extern void s3c2410_setup_clocks(void); -extern void s3c2412_setup_clocks(void); -extern void s3c244x_setup_clocks(void); -extern void s3c2443_setup_clocks(void); - -/* S3C64XX specific functions and clocks */ - -extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable); - -/* Init for pwm clock code */ - -extern void s3c_pwmclk_init(void); - diff --git a/arch/arm/plat-s3c/include/plat/cpu-freq.h b/arch/arm/plat-s3c/include/plat/cpu-freq.h deleted file mode 100644 index c86a13307e9..00000000000 --- a/arch/arm/plat-s3c/include/plat/cpu-freq.h +++ /dev/null @@ -1,94 +0,0 @@ -/* arch/arm/plat-s3c/include/plat/cpu-freq.h - * - * Copyright (c) 2006,2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C CPU frequency scaling support - driver and board - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/cpufreq.h> - -struct s3c_cpufreq_info; -struct s3c_cpufreq_board; -struct s3c_iotimings; - -struct s3c_freq { - unsigned long fclk; - unsigned long armclk; - unsigned long hclk_tns; /* in 10ths of ns */ - unsigned long hclk; - unsigned long pclk; -}; - -/* wrapper 'struct cpufreq_freqs' so that any drivers receiving the - * notification can use this information that is not provided by just - * having the core frequency alone. - */ - -struct s3c_cpufreq_freqs { - struct cpufreq_freqs freqs; - struct s3c_freq old; - struct s3c_freq new; -}; - -#define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs) - -struct s3c_clkdivs { - int p_divisor; /* fclk / pclk */ - int h_divisor; /* fclk / hclk */ - int arm_divisor; /* not all cpus have this. */ - unsigned char dvs; /* using dvs mode to arm. */ -}; - -#define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s)) - -struct s3c_pllval { - unsigned long freq; - unsigned long pll_reg; -}; - -struct s3c_cpufreq_config { - struct s3c_freq freq; - struct s3c_pllval pll; - struct s3c_clkdivs divs; - struct s3c_cpufreq_info *info; /* for core, not drivers */ - struct s3c_cpufreq_board *board; -}; - -/* s3c_cpufreq_board - * - * per-board configuraton information, such as memory refresh and - * how to initialise IO timings. - */ -struct s3c_cpufreq_board { - unsigned int refresh; /* refresh period in ns */ - unsigned int auto_io:1; /* automatically init io timings. */ - unsigned int need_io:1; /* set if needs io timing support. */ - - /* any non-zero field in here is taken as an upper limit. */ - struct s3c_freq max; /* frequency limits */ -}; - -/* Things depending on frequency scaling. */ -#ifdef CONFIG_CPU_FREQ_S3C -#define __init_or_cpufreq -#else -#define __init_or_cpufreq __init -#endif - -/* Board functions */ - -#ifdef CONFIG_CPU_FREQ_S3C -extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board); -#else - -static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) -{ - return 0; -} -#endif /* CONFIG_CPU_FREQ_S3C */ diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h deleted file mode 100644 index e62ae0fcfe5..00000000000 --- a/arch/arm/plat-s3c/include/plat/cpu.h +++ /dev/null @@ -1,71 +0,0 @@ -/* linux/arch/arm/plat-s3c/include/plat/cpu.h - * - * Copyright (c) 2004-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Header file for S3C24XX CPU support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* todo - fix when rmk changes iodescs to use `void __iomem *` */ - -#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } - -#ifndef MHZ -#define MHZ (1000*1000) -#endif - -#define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000) - -/* forward declaration */ -struct s3c24xx_uart_resources; -struct platform_device; -struct s3c2410_uartcfg; -struct map_desc; - -/* per-cpu initialisation function table. */ - -struct cpu_table { - unsigned long idcode; - unsigned long idmask; - void (*map_io)(void); - void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no); - void (*init_clocks)(int xtal); - int (*init)(void); - const char *name; -}; - -extern void s3c_init_cpu(unsigned long idcode, - struct cpu_table *cpus, unsigned int cputab_size); - -/* core initialisation functions */ - -extern void s3c24xx_init_irq(void); -extern void s3c64xx_init_irq(u32 vic0, u32 vic1); - -extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); -extern void s3c64xx_init_io(struct map_desc *mach_desc, int size); - -extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); - -extern void s3c24xx_init_clocks(int xtal); - -extern void s3c24xx_init_uartdevs(char *name, - struct s3c24xx_uart_resources *res, - struct s3c2410_uartcfg *cfg, int no); - -/* timer for 2410/2440 */ - -struct sys_timer; -extern struct sys_timer s3c24xx_timer; - -/* system device classes */ - -extern struct sysdev_class s3c2410_sysclass; -extern struct sysdev_class s3c2412_sysclass; -extern struct sysdev_class s3c2440_sysclass; -extern struct sysdev_class s3c2442_sysclass; -extern struct sysdev_class s3c2443_sysclass; diff --git a/arch/arm/plat-s3c/include/plat/debug-macro.S b/arch/arm/plat-s3c/include/plat/debug-macro.S deleted file mode 100644 index 3634d4e3708..00000000000 --- a/arch/arm/plat-s3c/include/plat/debug-macro.S +++ /dev/null @@ -1,75 +0,0 @@ -/* linux/include/asm-arm/plat-s3c/debug-macro.S - * - * Copyright 2005, 2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <plat/regs-serial.h> - -/* The S3C2440 implementations are used by default as they are the - * most widely re-used */ - - .macro fifo_level_s3c2440 rd, rx - ldr \rd, [ \rx, # S3C2410_UFSTAT ] - and \rd, \rd, #S3C2440_UFSTAT_TXMASK - .endm - -#ifndef fifo_level -#define fifo_level fifo_level_s3c2440 -#endif - - .macro fifo_full_s3c2440 rd, rx - ldr \rd, [ \rx, # S3C2410_UFSTAT ] - tst \rd, #S3C2440_UFSTAT_TXFULL - .endm - -#ifndef fifo_full -#define fifo_full fifo_full_s3c2440 -#endif - - .macro senduart,rd,rx - strb \rd, [\rx, # S3C2410_UTXH ] - .endm - - .macro busyuart, rd, rx - ldr \rd, [ \rx, # S3C2410_UFCON ] - tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? - beq 1001f @ - @ FIFO enabled... -1003: - fifo_full \rd, \rx - bne 1003b - b 1002f - -1001: - @ busy waiting for non fifo - ldr \rd, [ \rx, # S3C2410_UTRSTAT ] - tst \rd, #S3C2410_UTRSTAT_TXFE - beq 1001b - -1002: @ exit busyuart - .endm - - .macro waituart,rd,rx - ldr \rd, [ \rx, # S3C2410_UFCON ] - tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? - beq 1001f @ - @ FIFO enabled... -1003: - fifo_level \rd, \rx - teq \rd, #0 - bne 1003b - b 1002f -1001: - @ idle waiting for non fifo - ldr \rd, [ \rx, # S3C2410_UTRSTAT ] - tst \rd, #S3C2410_UTRSTAT_TXFE - beq 1001b - -1002: @ exit busyuart - .endm diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h deleted file mode 100644 index 6b1b5231511..00000000000 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ /dev/null @@ -1,54 +0,0 @@ -/* linux/include/asm-arm/plat-s3c24xx/devs.h - * - * Copyright (c) 2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Header file for s3c2410 standard platform devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ -#include <linux/platform_device.h> - -struct s3c24xx_uart_resources { - struct resource *resources; - unsigned long nr_resources; -}; - -extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; -extern struct s3c24xx_uart_resources s3c64xx_uart_resources[]; - -extern struct platform_device *s3c24xx_uart_devs[]; -extern struct platform_device *s3c24xx_uart_src[]; - -extern struct platform_device s3c_device_timer[]; - -extern struct platform_device s3c_device_fb; -extern struct platform_device s3c_device_usb; -extern struct platform_device s3c_device_lcd; -extern struct platform_device s3c_device_wdt; -extern struct platform_device s3c_device_i2c0; -extern struct platform_device s3c_device_i2c1; -extern struct platform_device s3c_device_iis; -extern struct platform_device s3c_device_rtc; -extern struct platform_device s3c_device_adc; -extern struct platform_device s3c_device_sdi; -extern struct platform_device s3c_device_hsmmc0; -extern struct platform_device s3c_device_hsmmc1; -extern struct platform_device s3c_device_hsmmc2; - -extern struct platform_device s3c_device_spi0; -extern struct platform_device s3c_device_spi1; - -extern struct platform_device s3c_device_nand; - -extern struct platform_device s3c_device_usbgadget; - -/* s3c2440 specific devices */ - -#ifdef CONFIG_CPU_S3C2440 - -extern struct platform_device s3c_device_camif; - -#endif diff --git a/arch/arm/plat-s3c/include/plat/fb.h b/arch/arm/plat-s3c/include/plat/fb.h deleted file mode 100644 index 214ff561b0d..00000000000 --- a/arch/arm/plat-s3c/include/plat/fb.h +++ /dev/null @@ -1,73 +0,0 @@ -/* linux/arch/arm/plat-s3c/include/plat/fb.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C - FB platform data definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_S3C_FB_H -#define __PLAT_S3C_FB_H __FILE__ - -/** - * struct s3c_fb_pd_win - per window setup data - * @win_mode: The display parameters to initialise (not for window 0) - * @virtual_x: The virtual X size. - * @virtual_y: The virtual Y size. - */ -struct s3c_fb_pd_win { - struct fb_videomode win_mode; - - unsigned short default_bpp; - unsigned short max_bpp; - unsigned short virtual_x; - unsigned short virtual_y; -}; - -/** - * struct s3c_fb_platdata - S3C driver platform specific information - * @setup_gpio: Setup the external GPIO pins to the right state to transfer - * the data from the display system to the connected display - * device. - * @vidcon0: The base vidcon0 values to control the panel data format. - * @vidcon1: The base vidcon1 values to control the panel data output. - * @win: The setup data for each hardware window, or NULL for unused. - * @display_mode: The LCD output display mode. - * - * The platform data supplies the video driver with all the information - * it requires to work with the display(s) attached to the machine. It - * controls the initial mode, the number of display windows (0 is always - * the base framebuffer) that are initialised etc. - * - */ -struct s3c_fb_platdata { - void (*setup_gpio)(void); - - struct s3c_fb_pd_win *win[S3C_FB_MAX_WIN]; - - u32 vidcon0; - u32 vidcon1; -}; - -/** - * s3c_fb_set_platdata() - Setup the FB device with platform data. - * @pd: The platform data to set. The data is copied from the passed structure - * so the machine data can mark the data __initdata so that any unused - * machines will end up dumping their data at runtime. - */ -extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd); - -/** - * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD - * - * Initialise the GPIO for an 24bpp LCD display on the RGB interface. - */ -extern void s3c64xx_fb_gpio_setup_24bpp(void); - -#endif /* __PLAT_S3C_FB_H */ diff --git a/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h deleted file mode 100644 index 652e2bbdaa2..00000000000 --- a/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h +++ /dev/null @@ -1,176 +0,0 @@ -/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C Platform - GPIO pin configuration helper definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* This is meant for core cpu support, machine or other driver files - * should not be including this header. - */ - -#ifndef __PLAT_GPIO_CFG_HELPERS_H -#define __PLAT_GPIO_CFG_HELPERS_H __FILE__ - -/* As a note, all gpio configuration functions are entered exclusively, either - * with the relevant lock held or the system prevented from doing anything else - * by disabling interrupts. -*/ - -static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip, - unsigned int off, unsigned int config) -{ - return (chip->config->set_config)(chip, off, config); -} - -static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull) -{ - return (chip->config->set_pull)(chip, off, pull); -} - -/** - * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration. - * @chip: The gpio chip that is being configured. - * @off: The offset for the GPIO being configured. - * @cfg: The configuration value to set. - * - * This helper deal with the GPIO cases where the control register - * has two bits of configuration per gpio, which have the following - * functions: - * 00 = input - * 01 = output - * 1x = special function -*/ -extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, - unsigned int off, unsigned int cfg); - -/** - * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A) - * @chip: The gpio chip that is being configured. - * @off: The offset for the GPIO being configured. - * @cfg: The configuration value to set. - * - * This helper deal with the GPIO cases where the control register - * has one bit of configuration for the gpio, where setting the bit - * means the pin is in special function mode and unset means output. -*/ -extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip, - unsigned int off, unsigned int cfg); - -/** - * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config. - * @chip: The gpio chip that is being configured. - * @off: The offset for the GPIO being configured. - * @cfg: The configuration value to set. - * - * This helper deal with the GPIO cases where the control register has 4 bits - * of control per GPIO, generally in the form of: - * 0000 = Input - * 0001 = Output - * others = Special functions (dependant on bank) - * - * Note, since the code to deal with the case where there are two control - * registers instead of one, we do not have a seperate set of functions for - * each case. -*/ -extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, - unsigned int off, unsigned int cfg); - - -/* Pull-{up,down} resistor controls. - * - * S3C2410,S3C2440,S3C24A0 = Pull-UP, - * S3C2412,S3C2413 = Pull-Down - * S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef] - * S3C2443 = Pull-Both [not same as S3C6400] - */ - -/** - * s3c_gpio_setpull_1up() - Pull configuration for choice of up or none. - * @chip: The gpio chip that is being configured. - * @off: The offset for the GPIO being configured. - * @param: pull: The pull mode being requested. - * - * This is a helper function for the case where we have GPIOs with one - * bit configuring the presence of a pull-up resistor. - */ -extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull); - -/** - * s3c_gpio_setpull_1down() - Pull configuration for choice of down or none - * @chip: The gpio chip that is being configured - * @off: The offset for the GPIO being configured - * @param: pull: The pull mode being requested - * - * This is a helper function for the case where we have GPIOs with one - * bit configuring the presence of a pull-down resistor. - */ -extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull); - -/** - * s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none - * @chip: The gpio chip that is being configured. - * @off: The offset for the GPIO being configured. - * @param: pull: The pull mode being requested. - * - * This is a helper function for the case where we have GPIOs with two - * bits configuring the presence of a pull resistor, in the following - * order: - * 00 = No pull resistor connected - * 01 = Pull-up resistor connected - * 10 = Pull-down resistor connected - */ -extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull); - - -/** - * s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none - * @chip: The gpio chip that the GPIO pin belongs to - * @off: The offset to the pin to get the configuration of. - * - * This helper function reads the state of the pull-{up,down} resistor for the - * given GPIO in the same case as s3c_gpio_setpull_upown. -*/ -extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, - unsigned int off); - -/** - * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443. - * @chip: The gpio chip that is being configured. - * @off: The offset for the GPIO being configured. - * @param: pull: The pull mode being requested. - * - * This is a helper function for the case where we have GPIOs with two - * bits configuring the presence of a pull resistor, in the following - * order: - * 00 = Pull-up resistor connected - * 10 = Pull-down resistor connected - * x1 = No pull up resistor - */ -extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull); - -/** - * s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors - * @chip: The gpio chip that the GPIO pin belongs to. - * @off: The offset to the pin to get the configuration of. - * - * This helper function reads the state of the pull-{up,down} resistor for the - * given GPIO in the same case as s3c_gpio_setpull_upown. -*/ -extern s3c_gpio_pull_t s3c_gpio_getpull_s3c24xx(struct s3c_gpio_chip *chip, - unsigned int off); - -#endif /* __PLAT_GPIO_CFG_HELPERS_H */ - diff --git a/arch/arm/plat-s3c/include/plat/gpio-cfg.h b/arch/arm/plat-s3c/include/plat/gpio-cfg.h deleted file mode 100644 index 29cd6a86cad..00000000000 --- a/arch/arm/plat-s3c/include/plat/gpio-cfg.h +++ /dev/null @@ -1,110 +0,0 @@ -/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C Platform - GPIO pin configuration - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* This file contains the necessary definitions to get the basic gpio - * pin configuration done such as setting a pin to input or output or - * changing the pull-{up,down} configurations. - */ - -/* Note, this interface is being added to the s3c64xx arch first and will - * be added to the s3c24xx systems later. - */ - -#ifndef __PLAT_GPIO_CFG_H -#define __PLAT_GPIO_CFG_H __FILE__ - -typedef unsigned int __bitwise__ s3c_gpio_pull_t; - -/* forward declaration if gpio-core.h hasn't been included */ -struct s3c_gpio_chip; - -/** - * struct s3c_gpio_cfg GPIO configuration - * @cfg_eint: Configuration setting when used for external interrupt source - * @get_pull: Read the current pull configuration for the GPIO - * @set_pull: Set the current pull configuraiton for the GPIO - * @set_config: Set the current configuration for the GPIO - * @get_config: Read the current configuration for the GPIO - * - * Each chip can have more than one type of GPIO bank available and some - * have different capabilites even when they have the same control register - * layouts. Provide an point to vector control routine and provide any - * per-bank configuration information that other systems such as the - * external interrupt code will need. - */ -struct s3c_gpio_cfg { - unsigned int cfg_eint; - - s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs); - int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs, - s3c_gpio_pull_t pull); - - unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs); - int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs, - unsigned config); -}; - -#define S3C_GPIO_SPECIAL_MARK (0xfffffff0) -#define S3C_GPIO_SPECIAL(x) (S3C_GPIO_SPECIAL_MARK | (x)) - -/* Defines for generic pin configurations */ -#define S3C_GPIO_INPUT (S3C_GPIO_SPECIAL(0)) -#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1)) -#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x)) - -#define s3c_gpio_is_cfg_special(_cfg) \ - (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK) - -/** - * s3c_gpio_cfgpin() - Change the GPIO function of a pin. - * @pin pin The pin number to configure. - * @pin to The configuration for the pin's function. - * - * Configure which function is actually connected to the external - * pin, such as an gpio input, output or some form of special function - * connected to an internal peripheral block. - */ -extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to); - -/* Define values for the pull-{up,down} available for each gpio pin. - * - * These values control the state of the weak pull-{up,down} resistors - * available on most pins on the S3C series. Not all chips support both - * up or down settings, and it may be dependant on the chip that is being - * used to whether the particular mode is available. - */ -#define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00) -#define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01) -#define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x02) - -/** - * s3c_gpio_setpull() - set the state of a gpio pin pull resistor - * @pin: The pin number to configure the pull resistor. - * @pull: The configuration for the pull resistor. - * - * This function sets the state of the pull-{up,down} resistor for the - * specified pin. It will return 0 if successfull, or a negative error - * code if the pin cannot support the requested pull setting. -*/ -extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull); - -/** - * s3c_gpio_getpull() - get the pull resistor state of a gpio pin - * @pin: The pin number to get the settings for - * - * Read the pull resistor value for the specified pin. -*/ -extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin); - -#endif /* __PLAT_GPIO_CFG_H */ diff --git a/arch/arm/plat-s3c/include/plat/gpio-core.h b/arch/arm/plat-s3c/include/plat/gpio-core.h deleted file mode 100644 index 2fc60a580ac..00000000000 --- a/arch/arm/plat-s3c/include/plat/gpio-core.h +++ /dev/null @@ -1,77 +0,0 @@ -/* linux/arch/arm/plat-s3c/include/plat/gpio-core.h - * - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C Platform - GPIO core - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* Define the core gpiolib support functions that the s3c platforms may - * need to extend or change depending on the hardware and the s3c chip - * selected at build or found at run time. - * - * These definitions are not intended for driver inclusion, there is - * nothing here that should not live outside the platform and core - * specific code. -*/ - -struct s3c_gpio_cfg; - -/** - * struct s3c_gpio_chip - wrapper for specific implementation of gpio - * @chip: The chip structure to be exported via gpiolib. - * @base: The base pointer to the gpio configuration registers. - * @config: special function and pull-resistor control information. - * - * This wrapper provides the necessary information for the Samsung - * specific gpios being registered with gpiolib. - */ -struct s3c_gpio_chip { - struct gpio_chip chip; - struct s3c_gpio_cfg *config; - void __iomem *base; -}; - -static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc) -{ - return container_of(gpc, struct s3c_gpio_chip, chip); -} - -/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip. - * @chip: The chip to register - * - * This is a wrapper to gpiochip_add() that takes our specific gpio chip - * information and makes the necessary alterations for the platform and - * notes the information for use with the configuration systems and any - * other parts of the system. - */ -extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip); - -/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios - * for use with the configuration calls, and other parts of the s3c gpiolib - * support code. - * - * Not all s3c support code will need this, as some configurations of cpu - * may only support one or two different configuration options and have an - * easy gpio to s3c_gpio_chip mapping function. If this is the case, then - * the machine support file should provide its own s3c_gpiolib_getchip() - * and any other necessary functions. - */ - -#ifdef CONFIG_S3C_GPIO_TRACK -extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; - -static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip) -{ - return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL; -} -#else -/* machine specific code should provide s3c_gpiolib_getchip */ - -static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } -#endif diff --git a/arch/arm/plat-s3c/include/plat/iic-core.h b/arch/arm/plat-s3c/include/plat/iic-core.h deleted file mode 100644 index 36397ca2096..00000000000 --- a/arch/arm/plat-s3c/include/plat/iic-core.h +++ /dev/null @@ -1,35 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/iic-core.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C - I2C Controller core functions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_IIC_CORE_H -#define __ASM_ARCH_IIC_CORE_H __FILE__ - -/* These functions are only for use with the core support code, such as - * the cpu specific initialisation code - */ - -/* re-define device name depending on support. */ -static inline void s3c_i2c0_setname(char *name) -{ - /* currently this device is always compiled in */ - s3c_device_i2c0.name = name; -} - -static inline void s3c_i2c1_setname(char *name) -{ -#ifdef CONFIG_S3C_DEV_I2C1 - s3c_device_i2c1.name = name; -#endif -} - -#endif /* __ASM_ARCH_IIC_H */ diff --git a/arch/arm/plat-s3c/include/plat/iic.h b/arch/arm/plat-s3c/include/plat/iic.h deleted file mode 100644 index dc1dfcb9bc6..00000000000 --- a/arch/arm/plat-s3c/include/plat/iic.h +++ /dev/null @@ -1,57 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/iic.h - * - * Copyright (c) 2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - I2C Controller platfrom_device info - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_IIC_H -#define __ASM_ARCH_IIC_H __FILE__ - -#define S3C_IICFLG_FILTER (1<<0) /* enable s3c2440 filter */ - -/* Notes: - * 1) All frequencies are expressed in Hz - * 2) A value of zero is `do not care` -*/ - -struct s3c2410_platform_i2c { - int bus_num; /* bus number to use */ - unsigned int flags; - unsigned int slave_addr; /* slave address for controller */ - unsigned long bus_freq; /* standard bus frequency */ - unsigned long max_freq; /* max frequency for the bus */ - unsigned long min_freq; /* min frequency for the bus */ - unsigned int sda_delay; /* pclks (s3c2440 only) */ - - void (*cfg_gpio)(struct platform_device *dev); -}; - -/** - * s3c_i2c0_set_platdata - set platform data for i2c0 device - * @i2c: The platform data to set, or NULL for default data. - * - * Register the given platform data for use with the i2c0 device. This - * call copies the platform data, so the caller can use __initdata for - * their copy. - * - * This call will set cfg_gpio if is null to the default platform - * implementation. - * - * Any user of s3c_device_i2c0 should call this, even if it is with - * NULL to ensure that the device is given the default platform data - * as the driver will no longer carry defaults. - */ -extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c); -extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c); - -/* defined by architecture to configure gpio */ -extern void s3c_i2c0_cfg_gpio(struct platform_device *dev); -extern void s3c_i2c1_cfg_gpio(struct platform_device *dev); - -#endif /* __ASM_ARCH_IIC_H */ diff --git a/arch/arm/plat-s3c/include/plat/map-base.h b/arch/arm/plat-s3c/include/plat/map-base.h deleted file mode 100644 index b84289d32a5..00000000000 --- a/arch/arm/plat-s3c/include/plat/map-base.h +++ /dev/null @@ -1,40 +0,0 @@ -/* linux/include/asm-arm/plat-s3c/map.h - * - * Copyright 2003, 2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C - Memory map definitions (virtual addresses) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_PLAT_MAP_H -#define __ASM_PLAT_MAP_H __FILE__ - -/* Fit all our registers in at 0xF4000000 upwards, trying to use as - * little of the VA space as possible so vmalloc and friends have a - * better chance of getting memory. - * - * we try to ensure stuff like the IRQ registers are available for - * an single MOVS instruction (ie, only 8 bits of set data) - */ - -#define S3C_ADDR_BASE (0xF4000000) - -#ifndef __ASSEMBLY__ -#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) -#else -#define S3C_ADDR(x) (S3C_ADDR_BASE + (x)) -#endif - -#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ -#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ -#define S3C_VA_MEM S3C_ADDR(0x00200000) /* system control */ -#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ -#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ -#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ - -#endif /* __ASM_PLAT_MAP_H */ diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h deleted file mode 100644 index f4dcd14af05..00000000000 --- a/arch/arm/plat-s3c/include/plat/nand.h +++ /dev/null @@ -1,50 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/nand.h - * - * Copyright (c) 2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - NAND device controller platfrom_device info - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* struct s3c2410_nand_set - * - * define an set of one or more nand chips registered with an unique mtd - * - * nr_chips = number of chips in this set - * nr_partitions = number of partitions pointed to be partitoons (or zero) - * name = name of set (optional) - * nr_map = map for low-layer logical to physical chip numbers (option) - * partitions = mtd partition list -*/ - -struct s3c2410_nand_set { - unsigned int disable_ecc : 1; - - int nr_chips; - int nr_partitions; - char *name; - int *nr_map; - struct mtd_partition *partitions; - struct nand_ecclayout *ecc_layout; -}; - -struct s3c2410_platform_nand { - /* timing information for controller, all times in nanoseconds */ - - int tacls; /* time for active CLE/ALE to nWE/nOE */ - int twrph0; /* active time for nWE/nOE */ - int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */ - - unsigned int ignore_unset_ecc : 1; - - int nr_sets; - struct s3c2410_nand_set *sets; - - void (*select_chip)(struct s3c2410_nand_set *, - int chip); -}; - diff --git a/arch/arm/plat-s3c/include/plat/regs-ac97.h b/arch/arm/plat-s3c/include/plat/regs-ac97.h deleted file mode 100644 index c3878f7acb8..00000000000 --- a/arch/arm/plat-s3c/include/plat/regs-ac97.h +++ /dev/null @@ -1,67 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-ac97.h - * - * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2440 AC97 Controller -*/ - -#ifndef __ASM_ARCH_REGS_AC97_H -#define __ASM_ARCH_REGS_AC97_H __FILE__ - -#define S3C_AC97_GLBCTRL (0x00) - -#define S3C_AC97_GLBCTRL_CODECREADYIE (1<<22) -#define S3C_AC97_GLBCTRL_PCMOUTURIE (1<<21) -#define S3C_AC97_GLBCTRL_PCMINORIE (1<<20) -#define S3C_AC97_GLBCTRL_MICINORIE (1<<19) -#define S3C_AC97_GLBCTRL_PCMOUTTIE (1<<18) -#define S3C_AC97_GLBCTRL_PCMINTIE (1<<17) -#define S3C_AC97_GLBCTRL_MICINTIE (1<<16) -#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF (0<<12) -#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO (1<<12) -#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA (2<<12) -#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK (3<<12) -#define S3C_AC97_GLBCTRL_PCMINTM_OFF (0<<10) -#define S3C_AC97_GLBCTRL_PCMINTM_PIO (1<<10) -#define S3C_AC97_GLBCTRL_PCMINTM_DMA (2<<10) -#define S3C_AC97_GLBCTRL_PCMINTM_MASK (3<<10) -#define S3C_AC97_GLBCTRL_MICINTM_OFF (0<<8) -#define S3C_AC97_GLBCTRL_MICINTM_PIO (1<<8) -#define S3C_AC97_GLBCTRL_MICINTM_DMA (2<<8) -#define S3C_AC97_GLBCTRL_MICINTM_MASK (3<<8) -#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE (1<<3) -#define S3C_AC97_GLBCTRL_ACLINKON (1<<2) -#define S3C_AC97_GLBCTRL_WARMRESET (1<<1) -#define S3C_AC97_GLBCTRL_COLDRESET (1<<0) - -#define S3C_AC97_GLBSTAT (0x04) - -#define S3C_AC97_GLBSTAT_CODECREADY (1<<22) -#define S3C_AC97_GLBSTAT_PCMOUTUR (1<<21) -#define S3C_AC97_GLBSTAT_PCMINORI (1<<20) -#define S3C_AC97_GLBSTAT_MICINORI (1<<19) -#define S3C_AC97_GLBSTAT_PCMOUTTI (1<<18) -#define S3C_AC97_GLBSTAT_PCMINTI (1<<17) -#define S3C_AC97_GLBSTAT_MICINTI (1<<16) -#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE (0<<0) -#define S3C_AC97_GLBSTAT_MAINSTATE_INIT (1<<0) -#define S3C_AC97_GLBSTAT_MAINSTATE_READY (2<<0) -#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE (3<<0) -#define S3C_AC97_GLBSTAT_MAINSTATE_LP (4<<0) -#define S3C_AC97_GLBSTAT_MAINSTATE_WARM (5<<0) - -#define S3C_AC97_CODEC_CMD (0x08) - -#define S3C_AC97_CODEC_CMD_READ (1<<23) - -#define S3C_AC97_STAT (0x0c) -#define S3C_AC97_PCM_ADDR (0x10) -#define S3C_AC97_PCM_DATA (0x18) -#define S3C_AC97_MIC_DATA (0x1C) - -#endif /* __ASM_ARCH_REGS_AC97_H */ diff --git a/arch/arm/plat-s3c/include/plat/regs-adc.h b/arch/arm/plat-s3c/include/plat/regs-adc.h deleted file mode 100644 index 4323cccc86c..00000000000 --- a/arch/arm/plat-s3c/include/plat/regs-adc.h +++ /dev/null @@ -1,60 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-adc.h - * - * Copyright (c) 2004 Shannon Holland <holland@loser.net> - * - * This program is free software; yosu can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 ADC registers -*/ - -#ifndef __ASM_ARCH_REGS_ADC_H -#define __ASM_ARCH_REGS_ADC_H "regs-adc.h" - -#define S3C2410_ADCREG(x) (x) - -#define S3C2410_ADCCON S3C2410_ADCREG(0x00) -#define S3C2410_ADCTSC S3C2410_ADCREG(0x04) -#define S3C2410_ADCDLY S3C2410_ADCREG(0x08) -#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) -#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) - - -/* ADCCON Register Bits */ -#define S3C2410_ADCCON_ECFLG (1<<15) -#define S3C2410_ADCCON_PRSCEN (1<<14) -#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) -#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) -#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) -#define S3C2410_ADCCON_MUXMASK (0x7<<3) -#define S3C2410_ADCCON_STDBM (1<<2) -#define S3C2410_ADCCON_READ_START (1<<1) -#define S3C2410_ADCCON_ENABLE_START (1<<0) -#define S3C2410_ADCCON_STARTMASK (0x3<<0) - - -/* ADCTSC Register Bits */ -#define S3C2410_ADCTSC_YM_SEN (1<<7) -#define S3C2410_ADCTSC_YP_SEN (1<<6) -#define S3C2410_ADCTSC_XM_SEN (1<<5) -#define S3C2410_ADCTSC_XP_SEN (1<<4) -#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3) -#define S3C2410_ADCTSC_AUTO_PST (1<<2) -#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0) - -/* ADCDAT0 Bits */ -#define S3C2410_ADCDAT0_UPDOWN (1<<15) -#define S3C2410_ADCDAT0_AUTO_PST (1<<14) -#define S3C2410_ADCDAT0_XY_PST (0x3<<12) -#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF) - -/* ADCDAT1 Bits */ -#define S3C2410_ADCDAT1_UPDOWN (1<<15) -#define S3C2410_ADCDAT1_AUTO_PST (1<<14) -#define S3C2410_ADCDAT1_XY_PST (0x3<<12) -#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF) - -#endif /* __ASM_ARCH_REGS_ADC_H */ - - diff --git a/arch/arm/plat-s3c/include/plat/regs-fb.h b/arch/arm/plat-s3c/include/plat/regs-fb.h deleted file mode 100644 index e9ee599d430..00000000000 --- a/arch/arm/plat-s3c/include/plat/regs-fb.h +++ /dev/null @@ -1,366 +0,0 @@ -/* arch/arm/plat-s3c/include/plat/regs-fb.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C Platform - new-style framebuffer register definitions - * - * This is the register set for the new style framebuffer interface - * found from the S3C2443 onwards into the S3C2416, S3C2450 and the - * S3C64XX series such as the S3C6400 and S3C6410. - * - * The file does not contain the cpu specific items which are based on - * whichever architecture is selected, it only contains the core of the - * register set. See <mach/regs-fb.h> to get the specifics. - * - * Note, we changed to using regs-fb.h as it avoids any clashes with - * the original regs-lcd.h so out of the way of regs-lcd.h as well as - * indicating the newer block is much more than just an LCD interface. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* Please do not include this file directly, use <mach/regs-fb.h> to - * ensure all the localised SoC support is included as necessary. -*/ - -/* VIDCON0 */ - -#define VIDCON0 (0x00) -#define VIDCON0_INTERLACE (1 << 29) -#define VIDCON0_VIDOUT_MASK (0x3 << 26) -#define VIDCON0_VIDOUT_SHIFT (26) -#define VIDCON0_VIDOUT_RGB (0x0 << 26) -#define VIDCON0_VIDOUT_TV (0x1 << 26) -#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26) -#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26) - -#define VIDCON0_L1_DATA_MASK (0x7 << 23) -#define VIDCON0_L1_DATA_SHIFT (23) -#define VIDCON0_L1_DATA_16BPP (0x0 << 23) -#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23) -#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23) -#define VIDCON0_L1_DATA_24BPP (0x3 << 23) -#define VIDCON0_L1_DATA_18BPP (0x4 << 23) -#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23) - -#define VIDCON0_L0_DATA_MASK (0x7 << 20) -#define VIDCON0_L0_DATA_SHIFT (20) -#define VIDCON0_L0_DATA_16BPP (0x0 << 20) -#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20) -#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20) -#define VIDCON0_L0_DATA_24BPP (0x3 << 20) -#define VIDCON0_L0_DATA_18BPP (0x4 << 20) -#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20) - -#define VIDCON0_PNRMODE_MASK (0x3 << 17) -#define VIDCON0_PNRMODE_SHIFT (17) -#define VIDCON0_PNRMODE_RGB (0x0 << 17) -#define VIDCON0_PNRMODE_BGR (0x1 << 17) -#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17) -#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17) - -#define VIDCON0_CLKVALUP (1 << 16) -#define VIDCON0_CLKVAL_F_MASK (0xff << 6) -#define VIDCON0_CLKVAL_F_SHIFT (6) -#define VIDCON0_CLKVAL_F_LIMIT (0xff) -#define VIDCON0_CLKVAL_F(_x) ((_x) << 6) -#define VIDCON0_VLCKFREE (1 << 5) -#define VIDCON0_CLKDIR (1 << 4) - -#define VIDCON0_CLKSEL_MASK (0x3 << 2) -#define VIDCON0_CLKSEL_SHIFT (2) -#define VIDCON0_CLKSEL_HCLK (0x0 << 2) -#define VIDCON0_CLKSEL_LCD (0x1 << 2) -#define VIDCON0_CLKSEL_27M (0x3 << 2) - -#define VIDCON0_ENVID (1 << 1) -#define VIDCON0_ENVID_F (1 << 0) - -#define VIDCON1 (0x04) -#define VIDCON1_LINECNT_MASK (0x7ff << 16) -#define VIDCON1_LINECNT_SHIFT (16) -#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff) -#define VIDCON1_VSTATUS_MASK (0x3 << 13) -#define VIDCON1_VSTATUS_SHIFT (13) -#define VIDCON1_VSTATUS_VSYNC (0x0 << 13) -#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13) -#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13) -#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13) - -#define VIDCON1_INV_VCLK (1 << 7) -#define VIDCON1_INV_HSYNC (1 << 6) -#define VIDCON1_INV_VSYNC (1 << 5) -#define VIDCON1_INV_VDEN (1 << 4) - -/* VIDCON2 */ - -#define VIDCON2 (0x08) -#define VIDCON2_EN601 (1 << 23) -#define VIDCON2_TVFMTSEL_SW (1 << 14) - -#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12) -#define VIDCON2_TVFMTSEL1_SHIFT (12) -#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12) -#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12) -#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12) - -#define VIDCON2_ORGYCbCr (1 << 8) -#define VIDCON2_YUVORDCrCb (1 << 7) - -/* VIDTCON0 */ - -#define VIDTCON0_VBPDE_MASK (0xff << 24) -#define VIDTCON0_VBPDE_SHIFT (24) -#define VIDTCON0_VBPDE_LIMIT (0xff) -#define VIDTCON0_VBPDE(_x) ((_x) << 24) - -#define VIDTCON0_VBPD_MASK (0xff << 16) -#define VIDTCON0_VBPD_SHIFT (16) -#define VIDTCON0_VBPD_LIMIT (0xff) -#define VIDTCON0_VBPD(_x) ((_x) << 16) - -#define VIDTCON0_VFPD_MASK (0xff << 8) -#define VIDTCON0_VFPD_SHIFT (8) -#define VIDTCON0_VFPD_LIMIT (0xff) -#define VIDTCON0_VFPD(_x) ((_x) << 8) - -#define VIDTCON0_VSPW_MASK (0xff << 0) -#define VIDTCON0_VSPW_SHIFT (0) -#define VIDTCON0_VSPW_LIMIT (0xff) -#define VIDTCON0_VSPW(_x) ((_x) << 0) - -/* VIDTCON1 */ - -#define VIDTCON1_VFPDE_MASK (0xff << 24) -#define VIDTCON1_VFPDE_SHIFT (24) -#define VIDTCON1_VFPDE_LIMIT (0xff) -#define VIDTCON1_VFPDE(_x) ((_x) << 24) - -#define VIDTCON1_HBPD_MASK (0xff << 16) -#define VIDTCON1_HBPD_SHIFT (16) -#define VIDTCON1_HBPD_LIMIT (0xff) -#define VIDTCON1_HBPD(_x) ((_x) << 16) - -#define VIDTCON1_HFPD_MASK (0xff << 8) -#define VIDTCON1_HFPD_SHIFT (8) -#define VIDTCON1_HFPD_LIMIT (0xff) -#define VIDTCON1_HFPD(_x) ((_x) << 8) - -#define VIDTCON1_HSPW_MASK (0xff << 0) -#define VIDTCON1_HSPW_SHIFT (0) -#define VIDTCON1_HSPW_LIMIT (0xff) -#define VIDTCON1_HSPW(_x) ((_x) << 0) - -#define VIDTCON2 (0x18) -#define VIDTCON2_LINEVAL_MASK (0x7ff << 11) -#define VIDTCON2_LINEVAL_SHIFT (11) -#define VIDTCON2_LINEVAL_LIMIT (0x7ff) -#define VIDTCON2_LINEVAL(_x) ((_x) << 11) - -#define VIDTCON2_HOZVAL_MASK (0x7ff << 0) -#define VIDTCON2_HOZVAL_SHIFT (0) -#define VIDTCON2_HOZVAL_LIMIT (0x7ff) -#define VIDTCON2_HOZVAL(_x) ((_x) << 0) - -/* WINCONx */ - - -#define WINCONx_BITSWP (1 << 18) -#define WINCONx_BYTSWP (1 << 17) -#define WINCONx_HAWSWP (1 << 16) -#define WINCONx_BURSTLEN_MASK (0x3 << 9) -#define WINCONx_BURSTLEN_SHIFT (9) -#define WINCONx_BURSTLEN_16WORD (0x0 << 9) -#define WINCONx_BURSTLEN_8WORD (0x1 << 9) -#define WINCONx_BURSTLEN_4WORD (0x2 << 9) - -#define WINCONx_ENWIN (1 << 0) -#define WINCON0_BPPMODE_MASK (0xf << 2) -#define WINCON0_BPPMODE_SHIFT (2) -#define WINCON0_BPPMODE_1BPP (0x0 << 2) -#define WINCON0_BPPMODE_2BPP (0x1 << 2) -#define WINCON0_BPPMODE_4BPP (0x2 << 2) -#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2) -#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2) -#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2) -#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2) -#define WINCON0_BPPMODE_24BPP_888 (0xb << 2) - -#define WINCON1_BLD_PIX (1 << 6) - -#define WINCON1_ALPHA_SEL (1 << 1) -#define WINCON1_BPPMODE_MASK (0xf << 2) -#define WINCON1_BPPMODE_SHIFT (2) -#define WINCON1_BPPMODE_1BPP (0x0 << 2) -#define WINCON1_BPPMODE_2BPP (0x1 << 2) -#define WINCON1_BPPMODE_4BPP (0x2 << 2) -#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2) -#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2) -#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2) -#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2) -#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2) -#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2) -#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2) -#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2) -#define WINCON1_BPPMODE_24BPP_888 (0xb << 2) -#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2) -#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2) -#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2) - - -#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) -#define VIDOSDxA_TOPLEFT_X_SHIFT (11) -#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff) -#define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11) - -#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0) -#define VIDOSDxA_TOPLEFT_Y_SHIFT (0) -#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff) -#define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0) - -#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11) -#define VIDOSDxB_BOTRIGHT_X_SHIFT (11) -#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff) -#define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11) - -#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0) -#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0) -#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff) -#define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0) - -/* For VIDOSD[1..4]C */ -#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20) -#define VIDISD14C_ALPHA0_G_MASK (0xf << 16) -#define VIDISD14C_ALPHA0_G_SHIFT (16) -#define VIDISD14C_ALPHA0_G_LIMIT (0xf) -#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16) -#define VIDISD14C_ALPHA0_B_MASK (0xf << 12) -#define VIDISD14C_ALPHA0_B_SHIFT (12) -#define VIDISD14C_ALPHA0_B_LIMIT (0xf) -#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12) -#define VIDISD14C_ALPHA1_R_MASK (0xf << 8) -#define VIDISD14C_ALPHA1_R_SHIFT (8) -#define VIDISD14C_ALPHA1_R_LIMIT (0xf) -#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8) -#define VIDISD14C_ALPHA1_G_MASK (0xf << 4) -#define VIDISD14C_ALPHA1_G_SHIFT (4) -#define VIDISD14C_ALPHA1_G_LIMIT (0xf) -#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4) -#define VIDISD14C_ALPHA1_B_MASK (0xf << 0) -#define VIDISD14C_ALPHA1_B_SHIFT (0) -#define VIDISD14C_ALPHA1_B_LIMIT (0xf) -#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0) - -/* Video buffer addresses */ -#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8)) -#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8)) -#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8)) -#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8)) -#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4)) - -#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13) -#define VIDW_BUF_SIZE_OFFSET_SHIFT (13) -#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff) -#define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13) - -#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0) -#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0) -#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff) -#define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0) - -/* Interrupt controls and status */ - -#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20) -#define VIDINTCON0_FIFOINTERVAL_SHIFT (20) -#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f) -#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20) - -#define VIDINTCON0_INT_SYSMAINCON (1 << 19) -#define VIDINTCON0_INT_SYSSUBCON (1 << 18) -#define VIDINTCON0_INT_I80IFDONE (1 << 17) - -#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15) -#define VIDINTCON0_FRAMESEL0_SHIFT (15) -#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15) -#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15) -#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15) -#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15) - -#define VIDINTCON0_FRAMESEL1 (1 << 14) -#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 14) -#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 14) -#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 14) -#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 14) - -#define VIDINTCON0_INT_FRAME (1 << 12) -#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5) -#define VIDINTCON0_FIFIOSEL_SHIFT (5) -#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5) -#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5) - -#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2) -#define VIDINTCON0_FIFOLEVEL_SHIFT (2) -#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2) -#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2) -#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2) -#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2) -#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2) - -#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0) -#define VIDINTCON0_INT_FIFO_SHIFT (0) -#define VIDINTCON0_INT_ENABLE (1 << 0) - -#define VIDINTCON1 (0x134) -#define VIDINTCON1_INT_I180 (1 << 2) -#define VIDINTCON1_INT_FRAME (1 << 1) -#define VIDINTCON1_INT_FIFO (1 << 0) - -/* Window colour-key control registers */ - -#define WxKEYCON0_KEYBL_EN (1 << 26) -#define WxKEYCON0_KEYEN_F (1 << 25) -#define WxKEYCON0_DIRCON (1 << 24) -#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0) -#define WxKEYCON0_COMPKEY_SHIFT (0) -#define WxKEYCON0_COMPKEY_LIMIT (0xffffff) -#define WxKEYCON0_COMPKEY(_x) ((_x) << 0) -#define WxKEYCON1_COLVAL_MASK (0xffffff << 0) -#define WxKEYCON1_COLVAL_SHIFT (0) -#define WxKEYCON1_COLVAL_LIMIT (0xffffff) -#define WxKEYCON1_COLVAL(_x) ((_x) << 0) - - -/* Window blanking (MAP) */ - -#define WINxMAP_MAP (1 << 24) -#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0) -#define WINxMAP_MAP_COLOUR_SHIFT (0) -#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff) -#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0) - -#define WPALCON_PAL_UPDATE (1 << 9) -#define WPALCON_W1PAL_MASK (0x7 << 3) -#define WPALCON_W1PAL_SHIFT (3) -#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3) -#define WPALCON_W1PAL_24BPP (0x1 << 3) -#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3) -#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3) -#define WPALCON_W1PAL_18BPP (0x4 << 3) -#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3) -#define WPALCON_W1PAL_16BPP_565 (0x6 << 3) - -#define WPALCON_W0PAL_MASK (0x7 << 0) -#define WPALCON_W0PAL_SHIFT (0) -#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0) -#define WPALCON_W0PAL_24BPP (0x1 << 0) -#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0) -#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0) -#define WPALCON_W0PAL_18BPP (0x4 << 0) -#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0) -#define WPALCON_W0PAL_16BPP_565 (0x6 << 0) - diff --git a/arch/arm/plat-s3c/include/plat/regs-iic.h b/arch/arm/plat-s3c/include/plat/regs-iic.h deleted file mode 100644 index 2f7c17de8ac..00000000000 --- a/arch/arm/plat-s3c/include/plat/regs-iic.h +++ /dev/null @@ -1,56 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-iic.h - * - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 I2C Controller -*/ - -#ifndef __ASM_ARCH_REGS_IIC_H -#define __ASM_ARCH_REGS_IIC_H __FILE__ - -/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */ - -#define S3C2410_IICREG(x) (x) - -#define S3C2410_IICCON S3C2410_IICREG(0x00) -#define S3C2410_IICSTAT S3C2410_IICREG(0x04) -#define S3C2410_IICADD S3C2410_IICREG(0x08) -#define S3C2410_IICDS S3C2410_IICREG(0x0C) -#define S3C2440_IICLC S3C2410_IICREG(0x10) - -#define S3C2410_IICCON_ACKEN (1<<7) -#define S3C2410_IICCON_TXDIV_16 (0<<6) -#define S3C2410_IICCON_TXDIV_512 (1<<6) -#define S3C2410_IICCON_IRQEN (1<<5) -#define S3C2410_IICCON_IRQPEND (1<<4) -#define S3C2410_IICCON_SCALE(x) ((x)&15) -#define S3C2410_IICCON_SCALEMASK (0xf) - -#define S3C2410_IICSTAT_MASTER_RX (2<<6) -#define S3C2410_IICSTAT_MASTER_TX (3<<6) -#define S3C2410_IICSTAT_SLAVE_RX (0<<6) -#define S3C2410_IICSTAT_SLAVE_TX (1<<6) -#define S3C2410_IICSTAT_MODEMASK (3<<6) - -#define S3C2410_IICSTAT_START (1<<5) -#define S3C2410_IICSTAT_BUSBUSY (1<<5) -#define S3C2410_IICSTAT_TXRXEN (1<<4) -#define S3C2410_IICSTAT_ARBITR (1<<3) -#define S3C2410_IICSTAT_ASSLAVE (1<<2) -#define S3C2410_IICSTAT_ADDR0 (1<<1) -#define S3C2410_IICSTAT_LASTBIT (1<<0) - -#define S3C2410_IICLC_SDA_DELAY0 (0 << 0) -#define S3C2410_IICLC_SDA_DELAY5 (1 << 0) -#define S3C2410_IICLC_SDA_DELAY10 (2 << 0) -#define S3C2410_IICLC_SDA_DELAY15 (3 << 0) -#define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0) - -#define S3C2410_IICLC_FILTER_ON (1<<2) - -#endif /* __ASM_ARCH_REGS_IIC_H */ diff --git a/arch/arm/plat-s3c/include/plat/regs-irqtype.h b/arch/arm/plat-s3c/include/plat/regs-irqtype.h deleted file mode 100644 index c63cd3fc5ad..00000000000 --- a/arch/arm/plat-s3c/include/plat/regs-irqtype.h +++ /dev/null @@ -1,21 +0,0 @@ -/* arch/arm/plat-s3c/include/plat/regs-irqtype.h - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C - IRQ detection types. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* values for S3C2410_EXTINT0/1/2 and other cpus in the series, including - * the S3C64XX -*/ -#define S3C2410_EXTINT_LOWLEV (0x00) -#define S3C2410_EXTINT_HILEV (0x01) -#define S3C2410_EXTINT_FALLEDGE (0x02) -#define S3C2410_EXTINT_RISEEDGE (0x04) -#define S3C2410_EXTINT_BOTHEDGE (0x06) diff --git a/arch/arm/plat-s3c/include/plat/regs-nand.h b/arch/arm/plat-s3c/include/plat/regs-nand.h deleted file mode 100644 index b2caa4bca27..00000000000 --- a/arch/arm/plat-s3c/include/plat/regs-nand.h +++ /dev/null @@ -1,123 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-nand.h - * - * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 NAND register definitions -*/ - -#ifndef __ASM_ARM_REGS_NAND -#define __ASM_ARM_REGS_NAND - - -#define S3C2410_NFREG(x) (x) - -#define S3C2410_NFCONF S3C2410_NFREG(0x00) -#define S3C2410_NFCMD S3C2410_NFREG(0x04) -#define S3C2410_NFADDR S3C2410_NFREG(0x08) -#define S3C2410_NFDATA S3C2410_NFREG(0x0C) -#define S3C2410_NFSTAT S3C2410_NFREG(0x10) -#define S3C2410_NFECC S3C2410_NFREG(0x14) - -#define S3C2440_NFCONT S3C2410_NFREG(0x04) -#define S3C2440_NFCMD S3C2410_NFREG(0x08) -#define S3C2440_NFADDR S3C2410_NFREG(0x0C) -#define S3C2440_NFDATA S3C2410_NFREG(0x10) -#define S3C2440_NFECCD0 S3C2410_NFREG(0x14) -#define S3C2440_NFECCD1 S3C2410_NFREG(0x18) -#define S3C2440_NFECCD S3C2410_NFREG(0x1C) -#define S3C2440_NFSTAT S3C2410_NFREG(0x20) -#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24) -#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28) -#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C) -#define S3C2440_NFMECC1 S3C2410_NFREG(0x30) -#define S3C2440_NFSECC S3C2410_NFREG(0x34) -#define S3C2440_NFSBLK S3C2410_NFREG(0x38) -#define S3C2440_NFEBLK S3C2410_NFREG(0x3C) - -#define S3C2412_NFSBLK S3C2410_NFREG(0x20) -#define S3C2412_NFEBLK S3C2410_NFREG(0x24) -#define S3C2412_NFSTAT S3C2410_NFREG(0x28) -#define S3C2412_NFMECC_ERR0 S3C2410_NFREG(0x2C) -#define S3C2412_NFMECC_ERR1 S3C2410_NFREG(0x30) -#define S3C2412_NFMECC0 S3C2410_NFREG(0x34) -#define S3C2412_NFMECC1 S3C2410_NFREG(0x38) -#define S3C2412_NFSECC S3C2410_NFREG(0x3C) - -#define S3C2410_NFCONF_EN (1<<15) -#define S3C2410_NFCONF_512BYTE (1<<14) -#define S3C2410_NFCONF_4STEP (1<<13) -#define S3C2410_NFCONF_INITECC (1<<12) -#define S3C2410_NFCONF_nFCE (1<<11) -#define S3C2410_NFCONF_TACLS(x) ((x)<<8) -#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) -#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) - -#define S3C2410_NFSTAT_BUSY (1<<0) - -#define S3C2440_NFCONF_BUSWIDTH_8 (0<<0) -#define S3C2440_NFCONF_BUSWIDTH_16 (1<<0) -#define S3C2440_NFCONF_ADVFLASH (1<<3) -#define S3C2440_NFCONF_TACLS(x) ((x)<<12) -#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8) -#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4) - -#define S3C2440_NFCONT_LOCKTIGHT (1<<13) -#define S3C2440_NFCONT_SOFTLOCK (1<<12) -#define S3C2440_NFCONT_ILLEGALACC_EN (1<<10) -#define S3C2440_NFCONT_RNBINT_EN (1<<9) -#define S3C2440_NFCONT_RN_FALLING (1<<8) -#define S3C2440_NFCONT_SPARE_ECCLOCK (1<<6) -#define S3C2440_NFCONT_MAIN_ECCLOCK (1<<5) -#define S3C2440_NFCONT_INITECC (1<<4) -#define S3C2440_NFCONT_nFCE (1<<1) -#define S3C2440_NFCONT_ENABLE (1<<0) - -#define S3C2440_NFSTAT_READY (1<<0) -#define S3C2440_NFSTAT_nCE (1<<1) -#define S3C2440_NFSTAT_RnB_CHANGE (1<<2) -#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3) - -#define S3C2412_NFCONF_NANDBOOT (1<<31) -#define S3C2412_NFCONF_ECCCLKCON (1<<30) -#define S3C2412_NFCONF_ECC_MLC (1<<24) -#define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */ - -#define S3C2412_NFCONT_ECC4_DIRWR (1<<18) -#define S3C2412_NFCONT_LOCKTIGHT (1<<17) -#define S3C2412_NFCONT_SOFTLOCK (1<<16) -#define S3C2412_NFCONT_ECC4_ENCINT (1<<13) -#define S3C2412_NFCONT_ECC4_DECINT (1<<12) -#define S3C2412_NFCONT_MAIN_ECC_LOCK (1<<7) -#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5) -#define S3C2412_NFCONT_nFCE1 (1<<2) -#define S3C2412_NFCONT_nFCE0 (1<<1) - -#define S3C2412_NFSTAT_ECC_ENCDONE (1<<7) -#define S3C2412_NFSTAT_ECC_DECDONE (1<<6) -#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1<<5) -#define S3C2412_NFSTAT_RnB_CHANGE (1<<4) -#define S3C2412_NFSTAT_nFCE1 (1<<3) -#define S3C2412_NFSTAT_nFCE0 (1<<2) -#define S3C2412_NFSTAT_Res1 (1<<1) -#define S3C2412_NFSTAT_READY (1<<0) - -#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf) -#define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7) -#define S3C2412_NFECCERR_MERRDATA(x) (((x) >> 7) & 0x3ff) -#define S3C2412_NFECCERR_MERRBIT(x) (((x) >> 4) & 0x7) -#define S3C2412_NFECCERR_SPARE_ERR(x) (((x) >> 2) & 0x3) -#define S3C2412_NFECCERR_MAIN_ERR(x) (((x) >> 2) & 0x3) -#define S3C2412_NFECCERR_NONE (0) -#define S3C2412_NFECCERR_1BIT (1) -#define S3C2412_NFECCERR_MULTIBIT (2) -#define S3C2412_NFECCERR_ECCAREA (3) - - - -#endif /* __ASM_ARM_REGS_NAND */ - diff --git a/arch/arm/plat-s3c/include/plat/regs-rtc.h b/arch/arm/plat-s3c/include/plat/regs-rtc.h deleted file mode 100644 index d5837cf8e40..00000000000 --- a/arch/arm/plat-s3c/include/plat/regs-rtc.h +++ /dev/null @@ -1,61 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h - * - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 Internal RTC register definition -*/ - -#ifndef __ASM_ARCH_REGS_RTC_H -#define __ASM_ARCH_REGS_RTC_H __FILE__ - -#define S3C2410_RTCREG(x) (x) - -#define S3C2410_RTCCON S3C2410_RTCREG(0x40) -#define S3C2410_RTCCON_RTCEN (1<<0) -#define S3C2410_RTCCON_CLKSEL (1<<1) -#define S3C2410_RTCCON_CNTSEL (1<<2) -#define S3C2410_RTCCON_CLKRST (1<<3) - -#define S3C2410_TICNT S3C2410_RTCREG(0x44) -#define S3C2410_TICNT_ENABLE (1<<7) - -#define S3C2410_RTCALM S3C2410_RTCREG(0x50) -#define S3C2410_RTCALM_ALMEN (1<<6) -#define S3C2410_RTCALM_YEAREN (1<<5) -#define S3C2410_RTCALM_MONEN (1<<4) -#define S3C2410_RTCALM_DAYEN (1<<3) -#define S3C2410_RTCALM_HOUREN (1<<2) -#define S3C2410_RTCALM_MINEN (1<<1) -#define S3C2410_RTCALM_SECEN (1<<0) - -#define S3C2410_RTCALM_ALL \ - S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\ - S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\ - S3C2410_RTCALM_SECEN - - -#define S3C2410_ALMSEC S3C2410_RTCREG(0x54) -#define S3C2410_ALMMIN S3C2410_RTCREG(0x58) -#define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c) - -#define S3C2410_ALMDATE S3C2410_RTCREG(0x60) -#define S3C2410_ALMMON S3C2410_RTCREG(0x64) -#define S3C2410_ALMYEAR S3C2410_RTCREG(0x68) - -#define S3C2410_RTCRST S3C2410_RTCREG(0x6c) - -#define S3C2410_RTCSEC S3C2410_RTCREG(0x70) -#define S3C2410_RTCMIN S3C2410_RTCREG(0x74) -#define S3C2410_RTCHOUR S3C2410_RTCREG(0x78) -#define S3C2410_RTCDATE S3C2410_RTCREG(0x7c) -#define S3C2410_RTCDAY S3C2410_RTCREG(0x80) -#define S3C2410_RTCMON S3C2410_RTCREG(0x84) -#define S3C2410_RTCYEAR S3C2410_RTCREG(0x88) - - -#endif /* __ASM_ARCH_REGS_RTC_H */ diff --git a/arch/arm/plat-s3c/include/plat/regs-sdhci.h b/arch/arm/plat-s3c/include/plat/regs-sdhci.h deleted file mode 100644 index e34049ad44c..00000000000 --- a/arch/arm/plat-s3c/include/plat/regs-sdhci.h +++ /dev/null @@ -1,87 +0,0 @@ -/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C Platform - SDHCI (HSMMC) register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_S3C_SDHCI_REGS_H -#define __PLAT_S3C_SDHCI_REGS_H __FILE__ - -#define S3C_SDHCI_CONTROL2 (0x80) -#define S3C_SDHCI_CONTROL3 (0x84) -#define S3C64XX_SDHCI_CONTROL4 (0x8C) - -#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31) -#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK (1 << 30) -#define S3C_SDHCI_CTRL2_CDINVRXD3 (1 << 29) -#define S3C_SDHCI_CTRL2_SLCARDOUT (1 << 28) - -#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) -#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) -#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24) - -#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16) -#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16) -#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) - -#define S3C_SDHCI_CTRL2_ENFBCLKTX (1 << 15) -#define S3C_SDHCI_CTRL2_ENFBCLKRX (1 << 14) -#define S3C_SDHCI_CTRL2_SDCDSEL (1 << 13) -#define S3C_SDHCI_CTRL2_SDSIGPC (1 << 12) -#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11) - -#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9) -#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9) -#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9) -#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9) -#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9) -#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9) - -#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8) -#define S3C_SDHCI_CTRL2_RWAITMODE (1 << 7) -#define S3C_SDHCI_CTRL2_DISBUFRD (1 << 6) -#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4) -#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4) -#define S3C_SDHCI_CTRL2_PWRSYNC (1 << 3) -#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1) -#define S3C_SDHCI_CTRL2_HWINITFIN (1 << 0) - -#define S3C_SDHCI_CTRL3_FCSEL3 (1 << 31) -#define S3C_SDHCI_CTRL3_FCSEL2 (1 << 23) -#define S3C_SDHCI_CTRL3_FCSEL1 (1 << 15) -#define S3C_SDHCI_CTRL3_FCSEL0 (1 << 7) - -#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24) -#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24) -#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24) - -#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16) -#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16) -#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16) - -#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8) -#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8) -#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8) - -#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0) -#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0) -#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0) - -#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16) -#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16) -#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16) -#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16) -#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16) -#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16) - -#define S3C64XX_SDHCI_CONTROL4_BUSY (1) - -#endif /* __PLAT_S3C_SDHCI_REGS_H */ diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h deleted file mode 100644 index 487d7d2a7e1..00000000000 --- a/arch/arm/plat-s3c/include/plat/regs-serial.h +++ /dev/null @@ -1,246 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-serial.h - * - * From linux/include/asm-arm/hardware/serial_s3c2410.h - * - * Internal header file for Samsung S3C2410 serial ports (UART0-2) - * - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * - * Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk) - * - * Adapted from: - * - * Internal header file for MX1ADS serial ports (UART1 & 2) - * - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#ifndef __ASM_ARM_REGS_SERIAL_H -#define __ASM_ARM_REGS_SERIAL_H - -#define S3C24XX_VA_UART0 (S3C_VA_UART) -#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 ) -#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 ) -#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 ) - -#define S3C2410_PA_UART0 (S3C24XX_PA_UART) -#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 ) -#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 ) -#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 ) - -#define S3C2410_URXH (0x24) -#define S3C2410_UTXH (0x20) -#define S3C2410_ULCON (0x00) -#define S3C2410_UCON (0x04) -#define S3C2410_UFCON (0x08) -#define S3C2410_UMCON (0x0C) -#define S3C2410_UBRDIV (0x28) -#define S3C2410_UTRSTAT (0x10) -#define S3C2410_UERSTAT (0x14) -#define S3C2410_UFSTAT (0x18) -#define S3C2410_UMSTAT (0x1C) - -#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3)) - -#define S3C2410_LCON_CS5 (0x0) -#define S3C2410_LCON_CS6 (0x1) -#define S3C2410_LCON_CS7 (0x2) -#define S3C2410_LCON_CS8 (0x3) -#define S3C2410_LCON_CSMASK (0x3) - -#define S3C2410_LCON_PNONE (0x0) -#define S3C2410_LCON_PEVEN (0x5 << 3) -#define S3C2410_LCON_PODD (0x4 << 3) -#define S3C2410_LCON_PMASK (0x7 << 3) - -#define S3C2410_LCON_STOPB (1<<2) -#define S3C2410_LCON_IRM (1<<6) - -#define S3C2440_UCON_CLKMASK (3<<10) -#define S3C2440_UCON_PCLK (0<<10) -#define S3C2440_UCON_UCLK (1<<10) -#define S3C2440_UCON_PCLK2 (2<<10) -#define S3C2440_UCON_FCLK (3<<10) -#define S3C2443_UCON_EPLL (3<<10) - -#define S3C6400_UCON_CLKMASK (3<<10) -#define S3C6400_UCON_PCLK (0<<10) -#define S3C6400_UCON_PCLK2 (2<<10) -#define S3C6400_UCON_UCLK0 (1<<10) -#define S3C6400_UCON_UCLK1 (3<<10) - -#define S3C2440_UCON2_FCLK_EN (1<<15) -#define S3C2440_UCON0_DIVMASK (15 << 12) -#define S3C2440_UCON1_DIVMASK (15 << 12) -#define S3C2440_UCON2_DIVMASK (7 << 12) -#define S3C2440_UCON_DIVSHIFT (12) - -#define S3C2412_UCON_CLKMASK (3<<10) -#define S3C2412_UCON_UCLK (1<<10) -#define S3C2412_UCON_USYSCLK (3<<10) -#define S3C2412_UCON_PCLK (0<<10) -#define S3C2412_UCON_PCLK2 (2<<10) - -#define S3C2410_UCON_UCLK (1<<10) -#define S3C2410_UCON_SBREAK (1<<4) - -#define S3C2410_UCON_TXILEVEL (1<<9) -#define S3C2410_UCON_RXILEVEL (1<<8) -#define S3C2410_UCON_TXIRQMODE (1<<2) -#define S3C2410_UCON_RXIRQMODE (1<<0) -#define S3C2410_UCON_RXFIFO_TOI (1<<7) -#define S3C2443_UCON_RXERR_IRQEN (1<<6) -#define S3C2443_UCON_LOOPBACK (1<<5) - -#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI) - -#define S3C2410_UFCON_FIFOMODE (1<<0) -#define S3C2410_UFCON_TXTRIG0 (0<<6) -#define S3C2410_UFCON_RXTRIG8 (1<<4) -#define S3C2410_UFCON_RXTRIG12 (2<<4) - -/* S3C2440 FIFO trigger levels */ -#define S3C2440_UFCON_RXTRIG1 (0<<4) -#define S3C2440_UFCON_RXTRIG8 (1<<4) -#define S3C2440_UFCON_RXTRIG16 (2<<4) -#define S3C2440_UFCON_RXTRIG32 (3<<4) - -#define S3C2440_UFCON_TXTRIG0 (0<<6) -#define S3C2440_UFCON_TXTRIG16 (1<<6) -#define S3C2440_UFCON_TXTRIG32 (2<<6) -#define S3C2440_UFCON_TXTRIG48 (3<<6) - -#define S3C2410_UFCON_RESETBOTH (3<<1) -#define S3C2410_UFCON_RESETTX (1<<2) -#define S3C2410_UFCON_RESETRX (1<<1) - -#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S3C2410_UFCON_TXTRIG0 | \ - S3C2410_UFCON_RXTRIG8 ) - -#define S3C2410_UMCOM_AFC (1<<4) -#define S3C2410_UMCOM_RTS_LOW (1<<0) - -#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */ -#define S3C2412_UMCON_AFC_56 (1<<5) -#define S3C2412_UMCON_AFC_48 (2<<5) -#define S3C2412_UMCON_AFC_40 (3<<5) -#define S3C2412_UMCON_AFC_32 (4<<5) -#define S3C2412_UMCON_AFC_24 (5<<5) -#define S3C2412_UMCON_AFC_16 (6<<5) -#define S3C2412_UMCON_AFC_8 (7<<5) - -#define S3C2410_UFSTAT_TXFULL (1<<9) -#define S3C2410_UFSTAT_RXFULL (1<<8) -#define S3C2410_UFSTAT_TXMASK (15<<4) -#define S3C2410_UFSTAT_TXSHIFT (4) -#define S3C2410_UFSTAT_RXMASK (15<<0) -#define S3C2410_UFSTAT_RXSHIFT (0) - -/* UFSTAT S3C24A0 */ -#define S3C24A0_UFSTAT_TXFULL (1 << 14) -#define S3C24A0_UFSTAT_RXFULL (1 << 6) -#define S3C24A0_UFSTAT_TXMASK (63 << 8) -#define S3C24A0_UFSTAT_TXSHIFT (8) -#define S3C24A0_UFSTAT_RXMASK (63) -#define S3C24A0_UFSTAT_RXSHIFT (0) - -/* UFSTAT S3C2443 same as S3C2440 */ -#define S3C2440_UFSTAT_TXFULL (1<<14) -#define S3C2440_UFSTAT_RXFULL (1<<6) -#define S3C2440_UFSTAT_TXSHIFT (8) -#define S3C2440_UFSTAT_RXSHIFT (0) -#define S3C2440_UFSTAT_TXMASK (63<<8) -#define S3C2440_UFSTAT_RXMASK (63) - -#define S3C2410_UTRSTAT_TXE (1<<2) -#define S3C2410_UTRSTAT_TXFE (1<<1) -#define S3C2410_UTRSTAT_RXDR (1<<0) - -#define S3C2410_UERSTAT_OVERRUN (1<<0) -#define S3C2410_UERSTAT_FRAME (1<<2) -#define S3C2410_UERSTAT_BREAK (1<<3) -#define S3C2443_UERSTAT_PARITY (1<<1) - -#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \ - S3C2410_UERSTAT_FRAME | \ - S3C2410_UERSTAT_BREAK) - -#define S3C2410_UMSTAT_CTS (1<<0) -#define S3C2410_UMSTAT_DeltaCTS (1<<2) - -#define S3C2443_DIVSLOT (0x2C) - -#ifndef __ASSEMBLY__ - -/* struct s3c24xx_uart_clksrc - * - * this structure defines a named clock source that can be used for the - * uart, so that the best clock can be selected for the requested baud - * rate. - * - * min_baud and max_baud define the range of baud-rates this clock is - * acceptable for, if they are both zero, it is assumed any baud rate that - * can be generated from this clock will be used. - * - * divisor gives the divisor from the clock to the one seen by the uart -*/ - -struct s3c24xx_uart_clksrc { - const char *name; - unsigned int divisor; - unsigned int min_baud; - unsigned int max_baud; -}; - -/* configuration structure for per-machine configurations for the - * serial port - * - * the pointer is setup by the machine specific initialisation from the - * arch/arm/mach-s3c2410/ directory. -*/ - -struct s3c2410_uartcfg { - unsigned char hwport; /* hardware port number */ - unsigned char unused; - unsigned short flags; - upf_t uart_flags; /* default uart flags */ - - unsigned long ucon; /* value of ucon for port */ - unsigned long ulcon; /* value of ulcon for port */ - unsigned long ufcon; /* value of ufcon for port */ - - struct s3c24xx_uart_clksrc *clocks; - unsigned int clocks_size; -}; - -/* s3c24xx_uart_devs - * - * this is exported from the core as we cannot use driver_register(), - * or platform_add_device() before the console_initcall() -*/ - -extern struct platform_device *s3c24xx_uart_devs[4]; - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_ARM_REGS_SERIAL_H */ - diff --git a/arch/arm/plat-s3c/include/plat/regs-timer.h b/arch/arm/plat-s3c/include/plat/regs-timer.h deleted file mode 100644 index d097d92f8cc..00000000000 --- a/arch/arm/plat-s3c/include/plat/regs-timer.h +++ /dev/null @@ -1,124 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-timer.h - * - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 Timer configuration -*/ - -#ifndef __ASM_ARCH_REGS_TIMER_H -#define __ASM_ARCH_REGS_TIMER_H - -#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x)) -#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c)) - -#define S3C2410_TCFG0 S3C_TIMERREG(0x00) -#define S3C2410_TCFG1 S3C_TIMERREG(0x04) -#define S3C2410_TCON S3C_TIMERREG(0x08) - -#define S3C64XX_TINT_CSTAT S3C_TIMERREG(0x44) - -#define S3C2410_TCFG_PRESCALER0_MASK (255<<0) -#define S3C2410_TCFG_PRESCALER1_MASK (255<<8) -#define S3C2410_TCFG_PRESCALER1_SHIFT (8) -#define S3C2410_TCFG_DEADZONE_MASK (255<<16) -#define S3C2410_TCFG_DEADZONE_SHIFT (16) - -#define S3C2410_TCFG1_MUX4_DIV2 (0<<16) -#define S3C2410_TCFG1_MUX4_DIV4 (1<<16) -#define S3C2410_TCFG1_MUX4_DIV8 (2<<16) -#define S3C2410_TCFG1_MUX4_DIV16 (3<<16) -#define S3C2410_TCFG1_MUX4_TCLK1 (4<<16) -#define S3C2410_TCFG1_MUX4_MASK (15<<16) -#define S3C2410_TCFG1_MUX4_SHIFT (16) - -#define S3C2410_TCFG1_MUX3_DIV2 (0<<12) -#define S3C2410_TCFG1_MUX3_DIV4 (1<<12) -#define S3C2410_TCFG1_MUX3_DIV8 (2<<12) -#define S3C2410_TCFG1_MUX3_DIV16 (3<<12) -#define S3C2410_TCFG1_MUX3_TCLK1 (4<<12) -#define S3C2410_TCFG1_MUX3_MASK (15<<12) - - -#define S3C2410_TCFG1_MUX2_DIV2 (0<<8) -#define S3C2410_TCFG1_MUX2_DIV4 (1<<8) -#define S3C2410_TCFG1_MUX2_DIV8 (2<<8) -#define S3C2410_TCFG1_MUX2_DIV16 (3<<8) -#define S3C2410_TCFG1_MUX2_TCLK1 (4<<8) -#define S3C2410_TCFG1_MUX2_MASK (15<<8) - - -#define S3C2410_TCFG1_MUX1_DIV2 (0<<4) -#define S3C2410_TCFG1_MUX1_DIV4 (1<<4) -#define S3C2410_TCFG1_MUX1_DIV8 (2<<4) -#define S3C2410_TCFG1_MUX1_DIV16 (3<<4) -#define S3C2410_TCFG1_MUX1_TCLK0 (4<<4) -#define S3C2410_TCFG1_MUX1_MASK (15<<4) - -#define S3C2410_TCFG1_MUX0_DIV2 (0<<0) -#define S3C2410_TCFG1_MUX0_DIV4 (1<<0) -#define S3C2410_TCFG1_MUX0_DIV8 (2<<0) -#define S3C2410_TCFG1_MUX0_DIV16 (3<<0) -#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0) -#define S3C2410_TCFG1_MUX0_MASK (15<<0) - -#define S3C2410_TCFG1_MUX_DIV2 (0<<0) -#define S3C2410_TCFG1_MUX_DIV4 (1<<0) -#define S3C2410_TCFG1_MUX_DIV8 (2<<0) -#define S3C2410_TCFG1_MUX_DIV16 (3<<0) -#define S3C2410_TCFG1_MUX_TCLK (4<<0) -#define S3C2410_TCFG1_MUX_MASK (15<<0) - -#define S3C64XX_TCFG1_MUX_DIV1 (0<<0) -#define S3C64XX_TCFG1_MUX_DIV2 (1<<0) -#define S3C64XX_TCFG1_MUX_DIV4 (2<<0) -#define S3C64XX_TCFG1_MUX_DIV8 (3<<0) -#define S3C64XX_TCFG1_MUX_DIV16 (4<<0) -#define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */ -#define S3C64XX_TCFG1_MUX_MASK (15<<0) - -#define S3C2410_TCFG1_SHIFT(x) ((x) * 4) - -/* for each timer, we have an count buffer, an compare buffer and - * an observation buffer -*/ - -/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */ - -#define S3C2410_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00) -#define S3C2410_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04) -#define S3C2410_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08)) - -#define S3C2410_TCON_T4RELOAD (1<<22) -#define S3C2410_TCON_T4MANUALUPD (1<<21) -#define S3C2410_TCON_T4START (1<<20) - -#define S3C2410_TCON_T3RELOAD (1<<19) -#define S3C2410_TCON_T3INVERT (1<<18) -#define S3C2410_TCON_T3MANUALUPD (1<<17) -#define S3C2410_TCON_T3START (1<<16) - -#define S3C2410_TCON_T2RELOAD (1<<15) -#define S3C2410_TCON_T2INVERT (1<<14) -#define S3C2410_TCON_T2MANUALUPD (1<<13) -#define S3C2410_TCON_T2START (1<<12) - -#define S3C2410_TCON_T1RELOAD (1<<11) -#define S3C2410_TCON_T1INVERT (1<<10) -#define S3C2410_TCON_T1MANUALUPD (1<<9) -#define S3C2410_TCON_T1START (1<<8) - -#define S3C2410_TCON_T0DEADZONE (1<<4) -#define S3C2410_TCON_T0RELOAD (1<<3) -#define S3C2410_TCON_T0INVERT (1<<2) -#define S3C2410_TCON_T0MANUALUPD (1<<1) -#define S3C2410_TCON_T0START (1<<0) - -#endif /* __ASM_ARCH_REGS_TIMER_H */ - - - diff --git a/arch/arm/plat-s3c/include/plat/regs-watchdog.h b/arch/arm/plat-s3c/include/plat/regs-watchdog.h deleted file mode 100644 index 4938492470f..00000000000 --- a/arch/arm/plat-s3c/include/plat/regs-watchdog.h +++ /dev/null @@ -1,41 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h - * - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 Watchdog timer control -*/ - - -#ifndef __ASM_ARCH_REGS_WATCHDOG_H -#define __ASM_ARCH_REGS_WATCHDOG_H - -#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG) - -#define S3C2410_WTCON S3C_WDOGREG(0x00) -#define S3C2410_WTDAT S3C_WDOGREG(0x04) -#define S3C2410_WTCNT S3C_WDOGREG(0x08) - -/* the watchdog can either generate a reset pulse, or an - * interrupt. - */ - -#define S3C2410_WTCON_RSTEN (0x01) -#define S3C2410_WTCON_INTEN (1<<2) -#define S3C2410_WTCON_ENABLE (1<<5) - -#define S3C2410_WTCON_DIV16 (0<<3) -#define S3C2410_WTCON_DIV32 (1<<3) -#define S3C2410_WTCON_DIV64 (2<<3) -#define S3C2410_WTCON_DIV128 (3<<3) - -#define S3C2410_WTCON_PRESCALE(x) ((x) << 8) -#define S3C2410_WTCON_PRESCALE_MASK (0xff00) - -#endif /* __ASM_ARCH_REGS_WATCHDOG_H */ - - diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-s3c/include/plat/sdhci.h deleted file mode 100644 index c4ca3920ca4..00000000000 --- a/arch/arm/plat-s3c/include/plat/sdhci.h +++ /dev/null @@ -1,108 +0,0 @@ -/* linux/arch/arm/plat-s3c/include/plat/sdhci.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C Platform - SDHCI (HSMMC) platform data definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_S3C_SDHCI_H -#define __PLAT_S3C_SDHCI_H __FILE__ - -struct platform_device; -struct mmc_host; -struct mmc_card; -struct mmc_ios; - -/** - * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI - * @max_width: The maximum number of data bits supported. - * @host_caps: Standard MMC host capabilities bit field. - * @cfg_gpio: Configure the GPIO for a specific card bit-width - * @cfg_card: Configure the interface for a specific card and speed. This - * is necessary the controllers and/or GPIO blocks require the - * changing of driver-strength and other controls dependant on - * the card and speed of operation. - * - * Initialisation data specific to either the machine or the platform - * for the device driver to use or call-back when configuring gpio or - * card speed information. -*/ -struct s3c_sdhci_platdata { - unsigned int max_width; - unsigned int host_caps; - - char **clocks; /* set of clock sources */ - - void (*cfg_gpio)(struct platform_device *dev, int width); - void (*cfg_card)(struct platform_device *dev, - void __iomem *regbase, - struct mmc_ios *ios, - struct mmc_card *card); -}; - -/** - * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device. - * @pd: Platform data to register to device. - * - * Register the given platform data for use withe S3C SDHCI device. - * The call will copy the platform data, so the board definitions can - * make the structure itself __initdata. - */ -extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd); -extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd); - -/* Default platform data, exported so that per-cpu initialisation can - * set the correct one when there are more than one cpu type selected. -*/ - -extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata; -extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata; - -/* Helper function availablity */ - -#ifdef CONFIG_S3C6410_SETUP_SDHCI -extern char *s3c6410_hsmmc_clksrcs[4]; - -extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w); -extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w); - -extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card); - -#ifdef CONFIG_S3C_DEV_HSMMC -static inline void s3c6410_default_sdhci0(void) -{ - s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs; - s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio; - s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; -} -#else -static inline void s3c6410_default_sdhci0(void) { } -#endif /* CONFIG_S3C_DEV_HSMMC */ - -#ifdef CONFIG_S3C_DEV_HSMMC1 -static inline void s3c6410_default_sdhci1(void) -{ - s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs; - s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio; - s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; -} -#else -static inline void s3c6410_default_sdhci1(void) { } -#endif /* CONFIG_S3C_DEV_HSMMC1 */ - -#else -static inline void s3c6410_default_sdhci0(void) { } -static inline void s3c6410_default_sdhci1(void) { } -#endif /* CONFIG_S3C6410_SETUP_SDHCI */ - -#endif /* __PLAT_S3C_SDHCI_H */ diff --git a/arch/arm/plat-s3c/include/plat/uncompress.h b/arch/arm/plat-s3c/include/plat/uncompress.h deleted file mode 100644 index 6061de87f22..00000000000 --- a/arch/arm/plat-s3c/include/plat/uncompress.h +++ /dev/null @@ -1,183 +0,0 @@ -/* linux/include/asm-arm/plat-s3c/uncompress.h - * - * Copyright 2003, 2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C - uncompress code - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_PLAT_UNCOMPRESS_H -#define __ASM_PLAT_UNCOMPRESS_H - -typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ - -/* uart setup */ - -static unsigned int fifo_mask; -static unsigned int fifo_max; - -/* forward declerations */ - -static void arch_detect_cpu(void); - -/* defines for UART registers */ - -#include <plat/regs-serial.h> -#include <plat/regs-watchdog.h> - -/* working in physical space... */ -#undef S3C2410_WDOGREG -#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x))) - -/* how many bytes we allow into the FIFO at a time in FIFO mode */ -#define FIFO_MAX (14) - -#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT) - -static __inline__ void -uart_wr(unsigned int reg, unsigned int val) -{ - volatile unsigned int *ptr; - - ptr = (volatile unsigned int *)(reg + uart_base); - *ptr = val; -} - -static __inline__ unsigned int -uart_rd(unsigned int reg) -{ - volatile unsigned int *ptr; - - ptr = (volatile unsigned int *)(reg + uart_base); - return *ptr; -} - -/* we can deal with the case the UARTs are being run - * in FIFO mode, so that we don't hold up our execution - * waiting for tx to happen... -*/ - -static void putc(int ch) -{ - if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) { - int level; - - while (1) { - level = uart_rd(S3C2410_UFSTAT); - level &= fifo_mask; - - if (level < fifo_max) - break; - } - - } else { - /* not using fifos */ - - while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE) - barrier(); - } - - /* write byte to transmission register */ - uart_wr(S3C2410_UTXH, ch); -} - -static inline void flush(void) -{ -} - -#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0) - -/* CONFIG_S3C_BOOT_WATCHDOG - * - * Simple boot-time watchdog setup, to reboot the system if there is - * any problem with the boot process -*/ - -#ifdef CONFIG_S3C_BOOT_WATCHDOG - -#define WDOG_COUNT (0xff00) - -static inline void arch_decomp_wdog(void) -{ - __raw_writel(WDOG_COUNT, S3C2410_WTCNT); -} - -static void arch_decomp_wdog_start(void) -{ - __raw_writel(WDOG_COUNT, S3C2410_WTDAT); - __raw_writel(WDOG_COUNT, S3C2410_WTCNT); - __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON); -} - -#else -#define arch_decomp_wdog_start() -#define arch_decomp_wdog() -#endif - -#ifdef CONFIG_S3C_BOOT_ERROR_RESET - -static void arch_decomp_error(const char *x) -{ - putstr("\n\n"); - putstr(x); - putstr("\n\n -- System resetting\n"); - - __raw_writel(0x4000, S3C2410_WTDAT); - __raw_writel(0x4000, S3C2410_WTCNT); - __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON); - - while(1); -} - -#define arch_error arch_decomp_error -#endif - -static void error(char *err); - -#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO -static inline void arch_enable_uart_fifo(void) -{ - u32 fifocon = uart_rd(S3C2410_UFCON); - - if (!(fifocon & S3C2410_UFCON_FIFOMODE)) { - fifocon |= S3C2410_UFCON_RESETBOTH; - uart_wr(S3C2410_UFCON, fifocon); - - /* wait for fifo reset to complete */ - while (1) { - fifocon = uart_rd(S3C2410_UFCON); - if (!(fifocon & S3C2410_UFCON_RESETBOTH)) - break; - } - } -} -#else -#define arch_enable_uart_fifo() do { } while(0) -#endif - - -static void -arch_decomp_setup(void) -{ - /* we may need to setup the uart(s) here if we are not running - * on an BAST... the BAST will have left the uarts configured - * after calling linux. - */ - - arch_detect_cpu(); - arch_decomp_wdog_start(); - - /* Enable the UART FIFOs if they where not enabled and our - * configuration says we should turn them on. - */ - - arch_enable_uart_fifo(); -} - - -#endif /* __ASM_PLAT_UNCOMPRESS_H */ diff --git a/arch/arm/plat-s3c/init.c b/arch/arm/plat-s3c/init.c deleted file mode 100644 index 6790edfaca6..00000000000 --- a/arch/arm/plat-s3c/init.c +++ /dev/null @@ -1,160 +0,0 @@ -/* linux/arch/arm/plat-s3c/init.c - * - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series CPU initialisation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> - -#include <mach/hardware.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/clock.h> - -#include <plat/regs-serial.h> - -static struct cpu_table *cpu; - -static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode, - struct cpu_table *tab, - unsigned int count) -{ - for (; count != 0; count--, tab++) { - if ((idcode & tab->idmask) == tab->idcode) - return tab; - } - - return NULL; -} - -void __init s3c_init_cpu(unsigned long idcode, - struct cpu_table *cputab, unsigned int cputab_size) -{ - cpu = s3c_lookup_cpu(idcode, cputab, cputab_size); - - if (cpu == NULL) { - printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode); - panic("Unknown S3C24XX CPU"); - } - - printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode); - - if (cpu->map_io == NULL || cpu->init == NULL) { - printk(KERN_ERR "CPU %s support not enabled\n", cpu->name); - panic("Unsupported Samsung CPU"); - } - - cpu->map_io(); -} - -/* s3c24xx_init_clocks - * - * Initialise the clock subsystem and associated information from the - * given master crystal value. - * - * xtal = 0 -> use default PLL crystal value (normally 12MHz) - * != 0 -> PLL crystal value in Hz -*/ - -void __init s3c24xx_init_clocks(int xtal) -{ - if (xtal == 0) - xtal = 12*1000*1000; - - if (cpu == NULL) - panic("s3c24xx_init_clocks: no cpu setup?\n"); - - if (cpu->init_clocks == NULL) - panic("s3c24xx_init_clocks: cpu has no clock init\n"); - else - (cpu->init_clocks)(xtal); -} - -/* uart management */ - -static int nr_uarts __initdata = 0; - -static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS]; - -/* s3c24xx_init_uartdevs - * - * copy the specified platform data and configuration into our central - * set of devices, before the data is thrown away after the init process. - * - * This also fills in the array passed to the serial driver for the - * early initialisation of the console. -*/ - -void __init s3c24xx_init_uartdevs(char *name, - struct s3c24xx_uart_resources *res, - struct s3c2410_uartcfg *cfg, int no) -{ - struct platform_device *platdev; - struct s3c2410_uartcfg *cfgptr = uart_cfgs; - struct s3c24xx_uart_resources *resp; - int uart; - - memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no); - - for (uart = 0; uart < no; uart++, cfg++, cfgptr++) { - platdev = s3c24xx_uart_src[cfgptr->hwport]; - - resp = res + cfgptr->hwport; - - s3c24xx_uart_devs[uart] = platdev; - - platdev->name = name; - platdev->resource = resp->resources; - platdev->num_resources = resp->nr_resources; - - platdev->dev.platform_data = cfgptr; - } - - nr_uarts = no; -} - -void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) -{ - if (cpu == NULL) - return; - - if (cpu->init_uarts == NULL) { - printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n"); - } else - (cpu->init_uarts)(cfg, no); -} - -static int __init s3c_arch_init(void) -{ - int ret; - - // do the correct init for cpu - - if (cpu == NULL) - panic("s3c_arch_init: NULL cpu\n"); - - ret = (cpu->init)(); - if (ret != 0) - return ret; - - ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts); - return ret; -} - -arch_initcall(s3c_arch_init); diff --git a/arch/arm/plat-s3c/pwm-clock.c b/arch/arm/plat-s3c/pwm-clock.c deleted file mode 100644 index a318215ab53..00000000000 --- a/arch/arm/plat-s3c/pwm-clock.c +++ /dev/null @@ -1,463 +0,0 @@ -/* linux/arch/arm/plat-s3c24xx/pwm-clock.c - * - * Copyright (c) 2007 Simtec Electronics - * Copyright (c) 2007, 2008 Ben Dooks - * Ben Dooks <ben-linux@fluff.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/log2.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/map.h> -#include <asm/irq.h> - -#include <plat/clock.h> -#include <plat/cpu.h> - -#include <plat/regs-timer.h> -#include <mach/pwm-clock.h> - -/* Each of the timers 0 through 5 go through the following - * clock tree, with the inputs depending on the timers. - * - * pclk ---- [ prescaler 0 ] -+---> timer 0 - * +---> timer 1 - * - * pclk ---- [ prescaler 1 ] -+---> timer 2 - * +---> timer 3 - * \---> timer 4 - * - * Which are fed into the timers as so: - * - * prescaled 0 ---- [ div 2,4,8,16 ] ---\ - * [mux] -> timer 0 - * tclk 0 ------------------------------/ - * - * prescaled 0 ---- [ div 2,4,8,16 ] ---\ - * [mux] -> timer 1 - * tclk 0 ------------------------------/ - * - * - * prescaled 1 ---- [ div 2,4,8,16 ] ---\ - * [mux] -> timer 2 - * tclk 1 ------------------------------/ - * - * prescaled 1 ---- [ div 2,4,8,16 ] ---\ - * [mux] -> timer 3 - * tclk 1 ------------------------------/ - * - * prescaled 1 ---- [ div 2,4,8, 16 ] --\ - * [mux] -> timer 4 - * tclk 1 ------------------------------/ - * - * Since the mux and the divider are tied together in the - * same register space, it is impossible to set the parent - * and the rate at the same time. To avoid this, we add an - * intermediate 'prescaled-and-divided' clock to select - * as the parent for the timer input clock called tdiv. - * - * prescaled clk --> pwm-tdiv ---\ - * [ mux ] --> timer X - * tclk -------------------------/ -*/ - -static struct clk clk_timer_scaler[]; - -static unsigned long clk_pwm_scaler_get_rate(struct clk *clk) -{ - unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0); - - if (clk == &clk_timer_scaler[1]) { - tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK; - tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT; - } else { - tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK; - } - - return clk_get_rate(clk->parent) / (tcfg0 + 1); -} - -static unsigned long clk_pwm_scaler_round_rate(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long divisor = parent_rate / rate; - - if (divisor > 256) - divisor = 256; - else if (divisor < 2) - divisor = 2; - - return parent_rate / divisor; -} - -static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long round = clk_pwm_scaler_round_rate(clk, rate); - unsigned long tcfg0; - unsigned long divisor; - unsigned long flags; - - divisor = clk_get_rate(clk->parent) / round; - divisor--; - - local_irq_save(flags); - tcfg0 = __raw_readl(S3C2410_TCFG0); - - if (clk == &clk_timer_scaler[1]) { - tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK; - tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT; - } else { - tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK; - tcfg0 |= divisor; - } - - __raw_writel(tcfg0, S3C2410_TCFG0); - local_irq_restore(flags); - - return 0; -} - -static struct clk clk_timer_scaler[] = { - [0] = { - .name = "pwm-scaler0", - .id = -1, - .get_rate = clk_pwm_scaler_get_rate, - .set_rate = clk_pwm_scaler_set_rate, - .round_rate = clk_pwm_scaler_round_rate, - }, - [1] = { - .name = "pwm-scaler1", - .id = -1, - .get_rate = clk_pwm_scaler_get_rate, - .set_rate = clk_pwm_scaler_set_rate, - .round_rate = clk_pwm_scaler_round_rate, - }, -}; - -static struct clk clk_timer_tclk[] = { - [0] = { - .name = "pwm-tclk0", - .id = -1, - }, - [1] = { - .name = "pwm-tclk1", - .id = -1, - }, -}; - -struct pwm_tdiv_clk { - struct clk clk; - unsigned int divisor; -}; - -static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk) -{ - return container_of(clk, struct pwm_tdiv_clk, clk); -} - -static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk) -{ - unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); - unsigned int divisor; - - tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id); - tcfg1 &= S3C2410_TCFG1_MUX_MASK; - - if (pwm_cfg_src_is_tclk(tcfg1)) - divisor = to_tdiv(clk)->divisor; - else - divisor = tcfg_to_divisor(tcfg1); - - return clk_get_rate(clk->parent) / divisor; -} - -static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate; - unsigned long divisor; - - parent_rate = clk_get_rate(clk->parent); - divisor = parent_rate / rate; - - if (divisor <= 1 && pwm_tdiv_has_div1()) - divisor = 1; - else if (divisor <= 2) - divisor = 2; - else if (divisor <= 4) - divisor = 4; - else if (divisor <= 8) - divisor = 8; - else - divisor = 16; - - return parent_rate / divisor; -} - -static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk) -{ - return pwm_tdiv_div_bits(divclk->divisor); -} - -static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk) -{ - unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); - unsigned long bits = clk_pwm_tdiv_bits(divclk); - unsigned long flags; - unsigned long shift = S3C2410_TCFG1_SHIFT(divclk->clk.id); - - local_irq_save(flags); - - tcfg1 = __raw_readl(S3C2410_TCFG1); - tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift); - tcfg1 |= bits << shift; - __raw_writel(tcfg1, S3C2410_TCFG1); - - local_irq_restore(flags); -} - -static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate) -{ - struct pwm_tdiv_clk *divclk = to_tdiv(clk); - unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long divisor; - - tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id); - tcfg1 &= S3C2410_TCFG1_MUX_MASK; - - rate = clk_round_rate(clk, rate); - divisor = parent_rate / rate; - - if (divisor > 16) - return -EINVAL; - - divclk->divisor = divisor; - - /* Update the current MUX settings if we are currently - * selected as the clock source for this clock. */ - - if (!pwm_cfg_src_is_tclk(tcfg1)) - clk_pwm_tdiv_update(divclk); - - return 0; -} - -static struct pwm_tdiv_clk clk_timer_tdiv[] = { - [0] = { - .clk = { - .name = "pwm-tdiv", - .parent = &clk_timer_scaler[0], - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, - }, - }, - [1] = { - .clk = { - .name = "pwm-tdiv", - .parent = &clk_timer_scaler[0], - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, - } - }, - [2] = { - .clk = { - .name = "pwm-tdiv", - .parent = &clk_timer_scaler[1], - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, - }, - }, - [3] = { - .clk = { - .name = "pwm-tdiv", - .parent = &clk_timer_scaler[1], - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, - }, - }, - [4] = { - .clk = { - .name = "pwm-tdiv", - .parent = &clk_timer_scaler[1], - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, - }, - }, -}; - -static int __init clk_pwm_tdiv_register(unsigned int id) -{ - struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id]; - unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); - - tcfg1 >>= S3C2410_TCFG1_SHIFT(id); - tcfg1 &= S3C2410_TCFG1_MUX_MASK; - - divclk->clk.id = id; - divclk->divisor = tcfg_to_divisor(tcfg1); - - return s3c24xx_register_clock(&divclk->clk); -} - -static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id) -{ - return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0]; -} - -static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id) -{ - return &clk_timer_tdiv[id].clk; -} - -static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent) -{ - unsigned int id = clk->id; - unsigned long tcfg1; - unsigned long flags; - unsigned long bits; - unsigned long shift = S3C2410_TCFG1_SHIFT(id); - - if (parent == s3c24xx_pwmclk_tclk(id)) - bits = S3C_TCFG1_MUX_TCLK << shift; - else if (parent == s3c24xx_pwmclk_tdiv(id)) - bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift; - else - return -EINVAL; - - clk->parent = parent; - - local_irq_save(flags); - - tcfg1 = __raw_readl(S3C2410_TCFG1); - tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift); - __raw_writel(tcfg1 | bits, S3C2410_TCFG1); - - local_irq_restore(flags); - - return 0; -} - -static struct clk clk_tin[] = { - [0] = { - .name = "pwm-tin", - .id = 0, - .set_parent = clk_pwm_tin_set_parent, - }, - [1] = { - .name = "pwm-tin", - .id = 1, - .set_parent = clk_pwm_tin_set_parent, - }, - [2] = { - .name = "pwm-tin", - .id = 2, - .set_parent = clk_pwm_tin_set_parent, - }, - [3] = { - .name = "pwm-tin", - .id = 3, - .set_parent = clk_pwm_tin_set_parent, - }, - [4] = { - .name = "pwm-tin", - .id = 4, - .set_parent = clk_pwm_tin_set_parent, - }, -}; - -static __init int clk_pwm_tin_register(struct clk *pwm) -{ - unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); - unsigned int id = pwm->id; - - struct clk *parent; - int ret; - - ret = s3c24xx_register_clock(pwm); - if (ret < 0) - return ret; - - tcfg1 >>= S3C2410_TCFG1_SHIFT(id); - tcfg1 &= S3C2410_TCFG1_MUX_MASK; - - if (pwm_cfg_src_is_tclk(tcfg1)) - parent = s3c24xx_pwmclk_tclk(id); - else - parent = s3c24xx_pwmclk_tdiv(id); - - return clk_set_parent(pwm, parent); -} - -/** - * s3c_pwmclk_init() - initialise pwm clocks - * - * Initialise and register the clocks which provide the inputs for the - * pwm timer blocks. - * - * Note, this call is required by the time core, so must be called after - * the base clocks are added and before any of the initcalls are run. - */ -__init void s3c_pwmclk_init(void) -{ - struct clk *clk_timers; - unsigned int clk; - int ret; - - clk_timers = clk_get(NULL, "timers"); - if (IS_ERR(clk_timers)) { - printk(KERN_ERR "%s: no parent clock\n", __func__); - return; - } - - for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) { - clk_timer_scaler[clk].parent = clk_timers; - ret = s3c24xx_register_clock(&clk_timer_scaler[clk]); - if (ret < 0) { - printk(KERN_ERR "error adding pwm scaler%d clock\n", clk); - return; - } - } - - for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) { - ret = s3c24xx_register_clock(&clk_timer_tclk[clk]); - if (ret < 0) { - printk(KERN_ERR "error adding pww tclk%d\n", clk); - return; - } - } - - for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) { - ret = clk_pwm_tdiv_register(clk); - if (ret < 0) { - printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk); - return; - } - } - - for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) { - ret = clk_pwm_tin_register(&clk_tin[clk]); - if (ret < 0) { - printk(KERN_ERR "error adding pwm%d tin clock\n", clk); - return; - } - } -} diff --git a/arch/arm/plat-s3c/time.c b/arch/arm/plat-s3c/time.c deleted file mode 100644 index 3b27b29da47..00000000000 --- a/arch/arm/plat-s3c/time.c +++ /dev/null @@ -1,285 +0,0 @@ -/* linux/arch/arm/plat-s3c24xx/time.c - * - * Copyright (C) 2003-2005 Simtec Electronics - * Ben Dooks, <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/platform_device.h> - -#include <asm/system.h> -#include <asm/leds.h> -#include <asm/mach-types.h> - -#include <asm/irq.h> -#include <mach/map.h> -#include <plat/regs-timer.h> -#include <mach/regs-irq.h> -#include <asm/mach/time.h> -#include <mach/tick.h> - -#include <plat/clock.h> -#include <plat/cpu.h> - -static unsigned long timer_startval; -static unsigned long timer_usec_ticks; - -#ifndef TICK_MAX -#define TICK_MAX (0xffff) -#endif - -#define TIMER_USEC_SHIFT 16 - -/* we use the shifted arithmetic to work out the ratio of timer ticks - * to usecs, as often the peripheral clock is not a nice even multiple - * of 1MHz. - * - * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok - * for the current HZ value of 200 without producing overflows. - * - * Original patch by Dimitry Andric, updated by Ben Dooks -*/ - - -/* timer_mask_usec_ticks - * - * given a clock and divisor, make the value to pass into timer_ticks_to_usec - * to scale the ticks into usecs -*/ - -static inline unsigned long -timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk) -{ - unsigned long den = pclk / 1000; - - return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den; -} - -/* timer_ticks_to_usec - * - * convert timer ticks to usec. -*/ - -static inline unsigned long timer_ticks_to_usec(unsigned long ticks) -{ - unsigned long res; - - res = ticks * timer_usec_ticks; - res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */ - - return res >> TIMER_USEC_SHIFT; -} - -/*** - * Returns microsecond since last clock interrupt. Note that interrupts - * will have been disabled by do_gettimeoffset() - * IRQs are disabled before entering here from do_gettimeofday() - */ - -static unsigned long s3c2410_gettimeoffset (void) -{ - unsigned long tdone; - unsigned long tval; - - /* work out how many ticks have gone since last timer interrupt */ - - tval = __raw_readl(S3C2410_TCNTO(4)); - tdone = timer_startval - tval; - - /* check to see if there is an interrupt pending */ - - if (s3c24xx_ostimer_pending()) { - /* re-read the timer, and try and fix up for the missed - * interrupt. Note, the interrupt may go off before the - * timer has re-loaded from wrapping. - */ - - tval = __raw_readl(S3C2410_TCNTO(4)); - tdone = timer_startval - tval; - - if (tval != 0) - tdone += timer_startval; - } - - return timer_ticks_to_usec(tdone); -} - - -/* - * IRQ handler for the timer - */ -static irqreturn_t -s3c2410_timer_interrupt(int irq, void *dev_id) -{ - timer_tick(); - return IRQ_HANDLED; -} - -static struct irqaction s3c2410_timer_irq = { - .name = "S3C2410 Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = s3c2410_timer_interrupt, -}; - -#define use_tclk1_12() ( \ - machine_is_bast() || \ - machine_is_vr1000() || \ - machine_is_anubis() || \ - machine_is_osiris()) - -static struct clk *tin; -static struct clk *tdiv; -static struct clk *timerclk; - -/* - * Set up timer interrupt, and return the current time in seconds. - * - * Currently we only use timer4, as it is the only timer which has no - * other function that can be exploited externally - */ -static void s3c2410_timer_setup (void) -{ - unsigned long tcon; - unsigned long tcnt; - unsigned long tcfg1; - unsigned long tcfg0; - - tcnt = TICK_MAX; /* default value for tcnt */ - - /* configure the system for whichever machine is in use */ - - if (use_tclk1_12()) { - /* timer is at 12MHz, scaler is 1 */ - timer_usec_ticks = timer_mask_usec_ticks(1, 12000000); - tcnt = 12000000 / HZ; - - tcfg1 = __raw_readl(S3C2410_TCFG1); - tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; - tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1; - __raw_writel(tcfg1, S3C2410_TCFG1); - } else { - unsigned long pclk; - struct clk *tscaler; - - /* for the h1940 (and others), we use the pclk from the core - * to generate the timer values. since values around 50 to - * 70MHz are not values we can directly generate the timer - * value from, we need to pre-scale and divide before using it. - * - * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz - * (8.45 ticks per usec) - */ - - pclk = clk_get_rate(timerclk); - - /* configure clock tick */ - - timer_usec_ticks = timer_mask_usec_ticks(6, pclk); - - tscaler = clk_get_parent(tdiv); - - clk_set_rate(tscaler, pclk / 3); - clk_set_rate(tdiv, pclk / 6); - clk_set_parent(tin, tdiv); - - tcnt = clk_get_rate(tin) / HZ; - } - - tcon = __raw_readl(S3C2410_TCON); - tcfg0 = __raw_readl(S3C2410_TCFG0); - tcfg1 = __raw_readl(S3C2410_TCFG1); - - /* timers reload after counting zero, so reduce the count by 1 */ - - tcnt--; - - printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n", - tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks); - - /* check to see if timer is within 16bit range... */ - if (tcnt > TICK_MAX) { - panic("setup_timer: HZ is too small, cannot configure timer!"); - return; - } - - __raw_writel(tcfg1, S3C2410_TCFG1); - __raw_writel(tcfg0, S3C2410_TCFG0); - - timer_startval = tcnt; - __raw_writel(tcnt, S3C2410_TCNTB(4)); - - /* ensure timer is stopped... */ - - tcon &= ~(7<<20); - tcon |= S3C2410_TCON_T4RELOAD; - tcon |= S3C2410_TCON_T4MANUALUPD; - - __raw_writel(tcon, S3C2410_TCON); - __raw_writel(tcnt, S3C2410_TCNTB(4)); - __raw_writel(tcnt, S3C2410_TCMPB(4)); - - /* start the timer running */ - tcon |= S3C2410_TCON_T4START; - tcon &= ~S3C2410_TCON_T4MANUALUPD; - __raw_writel(tcon, S3C2410_TCON); -} - -static void __init s3c2410_timer_resources(void) -{ - struct platform_device tmpdev; - - tmpdev.dev.bus = &platform_bus_type; - tmpdev.id = 4; - - timerclk = clk_get(NULL, "timers"); - if (IS_ERR(timerclk)) - panic("failed to get clock for system timer"); - - clk_enable(timerclk); - - if (!use_tclk1_12()) { - tin = clk_get(&tmpdev.dev, "pwm-tin"); - if (IS_ERR(tin)) - panic("failed to get pwm-tin clock for system timer"); - - tdiv = clk_get(&tmpdev.dev, "pwm-tdiv"); - if (IS_ERR(tdiv)) - panic("failed to get pwm-tdiv clock for system timer"); - } - - clk_enable(tin); -} - -static void __init s3c2410_timer_init(void) -{ - s3c2410_timer_resources(); - s3c2410_timer_setup(); - setup_irq(IRQ_TIMER4, &s3c2410_timer_irq); -} - -struct sys_timer s3c24xx_timer = { - .init = s3c2410_timer_init, - .offset = s3c2410_gettimeoffset, - .resume = s3c2410_timer_setup -}; |