diff options
Diffstat (limited to 'arch/arm/plat-pxa')
| -rw-r--r-- | arch/arm/plat-pxa/Kconfig | 5 | ||||
| -rw-r--r-- | arch/arm/plat-pxa/Makefile | 3 | ||||
| -rw-r--r-- | arch/arm/plat-pxa/dma.c | 285 | ||||
| -rw-r--r-- | arch/arm/plat-pxa/gpio.c | 352 | ||||
| -rw-r--r-- | arch/arm/plat-pxa/include/plat/gpio.h | 62 | ||||
| -rw-r--r-- | arch/arm/plat-pxa/include/plat/mfp.h | 86 | ||||
| -rw-r--r-- | arch/arm/plat-pxa/mfp.c | 21 | ||||
| -rw-r--r-- | arch/arm/plat-pxa/ssp.c | 292 |
8 files changed, 660 insertions, 446 deletions
diff --git a/arch/arm/plat-pxa/Kconfig b/arch/arm/plat-pxa/Kconfig index b158e98038e..da53395a17c 100644 --- a/arch/arm/plat-pxa/Kconfig +++ b/arch/arm/plat-pxa/Kconfig @@ -1,3 +1,8 @@ if PLAT_PXA +config PXA_SSP + tristate + help + Enable support for PXA2xx SSP ports + endif diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile index 8f2c4c7fbd4..1fc94194491 100644 --- a/arch/arm/plat-pxa/Makefile +++ b/arch/arm/plat-pxa/Makefile @@ -4,6 +4,7 @@ obj-y := dma.o -obj-$(CONFIG_GENERIC_GPIO) += gpio.o obj-$(CONFIG_PXA3xx) += mfp.o obj-$(CONFIG_ARCH_MMP) += mfp.o + +obj-$(CONFIG_PXA_SSP) += ssp.o diff --git a/arch/arm/plat-pxa/dma.c b/arch/arm/plat-pxa/dma.c index 70aeee407f7..054fc5a1a11 100644 --- a/arch/arm/plat-pxa/dma.c +++ b/arch/arm/plat-pxa/dma.c @@ -14,25 +14,269 @@ #include <linux/module.h> #include <linux/init.h> +#include <linux/slab.h> #include <linux/kernel.h> #include <linux/interrupt.h> #include <linux/errno.h> +#include <linux/dma-mapping.h> -#include <asm/system.h> #include <asm/irq.h> +#include <asm/memory.h> #include <mach/hardware.h> #include <mach/dma.h> +#define DMA_DEBUG_NAME "pxa_dma" +#define DMA_MAX_REQUESTERS 64 + struct dma_channel { char *name; pxa_dma_prio prio; void (*irq_handler)(int, void *); void *data; + spinlock_t lock; }; static struct dma_channel *dma_channels; static int num_dma_channels; +/* + * Debug fs + */ +#ifdef CONFIG_DEBUG_FS +#include <linux/debugfs.h> +#include <linux/uaccess.h> +#include <linux/seq_file.h> + +static struct dentry *dbgfs_root, *dbgfs_state, **dbgfs_chan; + +static int dbg_show_requester_chan(struct seq_file *s, void *p) +{ + int pos = 0; + int chan = (int)s->private; + int i; + u32 drcmr; + + pos += seq_printf(s, "DMA channel %d requesters list :\n", chan); + for (i = 0; i < DMA_MAX_REQUESTERS; i++) { + drcmr = DRCMR(i); + if ((drcmr & DRCMR_CHLNUM) == chan) + pos += seq_printf(s, "\tRequester %d (MAPVLD=%d)\n", i, + !!(drcmr & DRCMR_MAPVLD)); + } + return pos; +} + +static inline int dbg_burst_from_dcmd(u32 dcmd) +{ + int burst = (dcmd >> 16) & 0x3; + + return burst ? 4 << burst : 0; +} + +static int is_phys_valid(unsigned long addr) +{ + return pfn_valid(__phys_to_pfn(addr)); +} + +#define DCSR_STR(flag) (dcsr & DCSR_##flag ? #flag" " : "") +#define DCMD_STR(flag) (dcmd & DCMD_##flag ? #flag" " : "") + +static int dbg_show_descriptors(struct seq_file *s, void *p) +{ + int pos = 0; + int chan = (int)s->private; + int i, max_show = 20, burst, width; + u32 dcmd; + unsigned long phys_desc; + struct pxa_dma_desc *desc; + unsigned long flags; + + spin_lock_irqsave(&dma_channels[chan].lock, flags); + phys_desc = DDADR(chan); + + pos += seq_printf(s, "DMA channel %d descriptors :\n", chan); + pos += seq_printf(s, "[%03d] First descriptor unknown\n", 0); + for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) { + desc = phys_to_virt(phys_desc); + dcmd = desc->dcmd; + burst = dbg_burst_from_dcmd(dcmd); + width = (1 << ((dcmd >> 14) & 0x3)) >> 1; + + pos += seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n", + i, phys_desc, desc); + pos += seq_printf(s, "\tDDADR = %08x\n", desc->ddadr); + pos += seq_printf(s, "\tDSADR = %08x\n", desc->dsadr); + pos += seq_printf(s, "\tDTADR = %08x\n", desc->dtadr); + pos += seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d" + " width=%d len=%d)\n", + dcmd, + DCMD_STR(INCSRCADDR), DCMD_STR(INCTRGADDR), + DCMD_STR(FLOWSRC), DCMD_STR(FLOWTRG), + DCMD_STR(STARTIRQEN), DCMD_STR(ENDIRQEN), + DCMD_STR(ENDIAN), burst, width, + dcmd & DCMD_LENGTH); + phys_desc = desc->ddadr; + } + if (i == max_show) + pos += seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n", + i, phys_desc); + else + pos += seq_printf(s, "[%03d] Desc at %08lx is %s\n", + i, phys_desc, phys_desc == DDADR_STOP ? + "DDADR_STOP" : "invalid"); + + spin_unlock_irqrestore(&dma_channels[chan].lock, flags); + return pos; +} + +static int dbg_show_chan_state(struct seq_file *s, void *p) +{ + int pos = 0; + int chan = (int)s->private; + u32 dcsr, dcmd; + int burst, width; + static char *str_prio[] = { "high", "normal", "low" }; + + dcsr = DCSR(chan); + dcmd = DCMD(chan); + burst = dbg_burst_from_dcmd(dcmd); + width = (1 << ((dcmd >> 14) & 0x3)) >> 1; + + pos += seq_printf(s, "DMA channel %d\n", chan); + pos += seq_printf(s, "\tPriority : %s\n", + str_prio[dma_channels[chan].prio]); + pos += seq_printf(s, "\tUnaligned transfer bit: %s\n", + DALGN & (1 << chan) ? "yes" : "no"); + pos += seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", + dcsr, DCSR_STR(RUN), DCSR_STR(NODESC), + DCSR_STR(STOPIRQEN), DCSR_STR(EORIRQEN), + DCSR_STR(EORJMPEN), DCSR_STR(EORSTOPEN), + DCSR_STR(SETCMPST), DCSR_STR(CLRCMPST), + DCSR_STR(CMPST), DCSR_STR(EORINTR), DCSR_STR(REQPEND), + DCSR_STR(STOPSTATE), DCSR_STR(ENDINTR), + DCSR_STR(STARTINTR), DCSR_STR(BUSERR)); + + pos += seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d" + " len=%d)\n", + dcmd, + DCMD_STR(INCSRCADDR), DCMD_STR(INCTRGADDR), + DCMD_STR(FLOWSRC), DCMD_STR(FLOWTRG), + DCMD_STR(STARTIRQEN), DCMD_STR(ENDIRQEN), + DCMD_STR(ENDIAN), burst, width, dcmd & DCMD_LENGTH); + pos += seq_printf(s, "\tDSADR = %08x\n", DSADR(chan)); + pos += seq_printf(s, "\tDTADR = %08x\n", DTADR(chan)); + pos += seq_printf(s, "\tDDADR = %08x\n", DDADR(chan)); + return pos; +} + +static int dbg_show_state(struct seq_file *s, void *p) +{ + int pos = 0; + + /* basic device status */ + pos += seq_printf(s, "DMA engine status\n"); + pos += seq_printf(s, "\tChannel number: %d\n", num_dma_channels); + + return pos; +} + +#define DBGFS_FUNC_DECL(name) \ +static int dbg_open_##name(struct inode *inode, struct file *file) \ +{ \ + return single_open(file, dbg_show_##name, inode->i_private); \ +} \ +static const struct file_operations dbg_fops_##name = { \ + .owner = THIS_MODULE, \ + .open = dbg_open_##name, \ + .llseek = seq_lseek, \ + .read = seq_read, \ + .release = single_release, \ +} + +DBGFS_FUNC_DECL(state); +DBGFS_FUNC_DECL(chan_state); +DBGFS_FUNC_DECL(descriptors); +DBGFS_FUNC_DECL(requester_chan); + +static struct dentry *pxa_dma_dbg_alloc_chan(int ch, struct dentry *chandir) +{ + char chan_name[11]; + struct dentry *chan, *chan_state = NULL, *chan_descr = NULL; + struct dentry *chan_reqs = NULL; + void *dt; + + scnprintf(chan_name, sizeof(chan_name), "%d", ch); + chan = debugfs_create_dir(chan_name, chandir); + dt = (void *)ch; + + if (chan) + chan_state = debugfs_create_file("state", 0400, chan, dt, + &dbg_fops_chan_state); + if (chan_state) + chan_descr = debugfs_create_file("descriptors", 0400, chan, dt, + &dbg_fops_descriptors); + if (chan_descr) + chan_reqs = debugfs_create_file("requesters", 0400, chan, dt, + &dbg_fops_requester_chan); + if (!chan_reqs) + goto err_state; + + return chan; + +err_state: + debugfs_remove_recursive(chan); + return NULL; +} + +static void pxa_dma_init_debugfs(void) +{ + int i; + struct dentry *chandir; + + dbgfs_root = debugfs_create_dir(DMA_DEBUG_NAME, NULL); + if (IS_ERR(dbgfs_root) || !dbgfs_root) + goto err_root; + + dbgfs_state = debugfs_create_file("state", 0400, dbgfs_root, NULL, + &dbg_fops_state); + if (!dbgfs_state) + goto err_state; + + dbgfs_chan = kmalloc(sizeof(*dbgfs_state) * num_dma_channels, + GFP_KERNEL); + if (!dbgfs_chan) + goto err_alloc; + + chandir = debugfs_create_dir("channels", dbgfs_root); + if (!chandir) + goto err_chandir; + + for (i = 0; i < num_dma_channels; i++) { + dbgfs_chan[i] = pxa_dma_dbg_alloc_chan(i, chandir); + if (!dbgfs_chan[i]) + goto err_chans; + } + + return; +err_chans: +err_chandir: + kfree(dbgfs_chan); +err_alloc: +err_state: + debugfs_remove_recursive(dbgfs_root); +err_root: + pr_err("pxa_dma: debugfs is not available\n"); +} + +static void __exit pxa_dma_cleanup_debugfs(void) +{ + debugfs_remove_recursive(dbgfs_root); +} +#else +static inline void pxa_dma_init_debugfs(void) {} +static inline void pxa_dma_cleanup_debugfs(void) {} +#endif + int pxa_request_dma (char *name, pxa_dma_prio prio, void (*irq_handler)(int, void *), void *data) @@ -71,6 +315,7 @@ int pxa_request_dma (char *name, pxa_dma_prio prio, local_irq_restore(flags); return i; } +EXPORT_SYMBOL(pxa_request_dma); void pxa_free_dma (int dma_ch) { @@ -88,24 +333,26 @@ void pxa_free_dma (int dma_ch) dma_channels[dma_ch].name = NULL; local_irq_restore(flags); } +EXPORT_SYMBOL(pxa_free_dma); static irqreturn_t dma_irq_handler(int irq, void *dev_id) { int i, dint = DINT; + struct dma_channel *channel; - for (i = 0; i < num_dma_channels; i++) { - if (dint & (1 << i)) { - struct dma_channel *channel = &dma_channels[i]; - if (channel->name && channel->irq_handler) { - channel->irq_handler(i, channel->data); - } else { - /* - * IRQ for an unregistered DMA channel: - * let's clear the interrupts and disable it. - */ - printk (KERN_WARNING "spurious IRQ for DMA channel %d\n", i); - DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; - } + while (dint) { + i = __ffs(dint); + dint &= (dint - 1); + channel = &dma_channels[i]; + if (channel->name && channel->irq_handler) { + channel->irq_handler(i, channel->data); + } else { + /* + * IRQ for an unregistered DMA channel: + * let's clear the interrupts and disable it. + */ + printk (KERN_WARNING "spurious IRQ for DMA channel %d\n", i); + DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; } } return IRQ_HANDLED; @@ -127,18 +374,18 @@ int __init pxa_init_dma(int irq, int num_ch) for (i = 0; i < num_ch; i++) { DCSR(i) = 0; dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW); + spin_lock_init(&dma_channels[i].lock); } - ret = request_irq(irq, dma_irq_handler, IRQF_DISABLED, "DMA", NULL); + ret = request_irq(irq, dma_irq_handler, 0, "DMA", NULL); if (ret) { printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n"); kfree(dma_channels); return ret; } - num_dma_channels = num_ch; + + pxa_dma_init_debugfs(); + return 0; } - -EXPORT_SYMBOL(pxa_request_dma); -EXPORT_SYMBOL(pxa_free_dma); diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c deleted file mode 100644 index abc79d44aca..00000000000 --- a/arch/arm/plat-pxa/gpio.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * linux/arch/arm/plat-pxa/gpio.c - * - * Generic PXA GPIO handling - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/init.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/sysdev.h> -#include <linux/bootmem.h> - -#include <mach/gpio.h> - -int pxa_last_gpio; - -struct pxa_gpio_chip { - struct gpio_chip chip; - void __iomem *regbase; - char label[10]; - - unsigned long irq_mask; - unsigned long irq_edge_rise; - unsigned long irq_edge_fall; - -#ifdef CONFIG_PM - unsigned long saved_gplr; - unsigned long saved_gpdr; - unsigned long saved_grer; - unsigned long saved_gfer; -#endif -}; - -static DEFINE_SPINLOCK(gpio_lock); -static struct pxa_gpio_chip *pxa_gpio_chips; - -#define for_each_gpio_chip(i, c) \ - for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++) - -static inline void __iomem *gpio_chip_base(struct gpio_chip *c) -{ - return container_of(c, struct pxa_gpio_chip, chip)->regbase; -} - -static inline struct pxa_gpio_chip *gpio_to_chip(unsigned gpio) -{ - return &pxa_gpio_chips[gpio_to_bank(gpio)]; -} - -static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - void __iomem *base = gpio_chip_base(chip); - uint32_t value, mask = 1 << offset; - unsigned long flags; - - spin_lock_irqsave(&gpio_lock, flags); - - value = __raw_readl(base + GPDR_OFFSET); - if (__gpio_is_inverted(chip->base + offset)) - value |= mask; - else - value &= ~mask; - __raw_writel(value, base + GPDR_OFFSET); - - spin_unlock_irqrestore(&gpio_lock, flags); - return 0; -} - -static int pxa_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - void __iomem *base = gpio_chip_base(chip); - uint32_t tmp, mask = 1 << offset; - unsigned long flags; - - __raw_writel(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); - - spin_lock_irqsave(&gpio_lock, flags); - - tmp = __raw_readl(base + GPDR_OFFSET); - if (__gpio_is_inverted(chip->base + offset)) - tmp &= ~mask; - else - tmp |= mask; - __raw_writel(tmp, base + GPDR_OFFSET); - - spin_unlock_irqrestore(&gpio_lock, flags); - return 0; -} - -static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - return __raw_readl(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset); -} - -static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -{ - __raw_writel(1 << offset, gpio_chip_base(chip) + - (value ? GPSR_OFFSET : GPCR_OFFSET)); -} - -static int __init pxa_init_gpio_chip(int gpio_end) -{ - int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1; - struct pxa_gpio_chip *chips; - - /* this is early, we have to use bootmem allocator, and we really - * want this to be allocated dynamically for different 'gpio_end' - */ - chips = alloc_bootmem_low(nbanks * sizeof(struct pxa_gpio_chip)); - if (chips == NULL) { - pr_err("%s: failed to allocate GPIO chips\n", __func__); - return -ENOMEM; - } - - memset(chips, 0, nbanks * sizeof(struct pxa_gpio_chip)); - - for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { - struct gpio_chip *c = &chips[i].chip; - - sprintf(chips[i].label, "gpio-%d", i); - chips[i].regbase = (void __iomem *)GPIO_BANK(i); - - c->base = gpio; - c->label = chips[i].label; - - c->direction_input = pxa_gpio_direction_input; - c->direction_output = pxa_gpio_direction_output; - c->get = pxa_gpio_get; - c->set = pxa_gpio_set; - - /* number of GPIOs on last bank may be less than 32 */ - c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32; - gpiochip_add(c); - } - pxa_gpio_chips = chips; - return 0; -} - -/* Update only those GRERx and GFERx edge detection register bits if those - * bits are set in c->irq_mask - */ -static inline void update_edge_detect(struct pxa_gpio_chip *c) -{ - uint32_t grer, gfer; - - grer = __raw_readl(c->regbase + GRER_OFFSET) & ~c->irq_mask; - gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~c->irq_mask; - grer |= c->irq_edge_rise & c->irq_mask; - gfer |= c->irq_edge_fall & c->irq_mask; - __raw_writel(grer, c->regbase + GRER_OFFSET); - __raw_writel(gfer, c->regbase + GFER_OFFSET); -} - -static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) -{ - struct pxa_gpio_chip *c; - int gpio = irq_to_gpio(irq); - unsigned long gpdr, mask = GPIO_bit(gpio); - - c = gpio_to_chip(gpio); - - if (type == IRQ_TYPE_PROBE) { - /* Don't mess with enabled GPIOs using preconfigured edges or - * GPIOs set to alternate function or to output during probe - */ - if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) - return 0; - - if (__gpio_is_occupied(gpio)) - return 0; - - type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; - } - - gpdr = __raw_readl(c->regbase + GPDR_OFFSET); - - if (__gpio_is_inverted(gpio)) - __raw_writel(gpdr | mask, c->regbase + GPDR_OFFSET); - else - __raw_writel(gpdr & ~mask, c->regbase + GPDR_OFFSET); - - if (type & IRQ_TYPE_EDGE_RISING) - c->irq_edge_rise |= mask; - else - c->irq_edge_rise &= ~mask; - - if (type & IRQ_TYPE_EDGE_FALLING) - c->irq_edge_fall |= mask; - else - c->irq_edge_fall &= ~mask; - - update_edge_detect(c); - - pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio, - ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), - ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); - return 0; -} - -static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) -{ - struct pxa_gpio_chip *c; - int loop, gpio, gpio_base, n; - unsigned long gedr; - - do { - loop = 0; - for_each_gpio_chip(gpio, c) { - gpio_base = c->chip.base; - - gedr = __raw_readl(c->regbase + GEDR_OFFSET); - gedr = gedr & c->irq_mask; - __raw_writel(gedr, c->regbase + GEDR_OFFSET); - - n = find_first_bit(&gedr, BITS_PER_LONG); - while (n < BITS_PER_LONG) { - loop = 1; - - generic_handle_irq(gpio_to_irq(gpio_base + n)); - n = find_next_bit(&gedr, BITS_PER_LONG, n + 1); - } - } - } while (loop); -} - -static void pxa_ack_muxed_gpio(unsigned int irq) -{ - int gpio = irq_to_gpio(irq); - struct pxa_gpio_chip *c = gpio_to_chip(gpio); - - __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); -} - -static void pxa_mask_muxed_gpio(unsigned int irq) -{ - int gpio = irq_to_gpio(irq); - struct pxa_gpio_chip *c = gpio_to_chip(gpio); - uint32_t grer, gfer; - - c->irq_mask &= ~GPIO_bit(gpio); - - grer = __raw_readl(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio); - gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio); - __raw_writel(grer, c->regbase + GRER_OFFSET); - __raw_writel(gfer, c->regbase + GFER_OFFSET); -} - -static void pxa_unmask_muxed_gpio(unsigned int irq) -{ - int gpio = irq_to_gpio(irq); - struct pxa_gpio_chip *c = gpio_to_chip(gpio); - - c->irq_mask |= GPIO_bit(gpio); - update_edge_detect(c); -} - -static struct irq_chip pxa_muxed_gpio_chip = { - .name = "GPIO", - .ack = pxa_ack_muxed_gpio, - .mask = pxa_mask_muxed_gpio, - .unmask = pxa_unmask_muxed_gpio, - .set_type = pxa_gpio_irq_type, -}; - -void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn) -{ - struct pxa_gpio_chip *c; - int gpio, irq; - - pxa_last_gpio = end; - - /* Initialize GPIO chips */ - pxa_init_gpio_chip(end); - - /* clear all GPIO edge detects */ - for_each_gpio_chip(gpio, c) { - __raw_writel(0, c->regbase + GFER_OFFSET); - __raw_writel(0, c->regbase + GRER_OFFSET); - __raw_writel(~0,c->regbase + GEDR_OFFSET); - } - - for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) { - set_irq_chip(irq, &pxa_muxed_gpio_chip); - set_irq_handler(irq, handle_edge_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - } - - /* Install handler for GPIO>=2 edge detect interrupts */ - set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler); - pxa_muxed_gpio_chip.set_wake = fn; -} - -#ifdef CONFIG_PM -static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state) -{ - struct pxa_gpio_chip *c; - int gpio; - - for_each_gpio_chip(gpio, c) { - c->saved_gplr = __raw_readl(c->regbase + GPLR_OFFSET); - c->saved_gpdr = __raw_readl(c->regbase + GPDR_OFFSET); - c->saved_grer = __raw_readl(c->regbase + GRER_OFFSET); - c->saved_gfer = __raw_readl(c->regbase + GFER_OFFSET); - - /* Clear GPIO transition detect bits */ - __raw_writel(0xffffffff, c->regbase + GEDR_OFFSET); - } - return 0; -} - -static int pxa_gpio_resume(struct sys_device *dev) -{ - struct pxa_gpio_chip *c; - int gpio; - - for_each_gpio_chip(gpio, c) { - /* restore level with set/clear */ - __raw_writel( c->saved_gplr, c->regbase + GPSR_OFFSET); - __raw_writel(~c->saved_gplr, c->regbase + GPCR_OFFSET); - - __raw_writel(c->saved_grer, c->regbase + GRER_OFFSET); - __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET); - __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET); - } - return 0; -} -#else -#define pxa_gpio_suspend NULL -#define pxa_gpio_resume NULL -#endif - -struct sysdev_class pxa_gpio_sysclass = { - .name = "gpio", - .suspend = pxa_gpio_suspend, - .resume = pxa_gpio_resume, -}; - -static int __init pxa_gpio_init(void) -{ - return sysdev_class_register(&pxa_gpio_sysclass); -} - -core_initcall(pxa_gpio_init); diff --git a/arch/arm/plat-pxa/include/plat/gpio.h b/arch/arm/plat-pxa/include/plat/gpio.h deleted file mode 100644 index 44248cb926a..00000000000 --- a/arch/arm/plat-pxa/include/plat/gpio.h +++ /dev/null @@ -1,62 +0,0 @@ -#ifndef __PLAT_GPIO_H -#define __PLAT_GPIO_H - -/* - * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with - * one set of registers. The register offsets are organized below: - * - * GPLR GPDR GPSR GPCR GRER GFER GEDR - * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 - * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C - * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 - * - * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 - * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C - * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 - * - * NOTE: - * BANK 3 is only available on PXA27x and later processors. - * BANK 4 and 5 are only available on PXA935 - */ - -#define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n)) - -#define GPLR_OFFSET 0x00 -#define GPDR_OFFSET 0x0C -#define GPSR_OFFSET 0x18 -#define GPCR_OFFSET 0x24 -#define GRER_OFFSET 0x30 -#define GFER_OFFSET 0x3C -#define GEDR_OFFSET 0x48 - -static inline int gpio_get_value(unsigned gpio) -{ - if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) - return GPLR(gpio) & GPIO_bit(gpio); - else - return __gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) { - if (value) - GPSR(gpio) = GPIO_bit(gpio); - else - GPCR(gpio) = GPIO_bit(gpio); - } else - __gpio_set_value(gpio, value); -} - -#define gpio_cansleep __gpio_cansleep - -/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85). - * Those cases currently cause holes in the GPIO number space, the - * actual number of the last GPIO is recorded by 'pxa_last_gpio'. - */ -extern int pxa_last_gpio; - -typedef int (*set_wake_t)(unsigned int irq, unsigned int on); - -extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn); -#endif /* __PLAT_GPIO_H */ diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h index 64019464c8d..10bc4f3757d 100644 --- a/arch/arm/plat-pxa/include/plat/mfp.h +++ b/arch/arm/plat-pxa/include/plat/mfp.h @@ -16,7 +16,7 @@ #ifndef __ASM_PLAT_MFP_H #define __ASM_PLAT_MFP_H -#define mfp_to_gpio(m) ((m) % 128) +#define mfp_to_gpio(m) ((m) % 256) /* list of all the configurable MFP pins */ enum { @@ -150,6 +150,74 @@ enum { MFP_PIN_GPIO125, MFP_PIN_GPIO126, MFP_PIN_GPIO127, + + MFP_PIN_GPIO128, + MFP_PIN_GPIO129, + MFP_PIN_GPIO130, + MFP_PIN_GPIO131, + MFP_PIN_GPIO132, + MFP_PIN_GPIO133, + MFP_PIN_GPIO134, + MFP_PIN_GPIO135, + MFP_PIN_GPIO136, + MFP_PIN_GPIO137, + MFP_PIN_GPIO138, + MFP_PIN_GPIO139, + MFP_PIN_GPIO140, + MFP_PIN_GPIO141, + MFP_PIN_GPIO142, + MFP_PIN_GPIO143, + MFP_PIN_GPIO144, + MFP_PIN_GPIO145, + MFP_PIN_GPIO146, + MFP_PIN_GPIO147, + MFP_PIN_GPIO148, + MFP_PIN_GPIO149, + MFP_PIN_GPIO150, + MFP_PIN_GPIO151, + MFP_PIN_GPIO152, + MFP_PIN_GPIO153, + MFP_PIN_GPIO154, + MFP_PIN_GPIO155, + MFP_PIN_GPIO156, + MFP_PIN_GPIO157, + MFP_PIN_GPIO158, + MFP_PIN_GPIO159, + MFP_PIN_GPIO160, + MFP_PIN_GPIO161, + MFP_PIN_GPIO162, + MFP_PIN_GPIO163, + MFP_PIN_GPIO164, + MFP_PIN_GPIO165, + MFP_PIN_GPIO166, + MFP_PIN_GPIO167, + MFP_PIN_GPIO168, + MFP_PIN_GPIO169, + MFP_PIN_GPIO170, + MFP_PIN_GPIO171, + MFP_PIN_GPIO172, + MFP_PIN_GPIO173, + MFP_PIN_GPIO174, + MFP_PIN_GPIO175, + MFP_PIN_GPIO176, + MFP_PIN_GPIO177, + MFP_PIN_GPIO178, + MFP_PIN_GPIO179, + MFP_PIN_GPIO180, + MFP_PIN_GPIO181, + MFP_PIN_GPIO182, + MFP_PIN_GPIO183, + MFP_PIN_GPIO184, + MFP_PIN_GPIO185, + MFP_PIN_GPIO186, + MFP_PIN_GPIO187, + MFP_PIN_GPIO188, + MFP_PIN_GPIO189, + MFP_PIN_GPIO190, + MFP_PIN_GPIO191, + + MFP_PIN_GPIO255 = 255, + MFP_PIN_GPIO0_2, MFP_PIN_GPIO1_2, MFP_PIN_GPIO2_2, @@ -248,6 +316,13 @@ enum { MFP_PIN_PMIC_INT, MFP_PIN_RDY, + /* additional pins on MMP2 */ + MFP_PIN_TWSI1_SCL, + MFP_PIN_TWSI1_SDA, + MFP_PIN_TWSI4_SCL, + MFP_PIN_TWSI4_SDA, + MFP_PIN_CLK_REQ, + MFP_PIN_MAX, }; @@ -325,8 +400,9 @@ typedef unsigned long mfp_cfg_t; #define MFP_PULL_LOW (0x1 << 21) #define MFP_PULL_HIGH (0x2 << 21) #define MFP_PULL_BOTH (0x3 << 21) -#define MFP_PULL_MASK (0x3 << 21) -#define MFP_PULL(x) (((x) >> 21) & 0x3) +#define MFP_PULL_FLOAT (0x4 << 21) +#define MFP_PULL_MASK (0x7 << 21) +#define MFP_PULL(x) (((x) >> 21) & 0x7) #define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\ MFP_LPM_EDGE_NONE | MFP_PULL_NONE) @@ -358,7 +434,7 @@ typedef unsigned long mfp_cfg_t; * * mfp_init_addr() - accepts a table of "mfp_addr_map" structure, which * represents a range of MFP pins from "start" to "end", with the offset - * begining at "offset", to define a single pin, let "end" = -1. + * beginning at "offset", to define a single pin, let "end" = -1. * * use * @@ -380,7 +456,7 @@ struct mfp_addr_map { #define MFP_ADDR_END { MFP_PIN_INVALID, 0 } -void __init mfp_init_base(unsigned long mfpr_base); +void __init mfp_init_base(void __iomem *mfpr_base); void __init mfp_init_addr(struct mfp_addr_map *map); /* diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c index e716c622a17..2c4dbb1f423 100644 --- a/arch/arm/plat-pxa/mfp.c +++ b/arch/arm/plat-pxa/mfp.c @@ -17,7 +17,6 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/sysdev.h> #include <plat/mfp.h> @@ -77,11 +76,13 @@ * MFPR_PULL_LOW 1 0 1 * MFPR_PULL_HIGH 1 1 0 * MFPR_PULL_BOTH 1 1 1 + * MFPR_PULL_FLOAT 1 0 0 */ #define MFPR_PULL_NONE (0) #define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN) #define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN) #define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN) +#define MFPR_PULL_FLOAT (MFPR_PULL_SEL) /* mfp_spin_lock is used to ensure that MFP register configuration * (most likely a read-modify-write operation) is atomic, and that @@ -108,6 +109,7 @@ static const unsigned long mfpr_lpm[] = { MFPR_LPM_PULL_LOW, MFPR_LPM_PULL_HIGH, MFPR_LPM_FLOAT, + MFPR_LPM_INPUT, }; /* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */ @@ -116,6 +118,7 @@ static const unsigned long mfpr_pull[] = { MFPR_PULL_LOW, MFPR_PULL_HIGH, MFPR_PULL_BOTH, + MFPR_PULL_FLOAT, }; /* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */ @@ -135,10 +138,11 @@ static const unsigned long mfpr_edge[] = { #define mfp_configured(p) ((p)->config != -1) /* - * perform a read-back of any MFPR register to make sure the + * perform a read-back of any valid MFPR register to make sure the * previous writings are finished */ -#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0) +static unsigned long mfpr_off_readback; +#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + mfpr_off_readback) static inline void __mfp_config_run(struct mfp_pin *p) { @@ -204,7 +208,7 @@ unsigned long mfp_read(int mfp) { unsigned long val, flags; - BUG_ON(mfp >= MFP_PIN_MAX); + BUG_ON(mfp < 0 || mfp >= MFP_PIN_MAX); spin_lock_irqsave(&mfp_spin_lock, flags); val = mfpr_readl(mfp_table[mfp].mfpr_off); @@ -217,7 +221,7 @@ void mfp_write(int mfp, unsigned long val) { unsigned long flags; - BUG_ON(mfp >= MFP_PIN_MAX); + BUG_ON(mfp < 0 || mfp >= MFP_PIN_MAX); spin_lock_irqsave(&mfp_spin_lock, flags); mfpr_writel(mfp_table[mfp].mfpr_off, val); @@ -225,7 +229,7 @@ void mfp_write(int mfp, unsigned long val) spin_unlock_irqrestore(&mfp_spin_lock, flags); } -void __init mfp_init_base(unsigned long mfpr_base) +void __init mfp_init_base(void __iomem *mfpr_base) { int i; @@ -233,7 +237,7 @@ void __init mfp_init_base(unsigned long mfpr_base) for (i = 0; i < ARRAY_SIZE(mfp_table); i++) mfp_table[i].config = -1; - mfpr_mmio_base = (void __iomem *)mfpr_base; + mfpr_mmio_base = mfpr_base; } void __init mfp_init_addr(struct mfp_addr_map *map) @@ -244,6 +248,9 @@ void __init mfp_init_addr(struct mfp_addr_map *map) spin_lock_irqsave(&mfp_spin_lock, flags); + /* mfp offset for readback */ + mfpr_off_readback = map[0].offset; + for (p = map; p->start != MFP_PIN_INVALID; p++) { offset = p->offset; i = p->start; diff --git a/arch/arm/plat-pxa/ssp.c b/arch/arm/plat-pxa/ssp.c new file mode 100644 index 00000000000..3ea02903d75 --- /dev/null +++ b/arch/arm/plat-pxa/ssp.c @@ -0,0 +1,292 @@ +/* + * linux/arch/arm/mach-pxa/ssp.c + * + * based on linux/arch/arm/mach-sa1100/ssp.c by Russell King + * + * Copyright (C) 2003 Russell King. + * Copyright (C) 2003 Wolfson Microelectronics PLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * PXA2xx SSP driver. This provides the generic core for simple + * IO-based SSP applications and allows easy port setup for DMA access. + * + * Author: Liam Girdwood <liam.girdwood@wolfsonmicro.com> + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/errno.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/init.h> +#include <linux/mutex.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/spi/pxa2xx_spi.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_device.h> + +#include <asm/irq.h> +#include <mach/hardware.h> + +static DEFINE_MUTEX(ssp_lock); +static LIST_HEAD(ssp_list); + +struct ssp_device *pxa_ssp_request(int port, const char *label) +{ + struct ssp_device *ssp = NULL; + + mutex_lock(&ssp_lock); + + list_for_each_entry(ssp, &ssp_list, node) { + if (ssp->port_id == port && ssp->use_count == 0) { + ssp->use_count++; + ssp->label = label; + break; + } + } + + mutex_unlock(&ssp_lock); + + if (&ssp->node == &ssp_list) + return NULL; + + return ssp; +} +EXPORT_SYMBOL(pxa_ssp_request); + +struct ssp_device *pxa_ssp_request_of(const struct device_node *of_node, + const char *label) +{ + struct ssp_device *ssp = NULL; + + mutex_lock(&ssp_lock); + + list_for_each_entry(ssp, &ssp_list, node) { + if (ssp->of_node == of_node && ssp->use_count == 0) { + ssp->use_count++; + ssp->label = label; + break; + } + } + + mutex_unlock(&ssp_lock); + + if (&ssp->node == &ssp_list) + return NULL; + + return ssp; +} +EXPORT_SYMBOL(pxa_ssp_request_of); + +void pxa_ssp_free(struct ssp_device *ssp) +{ + mutex_lock(&ssp_lock); + if (ssp->use_count) { + ssp->use_count--; + ssp->label = NULL; + } else + dev_err(&ssp->pdev->dev, "device already free\n"); + mutex_unlock(&ssp_lock); +} +EXPORT_SYMBOL(pxa_ssp_free); + +#ifdef CONFIG_OF +static const struct of_device_id pxa_ssp_of_ids[] = { + { .compatible = "mrvl,pxa25x-ssp", .data = (void *) PXA25x_SSP }, + { .compatible = "mvrl,pxa25x-nssp", .data = (void *) PXA25x_NSSP }, + { .compatible = "mrvl,pxa27x-ssp", .data = (void *) PXA27x_SSP }, + { .compatible = "mrvl,pxa3xx-ssp", .data = (void *) PXA3xx_SSP }, + { .compatible = "mvrl,pxa168-ssp", .data = (void *) PXA168_SSP }, + { .compatible = "mrvl,pxa910-ssp", .data = (void *) PXA910_SSP }, + { .compatible = "mrvl,ce4100-ssp", .data = (void *) CE4100_SSP }, + { .compatible = "mrvl,lpss-ssp", .data = (void *) LPSS_SSP }, + { }, +}; +MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids); +#endif + +static int pxa_ssp_probe(struct platform_device *pdev) +{ + struct resource *res; + struct ssp_device *ssp; + struct device *dev = &pdev->dev; + + ssp = devm_kzalloc(dev, sizeof(struct ssp_device), GFP_KERNEL); + if (ssp == NULL) + return -ENOMEM; + + ssp->pdev = pdev; + + ssp->clk = devm_clk_get(dev, NULL); + if (IS_ERR(ssp->clk)) + return PTR_ERR(ssp->clk); + + if (dev->of_node) { + struct of_phandle_args dma_spec; + struct device_node *np = dev->of_node; + int ret; + + /* + * FIXME: we should allocate the DMA channel from this + * context and pass the channel down to the ssp users. + * For now, we lookup the rx and tx indices manually + */ + + /* rx */ + ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", + 0, &dma_spec); + + if (ret) { + dev_err(dev, "Can't parse dmas property\n"); + return -ENODEV; + } + ssp->drcmr_rx = dma_spec.args[0]; + of_node_put(dma_spec.np); + + /* tx */ + ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", + 1, &dma_spec); + if (ret) { + dev_err(dev, "Can't parse dmas property\n"); + return -ENODEV; + } + ssp->drcmr_tx = dma_spec.args[0]; + of_node_put(dma_spec.np); + } else { + res = platform_get_resource(pdev, IORESOURCE_DMA, 0); + if (res == NULL) { + dev_err(dev, "no SSP RX DRCMR defined\n"); + return -ENODEV; + } + ssp->drcmr_rx = res->start; + + res = platform_get_resource(pdev, IORESOURCE_DMA, 1); + if (res == NULL) { + dev_err(dev, "no SSP TX DRCMR defined\n"); + return -ENODEV; + } + ssp->drcmr_tx = res->start; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(dev, "no memory resource defined\n"); + return -ENODEV; + } + + res = devm_request_mem_region(dev, res->start, resource_size(res), + pdev->name); + if (res == NULL) { + dev_err(dev, "failed to request memory resource\n"); + return -EBUSY; + } + + ssp->phys_base = res->start; + + ssp->mmio_base = devm_ioremap(dev, res->start, resource_size(res)); + if (ssp->mmio_base == NULL) { + dev_err(dev, "failed to ioremap() registers\n"); + return -ENODEV; + } + + ssp->irq = platform_get_irq(pdev, 0); + if (ssp->irq < 0) { + dev_err(dev, "no IRQ resource defined\n"); + return -ENODEV; + } + + if (dev->of_node) { + const struct of_device_id *id = + of_match_device(of_match_ptr(pxa_ssp_of_ids), dev); + ssp->type = (int) id->data; + } else { + const struct platform_device_id *id = + platform_get_device_id(pdev); + ssp->type = (int) id->driver_data; + + /* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id + * starts from 0, do a translation here + */ + ssp->port_id = pdev->id + 1; + } + + ssp->use_count = 0; + ssp->of_node = dev->of_node; + + mutex_lock(&ssp_lock); + list_add(&ssp->node, &ssp_list); + mutex_unlock(&ssp_lock); + + platform_set_drvdata(pdev, ssp); + + return 0; +} + +static int pxa_ssp_remove(struct platform_device *pdev) +{ + struct resource *res; + struct ssp_device *ssp; + + ssp = platform_get_drvdata(pdev); + if (ssp == NULL) + return -ENODEV; + + iounmap(ssp->mmio_base); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, resource_size(res)); + + clk_put(ssp->clk); + + mutex_lock(&ssp_lock); + list_del(&ssp->node); + mutex_unlock(&ssp_lock); + + kfree(ssp); + return 0; +} + +static const struct platform_device_id ssp_id_table[] = { + { "pxa25x-ssp", PXA25x_SSP }, + { "pxa25x-nssp", PXA25x_NSSP }, + { "pxa27x-ssp", PXA27x_SSP }, + { "pxa168-ssp", PXA168_SSP }, + { "pxa910-ssp", PXA910_SSP }, + { }, +}; + +static struct platform_driver pxa_ssp_driver = { + .probe = pxa_ssp_probe, + .remove = pxa_ssp_remove, + .driver = { + .owner = THIS_MODULE, + .name = "pxa2xx-ssp", + .of_match_table = of_match_ptr(pxa_ssp_of_ids), + }, + .id_table = ssp_id_table, +}; + +static int __init pxa_ssp_init(void) +{ + return platform_driver_register(&pxa_ssp_driver); +} + +static void __exit pxa_ssp_exit(void) +{ + platform_driver_unregister(&pxa_ssp_driver); +} + +arch_initcall(pxa_ssp_init); +module_exit(pxa_ssp_exit); + +MODULE_DESCRIPTION("PXA SSP driver"); +MODULE_AUTHOR("Liam Girdwood"); +MODULE_LICENSE("GPL"); |