diff options
Diffstat (limited to 'arch/arm/plat-orion/time.c')
| -rw-r--r-- | arch/arm/plat-orion/time.c | 23 |
1 files changed, 10 insertions, 13 deletions
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 1ed8d1397fc..261258f717f 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -16,7 +16,8 @@ #include <linux/clockchips.h> #include <linux/interrupt.h> #include <linux/irq.h> -#include <asm/sched_clock.h> +#include <linux/sched_clock.h> +#include <plat/time.h> /* * MBus bridge block registers. @@ -60,7 +61,7 @@ static u32 ticks_per_jiffy; * at least 7.5ns (133MHz TCLK). */ -static u32 notrace orion_read_sched_clock(void) +static u64 notrace orion_read_sched_clock(void) { return ~readl(timer_base + TIMER0_VAL_OFF); } @@ -156,7 +157,6 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) static struct clock_event_device orion_clkevt = { .name = "orion_tick", .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .shift = 32, .rating = 300, .set_next_event = orion_clkevt_next_event, .set_mode = orion_clkevt_mode, @@ -175,18 +175,18 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) static struct irqaction orion_timer_irq = { .name = "orion_tick", - .flags = IRQF_DISABLED | IRQF_TIMER, + .flags = IRQF_TIMER, .handler = orion_timer_interrupt }; void __init -orion_time_set_base(u32 _timer_base) +orion_time_set_base(void __iomem *_timer_base) { - timer_base = (void __iomem *)_timer_base; + timer_base = _timer_base; } void __init -orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask, +orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask, unsigned int irq, unsigned int tclk) { u32 u; @@ -194,7 +194,7 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask, /* * Set SoC-specific data. */ - bridge_base = (void __iomem *)_bridge_base; + bridge_base = _bridge_base; bridge_timer1_clr_mask = _bridge_timer1_clr_mask; ticks_per_jiffy = (tclk + HZ/2) / HZ; @@ -202,7 +202,7 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask, /* * Set scale and timer for sched_clock. */ - setup_sched_clock(orion_read_sched_clock, 32, tclk); + sched_clock_register(orion_read_sched_clock, 32, tclk); /* * Setup free-running clocksource timer (interrupts @@ -221,9 +221,6 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask, * Setup clockevent timer (interrupt-driven). */ setup_irq(irq, &orion_timer_irq); - orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift); - orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt); - orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt); orion_clkevt.cpumask = cpumask_of(0); - clockevents_register_device(&orion_clkevt); + clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe); } |