diff options
Diffstat (limited to 'arch/arm/plat-omap/dma.c')
| -rw-r--r-- | arch/arm/plat-omap/dma.c | 953 |
1 files changed, 447 insertions, 506 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index f5c5b8da9a8..b5608b1f9fb 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -15,6 +15,10 @@ * * Support functions for the OMAP internal DMA channels. * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Converted DMA library into DMA platform driver. + * - G, Manjunath Kondaiah <manjugk@ti.com> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -32,11 +36,16 @@ #include <linux/slab.h> #include <linux/delay.h> -#include <asm/system.h> -#include <mach/hardware.h> -#include <plat/dma.h> +#include <linux/omap-dma.h> -#include <plat/tc.h> +/* + * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA + * channels that an instance of the SDMA IP block can support. Used + * to size arrays. (The actual maximum on a particular SoC may be less + * than this -- for example, OMAP1 SDMA instances only support 17 logical + * DMA channels.) + */ +#define MAX_LOGICAL_DMA_CH_COUNT 32 #undef DEBUG @@ -49,39 +58,23 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; #endif #define OMAP_DMA_ACTIVE 0x01 -#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe +#define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) +static struct omap_system_dma_plat_info *p; +static struct omap_dma_dev_attr *d; + static int enable_1510_mode; +static u32 errata; static struct omap_dma_global_context_registers { u32 dma_irqenable_l0; + u32 dma_irqenable_l1; u32 dma_ocp_sysconfig; u32 dma_gcr; } omap_dma_global_context; -struct omap_dma_lch { - int next_lch; - int dev_id; - u16 saved_csr; - u16 enabled_irqs; - const char *dev_name; - void (*callback)(int lch, u16 ch_status, void *data); - void *data; - -#ifndef CONFIG_ARCH_OMAP1 - /* required for Dynamic chaining */ - int prev_linked_ch; - int next_linked_ch; - int state; - int chain_id; - - int status; -#endif - long flags; -}; - struct dma_link_info { int *linked_dmach_q; int no_of_lchs_linked; @@ -137,15 +130,6 @@ static int omap_dma_reserve_channels; static spinlock_t dma_chan_lock; static struct omap_dma_lch *dma_chan; -static void __iomem *omap_dma_base; - -static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = { - INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3, - INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7, - INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10, - INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13, - INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD -}; static inline void disable_lnk(int lch); static void omap_disable_channel_irq(int lch); @@ -154,27 +138,9 @@ static inline void omap_enable_channel_irq(int lch); #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ __func__); -#define dma_read(reg) \ -({ \ - u32 __val; \ - if (cpu_class_is_omap1()) \ - __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \ - else \ - __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \ - __val; \ -}) - -#define dma_write(val, reg) \ -({ \ - if (cpu_class_is_omap1()) \ - __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \ - else \ - __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \ -}) - #ifdef CONFIG_ARCH_OMAP15XX /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ -int omap_dma_in_1510_mode(void) +static int omap_dma_in_1510_mode(void) { return enable_1510_mode; } @@ -204,24 +170,17 @@ static inline void set_gdma_dev(int req, int dev) } #else #define set_gdma_dev(req, dev) do {} while (0) +#define omap_readl(reg) 0 +#define omap_writel(val, reg) do {} while (0) #endif -/* Omap1 only */ -static void clear_lch_regs(int lch) -{ - int i; - void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch); - - for (i = 0; i < 0x2c; i += 2) - __raw_writew(0, lch_base + i); -} - +#ifdef CONFIG_ARCH_OMAP1 void omap_set_dma_priority(int lch, int dst_port, int priority) { unsigned long reg; u32 l; - if (cpu_class_is_omap1()) { + if (dma_omap1()) { switch (dst_port) { case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ reg = OMAP_TC_OCPT1_PRIOR; @@ -244,18 +203,22 @@ void omap_set_dma_priority(int lch, int dst_port, int priority) l |= (priority & 0xf) << 8; omap_writel(l, reg); } +} +#endif - if (cpu_class_is_omap2()) { - u32 ccr; +#ifdef CONFIG_ARCH_OMAP2PLUS +void omap_set_dma_priority(int lch, int dst_port, int priority) +{ + u32 ccr; - ccr = dma_read(CCR(lch)); - if (priority) - ccr |= (1 << 6); - else - ccr &= ~(1 << 6); - dma_write(ccr, CCR(lch)); - } + ccr = p->dma_read(CCR, lch); + if (priority) + ccr |= (1 << 6); + else + ccr &= ~(1 << 6); + p->dma_write(ccr, CCR, lch); } +#endif EXPORT_SYMBOL(omap_set_dma_priority); void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, @@ -264,31 +227,31 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, { u32 l; - l = dma_read(CSDP(lch)); + l = p->dma_read(CSDP, lch); l &= ~0x03; l |= data_type; - dma_write(l, CSDP(lch)); + p->dma_write(l, CSDP, lch); - if (cpu_class_is_omap1()) { + if (dma_omap1()) { u16 ccr; - ccr = dma_read(CCR(lch)); + ccr = p->dma_read(CCR, lch); ccr &= ~(1 << 5); if (sync_mode == OMAP_DMA_SYNC_FRAME) ccr |= 1 << 5; - dma_write(ccr, CCR(lch)); + p->dma_write(ccr, CCR, lch); - ccr = dma_read(CCR2(lch)); + ccr = p->dma_read(CCR2, lch); ccr &= ~(1 << 2); if (sync_mode == OMAP_DMA_SYNC_BLOCK) ccr |= 1 << 2; - dma_write(ccr, CCR2(lch)); + p->dma_write(ccr, CCR2, lch); } - if (cpu_class_is_omap2() && dma_trigger) { + if (dma_omap2plus() && dma_trigger) { u32 val; - val = dma_read(CCR(lch)); + val = p->dma_read(CCR, lch); /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ val &= ~((1 << 23) | (3 << 19) | 0x1f); @@ -313,11 +276,11 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, } else { val &= ~(1 << 24); /* dest synch */ } - dma_write(val, CCR(lch)); + p->dma_write(val, CCR, lch); } - dma_write(elem_count, CEN(lch)); - dma_write(frame_count, CFN(lch)); + p->dma_write(elem_count, CEN, lch); + p->dma_write(frame_count, CFN, lch); } EXPORT_SYMBOL(omap_set_dma_transfer_params); @@ -325,10 +288,10 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) { BUG_ON(omap_dma_in_1510_mode()); - if (cpu_class_is_omap1()) { + if (dma_omap1()) { u16 w; - w = dma_read(CCR2(lch)); + w = p->dma_read(CCR2, lch); w &= ~0x03; switch (mode) { @@ -343,23 +306,22 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) default: BUG(); } - dma_write(w, CCR2(lch)); + p->dma_write(w, CCR2, lch); - w = dma_read(LCH_CTRL(lch)); + w = p->dma_read(LCH_CTRL, lch); w &= ~0x0f; /* Default is channel type 2D */ if (mode) { - dma_write((u16)color, COLOR_L(lch)); - dma_write((u16)(color >> 16), COLOR_U(lch)); + p->dma_write(color, COLOR, lch); w |= 1; /* Channel type G */ } - dma_write(w, LCH_CTRL(lch)); + p->dma_write(w, LCH_CTRL, lch); } - if (cpu_class_is_omap2()) { + if (dma_omap2plus()) { u32 val; - val = dma_read(CCR(lch)); + val = p->dma_read(CCR, lch); val &= ~((1 << 17) | (1 << 16)); switch (mode) { @@ -374,36 +336,36 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) default: BUG(); } - dma_write(val, CCR(lch)); + p->dma_write(val, CCR, lch); color &= 0xffffff; - dma_write(color, COLOR(lch)); + p->dma_write(color, COLOR, lch); } } EXPORT_SYMBOL(omap_set_dma_color_mode); void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) { - if (cpu_class_is_omap2()) { + if (dma_omap2plus()) { u32 csdp; - csdp = dma_read(CSDP(lch)); + csdp = p->dma_read(CSDP, lch); csdp &= ~(0x3 << 16); csdp |= (mode << 16); - dma_write(csdp, CSDP(lch)); + p->dma_write(csdp, CSDP, lch); } } EXPORT_SYMBOL(omap_set_dma_write_mode); void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) { - if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { + if (dma_omap1() && !dma_omap15xx()) { u32 l; - l = dma_read(LCH_CTRL(lch)); + l = p->dma_read(LCH_CTRL, lch); l &= ~0x7; l |= mode; - dma_write(l, LCH_CTRL(lch)); + p->dma_write(l, LCH_CTRL, lch); } } EXPORT_SYMBOL(omap_set_dma_channel_mode); @@ -415,30 +377,24 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode, { u32 l; - if (cpu_class_is_omap1()) { + if (dma_omap1()) { u16 w; - w = dma_read(CSDP(lch)); + w = p->dma_read(CSDP, lch); w &= ~(0x1f << 2); w |= src_port << 2; - dma_write(w, CSDP(lch)); + p->dma_write(w, CSDP, lch); } - l = dma_read(CCR(lch)); + l = p->dma_read(CCR, lch); l &= ~(0x03 << 12); l |= src_amode << 12; - dma_write(l, CCR(lch)); - - if (cpu_class_is_omap1()) { - dma_write(src_start >> 16, CSSA_U(lch)); - dma_write((u16)src_start, CSSA_L(lch)); - } + p->dma_write(l, CCR, lch); - if (cpu_class_is_omap2()) - dma_write(src_start, CSSA(lch)); + p->dma_write(src_start, CSSA, lch); - dma_write(src_ei, CSEI(lch)); - dma_write(src_fi, CSFI(lch)); + p->dma_write(src_ei, CSEI, lch); + p->dma_write(src_fi, CSFI, lch); } EXPORT_SYMBOL(omap_set_dma_src_params); @@ -463,11 +419,11 @@ EXPORT_SYMBOL(omap_set_dma_params); void omap_set_dma_src_index(int lch, int eidx, int fidx) { - if (cpu_class_is_omap2()) + if (dma_omap2plus()) return; - dma_write(eidx, CSEI(lch)); - dma_write(fidx, CSFI(lch)); + p->dma_write(eidx, CSEI, lch); + p->dma_write(fidx, CSFI, lch); } EXPORT_SYMBOL(omap_set_dma_src_index); @@ -475,11 +431,11 @@ void omap_set_dma_src_data_pack(int lch, int enable) { u32 l; - l = dma_read(CSDP(lch)); + l = p->dma_read(CSDP, lch); l &= ~(1 << 6); if (enable) l |= (1 << 6); - dma_write(l, CSDP(lch)); + p->dma_write(l, CSDP, lch); } EXPORT_SYMBOL(omap_set_dma_src_data_pack); @@ -488,20 +444,20 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) unsigned int burst = 0; u32 l; - l = dma_read(CSDP(lch)); + l = p->dma_read(CSDP, lch); l &= ~(0x03 << 7); switch (burst_mode) { case OMAP_DMA_DATA_BURST_DIS: break; case OMAP_DMA_DATA_BURST_4: - if (cpu_class_is_omap2()) + if (dma_omap2plus()) burst = 0x1; else burst = 0x2; break; case OMAP_DMA_DATA_BURST_8: - if (cpu_class_is_omap2()) { + if (dma_omap2plus()) { burst = 0x2; break; } @@ -511,7 +467,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) * fall through */ case OMAP_DMA_DATA_BURST_16: - if (cpu_class_is_omap2()) { + if (dma_omap2plus()) { burst = 0x3; break; } @@ -524,7 +480,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) } l |= (burst << 7); - dma_write(l, CSDP(lch)); + p->dma_write(l, CSDP, lch); } EXPORT_SYMBOL(omap_set_dma_src_burst_mode); @@ -535,38 +491,32 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, { u32 l; - if (cpu_class_is_omap1()) { - l = dma_read(CSDP(lch)); + if (dma_omap1()) { + l = p->dma_read(CSDP, lch); l &= ~(0x1f << 9); l |= dest_port << 9; - dma_write(l, CSDP(lch)); + p->dma_write(l, CSDP, lch); } - l = dma_read(CCR(lch)); + l = p->dma_read(CCR, lch); l &= ~(0x03 << 14); l |= dest_amode << 14; - dma_write(l, CCR(lch)); - - if (cpu_class_is_omap1()) { - dma_write(dest_start >> 16, CDSA_U(lch)); - dma_write(dest_start, CDSA_L(lch)); - } + p->dma_write(l, CCR, lch); - if (cpu_class_is_omap2()) - dma_write(dest_start, CDSA(lch)); + p->dma_write(dest_start, CDSA, lch); - dma_write(dst_ei, CDEI(lch)); - dma_write(dst_fi, CDFI(lch)); + p->dma_write(dst_ei, CDEI, lch); + p->dma_write(dst_fi, CDFI, lch); } EXPORT_SYMBOL(omap_set_dma_dest_params); void omap_set_dma_dest_index(int lch, int eidx, int fidx) { - if (cpu_class_is_omap2()) + if (dma_omap2plus()) return; - dma_write(eidx, CDEI(lch)); - dma_write(fidx, CDFI(lch)); + p->dma_write(eidx, CDEI, lch); + p->dma_write(fidx, CDFI, lch); } EXPORT_SYMBOL(omap_set_dma_dest_index); @@ -574,11 +524,11 @@ void omap_set_dma_dest_data_pack(int lch, int enable) { u32 l; - l = dma_read(CSDP(lch)); + l = p->dma_read(CSDP, lch); l &= ~(1 << 13); if (enable) l |= 1 << 13; - dma_write(l, CSDP(lch)); + p->dma_write(l, CSDP, lch); } EXPORT_SYMBOL(omap_set_dma_dest_data_pack); @@ -587,26 +537,26 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) unsigned int burst = 0; u32 l; - l = dma_read(CSDP(lch)); + l = p->dma_read(CSDP, lch); l &= ~(0x03 << 14); switch (burst_mode) { case OMAP_DMA_DATA_BURST_DIS: break; case OMAP_DMA_DATA_BURST_4: - if (cpu_class_is_omap2()) + if (dma_omap2plus()) burst = 0x1; else burst = 0x2; break; case OMAP_DMA_DATA_BURST_8: - if (cpu_class_is_omap2()) + if (dma_omap2plus()) burst = 0x2; else burst = 0x3; break; case OMAP_DMA_DATA_BURST_16: - if (cpu_class_is_omap2()) { + if (dma_omap2plus()) { burst = 0x3; break; } @@ -620,28 +570,31 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) return; } l |= (burst << 14); - dma_write(l, CSDP(lch)); + p->dma_write(l, CSDP, lch); } EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); static inline void omap_enable_channel_irq(int lch) { - u32 status; - /* Clear CSR */ - if (cpu_class_is_omap1()) - status = dma_read(CSR(lch)); - else if (cpu_class_is_omap2()) - dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch)); + if (dma_omap1()) + p->dma_read(CSR, lch); + else + p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); /* Enable some nice interrupts. */ - dma_write(dma_chan[lch].enabled_irqs, CICR(lch)); + p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch); } -static void omap_disable_channel_irq(int lch) +static inline void omap_disable_channel_irq(int lch) { - if (cpu_class_is_omap2()) - dma_write(0, CICR(lch)); + /* disable channel interrupts */ + p->dma_write(0, CICR, lch); + /* Clear CSR */ + if (dma_omap1()) + p->dma_read(CSR, lch); + else + p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); } void omap_enable_dma_irq(int lch, u16 bits) @@ -660,9 +613,9 @@ static inline void enable_lnk(int lch) { u32 l; - l = dma_read(CLNK_CTRL(lch)); + l = p->dma_read(CLNK_CTRL, lch); - if (cpu_class_is_omap1()) + if (dma_omap1()) l &= ~(1 << 14); /* Set the ENABLE_LNK bits */ @@ -670,34 +623,34 @@ static inline void enable_lnk(int lch) l = dma_chan[lch].next_lch | (1 << 15); #ifndef CONFIG_ARCH_OMAP1 - if (cpu_class_is_omap2()) + if (dma_omap2plus()) if (dma_chan[lch].next_linked_ch != -1) l = dma_chan[lch].next_linked_ch | (1 << 15); #endif - dma_write(l, CLNK_CTRL(lch)); + p->dma_write(l, CLNK_CTRL, lch); } static inline void disable_lnk(int lch) { u32 l; - l = dma_read(CLNK_CTRL(lch)); + l = p->dma_read(CLNK_CTRL, lch); /* Disable interrupts */ - if (cpu_class_is_omap1()) { - dma_write(0, CICR(lch)); + omap_disable_channel_irq(lch); + + if (dma_omap1()) { /* Set the STOP_LNK bit */ l |= 1 << 14; } - if (cpu_class_is_omap2()) { - omap_disable_channel_irq(lch); + if (dma_omap2plus()) { /* Clear the ENABLE_LNK bit */ l &= ~(1 << 15); } - dma_write(l, CLNK_CTRL(lch)); + p->dma_write(l, CLNK_CTRL, lch); dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; } @@ -706,13 +659,16 @@ static inline void omap2_enable_irq_lch(int lch) u32 val; unsigned long flags; - if (!cpu_class_is_omap2()) + if (dma_omap1()) return; spin_lock_irqsave(&dma_chan_lock, flags); - val = dma_read(IRQENABLE_L0); + /* clear IRQ STATUS */ + p->dma_write(1 << lch, IRQSTATUS_L0, lch); + /* Enable interrupt */ + val = p->dma_read(IRQENABLE_L0, lch); val |= 1 << lch; - dma_write(val, IRQENABLE_L0); + p->dma_write(val, IRQENABLE_L0, lch); spin_unlock_irqrestore(&dma_chan_lock, flags); } @@ -721,13 +677,16 @@ static inline void omap2_disable_irq_lch(int lch) u32 val; unsigned long flags; - if (!cpu_class_is_omap2()) + if (dma_omap1()) return; spin_lock_irqsave(&dma_chan_lock, flags); - val = dma_read(IRQENABLE_L0); + /* Disable interrupt */ + val = p->dma_read(IRQENABLE_L0, lch); val &= ~(1 << lch); - dma_write(val, IRQENABLE_L0); + p->dma_write(val, IRQENABLE_L0, lch); + /* clear IRQ STATUS */ + p->dma_write(1 << lch, IRQSTATUS_L0, lch); spin_unlock_irqrestore(&dma_chan_lock, flags); } @@ -743,8 +702,8 @@ int omap_request_dma(int dev_id, const char *dev_name, for (ch = 0; ch < dma_chan_count; ch++) { if (free_ch == -1 && dma_chan[ch].dev_id == -1) { free_ch = ch; - if (dev_id == 0) - break; + /* Exit after first free channel found */ + break; } } if (free_ch == -1) { @@ -754,10 +713,10 @@ int omap_request_dma(int dev_id, const char *dev_name, chan = dma_chan + free_ch; chan->dev_id = dev_id; - if (cpu_class_is_omap1()) - clear_lch_regs(free_ch); + if (p->clear_lch_regs) + p->clear_lch_regs(free_ch); - if (cpu_class_is_omap2()) + if (dma_omap2plus()) omap_clear_dma(free_ch); spin_unlock_irqrestore(&dma_chan_lock, flags); @@ -768,7 +727,7 @@ int omap_request_dma(int dev_id, const char *dev_name, chan->flags = 0; #ifndef CONFIG_ARCH_OMAP1 - if (cpu_class_is_omap2()) { + if (dma_omap2plus()) { chan->chain_id = -1; chan->next_linked_ch = -1; } @@ -776,13 +735,13 @@ int omap_request_dma(int dev_id, const char *dev_name, chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; - if (cpu_class_is_omap1()) + if (dma_omap1()) chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; - else if (cpu_class_is_omap2()) + else if (dma_omap2plus()) chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ; - if (cpu_is_omap16xx()) { + if (dma_omap16xx()) { /* If the sync device is set, configure it dynamically. */ if (dev_id != 0) { set_gdma_dev(free_ch + 1, dev_id); @@ -792,17 +751,14 @@ int omap_request_dma(int dev_id, const char *dev_name, * Disable the 1510 compatibility mode and set the sync device * id. */ - dma_write(dev_id | (1 << 10), CCR(free_ch)); - } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) { - dma_write(dev_id, CCR(free_ch)); + p->dma_write(dev_id | (1 << 10), CCR, free_ch); + } else if (dma_omap1()) { + p->dma_write(dev_id, CCR, free_ch); } - if (cpu_class_is_omap2()) { - omap2_enable_irq_lch(free_ch); + if (dma_omap2plus()) { omap_enable_channel_irq(free_ch); - /* Clear the CSR register and IRQ status register */ - dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch)); - dma_write(1 << free_ch, IRQSTATUS_L0); + omap2_enable_irq_lch(free_ch); } *dma_ch_out = free_ch; @@ -821,27 +777,19 @@ void omap_free_dma(int lch) return; } - if (cpu_class_is_omap1()) { - /* Disable all DMA interrupts for the channel. */ - dma_write(0, CICR(lch)); - /* Make sure the DMA transfer is stopped. */ - dma_write(0, CCR(lch)); - } - - if (cpu_class_is_omap2()) { + /* Disable interrupt for logical channel */ + if (dma_omap2plus()) omap2_disable_irq_lch(lch); - /* Clear the CSR register and IRQ status register */ - dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch)); - dma_write(1 << lch, IRQSTATUS_L0); + /* Disable all DMA interrupts for the channel. */ + omap_disable_channel_irq(lch); - /* Disable all DMA interrupts for the channel. */ - dma_write(0, CICR(lch)); + /* Make sure the DMA transfer is stopped. */ + p->dma_write(0, CCR, lch); - /* Make sure the DMA transfer is stopped. */ - dma_write(0, CCR(lch)); + /* Clear registers */ + if (dma_omap2plus()) omap_clear_dma(lch); - } spin_lock_irqsave(&dma_chan_lock, flags); dma_chan[lch].dev_id = -1; @@ -866,7 +814,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) { u32 reg; - if (!cpu_class_is_omap2()) { + if (dma_omap1()) { printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__); return; } @@ -880,7 +828,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) reg |= (0x3 & tparams) << 12; reg |= (arb_rate & 0xff) << 16; - dma_write(reg, GCR); + p->dma_write(reg, GCR, 0); } EXPORT_SYMBOL(omap_dma_set_global_params); @@ -903,14 +851,14 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio, printk(KERN_ERR "Invalid channel id\n"); return -EINVAL; } - l = dma_read(CCR(lch)); + l = p->dma_read(CCR, lch); l &= ~((1 << 6) | (1 << 26)); - if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) + if (d->dev_caps & IS_RW_PRIORITY) l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); else l |= ((read_prio & 0x1) << 6); - dma_write(l, CCR(lch)); + p->dma_write(l, CCR, lch); return 0; } @@ -925,25 +873,7 @@ void omap_clear_dma(int lch) unsigned long flags; local_irq_save(flags); - - if (cpu_class_is_omap1()) { - u32 l; - - l = dma_read(CCR(lch)); - l &= ~OMAP_DMA_CCR_EN; - dma_write(l, CCR(lch)); - - /* Clear pending interrupts */ - l = dma_read(CSR(lch)); - } - - if (cpu_class_is_omap2()) { - int i; - void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch); - for (i = 0; i < 0x44; i += 4) - __raw_writel(0, lch_base + i); - } - + p->clear_dma(lch); local_irq_restore(flags); } EXPORT_SYMBOL(omap_clear_dma); @@ -956,20 +886,21 @@ void omap_start_dma(int lch) * The CPC/CDAC register needs to be initialized to zero * before starting dma transfer. */ - if (cpu_is_omap15xx()) - dma_write(0, CPC(lch)); + if (dma_omap15xx()) + p->dma_write(0, CPC, lch); else - dma_write(0, CDAC(lch)); + p->dma_write(0, CDAC, lch); if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch; - char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT]; + char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; - dma_chan_link_map[lch] = 1; /* Set the link register of the first channel */ enable_lnk(lch); memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); + dma_chan_link_map[lch] = 1; + cur_lch = dma_chan[lch].next_lch; do { next_lch = dma_chan[cur_lch].next_lch; @@ -985,32 +916,25 @@ void omap_start_dma(int lch) cur_lch = next_lch; } while (next_lch != -1); - } else if (cpu_is_omap242x() || - (cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) { - - /* Errata: Need to write lch even if not using chaining */ - dma_write(lch, CLNK_CTRL(lch)); - } + } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS)) + p->dma_write(lch, CLNK_CTRL, lch); omap_enable_channel_irq(lch); - l = dma_read(CCR(lch)); + l = p->dma_read(CCR, lch); + + if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING)) + l |= OMAP_DMA_CCR_BUFFERING_DISABLE; + l |= OMAP_DMA_CCR_EN; /* - * Errata: Inter Frame DMA buffering issue (All OMAP2420 and - * OMAP2430ES1.0): DMA will wrongly buffer elements if packing and - * bursting is enabled. This might result in data gets stalled in - * FIFO at the end of the block. - * Workaround: DMA channels must have BUFFERING_DISABLED bit set to - * guarantee no data will stay in the DMA FIFO in case inter frame - * buffering occurs. + * As dma_write() uses IO accessors which are weakly ordered, there + * is no guarantee that data in coherent DMA memory will be visible + * to the DMA device. Add a memory barrier here to ensure that any + * such data is visible prior to enabling DMA. */ - if (cpu_is_omap2420() || - (cpu_is_omap2430() && (omap_type() == OMAP2430_REV_ES1_0))) - l |= OMAP_DMA_CCR_BUFFERING_DISABLE; - - l |= OMAP_DMA_CCR_EN; - dma_write(l, CCR(lch)); + mb(); + p->dma_write(l, CCR, lch); dma_chan[lch].flags |= OMAP_DMA_ACTIVE; } @@ -1021,47 +945,52 @@ void omap_stop_dma(int lch) u32 l; /* Disable all interrupts on the channel */ - if (cpu_class_is_omap1()) - dma_write(0, CICR(lch)); + omap_disable_channel_irq(lch); - l = dma_read(CCR(lch)); - /* OMAP3 Errata i541: sDMA FIFO draining does not finish */ - if (cpu_is_omap34xx() && (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) { + l = p->dma_read(CCR, lch); + if (IS_DMA_ERRATA(DMA_ERRATA_i541) && + (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) { int i = 0; u32 sys_cf; /* Configure No-Standby */ - l = dma_read(OCP_SYSCONFIG); + l = p->dma_read(OCP_SYSCONFIG, lch); sys_cf = l; l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK; l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); - dma_write(l , OCP_SYSCONFIG); + p->dma_write(l , OCP_SYSCONFIG, 0); - l = dma_read(CCR(lch)); + l = p->dma_read(CCR, lch); l &= ~OMAP_DMA_CCR_EN; - dma_write(l, CCR(lch)); + p->dma_write(l, CCR, lch); /* Wait for sDMA FIFO drain */ - l = dma_read(CCR(lch)); + l = p->dma_read(CCR, lch); while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE | OMAP_DMA_CCR_WR_ACTIVE))) { udelay(5); i++; - l = dma_read(CCR(lch)); + l = p->dma_read(CCR, lch); } if (i >= 100) - printk(KERN_ERR "DMA drain did not complete on " - "lch %d\n", lch); + pr_err("DMA drain did not complete on lch %d\n", lch); /* Restore OCP_SYSCONFIG */ - dma_write(sys_cf, OCP_SYSCONFIG); + p->dma_write(sys_cf, OCP_SYSCONFIG, lch); } else { l &= ~OMAP_DMA_CCR_EN; - dma_write(l, CCR(lch)); + p->dma_write(l, CCR, lch); } + /* + * Ensure that data transferred by DMA is visible to any access + * after DMA has been disabled. This is important for coherent + * DMA regions. + */ + mb(); + if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch = lch; - char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT]; + char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); do { @@ -1114,27 +1043,35 @@ EXPORT_SYMBOL(omap_set_dma_callback); * If the channel is running the caller must disable interrupts prior calling * this function and process the returned value before re-enabling interrupt to * prevent races with the interrupt handler. Note that in continuous mode there - * is a chance for CSSA_L register overflow inbetween the two reads resulting + * is a chance for CSSA_L register overflow between the two reads resulting * in incorrect return value. */ dma_addr_t omap_get_dma_src_pos(int lch) { dma_addr_t offset = 0; - if (cpu_is_omap15xx()) - offset = dma_read(CPC(lch)); + if (dma_omap15xx()) + offset = p->dma_read(CPC, lch); else - offset = dma_read(CSAC(lch)); + offset = p->dma_read(CSAC, lch); - /* - * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is - * read before the DMA controller finished disabling the channel. - */ - if (!cpu_is_omap15xx() && offset == 0) - offset = dma_read(CSAC(lch)); + if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0) + offset = p->dma_read(CSAC, lch); + + if (!dma_omap15xx()) { + /* + * CDAC == 0 indicates that the DMA transfer on the channel has + * not been started (no data has been transferred so far). + * Return the programmed source start address in this case. + */ + if (likely(p->dma_read(CDAC, lch))) + offset = p->dma_read(CSAC, lch); + else + offset = p->dma_read(CSSA, lch); + } - if (cpu_class_is_omap1()) - offset |= (dma_read(CSSA_U(lch)) << 16); + if (dma_omap1()) + offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000); return offset; } @@ -1145,27 +1082,35 @@ EXPORT_SYMBOL(omap_get_dma_src_pos); * If the channel is running the caller must disable interrupts prior calling * this function and process the returned value before re-enabling interrupt to * prevent races with the interrupt handler. Note that in continuous mode there - * is a chance for CDSA_L register overflow inbetween the two reads resulting + * is a chance for CDSA_L register overflow between the two reads resulting * in incorrect return value. */ dma_addr_t omap_get_dma_dst_pos(int lch) { dma_addr_t offset = 0; - if (cpu_is_omap15xx()) - offset = dma_read(CPC(lch)); + if (dma_omap15xx()) + offset = p->dma_read(CPC, lch); else - offset = dma_read(CDAC(lch)); + offset = p->dma_read(CDAC, lch); /* * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is * read before the DMA controller finished disabling the channel. */ - if (!cpu_is_omap15xx() && offset == 0) - offset = dma_read(CDAC(lch)); + if (!dma_omap15xx() && offset == 0) { + offset = p->dma_read(CDAC, lch); + /* + * CDAC == 0 indicates that the DMA transfer on the channel has + * not been started (no data has been transferred so far). + * Return the programmed destination start address in this case. + */ + if (unlikely(!offset)) + offset = p->dma_read(CDSA, lch); + } - if (cpu_class_is_omap1()) - offset |= (dma_read(CDSA_U(lch)) << 16); + if (dma_omap1()) + offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000); return offset; } @@ -1173,7 +1118,7 @@ EXPORT_SYMBOL(omap_get_dma_dst_pos); int omap_get_dma_active_status(int lch) { - return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0; + return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0; } EXPORT_SYMBOL(omap_get_dma_active_status); @@ -1181,12 +1126,12 @@ int omap_dma_running(void) { int lch; - if (cpu_class_is_omap1()) + if (dma_omap1()) if (omap_lcd_dma_running()) return 1; for (lch = 0; lch < dma_chan_count; lch++) - if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) + if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) return 1; return 0; @@ -1201,8 +1146,8 @@ void omap_dma_link_lch(int lch_head, int lch_queue) { if (omap_dma_in_1510_mode()) { if (lch_head == lch_queue) { - dma_write(dma_read(CCR(lch_head)) | (3 << 8), - CCR(lch_head)); + p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8), + CCR, lch_head); return; } printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); @@ -1212,8 +1157,7 @@ void omap_dma_link_lch(int lch_head, int lch_queue) if ((dma_chan[lch_head].dev_id == -1) || (dma_chan[lch_queue].dev_id == -1)) { - printk(KERN_ERR "omap_dma: trying to link " - "non requested channels\n"); + pr_err("omap_dma: trying to link non requested channels\n"); dump_stack(); } @@ -1228,8 +1172,8 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue) { if (omap_dma_in_1510_mode()) { if (lch_head == lch_queue) { - dma_write(dma_read(CCR(lch_head)) & ~(3 << 8), - CCR(lch_head)); + p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8), + CCR, lch_head); return; } printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); @@ -1239,15 +1183,13 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue) if (dma_chan[lch_head].next_lch != lch_queue || dma_chan[lch_head].next_lch == -1) { - printk(KERN_ERR "omap_dma: trying to unlink " - "non linked channels\n"); + pr_err("omap_dma: trying to unlink non linked channels\n"); dump_stack(); } if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) || (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) { - printk(KERN_ERR "omap_dma: You need to stop the DMA channels " - "before unlinking\n"); + pr_err("omap_dma: You need to stop the DMA channels before unlinking\n"); dump_stack(); } @@ -1255,8 +1197,6 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue) } EXPORT_SYMBOL(omap_dma_unlink_lch); -/*----------------------------------------------------------------------------*/ - #ifndef CONFIG_ARCH_OMAP1 /* Create chain of DMA channesls */ static void create_dma_lch_chain(int lch_head, int lch_queue) @@ -1281,15 +1221,15 @@ static void create_dma_lch_chain(int lch_head, int lch_queue) lch_queue; } - l = dma_read(CLNK_CTRL(lch_head)); + l = p->dma_read(CLNK_CTRL, lch_head); l &= ~(0x1f); l |= lch_queue; - dma_write(l, CLNK_CTRL(lch_head)); + p->dma_write(l, CLNK_CTRL, lch_head); - l = dma_read(CLNK_CTRL(lch_queue)); + l = p->dma_read(CLNK_CTRL, lch_queue); l &= ~(0x1f); l |= (dma_chan[lch_queue].next_linked_ch); - dma_write(l, CLNK_CTRL(lch_queue)); + p->dma_write(l, CLNK_CTRL, lch_queue); } /** @@ -1565,13 +1505,13 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, /* Set the params to the free channel */ if (src_start != 0) - dma_write(src_start, CSSA(lch)); + p->dma_write(src_start, CSSA, lch); if (dest_start != 0) - dma_write(dest_start, CDSA(lch)); + p->dma_write(dest_start, CDSA, lch); /* Write the buffer size */ - dma_write(elem_count, CEN(lch)); - dma_write(frame_count, CFN(lch)); + p->dma_write(elem_count, CEN, lch); + p->dma_write(frame_count, CFN, lch); /* * If the chain is dynamically linked, @@ -1604,8 +1544,8 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, enable_lnk(dma_chan[lch].prev_linked_ch); dma_chan[lch].state = DMA_CH_QUEUED; start_dma = 0; - if (0 == ((1 << 7) & dma_read( - CCR(dma_chan[lch].prev_linked_ch)))) { + if (0 == ((1 << 7) & p->dma_read( + CCR, dma_chan[lch].prev_linked_ch))) { disable_lnk(dma_chan[lch]. prev_linked_ch); pr_debug("\n prev ch is stopped\n"); @@ -1621,7 +1561,7 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, } omap_enable_channel_irq(lch); - l = dma_read(CCR(lch)); + l = p->dma_read(CCR, lch); if ((0 == (l & (1 << 24)))) l &= ~(1 << 25); @@ -1632,12 +1572,12 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, l |= (1 << 7); dma_chan[lch].state = DMA_CH_STARTED; pr_debug("starting %d\n", lch); - dma_write(l, CCR(lch)); + p->dma_write(l, CCR, lch); } else start_dma = 0; } else { if (0 == (l & (1 << 7))) - dma_write(l, CCR(lch)); + p->dma_write(l, CCR, lch); } dma_chan[lch].flags |= OMAP_DMA_ACTIVE; } @@ -1682,7 +1622,7 @@ int omap_start_dma_chain_transfers(int chain_id) omap_enable_channel_irq(channels[0]); } - l = dma_read(CCR(channels[0])); + l = p->dma_read(CCR, channels[0]); l |= (1 << 7); dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED; dma_chan[channels[0]].state = DMA_CH_STARTED; @@ -1691,7 +1631,7 @@ int omap_start_dma_chain_transfers(int chain_id) l &= ~(1 << 25); else l |= (1 << 25); - dma_write(l, CCR(channels[0])); + p->dma_write(l, CCR, channels[0]); dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE; @@ -1711,7 +1651,7 @@ int omap_stop_dma_chain_transfers(int chain_id) { int *channels; u32 l, i; - u32 sys_cf; + u32 sys_cf = 0; /* Check for input params */ if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { @@ -1726,22 +1666,20 @@ int omap_stop_dma_chain_transfers(int chain_id) } channels = dma_linked_lch[chain_id].linked_dmach_q; - /* - * DMA Errata: - * Special programming model needed to disable DMA before end of block - */ - sys_cf = dma_read(OCP_SYSCONFIG); - l = sys_cf; - /* Middle mode reg set no Standby */ - l &= ~((1 << 12)|(1 << 13)); - dma_write(l, OCP_SYSCONFIG); + if (IS_DMA_ERRATA(DMA_ERRATA_i88)) { + sys_cf = p->dma_read(OCP_SYSCONFIG, 0); + l = sys_cf; + /* Middle mode reg set no Standby */ + l &= ~((1 << 12)|(1 << 13)); + p->dma_write(l, OCP_SYSCONFIG, 0); + } for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { /* Stop the Channel transmission */ - l = dma_read(CCR(channels[i])); + l = p->dma_read(CCR, channels[i]); l &= ~(1 << 7); - dma_write(l, CCR(channels[i])); + p->dma_write(l, CCR, channels[i]); /* Disable the link in all the channels */ disable_lnk(channels[i]); @@ -1753,8 +1691,8 @@ int omap_stop_dma_chain_transfers(int chain_id) /* Reset the Queue pointers */ OMAP_DMA_CHAIN_QINIT(chain_id); - /* Errata - put in the old value */ - dma_write(sys_cf, OCP_SYSCONFIG); + if (IS_DMA_ERRATA(DMA_ERRATA_i88)) + p->dma_write(sys_cf, OCP_SYSCONFIG, 0); return 0; } @@ -1796,8 +1734,8 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi) /* Get the current channel */ lch = channels[dma_linked_lch[chain_id].q_head]; - *ei = dma_read(CCEN(lch)); - *fi = dma_read(CCFN(lch)); + *ei = p->dma_read(CCEN, lch); + *fi = p->dma_read(CCFN, lch); return 0; } @@ -1834,7 +1772,7 @@ int omap_get_dma_chain_dst_pos(int chain_id) /* Get the current channel */ lch = channels[dma_linked_lch[chain_id].q_head]; - return dma_read(CDAC(lch)); + return p->dma_read(CDAC, lch); } EXPORT_SYMBOL(omap_get_dma_chain_dst_pos); @@ -1868,7 +1806,7 @@ int omap_get_dma_chain_src_pos(int chain_id) /* Get the current channel */ lch = channels[dma_linked_lch[chain_id].q_head]; - return dma_read(CSAC(lch)); + return p->dma_read(CSAC, lch); } EXPORT_SYMBOL(omap_get_dma_chain_src_pos); #endif /* ifndef CONFIG_ARCH_OMAP1 */ @@ -1885,7 +1823,7 @@ static int omap1_dma_handle_ch(int ch) csr = dma_chan[ch].saved_csr; dma_chan[ch].saved_csr = 0; } else - csr = dma_read(CSR(ch)); + csr = p->dma_read(CSR, ch); if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { dma_chan[ch + 6].saved_csr = csr >> 7; csr &= 0x7f; @@ -1893,16 +1831,15 @@ static int omap1_dma_handle_ch(int ch) if ((csr & 0x3f) == 0) return 0; if (unlikely(dma_chan[ch].dev_id == -1)) { - printk(KERN_WARNING "Spurious interrupt from DMA channel " - "%d (CSR %04x)\n", ch, csr); + pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n", + ch, csr); return 0; } if (unlikely(csr & OMAP1_DMA_TOUT_IRQ)) - printk(KERN_WARNING "DMA timeout with device %d\n", - dma_chan[ch].dev_id); + pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id); if (unlikely(csr & OMAP_DMA_DROP_IRQ)) - printk(KERN_WARNING "DMA synchronization event drop occurred " - "with device %d\n", dma_chan[ch].dev_id); + pr_warn("DMA synchronization event drop occurred with device %d\n", + dma_chan[ch].dev_id); if (likely(csr & OMAP_DMA_BLOCK_IRQ)) dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; if (likely(dma_chan[ch].callback != NULL)) @@ -1938,39 +1875,32 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) static int omap2_dma_handle_ch(int ch) { - u32 status = dma_read(CSR(ch)); + u32 status = p->dma_read(CSR, ch); if (!status) { if (printk_ratelimit()) - printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", - ch); - dma_write(1 << ch, IRQSTATUS_L0); + pr_warn("Spurious DMA IRQ for lch %d\n", ch); + p->dma_write(1 << ch, IRQSTATUS_L0, ch); return 0; } if (unlikely(dma_chan[ch].dev_id == -1)) { if (printk_ratelimit()) - printk(KERN_WARNING "IRQ %04x for non-allocated DMA" - "channel %d\n", status, ch); + pr_warn("IRQ %04x for non-allocated DMA channel %d\n", + status, ch); return 0; } if (unlikely(status & OMAP_DMA_DROP_IRQ)) - printk(KERN_INFO - "DMA synchronization event drop occurred with device " - "%d\n", dma_chan[ch].dev_id); + pr_info("DMA synchronization event drop occurred with device %d\n", + dma_chan[ch].dev_id); if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { printk(KERN_INFO "DMA transaction error with device %d\n", dma_chan[ch].dev_id); - if (cpu_class_is_omap2()) { - /* - * Errata: sDMA Channel is not disabled - * after a transaction error. So we explicitely - * disable the channel - */ + if (IS_DMA_ERRATA(DMA_ERRATA_i378)) { u32 ccr; - ccr = dma_read(CCR(ch)); + ccr = p->dma_read(CCR, ch); ccr &= ~OMAP_DMA_CCR_EN; - dma_write(ccr, CCR(ch)); + p->dma_write(ccr, CCR, ch); dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; } } @@ -1981,14 +1911,16 @@ static int omap2_dma_handle_ch(int ch) printk(KERN_INFO "DMA misaligned error with device %d\n", dma_chan[ch].dev_id); - dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch)); - dma_write(1 << ch, IRQSTATUS_L0); + p->dma_write(status, CSR, ch); + p->dma_write(1 << ch, IRQSTATUS_L0, ch); + /* read back the register to flush the write */ + p->dma_read(IRQSTATUS_L0, ch); /* If the ch is not chained then chain_id will be -1 */ if (dma_chan[ch].chain_id != -1) { int chain_id = dma_chan[ch].chain_id; dma_chan[ch].state = DMA_CH_NOTSTARTED; - if (dma_read(CLNK_CTRL(ch)) & (1 << 15)) + if (p->dma_read(CLNK_CTRL, ch) & (1 << 15)) dma_chan[dma_chan[ch].next_linked_ch].state = DMA_CH_STARTED; if (dma_linked_lch[chain_id].chain_mode == @@ -1998,11 +1930,10 @@ static int omap2_dma_handle_ch(int ch) if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) OMAP_DMA_CHAIN_INCQHEAD(chain_id); - status = dma_read(CSR(ch)); + status = p->dma_read(CSR, ch); + p->dma_write(status, CSR, ch); } - dma_write(status, CSR(ch)); - if (likely(dma_chan[ch].callback != NULL)) dma_chan[ch].callback(ch, status, dma_chan[ch].data); @@ -2015,13 +1946,13 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) u32 val, enable_reg; int i; - val = dma_read(IRQSTATUS_L0); + val = p->dma_read(IRQSTATUS_L0, 0); if (val == 0) { if (printk_ratelimit()) printk(KERN_WARNING "Spurious DMA IRQ\n"); return IRQ_HANDLED; } - enable_reg = dma_read(IRQENABLE_L0); + enable_reg = p->dma_read(IRQENABLE_L0, 0); val &= enable_reg; /* Dispatch only relevant interrupts */ for (i = 0; i < dma_lch_count && val != 0; i++) { if (val & 1) @@ -2035,7 +1966,6 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) static struct irqaction omap24xx_dma_irq = { .name = "DMA", .handler = omap2_dma_irq_handler, - .flags = IRQF_DISABLED }; #else @@ -2044,125 +1974,95 @@ static struct irqaction omap24xx_dma_irq; /*----------------------------------------------------------------------------*/ +/* + * Note that we are currently using only IRQENABLE_L0 and L1. + * As the DSP may be using IRQENABLE_L2 and L3, let's not + * touch those for now. + */ void omap_dma_global_context_save(void) { omap_dma_global_context.dma_irqenable_l0 = - dma_read(IRQENABLE_L0); + p->dma_read(IRQENABLE_L0, 0); + omap_dma_global_context.dma_irqenable_l1 = + p->dma_read(IRQENABLE_L1, 0); omap_dma_global_context.dma_ocp_sysconfig = - dma_read(OCP_SYSCONFIG); - omap_dma_global_context.dma_gcr = dma_read(GCR); + p->dma_read(OCP_SYSCONFIG, 0); + omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0); } void omap_dma_global_context_restore(void) { int ch; - dma_write(omap_dma_global_context.dma_gcr, GCR); - dma_write(omap_dma_global_context.dma_ocp_sysconfig, - OCP_SYSCONFIG); - dma_write(omap_dma_global_context.dma_irqenable_l0, - IRQENABLE_L0); + p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0); + p->dma_write(omap_dma_global_context.dma_ocp_sysconfig, + OCP_SYSCONFIG, 0); + p->dma_write(omap_dma_global_context.dma_irqenable_l0, + IRQENABLE_L0, 0); + p->dma_write(omap_dma_global_context.dma_irqenable_l1, + IRQENABLE_L1, 0); - /* - * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared - * after secure sram context save and restore. Hence we need to - * manually clear those IRQs to avoid spurious interrupts. This - * affects only secure devices. - */ - if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) - dma_write(0x3 , IRQSTATUS_L0); + if (IS_DMA_ERRATA(DMA_ROMCODE_BUG)) + p->dma_write(0x3 , IRQSTATUS_L0, 0); for (ch = 0; ch < dma_chan_count; ch++) if (dma_chan[ch].dev_id != -1) omap_clear_dma(ch); } -/*----------------------------------------------------------------------------*/ +struct omap_system_dma_plat_info *omap_get_plat_info(void) +{ + return p; +} +EXPORT_SYMBOL_GPL(omap_get_plat_info); -static int __init omap_init_dma(void) +static int omap_system_dma_probe(struct platform_device *pdev) { - unsigned long base; - int ch, r; - - if (cpu_class_is_omap1()) { - base = OMAP1_DMA_BASE; - dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; - } else if (cpu_is_omap24xx()) { - base = OMAP24XX_DMA4_BASE; - dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; - } else if (cpu_is_omap34xx()) { - base = OMAP34XX_DMA4_BASE; - dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; - } else if (cpu_is_omap44xx()) { - base = OMAP44XX_DMA4_BASE; - dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; - } else { - pr_err("DMA init failed for unsupported omap\n"); - return -ENODEV; + int ch, ret = 0; + int dma_irq; + char irq_name[4]; + int irq_rel; + + p = pdev->dev.platform_data; + if (!p) { + dev_err(&pdev->dev, + "%s: System DMA initialized without platform data\n", + __func__); + return -EINVAL; } - omap_dma_base = ioremap(base, SZ_4K); - BUG_ON(!omap_dma_base); + d = p->dma_attr; + errata = p->errata; + + if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels + && (omap_dma_reserve_channels < d->lch_count)) + d->lch_count = omap_dma_reserve_channels; - if (cpu_class_is_omap2() && omap_dma_reserve_channels - && (omap_dma_reserve_channels <= dma_lch_count)) - dma_lch_count = omap_dma_reserve_channels; + dma_lch_count = d->lch_count; + dma_chan_count = dma_lch_count; + enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; - dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count, - GFP_KERNEL); + dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count, + sizeof(struct omap_dma_lch), GFP_KERNEL); if (!dma_chan) { - r = -ENOMEM; - goto out_unmap; + dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__); + return -ENOMEM; } - if (cpu_class_is_omap2()) { + + if (dma_omap2plus()) { dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * dma_lch_count, GFP_KERNEL); if (!dma_linked_lch) { - r = -ENOMEM; - goto out_free; + ret = -ENOMEM; + goto exit_dma_lch_fail; } } - if (cpu_is_omap15xx()) { - printk(KERN_INFO "DMA support for OMAP15xx initialized\n"); - dma_chan_count = 9; - enable_1510_mode = 1; - } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) { - printk(KERN_INFO "OMAP DMA hardware version %d\n", - dma_read(HW_ID)); - printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", - (dma_read(CAPS_0_U) << 16) | - dma_read(CAPS_0_L), - (dma_read(CAPS_1_U) << 16) | - dma_read(CAPS_1_L), - dma_read(CAPS_2), dma_read(CAPS_3), - dma_read(CAPS_4)); - if (!enable_1510_mode) { - u16 w; - - /* Disable OMAP 3.0/3.1 compatibility mode. */ - w = dma_read(GSCR); - w |= 1 << 3; - dma_write(w, GSCR); - dma_chan_count = 16; - } else - dma_chan_count = 9; - } else if (cpu_class_is_omap2()) { - u8 revision = dma_read(REVISION) & 0xff; - printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", - revision >> 4, revision & 0xf); - dma_chan_count = dma_lch_count; - } else { - dma_chan_count = 0; - return 0; - } - spin_lock_init(&dma_chan_lock); - for (ch = 0; ch < dma_chan_count; ch++) { omap_clear_dma(ch); - if (cpu_class_is_omap2()) + if (dma_omap2plus()) omap2_disable_irq_lch(ch); dma_chan[ch].dev_id = -1; @@ -2171,73 +2071,114 @@ static int __init omap_init_dma(void) if (ch >= 6 && enable_1510_mode) continue; - if (cpu_class_is_omap1()) { + if (dma_omap1()) { /* * request_irq() doesn't like dev_id (ie. ch) being * zero, so we have to kludge around this. */ - r = request_irq(omap1_dma_irq[ch], + sprintf(&irq_name[0], "%d", ch); + dma_irq = platform_get_irq_byname(pdev, irq_name); + + if (dma_irq < 0) { + ret = dma_irq; + goto exit_dma_irq_fail; + } + + /* INT_DMA_LCD is handled in lcd_dma.c */ + if (dma_irq == INT_DMA_LCD) + continue; + + ret = request_irq(dma_irq, omap1_dma_irq_handler, 0, "DMA", (void *) (ch + 1)); - if (r != 0) { - int i; - - printk(KERN_ERR "unable to request IRQ %d " - "for DMA (error %d)\n", - omap1_dma_irq[ch], r); - for (i = 0; i < ch; i++) - free_irq(omap1_dma_irq[i], - (void *) (i + 1)); - goto out_free; - } + if (ret != 0) + goto exit_dma_irq_fail; } } - if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) + if (d->dev_caps & IS_RW_PRIORITY) omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, DMA_DEFAULT_FIFO_DEPTH, 0); - if (cpu_class_is_omap2()) { - int irq; - if (cpu_is_omap44xx()) - irq = OMAP44XX_IRQ_SDMA_0; - else - irq = INT_24XX_SDMA_IRQ0; - setup_irq(irq, &omap24xx_dma_irq); - } - - if (cpu_is_omap34xx() || cpu_is_omap44xx()) { - /* Enable smartidle idlemodes and autoidle */ - u32 v = dma_read(OCP_SYSCONFIG); - v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK | - DMA_SYSCONFIG_SIDLEMODE_MASK | - DMA_SYSCONFIG_AUTOIDLE); - v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) | - DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) | - DMA_SYSCONFIG_AUTOIDLE); - dma_write(v , OCP_SYSCONFIG); - /* reserve dma channels 0 and 1 in high security devices */ - if (cpu_is_omap34xx() && - (omap_type() != OMAP2_DEVICE_TYPE_GP)) { - printk(KERN_INFO "Reserving DMA channels 0 and 1 for " - "HS ROM code\n"); - dma_chan[0].dev_id = 0; - dma_chan[1].dev_id = 1; + if (dma_omap2plus()) { + strcpy(irq_name, "0"); + dma_irq = platform_get_irq_byname(pdev, irq_name); + if (dma_irq < 0) { + dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq); + ret = dma_irq; + goto exit_dma_lch_fail; + } + ret = setup_irq(dma_irq, &omap24xx_dma_irq); + if (ret) { + dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n", + dma_irq, ret); + goto exit_dma_lch_fail; } } + /* reserve dma channels 0 and 1 in high security devices on 34xx */ + if (d->dev_caps & HS_CHANNELS_RESERVED) { + pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n"); + dma_chan[0].dev_id = 0; + dma_chan[1].dev_id = 1; + } + p->show_dma_caps(); return 0; -out_free: - kfree(dma_chan); +exit_dma_irq_fail: + dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n", + dma_irq, ret); + for (irq_rel = 0; irq_rel < ch; irq_rel++) { + dma_irq = platform_get_irq(pdev, irq_rel); + free_irq(dma_irq, (void *)(irq_rel + 1)); + } -out_unmap: - iounmap(omap_dma_base); +exit_dma_lch_fail: + return ret; +} + +static int omap_system_dma_remove(struct platform_device *pdev) +{ + int dma_irq; - return r; + if (dma_omap2plus()) { + char irq_name[4]; + strcpy(irq_name, "0"); + dma_irq = platform_get_irq_byname(pdev, irq_name); + remove_irq(dma_irq, &omap24xx_dma_irq); + } else { + int irq_rel = 0; + for ( ; irq_rel < dma_chan_count; irq_rel++) { + dma_irq = platform_get_irq(pdev, irq_rel); + free_irq(dma_irq, (void *)(irq_rel + 1)); + } + } + return 0; +} + +static struct platform_driver omap_system_dma_driver = { + .probe = omap_system_dma_probe, + .remove = omap_system_dma_remove, + .driver = { + .name = "omap_dma_system" + }, +}; + +static int __init omap_system_dma_init(void) +{ + return platform_driver_register(&omap_system_dma_driver); +} +arch_initcall(omap_system_dma_init); + +static void __exit omap_system_dma_exit(void) +{ + platform_driver_unregister(&omap_system_dma_driver); } -arch_initcall(omap_init_dma); +MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRIVER_NAME); +MODULE_AUTHOR("Texas Instruments Inc"); /* * Reserve the omap SDMA channels using cmdline bootarg |