diff options
Diffstat (limited to 'arch/arm/mach-vexpress/platsmp.c')
| -rw-r--r-- | arch/arm/mach-vexpress/platsmp.c | 180 |
1 files changed, 64 insertions, 116 deletions
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c index 634bf1d3a31..a1f3804fd5a 100644 --- a/arch/arm/mach-vexpress/platsmp.c +++ b/arch/arm/mach-vexpress/platsmp.c @@ -10,151 +10,90 @@ */ #include <linux/init.h> #include <linux/errno.h> -#include <linux/delay.h> -#include <linux/device.h> -#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> +#include <linux/of_address.h> +#include <linux/vexpress.h> -#include <asm/cacheflush.h> +#include <asm/mcpm.h> #include <asm/smp_scu.h> -#include <asm/unified.h> +#include <asm/mach/map.h> -#include <mach/ct-ca9x4.h> #include <mach/motherboard.h> -#define V2M_PA_CS7 0x10000000 -#include "core.h" - -extern void vexpress_secondary_startup(void); +#include <plat/platsmp.h> -/* - * control for which core is the next to come out of the secondary - * boot "holding pen" - */ -volatile int __cpuinitdata pen_release = -1; +#include "core.h" /* - * Write pen_release in a way that is guaranteed to be visible to all - * observers, irrespective of whether they're taking part in coherency - * or not. This is necessary for the hotplug code to work reliably. + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. */ -static void __cpuinit write_pen_release(int val) -{ - pen_release = val; - smp_wmb(); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); -} - -static void __iomem *scu_base_addr(void) +static void __init vexpress_smp_init_cpus(void) { - return MMIO_P2V(A9_MPCORE_SCU); + ct_desc->init_cpu_map(); } -static DEFINE_SPINLOCK(boot_lock); - -void __cpuinit platform_secondary_init(unsigned int cpu) +static void __init vexpress_smp_prepare_cpus(unsigned int max_cpus) { /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); - - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point + * Initialise the present map, which describes the set of CPUs + * actually populated at the present time. */ - write_pen_release(-1); + ct_desc->smp_enable(max_cpus); /* - * Synchronise with the boot thread. + * Write the address of secondary startup into the + * system-wide flags register. The boot monitor waits + * until it receives a soft interrupt, and then the + * secondary CPU branches to this address. */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); + vexpress_flags_set(virt_to_phys(versatile_secondary_startup)); } -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +struct smp_operations __initdata vexpress_smp_ops = { + .smp_init_cpus = vexpress_smp_init_cpus, + .smp_prepare_cpus = vexpress_smp_prepare_cpus, + .smp_secondary_init = versatile_secondary_init, + .smp_boot_secondary = versatile_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = vexpress_cpu_die, +#endif +}; + +bool __init vexpress_smp_init_ops(void) { - unsigned long timeout; - - /* - * Set synchronisation state between this boot processor - * and the secondary one - */ - spin_lock(&boot_lock); - +#ifdef CONFIG_MCPM /* - * This is really belt and braces; we hold unintended secondary - * CPUs in the holding pen until we're ready for them. However, - * since we haven't sent them a soft interrupt, they shouldn't - * be there. + * The best way to detect a multi-cluster configuration at the moment + * is to look for the presence of a CCI in the system. + * Override the default vexpress_smp_ops if so. */ - write_pen_release(cpu); - - /* - * Send the secondary CPU a soft interrupt, thereby causing - * the boot monitor to read the system wide flags register, - * and branch to the address found there. - */ - smp_cross_call(cpumask_of(cpu), 1); - - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - smp_rmb(); - if (pen_release == -1) - break; - - udelay(10); + struct device_node *node; + node = of_find_compatible_node(NULL, NULL, "arm,cci-400"); + if (node && of_device_is_available(node)) { + mcpm_smp_set_ops(); + return true; } - - /* - * now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - spin_unlock(&boot_lock); - - return pen_release != -1 ? -ENOSYS : 0; +#endif + return false; } -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ -void __init smp_init_cpus(void) -{ - void __iomem *scu_base = scu_base_addr(); - unsigned int i, ncores; - - ncores = scu_base ? scu_get_core_count(scu_base) : 1; - - /* sanity check */ - if (ncores > NR_CPUS) { - printk(KERN_WARNING - "vexpress: no. of cores (%d) greater than configured " - "maximum of %d - clipping\n", - ncores, NR_CPUS); - ncores = NR_CPUS; - } +#if defined(CONFIG_OF) - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); -} +static const struct of_device_id vexpress_smp_dt_scu_match[] __initconst = { + { .compatible = "arm,cortex-a5-scu", }, + { .compatible = "arm,cortex-a9-scu", }, + {} +}; -void __init platform_smp_prepare_cpus(unsigned int max_cpus) +static void __init vexpress_smp_dt_prepare_cpus(unsigned int max_cpus) { - int i; + struct device_node *scu = of_find_matching_node(NULL, + vexpress_smp_dt_scu_match); - /* - * Initialise the present map, which describes the set of CPUs - * actually populated at the present time. - */ - for (i = 0; i < max_cpus; i++) - set_cpu_present(i, true); - - scu_enable(scu_base_addr()); + if (scu) + scu_enable(of_iomap(scu, 0)); /* * Write the address of secondary startup into the @@ -162,7 +101,16 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) * until it receives a soft interrupt, and then the * secondary CPU branches to this address. */ - writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR)); - writel(BSYM(virt_to_phys(vexpress_secondary_startup)), - MMIO_P2V(V2M_SYS_FLAGSSET)); + vexpress_flags_set(virt_to_phys(versatile_secondary_startup)); } + +struct smp_operations __initdata vexpress_smp_dt_ops = { + .smp_prepare_cpus = vexpress_smp_dt_prepare_cpus, + .smp_secondary_init = versatile_secondary_init, + .smp_boot_secondary = versatile_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = vexpress_cpu_die, +#endif +}; + +#endif |