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Diffstat (limited to 'arch/arm/mach-shmobile/pm-sh7372.c')
-rw-r--r--arch/arm/mach-shmobile/pm-sh7372.c594
1 files changed, 433 insertions, 161 deletions
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index 933fb411be0..0de75fd394b 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -15,247 +15,508 @@
#include <linux/list.h>
#include <linux/err.h>
#include <linux/slab.h>
-#include <linux/pm_runtime.h>
+#include <linux/pm_clock.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
-#include <asm/system.h>
+#include <linux/irq.h>
+#include <linux/bitrev.h>
+#include <linux/console.h>
+#include <asm/cpuidle.h>
#include <asm/io.h>
#include <asm/tlbflush.h>
+#include <asm/suspend.h>
#include <mach/common.h>
#include <mach/sh7372.h>
-
+#include <mach/pm-rmobile.h>
+
+/* DBG */
+#define DBGREG1 IOMEM(0xe6100020)
+#define DBGREG9 IOMEM(0xe6100040)
+
+/* CPGA */
+#define SYSTBCR IOMEM(0xe6150024)
+#define MSTPSR0 IOMEM(0xe6150030)
+#define MSTPSR1 IOMEM(0xe6150038)
+#define MSTPSR2 IOMEM(0xe6150040)
+#define MSTPSR3 IOMEM(0xe6150048)
+#define MSTPSR4 IOMEM(0xe615004c)
+#define PLLC01STPCR IOMEM(0xe61500c8)
+
+/* SYSC */
+#define SBAR IOMEM(0xe6180020)
+#define WUPRMSK IOMEM(0xe6180028)
+#define WUPSMSK IOMEM(0xe618002c)
+#define WUPSMSK2 IOMEM(0xe6180048)
+#define WUPSFAC IOMEM(0xe6180098)
+#define IRQCR IOMEM(0xe618022c)
+#define IRQCR2 IOMEM(0xe6180238)
+#define IRQCR3 IOMEM(0xe6180244)
+#define IRQCR4 IOMEM(0xe6180248)
+#define PDNSEL IOMEM(0xe6180254)
+
+/* INTC */
+#define ICR1A IOMEM(0xe6900000)
+#define ICR2A IOMEM(0xe6900004)
+#define ICR3A IOMEM(0xe6900008)
+#define ICR4A IOMEM(0xe690000c)
+#define INTMSK00A IOMEM(0xe6900040)
+#define INTMSK10A IOMEM(0xe6900044)
+#define INTMSK20A IOMEM(0xe6900048)
+#define INTMSK30A IOMEM(0xe690004c)
+
+/* MFIS */
+/* FIXME: pointing where? */
#define SMFRAM 0xe6a70000
-#define SYSTBCR 0xe6150024
-#define SBAR 0xe6180020
-#define APARMBAREA 0xe6f10020
-
-#define SPDCR 0xe6180008
-#define SWUCR 0xe6180014
-#define PSTR 0xe6180080
-#define PSTR_RETRIES 100
-#define PSTR_DELAY_US 10
+/* AP-System Core */
+#define APARMBAREA IOMEM(0xe6f10020)
#ifdef CONFIG_PM
-static int pd_power_down(struct generic_pm_domain *genpd)
-{
- struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
- unsigned int mask = 1 << sh7372_pd->bit_shift;
+#define PM_DOMAIN_ON_OFF_LATENCY_NS 250000
- if (__raw_readl(PSTR) & mask) {
- unsigned int retry_count;
+static int sh7372_a4r_pd_suspend(void)
+{
+ sh7372_intcs_suspend();
+ __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
+ return 0;
+}
- __raw_writel(mask, SPDCR);
+static bool a4s_suspend_ready;
- for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
- if (!(__raw_readl(SPDCR) & mask))
- break;
- cpu_relax();
- }
- }
+static int sh7372_a4s_pd_suspend(void)
+{
+ /*
+ * The A4S domain contains the CPU core and therefore it should
+ * only be turned off if the CPU is not in use. This may happen
+ * during system suspend, when SYSC is going to be used for generating
+ * resume signals and a4s_suspend_ready is set to let
+ * sh7372_enter_suspend() know that it can turn A4S off.
+ */
+ a4s_suspend_ready = true;
+ return -EBUSY;
+}
- pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
- mask, __raw_readl(PSTR));
+static void sh7372_a4s_pd_resume(void)
+{
+ a4s_suspend_ready = false;
+}
- return 0;
+static int sh7372_a3sp_pd_suspend(void)
+{
+ /*
+ * Serial consoles make use of SCIF hardware located in A3SP,
+ * keep such power domain on if "no_console_suspend" is set.
+ */
+ return console_suspend_enabled ? 0 : -EBUSY;
}
-static int pd_power_up(struct generic_pm_domain *genpd)
+static struct rmobile_pm_domain sh7372_pm_domains[] = {
+ {
+ .genpd.name = "A4LC",
+ .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .bit_shift = 1,
+ },
+ {
+ .genpd.name = "A4MP",
+ .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .bit_shift = 2,
+ },
+ {
+ .genpd.name = "D4",
+ .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .bit_shift = 3,
+ },
+ {
+ .genpd.name = "A4R",
+ .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .bit_shift = 5,
+ .suspend = sh7372_a4r_pd_suspend,
+ .resume = sh7372_intcs_resume,
+ },
+ {
+ .genpd.name = "A3RV",
+ .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .bit_shift = 6,
+ },
+ {
+ .genpd.name = "A3RI",
+ .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .bit_shift = 8,
+ },
+ {
+ .genpd.name = "A4S",
+ .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .bit_shift = 10,
+ .gov = &pm_domain_always_on_gov,
+ .no_debug = true,
+ .suspend = sh7372_a4s_pd_suspend,
+ .resume = sh7372_a4s_pd_resume,
+ },
+ {
+ .genpd.name = "A3SP",
+ .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .bit_shift = 11,
+ .gov = &pm_domain_always_on_gov,
+ .no_debug = true,
+ .suspend = sh7372_a3sp_pd_suspend,
+ },
+ {
+ .genpd.name = "A3SG",
+ .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+ .bit_shift = 13,
+ },
+};
+
+void __init sh7372_init_pm_domains(void)
{
- struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
- unsigned int mask = 1 << sh7372_pd->bit_shift;
- unsigned int retry_count;
- int ret = 0;
-
- if (__raw_readl(PSTR) & mask)
- goto out;
-
- __raw_writel(mask, SWUCR);
-
- for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
- if (!(__raw_readl(SWUCR) & mask))
- goto out;
- if (retry_count > PSTR_RETRIES)
- udelay(PSTR_DELAY_US);
- else
- cpu_relax();
- }
- if (__raw_readl(SWUCR) & mask)
- ret = -EIO;
+ rmobile_init_domains(sh7372_pm_domains, ARRAY_SIZE(sh7372_pm_domains));
+ pm_genpd_add_subdomain_names("A4LC", "A3RV");
+ pm_genpd_add_subdomain_names("A4R", "A4LC");
+ pm_genpd_add_subdomain_names("A4S", "A3SG");
+ pm_genpd_add_subdomain_names("A4S", "A3SP");
+}
- out:
- pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
- mask, __raw_readl(PSTR));
+#endif /* CONFIG_PM */
- return ret;
+#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
+static void sh7372_set_reset_vector(unsigned long address)
+{
+ /* set reset vector, translate 4k */
+ __raw_writel(address, SBAR);
+ __raw_writel(0, APARMBAREA);
}
-static int pd_power_up_a3rv(struct generic_pm_domain *genpd)
+static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode)
{
- int ret = pd_power_up(genpd);
+ if (pllc0_on)
+ __raw_writel(0, PLLC01STPCR);
+ else
+ __raw_writel(1 << 28, PLLC01STPCR);
- /* force A4LC on after A3RV has been requested on */
- pm_genpd_poweron(&sh7372_a4lc.genpd);
+ __raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */
+ cpu_suspend(sleep_mode, sh7372_do_idle_sysc);
+ __raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */
- return ret;
+ /* disable reset vector translation */
+ __raw_writel(0, SBAR);
}
-static int pd_power_down_a3rv(struct generic_pm_domain *genpd)
+static int sh7372_sysc_valid(unsigned long *mskp, unsigned long *msk2p)
{
- int ret = pd_power_down(genpd);
+ unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4;
+ unsigned long msk, msk2;
- /* try to power down A4LC after A3RV is requested off */
- genpd_queue_power_off_work(&sh7372_a4lc.genpd);
+ /* check active clocks to determine potential wakeup sources */
- return ret;
+ mstpsr0 = __raw_readl(MSTPSR0);
+ if ((mstpsr0 & 0x00000003) != 0x00000003) {
+ pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0);
+ return 0;
+ }
+
+ mstpsr1 = __raw_readl(MSTPSR1);
+ if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) {
+ pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1);
+ return 0;
+ }
+
+ mstpsr2 = __raw_readl(MSTPSR2);
+ if ((mstpsr2 & 0x000741ff) != 0x000741ff) {
+ pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2);
+ return 0;
+ }
+
+ mstpsr3 = __raw_readl(MSTPSR3);
+ if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) {
+ pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3);
+ return 0;
+ }
+
+ mstpsr4 = __raw_readl(MSTPSR4);
+ if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) {
+ pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4);
+ return 0;
+ }
+
+ msk = 0;
+ msk2 = 0;
+
+ /* make bitmaps of limited number of wakeup sources */
+
+ if ((mstpsr2 & (1 << 23)) == 0) /* SPU2 */
+ msk |= 1 << 31;
+
+ if ((mstpsr2 & (1 << 12)) == 0) /* MFI_MFIM */
+ msk |= 1 << 21;
+
+ if ((mstpsr4 & (1 << 3)) == 0) /* KEYSC */
+ msk |= 1 << 2;
+
+ if ((mstpsr1 & (1 << 24)) == 0) /* CMT0 */
+ msk |= 1 << 1;
+
+ if ((mstpsr3 & (1 << 29)) == 0) /* CMT1 */
+ msk |= 1 << 1;
+
+ if ((mstpsr4 & (1 << 0)) == 0) /* CMT2 */
+ msk |= 1 << 1;
+
+ if ((mstpsr2 & (1 << 13)) == 0) /* MFI_MFIS */
+ msk2 |= 1 << 17;
+
+ *mskp = msk;
+ *msk2p = msk2;
+
+ return 1;
}
-static int pd_power_down_a4lc(struct generic_pm_domain *genpd)
+static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p)
{
- /* only power down A4LC if A3RV is off */
- if (!(__raw_readl(PSTR) & (1 << sh7372_a3rv.bit_shift)))
- return pd_power_down(genpd);
+ u16 tmp, irqcr1, irqcr2;
+ int k;
- return -EBUSY;
+ irqcr1 = 0;
+ irqcr2 = 0;
+
+ /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
+ for (k = 0; k <= 7; k++) {
+ tmp = (icr >> ((7 - k) * 4)) & 0xf;
+ irqcr1 |= (tmp & 0x03) << (k * 2);
+ irqcr2 |= (tmp >> 2) << (k * 2);
+ }
+
+ *irqcr1p = irqcr1;
+ *irqcr2p = irqcr2;
}
-static bool pd_active_wakeup(struct device *dev)
+static void sh7372_setup_sysc(unsigned long msk, unsigned long msk2)
{
- return true;
+ u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high;
+ unsigned long tmp;
+
+ /* read IRQ0A -> IRQ15A mask */
+ tmp = bitrev8(__raw_readb(INTMSK00A));
+ tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8;
+
+ /* setup WUPSMSK from clocks and external IRQ mask */
+ msk = (~msk & 0xc030000f) | (tmp << 4);
+ __raw_writel(msk, WUPSMSK);
+
+ /* propage level/edge trigger for external IRQ 0->15 */
+ sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low);
+ sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high);
+ __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR);
+ __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2);
+
+ /* read IRQ16A -> IRQ31A mask */
+ tmp = bitrev8(__raw_readb(INTMSK20A));
+ tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8;
+
+ /* setup WUPSMSK2 from clocks and external IRQ mask */
+ msk2 = (~msk2 & 0x00030000) | tmp;
+ __raw_writel(msk2, WUPSMSK2);
+
+ /* propage level/edge trigger for external IRQ 16->31 */
+ sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low);
+ sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high);
+ __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3);
+ __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4);
}
-void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
+static void sh7372_enter_a3sm_common(int pllc0_on)
{
- struct generic_pm_domain *genpd = &sh7372_pd->genpd;
-
- pm_genpd_init(genpd, NULL, false);
- genpd->stop_device = pm_clk_suspend;
- genpd->start_device = pm_clk_resume;
- genpd->active_wakeup = pd_active_wakeup;
-
- if (sh7372_pd == &sh7372_a4lc) {
- genpd->power_off = pd_power_down_a4lc;
- genpd->power_on = pd_power_up;
- } else if (sh7372_pd == &sh7372_a3rv) {
- genpd->power_off = pd_power_down_a3rv;
- genpd->power_on = pd_power_up_a3rv;
- } else {
- genpd->power_off = pd_power_down;
- genpd->power_on = pd_power_up;
- }
- genpd->power_on(&sh7372_pd->genpd);
+ /* use INTCA together with SYSC for wakeup */
+ sh7372_setup_sysc(1 << 0, 0);
+ sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
+ sh7372_enter_sysc(pllc0_on, 1 << 12);
}
-void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
- struct platform_device *pdev)
+static void sh7372_enter_a4s_common(int pllc0_on)
{
- struct device *dev = &pdev->dev;
-
- if (!dev->power.subsys_data) {
- pm_clk_init(dev);
- pm_clk_add(dev, NULL);
- }
- pm_genpd_add_device(&sh7372_pd->genpd, dev);
+ sh7372_intca_suspend();
+ sh7372_set_reset_vector(SMFRAM);
+ sh7372_enter_sysc(pllc0_on, 1 << 10);
+ sh7372_intca_resume();
}
-struct sh7372_pm_domain sh7372_a4lc = {
- .bit_shift = 1,
-};
+static void sh7372_pm_setup_smfram(void)
+{
+ /* pass physical address of cpu_resume() to assembly resume code */
+ sh7372_cpu_resume = virt_to_phys(cpu_resume);
-struct sh7372_pm_domain sh7372_a4mp = {
- .bit_shift = 2,
-};
+ memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
+}
+#else
+static inline void sh7372_pm_setup_smfram(void) {}
+#endif /* CONFIG_SUSPEND || CONFIG_CPU_IDLE */
-struct sh7372_pm_domain sh7372_d4 = {
- .bit_shift = 3,
-};
+#ifdef CONFIG_CPU_IDLE
+static int sh7372_do_idle_core_standby(unsigned long unused)
+{
+ cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
+ return 0;
+}
-struct sh7372_pm_domain sh7372_a3rv = {
- .bit_shift = 6,
-};
+static int sh7372_enter_core_standby(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
+{
+ sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
-struct sh7372_pm_domain sh7372_a3ri = {
- .bit_shift = 8,
-};
+ /* enter sleep mode with SYSTBCR to 0x10 */
+ __raw_writel(0x10, SYSTBCR);
+ cpu_suspend(0, sh7372_do_idle_core_standby);
+ __raw_writel(0, SYSTBCR);
-struct sh7372_pm_domain sh7372_a3sg = {
- .bit_shift = 13,
-};
+ /* disable reset vector translation */
+ __raw_writel(0, SBAR);
-#endif /* CONFIG_PM */
+ return 1;
+}
-static void sh7372_enter_core_standby(void)
+static int sh7372_enter_a3sm_pll_on(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
{
- void __iomem *smfram = (void __iomem *)SMFRAM;
-
- __raw_writel(0, APARMBAREA); /* translate 4k */
- __raw_writel(__pa(sh7372_cpu_resume), SBAR); /* set reset vector */
- __raw_writel(0x10, SYSTBCR); /* enable core standby */
-
- __raw_writel(0, smfram + 0x3c); /* clear page table address */
+ sh7372_enter_a3sm_common(1);
+ return 2;
+}
- sh7372_cpu_suspend();
- cpu_init();
+static int sh7372_enter_a3sm_pll_off(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
+{
+ sh7372_enter_a3sm_common(0);
+ return 3;
+}
- /* if page table address is non-NULL then we have been powered down */
- if (__raw_readl(smfram + 0x3c)) {
- __raw_writel(__raw_readl(smfram + 0x40),
- __va(__raw_readl(smfram + 0x3c)));
+static int sh7372_enter_a4s(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
+{
+ unsigned long msk, msk2;
- flush_tlb_all();
- set_cr(__raw_readl(smfram + 0x38));
- }
+ if (!sh7372_sysc_valid(&msk, &msk2))
+ return sh7372_enter_a3sm_pll_off(dev, drv, index);
- __raw_writel(0, SYSTBCR); /* disable core standby */
- __raw_writel(0, SBAR); /* disable reset vector translation */
+ sh7372_setup_sysc(msk, msk2);
+ sh7372_enter_a4s_common(0);
+ return 4;
}
-#ifdef CONFIG_CPU_IDLE
-static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
-{
- struct cpuidle_state *state;
- int i = dev->state_count;
-
- state = &dev->states[i];
- snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
- strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
- state->exit_latency = 10;
- state->target_residency = 20 + 10;
- state->power_usage = 1; /* perhaps not */
- state->flags = 0;
- state->flags |= CPUIDLE_FLAG_TIME_VALID;
- shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
-
- dev->state_count = i + 1;
-}
+static struct cpuidle_driver sh7372_cpuidle_driver = {
+ .name = "sh7372_cpuidle",
+ .owner = THIS_MODULE,
+ .state_count = 5,
+ .safe_state_index = 0, /* C1 */
+ .states[0] = ARM_CPUIDLE_WFI_STATE,
+ .states[1] = {
+ .name = "C2",
+ .desc = "Core Standby Mode",
+ .exit_latency = 10,
+ .target_residency = 20 + 10,
+ .flags = CPUIDLE_FLAG_TIME_VALID,
+ .enter = sh7372_enter_core_standby,
+ },
+ .states[2] = {
+ .name = "C3",
+ .desc = "A3SM PLL ON",
+ .exit_latency = 20,
+ .target_residency = 30 + 20,
+ .flags = CPUIDLE_FLAG_TIME_VALID,
+ .enter = sh7372_enter_a3sm_pll_on,
+ },
+ .states[3] = {
+ .name = "C4",
+ .desc = "A3SM PLL OFF",
+ .exit_latency = 120,
+ .target_residency = 30 + 120,
+ .flags = CPUIDLE_FLAG_TIME_VALID,
+ .enter = sh7372_enter_a3sm_pll_off,
+ },
+ .states[4] = {
+ .name = "C5",
+ .desc = "A4S PLL OFF",
+ .exit_latency = 240,
+ .target_residency = 30 + 240,
+ .flags = CPUIDLE_FLAG_TIME_VALID,
+ .enter = sh7372_enter_a4s,
+ .disabled = true,
+ },
+};
-static void sh7372_cpuidle_init(void)
+static void __init sh7372_cpuidle_init(void)
{
- shmobile_cpuidle_setup = sh7372_cpuidle_setup;
+ shmobile_cpuidle_set_driver(&sh7372_cpuidle_driver);
}
#else
-static void sh7372_cpuidle_init(void) {}
+static void __init sh7372_cpuidle_init(void) {}
#endif
#ifdef CONFIG_SUSPEND
static int sh7372_enter_suspend(suspend_state_t suspend_state)
{
- sh7372_enter_core_standby();
+ unsigned long msk, msk2;
+
+ /* check active clocks to determine potential wakeup sources */
+ if (sh7372_sysc_valid(&msk, &msk2) && a4s_suspend_ready) {
+ /* convert INTC mask/sense to SYSC mask/sense */
+ sh7372_setup_sysc(msk, msk2);
+
+ /* enter A4S sleep with PLLC0 off */
+ pr_debug("entering A4S\n");
+ sh7372_enter_a4s_common(0);
+ return 0;
+ }
+
+ /* default to enter A3SM sleep with PLLC0 off */
+ pr_debug("entering A3SM\n");
+ sh7372_enter_a3sm_common(0);
return 0;
}
+/**
+ * sh7372_pm_notifier_fn - SH7372 PM notifier routine.
+ * @notifier: Unused.
+ * @pm_event: Event being handled.
+ * @unused: Unused.
+ */
+static int sh7372_pm_notifier_fn(struct notifier_block *notifier,
+ unsigned long pm_event, void *unused)
+{
+ switch (pm_event) {
+ case PM_SUSPEND_PREPARE:
+ /*
+ * This is necessary, because the A4R domain has to be "on"
+ * when suspend_device_irqs() and resume_device_irqs() are
+ * executed during system suspend and resume, respectively, so
+ * that those functions don't crash while accessing the INTCS.
+ */
+ pm_genpd_name_poweron("A4R");
+ break;
+ case PM_POST_SUSPEND:
+ pm_genpd_poweroff_unused();
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
static void sh7372_suspend_init(void)
{
shmobile_suspend_ops.enter = sh7372_enter_suspend;
+ pm_notifier(sh7372_pm_notifier_fn, 0);
}
#else
static void sh7372_suspend_init(void) {}
#endif
-#define DBGREG1 0xe6100020
-#define DBGREG9 0xe6100040
-
void __init sh7372_pm_init(void)
{
/* enable DBG hardware block to kick SYSC */
@@ -263,6 +524,17 @@ void __init sh7372_pm_init(void)
__raw_writel(0x0000a501, DBGREG9);
__raw_writel(0x00000000, DBGREG1);
+ /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
+ __raw_writel(0, PDNSEL);
+
+ sh7372_pm_setup_smfram();
+
sh7372_suspend_init();
sh7372_cpuidle_init();
}
+
+void __init sh7372_pm_init_late(void)
+{
+ shmobile_init_late();
+ pm_genpd_name_attach_cpuidle("A4S", 4);
+}
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-12-21 07:37:39 +0000