diff options
Diffstat (limited to 'arch/arm/mach-shmobile/include')
28 files changed, 1808 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/include/mach/clkdev.h b/arch/arm/mach-shmobile/include/mach/clkdev.h new file mode 100644 index 00000000000..36d0163a857 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +int __clk_get(struct clk *clk); +void __clk_put(struct clk *clk); + +#endif /* __ASM_MACH_CLKDEV_H */ diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h new file mode 100644 index 00000000000..31b6417463e --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/clock.h @@ -0,0 +1,56 @@ +#ifndef CLOCK_H +#define CLOCK_H + +#ifdef CONFIG_COMMON_CLK +/* temporary clock configuration helper for platform devices */ + +struct clk_name { + const char *clk; + const char *con_id; + const char *dev_id; +}; + +void shmobile_clk_workaround(const struct clk_name *clks, int nr_clks, + bool enable); + +#else /* CONFIG_COMMON_CLK */ +/* legacy clock implementation */ + +struct clk; +unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk); +extern struct sh_clk_ops shmobile_fixed_ratio_clk_ops; + +/* clock ratio */ +struct clk_ratio { + int mul; + int div; +}; + +#define SH_CLK_RATIO(name, m, d) \ +static struct clk_ratio name ##_ratio = { \ + .mul = m, \ + .div = d, \ +} + +#define SH_FIXED_RATIO_CLKg(name, p, r) \ +struct clk name = { \ + .parent = &p, \ + .ops = &shmobile_fixed_ratio_clk_ops,\ + .priv = &r ## _ratio, \ +} + +#define SH_FIXED_RATIO_CLK(name, p, r) \ +static SH_FIXED_RATIO_CLKg(name, p, r) + +#define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \ + SH_CLK_RATIO(name, m, d); \ + SH_FIXED_RATIO_CLK(name, p, name) + +#define SH_CLK_SET_RATIO(p, m, d) \ +do { \ + (p)->mul = m; \ + (p)->div = d; \ +} while (0) + +#endif /* CONFIG_COMMON_CLK */ +#endif diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h new file mode 100644 index 00000000000..f7a360edcc3 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -0,0 +1,56 @@ +#ifndef __ARCH_MACH_COMMON_H +#define __ARCH_MACH_COMMON_H + +extern void shmobile_earlytimer_init(void); +extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz, + unsigned int mult, unsigned int div); +extern void shmobile_init_delay(void); +struct twd_local_timer; +extern void shmobile_setup_console(void); +extern void shmobile_boot_vector(void); +extern unsigned long shmobile_boot_fn; +extern unsigned long shmobile_boot_arg; +extern unsigned long shmobile_boot_size; +extern void shmobile_smp_boot(void); +extern void shmobile_smp_sleep(void); +extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn, + unsigned long arg); +extern int shmobile_smp_cpu_disable(unsigned int cpu); +extern void shmobile_invalidate_start(void); +extern void shmobile_boot_scu(void); +extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus); +extern void shmobile_smp_scu_cpu_die(unsigned int cpu); +extern int shmobile_smp_scu_cpu_kill(unsigned int cpu); +extern void shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus); +extern int shmobile_smp_apmu_boot_secondary(unsigned int cpu, + struct task_struct *idle); +extern void shmobile_smp_apmu_cpu_die(unsigned int cpu); +extern int shmobile_smp_apmu_cpu_kill(unsigned int cpu); +struct clk; +extern int shmobile_clk_init(void); +extern void shmobile_handle_irq_intc(struct pt_regs *); +extern struct platform_suspend_ops shmobile_suspend_ops; +struct cpuidle_driver; +extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); + +#ifdef CONFIG_SUSPEND +int shmobile_suspend_init(void); +#else +static inline int shmobile_suspend_init(void) { return 0; } +#endif + +#ifdef CONFIG_CPU_IDLE +int shmobile_cpuidle_init(void); +#else +static inline int shmobile_cpuidle_init(void) { return 0; } +#endif + +extern void __iomem *shmobile_scu_base; + +static inline void __init shmobile_init_late(void) +{ + shmobile_suspend_init(); + shmobile_cpuidle_init(); +} + +#endif /* __ARCH_MACH_COMMON_H */ diff --git a/arch/arm/mach-shmobile/include/mach/dma-register.h b/arch/arm/mach-shmobile/include/mach/dma-register.h new file mode 100644 index 00000000000..97c40bd9b94 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/dma-register.h @@ -0,0 +1,84 @@ +/* + * SH-ARM CPU-specific DMA definitions, used by both DMA drivers + * + * Copyright (C) 2012 Renesas Solutions Corp + * + * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * Based on arch/sh/include/cpu-sh4/cpu/dma-register.h + * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef DMA_REGISTER_H +#define DMA_REGISTER_H + +/* + * Direct Memory Access Controller + */ + +/* Transmit sizes and respective CHCR register values */ +enum { + XMIT_SZ_8BIT = 0, + XMIT_SZ_16BIT = 1, + XMIT_SZ_32BIT = 2, + XMIT_SZ_64BIT = 7, + XMIT_SZ_128BIT = 3, + XMIT_SZ_256BIT = 4, + XMIT_SZ_512BIT = 5, +}; + +/* log2(size / 8) - used to calculate number of transfers */ +static const unsigned int dma_ts_shift[] = { + [XMIT_SZ_8BIT] = 0, + [XMIT_SZ_16BIT] = 1, + [XMIT_SZ_32BIT] = 2, + [XMIT_SZ_64BIT] = 3, + [XMIT_SZ_128BIT] = 4, + [XMIT_SZ_256BIT] = 5, + [XMIT_SZ_512BIT] = 6, +}; + +#define TS_LOW_BIT 0x3 /* --xx */ +#define TS_HI_BIT 0xc /* xx-- */ + +#define TS_LOW_SHIFT (3) +#define TS_HI_SHIFT (20 - 2) /* 2 bits for shifted low TS */ + +#define TS_INDEX2VAL(i) \ + ((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\ + (((i) & TS_HI_BIT) << TS_HI_SHIFT)) + +#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz))) +#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz))) + + +/* + * USB High-Speed DMAC + */ +/* Transmit sizes and respective CHCR register values */ +enum { + USBTS_XMIT_SZ_8BYTE = 0, + USBTS_XMIT_SZ_16BYTE = 1, + USBTS_XMIT_SZ_32BYTE = 2, +}; + +/* log2(size / 8) - used to calculate number of transfers */ +static const unsigned int dma_usbts_shift[] = { + [USBTS_XMIT_SZ_8BYTE] = 3, + [USBTS_XMIT_SZ_16BYTE] = 4, + [USBTS_XMIT_SZ_32BYTE] = 5, +}; + +#define USBTS_LOW_BIT 0x3 /* --xx */ +#define USBTS_HI_BIT 0x0 /* ---- */ + +#define USBTS_LOW_SHIFT 6 +#define USBTS_HI_SHIFT 0 + +#define USBTS_INDEX2VAL(i) (((i) & 3) << 6) + +#endif /* DMA_REGISTER_H */ diff --git a/arch/arm/mach-shmobile/include/mach/head-kzm9g.txt b/arch/arm/mach-shmobile/include/mach/head-kzm9g.txt new file mode 100644 index 00000000000..9531f46a822 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/head-kzm9g.txt @@ -0,0 +1,410 @@ +LIST "KZM9G low-level initialization routine." +LIST "Adapted from u-boot KZM9G support code." + +LIST "Copyright (C) 2013 Ulrich Hecht" + +LIST "This program is free software; you can redistribute it and/or modify" +LIST "it under the terms of the GNU General Public License version 2 as" +LIST "published by the Free Software Foundation." + +LIST "This program is distributed in the hope that it will be useful," +LIST "but WITHOUT ANY WARRANTY; without even the implied warranty of" +LIST "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the" +LIST "GNU General Public License for more details." + + +LIST "Register definitions:" + +LIST "Secure control register" +#define LIFEC_SEC_SRC (0xE6110008) + +LIST "RWDT" +#define RWDT_BASE (0xE6020000) +#define RWTCSRA0 (RWDT_BASE + 0x04) + +LIST "HPB Semaphore Control Registers" +#define HPBSCR_BASE (0xE6000000) +#define HPBCTRL6 (HPBSCR_BASE + 0x1030) + +#define SBSC1_BASE (0xFE400000) +#define SDCR0A (SBSC1_BASE + 0x0008) +#define SDCR1A (SBSC1_BASE + 0x000C) +#define SDPCRA (SBSC1_BASE + 0x0010) +#define SDCR0SA (SBSC1_BASE + 0x0018) +#define SDCR1SA (SBSC1_BASE + 0x001C) +#define RTCSRA (SBSC1_BASE + 0x0020) +#define RTCORA (SBSC1_BASE + 0x0028) +#define RTCORHA (SBSC1_BASE + 0x002C) +#define SDWCRC0A (SBSC1_BASE + 0x0040) +#define SDWCRC1A (SBSC1_BASE + 0x0044) +#define SDWCR00A (SBSC1_BASE + 0x0048) +#define SDWCR01A (SBSC1_BASE + 0x004C) +#define SDWCR10A (SBSC1_BASE + 0x0050) +#define SDWCR11A (SBSC1_BASE + 0x0054) +#define SDWCR2A (SBSC1_BASE + 0x0060) +#define SDWCRC2A (SBSC1_BASE + 0x0064) +#define ZQCCRA (SBSC1_BASE + 0x0068) +#define SDMRACR0A (SBSC1_BASE + 0x0084) +#define SDMRTMPCRA (SBSC1_BASE + 0x008C) +#define SDMRTMPMSKA (SBSC1_BASE + 0x0094) +#define SDGENCNTA (SBSC1_BASE + 0x009C) +#define SDDRVCR0A (SBSC1_BASE + 0x00B4) +#define DLLCNT0A (SBSC1_BASE + 0x0354) + +#define SDMRA1 (0xFE500000) +#define SDMRA2 (0xFE5C0000) +#define SDMRA3 (0xFE504000) + +#define SBSC2_BASE (0xFB400000) +#define SDCR0B (SBSC2_BASE + 0x0008) +#define SDCR1B (SBSC2_BASE + 0x000C) +#define SDPCRB (SBSC2_BASE + 0x0010) +#define SDCR0SB (SBSC2_BASE + 0x0018) +#define SDCR1SB (SBSC2_BASE + 0x001C) +#define RTCSRB (SBSC2_BASE + 0x0020) +#define RTCORB (SBSC2_BASE + 0x0028) +#define RTCORHB (SBSC2_BASE + 0x002C) +#define SDWCRC0B (SBSC2_BASE + 0x0040) +#define SDWCRC1B (SBSC2_BASE + 0x0044) +#define SDWCR00B (SBSC2_BASE + 0x0048) +#define SDWCR01B (SBSC2_BASE + 0x004C) +#define SDWCR10B (SBSC2_BASE + 0x0050) +#define SDWCR11B (SBSC2_BASE + 0x0054) +#define SDPDCR0B (SBSC2_BASE + 0x0058) +#define SDWCR2B (SBSC2_BASE + 0x0060) +#define SDWCRC2B (SBSC2_BASE + 0x0064) +#define ZQCCRB (SBSC2_BASE + 0x0068) +#define SDMRACR0B (SBSC2_BASE + 0x0084) +#define SDMRTMPCRB (SBSC2_BASE + 0x008C) +#define SDMRTMPMSKB (SBSC2_BASE + 0x0094) +#define SDGENCNTB (SBSC2_BASE + 0x009C) +#define DPHYCNT0B (SBSC2_BASE + 0x00A0) +#define DPHYCNT1B (SBSC2_BASE + 0x00A4) +#define DPHYCNT2B (SBSC2_BASE + 0x00A8) +#define SDDRVCR0B (SBSC2_BASE + 0x00B4) +#define DLLCNT0B (SBSC2_BASE + 0x0354) + +#define SDMRB1 (0xFB500000) +#define SDMRB2 (0xFB5C0000) +#define SDMRB3 (0xFB504000) + +#define CPG_BASE (0xE6150000) +#define FRQCRA (CPG_BASE + 0x0000) +#define FRQCRB (CPG_BASE + 0x0004) +#define FRQCRD (CPG_BASE + 0x00E4) +#define VCLKCR1 (CPG_BASE + 0x0008) +#define VCLKCR2 (CPG_BASE + 0x000C) +#define VCLKCR3 (CPG_BASE + 0x001C) +#define ZBCKCR (CPG_BASE + 0x0010) +#define FLCKCR (CPG_BASE + 0x0014) +#define SD0CKCR (CPG_BASE + 0x0074) +#define SD1CKCR (CPG_BASE + 0x0078) +#define SD2CKCR (CPG_BASE + 0x007C) +#define FSIACKCR (CPG_BASE + 0x0018) +#define SUBCKCR (CPG_BASE + 0x0080) +#define SPUACKCR (CPG_BASE + 0x0084) +#define SPUVCKCR (CPG_BASE + 0x0094) +#define MSUCKCR (CPG_BASE + 0x0088) +#define HSICKCR (CPG_BASE + 0x008C) +#define FSIBCKCR (CPG_BASE + 0x0090) +#define MFCK1CR (CPG_BASE + 0x0098) +#define MFCK2CR (CPG_BASE + 0x009C) +#define DSITCKCR (CPG_BASE + 0x0060) +#define DSI0PCKCR (CPG_BASE + 0x0064) +#define DSI1PCKCR (CPG_BASE + 0x0068) +#define DSI0PHYCR (CPG_BASE + 0x006C) +#define DVFSCR3 (CPG_BASE + 0x0174) +#define DVFSCR4 (CPG_BASE + 0x0178) +#define DVFSCR5 (CPG_BASE + 0x017C) +#define MPMODE (CPG_BASE + 0x00CC) + +#define PLLECR (CPG_BASE + 0x00D0) +#define PLL0CR (CPG_BASE + 0x00D8) +#define PLL1CR (CPG_BASE + 0x0028) +#define PLL2CR (CPG_BASE + 0x002C) +#define PLL3CR (CPG_BASE + 0x00DC) +#define PLL0STPCR (CPG_BASE + 0x00F0) +#define PLL1STPCR (CPG_BASE + 0x00C8) +#define PLL2STPCR (CPG_BASE + 0x00F8) +#define PLL3STPCR (CPG_BASE + 0x00FC) +#define RMSTPCR0 (CPG_BASE + 0x0110) +#define RMSTPCR1 (CPG_BASE + 0x0114) +#define RMSTPCR2 (CPG_BASE + 0x0118) +#define RMSTPCR3 (CPG_BASE + 0x011C) +#define RMSTPCR4 (CPG_BASE + 0x0120) +#define RMSTPCR5 (CPG_BASE + 0x0124) +#define SMSTPCR0 (CPG_BASE + 0x0130) +#define SMSTPCR2 (CPG_BASE + 0x0138) +#define SMSTPCR3 (CPG_BASE + 0x013C) +#define CPGXXCR4 (CPG_BASE + 0x0150) +#define SRCR0 (CPG_BASE + 0x80A0) +#define SRCR2 (CPG_BASE + 0x80B0) +#define SRCR3 (CPG_BASE + 0x80A8) +#define VREFCR (CPG_BASE + 0x00EC) +#define PCLKCR (CPG_BASE + 0x1020) + +#define PORT32CR (0xE6051020) +#define PORT33CR (0xE6051021) +#define PORT34CR (0xE6051022) +#define PORT35CR (0xE6051023) + +LIST "DRAM initialization code:" + +EW RWTCSRA0, 0xA507 + +ED_AND LIFEC_SEC_SRC, 0xFFFF7FFF + +ED_AND SMSTPCR3,0xFFFF7FFF +ED_AND SRCR3, 0xFFFF7FFF +ED_AND SMSTPCR2,0xFFFBFFFF +ED_AND SRCR2, 0xFFFBFFFF +ED PLLECR, 0x00000000 + +WAIT_MASK PLLECR, 0x00000F00, 0x00000000 +WAIT_MASK FRQCRB, 0x80000000, 0x00000000 + +ED PLL0CR, 0x2D000000 +ED PLL1CR, 0x17100000 +ED FRQCRB, 0x96235880 +WAIT_MASK FRQCRB, 0x80000000, 0x00000000 + +ED FLCKCR, 0x0000000B +ED_AND SMSTPCR0, 0xFFFFFFFD + +ED_AND SRCR0, 0xFFFFFFFD +ED 0xE6001628, 0x514 +ED 0xE6001648, 0x514 +ED 0xE6001658, 0x514 +ED 0xE6001678, 0x514 + +ED DVFSCR4, 0x00092000 +ED DVFSCR5, 0x000000DC +ED PLLECR, 0x00000000 +WAIT_MASK PLLECR, 0x00000F00, 0x00000000 + +ED FRQCRA, 0x0012453C +ED FRQCRB, 0x80431350 +WAIT_MASK FRQCRB, 0x80000000, 0x00000000 +ED FRQCRD, 0x00000B0B +WAIT_MASK FRQCRD, 0x80000000, 0x00000000 + +ED PCLKCR, 0x00000003 +ED VCLKCR1, 0x0000012F +ED VCLKCR2, 0x00000119 +ED VCLKCR3, 0x00000119 +ED ZBCKCR, 0x00000002 +ED FLCKCR, 0x00000005 +ED SD0CKCR, 0x00000080 +ED SD1CKCR, 0x00000080 +ED SD2CKCR, 0x00000080 +ED FSIACKCR, 0x0000003F +ED FSIBCKCR, 0x0000003F +ED SUBCKCR, 0x00000080 +ED SPUACKCR, 0x0000000B +ED SPUVCKCR, 0x0000000B +ED MSUCKCR, 0x0000013F +ED HSICKCR, 0x00000080 +ED MFCK1CR, 0x0000003F +ED MFCK2CR, 0x0000003F +ED DSITCKCR, 0x00000107 +ED DSI0PCKCR, 0x00000313 +ED DSI1PCKCR, 0x0000130D +ED DSI0PHYCR, 0x2A800E0E +ED PLL0CR, 0x1E000000 +ED PLL0CR, 0x2D000000 +ED PLL1CR, 0x17100000 +ED PLL2CR, 0x27000080 +ED PLL3CR, 0x1D000000 +ED PLL0STPCR, 0x00080000 +ED PLL1STPCR, 0x000120C0 +ED PLL2STPCR, 0x00012000 +ED PLL3STPCR, 0x00000030 +ED PLLECR, 0x0000000B +WAIT_MASK PLLECR, 0x00000B00, 0x00000B00 + +ED DVFSCR3, 0x000120F0 +ED MPMODE, 0x00000020 +ED VREFCR, 0x0000028A +ED RMSTPCR0, 0xE4628087 +ED RMSTPCR1, 0xFFFFFFFF +ED RMSTPCR2, 0x53FFFFFF +ED RMSTPCR3, 0xFFFFFFFF +ED RMSTPCR4, 0x00800D3D +ED RMSTPCR5, 0xFFFFF3FF +ED SMSTPCR2, 0x00000000 +ED SRCR2, 0x00040000 +ED_AND PLLECR, 0xFFFFFFF7 +WAIT_MASK PLLECR, 0x00000800, 0x00000000 + +LIST "set SBSC operational" +ED HPBCTRL6, 0x00000001 +WAIT_MASK HPBCTRL6, 0x00000001, 0x00000001 + +LIST "set SBSC operating frequency" +ED FRQCRD, 0x00001414 +WAIT_MASK FRQCRD, 0x80000000, 0x00000000 +ED PLL3CR, 0x1D000000 +ED_OR PLLECR, 0x00000008 +WAIT_MASK PLLECR, 0x00000800, 0x00000800 + +LIST "enable DLL oscillation in DDRPHY" +ED_OR DLLCNT0A, 0x00000002 + +LIST "wait >= 100 ns" +ED SDGENCNTA, 0x00000005 +WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000 + +LIST "target LPDDR2 device settings" +ED SDCR0A, 0xACC90159 +ED SDCR1A, 0x00010059 +ED SDWCRC0A, 0x50874114 +ED SDWCRC1A, 0x33199B37 +ED SDWCRC2A, 0x008F2313 +ED SDWCR00A, 0x31020707 +ED SDWCR01A, 0x0017040A +ED SDWCR10A, 0x31020707 +ED SDWCR11A, 0x0017040A + +ED SDDRVCR0A, 0x055557ff + +ED SDWCR2A, 0x30000000 + +LIST "drive CKE high" +ED_OR SDPCRA, 0x00000080 +WAIT_MASK SDPCRA, 0x00000080, 0x00000080 + +LIST "wait >= 200 us" +ED SDGENCNTA, 0x00002710 +WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000 + +LIST "issue reset command to LPDDR2 device" +ED SDMRACR0A, 0x0000003F +ED SDMRA1, 0x00000000 + +LIST "wait >= 10 (or 1) us (docs inconsistent)" +ED SDGENCNTA, 0x000001F4 +WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000 + +LIST "MRW ZS initialization calibration command" +ED SDMRACR0A, 0x0000FF0A +ED SDMRA3, 0x00000000 + +LIST "wait >= 1 us" +ED SDGENCNTA, 0x00000032 +WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000 + +LIST "specify operating mode in LPDDR2" +ED SDMRACR0A, 0x00002201 +ED SDMRA1, 0x00000000 +ED SDMRACR0A, 0x00000402 +ED SDMRA1, 0x00000000 +ED SDMRACR0A, 0x00000203 +ED SDMRA1, 0x00000000 + +LIST "initialize DDR interface" +ED SDMRA2, 0x00000000 + +LIST "temperature sensor control" +ED SDMRTMPCRA, 0x88800004 +ED SDMRTMPMSKA,0x00000004 + +LIST "auto-refreshing control" +ED RTCORA, 0xA55A0032 +ED RTCORHA, 0xA55A000C +ED RTCSRA, 0xA55A2048 + +ED_OR SDCR0A, 0x00000800 +ED_OR SDCR1A, 0x00000400 + +LIST "auto ZQ calibration control" +ED ZQCCRA, 0xFFF20000 + +ED_OR DLLCNT0B, 0x00000002 +ED SDGENCNTB, 0x00000005 +WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000 + +ED SDCR0B, 0xACC90159 +ED SDCR1B, 0x00010059 +ED SDWCRC0B, 0x50874114 +ED SDWCRC1B, 0x33199B37 +ED SDWCRC2B, 0x008F2313 +ED SDWCR00B, 0x31020707 +ED SDWCR01B, 0x0017040A +ED SDWCR10B, 0x31020707 +ED SDWCR11B, 0x0017040A +ED SDDRVCR0B, 0x055557ff +ED SDWCR2B, 0x30000000 +ED_OR SDPCRB, 0x00000080 +WAIT_MASK SDPCRB, 0x00000080, 0x00000080 + +ED SDGENCNTB, 0x00002710 +WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000 +ED SDMRACR0B, 0x0000003F + +LIST "upstream u-boot writes to SDMRA1A for both SBSC 1 and 2, which does" +LIST "not seem to make a lot of sense..." +ED SDMRB1, 0x00000000 + +ED SDGENCNTB, 0x000001F4 +WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000 + +ED SDMRACR0B, 0x0000FF0A +ED SDMRB3, 0x00000000 +ED SDGENCNTB, 0x00000032 +WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000 + +ED SDMRACR0B, 0x00002201 +ED SDMRB1, 0x00000000 +ED SDMRACR0B, 0x00000402 +ED SDMRB1, 0x00000000 +ED SDMRACR0B, 0x00000203 +ED SDMRB1, 0x00000000 +ED SDMRB2, 0x00000000 +ED SDMRTMPCRB, 0x88800004 +ED SDMRTMPMSKB, 0x00000004 +ED RTCORB, 0xA55A0032 +ED RTCORHB, 0xA55A000C +ED RTCSRB, 0xA55A2048 +ED_OR SDCR0B, 0x00000800 +ED_OR SDCR1B, 0x00000400 +ED ZQCCRB, 0xFFF20000 +ED_OR SDPDCR0B, 0x00030000 +ED DPHYCNT1B, 0xA5390000 +ED DPHYCNT0B, 0x00001200 +ED DPHYCNT1B, 0x07CE0000 +ED DPHYCNT0B, 0x00001247 +WAIT_MASK DPHYCNT2B, 0xFFFFFFFF, 0x07CE0000 + +ED_AND SDPDCR0B, 0xFFFCFFFF + +ED FRQCRD, 0x00000B0B +WAIT_MASK FRQCRD, 0x80000000, 0x00000000 + +ED CPGXXCR4, 0xfffffffc + +LIST "Setup SCIF4 / workaround" +EB PORT32CR, 0x12 +EB PORT33CR, 0x22 +EB PORT34CR, 0x12 +EB PORT35CR, 0x22 + +EW 0xE6C80000, 0 +EB 0xE6C80004, 0x19 +EW 0xE6C80008, 0x0030 +EW 0xE6C80018, 0 +EW 0xE6C80030, 0x0014 + +LIST "Magic to avoid hangs and corruption on DRAM writes." + +LIST "It has been observed that the system would most often hang while" +LIST "decompressing the kernel, and if it didn't it would always write" +LIST "a corrupt image to DRAM." +LIST "This problem does not occur in u-boot, and the reason is that" +LIST "u-boot performs an additional cache invalidation after setting up" +LIST "the DRAM controller. Such an invalidation should not be necessary at" +LIST "this point, and attempts at removing parts of the routine to arrive" +LIST "at the minimal snippet of code necessary to avoid the DRAM stability" +LIST "problem yielded the following:" + +MRC p15, 0, r0, c1, c0, 0 +MCR p15, 0, r0, c1, c0, 0 diff --git a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt new file mode 100644 index 00000000000..9f134dfeffd --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt @@ -0,0 +1,93 @@ +LIST "partner-jet-setup.txt" +LIST "(C) Copyright 2010 Renesas Solutions Corp" +LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>" + +LIST "RWT Setting" +EW 0xE6020004, 0xA500 +EW 0xE6030004, 0xA500 + +LIST "GPIO Setting" +EB 0xE6051013, 0xA2 + +LIST "CPG" +ED 0xE61500C0, 0x00000002 + +WAIT 1, 0xFE40009C + +LIST "FRQCR" +ED 0xE6150000, 0x2D1305C3 +ED 0xE61500E0, 0x9E40358E +ED 0xE6150004, 0x80331050 + +WAIT 1, 0xFE40009C + +ED 0xE61500E4, 0x00002000 + +WAIT 1, 0xFE40009C + +LIST "PLL" +ED 0xE6150028, 0x00004000 + +WAIT 1, 0xFE40009C + +ED 0xE615002C, 0x93000040 + +WAIT 1, 0xFE40009C + +LIST "SUB/USBClk" +ED 0xE6150080, 0x00000180 + +LIST "BSC" +ED 0xFEC10000, 0x00E0001B + +LIST "SBSC1" +ED 0xFE400354, 0x01AD8000 +ED 0xFE400354, 0x01AD8001 + +WAIT 5, 0xFE40009C + +ED 0xFE400008, 0xBCC90151 +ED 0xFE400040, 0x41774113 +ED 0xFE400044, 0x2712E229 +ED 0xFE400048, 0x20C18505 +ED 0xFE40004C, 0x00110209 +ED 0xFE400010, 0x00000087 + +WAIT 30, 0xFE40009C + +ED 0xFE400084, 0x0000003F +EB 0xFE500000, 0x00 + +WAIT 5, 0xFE40009C + +ED 0xFE400084, 0x0000FF0A +EB 0xFE500000, 0x00 + +WAIT 1, 0xFE40009C + +ED 0xFE400084, 0x00002201 +EB 0xFE500000, 0x00 +ED 0xFE400084, 0x00000302 +EB 0xFE500000, 0x00 +EB 0xFE5C0000, 0x00 +ED 0xFE400008, 0xBCC90159 +ED 0xFE40008C, 0x88800004 +ED 0xFE400094, 0x00000004 +ED 0xFE400028, 0xA55A0032 +ED 0xFE40002C, 0xA55A000C +ED 0xFE400020, 0xA55A2048 +ED 0xFE400008, 0xBCC90959 + +LIST "Change CPGA setting" +ED 0xE61500E0, 0x9E40352E +ED 0xE6150004, 0x80331050 + +WAIT 1, 0xFE40009C + +ED 0xFE400354, 0x01AD8002 + +LIST "SCIF0 - Serial port for earlyprintk" +EB 0xE6053098, 0xe1 +EW 0xE6C40000, 0x0000 +EB 0xE6C40004, 0x19 +EW 0xE6C40008, 0x0030 diff --git a/arch/arm/mach-shmobile/include/mach/intc.h b/arch/arm/mach-shmobile/include/mach/intc.h new file mode 100644 index 00000000000..a5603c76cfe --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/intc.h @@ -0,0 +1,290 @@ +#ifndef __ASM_MACH_INTC_H +#define __ASM_MACH_INTC_H +#include <linux/sh_intc.h> + +#define INTC_IRQ_PINS_ENUM_16L(p) \ + p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7, \ + p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 + +#define INTC_IRQ_PINS_ENUM_16H(p) \ + p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23, \ + p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 + +#define INTC_IRQ_PINS_VECT_16L(p, vect) \ + vect(p ## _IRQ0, 0x0200), vect(p ## _IRQ1, 0x0220), \ + vect(p ## _IRQ2, 0x0240), vect(p ## _IRQ3, 0x0260), \ + vect(p ## _IRQ4, 0x0280), vect(p ## _IRQ5, 0x02a0), \ + vect(p ## _IRQ6, 0x02c0), vect(p ## _IRQ7, 0x02e0), \ + vect(p ## _IRQ8, 0x0300), vect(p ## _IRQ9, 0x0320), \ + vect(p ## _IRQ10, 0x0340), vect(p ## _IRQ11, 0x0360), \ + vect(p ## _IRQ12, 0x0380), vect(p ## _IRQ13, 0x03a0), \ + vect(p ## _IRQ14, 0x03c0), vect(p ## _IRQ15, 0x03e0) + +#define INTC_IRQ_PINS_VECT_16H(p, vect) \ + vect(p ## _IRQ16, 0x3200), vect(p ## _IRQ17, 0x3220), \ + vect(p ## _IRQ18, 0x3240), vect(p ## _IRQ19, 0x3260), \ + vect(p ## _IRQ20, 0x3280), vect(p ## _IRQ21, 0x32a0), \ + vect(p ## _IRQ22, 0x32c0), vect(p ## _IRQ23, 0x32e0), \ + vect(p ## _IRQ24, 0x3300), vect(p ## _IRQ25, 0x3320), \ + vect(p ## _IRQ26, 0x3340), vect(p ## _IRQ27, 0x3360), \ + vect(p ## _IRQ28, 0x3380), vect(p ## _IRQ29, 0x33a0), \ + vect(p ## _IRQ30, 0x33c0), vect(p ## _IRQ31, 0x33e0) + +#define INTC_IRQ_PINS_MASK_16L(p, base) \ + { base + 0x40, base + 0x60, 8, /* INTMSK00A / INTMSKCLR00A */ \ + { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ + { base + 0x44, base + 0x64, 8, /* INTMSK10A / INTMSKCLR10A */ \ + { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } + +#define INTC_IRQ_PINS_MASK_16H(p, base) \ + { base + 0x48, base + 0x68, 8, /* INTMSK20A / INTMSKCLR20A */ \ + { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ + { base + 0x4c, base + 0x6c, 8, /* INTMSK30A / INTMSKCLR30A */ \ + { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } + +#define INTC_IRQ_PINS_PRIO_16L(p, base) \ + { base + 0x10, 0, 32, 4, /* INTPRI00A */ \ + { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ + { base + 0x14, 0, 32, 4, /* INTPRI10A */ \ + { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } + +#define INTC_IRQ_PINS_PRIO_16H(p, base) \ + { base + 0x18, 0, 32, 4, /* INTPRI20A */ \ + { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ + { base + 0x1c, 0, 32, 4, /* INTPRI30A */ \ + { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } + +#define INTC_IRQ_PINS_SENSE_16L(p, base) \ + { base + 0x00, 32, 4, /* ICR1A */ \ + { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ + { base + 0x04, 32, 4, /* ICR2A */ \ + { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } + +#define INTC_IRQ_PINS_SENSE_16H(p, base) \ + { base + 0x08, 32, 4, /* ICR3A */ \ + { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ + { base + 0x0c, 32, 4, /* ICR4A */ \ + { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } + +#define INTC_IRQ_PINS_ACK_16L(p, base) \ + { base + 0x20, 0, 8, /* INTREQ00A */ \ + { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ + { base + 0x24, 0, 8, /* INTREQ10A */ \ + { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } + +#define INTC_IRQ_PINS_ACK_16H(p, base) \ + { base + 0x28, 0, 8, /* INTREQ20A */ \ + { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ + { base + 0x2c, 0, 8, /* INTREQ30A */ \ + { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } + +#define INTC_IRQ_PINS_16(p, base, vect, str) \ + \ +static struct resource p ## _resources[] __initdata = { \ + [0] = { \ + .start = base, \ + .end = base + 0x64, \ + .flags = IORESOURCE_MEM, \ + }, \ +}; \ + \ +enum { \ + p ## _UNUSED = 0, \ + INTC_IRQ_PINS_ENUM_16L(p), \ +}; \ + \ +static struct intc_vect p ## _vectors[] __initdata = { \ + INTC_IRQ_PINS_VECT_16L(p, vect), \ +}; \ + \ +static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ + INTC_IRQ_PINS_MASK_16L(p, base), \ +}; \ + \ +static struct intc_prio_reg p ## _prio_registers[] __initdata = { \ + INTC_IRQ_PINS_PRIO_16L(p, base), \ +}; \ + \ +static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ + INTC_IRQ_PINS_SENSE_16L(p, base), \ +}; \ + \ +static struct intc_mask_reg p ## _ack_registers[] __initdata = { \ + INTC_IRQ_PINS_ACK_16L(p, base), \ +}; \ + \ +static struct intc_desc p ## _desc __initdata = { \ + .name = str, \ + .resource = p ## _resources, \ + .num_resources = ARRAY_SIZE(p ## _resources), \ + .hw = INTC_HW_DESC(p ## _vectors, NULL, \ + p ## _mask_registers, p ## _prio_registers, \ + p ## _sense_registers, p ## _ack_registers) \ +} + +#define INTC_IRQ_PINS_16H(p, base, vect, str) \ + \ +static struct resource p ## _resources[] __initdata = { \ + [0] = { \ + .start = base, \ + .end = base + 0x64, \ + .flags = IORESOURCE_MEM, \ + }, \ +}; \ + \ +enum { \ + p ## _UNUSED = 0, \ + INTC_IRQ_PINS_ENUM_16H(p), \ +}; \ + \ +static struct intc_vect p ## _vectors[] __initdata = { \ + INTC_IRQ_PINS_VECT_16H(p, vect), \ +}; \ + \ +static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ + INTC_IRQ_PINS_MASK_16H(p, base), \ +}; \ + \ +static struct intc_prio_reg p ## _prio_registers[] __initdata = { \ + INTC_IRQ_PINS_PRIO_16H(p, base), \ +}; \ + \ +static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ + INTC_IRQ_PINS_SENSE_16H(p, base), \ +}; \ + \ +static struct intc_mask_reg p ## _ack_registers[] __initdata = { \ + INTC_IRQ_PINS_ACK_16H(p, base), \ +}; \ + \ +static struct intc_desc p ## _desc __initdata = { \ + .name = str, \ + .resource = p ## _resources, \ + .num_resources = ARRAY_SIZE(p ## _resources), \ + .hw = INTC_HW_DESC(p ## _vectors, NULL, \ + p ## _mask_registers, p ## _prio_registers, \ + p ## _sense_registers, p ## _ack_registers) \ +} + +#define INTC_IRQ_PINS_32(p, base, vect, str) \ + \ +static struct resource p ## _resources[] __initdata = { \ + [0] = { \ + .start = base, \ + .end = base + 0x6c, \ + .flags = IORESOURCE_MEM, \ + }, \ +}; \ + \ +enum { \ + p ## _UNUSED = 0, \ + INTC_IRQ_PINS_ENUM_16L(p), \ + INTC_IRQ_PINS_ENUM_16H(p), \ +}; \ + \ +static struct intc_vect p ## _vectors[] __initdata = { \ + INTC_IRQ_PINS_VECT_16L(p, vect), \ + INTC_IRQ_PINS_VECT_16H(p, vect), \ +}; \ + \ +static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ + INTC_IRQ_PINS_MASK_16L(p, base), \ + INTC_IRQ_PINS_MASK_16H(p, base), \ +}; \ + \ +static struct intc_prio_reg p ## _prio_registers[] __initdata = { \ + INTC_IRQ_PINS_PRIO_16L(p, base), \ + INTC_IRQ_PINS_PRIO_16H(p, base), \ +}; \ + \ +static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ + INTC_IRQ_PINS_SENSE_16L(p, base), \ + INTC_IRQ_PINS_SENSE_16H(p, base), \ +}; \ + \ +static struct intc_mask_reg p ## _ack_registers[] __initdata = { \ + INTC_IRQ_PINS_ACK_16L(p, base), \ + INTC_IRQ_PINS_ACK_16H(p, base), \ +}; \ + \ +static struct intc_desc p ## _desc __initdata = { \ + .name = str, \ + .resource = p ## _resources, \ + .num_resources = ARRAY_SIZE(p ## _resources), \ + .hw = INTC_HW_DESC(p ## _vectors, NULL, \ + p ## _mask_registers, p ## _prio_registers, \ + p ## _sense_registers, p ## _ack_registers) \ +} + +#define INTC_PINT_E_EMPTY +#define INTC_PINT_E_NONE 0, 0, 0, 0, 0, 0, 0, 0, +#define INTC_PINT_E(p) \ + PINT ## p ## 0, PINT ## p ## 1, PINT ## p ## 2, PINT ## p ## 3, \ + PINT ## p ## 4, PINT ## p ## 5, PINT ## p ## 6, PINT ## p ## 7, + +#define INTC_PINT_V_NONE +#define INTC_PINT_V(p, vect) \ + vect(PINT ## p ## 0, 0), vect(PINT ## p ## 1, 1), \ + vect(PINT ## p ## 2, 2), vect(PINT ## p ## 3, 3), \ + vect(PINT ## p ## 4, 4), vect(PINT ## p ## 5, 5), \ + vect(PINT ## p ## 6, 6), vect(PINT ## p ## 7, 7), + +#define INTC_PINT(p, mask_reg, sense_base, str, \ + enums_1, enums_2, enums_3, enums_4, \ + vect_1, vect_2, vect_3, vect_4, \ + mask_a, mask_b, mask_c, mask_d, \ + sense_a, sense_b, sense_c, sense_d) \ + \ +enum { \ + PINT ## p ## _UNUSED = 0, \ + enums_1 enums_2 enums_3 enums_4 \ +}; \ + \ +static struct intc_vect p ## _vectors[] __initdata = { \ + vect_1 vect_2 vect_3 vect_4 \ +}; \ + \ +static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ + { mask_reg, 0, 32, /* PINTER */ \ + { mask_a mask_b mask_c mask_d } } \ +}; \ + \ +static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ + { sense_base + 0x00, 16, 2, /* PINTCR */ \ + { sense_a } }, \ + { sense_base + 0x04, 16, 2, /* PINTCR */ \ + { sense_b } }, \ + { sense_base + 0x08, 16, 2, /* PINTCR */ \ + { sense_c } }, \ + { sense_base + 0x0c, 16, 2, /* PINTCR */ \ + { sense_d } }, \ +}; \ + \ +static struct intc_desc p ## _desc __initdata = { \ + .name = str, \ + .hw = INTC_HW_DESC(p ## _vectors, NULL, \ + p ## _mask_registers, NULL, \ + p ## _sense_registers, NULL), \ +} + +#endif /* __ASM_MACH_INTC_H */ diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h new file mode 100644 index 00000000000..d241bfd6926 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/irqs.h @@ -0,0 +1,24 @@ +#ifndef __ASM_MACH_IRQS_H +#define __ASM_MACH_IRQS_H + +#include <linux/sh_intc.h> + +/* GIC */ +#define gic_spi(nr) ((nr) + 32) +#define gic_iid(nr) (nr) /* ICCIAR / interrupt ID */ + +/* INTCS */ +#define INTCS_VECT_BASE 0x3400 +#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) +#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) + +/* External IRQ pins */ +#define IRQPIN_BASE 2000 +#define irq_pin(nr) ((nr) + IRQPIN_BASE) + +/* GPIO IRQ */ +#define _GPIO_IRQ_BASE 2500 +#define GPIO_IRQ_BASE(x) (_GPIO_IRQ_BASE + (32 * x)) +#define GPIO_IRQ(x, y) (_GPIO_IRQ_BASE + (32 * x) + y) + +#endif /* __ASM_MACH_IRQS_H */ diff --git a/arch/arm/mach-shmobile/include/mach/mmc-mackerel.h b/arch/arm/mach-shmobile/include/mach/mmc-mackerel.h new file mode 100644 index 00000000000..15d3a9efdec --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/mmc-mackerel.h @@ -0,0 +1,38 @@ +#ifndef MMC_MACKEREL_H +#define MMC_MACKEREL_H + +#define PORT0CR (void __iomem *)0xe6051000 +#define PORT1CR (void __iomem *)0xe6051001 +#define PORT2CR (void __iomem *)0xe6051002 +#define PORT159CR (void __iomem *)0xe605009f + +#define PORTR031_000DR (void __iomem *)0xe6055000 +#define PORTL159_128DR (void __iomem *)0xe6054010 + +static inline void mmc_init_progress(void) +{ + /* Initialise LEDS0-3 + * registers: PORT0CR-PORT2CR,PORT159CR (LED0-LED3 Control) + * value: 0x10 - enable output + */ + __raw_writeb(0x10, PORT0CR); + __raw_writeb(0x10, PORT1CR); + __raw_writeb(0x10, PORT2CR); + __raw_writeb(0x10, PORT159CR); +} + +static inline void mmc_update_progress(int n) +{ + unsigned a = 0, b = 0; + + if (n < 3) + a = 1 << n; + else + b = 1 << 31; + + __raw_writel((__raw_readl(PORTR031_000DR) & ~0x7) | a, + PORTR031_000DR); + __raw_writel((__raw_readl(PORTL159_128DR) & ~(1 << 31)) | b, + PORTL159_128DR); +} +#endif /* MMC_MACKEREL_H */ diff --git a/arch/arm/mach-shmobile/include/mach/mmc.h b/arch/arm/mach-shmobile/include/mach/mmc.h new file mode 100644 index 00000000000..e979b8fc1da --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/mmc.h @@ -0,0 +1,16 @@ +#ifndef MMC_H +#define MMC_H + +/************************************************** + * + * board specific settings + * + **************************************************/ + +#ifdef CONFIG_MACH_MACKEREL +#include "mach/mmc-mackerel.h" +#else +#error "unsupported board." +#endif + +#endif /* MMC_H */ diff --git a/arch/arm/mach-shmobile/include/mach/pm-rcar.h b/arch/arm/mach-shmobile/include/mach/pm-rcar.h new file mode 100644 index 00000000000..ef3a1ef628f --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/pm-rcar.h @@ -0,0 +1,15 @@ +#ifndef PM_RCAR_H +#define PM_RCAR_H + +struct rcar_sysc_ch { + unsigned long chan_offs; + unsigned int chan_bit; + unsigned int isr_bit; +}; + +int rcar_sysc_power_down(struct rcar_sysc_ch *sysc_ch); +int rcar_sysc_power_up(struct rcar_sysc_ch *sysc_ch); +bool rcar_sysc_power_is_off(struct rcar_sysc_ch *sysc_ch); +void __iomem *rcar_sysc_init(phys_addr_t base); + +#endif /* PM_RCAR_H */ diff --git a/arch/arm/mach-shmobile/include/mach/pm-rmobile.h b/arch/arm/mach-shmobile/include/mach/pm-rmobile.h new file mode 100644 index 00000000000..690553a0688 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/pm-rmobile.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + * + * Kuninori Morimoto <morimoto.kuninori@renesas.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef PM_RMOBILE_H +#define PM_RMOBILE_H + +#include <linux/pm_domain.h> + +#define DEFAULT_DEV_LATENCY_NS 250000 + +struct platform_device; + +struct rmobile_pm_domain { + struct generic_pm_domain genpd; + struct dev_power_governor *gov; + int (*suspend)(void); + void (*resume)(void); + unsigned int bit_shift; + bool no_debug; +}; + +static inline +struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d) +{ + return container_of(d, struct rmobile_pm_domain, genpd); +} + +struct pm_domain_device { + const char *domain_name; + struct platform_device *pdev; +}; + +#ifdef CONFIG_PM +extern void rmobile_init_domains(struct rmobile_pm_domain domains[], int num); +extern void rmobile_add_device_to_domain_td(const char *domain_name, + struct platform_device *pdev, + struct gpd_timing_data *td); + +static inline void rmobile_add_device_to_domain(const char *domain_name, + struct platform_device *pdev) +{ + rmobile_add_device_to_domain_td(domain_name, pdev, NULL); +} + +extern void rmobile_add_devices_to_domains(struct pm_domain_device data[], + int size); +#else + +#define rmobile_init_domains(domains, num) do { } while (0) +#define rmobile_add_device_to_domain_td(name, pdev, td) do { } while (0) +#define rmobile_add_device_to_domain(name, pdev) do { } while (0) + +static inline void rmobile_add_devices_to_domains(struct pm_domain_device d[], + int size) {} +#endif /* CONFIG_PM */ + +#endif /* PM_RMOBILE_H */ diff --git a/arch/arm/mach-shmobile/include/mach/r7s72100.h b/arch/arm/mach-shmobile/include/mach/r7s72100.h new file mode 100644 index 00000000000..5f34b20ecd4 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r7s72100.h @@ -0,0 +1,8 @@ +#ifndef __ASM_R7S72100_H__ +#define __ASM_R7S72100_H__ + +void r7s72100_add_dt_devices(void); +void r7s72100_clock_init(void); +void r7s72100_init_early(void); + +#endif /* __ASM_R7S72100_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h new file mode 100644 index 00000000000..ce8bdd1d8a8 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h @@ -0,0 +1,19 @@ +#ifndef __ASM_R8A73A4_H__ +#define __ASM_R8A73A4_H__ + +/* DMA slave IDs */ +enum { + SHDMA_SLAVE_INVALID, + SHDMA_SLAVE_MMCIF0_TX, + SHDMA_SLAVE_MMCIF0_RX, + SHDMA_SLAVE_MMCIF1_TX, + SHDMA_SLAVE_MMCIF1_RX, +}; + +void r8a73a4_add_standard_devices(void); +void r8a73a4_add_dt_devices(void); +void r8a73a4_clock_init(void); +void r8a73a4_pinmux_init(void); +void r8a73a4_init_early(void); + +#endif /* __ASM_R8A73A4_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h new file mode 100644 index 00000000000..5e3c9ec0630 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ASM_R8A7740_H__ +#define __ASM_R8A7740_H__ + +#include <mach/pm-rmobile.h> + +/* + * MD_CKx pin + */ +#define MD_CK2 (1 << 2) +#define MD_CK1 (1 << 1) +#define MD_CK0 (1 << 0) + +/* DMA slave IDs */ +enum { + SHDMA_SLAVE_INVALID, + SHDMA_SLAVE_SDHI0_RX, + SHDMA_SLAVE_SDHI0_TX, + SHDMA_SLAVE_SDHI1_RX, + SHDMA_SLAVE_SDHI1_TX, + SHDMA_SLAVE_SDHI2_RX, + SHDMA_SLAVE_SDHI2_TX, + SHDMA_SLAVE_FSIA_RX, + SHDMA_SLAVE_FSIA_TX, + SHDMA_SLAVE_FSIB_TX, + SHDMA_SLAVE_USBHS_TX, + SHDMA_SLAVE_USBHS_RX, + SHDMA_SLAVE_MMCIF_TX, + SHDMA_SLAVE_MMCIF_RX, +}; + +extern void r8a7740_meram_workaround(void); +extern void r8a7740_init_irq_of(void); +extern void r8a7740_map_io(void); +extern void r8a7740_add_early_devices(void); +extern void r8a7740_add_standard_devices(void); +extern void r8a7740_add_standard_devices_dt(void); +extern void r8a7740_clock_init(u8 md_ck); +extern void r8a7740_pinmux_init(void); +extern void r8a7740_pm_init(void); + +#ifdef CONFIG_PM +extern void __init r8a7740_init_pm_domains(void); +#else +static inline void r8a7740_init_pm_domains(void) {} +#endif /* CONFIG_PM */ + +#endif /* __ASM_R8A7740_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h new file mode 100644 index 00000000000..f4076a50e97 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * Copyright (C) 2013 Cogent Embedded, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef __ASM_R8A7778_H__ +#define __ASM_R8A7778_H__ + +#include <linux/sh_eth.h> + +/* HPB-DMA slave IDs */ +enum { + HPBDMA_SLAVE_DUMMY, + HPBDMA_SLAVE_SDHI0_TX, + HPBDMA_SLAVE_SDHI0_RX, + HPBDMA_SLAVE_SSI0_TX, + HPBDMA_SLAVE_SSI0_RX, + HPBDMA_SLAVE_SSI1_TX, + HPBDMA_SLAVE_SSI1_RX, + HPBDMA_SLAVE_SSI2_TX, + HPBDMA_SLAVE_SSI2_RX, + HPBDMA_SLAVE_SSI3_TX, + HPBDMA_SLAVE_SSI3_RX, + HPBDMA_SLAVE_SSI4_TX, + HPBDMA_SLAVE_SSI4_RX, + HPBDMA_SLAVE_SSI5_TX, + HPBDMA_SLAVE_SSI5_RX, + HPBDMA_SLAVE_SSI6_TX, + HPBDMA_SLAVE_SSI6_RX, + HPBDMA_SLAVE_SSI7_TX, + HPBDMA_SLAVE_SSI7_RX, + HPBDMA_SLAVE_SSI8_TX, + HPBDMA_SLAVE_SSI8_RX, + HPBDMA_SLAVE_HPBIF0_TX, + HPBDMA_SLAVE_HPBIF0_RX, + HPBDMA_SLAVE_HPBIF1_TX, + HPBDMA_SLAVE_HPBIF1_RX, + HPBDMA_SLAVE_HPBIF2_TX, + HPBDMA_SLAVE_HPBIF2_RX, + HPBDMA_SLAVE_HPBIF3_TX, + HPBDMA_SLAVE_HPBIF3_RX, + HPBDMA_SLAVE_HPBIF4_TX, + HPBDMA_SLAVE_HPBIF4_RX, + HPBDMA_SLAVE_HPBIF5_TX, + HPBDMA_SLAVE_HPBIF5_RX, + HPBDMA_SLAVE_HPBIF6_TX, + HPBDMA_SLAVE_HPBIF6_RX, + HPBDMA_SLAVE_HPBIF7_TX, + HPBDMA_SLAVE_HPBIF7_RX, + HPBDMA_SLAVE_HPBIF8_TX, + HPBDMA_SLAVE_HPBIF8_RX, + HPBDMA_SLAVE_USBFUNC_TX, + HPBDMA_SLAVE_USBFUNC_RX, +}; + +extern void r8a7778_add_standard_devices(void); +extern void r8a7778_add_standard_devices_dt(void); +extern void r8a7778_add_dt_devices(void); + +extern void r8a7778_init_late(void); +extern void r8a7778_init_delay(void); +extern void r8a7778_init_irq_dt(void); +extern void r8a7778_clock_init(void); +extern void r8a7778_init_irq_extpin(int irlm); +extern void r8a7778_init_irq_extpin_dt(int irlm); +extern void r8a7778_pinmux_init(void); + +extern int r8a7778_usb_phy_power(bool enable); + +#endif /* __ASM_R8A7778_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h new file mode 100644 index 00000000000..88eeceaf108 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -0,0 +1,48 @@ +#ifndef __ASM_R8A7779_H__ +#define __ASM_R8A7779_H__ + +#include <linux/sh_clk.h> +#include <linux/pm_domain.h> +#include <mach/pm-rcar.h> + +/* HPB-DMA slave IDs */ +enum { + HPBDMA_SLAVE_DUMMY, + HPBDMA_SLAVE_SDHI0_TX, + HPBDMA_SLAVE_SDHI0_RX, +}; + +struct r8a7779_pm_domain { + struct generic_pm_domain genpd; + struct rcar_sysc_ch ch; +}; + +static inline struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d) +{ + return &container_of(d, struct r8a7779_pm_domain, genpd)->ch; +} + +extern void r8a7779_init_delay(void); +extern void r8a7779_init_irq_extpin(int irlm); +extern void r8a7779_init_irq_extpin_dt(int irlm); +extern void r8a7779_init_irq_dt(void); +extern void r8a7779_map_io(void); +extern void r8a7779_earlytimer_init(void); +extern void r8a7779_add_early_devices(void); +extern void r8a7779_add_standard_devices(void); +extern void r8a7779_add_standard_devices_dt(void); +extern void r8a7779_init_late(void); +extern void r8a7779_clock_init(void); +extern void r8a7779_pinmux_init(void); +extern void r8a7779_pm_init(void); +extern void r8a7779_register_twd(void); + +#ifdef CONFIG_PM +extern void __init r8a7779_init_pm_domains(void); +#else +static inline void r8a7779_init_pm_domains(void) {} +#endif /* CONFIG_PM */ + +extern struct smp_operations r8a7779_smp_ops; + +#endif /* __ASM_R8A7779_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h new file mode 100644 index 00000000000..0b95babe84b --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h @@ -0,0 +1,39 @@ +#ifndef __ASM_R8A7790_H__ +#define __ASM_R8A7790_H__ + +#include <mach/rcar-gen2.h> + +/* DMA slave IDs */ +enum { + RCAR_DMA_SLAVE_INVALID, + AUDIO_DMAC_SLAVE_SSI0_TX, + AUDIO_DMAC_SLAVE_SSI0_RX, + AUDIO_DMAC_SLAVE_SSI1_TX, + AUDIO_DMAC_SLAVE_SSI1_RX, + AUDIO_DMAC_SLAVE_SSI2_TX, + AUDIO_DMAC_SLAVE_SSI2_RX, + AUDIO_DMAC_SLAVE_SSI3_TX, + AUDIO_DMAC_SLAVE_SSI3_RX, + AUDIO_DMAC_SLAVE_SSI4_TX, + AUDIO_DMAC_SLAVE_SSI4_RX, + AUDIO_DMAC_SLAVE_SSI5_TX, + AUDIO_DMAC_SLAVE_SSI5_RX, + AUDIO_DMAC_SLAVE_SSI6_TX, + AUDIO_DMAC_SLAVE_SSI6_RX, + AUDIO_DMAC_SLAVE_SSI7_TX, + AUDIO_DMAC_SLAVE_SSI7_RX, + AUDIO_DMAC_SLAVE_SSI8_TX, + AUDIO_DMAC_SLAVE_SSI8_RX, + AUDIO_DMAC_SLAVE_SSI9_TX, + AUDIO_DMAC_SLAVE_SSI9_RX, +}; + +void r8a7790_add_standard_devices(void); +void r8a7790_add_dt_devices(void); +void r8a7790_clock_init(void); +void r8a7790_pinmux_init(void); +void r8a7790_pm_init(void); +void r8a7790_init_early(void); +extern struct smp_operations r8a7790_smp_ops; + +#endif /* __ASM_R8A7790_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a7791.h b/arch/arm/mach-shmobile/include/mach/r8a7791.h new file mode 100644 index 00000000000..664274cc4b6 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r8a7791.h @@ -0,0 +1,10 @@ +#ifndef __ASM_R8A7791_H__ +#define __ASM_R8A7791_H__ + +void r8a7791_add_standard_devices(void); +void r8a7791_add_dt_devices(void); +void r8a7791_clock_init(void); +void r8a7791_pinmux_init(void); +extern struct smp_operations r8a7791_smp_ops; + +#endif /* __ASM_R8A7791_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/rcar-gen2.h b/arch/arm/mach-shmobile/include/mach/rcar-gen2.h new file mode 100644 index 00000000000..43f606eb2d8 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/rcar-gen2.h @@ -0,0 +1,8 @@ +#ifndef __ASM_RCAR_GEN2_H__ +#define __ASM_RCAR_GEN2_H__ + +void rcar_gen2_timer_init(void); +#define MD(nr) BIT(nr) +u32 rcar_gen2_read_mode_pins(void); + +#endif /* __ASM_RCAR_GEN2_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/sdhi-sh7372.h b/arch/arm/mach-shmobile/include/mach/sdhi-sh7372.h new file mode 100644 index 00000000000..4a81b01f1e8 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/sdhi-sh7372.h @@ -0,0 +1,21 @@ +#ifndef SDHI_SH7372_H +#define SDHI_SH7372_H + +#define SDGENCNTA 0xfe40009c + +/* The countdown of SDGENCNTA is controlled by + * ZB3D2CLK which runs at 149.5MHz. + * That is 149.5ticks/us. Approximate this as 150ticks/us. + */ +static void udelay(int us) +{ + __raw_writel(us * 150, SDGENCNTA); + while(__raw_readl(SDGENCNTA)) ; +} + +static void msleep(int ms) +{ + udelay(ms * 1000); +} + +#endif diff --git a/arch/arm/mach-shmobile/include/mach/sdhi.h b/arch/arm/mach-shmobile/include/mach/sdhi.h new file mode 100644 index 00000000000..0ec9e69f2c3 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/sdhi.h @@ -0,0 +1,16 @@ +#ifndef SDHI_H +#define SDHI_H + +/************************************************** + * + * CPU specific settings + * + **************************************************/ + +#ifdef CONFIG_ARCH_SH7372 +#include "mach/sdhi-sh7372.h" +#else +#error "unsupported CPU." +#endif + +#endif /* SDHI_H */ diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h new file mode 100644 index 00000000000..854a9f0ca04 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2010 Renesas Solutions Corp. + * + * Kuninori Morimoto <morimoto.kuninori@renesas.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_SH7372_H__ +#define __ASM_SH7372_H__ + +#include <linux/sh_clk.h> +#include <linux/pm_domain.h> +#include <mach/pm-rmobile.h> + +/* DMA slave IDs */ +enum { + SHDMA_SLAVE_INVALID, + SHDMA_SLAVE_SCIF0_TX, + SHDMA_SLAVE_SCIF0_RX, + SHDMA_SLAVE_SCIF1_TX, + SHDMA_SLAVE_SCIF1_RX, + SHDMA_SLAVE_SCIF2_TX, + SHDMA_SLAVE_SCIF2_RX, + SHDMA_SLAVE_SCIF3_TX, + SHDMA_SLAVE_SCIF3_RX, + SHDMA_SLAVE_SCIF4_TX, + SHDMA_SLAVE_SCIF4_RX, + SHDMA_SLAVE_SCIF5_TX, + SHDMA_SLAVE_SCIF5_RX, + SHDMA_SLAVE_SCIF6_TX, + SHDMA_SLAVE_SCIF6_RX, + SHDMA_SLAVE_FLCTL0_TX, + SHDMA_SLAVE_FLCTL0_RX, + SHDMA_SLAVE_FLCTL1_TX, + SHDMA_SLAVE_FLCTL1_RX, + SHDMA_SLAVE_SDHI0_RX, + SHDMA_SLAVE_SDHI0_TX, + SHDMA_SLAVE_SDHI1_RX, + SHDMA_SLAVE_SDHI1_TX, + SHDMA_SLAVE_SDHI2_RX, + SHDMA_SLAVE_SDHI2_TX, + SHDMA_SLAVE_FSIA_RX, + SHDMA_SLAVE_FSIA_TX, + SHDMA_SLAVE_MMCIF_RX, + SHDMA_SLAVE_MMCIF_TX, + SHDMA_SLAVE_USB0_TX, + SHDMA_SLAVE_USB0_RX, + SHDMA_SLAVE_USB1_TX, + SHDMA_SLAVE_USB1_RX, +}; + +extern struct clk sh7372_extal1_clk; +extern struct clk sh7372_extal2_clk; +extern struct clk sh7372_dv_clki_clk; +extern struct clk sh7372_dv_clki_div2_clk; +extern struct clk sh7372_pllc2_clk; + +extern void sh7372_init_irq(void); +extern void sh7372_map_io(void); +extern void sh7372_earlytimer_init(void); +extern void sh7372_add_early_devices(void); +extern void sh7372_add_standard_devices(void); +extern void sh7372_add_early_devices_dt(void); +extern void sh7372_add_standard_devices_dt(void); +extern void sh7372_clock_init(void); +extern void sh7372_pinmux_init(void); +extern void sh7372_pm_init(void); +extern void sh7372_resume_core_standby_sysc(void); +extern int sh7372_do_idle_sysc(unsigned long sleep_mode); +extern void sh7372_intcs_suspend(void); +extern void sh7372_intcs_resume(void); +extern void sh7372_intca_suspend(void); +extern void sh7372_intca_resume(void); + +extern unsigned long sh7372_cpu_resume; + +#ifdef CONFIG_PM +extern void __init sh7372_init_pm_domains(void); +#else +static inline void sh7372_init_pm_domains(void) {} +#endif + +extern void __init sh7372_pm_init_late(void); + +#endif /* __ASM_SH7372_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h new file mode 100644 index 00000000000..359b582dc27 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h @@ -0,0 +1,91 @@ +#ifndef __ASM_SH73A0_H__ +#define __ASM_SH73A0_H__ + +/* DMA slave IDs */ +enum { + SHDMA_SLAVE_INVALID, + SHDMA_SLAVE_SCIF0_TX, + SHDMA_SLAVE_SCIF0_RX, + SHDMA_SLAVE_SCIF1_TX, + SHDMA_SLAVE_SCIF1_RX, + SHDMA_SLAVE_SCIF2_TX, + SHDMA_SLAVE_SCIF2_RX, + SHDMA_SLAVE_SCIF3_TX, + SHDMA_SLAVE_SCIF3_RX, + SHDMA_SLAVE_SCIF4_TX, + SHDMA_SLAVE_SCIF4_RX, + SHDMA_SLAVE_SCIF5_TX, + SHDMA_SLAVE_SCIF5_RX, + SHDMA_SLAVE_SCIF6_TX, + SHDMA_SLAVE_SCIF6_RX, + SHDMA_SLAVE_SCIF7_TX, + SHDMA_SLAVE_SCIF7_RX, + SHDMA_SLAVE_SCIF8_TX, + SHDMA_SLAVE_SCIF8_RX, + SHDMA_SLAVE_SDHI0_TX, + SHDMA_SLAVE_SDHI0_RX, + SHDMA_SLAVE_SDHI1_TX, + SHDMA_SLAVE_SDHI1_RX, + SHDMA_SLAVE_SDHI2_TX, + SHDMA_SLAVE_SDHI2_RX, + SHDMA_SLAVE_MMCIF_TX, + SHDMA_SLAVE_MMCIF_RX, + SHDMA_SLAVE_FSI2A_TX, + SHDMA_SLAVE_FSI2A_RX, + SHDMA_SLAVE_FSI2B_TX, + SHDMA_SLAVE_FSI2B_RX, + SHDMA_SLAVE_FSI2C_TX, + SHDMA_SLAVE_FSI2C_RX, + SHDMA_SLAVE_FSI2D_RX, +}; + +/* + * SH73A0 IRQ LOCATION TABLE + * + * 416 ----------------------------------------- + * IRQ0-IRQ15 + * 431 ----------------------------------------- + * ... + * 448 ----------------------------------------- + * sh73a0-intcs + * sh73a0-intca-irq-pins + * 680 ----------------------------------------- + * ... + * 700 ----------------------------------------- + * sh73a0-pint0 + * 731 ----------------------------------------- + * 732 ----------------------------------------- + * sh73a0-pint1 + * 739 ----------------------------------------- + * ... + * 800 ----------------------------------------- + * IRQ16-IRQ31 + * 815 ----------------------------------------- + * ... + * 928 ----------------------------------------- + * sh73a0-intca-irq-pins + * 943 ----------------------------------------- + */ + +/* PINT interrupts are located at Linux IRQ 700 and up */ +#define SH73A0_PINT0_IRQ(irq) ((irq) + 700) +#define SH73A0_PINT1_IRQ(irq) ((irq) + 732) + +extern void sh73a0_init_delay(void); +extern void sh73a0_init_irq(void); +extern void sh73a0_init_irq_dt(void); +extern void sh73a0_map_io(void); +extern void sh73a0_earlytimer_init(void); +extern void sh73a0_add_early_devices(void); +extern void sh73a0_add_standard_devices(void); +extern void sh73a0_add_standard_devices_dt(void); +extern void sh73a0_clock_init(void); +extern void sh73a0_pinmux_init(void); +extern void sh73a0_pm_init(void); +extern struct clk sh73a0_extal1_clk; +extern struct clk sh73a0_extal2_clk; +extern struct clk sh73a0_extcki_clk; +extern struct clk sh73a0_extalr_clk; +extern struct smp_operations sh73a0_smp_ops; + +#endif /* __ASM_SH73A0_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h new file mode 100644 index 00000000000..540eaff08f3 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/system.h @@ -0,0 +1,11 @@ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include <asm/system_misc.h> + +static inline void arch_reset(char mode, const char *cmd) +{ + soft_restart(0); +} + +#endif diff --git a/arch/arm/mach-shmobile/include/mach/uncompress.h b/arch/arm/mach-shmobile/include/mach/uncompress.h new file mode 100644 index 00000000000..f1aee56781e --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/uncompress.h @@ -0,0 +1,19 @@ +#ifndef __ASM_MACH_UNCOMPRESS_H +#define __ASM_MACH_UNCOMPRESS_H + +/* + * This does not append a newline + */ +static void putc(int c) +{ +} + +static inline void flush(void) +{ +} + +static void arch_decomp_setup(void) +{ +} + +#endif /* __ASM_MACH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h new file mode 100644 index 00000000000..727cc78ac8e --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/zboot.h @@ -0,0 +1,22 @@ +#ifndef ZBOOT_H +#define ZBOOT_H + +#include <mach/zboot_macros.h> + +/************************************************** + * + * board specific settings + * + **************************************************/ + +#ifdef CONFIG_MACH_MACKEREL +#define MEMORY_START 0x40000000 +#include "mach/head-mackerel.txt" +#elif defined(CONFIG_MACH_KZM9G) || defined(CONFIG_MACH_KZM9G_REFERENCE) +#define MEMORY_START 0x43000000 +#include "mach/head-kzm9g.txt" +#else +#error "unsupported board." +#endif + +#endif /* ZBOOT_H */ diff --git a/arch/arm/mach-shmobile/include/mach/zboot_macros.h b/arch/arm/mach-shmobile/include/mach/zboot_macros.h new file mode 100644 index 00000000000..14fd3d538e9 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/zboot_macros.h @@ -0,0 +1,108 @@ +#ifndef __ZBOOT_MACRO_H +#define __ZBOOT_MACRO_H + +/* The LIST command is used to include comments in the script */ +.macro LIST comment +.endm + +/* The ED command is used to write a 32-bit word */ +.macro ED, addr, data + LDR r0, 1f + LDR r1, 2f + STR r1, [r0] + B 3f +1 : .long \addr +2 : .long \data +3 : +.endm + +/* The EW command is used to write a 16-bit word */ +.macro EW, addr, data + LDR r0, 1f + LDR r1, 2f + STRH r1, [r0] + B 3f +1 : .long \addr +2 : .long \data +3 : +.endm + +/* The EB command is used to write an 8-bit word */ +.macro EB, addr, data + LDR r0, 1f + LDR r1, 2f + STRB r1, [r0] + B 3f +1 : .long \addr +2 : .long \data +3 : +.endm + +/* The WAIT command is used to delay the execution */ +.macro WAIT, time, reg + LDR r1, 1f + LDR r0, 2f + STR r0, [r1] +10 : + LDR r0, [r1] + CMP r0, #0x00000000 + BNE 10b + NOP + B 3f +1 : .long \reg +2 : .long \time * 100 +3 : +.endm + +/* The DD command is used to read a 32-bit word */ +.macro DD, start, end + LDR r1, 1f + B 2f +1 : .long \start +2 : +.endm + +/* loop until a given value has been read (with mask) */ +.macro WAIT_MASK, addr, data, cmp + LDR r0, 2f + LDR r1, 3f + LDR r2, 4f +1: + LDR r3, [r0, #0] + AND r3, r1, r3 + CMP r2, r3 + BNE 1b + B 5f +2: .long \addr +3: .long \data +4: .long \cmp +5: +.endm + +/* read 32-bit value from addr, "or" an immediate and write back */ +.macro ED_OR, addr, data + LDR r4, 1f + LDR r5, 2f + LDR r6, [r4] + ORR r5, r6, r5 + STR r5, [r4] + B 3f +1: .long \addr +2: .long \data +3: +.endm + +/* read 32-bit value from addr, "and" an immediate and write back */ +.macro ED_AND, addr, data + LDR r4, 1f + LDR r5, 2f + LDR r6, [r4] + AND r5, r6, r5 + STR r5, [r4] + B 3f +1: .long \addr +2: .long \data +3: +.endm + +#endif /* __ZBOOT_MACRO_H */ |