diff options
Diffstat (limited to 'arch/arm/mach-sa1100')
68 files changed, 3172 insertions, 5540 deletions
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig index f99d9013905..04f9784ff0e 100644 --- a/arch/arm/mach-sa1100/Kconfig +++ b/arch/arm/mach-sa1100/Kconfig @@ -4,6 +4,7 @@ menu "SA11x0 Implementations" config SA1100_ASSABET bool "Assabet" + select ARM_SA1110_CPUFREQ help Say Y here if you are using the Intel(R) StrongARM(R) SA-1110 Microprocessor Development Board (also known as the Assabet). @@ -19,6 +20,7 @@ config ASSABET_NEPONSET config SA1100_CERF bool "CerfBoard" + select ARM_SA1110_CPUFREQ help The Intrinsyc CerfBoard is based on the StrongARM 1110 (Discontinued). More information is available at: @@ -45,49 +47,38 @@ endchoice config SA1100_COLLIE bool "Sharp Zaurus SL5500" + # FIXME: select ARM_SA11x0_CPUFREQ select SHARP_LOCOMO - select SHARP_SCOOP select SHARP_PARAM + select SHARP_SCOOP help Say Y here to support the Sharp Zaurus SL5500 PDAs. config SA1100_H3100 bool "Compaq iPAQ H3100" + select ARM_SA1110_CPUFREQ + select HTC_EGPIO help Say Y here if you intend to run this kernel on the Compaq iPAQ H3100 handheld computer. Information about this machine and the Linux port to this machine can be found at: <http://www.handhelds.org/Compaq/index.html#iPAQ_H3100> - <http://www.compaq.com/products/handhelds/pocketpc/> config SA1100_H3600 bool "Compaq iPAQ H3600/H3700" + select ARM_SA1110_CPUFREQ + select HTC_EGPIO help Say Y here if you intend to run this kernel on the Compaq iPAQ H3600 handheld computer. Information about this machine and the Linux port to this machine can be found at: <http://www.handhelds.org/Compaq/index.html#iPAQ_H3600> - <http://www.compaq.com/products/handhelds/pocketpc/> - -config SA1100_H3800 - bool "Compaq iPAQ H3800" - help - Say Y here if you intend to run this kernel on the Compaq iPAQ H3800 - series handheld computer. Information about this machine and the - Linux port to this machine can be found at: - - <http://www.handhelds.org/Compaq/index.html#iPAQ_H3800> - <http://www.compaq.com/products/handhelds/pocketpc/> - -config SA1100_H3XXX - bool - depends on SA1100_H3100 || SA1100_H3600 || SA1100_H3800 - default y config SA1100_BADGE4 bool "HP Labs BadgePAD 4" + select ARM_SA1100_CPUFREQ select SA1111 help Say Y here if you want to build a kernel for the HP Laboratories @@ -95,16 +86,17 @@ config SA1100_BADGE4 config SA1100_JORNADA720 bool "HP Jornada 720" + # FIXME: select ARM_SA11x0_CPUFREQ select SA1111 help Say Y here if you want to build a kernel for the HP Jornada 720 - handheld computer. See <http://www.hp.com/jornada/products/720> - for details. + handheld computer. See + <http://h10025.www1.hp.com/ewfrf/wc/product?product=61677&cc=us&lc=en&dlc=en&product=61677#> config SA1100_JORNADA720_SSP bool "HP Jornada 720 Extended SSP driver" - select SA1100_SSP depends on SA1100_JORNADA720 + select SA1100_SSP help Say Y here if you have a HP Jornada 7xx handheld computer and you want to access devices connected to the MCU. Those include the @@ -113,19 +105,32 @@ config SA1100_JORNADA720_SSP config SA1100_HACKKIT bool "HackKit Core CPU Board" + select ARM_SA1100_CPUFREQ help Say Y here to support the HackKit Core CPU Board <http://hackkit.eletztrick.de>; config SA1100_LART bool "LART" + select ARM_SA1100_CPUFREQ help Say Y here if you are using the Linux Advanced Radio Terminal (also known as the LART). See <http://www.lartmaker.nl/> for information on the LART. +config SA1100_NANOENGINE + bool "nanoEngine" + select ARM_SA1110_CPUFREQ + select PCI + select PCI_NANOENGINE + help + Say Y here if you are using the Bright Star Engineering nanoEngine. + See <http://www.brightstareng.com/arm/nanoeng.htm> for information + on the BSE nanoEngine. + config SA1100_PLEB bool "PLEB" + select ARM_SA1100_CPUFREQ help Say Y here if you are using version 1 of the Portable Linux Embedded Board (also known as PLEB). @@ -134,6 +139,7 @@ config SA1100_PLEB config SA1100_SHANNON bool "Shannon" + select ARM_SA1100_CPUFREQ help The Shannon (also known as a Tuxscreen, and also as a IS2630) was a limited edition webphone produced by Philips. The Shannon is a SA1100 @@ -142,13 +148,14 @@ config SA1100_SHANNON config SA1100_SIMPAD bool "Simpad" + select ARM_SA1110_CPUFREQ help The SIEMENS webpad SIMpad is based on the StrongARM 1110. There are two different versions CL4 and SL4. CL4 has 32MB RAM and 16MB FLASH. The SL4 version got 64 MB RAM and 32 MB FLASH and a PCMCIA-Slot. The version for the Germany Telecom (DTAG) is the same like CL4 in additional it has a PCMCIA-Slot. For more information - visit <http://www.my-siemens.com/> or <http://www.siemens.ch/>. + visit <http://www.usa.siemens.com/> or <http://www.siemens.ch/>. config SA1100_SSP tristate "Generic PIO SSP" @@ -157,15 +164,7 @@ config SA1100_SSP This isn't for audio support, but for attached sensors and other devices, eg for BadgePAD 4 sensor support. -config H3600_SLEEVE - tristate "Compaq iPAQ Handheld sleeve support" - depends on SA1100_H3100 || SA1100_H3600 - help - Choose this option to enable support for extension packs (sleeves) - for the Compaq iPAQ H3XXX series of handheld computers. This option - is required for the CF, PCMCIA, Bluetooth and GSM/GPRS extension - packs. - endmenu endif + diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile index 8a5546e6d54..2732eef4896 100644 --- a/arch/arm/mach-sa1100/Makefile +++ b/arch/arm/mach-sa1100/Makefile @@ -3,50 +3,41 @@ # # Common support -obj-y := clock.o generic.o gpio.o irq.o dma.o time.o #nmi-oopser.o +obj-y := clock.o generic.o irq.o time.o #nmi-oopser.o obj-m := obj-n := obj- := -led-y := leds.o - -obj-$(CONFIG_CPU_FREQ_SA1100) += cpu-sa1100.o -obj-$(CONFIG_CPU_FREQ_SA1110) += cpu-sa1110.o # Specific board support obj-$(CONFIG_SA1100_ASSABET) += assabet.o -led-$(CONFIG_SA1100_ASSABET) += leds-assabet.o obj-$(CONFIG_ASSABET_NEPONSET) += neponset.o obj-$(CONFIG_SA1100_BADGE4) += badge4.o -led-$(CONFIG_SA1100_BADGE4) += leds-badge4.o obj-$(CONFIG_SA1100_CERF) += cerf.o -led-$(CONFIG_SA1100_CERF) += leds-cerf.o obj-$(CONFIG_SA1100_COLLIE) += collie.o -obj-$(CONFIG_SA1100_H3600) += h3600.o +obj-$(CONFIG_SA1100_H3100) += h3100.o h3xxx.o +obj-$(CONFIG_SA1100_H3600) += h3600.o h3xxx.o obj-$(CONFIG_SA1100_HACKKIT) += hackkit.o -led-$(CONFIG_SA1100_HACKKIT) += leds-hackkit.o obj-$(CONFIG_SA1100_JORNADA720) += jornada720.o obj-$(CONFIG_SA1100_JORNADA720_SSP) += jornada720_ssp.o obj-$(CONFIG_SA1100_LART) += lart.o -led-$(CONFIG_SA1100_LART) += leds-lart.o + +obj-$(CONFIG_SA1100_NANOENGINE) += nanoengine.o +obj-$(CONFIG_PCI_NANOENGINE) += pci-nanoengine.o obj-$(CONFIG_SA1100_PLEB) += pleb.o obj-$(CONFIG_SA1100_SHANNON) += shannon.o obj-$(CONFIG_SA1100_SIMPAD) += simpad.o -led-$(CONFIG_SA1100_SIMPAD) += leds-simpad.o - -# LEDs support -obj-$(CONFIG_LEDS) += $(led-y) -# Miscelaneous functions +# Miscellaneous functions obj-$(CONFIG_PM) += pm.o sleep.o obj-$(CONFIG_SA1100_SSP) += ssp.o diff --git a/arch/arm/mach-sa1100/Makefile.boot b/arch/arm/mach-sa1100/Makefile.boot index a56ad0417cf..f7951aa0456 100644 --- a/arch/arm/mach-sa1100/Makefile.boot +++ b/arch/arm/mach-sa1100/Makefile.boot @@ -1,6 +1,7 @@ - zreladdr-y := 0xc0008000 -ifeq ($(CONFIG_ARCH_SA1100),y) - zreladdr-$(CONFIG_SA1111) := 0xc0208000 +ifeq ($(CONFIG_SA1111),y) + zreladdr-y += 0xc0208000 +else + zreladdr-y += 0xc0008000 endif params_phys-y := 0xc0000100 initrd_phys-y := 0xc0800000 diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index 55e64477a87..7dd894ece9a 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c @@ -14,15 +14,21 @@ #include <linux/module.h> #include <linux/errno.h> #include <linux/ioport.h> +#include <linux/platform_data/sa11x0-serial.h> #include <linux/serial_core.h> +#include <linux/platform_device.h> +#include <linux/mfd/ucb1x00.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/delay.h> #include <linux/mm.h> +#include <linux/leds.h> +#include <linux/slab.h> + +#include <video/sa1100fb.h> #include <mach/hardware.h> #include <asm/mach-types.h> -#include <asm/irq.h> #include <asm/setup.h> #include <asm/page.h> #include <asm/pgtable-hwdef.h> @@ -33,20 +39,20 @@ #include <asm/mach/flash.h> #include <asm/mach/irda.h> #include <asm/mach/map.h> -#include <asm/mach/serial_sa1100.h> #include <mach/assabet.h> -#include <mach/mcp.h> +#include <linux/platform_data/mfd-mcp-sa11x0.h> +#include <mach/irqs.h> #include "generic.h" #define ASSABET_BCR_DB1110 \ - (ASSABET_BCR_SPK_OFF | ASSABET_BCR_QMUTE | \ + (ASSABET_BCR_SPK_OFF | \ ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \ ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \ ASSABET_BCR_IRDA_MD0) #define ASSABET_BCR_DB1111 \ - (ASSABET_BCR_SPK_OFF | ASSABET_BCR_QMUTE | \ + (ASSABET_BCR_SPK_OFF | \ ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \ ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \ ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \ @@ -69,33 +75,143 @@ void ASSABET_BCR_frob(unsigned int mask, unsigned int val) EXPORT_SYMBOL(ASSABET_BCR_frob); -static void assabet_backlight_power(int on) +/* + * The codec reset goes to three devices, so we need to release + * the rest when any one of these requests it. However, that + * causes the ADV7171 to consume around 100mA - more than half + * the LCD-blanked power. + * + * With the ADV7171, LCD and backlight enabled, we go over + * budget on the MAX846 Li-Ion charger, and if no Li-Ion battery + * is connected, the Assabet crashes. + */ +#define RST_UCB1X00 (1 << 0) +#define RST_UDA1341 (1 << 1) +#define RST_ADV7171 (1 << 2) + +#define SDA GPIO_GPIO(15) +#define SCK GPIO_GPIO(18) +#define MOD GPIO_GPIO(17) + +static void adv7171_start(void) { -#ifndef ASSABET_PAL_VIDEO - if (on) - ASSABET_BCR_set(ASSABET_BCR_LIGHT_ON); + GPSR = SCK; + udelay(1); + GPSR = SDA; + udelay(2); + GPCR = SDA; +} + +static void adv7171_stop(void) +{ + GPSR = SCK; + udelay(2); + GPSR = SDA; + udelay(1); +} + +static void adv7171_send(unsigned byte) +{ + unsigned i; + + for (i = 0; i < 8; i++, byte <<= 1) { + GPCR = SCK; + udelay(1); + if (byte & 0x80) + GPSR = SDA; + else + GPCR = SDA; + udelay(1); + GPSR = SCK; + udelay(1); + } + GPCR = SCK; + udelay(1); + GPSR = SDA; + udelay(1); + GPDR &= ~SDA; + GPSR = SCK; + udelay(1); + if (GPLR & SDA) + printk(KERN_WARNING "No ACK from ADV7171\n"); + udelay(1); + GPCR = SCK | SDA; + udelay(1); + GPDR |= SDA; + udelay(1); +} + +static void adv7171_write(unsigned reg, unsigned val) +{ + unsigned gpdr = GPDR; + unsigned gplr = GPLR; + + ASSABET_BCR = BCR_value | ASSABET_BCR_AUDIO_ON; + udelay(100); + + GPCR = SDA | SCK | MOD; /* clear L3 mode to ensure UDA1341 doesn't respond */ + GPDR = (GPDR | SCK | MOD) & ~SDA; + udelay(10); + if (!(GPLR & SDA)) + printk(KERN_WARNING "Something dragging SDA down?\n"); + GPDR |= SDA; + + adv7171_start(); + adv7171_send(0x54); + adv7171_send(reg); + adv7171_send(val); + adv7171_stop(); + + /* Restore GPIO state for L3 bus */ + GPSR = gplr & (SDA | SCK | MOD); + GPCR = (~gplr) & (SDA | SCK | MOD); + GPDR = gpdr; +} + +static void adv7171_sleep(void) +{ + /* Put the ADV7171 into sleep mode */ + adv7171_write(0x04, 0x40); +} + +static unsigned codec_nreset; + +static void assabet_codec_reset(unsigned mask, int set) +{ + unsigned long flags; + bool old; + + local_irq_save(flags); + old = !codec_nreset; + if (set) + codec_nreset &= ~mask; else -#endif - ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON); + codec_nreset |= mask; + + if (old != !codec_nreset) { + if (codec_nreset) { + ASSABET_BCR_set(ASSABET_BCR_NCODEC_RST); + adv7171_sleep(); + } else { + ASSABET_BCR_clear(ASSABET_BCR_NCODEC_RST); + } + } + local_irq_restore(flags); } -/* - * Turn on/off the backlight. When turning the backlight on, - * we wait 500us after turning it on so we don't cause the - * supplies to droop when we enable the LCD controller (and - * cause a hard reset.) - */ -static void assabet_lcd_power(int on) +static void assabet_ucb1x00_reset(enum ucb1x00_reset state) { -#ifndef ASSABET_PAL_VIDEO - if (on) { - ASSABET_BCR_set(ASSABET_BCR_LCD_ON); - udelay(500); - } else -#endif - ASSABET_BCR_clear(ASSABET_BCR_LCD_ON); + int set = state == UCB_RST_REMOVE || state == UCB_RST_SUSPEND || + state == UCB_RST_PROBE_FAIL; + assabet_codec_reset(RST_UCB1X00, set); } +void assabet_uda1341_reset(int set) +{ + assabet_codec_reset(RST_UDA1341, set); +} +EXPORT_SYMBOL(assabet_uda1341_reset); + /* * Assabet flash support code. @@ -152,15 +268,8 @@ static struct flash_platform_data assabet_flash_data = { }; static struct resource assabet_flash_resources[] = { - { - .start = SA1100_CS0_PHYS, - .end = SA1100_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = SA1100_CS1_PHYS, - .end = SA1100_CS1_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, - } + DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M), + DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M), }; @@ -177,12 +286,9 @@ static int assabet_irda_set_power(struct device *dev, unsigned int state) 0 }; - if (state < 4) { - state = bcr_state[state]; - ASSABET_BCR_clear(state ^ (ASSABET_BCR_IRDA_MD1| - ASSABET_BCR_IRDA_MD0)); - ASSABET_BCR_set(state); - } + if (state < 4) + ASSABET_BCR_frob(ASSABET_BCR_IRDA_MD1 | ASSABET_BCR_IRDA_MD0, + bcr_state[state]); return 0; } @@ -199,18 +305,127 @@ static struct irda_platform_data assabet_irda_data = { .set_speed = assabet_irda_set_speed, }; +static struct ucb1x00_plat_data assabet_ucb1x00_data = { + .reset = assabet_ucb1x00_reset, + .gpio_base = -1, + .can_wakeup = 1, +}; + static struct mcp_plat_data assabet_mcp_data = { .mccr0 = MCCR0_ADM, .sclk_rate = 11981000, + .codec_pdata = &assabet_ucb1x00_data, }; +static void assabet_lcd_set_visual(u32 visual) +{ + u_int is_true_color = visual == FB_VISUAL_TRUECOLOR; + + if (machine_is_assabet()) { +#if 1 // phase 4 or newer Assabet's + if (is_true_color) + ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB); + else + ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB); +#else + // older Assabet's + if (is_true_color) + ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB); + else + ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB); +#endif + } +} + +#ifndef ASSABET_PAL_VIDEO +static void assabet_lcd_backlight_power(int on) +{ + if (on) + ASSABET_BCR_set(ASSABET_BCR_LIGHT_ON); + else + ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON); +} + +/* + * Turn on/off the backlight. When turning the backlight on, we wait + * 500us after turning it on so we don't cause the supplies to droop + * when we enable the LCD controller (and cause a hard reset.) + */ +static void assabet_lcd_power(int on) +{ + if (on) { + ASSABET_BCR_set(ASSABET_BCR_LCD_ON); + udelay(500); + } else + ASSABET_BCR_clear(ASSABET_BCR_LCD_ON); +} + +/* + * The assabet uses a sharp LQ039Q2DS54 LCD module. It is actually + * takes an RGB666 signal, but we provide it with an RGB565 signal + * instead (def_rgb_16). + */ +static struct sa1100fb_mach_info lq039q2ds54_info = { + .pixclock = 171521, .bpp = 16, + .xres = 320, .yres = 240, + + .hsync_len = 5, .vsync_len = 1, + .left_margin = 61, .upper_margin = 3, + .right_margin = 9, .lower_margin = 0, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + + .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act, + .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2), + + .backlight_power = assabet_lcd_backlight_power, + .lcd_power = assabet_lcd_power, + .set_visual = assabet_lcd_set_visual, +}; +#else +static void assabet_pal_backlight_power(int on) +{ + ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON); +} + +static void assabet_pal_power(int on) +{ + ASSABET_BCR_clear(ASSABET_BCR_LCD_ON); +} + +static struct sa1100fb_mach_info pal_info = { + .pixclock = 67797, .bpp = 16, + .xres = 640, .yres = 512, + + .hsync_len = 64, .vsync_len = 6, + .left_margin = 125, .upper_margin = 70, + .right_margin = 115, .lower_margin = 36, + + .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act, + .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512), + + .backlight_power = assabet_pal_backlight_power, + .lcd_power = assabet_pal_power, + .set_visual = assabet_lcd_set_visual, +}; +#endif + +#ifdef CONFIG_ASSABET_NEPONSET +static struct resource neponset_resources[] = { + DEFINE_RES_MEM(0x10000000, 0x08000000), + DEFINE_RES_MEM(0x18000000, 0x04000000), + DEFINE_RES_MEM(0x40000000, SZ_8K), + DEFINE_RES_IRQ(IRQ_GPIO25), +}; +#endif + static void __init assabet_init(void) { /* * Ensure that the power supply is in "high power" mode. */ - GPDR |= GPIO_GPIO16; GPSR = GPIO_GPIO16; + GPDR |= GPIO_GPIO16; /* * Ensure that these pins are set as outputs and are driving @@ -218,8 +433,16 @@ static void __init assabet_init(void) * the WS latch in the CPLD, and we don't float causing * excessive power drain. --rmk */ - GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM; GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM; + GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM; + + /* + * Also set GPIO27 as an output; this is used to clock UART3 + * via the FPGA and as otherwise has no pullups or pulldowns, + * so stop it floating. + */ + GPCR = GPIO_GPIO27; + GPDR |= GPIO_GPIO27; /* * Set up registers for sleep mode. @@ -231,8 +454,7 @@ static void __init assabet_init(void) PPDR |= PPC_TXD3 | PPC_TXD1; PPSR |= PPC_TXD3 | PPC_TXD1; - sa1100fb_lcd_power = assabet_lcd_power; - sa1100fb_backlight_power = assabet_backlight_power; + sa11x0_ppc_configure_mcp(); if (machine_has_neponset()) { /* @@ -246,13 +468,21 @@ static void __init assabet_init(void) #ifndef CONFIG_ASSABET_NEPONSET printk( "Warning: Neponset detected but full support " "hasn't been configured in the kernel\n" ); +#else + platform_device_register_simple("neponset", 0, + neponset_resources, ARRAY_SIZE(neponset_resources)); #endif } - sa11x0_set_flash_data(&assabet_flash_data, assabet_flash_resources, - ARRAY_SIZE(assabet_flash_resources)); - sa11x0_set_irda_data(&assabet_irda_data); - sa11x0_set_mcp_data(&assabet_mcp_data); +#ifndef ASSABET_PAL_VIDEO + sa11x0_register_lcd(&lq039q2ds54_info); +#else + sa11x0_register_lcd(&pal_video); +#endif + sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources, + ARRAY_SIZE(assabet_flash_resources)); + sa11x0_register_irda(&assabet_irda_data); + sa11x0_register_mcp(&assabet_mcp_data); } /* @@ -264,11 +494,11 @@ static void __init assabet_init(void) static void __init map_sa1100_gpio_regs( void ) { unsigned long phys = __PREG(GPLR) & PMD_MASK; - unsigned long virt = io_p2v(phys); + unsigned long virt = (unsigned long)io_p2v(phys); int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO); pmd_t *pmd; - pmd = pmd_offset(pgd_offset_k(virt), virt); + pmd = pmd_offset(pud_offset(pgd_offset_k(virt), virt), virt); *pmd = __pmd(phys | prot); flush_pmd_entry(pmd); } @@ -288,7 +518,7 @@ static void __init map_sa1100_gpio_regs( void ) */ static void __init get_assabet_scr(void) { - unsigned long scr, i; + unsigned long uninitialized_var(scr), i; GPDR |= 0x3fc; /* Configure GPIO 9:2 as outputs */ GPSR = 0x3fc; /* Write 0xFF to GPIO 9:2 */ @@ -301,8 +531,7 @@ static void __init get_assabet_scr(void) } static void __init -fixup_assabet(struct machine_desc *desc, struct tag *tags, - char **cmdline, struct meminfo *mi) +fixup_assabet(struct tag *tags, char **cmdline) { /* This must be done before any call to machine_has_neponset() */ map_sa1100_gpio_regs(); @@ -412,22 +641,12 @@ static void __init assabet_map_io(void) * Its called GPCLKR0 in my SA1110 manual. */ Ser1SDCR0 |= SDCR0_SUS; + MSC1 = (MSC1 & ~0xffff) | + MSC_NonBrst | MSC_32BitStMem | + MSC_RdAcc(2) | MSC_WrAcc(2) | MSC_Rec(0); - if (machine_has_neponset()) { -#ifdef CONFIG_ASSABET_NEPONSET - extern void neponset_map_io(void); - - /* - * We map Neponset registers even if it isn't present since - * many drivers will try to probe their stuff (and fail). - * This is still more friendly than a kernel paging request - * crash. - */ - neponset_map_io(); -#endif - } else { + if (!machine_has_neponset()) sa1100_register_uart_fns(&assabet_port_fns); - } /* * When Neponset is attached, the first UART should be @@ -445,14 +664,101 @@ static void __init assabet_map_io(void) sa1100_register_uart(2, 3); } +/* LEDs */ +#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS) +struct assabet_led { + struct led_classdev cdev; + u32 mask; +}; + +/* + * The triggers lines up below will only be used if the + * LED triggers are compiled in. + */ +static const struct { + const char *name; + const char *trigger; +} assabet_leds[] = { + { "assabet:red", "cpu0",}, + { "assabet:green", "heartbeat", }, +}; + +/* + * The LED control in Assabet is reversed: + * - setting bit means turn off LED + * - clearing bit means turn on LED + */ +static void assabet_led_set(struct led_classdev *cdev, + enum led_brightness b) +{ + struct assabet_led *led = container_of(cdev, + struct assabet_led, cdev); + + if (b != LED_OFF) + ASSABET_BCR_clear(led->mask); + else + ASSABET_BCR_set(led->mask); +} + +static enum led_brightness assabet_led_get(struct led_classdev *cdev) +{ + struct assabet_led *led = container_of(cdev, + struct assabet_led, cdev); + + return (ASSABET_BCR & led->mask) ? LED_OFF : LED_FULL; +} + +static int __init assabet_leds_init(void) +{ + int i; + + if (!machine_is_assabet()) + return -ENODEV; + + for (i = 0; i < ARRAY_SIZE(assabet_leds); i++) { + struct assabet_led *led; + + led = kzalloc(sizeof(*led), GFP_KERNEL); + if (!led) + break; + + led->cdev.name = assabet_leds[i].name; + led->cdev.brightness_set = assabet_led_set; + led->cdev.brightness_get = assabet_led_get; + led->cdev.default_trigger = assabet_leds[i].trigger; + + if (!i) + led->mask = ASSABET_BCR_LED_RED; + else + led->mask = ASSABET_BCR_LED_GREEN; + + if (led_classdev_register(NULL, &led->cdev) < 0) { + kfree(led); + break; + } + } + + return 0; +} + +/* + * Since we may have triggers on any subsystem, defer registration + * until after subsystem_init. + */ +fs_initcall(assabet_leds_init); +#endif MACHINE_START(ASSABET, "Intel-Assabet") - .phys_io = 0x80000000, - .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc, - .boot_params = 0xc0000100, + .atag_offset = 0x100, .fixup = fixup_assabet, .map_io = assabet_map_io, + .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = assabet_init, + .init_late = sa11x0_init_late, +#ifdef CONFIG_SA1111 + .dma_zone_size = SZ_1M, +#endif + .restart = sa11x0_restart, MACHINE_END diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c index ab5883b39dd..63361b6d04e 100644 --- a/arch/arm/mach-sa1100/badge4.c +++ b/arch/arm/mach-sa1100/badge4.c @@ -16,12 +16,15 @@ #include <linux/module.h> #include <linux/init.h> #include <linux/kernel.h> +#include <linux/platform_data/sa11x0-serial.h> #include <linux/platform_device.h> #include <linux/delay.h> #include <linux/tty.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/errno.h> +#include <linux/gpio.h> +#include <linux/leds.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -32,23 +35,33 @@ #include <asm/mach/flash.h> #include <asm/mach/map.h> #include <asm/hardware/sa1111.h> -#include <asm/mach/serial_sa1100.h> #include <mach/badge4.h> #include "generic.h" static struct resource sa1111_resources[] = { - [0] = { - .start = BADGE4_SA1111_BASE, - .end = BADGE4_SA1111_BASE + 0x00001fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = BADGE4_IRQ_GPIO_SA1111, - .end = BADGE4_IRQ_GPIO_SA1111, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(BADGE4_SA1111_BASE, 0x2000), + [1] = DEFINE_RES_IRQ(BADGE4_IRQ_GPIO_SA1111), +}; + +static int badge4_sa1111_enable(void *data, unsigned devid) +{ + if (devid == SA1111_DEVID_USB) + badge4_set_5V(BADGE4_5V_USB, 1); + return 0; +} + +static void badge4_sa1111_disable(void *data, unsigned devid) +{ + if (devid == SA1111_DEVID_USB) + badge4_set_5V(BADGE4_5V_USB, 0); +} + +static struct sa1111_platform_data sa1111_info = { + .disable_devs = SA1111_DEVID_PS2_MSE, + .enable = badge4_sa1111_enable, + .disable = badge4_sa1111_disable, }; static u64 sa1111_dmamask = 0xffffffffUL; @@ -59,13 +72,42 @@ static struct platform_device sa1111_device = { .dev = { .dma_mask = &sa1111_dmamask, .coherent_dma_mask = 0xffffffff, + .platform_data = &sa1111_info, }, .num_resources = ARRAY_SIZE(sa1111_resources), .resource = sa1111_resources, }; +/* LEDs */ +struct gpio_led badge4_gpio_leds[] = { + { + .name = "badge4:red", + .default_trigger = "heartbeat", + .gpio = 7, + }, + { + .name = "badge4:green", + .default_trigger = "cpu0", + .gpio = 9, + }, +}; + +static struct gpio_led_platform_data badge4_gpio_led_info = { + .leds = badge4_gpio_leds, + .num_leds = ARRAY_SIZE(badge4_gpio_leds), +}; + +static struct platform_device badge4_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &badge4_gpio_led_info, + } +}; + static struct platform_device *devices[] __initdata = { &sa1111_device, + &badge4_leds, }; static int __init badge4_sa1111_init(void) @@ -116,11 +158,8 @@ static struct flash_platform_data badge4_flash_data = { .nr_parts = ARRAY_SIZE(badge4_partitions), }; -static struct resource badge4_flash_resource = { - .start = SA1100_CS0_PHYS, - .end = SA1100_CS0_PHYS + SZ_64M - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource badge4_flash_resource = + DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_64M); static int five_v_on __initdata = 0; @@ -212,7 +251,7 @@ static int __init badge4_init(void) /* maybe turn on 5v0 from the start */ badge4_set_5V(BADGE4_5V_INITIALLY, five_v_on); - sa11x0_set_flash_data(&badge4_flash_data, &badge4_flash_resource, 1); + sa11x0_register_mtd(&badge4_flash_data, &badge4_flash_resource, 1); return 0; } @@ -264,11 +303,6 @@ static struct map_desc badge4_io_desc[] __initdata = { .pfn = __phys_to_pfn(0x10000000), .length = 0x00100000, .type = MT_DEVICE - }, { /* SA-1111 */ - .virtual = 0xf4000000, - .pfn = __phys_to_pfn(0x48000000), - .length = 0x00100000, - .type = MT_DEVICE } }; @@ -297,10 +331,14 @@ static void __init badge4_map_io(void) } MACHINE_START(BADGE4, "Hewlett-Packard Laboratories BadgePAD 4") - .phys_io = 0x80000000, - .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc, - .boot_params = 0xc0000100, + .atag_offset = 0x100, .map_io = badge4_map_io, + .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_late = sa11x0_init_late, + .init_time = sa1100_timer_init, +#ifdef CONFIG_SA1111 + .dma_zone_size = SZ_1M, +#endif + .restart = sa11x0_restart, MACHINE_END diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c index fd3ad9cfc91..2d25ececb41 100644 --- a/arch/arm/mach-sa1100/cerf.c +++ b/arch/arm/mach-sa1100/cerf.c @@ -13,12 +13,14 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/tty.h> +#include <linux/platform_data/sa11x0-serial.h> #include <linux/platform_device.h> #include <linux/irq.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <linux/gpio.h> +#include <linux/leds.h> -#include <asm/irq.h> #include <mach/hardware.h> #include <asm/setup.h> @@ -26,18 +28,14 @@ #include <asm/mach/arch.h> #include <asm/mach/flash.h> #include <asm/mach/map.h> -#include <asm/mach/serial_sa1100.h> #include <mach/cerf.h> -#include <mach/mcp.h> +#include <linux/platform_data/mfd-mcp-sa11x0.h> +#include <mach/irqs.h> #include "generic.h" static struct resource cerfuart2_resources[] = { - [0] = { - .start = 0x80030000, - .end = 0x8003ffff, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM(0x80030000, SZ_64K), }; static struct platform_device cerfuart2_device = { @@ -47,8 +45,48 @@ static struct platform_device cerfuart2_device = { .resource = cerfuart2_resources, }; +/* LEDs */ +struct gpio_led cerf_gpio_leds[] = { + { + .name = "cerf:d0", + .default_trigger = "heartbeat", + .gpio = 0, + }, + { + .name = "cerf:d1", + .default_trigger = "cpu0", + .gpio = 1, + }, + { + .name = "cerf:d2", + .default_trigger = "default-on", + .gpio = 2, + }, + { + .name = "cerf:d3", + .default_trigger = "default-on", + .gpio = 3, + }, + +}; + +static struct gpio_led_platform_data cerf_gpio_led_info = { + .leds = cerf_gpio_leds, + .num_leds = ARRAY_SIZE(cerf_gpio_leds), +}; + +static struct platform_device cerf_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &cerf_gpio_led_info, + } +}; + + static struct platform_device *cerf_devices[] __initdata = { &cerfuart2_device, + &cerf_leds, }; #ifdef CONFIG_SA1100_CERF_FLASH_32MB @@ -87,16 +125,13 @@ static struct flash_platform_data cerf_flash_data = { .nr_parts = ARRAY_SIZE(cerf_partitions), }; -static struct resource cerf_flash_resource = { - .start = SA1100_CS0_PHYS, - .end = SA1100_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource cerf_flash_resource = + DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); static void __init cerf_init_irq(void) { sa1100_init_irq(); - set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING); } static struct map_desc cerf_io_desc[] __initdata = { @@ -128,17 +163,19 @@ static struct mcp_plat_data cerf_mcp_data = { static void __init cerf_init(void) { + sa11x0_ppc_configure_mcp(); platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices)); - sa11x0_set_flash_data(&cerf_flash_data, &cerf_flash_resource, 1); - sa11x0_set_mcp_data(&cerf_mcp_data); + sa11x0_register_mtd(&cerf_flash_data, &cerf_flash_resource, 1); + sa11x0_register_mcp(&cerf_mcp_data); } MACHINE_START(CERF, "Intrinsyc CerfBoard/CerfCube") /* Maintainer: support@intrinsyc.com */ - .phys_io = 0x80000000, - .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc, .map_io = cerf_map_io, + .nr_irqs = SA1100_NR_IRQS, .init_irq = cerf_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = cerf_init, + .init_late = sa11x0_init_late, + .restart = sa11x0_restart, MACHINE_END diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c index dab3c6347a8..9fa6a990cf0 100644 --- a/arch/arm/mach-sa1100/clock.c +++ b/arch/arm/mach-sa1100/clock.c @@ -11,17 +11,36 @@ #include <linux/clk.h> #include <linux/spinlock.h> #include <linux/mutex.h> +#include <linux/io.h> +#include <linux/clkdev.h> #include <mach/hardware.h> -/* - * Very simple clock implementation - we only have one clock to deal with. - */ +struct clkops { + void (*enable)(struct clk *); + void (*disable)(struct clk *); +}; + struct clk { + const struct clkops *ops; unsigned int enabled; }; -static void clk_gpio27_enable(void) +#define DEFINE_CLK(_name, _ops) \ +struct clk clk_##_name = { \ + .ops = _ops, \ + } + +static DEFINE_SPINLOCK(clocks_lock); + +/* Dummy clk routine to build generic kernel parts that may be using them */ +unsigned long clk_get_rate(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_get_rate); + +static void clk_gpio27_enable(struct clk *clk) { /* * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: @@ -32,38 +51,24 @@ static void clk_gpio27_enable(void) TUCR = TUCR_3_6864MHz; } -static void clk_gpio27_disable(void) +static void clk_gpio27_disable(struct clk *clk) { TUCR = 0; GPDR &= ~GPIO_32_768kHz; GAFR &= ~GPIO_32_768kHz; } -static struct clk clk_gpio27; - -static DEFINE_SPINLOCK(clocks_lock); - -struct clk *clk_get(struct device *dev, const char *id) -{ - const char *devname = dev_name(dev); - - return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27; -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); - int clk_enable(struct clk *clk) { unsigned long flags; - spin_lock_irqsave(&clocks_lock, flags); - if (clk->enabled++ == 0) - clk_gpio27_enable(); - spin_unlock_irqrestore(&clocks_lock, flags); + if (clk) { + spin_lock_irqsave(&clocks_lock, flags); + if (clk->enabled++ == 0) + clk->ops->enable(clk); + spin_unlock_irqrestore(&clocks_lock, flags); + } + return 0; } EXPORT_SYMBOL(clk_enable); @@ -72,17 +77,31 @@ void clk_disable(struct clk *clk) { unsigned long flags; - WARN_ON(clk->enabled == 0); - - spin_lock_irqsave(&clocks_lock, flags); - if (--clk->enabled == 0) - clk_gpio27_disable(); - spin_unlock_irqrestore(&clocks_lock, flags); + if (clk) { + WARN_ON(clk->enabled == 0); + spin_lock_irqsave(&clocks_lock, flags); + if (--clk->enabled == 0) + clk->ops->disable(clk); + spin_unlock_irqrestore(&clocks_lock, flags); + } } EXPORT_SYMBOL(clk_disable); -unsigned long clk_get_rate(struct clk *clk) +const struct clkops clk_gpio27_ops = { + .enable = clk_gpio27_enable, + .disable = clk_gpio27_disable, +}; + +static DEFINE_CLK(gpio27, &clk_gpio27_ops); + +static struct clk_lookup sa11xx_clkregs[] = { + CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27), + CLKDEV_INIT("sa1100-rtc", NULL, NULL), +}; + +static int __init sa11xx_clk_init(void) { - return 3686400; + clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs)); + return 0; } -EXPORT_SYMBOL(clk_get_rate); +core_initcall(sa11xx_clk_init); diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index 2052eb88c96..108939f8d05 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c @@ -11,7 +11,7 @@ * published by the Free Software Foundation. * * ChangeLog: - * 2006 Pavel Machek <pavel@suse.cz> + * 2006 Pavel Machek <pavel@ucw.cz> * 03-06-2004 John Lenz <lenz@cs.wisc.edu> * 06-04-2002 Chris Larson <kergoth@digitalnemesis.net> * 04-16-2001 Lineo Japan,Inc. ... @@ -21,40 +21,46 @@ #include <linux/kernel.h> #include <linux/tty.h> #include <linux/delay.h> +#include <linux/platform_data/sa11x0-serial.h> #include <linux/platform_device.h> +#include <linux/mfd/ucb1x00.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/timer.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/gpio.h> +#include <linux/pda_power.h> + +#include <video/sa1100fb.h> #include <mach/hardware.h> #include <asm/mach-types.h> -#include <asm/irq.h> +#include <asm/page.h> #include <asm/setup.h> #include <mach/collie.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> #include <asm/mach/map.h> -#include <asm/mach/serial_sa1100.h> +#include <asm/mach/irda.h> #include <asm/hardware/scoop.h> #include <asm/mach/sharpsl_param.h> #include <asm/hardware/locomo.h> -#include <mach/mcp.h> +#include <linux/platform_data/mfd-mcp-sa11x0.h> +#include <mach/irqs.h> #include "generic.h" static struct resource collie_scoop_resources[] = { - [0] = { - .start = 0x40800000, - .end = 0x40800fff, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM(0x40800000, SZ_4K), }; static struct scoop_config collie_scoop_setup = { .io_dir = COLLIE_SCOOP_IO_DIR, .io_out = COLLIE_SCOOP_IO_OUT, + .gpio_base = COLLIE_SCOOP_GPIO_BASE, }; struct platform_device colliescoop_device = { @@ -81,9 +87,106 @@ static struct scoop_pcmcia_config collie_pcmcia_config = { .num_devs = 1, }; +static struct ucb1x00_plat_data collie_ucb1x00_data = { + .gpio_base = COLLIE_TC35143_GPIO_BASE, +}; + static struct mcp_plat_data collie_mcp_data = { .mccr0 = MCCR0_ADM | MCCR0_ExtClk, .sclk_rate = 9216000, + .codec_pdata = &collie_ucb1x00_data, +}; + +static int collie_ir_startup(struct device *dev) +{ + int rc = gpio_request(COLLIE_GPIO_IR_ON, "IrDA"); + if (rc) + return rc; + rc = gpio_direction_output(COLLIE_GPIO_IR_ON, 1); + + if (!rc) + return 0; + + gpio_free(COLLIE_GPIO_IR_ON); + return rc; +} + +static void collie_ir_shutdown(struct device *dev) +{ + gpio_free(COLLIE_GPIO_IR_ON); +} + +static int collie_ir_set_power(struct device *dev, unsigned int state) +{ + gpio_set_value(COLLIE_GPIO_IR_ON, !state); + return 0; +} + +static struct irda_platform_data collie_ir_data = { + .startup = collie_ir_startup, + .shutdown = collie_ir_shutdown, + .set_power = collie_ir_set_power, +}; + +/* + * Collie AC IN + */ +static int collie_power_init(struct device *dev) +{ + int ret = gpio_request(COLLIE_GPIO_AC_IN, "ac in"); + if (ret) + goto err_gpio_req; + + ret = gpio_direction_input(COLLIE_GPIO_AC_IN); + if (ret) + goto err_gpio_in; + + return 0; + +err_gpio_in: + gpio_free(COLLIE_GPIO_AC_IN); +err_gpio_req: + return ret; +} + +static void collie_power_exit(struct device *dev) +{ + gpio_free(COLLIE_GPIO_AC_IN); +} + +static int collie_power_ac_online(void) +{ + return gpio_get_value(COLLIE_GPIO_AC_IN) == 2; +} + +static char *collie_ac_supplied_to[] = { + "main-battery", + "backup-battery", +}; + +static struct pda_power_pdata collie_power_data = { + .init = collie_power_init, + .is_ac_online = collie_power_ac_online, + .exit = collie_power_exit, + .supplied_to = collie_ac_supplied_to, + .num_supplicants = ARRAY_SIZE(collie_ac_supplied_to), +}; + +static struct resource collie_power_resource[] = { + { + .name = "ac", + .flags = IORESOURCE_IRQ | + IORESOURCE_IRQ_HIGHEDGE | + IORESOURCE_IRQ_LOWEDGE, + }, +}; + +static struct platform_device collie_power_device = { + .name = "pda-power", + .id = -1, + .dev.platform_data = &collie_power_data, + .resource = collie_power_resource, + .num_resources = ARRAY_SIZE(collie_power_resource), }; #ifdef CONFIG_SHARP_LOCOMO @@ -145,7 +248,8 @@ static struct locomo_driver collie_uart_driver = { .remove = collie_uart_remove, }; -static int __init collie_uart_init(void) { +static int __init collie_uart_init(void) +{ return locomo_driver_register(&collie_uart_driver); } device_initcall(collie_uart_init); @@ -154,28 +258,61 @@ device_initcall(collie_uart_init); static struct resource locomo_resources[] = { - [0] = { - .start = 0x40000000, - .end = 0x40001fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_GPIO25, - .end = IRQ_GPIO25, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(0x40000000, SZ_8K), + [1] = DEFINE_RES_IRQ(IRQ_GPIO25), +}; + +static struct locomo_platform_data locomo_info = { + .irq_base = IRQ_BOARD_START, }; struct platform_device collie_locomo_device = { .name = "locomo", .id = 0, + .dev = { + .platform_data = &locomo_info, + }, .num_resources = ARRAY_SIZE(locomo_resources), .resource = locomo_resources, }; +static struct gpio_keys_button collie_gpio_keys[] = { + { + .type = EV_PWR, + .code = KEY_RESERVED, + .gpio = COLLIE_GPIO_ON_KEY, + .desc = "On key", + .wakeup = 1, + .active_low = 1, + }, + { + .type = EV_PWR, + .code = KEY_WAKEUP, + .gpio = COLLIE_GPIO_WAKEUP, + .desc = "Sync", + .wakeup = 1, + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data collie_gpio_keys_data = { + .buttons = collie_gpio_keys, + .nbuttons = ARRAY_SIZE(collie_gpio_keys), +}; + +static struct platform_device collie_gpio_keys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &collie_gpio_keys_data, + }, +}; + static struct platform_device *devices[] __initdata = { &collie_locomo_device, &colliescoop_device, + &collie_power_device, + &collie_gpio_keys_device, }; static struct mtd_partition collie_partitions[] = { @@ -192,31 +329,66 @@ static struct mtd_partition collie_partitions[] = { .name = "rootfs", .offset = MTDPART_OFS_APPEND, .size = 0x00e20000, + }, { + .name = "bootblock", + .offset = MTDPART_OFS_APPEND, + .size = 0x00020000, + .mask_flags = MTD_WRITEABLE } }; +static int collie_flash_init(void) +{ + int rc = gpio_request(COLLIE_GPIO_VPEN, "flash Vpp enable"); + if (rc) + return rc; + + rc = gpio_direction_output(COLLIE_GPIO_VPEN, 1); + if (rc) + gpio_free(COLLIE_GPIO_VPEN); + + return rc; +} + static void collie_set_vpp(int vpp) { - write_scoop_reg(&colliescoop_device.dev, SCOOP_GPCR, read_scoop_reg(&colliescoop_device.dev, SCOOP_GPCR) | COLLIE_SCP_VPEN); - if (vpp) - write_scoop_reg(&colliescoop_device.dev, SCOOP_GPWR, read_scoop_reg(&colliescoop_device.dev, SCOOP_GPWR) | COLLIE_SCP_VPEN); - else - write_scoop_reg(&colliescoop_device.dev, SCOOP_GPWR, read_scoop_reg(&colliescoop_device.dev, SCOOP_GPWR) & ~COLLIE_SCP_VPEN); + gpio_set_value(COLLIE_GPIO_VPEN, vpp); +} + +static void collie_flash_exit(void) +{ + gpio_free(COLLIE_GPIO_VPEN); } static struct flash_platform_data collie_flash_data = { .map_name = "cfi_probe", + .init = collie_flash_init, .set_vpp = collie_set_vpp, + .exit = collie_flash_exit, .parts = collie_partitions, .nr_parts = ARRAY_SIZE(collie_partitions), }; static struct resource collie_flash_resources[] = { - { - .start = SA1100_CS0_PHYS, - .end = SA1100_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, - } + DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M), +}; + +static struct sa1100fb_mach_info collie_lcd_info = { + .pixclock = 171521, .bpp = 16, + .xres = 320, .yres = 240, + + .hsync_len = 5, .vsync_len = 1, + .left_margin = 11, .upper_margin = 2, + .right_margin = 30, .lower_margin = 0, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + + .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act, + .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2), + +#ifdef CONFIG_BACKLIGHT_LOCOMO + .lcd_power = locomolcd_power +#endif }; static void __init collie_init(void) @@ -230,22 +402,29 @@ static void __init collie_init(void) GPDR = GPIO_LDD8 | GPIO_LDD9 | GPIO_LDD10 | GPIO_LDD11 | GPIO_LDD12 | GPIO_LDD13 | GPIO_LDD14 | GPIO_LDD15 | GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM | GPIO_SDLC_SCLK | - COLLIE_GPIO_UCB1x00_RESET | COLLIE_GPIO_nMIC_ON | - COLLIE_GPIO_nREMOCON_ON | GPIO_32_768kHz; + _COLLIE_GPIO_UCB1x00_RESET | _COLLIE_GPIO_nMIC_ON | + _COLLIE_GPIO_nREMOCON_ON | GPIO_32_768kHz; PPDR = PPC_LDD0 | PPC_LDD1 | PPC_LDD2 | PPC_LDD3 | PPC_LDD4 | PPC_LDD5 | PPC_LDD6 | PPC_LDD7 | PPC_L_PCLK | PPC_L_LCLK | PPC_L_FCLK | PPC_L_BIAS | PPC_TXD1 | PPC_TXD2 | PPC_TXD3 | PPC_TXD4 | PPC_SCLK | PPC_SFRM; - PWER = COLLIE_GPIO_AC_IN | COLLIE_GPIO_CO | COLLIE_GPIO_ON_KEY | - COLLIE_GPIO_WAKEUP | COLLIE_GPIO_nREMOCON_INT | PWER_RTC; + PWER = _COLLIE_GPIO_AC_IN | _COLLIE_GPIO_CO | _COLLIE_GPIO_ON_KEY | + _COLLIE_GPIO_WAKEUP | _COLLIE_GPIO_nREMOCON_INT | PWER_RTC; - PGSR = COLLIE_GPIO_nREMOCON_ON; + PGSR = _COLLIE_GPIO_nREMOCON_ON; PSDR = PPC_RXD1 | PPC_RXD2 | PPC_RXD3 | PPC_RXD4; PCFR = PCFR_OPDE; + GPSR |= _COLLIE_GPIO_UCB1x00_RESET; + + collie_power_resource[0].start = gpio_to_irq(COLLIE_GPIO_AC_IN); + collie_power_resource[0].end = gpio_to_irq(COLLIE_GPIO_AC_IN); + + sa11x0_ppc_configure_mcp(); + platform_scoop_config = &collie_pcmcia_config; @@ -254,9 +433,11 @@ static void __init collie_init(void) printk(KERN_WARNING "collie: Unable to register LoCoMo device\n"); } - sa11x0_set_flash_data(&collie_flash_data, collie_flash_resources, - ARRAY_SIZE(collie_flash_resources)); - sa11x0_set_mcp_data(&collie_mcp_data); + sa11x0_register_lcd(&collie_lcd_info); + sa11x0_register_mtd(&collie_flash_data, collie_flash_resources, + ARRAY_SIZE(collie_flash_resources)); + sa11x0_register_mcp(&collie_mcp_data); + sa11x0_register_irda(&collie_ir_data); sharpsl_save_param(); } @@ -288,10 +469,11 @@ static void __init collie_map_io(void) } MACHINE_START(COLLIE, "Sharp-Collie") - .phys_io = 0x80000000, - .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc, .map_io = collie_map_io, + .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = collie_init, + .init_late = sa11x0_init_late, + .restart = sa11x0_restart, MACHINE_END diff --git a/arch/arm/mach-sa1100/collie_pm.c b/arch/arm/mach-sa1100/collie_pm.c deleted file mode 100644 index b39307f26b5..00000000000 --- a/arch/arm/mach-sa1100/collie_pm.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - * Based on spitz_pm.c and sharp code. - * - * Copyright (C) 2001 SHARP - * Copyright 2005 Pavel Machek <pavel@suse.cz> - * - * Distribute under GPLv2. - * - * Li-ion batteries are angry beasts, and they like to explode. This driver is not finished, - * and sometimes charges them when it should not. If it makes angry lithium to come your way... - * ...well, you have been warned. - * - * Actually, this should be quite safe, it seems sharp leaves charger enabled by default, - * and my collie did not explode (yet). - */ - -#include <linux/module.h> -#include <linux/stat.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/interrupt.h> -#include <linux/device.h> -#include <linux/platform_device.h> - -#include <asm/irq.h> -#include <mach/hardware.h> -#include <asm/hardware/scoop.h> -#include <mach/dma.h> -#include <mach/collie.h> -#include <asm/mach/sharpsl_param.h> -#include <asm/hardware/sharpsl_pm.h> - -#include "../drivers/mfd/ucb1x00.h" - -static struct ucb1x00 *ucb; -static int ad_revise; - -#define ADCtoPower(x) ((330 * x * 2) / 1024) - -static void collie_charger_init(void) -{ - int err; - - if (sharpsl_param.adadj != -1) - ad_revise = sharpsl_param.adadj; - - /* Register interrupt handler. */ - if ((err = request_irq(COLLIE_IRQ_GPIO_AC_IN, sharpsl_ac_isr, IRQF_DISABLED, - "ACIN", sharpsl_ac_isr))) { - printk("Could not get irq %d.\n", COLLIE_IRQ_GPIO_AC_IN); - return; - } - if ((err = request_irq(COLLIE_IRQ_GPIO_CO, sharpsl_chrg_full_isr, IRQF_DISABLED, - "CO", sharpsl_chrg_full_isr))) { - free_irq(COLLIE_IRQ_GPIO_AC_IN, sharpsl_ac_isr); - printk("Could not get irq %d.\n", COLLIE_IRQ_GPIO_CO); - return; - } - - ucb1x00_io_set_dir(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON | COLLIE_TC35143_GPIO_TMP_ON | - COLLIE_TC35143_GPIO_BBAT_ON); - return; -} - -static void collie_measure_temp(int on) -{ - if (on) - ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_TMP_ON, 0); - else - ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_TMP_ON); -} - -static void collie_charge(int on) -{ - extern struct platform_device colliescoop_device; - - /* Zaurus seems to contain LTC1731; it should know when to - * stop charging itself, so setting charge on should be - * relatively harmless (as long as it is not done too often). - */ - if (on) { - set_scoop_gpio(&colliescoop_device.dev, COLLIE_SCP_CHARGE_ON); - } else { - reset_scoop_gpio(&colliescoop_device.dev, COLLIE_SCP_CHARGE_ON); - } -} - -static void collie_discharge(int on) -{ -} - -static void collie_discharge1(int on) -{ -} - -static void collie_presuspend(void) -{ -} - -static void collie_postsuspend(void) -{ -} - -static int collie_should_wakeup(unsigned int resume_on_alarm) -{ - return 0; -} - -static unsigned long collie_charger_wakeup(void) -{ - return 0; -} - -int collie_read_backup_battery(void) -{ - int voltage; - - ucb1x00_adc_enable(ucb); - - ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_BBAT_ON, 0); - voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD1, UCB_SYNC); - - ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_BBAT_ON); - ucb1x00_adc_disable(ucb); - - printk("Backup battery = %d(%d)\n", ADCtoPower(voltage), voltage); - - return ADCtoPower(voltage); -} - -int collie_read_main_battery(void) -{ - int voltage, voltage_rev, voltage_volts; - - ucb1x00_adc_enable(ucb); - ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_BBAT_ON); - ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_MBAT_ON, 0); - - mdelay(1); - voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD1, UCB_SYNC); - - ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON); - ucb1x00_adc_disable(ucb); - - voltage_rev = voltage + ((ad_revise * voltage) / 652); - voltage_volts = ADCtoPower(voltage_rev); - - printk("Main battery = %d(%d)\n", voltage_volts, voltage); - - if (voltage != -1) - return voltage_volts; - else - return voltage; -} - -int collie_read_temp(void) -{ - int voltage; - - /* According to Sharp, temp must be > 973, main battery must be < 465, - FIXME: sharpsl_pm.c has both conditions negated? FIXME: values - are way out of range? */ - - ucb1x00_adc_enable(ucb); - ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_TMP_ON, 0); - /* >1010 = battery removed, 460 = 22C ?, higher = lower temp ? */ - voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD0, UCB_SYNC); - ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_TMP_ON); - ucb1x00_adc_disable(ucb); - - printk("Battery temp = %d\n", voltage); - return voltage; -} - -static unsigned long read_devdata(int which) -{ - switch (which) { - case SHARPSL_BATT_VOLT: - return collie_read_main_battery(); - case SHARPSL_BATT_TEMP: - return collie_read_temp(); - case SHARPSL_ACIN_VOLT: - return 500; - case SHARPSL_STATUS_ACIN: { - int ret = GPLR & COLLIE_GPIO_AC_IN; - printk("AC status = %d\n", ret); - return ret; - } - case SHARPSL_STATUS_FATAL: { - int ret = GPLR & COLLIE_GPIO_MAIN_BAT_LOW; - printk("Fatal bat = %d\n", ret); - return ret; - } - default: - return ~0; - } -} - -struct battery_thresh collie_battery_levels_acin[] = { - { 420, 100}, - { 417, 95}, - { 415, 90}, - { 413, 80}, - { 411, 75}, - { 408, 70}, - { 406, 60}, - { 403, 50}, - { 398, 40}, - { 391, 25}, - { 10, 5}, - { 0, 0}, -}; - -struct battery_thresh collie_battery_levels[] = { - { 394, 100}, - { 390, 95}, - { 380, 90}, - { 370, 80}, - { 368, 75}, /* From sharp code: battery high with frontlight */ - { 366, 70}, /* 60..90 -- fake values invented by me for testing */ - { 364, 60}, - { 362, 50}, - { 360, 40}, - { 358, 25}, /* From sharp code: battery low with frontlight */ - { 356, 5}, /* From sharp code: battery verylow with frontlight */ - { 0, 0}, -}; - -struct sharpsl_charger_machinfo collie_pm_machinfo = { - .init = collie_charger_init, - .read_devdata = read_devdata, - .discharge = collie_discharge, - .discharge1 = collie_discharge1, - .charge = collie_charge, - .measure_temp = collie_measure_temp, - .presuspend = collie_presuspend, - .postsuspend = collie_postsuspend, - .charger_wakeup = collie_charger_wakeup, - .should_wakeup = collie_should_wakeup, - .bat_levels = 12, - .bat_levels_noac = collie_battery_levels, - .bat_levels_acin = collie_battery_levels_acin, - .status_high_acin = 368, - .status_low_acin = 358, - .status_high_noac = 368, - .status_low_noac = 358, - .charge_on_volt = 350, /* spitz uses 2.90V, but lets play it safe. */ - .charge_on_temp = 550, - .charge_acin_high = 550, /* collie does not seem to have sensor for this, anyway */ - .charge_acin_low = 450, /* ignored, too */ - .fatal_acin_volt = 356, - .fatal_noacin_volt = 356, - - .batfull_irq = 1, /* We do not want periodical charge restarts */ -}; - -static int __init collie_pm_ucb_add(struct ucb1x00_dev *pdev) -{ - sharpsl_pm.machinfo = &collie_pm_machinfo; - ucb = pdev->ucb; - return 0; -} - -static struct ucb1x00_driver collie_pm_ucb_driver = { - .add = collie_pm_ucb_add, -}; - -static struct platform_device *collie_pm_device; - -static int __init collie_pm_init(void) -{ - int ret; - - collie_pm_device = platform_device_alloc("sharpsl-pm", -1); - if (!collie_pm_device) - return -ENOMEM; - - collie_pm_device->dev.platform_data = &collie_pm_machinfo; - ret = platform_device_add(collie_pm_device); - - if (ret) - platform_device_put(collie_pm_device); - - if (!ret) - ret = ucb1x00_register_driver(&collie_pm_ucb_driver); - - return ret; -} - -static void __exit collie_pm_exit(void) -{ - ucb1x00_unregister_driver(&collie_pm_ucb_driver); - platform_device_unregister(collie_pm_device); -} - -module_init(collie_pm_init); -module_exit(collie_pm_exit); diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c deleted file mode 100644 index ef817876a5d..00000000000 --- a/arch/arm/mach-sa1100/cpu-sa1100.c +++ /dev/null @@ -1,250 +0,0 @@ -/* - * cpu-sa1100.c: clock scaling for the SA1100 - * - * Copyright (C) 2000 2001, The Delft University of Technology - * - * Authors: - * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version - * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl): - * - major rewrite for linux-2.3.99 - * - rewritten for the more generic power management scheme in - * linux-2.4.5-rmk1 - * - * This software has been developed while working on the LART - * computing board (http://www.lartmaker.nl/), which is - * sponsored by the Mobile Multi-media Communications - * (http://www.mmc.tudelft.nl/) and Ubiquitous Communications - * (http://www.ubicom.tudelft.nl/) projects. - * - * The authors can be reached at: - * - * Erik Mouw - * Information and Communication Theory Group - * Faculty of Information Technology and Systems - * Delft University of Technology - * P.O. Box 5031 - * 2600 GA Delft - * The Netherlands - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * - * Theory of operations - * ==================== - * - * Clock scaling can be used to lower the power consumption of the CPU - * core. This will give you a somewhat longer running time. - * - * The SA-1100 has a single register to change the core clock speed: - * - * PPCR 0x90020014 PLL config - * - * However, the DRAM timings are closely related to the core clock - * speed, so we need to change these, too. The used registers are: - * - * MDCNFG 0xA0000000 DRAM config - * MDCAS0 0xA0000004 Access waveform - * MDCAS1 0xA0000008 Access waveform - * MDCAS2 0xA000000C Access waveform - * - * Care must be taken to change the DRAM parameters the correct way, - * because otherwise the DRAM becomes unusable and the kernel will - * crash. - * - * The simple solution to avoid a kernel crash is to put the actual - * clock change in ROM and jump to that code from the kernel. The main - * disadvantage is that the ROM has to be modified, which is not - * possible on all SA-1100 platforms. Another disadvantage is that - * jumping to ROM makes clock switching unecessary complicated. - * - * The idea behind this driver is that the memory configuration can be - * changed while running from DRAM (even with interrupts turned on!) - * as long as all re-configuration steps yield a valid DRAM - * configuration. The advantages are clear: it will run on all SA-1100 - * platforms, and the code is very simple. - * - * If you really want to understand what is going on in - * sa1100_update_dram_timings(), you'll have to read sections 8.2, - * 9.5.7.3, and 10.2 from the "Intel StrongARM SA-1100 Microprocessor - * Developers Manual" (available for free from Intel). - * - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/cpufreq.h> - -#include <asm/cputype.h> - -#include <mach/hardware.h> - -#include "generic.h" - -typedef struct { - int speed; - u32 mdcnfg; - u32 mdcas0; - u32 mdcas1; - u32 mdcas2; -} sa1100_dram_regs_t; - - -static struct cpufreq_driver sa1100_driver; - -static sa1100_dram_regs_t sa1100_dram_settings[] = -{ - /* speed, mdcnfg, mdcas0, mdcas1, mdcas2 clock frequency */ - { 59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 59.0 MHz */ - { 73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 73.7 MHz */ - { 88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 88.5 MHz */ - { 103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 103.2 MHz */ - { 118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff }, /* 118.0 MHz */ - { 132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff }, /* 132.7 MHz */ - { 147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff }, /* 147.5 MHz */ - { 162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff }, /* 162.2 MHz */ - { 176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff }, /* 176.9 MHz */ - { 191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff }, /* 191.7 MHz */ - { 206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff }, /* 206.4 MHz */ - { 221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff }, /* 221.2 MHz */ - { 235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1 }, /* 235.9 MHz */ - { 250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3 }, /* 250.7 MHz */ - { 265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3 }, /* 265.4 MHz */ - { 280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87 }, /* 280.2 MHz */ - { 0, 0, 0, 0, 0 } /* last entry */ -}; - -static void sa1100_update_dram_timings(int current_speed, int new_speed) -{ - sa1100_dram_regs_t *settings = sa1100_dram_settings; - - /* find speed */ - while (settings->speed != 0) { - if(new_speed == settings->speed) - break; - - settings++; - } - - if (settings->speed == 0) { - panic("%s: couldn't find dram setting for speed %d\n", - __func__, new_speed); - } - - /* No risk, no fun: run with interrupts on! */ - if (new_speed > current_speed) { - /* We're going FASTER, so first relax the memory - * timings before changing the core frequency - */ - - /* Half the memory access clock */ - MDCNFG |= MDCNFG_CDB2; - - /* The order of these statements IS important, keep 8 - * pulses!! - */ - MDCAS2 = settings->mdcas2; - MDCAS1 = settings->mdcas1; - MDCAS0 = settings->mdcas0; - MDCNFG = settings->mdcnfg; - } else { - /* We're going SLOWER: first decrease the core - * frequency and then tighten the memory settings. - */ - - /* Half the memory access clock */ - MDCNFG |= MDCNFG_CDB2; - - /* The order of these statements IS important, keep 8 - * pulses!! - */ - MDCAS0 = settings->mdcas0; - MDCAS1 = settings->mdcas1; - MDCAS2 = settings->mdcas2; - MDCNFG = settings->mdcnfg; - } -} - -static int sa1100_target(struct cpufreq_policy *policy, - unsigned int target_freq, - unsigned int relation) -{ - unsigned int cur = sa11x0_getspeed(0); - unsigned int new_ppcr; - - struct cpufreq_freqs freqs; - switch(relation){ - case CPUFREQ_RELATION_L: - new_ppcr = sa11x0_freq_to_ppcr(target_freq); - if (sa11x0_ppcr_to_freq(new_ppcr) > policy->max) - new_ppcr--; - break; - case CPUFREQ_RELATION_H: - new_ppcr = sa11x0_freq_to_ppcr(target_freq); - if ((sa11x0_ppcr_to_freq(new_ppcr) > target_freq) && - (sa11x0_ppcr_to_freq(new_ppcr - 1) >= policy->min)) - new_ppcr--; - break; - } - - freqs.old = cur; - freqs.new = sa11x0_ppcr_to_freq(new_ppcr); - freqs.cpu = 0; - - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); - - if (freqs.new > cur) - sa1100_update_dram_timings(cur, freqs.new); - - PPCR = new_ppcr; - - if (freqs.new < cur) - sa1100_update_dram_timings(cur, freqs.new); - - cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - - return 0; -} - -static int __init sa1100_cpu_init(struct cpufreq_policy *policy) -{ - if (policy->cpu != 0) - return -EINVAL; - policy->cur = policy->min = policy->max = sa11x0_getspeed(0); - policy->cpuinfo.min_freq = 59000; - policy->cpuinfo.max_freq = 287000; - policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; - return 0; -} - -static struct cpufreq_driver sa1100_driver = { - .flags = CPUFREQ_STICKY, - .verify = sa11x0_verify_speed, - .target = sa1100_target, - .get = sa11x0_getspeed, - .init = sa1100_cpu_init, - .name = "sa1100", -}; - -static int __init sa1100_dram_init(void) -{ - if (cpu_is_sa1100()) - return cpufreq_register_driver(&sa1100_driver); - else - return -ENODEV; -} - -arch_initcall(sa1100_dram_init); diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c deleted file mode 100644 index 63b32b68b29..00000000000 --- a/arch/arm/mach-sa1100/cpu-sa1110.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * linux/arch/arm/mach-sa1100/cpu-sa1110.c - * - * Copyright (C) 2001 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Note: there are two erratas that apply to the SA1110 here: - * 7 - SDRAM auto-power-up failure (rev A0) - * 13 - Corruption of internal register reads/writes following - * SDRAM reads (rev A0, B0, B1) - * - * We ignore rev. A0 and B0 devices; I don't think they're worth supporting. - * - * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type - */ -#include <linux/moduleparam.h> -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/cpufreq.h> -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <asm/cputype.h> -#include <asm/mach-types.h> -#include <asm/system.h> - -#include "generic.h" - -#undef DEBUG - -static struct cpufreq_driver sa1110_driver; - -struct sdram_params { - const char name[16]; - u_char rows; /* bits */ - u_char cas_latency; /* cycles */ - u_char tck; /* clock cycle time (ns) */ - u_char trcd; /* activate to r/w (ns) */ - u_char trp; /* precharge to activate (ns) */ - u_char twr; /* write recovery time (ns) */ - u_short refresh; /* refresh time for array (us) */ -}; - -struct sdram_info { - u_int mdcnfg; - u_int mdrefr; - u_int mdcas[3]; -}; - -static struct sdram_params sdram_tbl[] __initdata = { - { /* Toshiba TC59SM716 CL2 */ - .name = "TC59SM716-CL2", - .rows = 12, - .tck = 10, - .trcd = 20, - .trp = 20, - .twr = 10, - .refresh = 64000, - .cas_latency = 2, - }, { /* Toshiba TC59SM716 CL3 */ - .name = "TC59SM716-CL3", - .rows = 12, - .tck = 8, - .trcd = 20, - .trp = 20, - .twr = 8, - .refresh = 64000, - .cas_latency = 3, - }, { /* Samsung K4S641632D TC75 */ - .name = "K4S641632D", - .rows = 14, - .tck = 9, - .trcd = 27, - .trp = 20, - .twr = 9, - .refresh = 64000, - .cas_latency = 3, - }, { /* Samsung K4S281632B-1H */ - .name = "K4S281632B-1H", - .rows = 12, - .tck = 10, - .trp = 20, - .twr = 10, - .refresh = 64000, - .cas_latency = 3, - }, { /* Samsung KM416S4030CT */ - .name = "KM416S4030CT", - .rows = 13, - .tck = 8, - .trcd = 24, /* 3 CLKs */ - .trp = 24, /* 3 CLKs */ - .twr = 16, /* Trdl: 2 CLKs */ - .refresh = 64000, - .cas_latency = 3, - }, { /* Winbond W982516AH75L CL3 */ - .name = "W982516AH75L", - .rows = 16, - .tck = 8, - .trcd = 20, - .trp = 20, - .twr = 8, - .refresh = 64000, - .cas_latency = 3, - }, -}; - -static struct sdram_params sdram_params; - -/* - * Given a period in ns and frequency in khz, calculate the number of - * cycles of frequency in period. Note that we round up to the next - * cycle, even if we are only slightly over. - */ -static inline u_int ns_to_cycles(u_int ns, u_int khz) -{ - return (ns * khz + 999999) / 1000000; -} - -/* - * Create the MDCAS register bit pattern. - */ -static inline void set_mdcas(u_int *mdcas, int delayed, u_int rcd) -{ - u_int shift; - - rcd = 2 * rcd - 1; - shift = delayed + 1 + rcd; - - mdcas[0] = (1 << rcd) - 1; - mdcas[0] |= 0x55555555 << shift; - mdcas[1] = mdcas[2] = 0x55555555 << (shift & 1); -} - -static void -sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz, - struct sdram_params *sdram) -{ - u_int mem_khz, sd_khz, trp, twr; - - mem_khz = cpu_khz / 2; - sd_khz = mem_khz; - - /* - * If SDCLK would invalidate the SDRAM timings, - * run SDCLK at half speed. - * - * CPU steppings prior to B2 must either run the memory at - * half speed or use delayed read latching (errata 13). - */ - if ((ns_to_cycles(sdram->tck, sd_khz) > 1) || - (CPU_REVISION < CPU_SA1110_B2 && sd_khz < 62000)) - sd_khz /= 2; - - sd->mdcnfg = MDCNFG & 0x007f007f; - - twr = ns_to_cycles(sdram->twr, mem_khz); - - /* trp should always be >1 */ - trp = ns_to_cycles(sdram->trp, mem_khz) - 1; - if (trp < 1) - trp = 1; - - sd->mdcnfg |= trp << 8; - sd->mdcnfg |= trp << 24; - sd->mdcnfg |= sdram->cas_latency << 12; - sd->mdcnfg |= sdram->cas_latency << 28; - sd->mdcnfg |= twr << 14; - sd->mdcnfg |= twr << 30; - - sd->mdrefr = MDREFR & 0xffbffff0; - sd->mdrefr |= 7; - - if (sd_khz != mem_khz) - sd->mdrefr |= MDREFR_K1DB2; - - /* initial number of '1's in MDCAS + 1 */ - set_mdcas(sd->mdcas, sd_khz >= 62000, ns_to_cycles(sdram->trcd, mem_khz)); - -#ifdef DEBUG - printk("MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n", - sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1], sd->mdcas[2]); -#endif -} - -/* - * Set the SDRAM refresh rate. - */ -static inline void sdram_set_refresh(u_int dri) -{ - MDREFR = (MDREFR & 0xffff000f) | (dri << 4); - (void) MDREFR; -} - -/* - * Update the refresh period. We do this such that we always refresh - * the SDRAMs within their permissible period. The refresh period is - * always a multiple of the memory clock (fixed at cpu_clock / 2). - * - * FIXME: we don't currently take account of burst accesses here, - * but neither do Intels DM nor Angel. - */ -static void -sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram) -{ - u_int ns_row = (sdram->refresh * 1000) >> sdram->rows; - u_int dri = ns_to_cycles(ns_row, cpu_khz / 2) / 32; - -#ifdef DEBUG - mdelay(250); - printk("new dri value = %d\n", dri); -#endif - - sdram_set_refresh(dri); -} - -/* - * Ok, set the CPU frequency. - */ -static int sa1110_target(struct cpufreq_policy *policy, - unsigned int target_freq, - unsigned int relation) -{ - struct sdram_params *sdram = &sdram_params; - struct cpufreq_freqs freqs; - struct sdram_info sd; - unsigned long flags; - unsigned int ppcr, unused; - - switch(relation){ - case CPUFREQ_RELATION_L: - ppcr = sa11x0_freq_to_ppcr(target_freq); - if (sa11x0_ppcr_to_freq(ppcr) > policy->max) - ppcr--; - break; - case CPUFREQ_RELATION_H: - ppcr = sa11x0_freq_to_ppcr(target_freq); - if (ppcr && (sa11x0_ppcr_to_freq(ppcr) > target_freq) && - (sa11x0_ppcr_to_freq(ppcr-1) >= policy->min)) - ppcr--; - break; - default: - return -EINVAL; - } - - freqs.old = sa11x0_getspeed(0); - freqs.new = sa11x0_ppcr_to_freq(ppcr); - freqs.cpu = 0; - - sdram_calculate_timing(&sd, freqs.new, sdram); - -#if 0 - /* - * These values are wrong according to the SA1110 documentation - * and errata, but they seem to work. Need to get a storage - * scope on to the SDRAM signals to work out why. - */ - if (policy->max < 147500) { - sd.mdrefr |= MDREFR_K1DB2; - sd.mdcas[0] = 0xaaaaaa7f; - } else { - sd.mdrefr &= ~MDREFR_K1DB2; - sd.mdcas[0] = 0xaaaaaa9f; - } - sd.mdcas[1] = 0xaaaaaaaa; - sd.mdcas[2] = 0xaaaaaaaa; -#endif - - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); - - /* - * The clock could be going away for some time. Set the SDRAMs - * to refresh rapidly (every 64 memory clock cycles). To get - * through the whole array, we need to wait 262144 mclk cycles. - * We wait 20ms to be safe. - */ - sdram_set_refresh(2); - if (!irqs_disabled()) { - msleep(20); - } else { - mdelay(20); - } - - /* - * Reprogram the DRAM timings with interrupts disabled, and - * ensure that we are doing this within a complete cache line. - * This means that we won't access SDRAM for the duration of - * the programming. - */ - local_irq_save(flags); - asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); - udelay(10); - __asm__ __volatile__(" \n\ - b 2f \n\ - .align 5 \n\ -1: str %3, [%1, #0] @ MDCNFG \n\ - str %4, [%1, #28] @ MDREFR \n\ - str %5, [%1, #4] @ MDCAS0 \n\ - str %6, [%1, #8] @ MDCAS1 \n\ - str %7, [%1, #12] @ MDCAS2 \n\ - str %8, [%2, #0] @ PPCR \n\ - ldr %0, [%1, #0] \n\ - b 3f \n\ -2: b 1b \n\ -3: nop \n\ - nop" - : "=&r" (unused) - : "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg), - "r" (sd.mdrefr), "r" (sd.mdcas[0]), - "r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr)); - local_irq_restore(flags); - - /* - * Now, return the SDRAM refresh back to normal. - */ - sdram_update_refresh(freqs.new, sdram); - - cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - - return 0; -} - -static int __init sa1110_cpu_init(struct cpufreq_policy *policy) -{ - if (policy->cpu != 0) - return -EINVAL; - policy->cur = policy->min = policy->max = sa11x0_getspeed(0); - policy->cpuinfo.min_freq = 59000; - policy->cpuinfo.max_freq = 287000; - policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; - return 0; -} - -static struct cpufreq_driver sa1110_driver = { - .flags = CPUFREQ_STICKY, - .verify = sa11x0_verify_speed, - .target = sa1110_target, - .get = sa11x0_getspeed, - .init = sa1110_cpu_init, - .name = "sa1110", -}; - -static struct sdram_params *sa1110_find_sdram(const char *name) -{ - struct sdram_params *sdram; - - for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl); sdram++) - if (strcmp(name, sdram->name) == 0) - return sdram; - - return NULL; -} - -static char sdram_name[16]; - -static int __init sa1110_clk_init(void) -{ - struct sdram_params *sdram; - const char *name = sdram_name; - - if (!name[0]) { - if (machine_is_assabet()) - name = "TC59SM716-CL3"; - - if (machine_is_pt_system3()) - name = "K4S641632D"; - - if (machine_is_h3100()) - name = "KM416S4030CT"; - if (machine_is_jornada720()) - name = "K4S281632B-1H"; - } - - sdram = sa1110_find_sdram(name); - if (sdram) { - printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d" - " twr: %d refresh: %d cas_latency: %d\n", - sdram->tck, sdram->trcd, sdram->trp, - sdram->twr, sdram->refresh, sdram->cas_latency); - - memcpy(&sdram_params, sdram, sizeof(sdram_params)); - - return cpufreq_register_driver(&sa1110_driver); - } - - return 0; -} - -module_param_string(sdram, sdram_name, sizeof(sdram_name), 0); -arch_initcall(sa1110_clk_init); diff --git a/arch/arm/mach-sa1100/dma.c b/arch/arm/mach-sa1100/dma.c deleted file mode 100644 index 95f9c5a6d6d..00000000000 --- a/arch/arm/mach-sa1100/dma.c +++ /dev/null @@ -1,348 +0,0 @@ -/* - * arch/arm/mach-sa1100/dma.c - * - * Support functions for the SA11x0 internal DMA channels. - * - * Copyright (C) 2000, 2001 by Nicolas Pitre - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/errno.h> - -#include <asm/system.h> -#include <asm/irq.h> -#include <mach/hardware.h> -#include <mach/dma.h> - - -#undef DEBUG -#ifdef DEBUG -#define DPRINTK( s, arg... ) printk( "dma<%p>: " s, regs , ##arg ) -#else -#define DPRINTK( x... ) -#endif - - -typedef struct { - const char *device_id; /* device name */ - u_long device; /* this channel device, 0 if unused*/ - dma_callback_t callback; /* to call when DMA completes */ - void *data; /* ... with private data ptr */ -} sa1100_dma_t; - -static sa1100_dma_t dma_chan[SA1100_DMA_CHANNELS]; - -static spinlock_t dma_list_lock; - - -static irqreturn_t dma_irq_handler(int irq, void *dev_id) -{ - dma_regs_t *dma_regs = dev_id; - sa1100_dma_t *dma = dma_chan + (((u_int)dma_regs >> 5) & 7); - int status = dma_regs->RdDCSR; - - if (status & (DCSR_ERROR)) { - printk(KERN_CRIT "DMA on \"%s\" caused an error\n", dma->device_id); - dma_regs->ClrDCSR = DCSR_ERROR; - } - - dma_regs->ClrDCSR = status & (DCSR_DONEA | DCSR_DONEB); - if (dma->callback) { - if (status & DCSR_DONEA) - dma->callback(dma->data); - if (status & DCSR_DONEB) - dma->callback(dma->data); - } - return IRQ_HANDLED; -} - - -/** - * sa1100_request_dma - allocate one of the SA11x0's DMA chanels - * @device: The SA11x0 peripheral targeted by this request - * @device_id: An ascii name for the claiming device - * @callback: Function to be called when the DMA completes - * @data: A cookie passed back to the callback function - * @dma_regs: Pointer to the location of the allocated channel's identifier - * - * This function will search for a free DMA channel and returns the - * address of the hardware registers for that channel as the channel - * identifier. This identifier is written to the location pointed by - * @dma_regs. The list of possible values for @device are listed into - * arch/arm/mach-sa1100/include/mach/dma.h as a dma_device_t enum. - * - * Note that reading from a port and writing to the same port are - * actually considered as two different streams requiring separate - * DMA registrations. - * - * The @callback function is called from interrupt context when one - * of the two possible DMA buffers in flight has terminated. That - * function has to be small and efficient while posponing more complex - * processing to a lower priority execution context. - * - * If no channels are available, or if the desired @device is already in - * use by another DMA channel, then an error code is returned. This - * function must be called before any other DMA calls. - **/ - -int sa1100_request_dma (dma_device_t device, const char *device_id, - dma_callback_t callback, void *data, - dma_regs_t **dma_regs) -{ - sa1100_dma_t *dma = NULL; - dma_regs_t *regs; - int i, err; - - *dma_regs = NULL; - - err = 0; - spin_lock(&dma_list_lock); - for (i = 0; i < SA1100_DMA_CHANNELS; i++) { - if (dma_chan[i].device == device) { - err = -EBUSY; - break; - } else if (!dma_chan[i].device && !dma) { - dma = &dma_chan[i]; - } - } - if (!err) { - if (dma) - dma->device = device; - else - err = -ENOSR; - } - spin_unlock(&dma_list_lock); - if (err) - return err; - - i = dma - dma_chan; - regs = (dma_regs_t *)&DDAR(i); - err = request_irq(IRQ_DMA0 + i, dma_irq_handler, IRQF_DISABLED, - device_id, regs); - if (err) { - printk(KERN_ERR - "%s: unable to request IRQ %d for %s\n", - __func__, IRQ_DMA0 + i, device_id); - dma->device = 0; - return err; - } - - *dma_regs = regs; - dma->device_id = device_id; - dma->callback = callback; - dma->data = data; - - regs->ClrDCSR = - (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB | - DCSR_IE | DCSR_ERROR | DCSR_RUN); - regs->DDAR = device; - - return 0; -} - - -/** - * sa1100_free_dma - free a SA11x0 DMA channel - * @regs: identifier for the channel to free - * - * This clears all activities on a given DMA channel and releases it - * for future requests. The @regs identifier is provided by a - * successful call to sa1100_request_dma(). - **/ - -void sa1100_free_dma(dma_regs_t *regs) -{ - int i; - - for (i = 0; i < SA1100_DMA_CHANNELS; i++) - if (regs == (dma_regs_t *)&DDAR(i)) - break; - if (i >= SA1100_DMA_CHANNELS) { - printk(KERN_ERR "%s: bad DMA identifier\n", __func__); - return; - } - - if (!dma_chan[i].device) { - printk(KERN_ERR "%s: Trying to free free DMA\n", __func__); - return; - } - - regs->ClrDCSR = - (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB | - DCSR_IE | DCSR_ERROR | DCSR_RUN); - free_irq(IRQ_DMA0 + i, regs); - dma_chan[i].device = 0; -} - - -/** - * sa1100_start_dma - submit a data buffer for DMA - * @regs: identifier for the channel to use - * @dma_ptr: buffer physical (or bus) start address - * @size: buffer size - * - * This function hands the given data buffer to the hardware for DMA - * access. If another buffer is already in flight then this buffer - * will be queued so the DMA engine will switch to it automatically - * when the previous one is done. The DMA engine is actually toggling - * between two buffers so at most 2 successful calls can be made before - * one of them terminates and the callback function is called. - * - * The @regs identifier is provided by a successful call to - * sa1100_request_dma(). - * - * The @size must not be larger than %MAX_DMA_SIZE. If a given buffer - * is larger than that then it's the caller's responsibility to split - * it into smaller chunks and submit them separately. If this is the - * case then a @size of %CUT_DMA_SIZE is recommended to avoid ending - * up with too small chunks. The callback function can be used to chain - * submissions of buffer chunks. - * - * Error return values: - * %-EOVERFLOW: Given buffer size is too big. - * %-EBUSY: Both DMA buffers are already in use. - * %-EAGAIN: Both buffers were busy but one of them just completed - * but the interrupt handler has to execute first. - * - * This function returs 0 on success. - **/ - -int sa1100_start_dma(dma_regs_t *regs, dma_addr_t dma_ptr, u_int size) -{ - unsigned long flags; - u_long status; - int ret; - - if (dma_ptr & 3) - printk(KERN_WARNING "DMA: unaligned start address (0x%08lx)\n", - (unsigned long)dma_ptr); - - if (size > MAX_DMA_SIZE) - return -EOVERFLOW; - - local_irq_save(flags); - status = regs->RdDCSR; - - /* If both DMA buffers are started, there's nothing else we can do. */ - if ((status & (DCSR_STRTA | DCSR_STRTB)) == (DCSR_STRTA | DCSR_STRTB)) { - DPRINTK("start: st %#x busy\n", status); - ret = -EBUSY; - goto out; - } - - if (((status & DCSR_BIU) && (status & DCSR_STRTB)) || - (!(status & DCSR_BIU) && !(status & DCSR_STRTA))) { - if (status & DCSR_DONEA) { - /* give a chance for the interrupt to be processed */ - ret = -EAGAIN; - goto out; - } - regs->DBSA = dma_ptr; - regs->DBTA = size; - regs->SetDCSR = DCSR_STRTA | DCSR_IE | DCSR_RUN; - DPRINTK("start a=%#x s=%d on A\n", dma_ptr, size); - } else { - if (status & DCSR_DONEB) { - /* give a chance for the interrupt to be processed */ - ret = -EAGAIN; - goto out; - } - regs->DBSB = dma_ptr; - regs->DBTB = size; - regs->SetDCSR = DCSR_STRTB | DCSR_IE | DCSR_RUN; - DPRINTK("start a=%#x s=%d on B\n", dma_ptr, size); - } - ret = 0; - -out: - local_irq_restore(flags); - return ret; -} - - -/** - * sa1100_get_dma_pos - return current DMA position - * @regs: identifier for the channel to use - * - * This function returns the current physical (or bus) address for the - * given DMA channel. If the channel is running i.e. not in a stopped - * state then the caller must disable interrupts prior calling this - * function and process the returned value before re-enabling them to - * prevent races with the completion interrupt handler and the callback - * function. The validation of the returned value is the caller's - * responsibility as well -- the hardware seems to return out of range - * values when the DMA engine completes a buffer. - * - * The @regs identifier is provided by a successful call to - * sa1100_request_dma(). - **/ - -dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs) -{ - int status; - - /* - * We must determine whether buffer A or B is active. - * Two possibilities: either we are in the middle of - * a buffer, or the DMA controller just switched to the - * next toggle but the interrupt hasn't been serviced yet. - * The former case is straight forward. In the later case, - * we'll do like if DMA is just at the end of the previous - * toggle since all registers haven't been reset yet. - * This goes around the edge case and since we're always - * a little behind anyways it shouldn't make a big difference. - * If DMA has been stopped prior calling this then the - * position is exact. - */ - status = regs->RdDCSR; - if ((!(status & DCSR_BIU) && (status & DCSR_STRTA)) || - ( (status & DCSR_BIU) && !(status & DCSR_STRTB))) - return regs->DBSA; - else - return regs->DBSB; -} - - -/** - * sa1100_reset_dma - reset a DMA channel - * @regs: identifier for the channel to use - * - * This function resets and reconfigure the given DMA channel. This is - * particularly useful after a sleep/wakeup event. - * - * The @regs identifier is provided by a successful call to - * sa1100_request_dma(). - **/ - -void sa1100_reset_dma(dma_regs_t *regs) -{ - int i; - - for (i = 0; i < SA1100_DMA_CHANNELS; i++) - if (regs == (dma_regs_t *)&DDAR(i)) - break; - if (i >= SA1100_DMA_CHANNELS) { - printk(KERN_ERR "%s: bad DMA identifier\n", __func__); - return; - } - - regs->ClrDCSR = - (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB | - DCSR_IE | DCSR_ERROR | DCSR_RUN); - regs->DDAR = dma_chan[i].device; -} - - -EXPORT_SYMBOL(sa1100_request_dma); -EXPORT_SYMBOL(sa1100_free_dma); -EXPORT_SYMBOL(sa1100_start_dma); -EXPORT_SYMBOL(sa1100_get_dma_pos); -EXPORT_SYMBOL(sa1100_reset_dma); - diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 23cfdd59395..d4ea142c4ed 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c @@ -9,25 +9,28 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include <linux/gpio.h> #include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/delay.h> +#include <linux/dma-mapping.h> #include <linux/pm.h> #include <linux/cpufreq.h> #include <linux/ioport.h> -#include <linux/sched.h> /* just for sched_clock() - funny that */ #include <linux/platform_device.h> -#include <linux/cnt32_to_63.h> +#include <linux/reboot.h> + +#include <video/sa1100fb.h> #include <asm/div64.h> -#include <mach/hardware.h> -#include <asm/system.h> -#include <asm/pgtable.h> #include <asm/mach/map.h> #include <asm/mach/flash.h> #include <asm/irq.h> -#include <asm/gpio.h> +#include <asm/system_misc.h> + +#include <mach/hardware.h> +#include <mach/irqs.h> #include "generic.h" @@ -39,107 +42,31 @@ EXPORT_SYMBOL(reset_status); /* * This table is setup for a 3.6864MHz Crystal. */ -static const unsigned short cclk_frequency_100khz[NR_FREQS] = { - 590, /* 59.0 MHz */ - 737, /* 73.7 MHz */ - 885, /* 88.5 MHz */ - 1032, /* 103.2 MHz */ - 1180, /* 118.0 MHz */ - 1327, /* 132.7 MHz */ - 1475, /* 147.5 MHz */ - 1622, /* 162.2 MHz */ - 1769, /* 176.9 MHz */ - 1917, /* 191.7 MHz */ - 2064, /* 206.4 MHz */ - 2212, /* 221.2 MHz */ - 2359, /* 235.9 MHz */ - 2507, /* 250.7 MHz */ - 2654, /* 265.4 MHz */ - 2802 /* 280.2 MHz */ +struct cpufreq_frequency_table sa11x0_freq_table[NR_FREQS+1] = { + { .frequency = 59000, /* 59.0 MHz */}, + { .frequency = 73700, /* 73.7 MHz */}, + { .frequency = 88500, /* 88.5 MHz */}, + { .frequency = 103200, /* 103.2 MHz */}, + { .frequency = 118000, /* 118.0 MHz */}, + { .frequency = 132700, /* 132.7 MHz */}, + { .frequency = 147500, /* 147.5 MHz */}, + { .frequency = 162200, /* 162.2 MHz */}, + { .frequency = 176900, /* 176.9 MHz */}, + { .frequency = 191700, /* 191.7 MHz */}, + { .frequency = 206400, /* 206.4 MHz */}, + { .frequency = 221200, /* 221.2 MHz */}, + { .frequency = 235900, /* 235.9 MHz */}, + { .frequency = 250700, /* 250.7 MHz */}, + { .frequency = 265400, /* 265.4 MHz */}, + { .frequency = 280200, /* 280.2 MHz */}, + { .frequency = CPUFREQ_TABLE_END, }, }; -#if defined(CONFIG_CPU_FREQ_SA1100) || defined(CONFIG_CPU_FREQ_SA1110) -/* rounds up(!) */ -unsigned int sa11x0_freq_to_ppcr(unsigned int khz) -{ - int i; - - khz /= 100; - - for (i = 0; i < NR_FREQS; i++) - if (cclk_frequency_100khz[i] >= khz) - break; - - return i; -} - -unsigned int sa11x0_ppcr_to_freq(unsigned int idx) -{ - unsigned int freq = 0; - if (idx < NR_FREQS) - freq = cclk_frequency_100khz[idx] * 100; - return freq; -} - - -/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on - * this platform, anyway. - */ -int sa11x0_verify_speed(struct cpufreq_policy *policy) -{ - unsigned int tmp; - if (policy->cpu) - return -EINVAL; - - cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); - - /* make sure that at least one frequency is within the policy */ - tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100; - if (tmp > policy->max) - policy->max = tmp; - - cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); - - return 0; -} - unsigned int sa11x0_getspeed(unsigned int cpu) { if (cpu) return 0; - return cclk_frequency_100khz[PPCR & 0xf] * 100; -} - -#else -/* - * We still need to provide this so building without cpufreq works. - */ -unsigned int cpufreq_get(unsigned int cpu) -{ - return cclk_frequency_100khz[PPCR & 0xf] * 100; -} -EXPORT_SYMBOL(cpufreq_get); -#endif - -/* - * This is the SA11x0 sched_clock implementation. This has - * a resolution of 271ns, and a maximum value of 32025597s (370 days). - * - * The return value is guaranteed to be monotonic in that range as - * long as there is always less than 582 seconds between successive - * calls to this function. - * - * ( * 1E9 / 3686400 => * 78125 / 288) - */ -unsigned long long sched_clock(void) -{ - unsigned long long v = cnt32_to_63(OSCR); - - /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */ - v *= 78125<<1; - do_div(v, 288<<1); - - return v; + return sa11x0_freq_table[PPCR & 0xf].frequency; } /* @@ -162,12 +89,31 @@ static void sa1100_power_off(void) PMCR = PMCR_SF; } +void sa11x0_restart(enum reboot_mode mode, const char *cmd) +{ + if (mode == REBOOT_SOFT) { + /* Jump into ROM at address 0 */ + soft_restart(0); + } else { + /* Use on-chip reset capability */ + RSRR = RSRR_SWR; + } +} + +static void sa11x0_register_device(struct platform_device *dev, void *data) +{ + int err; + dev->dev.platform_data = data; + err = platform_device_register(dev); + if (err) + printk(KERN_ERR "Unable to register device %s: %d\n", + dev->name, err); +} + + static struct resource sa11x0udc_resources[] = { - [0] = { - .start = 0x80000000, - .end = 0x8000ffff, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K), + [1] = DEFINE_RES_IRQ(IRQ_Ser0UDC), }; static u64 sa11x0udc_dma_mask = 0xffffffffUL; @@ -184,11 +130,8 @@ static struct platform_device sa11x0udc_device = { }; static struct resource sa11x0uart1_resources[] = { - [0] = { - .start = 0x80010000, - .end = 0x8001ffff, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K), + [1] = DEFINE_RES_IRQ(IRQ_Ser1UART), }; static struct platform_device sa11x0uart1_device = { @@ -199,11 +142,8 @@ static struct platform_device sa11x0uart1_device = { }; static struct resource sa11x0uart3_resources[] = { - [0] = { - .start = 0x80050000, - .end = 0x8005ffff, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K), + [1] = DEFINE_RES_IRQ(IRQ_Ser3UART), }; static struct platform_device sa11x0uart3_device = { @@ -214,11 +154,9 @@ static struct platform_device sa11x0uart3_device = { }; static struct resource sa11x0mcp_resources[] = { - [0] = { - .start = 0x80060000, - .end = 0x8006ffff, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K), + [1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4), + [2] = DEFINE_RES_IRQ(IRQ_Ser4MCP), }; static u64 sa11x0mcp_dma_mask = 0xffffffffUL; @@ -234,17 +172,24 @@ static struct platform_device sa11x0mcp_device = { .resource = sa11x0mcp_resources, }; -void sa11x0_set_mcp_data(struct mcp_plat_data *data) +void __init sa11x0_ppc_configure_mcp(void) { - sa11x0mcp_device.dev.platform_data = data; + /* Setup the PPC unit for the MCP */ + PPDR &= ~PPC_RXD4; + PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; + PSDR |= PPC_RXD4; + PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); + PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); +} + +void sa11x0_register_mcp(struct mcp_plat_data *data) +{ + sa11x0_register_device(&sa11x0mcp_device, data); } static struct resource sa11x0ssp_resources[] = { - [0] = { - .start = 0x80070000, - .end = 0x8007ffff, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM(0x80070000, SZ_64K), + [1] = DEFINE_RES_IRQ(IRQ_Ser4SSP), }; static u64 sa11x0ssp_dma_mask = 0xffffffffUL; @@ -261,16 +206,8 @@ static struct platform_device sa11x0ssp_device = { }; static struct resource sa11x0fb_resources[] = { - [0] = { - .start = 0xb0100000, - .end = 0xb010ffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_LCD, - .end = IRQ_LCD, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K), + [1] = DEFINE_RES_IRQ(IRQ_LCD), }; static struct platform_device sa11x0fb_device = { @@ -283,6 +220,11 @@ static struct platform_device sa11x0fb_device = { .resource = sa11x0fb_resources, }; +void sa11x0_register_lcd(struct sa1100fb_mach_info *inf) +{ + sa11x0_register_device(&sa11x0fb_device, inf); +} + static struct platform_device sa11x0pcmcia_device = { .name = "sa11x0-pcmcia", .id = -1, @@ -293,33 +235,20 @@ static struct platform_device sa11x0mtd_device = { .id = -1, }; -void sa11x0_set_flash_data(struct flash_platform_data *flash, - struct resource *res, int nr) +void sa11x0_register_mtd(struct flash_platform_data *flash, + struct resource *res, int nr) { flash->name = "sa1100"; - sa11x0mtd_device.dev.platform_data = flash; sa11x0mtd_device.resource = res; sa11x0mtd_device.num_resources = nr; + sa11x0_register_device(&sa11x0mtd_device, flash); } static struct resource sa11x0ir_resources[] = { - { - .start = __PREG(Ser2UTCR0), - .end = __PREG(Ser2UTCR0) + 0x24 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = __PREG(Ser2HSCR0), - .end = __PREG(Ser2HSCR0) + 0x1c - 1, - .flags = IORESOURCE_MEM, - }, { - .start = __PREG(Ser2HSCR2), - .end = __PREG(Ser2HSCR2) + 0x04 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_Ser2ICP, - .end = IRQ_Ser2ICP, - .flags = IORESOURCE_IRQ, - } + DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24), + DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c), + DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04), + DEFINE_RES_IRQ(IRQ_Ser2ICP), }; static struct platform_device sa11x0ir_device = { @@ -329,46 +258,69 @@ static struct platform_device sa11x0ir_device = { .resource = sa11x0ir_resources, }; -void sa11x0_set_irda_data(struct irda_platform_data *irda) +void sa11x0_register_irda(struct irda_platform_data *irda) { - sa11x0ir_device.dev.platform_data = irda; + sa11x0_register_device(&sa11x0ir_device, irda); } +static struct resource sa1100_rtc_resources[] = { + DEFINE_RES_MEM(0x90010000, 0x40), + DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"), + DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"), +}; + static struct platform_device sa11x0rtc_device = { .name = "sa1100-rtc", .id = -1, + .num_resources = ARRAY_SIZE(sa1100_rtc_resources), + .resource = sa1100_rtc_resources, +}; + +static struct resource sa11x0dma_resources[] = { + DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE), + DEFINE_RES_IRQ(IRQ_DMA0), + DEFINE_RES_IRQ(IRQ_DMA1), + DEFINE_RES_IRQ(IRQ_DMA2), + DEFINE_RES_IRQ(IRQ_DMA3), + DEFINE_RES_IRQ(IRQ_DMA4), + DEFINE_RES_IRQ(IRQ_DMA5), +}; + +static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device sa11x0dma_device = { + .name = "sa11x0-dma", + .id = -1, + .dev = { + .dma_mask = &sa11x0dma_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(sa11x0dma_resources), + .resource = sa11x0dma_resources, }; static struct platform_device *sa11x0_devices[] __initdata = { &sa11x0udc_device, &sa11x0uart1_device, &sa11x0uart3_device, - &sa11x0mcp_device, &sa11x0ssp_device, &sa11x0pcmcia_device, - &sa11x0fb_device, - &sa11x0mtd_device, &sa11x0rtc_device, + &sa11x0dma_device, }; static int __init sa1100_init(void) { pm_power_off = sa1100_power_off; - - if (sa11x0ir_device.dev.platform_data) - platform_device_register(&sa11x0ir_device); - return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices)); } arch_initcall(sa1100_init); -void (*sa1100fb_backlight_power)(int on); -void (*sa1100fb_lcd_power)(int on); - -EXPORT_SYMBOL(sa1100fb_backlight_power); -EXPORT_SYMBOL(sa1100fb_lcd_power); - +void __init sa11x0_init_late(void) +{ + sa11x0_pm_init(); +} /* * Common I/O mapping: @@ -423,7 +375,7 @@ void __init sa1100_map_io(void) * the MBGNT signal false to ensure the SA1111 doesn't own the * SDRAM bus. */ -void __init sa1110_mb_disable(void) +void sa1110_mb_disable(void) { unsigned long flags; @@ -442,7 +394,7 @@ void __init sa1110_mb_disable(void) * If the system is going to use the SA-1111 DMA engines, set up * the memory bus request/grant pins. */ -void __devinit sa1110_mb_enable(void) +void sa1110_mb_enable(void) { unsigned long flags; diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h index 793c2e6c991..0d92e119b36 100644 --- a/arch/arm/mach-sa1100/generic.h +++ b/arch/arm/mach-sa1100/generic.h @@ -3,43 +3,44 @@ * * Author: Nicolas Pitre */ +#include <linux/cpufreq.h> +#include <linux/reboot.h> -struct sys_timer; - -extern struct sys_timer sa1100_timer; +extern void sa1100_timer_init(void); extern void __init sa1100_map_io(void); extern void __init sa1100_init_irq(void); extern void __init sa1100_init_gpio(void); +extern void sa11x0_restart(enum reboot_mode, const char *); +extern void sa11x0_init_late(void); #define SET_BANK(__nr,__start,__size) \ mi->bank[__nr].start = (__start), \ - mi->bank[__nr].size = (__size), \ - mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27) - -extern void (*sa1100fb_backlight_power)(int on); -extern void (*sa1100fb_lcd_power)(int on); + mi->bank[__nr].size = (__size) extern void sa1110_mb_enable(void); extern void sa1110_mb_disable(void); -struct cpufreq_policy; - -extern unsigned int sa11x0_freq_to_ppcr(unsigned int khz); -extern int sa11x0_verify_speed(struct cpufreq_policy *policy); +extern struct cpufreq_frequency_table sa11x0_freq_table[]; extern unsigned int sa11x0_getspeed(unsigned int cpu); -extern unsigned int sa11x0_ppcr_to_freq(unsigned int idx); struct flash_platform_data; struct resource; -extern void sa11x0_set_flash_data(struct flash_platform_data *flash, - struct resource *res, int nr); - -struct sa11x0_ssp_plat_ops; -extern void sa11x0_set_ssp_data(struct sa11x0_ssp_plat_ops *ops); +void sa11x0_register_mtd(struct flash_platform_data *flash, + struct resource *res, int nr); struct irda_platform_data; -void sa11x0_set_irda_data(struct irda_platform_data *irda); +void sa11x0_register_irda(struct irda_platform_data *irda); struct mcp_plat_data; -void sa11x0_set_mcp_data(struct mcp_plat_data *data); +void sa11x0_ppc_configure_mcp(void); +void sa11x0_register_mcp(struct mcp_plat_data *data); + +struct sa1100fb_mach_info; +void sa11x0_register_lcd(struct sa1100fb_mach_info *inf); + +#ifdef CONFIG_PM +int sa11x0_pm_init(void); +#else +static inline int sa11x0_pm_init(void) { return 0; } +#endif diff --git a/arch/arm/mach-sa1100/gpio.c b/arch/arm/mach-sa1100/gpio.c deleted file mode 100644 index 0d3829a8c2c..00000000000 --- a/arch/arm/mach-sa1100/gpio.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * linux/arch/arm/mach-sa1100/gpio.c - * - * Generic SA-1100 GPIO handling - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/init.h> -#include <linux/module.h> - -#include <asm/gpio.h> -#include <mach/hardware.h> -#include "generic.h" - -static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - return GPLR & GPIO_GPIO(offset); -} - -static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -{ - if (value) - GPSR = GPIO_GPIO(offset); - else - GPCR = GPIO_GPIO(offset); -} - -static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset) -{ - unsigned long flags; - - local_irq_save(flags); - GPDR &= ~GPIO_GPIO(offset); - local_irq_restore(flags); - return 0; -} - -static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value) -{ - unsigned long flags; - - local_irq_save(flags); - sa1100_gpio_set(chip, offset, value); - GPDR |= GPIO_GPIO(offset); - local_irq_restore(flags); - return 0; -} - -static struct gpio_chip sa1100_gpio_chip = { - .label = "gpio", - .direction_input = sa1100_direction_input, - .direction_output = sa1100_direction_output, - .set = sa1100_gpio_set, - .get = sa1100_gpio_get, - .base = 0, - .ngpio = GPIO_MAX + 1, -}; - -void __init sa1100_init_gpio(void) -{ - gpiochip_add(&sa1100_gpio_chip); -} diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c new file mode 100644 index 00000000000..3c43219bc88 --- /dev/null +++ b/arch/arm/mach-sa1100/h3100.c @@ -0,0 +1,143 @@ +/* + * Support for Compaq iPAQ H3100 handheld computer + * + * Copyright (c) 2000,1 Compaq Computer Corporation. (Author: Jamey Hicks) + * Copyright (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/gpio.h> + +#include <video/sa1100fb.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/irda.h> + +#include <mach/h3xxx.h> +#include <mach/irqs.h> + +#include "generic.h" + +/* + * helper for sa1100fb + */ +static struct gpio h3100_lcd_gpio[] = { + { H3100_GPIO_LCD_3V_ON, GPIOF_OUT_INIT_LOW, "LCD 3V" }, + { H3XXX_EGPIO_LCD_ON, GPIOF_OUT_INIT_LOW, "LCD ON" }, +}; + +static bool h3100_lcd_request(void) +{ + static bool h3100_lcd_ok; + int rc; + + if (h3100_lcd_ok) + return true; + + rc = gpio_request_array(h3100_lcd_gpio, ARRAY_SIZE(h3100_lcd_gpio)); + if (rc) + pr_err("%s: can't request GPIOs\n", __func__); + else + h3100_lcd_ok = true; + + return h3100_lcd_ok; +} + +static void h3100_lcd_power(int enable) +{ + if (!h3100_lcd_request()) + return; + + gpio_set_value(H3100_GPIO_LCD_3V_ON, enable); + gpio_set_value(H3XXX_EGPIO_LCD_ON, enable); +} + +static struct sa1100fb_mach_info h3100_lcd_info = { + .pixclock = 406977, .bpp = 4, + .xres = 320, .yres = 240, + + .hsync_len = 26, .vsync_len = 41, + .left_margin = 4, .upper_margin = 0, + .right_margin = 4, .lower_margin = 0, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .cmap_greyscale = 1, + .cmap_inverse = 1, + + .lccr0 = LCCR0_Mono | LCCR0_4PixMono | LCCR0_Sngl | LCCR0_Pas, + .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2), + + .lcd_power = h3100_lcd_power, +}; + +static void __init h3100_map_io(void) +{ + h3xxx_map_io(); + + /* Older bootldrs put GPIO2-9 in alternate mode on the + assumption that they are used for video */ + GAFR &= ~0x000001fb; +} + +/* + * This turns the IRDA power on or off on the Compaq H3100 + */ +static struct gpio h3100_irda_gpio[] = { + { H3100_GPIO_IR_ON, GPIOF_OUT_INIT_LOW, "IrDA power" }, + { H3100_GPIO_IR_FSEL, GPIOF_OUT_INIT_LOW, "IrDA fsel" }, +}; + +static int h3100_irda_set_power(struct device *dev, unsigned int state) +{ + gpio_set_value(H3100_GPIO_IR_ON, state); + return 0; +} + +static void h3100_irda_set_speed(struct device *dev, unsigned int speed) +{ + gpio_set_value(H3100_GPIO_IR_FSEL, !(speed < 4000000)); +} + +static int h3100_irda_startup(struct device *dev) +{ + return gpio_request_array(h3100_irda_gpio, sizeof(h3100_irda_gpio)); +} + +static void h3100_irda_shutdown(struct device *dev) +{ + return gpio_free_array(h3100_irda_gpio, sizeof(h3100_irda_gpio)); +} + +static struct irda_platform_data h3100_irda_data = { + .set_power = h3100_irda_set_power, + .set_speed = h3100_irda_set_speed, + .startup = h3100_irda_startup, + .shutdown = h3100_irda_shutdown, +}; + +static void __init h3100_mach_init(void) +{ + h3xxx_mach_init(); + + sa11x0_register_lcd(&h3100_lcd_info); + sa11x0_register_irda(&h3100_irda_data); +} + +MACHINE_START(H3100, "Compaq iPAQ H3100") + .atag_offset = 0x100, + .map_io = h3100_map_io, + .nr_irqs = SA1100_NR_IRQS, + .init_irq = sa1100_init_irq, + .init_time = sa1100_timer_init, + .init_machine = h3100_mach_init, + .init_late = sa11x0_init_late, + .restart = sa11x0_restart, +MACHINE_END + diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c index af25a78d705..5be54c214c7 100644 --- a/arch/arm/mach-sa1100/h3600.c +++ b/arch/arm/mach-sa1100/h3600.c @@ -1,906 +1,151 @@ /* - * Hardware definitions for Compaq iPAQ H3xxx Handheld Computers + * Support for Compaq iPAQ H3600 handheld computer * - * Copyright 2000,1 Compaq Computer Corporation. + * Copyright (c) 2000,1 Compaq Computer Corporation. (Author: Jamey Hicks) + * Copyright (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru> * - * Use consistent with the GNU GPL is permitted, - * provided that this copyright notice is - * preserved in its entirety in all copies and derived works. - * - * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, - * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS - * FITNESS FOR ANY PARTICULAR PURPOSE. - * - * Author: Jamey Hicks. - * - * History: - * - * 2001-10-?? Andrew Christian Added support for iPAQ H3800 - * and abstracted EGPIO interface. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. * */ -#include <linux/module.h> + #include <linux/init.h> #include <linux/kernel.h> -#include <linux/tty.h> -#include <linux/pm.h> -#include <linux/device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/serial_core.h> +#include <linux/gpio.h> -#include <asm/irq.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/setup.h> +#include <video/sa1100fb.h> -#include <asm/mach/irq.h> +#include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/irda.h> -#include <asm/mach/map.h> -#include <asm/mach/serial_sa1100.h> -#include <mach/h3600.h> - -#if defined (CONFIG_SA1100_H3600) || defined (CONFIG_SA1100_H3100) -#include <mach/h3600_gpio.h> -#endif - -#ifdef CONFIG_SA1100_H3800 -#include <mach/h3600_asic.h> -#endif +#include <mach/h3xxx.h> +#include <mach/irqs.h> #include "generic.h" -struct ipaq_model_ops ipaq_model_ops; -EXPORT_SYMBOL(ipaq_model_ops); - -static struct mtd_partition h3xxx_partitions[] = { - { - .name = "H3XXX boot firmware", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { -#ifdef CONFIG_MTD_2PARTS_IPAQ - .name = "H3XXX root jffs2", - .size = MTDPART_SIZ_FULL, - .offset = 0x00040000, -#else - .name = "H3XXX kernel", - .size = 0x00080000, - .offset = 0x00040000, - }, { - .name = "H3XXX params", - .size = 0x00040000, - .offset = 0x000C0000, - }, { -#ifdef CONFIG_JFFS2_FS - .name = "H3XXX root jffs2", - .size = MTDPART_SIZ_FULL, - .offset = 0x00100000, -#else - .name = "H3XXX initrd", - .size = 0x00100000, - .offset = 0x00100000, - }, { - .name = "H3XXX root cramfs", - .size = 0x00300000, - .offset = 0x00200000, - }, { - .name = "H3XXX usr cramfs", - .size = 0x00800000, - .offset = 0x00500000, - }, { - .name = "H3XXX usr local", - .size = MTDPART_SIZ_FULL, - .offset = 0x00d00000, -#endif -#endif - } -}; - -static void h3xxx_set_vpp(int vpp) -{ - assign_h3600_egpio(IPAQ_EGPIO_VPP_ON, vpp); -} - -static struct flash_platform_data h3xxx_flash_data = { - .map_name = "cfi_probe", - .set_vpp = h3xxx_set_vpp, - .parts = h3xxx_partitions, - .nr_parts = ARRAY_SIZE(h3xxx_partitions), -}; - -static struct resource h3xxx_flash_resource = { - .start = SA1100_CS0_PHYS, - .end = SA1100_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -/* - * This turns the IRDA power on or off on the Compaq H3600 - */ -static int h3600_irda_set_power(struct device *dev, unsigned int state) -{ - assign_h3600_egpio( IPAQ_EGPIO_IR_ON, state ); - - return 0; -} - -static void h3600_irda_set_speed(struct device *dev, unsigned int speed) -{ - if (speed < 4000000) { - clr_h3600_egpio(IPAQ_EGPIO_IR_FSEL); - } else { - set_h3600_egpio(IPAQ_EGPIO_IR_FSEL); - } -} - -static struct irda_platform_data h3600_irda_data = { - .set_power = h3600_irda_set_power, - .set_speed = h3600_irda_set_speed, -}; - -static void h3xxx_mach_init(void) -{ - sa11x0_set_flash_data(&h3xxx_flash_data, &h3xxx_flash_resource, 1); - sa11x0_set_irda_data(&h3600_irda_data); -} - -/* - * low-level UART features - */ - -static void h3600_uart_set_mctrl(struct uart_port *port, u_int mctrl) -{ - if (port->mapbase == _Ser3UTCR0) { - if (mctrl & TIOCM_RTS) - GPCR = GPIO_H3600_COM_RTS; - else - GPSR = GPIO_H3600_COM_RTS; - } -} - -static u_int h3600_uart_get_mctrl(struct uart_port *port) -{ - u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; - - if (port->mapbase == _Ser3UTCR0) { - int gplr = GPLR; - /* DCD and CTS bits are inverted in GPLR by RS232 transceiver */ - if (gplr & GPIO_H3600_COM_DCD) - ret &= ~TIOCM_CD; - if (gplr & GPIO_H3600_COM_CTS) - ret &= ~TIOCM_CTS; - } - - return ret; -} - -static void h3600_uart_pm(struct uart_port *port, u_int state, u_int oldstate) -{ - if (port->mapbase == _Ser2UTCR0) { /* TODO: REMOVE THIS */ - assign_h3600_egpio(IPAQ_EGPIO_IR_ON, !state); - } else if (port->mapbase == _Ser3UTCR0) { - assign_h3600_egpio(IPAQ_EGPIO_RS232_ON, !state); - } -} - -/* - * Enable/Disable wake up events for this serial port. - * Obviously, we only support this on the normal COM port. - */ -static int h3600_uart_set_wake(struct uart_port *port, u_int enable) -{ - int err = -EINVAL; - - if (port->mapbase == _Ser3UTCR0) { - if (enable) - PWER |= PWER_GPIO23 | PWER_GPIO25; /* DCD and CTS */ - else - PWER &= ~(PWER_GPIO23 | PWER_GPIO25); /* DCD and CTS */ - err = 0; - } - return err; -} - -static struct sa1100_port_fns h3600_port_fns __initdata = { - .set_mctrl = h3600_uart_set_mctrl, - .get_mctrl = h3600_uart_get_mctrl, - .pm = h3600_uart_pm, - .set_wake = h3600_uart_set_wake, -}; - /* * helper for sa1100fb */ -static void h3xxx_lcd_power(int enable) -{ - assign_h3600_egpio(IPAQ_EGPIO_LCD_POWER, enable); -} - -static struct map_desc h3600_io_desc[] __initdata = { - { /* static memory bank 2 CS#2 */ - .virtual = H3600_BANK_2_VIRT, - .pfn = __phys_to_pfn(SA1100_CS2_PHYS), - .length = 0x02800000, - .type = MT_DEVICE - }, { /* static memory bank 4 CS#4 */ - .virtual = H3600_BANK_4_VIRT, - .pfn = __phys_to_pfn(SA1100_CS4_PHYS), - .length = 0x00800000, - .type = MT_DEVICE - }, { /* EGPIO 0 CS#5 */ - .virtual = H3600_EGPIO_VIRT, - .pfn = __phys_to_pfn(H3600_EGPIO_PHYS), - .length = 0x01000000, - .type = MT_DEVICE - } +static struct gpio h3600_lcd_gpio[] = { + { H3XXX_EGPIO_LCD_ON, GPIOF_OUT_INIT_LOW, "LCD power" }, + { H3600_EGPIO_LCD_PCI, GPIOF_OUT_INIT_LOW, "LCD control" }, + { H3600_EGPIO_LCD_5V_ON, GPIOF_OUT_INIT_LOW, "LCD 5v" }, + { H3600_EGPIO_LVDD_ON, GPIOF_OUT_INIT_LOW, "LCD 9v/-6.5v" }, }; -/* - * Common map_io initialization - */ - -static void __init h3xxx_map_io(void) +static bool h3600_lcd_request(void) { - sa1100_map_io(); - iotable_init(h3600_io_desc, ARRAY_SIZE(h3600_io_desc)); - - sa1100_register_uart_fns(&h3600_port_fns); - sa1100_register_uart(0, 3); /* Common serial port */ -// sa1100_register_uart(1, 1); /* Microcontroller on 3100/3600 */ - - /* Ensure those pins are outputs and driving low */ - PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; - PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); - - /* Configure suspend conditions */ - PGSR = 0; - PWER = PWER_GPIO0 | PWER_RTC; - PCFR = PCFR_OPDE; - PSDR = 0; - - sa1100fb_lcd_power = h3xxx_lcd_power; -} - -static __inline__ void do_blank(int setp) -{ - if (ipaq_model_ops.blank_callback) - ipaq_model_ops.blank_callback(1-setp); -} - -/************************* H3100 *************************/ - -#ifdef CONFIG_SA1100_H3100 - -#define H3100_EGPIO (*(volatile unsigned int *)H3600_EGPIO_VIRT) -static unsigned int h3100_egpio = 0; + static bool h3600_lcd_ok; + int rc; -static void h3100_control_egpio(enum ipaq_egpio_type x, int setp) -{ - unsigned int egpio = 0; - long gpio = 0; - unsigned long flags; + if (h3600_lcd_ok) + return true; - switch (x) { - case IPAQ_EGPIO_LCD_POWER: - egpio |= EGPIO_H3600_LCD_ON; - gpio |= GPIO_H3100_LCD_3V_ON; - do_blank(setp); - break; - case IPAQ_EGPIO_LCD_ENABLE: - break; - case IPAQ_EGPIO_CODEC_NRESET: - egpio |= EGPIO_H3600_CODEC_NRESET; - break; - case IPAQ_EGPIO_AUDIO_ON: - gpio |= GPIO_H3100_AUD_PWR_ON - | GPIO_H3100_AUD_ON; - break; - case IPAQ_EGPIO_QMUTE: - gpio |= GPIO_H3100_QMUTE; - break; - case IPAQ_EGPIO_OPT_NVRAM_ON: - egpio |= EGPIO_H3600_OPT_NVRAM_ON; - break; - case IPAQ_EGPIO_OPT_ON: - egpio |= EGPIO_H3600_OPT_ON; - break; - case IPAQ_EGPIO_CARD_RESET: - egpio |= EGPIO_H3600_CARD_RESET; - break; - case IPAQ_EGPIO_OPT_RESET: - egpio |= EGPIO_H3600_OPT_RESET; - break; - case IPAQ_EGPIO_IR_ON: - gpio |= GPIO_H3100_IR_ON; - break; - case IPAQ_EGPIO_IR_FSEL: - gpio |= GPIO_H3100_IR_FSEL; - break; - case IPAQ_EGPIO_RS232_ON: - egpio |= EGPIO_H3600_RS232_ON; - break; - case IPAQ_EGPIO_VPP_ON: - egpio |= EGPIO_H3600_VPP_ON; - break; - } + rc = gpio_request_array(h3600_lcd_gpio, ARRAY_SIZE(h3600_lcd_gpio)); + if (rc) + pr_err("%s: can't request GPIOs\n", __func__); + else + h3600_lcd_ok = true; - if (egpio || gpio) { - local_irq_save(flags); - if (setp) { - h3100_egpio |= egpio; - GPSR = gpio; - } else { - h3100_egpio &= ~egpio; - GPCR = gpio; - } - H3100_EGPIO = h3100_egpio; - local_irq_restore(flags); - } + return h3600_lcd_ok; } -static unsigned long h3100_read_egpio(void) +static void h3600_lcd_power(int enable) { - return h3100_egpio; -} + if (!h3600_lcd_request()) + return; -static int h3100_pm_callback(int req) -{ - if (ipaq_model_ops.pm_callback_aux) - return ipaq_model_ops.pm_callback_aux(req); - return 0; + gpio_direction_output(H3XXX_EGPIO_LCD_ON, enable); + gpio_direction_output(H3600_EGPIO_LCD_PCI, enable); + gpio_direction_output(H3600_EGPIO_LCD_5V_ON, enable); + gpio_direction_output(H3600_EGPIO_LVDD_ON, enable); } -static struct ipaq_model_ops h3100_model_ops __initdata = { - .generic_name = "3100", - .control = h3100_control_egpio, - .read = h3100_read_egpio, - .pm_callback = h3100_pm_callback +static const struct sa1100fb_rgb h3600_rgb_16 = { + .red = { .offset = 12, .length = 4, }, + .green = { .offset = 7, .length = 4, }, + .blue = { .offset = 1, .length = 4, }, + .transp = { .offset = 0, .length = 0, }, }; -#define H3100_DIRECT_EGPIO (GPIO_H3100_BT_ON \ - | GPIO_H3100_GPIO3 \ - | GPIO_H3100_QMUTE \ - | GPIO_H3100_LCD_3V_ON \ - | GPIO_H3100_AUD_ON \ - | GPIO_H3100_AUD_PWR_ON \ - | GPIO_H3100_IR_ON \ - | GPIO_H3100_IR_FSEL) - -static void __init h3100_map_io(void) -{ - h3xxx_map_io(); - - /* Initialize h3100-specific values here */ - GPCR = 0x0fffffff; /* All outputs are set low by default */ - GPDR = GPIO_H3600_COM_RTS | GPIO_H3600_L3_CLOCK | - GPIO_H3600_L3_MODE | GPIO_H3600_L3_DATA | - GPIO_H3600_CLK_SET1 | GPIO_H3600_CLK_SET0 | - H3100_DIRECT_EGPIO; - - /* Older bootldrs put GPIO2-9 in alternate mode on the - assumption that they are used for video */ - GAFR &= ~H3100_DIRECT_EGPIO; - - H3100_EGPIO = h3100_egpio; - ipaq_model_ops = h3100_model_ops; -} - -MACHINE_START(H3100, "Compaq iPAQ H3100") - .phys_io = 0x80000000, - .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc, - .boot_params = 0xc0000100, - .map_io = h3100_map_io, - .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, - .init_machine = h3xxx_mach_init, -MACHINE_END - -#endif /* CONFIG_SA1100_H3100 */ +static struct sa1100fb_mach_info h3600_lcd_info = { + .pixclock = 174757, .bpp = 16, + .xres = 320, .yres = 240, -/************************* H3600 *************************/ + .hsync_len = 3, .vsync_len = 3, + .left_margin = 12, .upper_margin = 10, + .right_margin = 17, .lower_margin = 1, -#ifdef CONFIG_SA1100_H3600 + .cmap_static = 1, -#define H3600_EGPIO (*(volatile unsigned int *)H3600_EGPIO_VIRT) -static unsigned int h3600_egpio = EGPIO_H3600_RS232_ON; - -static void h3600_control_egpio(enum ipaq_egpio_type x, int setp) -{ - unsigned int egpio = 0; - unsigned long flags; - - switch (x) { - case IPAQ_EGPIO_LCD_POWER: - egpio |= EGPIO_H3600_LCD_ON | - EGPIO_H3600_LCD_PCI | - EGPIO_H3600_LCD_5V_ON | - EGPIO_H3600_LVDD_ON; - do_blank(setp); - break; - case IPAQ_EGPIO_LCD_ENABLE: - break; - case IPAQ_EGPIO_CODEC_NRESET: - egpio |= EGPIO_H3600_CODEC_NRESET; - break; - case IPAQ_EGPIO_AUDIO_ON: - egpio |= EGPIO_H3600_AUD_AMP_ON | - EGPIO_H3600_AUD_PWR_ON; - break; - case IPAQ_EGPIO_QMUTE: - egpio |= EGPIO_H3600_QMUTE; - break; - case IPAQ_EGPIO_OPT_NVRAM_ON: - egpio |= EGPIO_H3600_OPT_NVRAM_ON; - break; - case IPAQ_EGPIO_OPT_ON: - egpio |= EGPIO_H3600_OPT_ON; - break; - case IPAQ_EGPIO_CARD_RESET: - egpio |= EGPIO_H3600_CARD_RESET; - break; - case IPAQ_EGPIO_OPT_RESET: - egpio |= EGPIO_H3600_OPT_RESET; - break; - case IPAQ_EGPIO_IR_ON: - egpio |= EGPIO_H3600_IR_ON; - break; - case IPAQ_EGPIO_IR_FSEL: - egpio |= EGPIO_H3600_IR_FSEL; - break; - case IPAQ_EGPIO_RS232_ON: - egpio |= EGPIO_H3600_RS232_ON; - break; - case IPAQ_EGPIO_VPP_ON: - egpio |= EGPIO_H3600_VPP_ON; - break; - } - - if (egpio) { - local_irq_save(flags); - if (setp) - h3600_egpio |= egpio; - else - h3600_egpio &= ~egpio; - H3600_EGPIO = h3600_egpio; - local_irq_restore(flags); - } -} + .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act, + .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2), -static unsigned long h3600_read_egpio(void) -{ - return h3600_egpio; -} - -static int h3600_pm_callback(int req) -{ - if (ipaq_model_ops.pm_callback_aux) - return ipaq_model_ops.pm_callback_aux(req); - return 0; -} + .rgb[RGB_16] = &h3600_rgb_16, -static struct ipaq_model_ops h3600_model_ops __initdata = { - .generic_name = "3600", - .control = h3600_control_egpio, - .read = h3600_read_egpio, - .pm_callback = h3600_pm_callback + .lcd_power = h3600_lcd_power, }; + static void __init h3600_map_io(void) { h3xxx_map_io(); - - /* Initialize h3600-specific values here */ - - GPCR = 0x0fffffff; /* All outputs are set low by default */ - GPDR = GPIO_H3600_COM_RTS | GPIO_H3600_L3_CLOCK | - GPIO_H3600_L3_MODE | GPIO_H3600_L3_DATA | - GPIO_H3600_CLK_SET1 | GPIO_H3600_CLK_SET0 | - GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 | - GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8; - - H3600_EGPIO = h3600_egpio; /* Maintains across sleep? */ - ipaq_model_ops = h3600_model_ops; } -MACHINE_START(H3600, "Compaq iPAQ H3600") - .phys_io = 0x80000000, - .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc, - .boot_params = 0xc0000100, - .map_io = h3600_map_io, - .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, - .init_machine = h3xxx_mach_init, -MACHINE_END - -#endif /* CONFIG_SA1100_H3600 */ - -#ifdef CONFIG_SA1100_H3800 - -#define SET_ASIC1(x) \ - do {if (setp) { H3800_ASIC1_GPIO_OUT |= (x); } else { H3800_ASIC1_GPIO_OUT &= ~(x); }} while(0) - -#define SET_ASIC2(x) \ - do {if (setp) { H3800_ASIC2_GPIOPIOD |= (x); } else { H3800_ASIC2_GPIOPIOD &= ~(x); }} while(0) - -#define CLEAR_ASIC1(x) \ - do {if (setp) { H3800_ASIC1_GPIO_OUT &= ~(x); } else { H3800_ASIC1_GPIO_OUT |= (x); }} while(0) - -#define CLEAR_ASIC2(x) \ - do {if (setp) { H3800_ASIC2_GPIOPIOD &= ~(x); } else { H3800_ASIC2_GPIOPIOD |= (x); }} while(0) - - /* - On screen enable, we get - - h3800_video_power_on(1) - LCD controller starts - h3800_video_lcd_enable(1) - - On screen disable, we get - - h3800_video_lcd_enable(0) - LCD controller stops - h3800_video_power_on(0) -*/ - - -static void h3800_video_power_on(int setp) -{ - if (setp) { - H3800_ASIC1_GPIO_OUT |= GPIO1_LCD_ON; - msleep(30); - H3800_ASIC1_GPIO_OUT |= GPIO1_VGL_ON; - msleep(5); - H3800_ASIC1_GPIO_OUT |= GPIO1_VGH_ON; - msleep(50); - H3800_ASIC1_GPIO_OUT |= GPIO1_LCD_5V_ON; - msleep(5); - } else { - msleep(5); - H3800_ASIC1_GPIO_OUT &= ~GPIO1_LCD_5V_ON; - msleep(50); - H3800_ASIC1_GPIO_OUT &= ~GPIO1_VGL_ON; - msleep(5); - H3800_ASIC1_GPIO_OUT &= ~GPIO1_VGH_ON; - msleep(100); - H3800_ASIC1_GPIO_OUT &= ~GPIO1_LCD_ON; - } -} - -static void h3800_video_lcd_enable(int setp) -{ - if (setp) { - msleep(17); // Wait one from before turning on - H3800_ASIC1_GPIO_OUT |= GPIO1_LCD_PCI; - } else { - H3800_ASIC1_GPIO_OUT &= ~GPIO1_LCD_PCI; - msleep(30); // Wait before turning off - } -} - - -static void h3800_control_egpio(enum ipaq_egpio_type x, int setp) -{ - switch (x) { - case IPAQ_EGPIO_LCD_POWER: - h3800_video_power_on(setp); - break; - case IPAQ_EGPIO_LCD_ENABLE: - h3800_video_lcd_enable(setp); - break; - case IPAQ_EGPIO_CODEC_NRESET: - case IPAQ_EGPIO_AUDIO_ON: - case IPAQ_EGPIO_QMUTE: - printk("%s: error - should not be called\n", __func__); - break; - case IPAQ_EGPIO_OPT_NVRAM_ON: - SET_ASIC2(GPIO2_OPT_ON_NVRAM); - break; - case IPAQ_EGPIO_OPT_ON: - SET_ASIC2(GPIO2_OPT_ON); - break; - case IPAQ_EGPIO_CARD_RESET: - SET_ASIC2(GPIO2_OPT_PCM_RESET); - break; - case IPAQ_EGPIO_OPT_RESET: - SET_ASIC2(GPIO2_OPT_RESET); - break; - case IPAQ_EGPIO_IR_ON: - CLEAR_ASIC1(GPIO1_IR_ON_N); - break; - case IPAQ_EGPIO_IR_FSEL: - break; - case IPAQ_EGPIO_RS232_ON: - SET_ASIC1(GPIO1_RS232_ON); - break; - case IPAQ_EGPIO_VPP_ON: - H3800_ASIC2_FlashWP_VPP_ON = setp; - break; - } -} - -static unsigned long h3800_read_egpio(void) -{ - return H3800_ASIC1_GPIO_OUT | (H3800_ASIC2_GPIOPIOD << 16); -} - -/* We need to fix ASIC2 GPIO over suspend/resume. At the moment, - it doesn't appear that ASIC1 GPIO has the same problem */ - -static int h3800_pm_callback(int req) -{ - static u16 asic1_data; - static u16 asic2_data; - int result = 0; - - printk("%s %d\n", __func__, req); - - switch (req) { - case PM_RESUME: - MSC2 = (MSC2 & 0x0000ffff) | 0xE4510000; /* Set MSC2 correctly */ - - H3800_ASIC2_GPIOPIOD = asic2_data; - H3800_ASIC2_GPIODIR = GPIO2_PEN_IRQ - | GPIO2_SD_DETECT - | GPIO2_EAR_IN_N - | GPIO2_USB_DETECT_N - | GPIO2_SD_CON_SLT; - - H3800_ASIC1_GPIO_OUT = asic1_data; - - if (ipaq_model_ops.pm_callback_aux) - result = ipaq_model_ops.pm_callback_aux(req); - break; - - case PM_SUSPEND: - if (ipaq_model_ops.pm_callback_aux && - ((result = ipaq_model_ops.pm_callback_aux(req)) != 0)) - return result; - - asic1_data = H3800_ASIC1_GPIO_OUT; - asic2_data = H3800_ASIC2_GPIOPIOD; - break; - default: - printk("%s: unrecognized PM callback\n", __func__); - break; - } - return result; -} - -static struct ipaq_model_ops h3800_model_ops __initdata = { - .generic_name = "3800", - .control = h3800_control_egpio, - .read = h3800_read_egpio, - .pm_callback = h3800_pm_callback -}; - -#define MAX_ASIC_ISR_LOOPS 20 - -/* The order of these is important - see #include <mach/irqs.h> */ -static u32 kpio_irq_mask[] = { - KPIO_KEY_ALL, - KPIO_SPI_INT, - KPIO_OWM_INT, - KPIO_ADC_INT, - KPIO_UART_0_INT, - KPIO_UART_1_INT, - KPIO_TIMER_0_INT, - KPIO_TIMER_1_INT, - KPIO_TIMER_2_INT -}; - -static u32 gpio_irq_mask[] = { - GPIO2_PEN_IRQ, - GPIO2_SD_DETECT, - GPIO2_EAR_IN_N, - GPIO2_USB_DETECT_N, - GPIO2_SD_CON_SLT, -}; - -static void h3800_IRQ_demux(unsigned int irq, struct irq_desc *desc) -{ - int i; - - if (0) printk("%s: interrupt received\n", __func__); - - desc->chip->ack(irq); - - for (i = 0; i < MAX_ASIC_ISR_LOOPS && (GPLR & GPIO_H3800_ASIC); i++) { - u32 irq; - int j; - - /* KPIO */ - irq = H3800_ASIC2_KPIINTFLAG; - if (0) printk("%s KPIO 0x%08X\n", __func__, irq); - for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++) - if (irq & kpio_irq_mask[j]) - handle_edge_irq(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j); - - /* GPIO2 */ - irq = H3800_ASIC2_GPIINTFLAG; - if (0) printk("%s GPIO 0x%08X\n", __func__, irq); - for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++) - if (irq & gpio_irq_mask[j]) - handle_edge_irq(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j); - } - - if (i >= MAX_ASIC_ISR_LOOPS) - printk("%s: interrupt processing overrun\n", __func__); - - /* For level-based interrupts */ - desc->chip->unmask(irq); - -} - -static struct irqaction h3800_irq = { - .name = "h3800_asic", - .handler = h3800_IRQ_demux, - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, -}; - -u32 kpio_int_shadow = 0; - - -/* mask_ack <- IRQ is first serviced. - mask <- IRQ is disabled. - unmask <- IRQ is enabled - - The INTCLR registers are poorly documented. I believe that writing - a "1" to the register clears the specific interrupt, but the documentation - indicates writing a "0" clears the interrupt. In any case, they shouldn't - be read (that's the INTFLAG register) + * This turns the IRDA power on or off on the Compaq H3600 */ +static struct gpio h3600_irda_gpio[] = { + { H3600_EGPIO_IR_ON, GPIOF_OUT_INIT_LOW, "IrDA power" }, + { H3600_EGPIO_IR_FSEL, GPIOF_OUT_INIT_LOW, "IrDA fsel" }, +}; -static void h3800_mask_ack_kpio_irq(unsigned int irq) -{ - u32 mask = kpio_irq_mask[irq - H3800_KPIO_IRQ_START]; - kpio_int_shadow &= ~mask; - H3800_ASIC2_KPIINTSTAT = kpio_int_shadow; - H3800_ASIC2_KPIINTCLR = mask; -} - -static void h3800_mask_kpio_irq(unsigned int irq) -{ - u32 mask = kpio_irq_mask[irq - H3800_KPIO_IRQ_START]; - kpio_int_shadow &= ~mask; - H3800_ASIC2_KPIINTSTAT = kpio_int_shadow; -} - -static void h3800_unmask_kpio_irq(unsigned int irq) +static int h3600_irda_set_power(struct device *dev, unsigned int state) { - u32 mask = kpio_irq_mask[irq - H3800_KPIO_IRQ_START]; - kpio_int_shadow |= mask; - H3800_ASIC2_KPIINTSTAT = kpio_int_shadow; + gpio_set_value(H3600_EGPIO_IR_ON, state); + return 0; } -static void h3800_mask_ack_gpio_irq(unsigned int irq) +static void h3600_irda_set_speed(struct device *dev, unsigned int speed) { - u32 mask = gpio_irq_mask[irq - H3800_GPIO_IRQ_START]; - H3800_ASIC2_GPIINTSTAT &= ~mask; - H3800_ASIC2_GPIINTCLR = mask; + gpio_set_value(H3600_EGPIO_IR_FSEL, !(speed < 4000000)); } -static void h3800_mask_gpio_irq(unsigned int irq) +static int h3600_irda_startup(struct device *dev) { - u32 mask = gpio_irq_mask[irq - H3800_GPIO_IRQ_START]; - H3800_ASIC2_GPIINTSTAT &= ~mask; - } - -static void h3800_unmask_gpio_irq(unsigned int irq) -{ - u32 mask = gpio_irq_mask[irq - H3800_GPIO_IRQ_START]; - H3800_ASIC2_GPIINTSTAT |= mask; + return gpio_request_array(h3600_irda_gpio, sizeof(h3600_irda_gpio)); } -static void __init h3800_init_irq(void) +static void h3600_irda_shutdown(struct device *dev) { - int i; - - /* Initialize standard IRQs */ - sa1100_init_irq(); - - /* Disable all IRQs and set up clock */ - H3800_ASIC2_KPIINTSTAT = 0; /* Disable all interrupts */ - H3800_ASIC2_GPIINTSTAT = 0; - - H3800_ASIC2_KPIINTCLR = 0; /* Clear all KPIO interrupts */ - H3800_ASIC2_GPIINTCLR = 0; /* Clear all GPIO interrupts */ - -// H3800_ASIC2_KPIINTCLR = 0xffff; /* Clear all KPIO interrupts */ -// H3800_ASIC2_GPIINTCLR = 0xffff; /* Clear all GPIO interrupts */ - - H3800_ASIC2_CLOCK_Enable |= ASIC2_CLOCK_EX0; /* 32 kHZ crystal on */ - H3800_ASIC2_INTR_ClockPrescale |= ASIC2_INTCPS_SET; - H3800_ASIC2_INTR_ClockPrescale = ASIC2_INTCPS_CPS(0x0e) | ASIC2_INTCPS_SET; - H3800_ASIC2_INTR_TimerSet = 1; - -#if 0 - for (i = 0; i < H3800_KPIO_IRQ_COUNT; i++) { - int irq = i + H3800_KPIO_IRQ_START; - irq_desc[irq].valid = 1; - irq_desc[irq].probe_ok = 1; - set_irq_chip(irq, &h3800_kpio_irqchip); - } - - for (i = 0; i < H3800_GPIO_IRQ_COUNT; i++) { - int irq = i + H3800_GPIO_IRQ_START; - irq_desc[irq].valid = 1; - irq_desc[irq].probe_ok = 1; - set_irq_chip(irq, &h3800_gpio_irqchip); - } -#endif - set_irq_type(IRQ_GPIO_H3800_ASIC, IRQ_TYPE_EDGE_RISING); - set_irq_chained_handler(IRQ_GPIO_H3800_ASIC, h3800_IRQ_demux); + return gpio_free_array(h3600_irda_gpio, sizeof(h3600_irda_gpio)); } +static struct irda_platform_data h3600_irda_data = { + .set_power = h3600_irda_set_power, + .set_speed = h3600_irda_set_speed, + .startup = h3600_irda_startup, + .shutdown = h3600_irda_shutdown, +}; -#define ASIC1_OUTPUTS 0x7fff /* First 15 bits are used */ - -static void __init h3800_map_io(void) +static void __init h3600_mach_init(void) { - h3xxx_map_io(); - - /* Add wakeup on AC plug/unplug */ - PWER |= PWER_GPIO12; - - /* Initialize h3800-specific values here */ - GPCR = 0x0fffffff; /* All outputs are set low by default */ - GAFR = GPIO_H3800_CLK_OUT | - GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 | - GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8; - GPDR = GPIO_H3800_CLK_OUT | - GPIO_H3600_COM_RTS | GPIO_H3600_L3_CLOCK | - GPIO_H3600_L3_MODE | GPIO_H3600_L3_DATA | - GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 | - GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8; - TUCR = TUCR_3_6864MHz; /* Seems to be used only for the Bluetooth UART */ - - /* Fix the memory bus */ - MSC2 = (MSC2 & 0x0000ffff) | 0xE4510000; - - /* Set up ASIC #1 */ - H3800_ASIC1_GPIO_DIR = ASIC1_OUTPUTS; /* All outputs */ - H3800_ASIC1_GPIO_MASK = ASIC1_OUTPUTS; /* No interrupts */ - H3800_ASIC1_GPIO_SLEEP_MASK = ASIC1_OUTPUTS; - H3800_ASIC1_GPIO_SLEEP_DIR = ASIC1_OUTPUTS; - H3800_ASIC1_GPIO_SLEEP_OUT = GPIO1_EAR_ON_N; - H3800_ASIC1_GPIO_BATT_FAULT_DIR = ASIC1_OUTPUTS; - H3800_ASIC1_GPIO_BATT_FAULT_OUT = GPIO1_EAR_ON_N; - - H3800_ASIC1_GPIO_OUT = GPIO1_IR_ON_N - | GPIO1_RS232_ON - | GPIO1_EAR_ON_N; + h3xxx_mach_init(); - /* Set up ASIC #2 */ - H3800_ASIC2_GPIOPIOD = GPIO2_IN_Y1_N | GPIO2_IN_X1_N; - H3800_ASIC2_GPOBFSTAT = GPIO2_IN_Y1_N | GPIO2_IN_X1_N; - - H3800_ASIC2_GPIODIR = GPIO2_PEN_IRQ - | GPIO2_SD_DETECT - | GPIO2_EAR_IN_N - | GPIO2_USB_DETECT_N - | GPIO2_SD_CON_SLT; - - /* TODO : Set sleep states & battery fault states */ - - /* Clear VPP Enable */ - H3800_ASIC2_FlashWP_VPP_ON = 0; - ipaq_model_ops = h3800_model_ops; + sa11x0_register_lcd(&h3600_lcd_info); + sa11x0_register_irda(&h3600_irda_data); } -MACHINE_START(H3800, "Compaq iPAQ H3800") - .phys_io = 0x80000000, - .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc, - .boot_params = 0xc0000100, - .map_io = h3800_map_io, - .init_irq = h3800_init_irq, - .timer = &sa1100_timer, - .init_machine = h3xxx_mach_init, +MACHINE_START(H3600, "Compaq iPAQ H3600") + .atag_offset = 0x100, + .map_io = h3600_map_io, + .nr_irqs = SA1100_NR_IRQS, + .init_irq = sa1100_init_irq, + .init_time = sa1100_timer_init, + .init_machine = h3600_mach_init, + .init_late = sa11x0_init_late, + .restart = sa11x0_restart, MACHINE_END -#endif /* CONFIG_SA1100_H3800 */ diff --git a/arch/arm/mach-sa1100/h3xxx.c b/arch/arm/mach-sa1100/h3xxx.c new file mode 100644 index 00000000000..c79bf467fb7 --- /dev/null +++ b/arch/arm/mach-sa1100/h3xxx.c @@ -0,0 +1,302 @@ +/* + * Support for Compaq iPAQ H3100 and H3600 handheld computers (common code) + * + * Copyright (c) 2000,1 Compaq Computer Corporation. (Author: Jamey Hicks) + * Copyright (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/mfd/htc-egpio.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/platform_data/sa11x0-serial.h> +#include <linux/platform_device.h> +#include <linux/serial_core.h> + +#include <asm/mach/flash.h> +#include <asm/mach/map.h> + +#include <mach/h3xxx.h> + +#include "generic.h" + +/* + * H3xxx flash support + */ +static struct mtd_partition h3xxx_partitions[] = { + { + .name = "H3XXX boot firmware", + .size = 0x00040000, + .offset = 0, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "H3XXX rootfs", + .size = MTDPART_SIZ_FULL, + .offset = 0x00040000, + } +}; + +static void h3xxx_set_vpp(int vpp) +{ + gpio_set_value(H3XXX_EGPIO_VPP_ON, vpp); +} + +static int h3xxx_flash_init(void) +{ + int err = gpio_request(H3XXX_EGPIO_VPP_ON, "Flash Vpp"); + if (err) { + pr_err("%s: can't request H3XXX_EGPIO_VPP_ON\n", __func__); + return err; + } + + err = gpio_direction_output(H3XXX_EGPIO_VPP_ON, 0); + if (err) + gpio_free(H3XXX_EGPIO_VPP_ON); + + return err; +} + +static void h3xxx_flash_exit(void) +{ + gpio_free(H3XXX_EGPIO_VPP_ON); +} + +static struct flash_platform_data h3xxx_flash_data = { + .map_name = "cfi_probe", + .set_vpp = h3xxx_set_vpp, + .init = h3xxx_flash_init, + .exit = h3xxx_flash_exit, + .parts = h3xxx_partitions, + .nr_parts = ARRAY_SIZE(h3xxx_partitions), +}; + +static struct resource h3xxx_flash_resource = + DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); + + +/* + * H3xxx uart support + */ +static struct gpio h3xxx_uart_gpio[] = { + { H3XXX_GPIO_COM_DCD, GPIOF_IN, "COM DCD" }, + { H3XXX_GPIO_COM_CTS, GPIOF_IN, "COM CTS" }, + { H3XXX_GPIO_COM_RTS, GPIOF_OUT_INIT_LOW, "COM RTS" }, +}; + +static bool h3xxx_uart_request_gpios(void) +{ + static bool h3xxx_uart_gpio_ok; + int rc; + + if (h3xxx_uart_gpio_ok) + return true; + + rc = gpio_request_array(h3xxx_uart_gpio, ARRAY_SIZE(h3xxx_uart_gpio)); + if (rc) + pr_err("h3xxx_uart_request_gpios: error %d\n", rc); + else + h3xxx_uart_gpio_ok = true; + + return h3xxx_uart_gpio_ok; +} + +static void h3xxx_uart_set_mctrl(struct uart_port *port, u_int mctrl) +{ + if (port->mapbase == _Ser3UTCR0) { + if (!h3xxx_uart_request_gpios()) + return; + gpio_set_value(H3XXX_GPIO_COM_RTS, !(mctrl & TIOCM_RTS)); + } +} + +static u_int h3xxx_uart_get_mctrl(struct uart_port *port) +{ + u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; + + if (port->mapbase == _Ser3UTCR0) { + if (!h3xxx_uart_request_gpios()) + return ret; + /* + * DCD and CTS bits are inverted in GPLR by RS232 transceiver + */ + if (gpio_get_value(H3XXX_GPIO_COM_DCD)) + ret &= ~TIOCM_CD; + if (gpio_get_value(H3XXX_GPIO_COM_CTS)) + ret &= ~TIOCM_CTS; + } + + return ret; +} + +static void h3xxx_uart_pm(struct uart_port *port, u_int state, u_int oldstate) +{ + if (port->mapbase == _Ser3UTCR0) { + if (!gpio_request(H3XXX_EGPIO_RS232_ON, "RS232 transceiver")) { + gpio_direction_output(H3XXX_EGPIO_RS232_ON, !state); + gpio_free(H3XXX_EGPIO_RS232_ON); + } else { + pr_err("%s: can't request H3XXX_EGPIO_RS232_ON\n", + __func__); + } + } +} + +/* + * Enable/Disable wake up events for this serial port. + * Obviously, we only support this on the normal COM port. + */ +static int h3xxx_uart_set_wake(struct uart_port *port, u_int enable) +{ + int err = -EINVAL; + + if (port->mapbase == _Ser3UTCR0) { + if (enable) + PWER |= PWER_GPIO23 | PWER_GPIO25; /* DCD and CTS */ + else + PWER &= ~(PWER_GPIO23 | PWER_GPIO25); /* DCD and CTS */ + err = 0; + } + return err; +} + +static struct sa1100_port_fns h3xxx_port_fns __initdata = { + .set_mctrl = h3xxx_uart_set_mctrl, + .get_mctrl = h3xxx_uart_get_mctrl, + .pm = h3xxx_uart_pm, + .set_wake = h3xxx_uart_set_wake, +}; + +/* + * EGPIO + */ + +static struct resource egpio_resources[] = { + [0] = DEFINE_RES_MEM(H3600_EGPIO_PHYS, 0x4), +}; + +static struct htc_egpio_chip egpio_chips[] = { + [0] = { + .reg_start = 0, + .gpio_base = H3XXX_EGPIO_BASE, + .num_gpios = 16, + .direction = HTC_EGPIO_OUTPUT, + .initial_values = 0x0080, /* H3XXX_EGPIO_RS232_ON */ + }, +}; + +static struct htc_egpio_platform_data egpio_info = { + .reg_width = 16, + .bus_width = 16, + .chip = egpio_chips, + .num_chips = ARRAY_SIZE(egpio_chips), +}; + +static struct platform_device h3xxx_egpio = { + .name = "htc-egpio", + .id = -1, + .resource = egpio_resources, + .num_resources = ARRAY_SIZE(egpio_resources), + .dev = { + .platform_data = &egpio_info, + }, +}; + +/* + * GPIO keys + */ + +static struct gpio_keys_button h3xxx_button_table[] = { + { + .code = KEY_POWER, + .gpio = H3XXX_GPIO_PWR_BUTTON, + .desc = "Power Button", + .active_low = 1, + .type = EV_KEY, + .wakeup = 1, + }, { + .code = KEY_ENTER, + .gpio = H3XXX_GPIO_ACTION_BUTTON, + .active_low = 1, + .desc = "Action button", + .type = EV_KEY, + .wakeup = 0, + }, +}; + +static struct gpio_keys_platform_data h3xxx_keys_data = { + .buttons = h3xxx_button_table, + .nbuttons = ARRAY_SIZE(h3xxx_button_table), +}; + +static struct platform_device h3xxx_keys = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &h3xxx_keys_data, + }, +}; + +static struct platform_device *h3xxx_devices[] = { + &h3xxx_egpio, + &h3xxx_keys, +}; + +void __init h3xxx_mach_init(void) +{ + sa1100_register_uart_fns(&h3xxx_port_fns); + sa11x0_register_mtd(&h3xxx_flash_data, &h3xxx_flash_resource, 1); + platform_add_devices(h3xxx_devices, ARRAY_SIZE(h3xxx_devices)); +} + +static struct map_desc h3600_io_desc[] __initdata = { + { /* static memory bank 2 CS#2 */ + .virtual = H3600_BANK_2_VIRT, + .pfn = __phys_to_pfn(SA1100_CS2_PHYS), + .length = 0x02800000, + .type = MT_DEVICE + }, { /* static memory bank 4 CS#4 */ + .virtual = H3600_BANK_4_VIRT, + .pfn = __phys_to_pfn(SA1100_CS4_PHYS), + .length = 0x00800000, + .type = MT_DEVICE + }, { /* EGPIO 0 CS#5 */ + .virtual = H3600_EGPIO_VIRT, + .pfn = __phys_to_pfn(H3600_EGPIO_PHYS), + .length = 0x01000000, + .type = MT_DEVICE + } +}; + +/* + * Common map_io initialization + */ + +void __init h3xxx_map_io(void) +{ + sa1100_map_io(); + iotable_init(h3600_io_desc, ARRAY_SIZE(h3600_io_desc)); + + sa1100_register_uart(0, 3); /* Common serial port */ +// sa1100_register_uart(1, 1); /* Microcontroller on 3100/3600 */ + + /* Ensure those pins are outputs and driving low */ + PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; + PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); + + /* Configure suspend conditions */ + PGSR = 0; + PCFR = PCFR_OPDE; + PSDR = 0; + + GPCR = 0x0fffffff; /* All outputs are set low by default */ + GPDR = 0; /* Configure all GPIOs as input */ +} + diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c index e7056c0b562..643d5f2d9af 100644 --- a/arch/arm/mach-sa1100/hackkit.c +++ b/arch/arm/mach-sa1100/hackkit.c @@ -18,22 +18,27 @@ #include <linux/module.h> #include <linux/errno.h> #include <linux/cpufreq.h> +#include <linux/platform_data/sa11x0-serial.h> #include <linux/serial_core.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <linux/tty.h> +#include <linux/gpio.h> +#include <linux/leds.h> +#include <linux/platform_device.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/setup.h> #include <asm/page.h> #include <asm/pgtable.h> -#include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <asm/mach/serial_sa1100.h> + +#include <mach/hardware.h> +#include <mach/irqs.h> #include "generic.h" @@ -179,15 +184,40 @@ static struct flash_platform_data hackkit_flash_data = { .nr_parts = ARRAY_SIZE(hackkit_partitions), }; -static struct resource hackkit_flash_resource = { - .start = SA1100_CS0_PHYS, - .end = SA1100_CS0_PHYS + SZ_32M, - .flags = IORESOURCE_MEM, +static struct resource hackkit_flash_resource = + DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); + +/* LEDs */ +struct gpio_led hackkit_gpio_leds[] = { + { + .name = "hackkit:red", + .default_trigger = "cpu0", + .gpio = 22, + }, + { + .name = "hackkit:green", + .default_trigger = "heartbeat", + .gpio = 23, + }, +}; + +static struct gpio_led_platform_data hackkit_gpio_led_info = { + .leds = hackkit_gpio_leds, + .num_leds = ARRAY_SIZE(hackkit_gpio_leds), +}; + +static struct platform_device hackkit_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &hackkit_gpio_led_info, + } }; static void __init hackkit_init(void) { - sa11x0_set_flash_data(&hackkit_flash_data, &hackkit_flash_resource, 1); + sa11x0_register_mtd(&hackkit_flash_data, &hackkit_flash_resource, 1); + platform_device_register(&hackkit_leds); } /********************************************************************** @@ -195,11 +225,12 @@ static void __init hackkit_init(void) */ MACHINE_START(HACKKIT, "HackKit Cpu Board") - .phys_io = 0x80000000, - .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc, - .boot_params = 0xc0000100, + .atag_offset = 0x100, .map_io = hackkit_map_io, + .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = hackkit_init, + .init_late = sa11x0_init_late, + .restart = sa11x0_restart, MACHINE_END diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h index 4f7ea012e1e..0ac6cc08a19 100644 --- a/arch/arm/mach-sa1100/include/mach/SA-1100.h +++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h @@ -830,14 +830,14 @@ * (read/write). */ -#define OSMR0 __REG(0x90000000) /* OS timer Match Reg. 0 */ -#define OSMR1 __REG(0x90000004) /* OS timer Match Reg. 1 */ -#define OSMR2 __REG(0x90000008) /* OS timer Match Reg. 2 */ -#define OSMR3 __REG(0x9000000c) /* OS timer Match Reg. 3 */ -#define OSCR __REG(0x90000010) /* OS timer Counter Reg. */ -#define OSSR __REG(0x90000014 ) /* OS timer Status Reg. */ -#define OWER __REG(0x90000018 ) /* OS timer Watch-dog Enable Reg. */ -#define OIER __REG(0x9000001C ) /* OS timer Interrupt Enable Reg. */ +#define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */ +#define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */ +#define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */ +#define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */ +#define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */ +#define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */ +#define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */ +#define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */ #define OSSR_M(Nb) /* Match detected [0..3] */ \ (0x00000001 << (Nb)) @@ -1590,224 +1590,9 @@ /* * Direct Memory Access (DMA) control registers - * - * Registers - * DDAR0 Direct Memory Access (DMA) Device Address Register - * channel 0 (read/write). - * DCSR0 Direct Memory Access (DMA) Control and Status - * Register channel 0 (read/write). - * DBSA0 Direct Memory Access (DMA) Buffer Start address - * register A channel 0 (read/write). - * DBTA0 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 0 (read/write). - * DBSB0 Direct Memory Access (DMA) Buffer Start address - * register B channel 0 (read/write). - * DBTB0 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 0 (read/write). - * - * DDAR1 Direct Memory Access (DMA) Device Address Register - * channel 1 (read/write). - * DCSR1 Direct Memory Access (DMA) Control and Status - * Register channel 1 (read/write). - * DBSA1 Direct Memory Access (DMA) Buffer Start address - * register A channel 1 (read/write). - * DBTA1 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 1 (read/write). - * DBSB1 Direct Memory Access (DMA) Buffer Start address - * register B channel 1 (read/write). - * DBTB1 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 1 (read/write). - * - * DDAR2 Direct Memory Access (DMA) Device Address Register - * channel 2 (read/write). - * DCSR2 Direct Memory Access (DMA) Control and Status - * Register channel 2 (read/write). - * DBSA2 Direct Memory Access (DMA) Buffer Start address - * register A channel 2 (read/write). - * DBTA2 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 2 (read/write). - * DBSB2 Direct Memory Access (DMA) Buffer Start address - * register B channel 2 (read/write). - * DBTB2 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 2 (read/write). - * - * DDAR3 Direct Memory Access (DMA) Device Address Register - * channel 3 (read/write). - * DCSR3 Direct Memory Access (DMA) Control and Status - * Register channel 3 (read/write). - * DBSA3 Direct Memory Access (DMA) Buffer Start address - * register A channel 3 (read/write). - * DBTA3 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 3 (read/write). - * DBSB3 Direct Memory Access (DMA) Buffer Start address - * register B channel 3 (read/write). - * DBTB3 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 3 (read/write). - * - * DDAR4 Direct Memory Access (DMA) Device Address Register - * channel 4 (read/write). - * DCSR4 Direct Memory Access (DMA) Control and Status - * Register channel 4 (read/write). - * DBSA4 Direct Memory Access (DMA) Buffer Start address - * register A channel 4 (read/write). - * DBTA4 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 4 (read/write). - * DBSB4 Direct Memory Access (DMA) Buffer Start address - * register B channel 4 (read/write). - * DBTB4 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 4 (read/write). - * - * DDAR5 Direct Memory Access (DMA) Device Address Register - * channel 5 (read/write). - * DCSR5 Direct Memory Access (DMA) Control and Status - * Register channel 5 (read/write). - * DBSA5 Direct Memory Access (DMA) Buffer Start address - * register A channel 5 (read/write). - * DBTA5 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 5 (read/write). - * DBSB5 Direct Memory Access (DMA) Buffer Start address - * register B channel 5 (read/write). - * DBTB5 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 5 (read/write). */ - -#define DMASp 0x00000020 /* DMA control reg. Space [byte] */ - -#define DDAR(Nb) __REG(0xB0000000 + (Nb)*DMASp) /* DMA Device Address Reg. channel [0..5] */ -#define SetDCSR(Nb) __REG(0xB0000004 + (Nb)*DMASp) /* Set DMA Control & Status Reg. channel [0..5] (write) */ -#define ClrDCSR(Nb) __REG(0xB0000008 + (Nb)*DMASp) /* Clear DMA Control & Status Reg. channel [0..5] (write) */ -#define RdDCSR(Nb) __REG(0xB000000C + (Nb)*DMASp) /* Read DMA Control & Status Reg. channel [0..5] (read) */ -#define DBSA(Nb) __REG(0xB0000010 + (Nb)*DMASp) /* DMA Buffer Start address reg. A channel [0..5] */ -#define DBTA(Nb) __REG(0xB0000014 + (Nb)*DMASp) /* DMA Buffer Transfer count reg. A channel [0..5] */ -#define DBSB(Nb) __REG(0xB0000018 + (Nb)*DMASp) /* DMA Buffer Start address reg. B channel [0..5] */ -#define DBTB(Nb) __REG(0xB000001C + (Nb)*DMASp) /* DMA Buffer Transfer count reg. B channel [0..5] */ - -#define DDAR_RW 0x00000001 /* device data Read/Write */ -#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */ - /* (memory -> device) */ -#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */ - /* (device -> memory) */ -#define DDAR_E 0x00000002 /* big/little Endian device */ -#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */ -#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */ -#define DDAR_BS 0x00000004 /* device Burst Size */ -#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */ -#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */ -#define DDAR_DW 0x00000008 /* device Data Width */ -#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */ -#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */ -#define DDAR_DS Fld (4, 4) /* Device Select */ -#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \ - (0x0 << FShft (DDAR_DS)) -#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \ - (0x1 << FShft (DDAR_DS)) -#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \ - (0x2 << FShft (DDAR_DS)) -#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \ - (0x3 << FShft (DDAR_DS)) -#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \ - (0x4 << FShft (DDAR_DS)) -#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \ - (0x5 << FShft (DDAR_DS)) -#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \ - (0x6 << FShft (DDAR_DS)) -#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \ - (0x7 << FShft (DDAR_DS)) -#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \ - (0x8 << FShft (DDAR_DS)) -#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \ - (0x9 << FShft (DDAR_DS)) -#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \ - /* (audio) */ \ - (0xA << FShft (DDAR_DS)) -#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \ - /* (audio) */ \ - (0xB << FShft (DDAR_DS)) -#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \ - /* (telecom) */ \ - (0xC << FShft (DDAR_DS)) -#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \ - /* (telecom) */ \ - (0xD << FShft (DDAR_DS)) -#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \ - (0xE << FShft (DDAR_DS)) -#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \ - (0xF << FShft (DDAR_DS)) -#define DDAR_DA Fld (24, 8) /* Device Address */ -#define DDAR_DevAdd(Add) /* Device Address */ \ - (((Add) & 0xF0000000) | \ - (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2))) -#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \ - (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser0UDCTr + DDAR_DevAdd (__PREG(Ser0UDCDR))) -#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \ - (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser0UDCRc + DDAR_DevAdd (__PREG(Ser0UDCDR))) -#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1UARTTr + DDAR_DevAdd (__PREG(Ser1UTDR))) -#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1UARTRc + DDAR_DevAdd (__PREG(Ser1UTDR))) -#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1SDLCTr + DDAR_DevAdd (__PREG(Ser1SDDR))) -#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1SDLCRc + DDAR_DevAdd (__PREG(Ser1SDDR))) -#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2UTDR))) -#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2UTDR))) -#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \ - (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2HSDR))) -#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \ - (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2HSDR))) -#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser3UARTTr + DDAR_DevAdd (__PREG(Ser3UTDR))) -#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser3UARTRc + DDAR_DevAdd (__PREG(Ser3UTDR))) -#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP0Tr + DDAR_DevAdd (__PREG(Ser4MCDR0))) -#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP0Rc + DDAR_DevAdd (__PREG(Ser4MCDR0))) -#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \ - /* (telecom) */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP1Tr + DDAR_DevAdd (__PREG(Ser4MCDR1))) -#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \ - /* (telecom) */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP1Rc + DDAR_DevAdd (__PREG(Ser4MCDR1))) -#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4SSPTr + DDAR_DevAdd (__PREG(Ser4SSDR))) -#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR))) - -#define DCSR_RUN 0x00000001 /* DMA RUNing */ -#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ -#define DCSR_ERROR 0x00000004 /* DMA ERROR */ -#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ -#define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */ -#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */ -#define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */ -#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */ -#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */ -#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */ - -#define DBT_TC Fld (13, 0) /* Transfer Count */ -#define DBTA_TCA DBT_TC /* Transfer Count buffer A */ -#define DBTB_TCB DBT_TC /* Transfer Count buffer B */ +#define DMA_SIZE (6 * 0x20) +#define DMA_PHYS 0xb0000000 /* @@ -1903,16 +1688,6 @@ #define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ /* (Alternative) */ -#define LCCR0 __REG(0xB0100000) /* LCD Control Reg. 0 */ -#define LCSR __REG(0xB0100004) /* LCD Status Reg. */ -#define DBAR1 __REG(0xB0100010) /* LCD DMA Base Address Reg. channel 1 */ -#define DCAR1 __REG(0xB0100014) /* LCD DMA Current Address Reg. channel 1 */ -#define DBAR2 __REG(0xB0100018) /* LCD DMA Base Address Reg. channel 2 */ -#define DCAR2 __REG(0xB010001C) /* LCD DMA Current Address Reg. channel 2 */ -#define LCCR1 __REG(0xB0100020) /* LCD Control Reg. 1 */ -#define LCCR2 __REG(0xB0100024) /* LCD Control Reg. 2 */ -#define LCCR3 __REG(0xB0100028) /* LCD Control Reg. 3 */ - #define LCCR0_LEN 0x00000001 /* LCD ENable */ #define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ #define LCCR0_Color (LCCR0_CMS*0) /* Color display */ diff --git a/arch/arm/mach-sa1100/include/mach/SA-1111.h b/arch/arm/mach-sa1100/include/mach/SA-1111.h deleted file mode 100644 index c38f60915cb..00000000000 --- a/arch/arm/mach-sa1100/include/mach/SA-1111.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Moved to new location - */ -#warning using old SA-1111.h - update to <asm/hardware/sa1111.h> -#include <asm/hardware/sa1111.h> diff --git a/arch/arm/mach-sa1100/include/mach/assabet.h b/arch/arm/mach-sa1100/include/mach/assabet.h index 3959b20d5d1..c23fcdb047a 100644 --- a/arch/arm/mach-sa1100/include/mach/assabet.h +++ b/arch/arm/mach-sa1100/include/mach/assabet.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-sa1100/include/mach/assabet.h * - * Created 2000/06/05 by Nicolas Pitre <nico@cam.org> + * Created 2000/06/05 by Nicolas Pitre <nico@fluxnic.net> * * This file contains the hardware specific definitions for Assabet * Only include this file from SA1100-specific files. @@ -39,8 +39,8 @@ extern unsigned long SCR_value; #define ASSABET_BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */ #define ASSABET_BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */ -#define ASSABET_BCR_GFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */ -#define ASSABET_BCR_CODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */ +#define ASSABET_BCR_NGFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */ +#define ASSABET_BCR_NCODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */ #define ASSABET_BCR_IRDA_FSEL (1<<3) /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */ #define ASSABET_BCR_IRDA_MD0 (1<<4) /* Range/Power select */ #define ASSABET_BCR_IRDA_MD1 (1<<5) /* Range/Power select */ @@ -69,6 +69,8 @@ extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set); #define ASSABET_BCR_frob(x,y) do { } while (0) #endif +extern void assabet_uda1341_reset(int set); + #define ASSABET_BCR_set(x) ASSABET_BCR_frob((x), (x)) #define ASSABET_BCR_clear(x) ASSABET_BCR_frob((x), 0) @@ -85,21 +87,18 @@ extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set); #define ASSABET_BSR_RAD_RI (1 << 31) -/* GPIOs for which the generic definition doesn't say much */ +/* GPIOs (bitmasks) for which the generic definition doesn't say much */ #define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */ #define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */ #define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */ -#define ASSABET_GPIO_CF_IRQ GPIO_GPIO (21) /* CF IRQ */ -#define ASSABET_GPIO_CF_CD GPIO_GPIO (22) /* CF CD */ -#define ASSABET_GPIO_CF_BVD2 GPIO_GPIO (24) /* CF BVD */ #define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */ -#define ASSABET_GPIO_CF_BVD1 GPIO_GPIO (25) /* CF BVD */ #define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */ #define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */ -#define ASSABET_IRQ_GPIO_CF_IRQ IRQ_GPIO21 -#define ASSABET_IRQ_GPIO_CF_CD IRQ_GPIO22 -#define ASSABET_IRQ_GPIO_CF_BVD2 IRQ_GPIO24 -#define ASSABET_IRQ_GPIO_CF_BVD1 IRQ_GPIO25 +/* These are gpiolib GPIO numbers, not bitmasks */ +#define ASSABET_GPIO_CF_IRQ 21 /* CF IRQ */ +#define ASSABET_GPIO_CF_CD 22 /* CF CD */ +#define ASSABET_GPIO_CF_BVD2 24 /* CF BVD / IOSPKR */ +#define ASSABET_GPIO_CF_BVD1 25 /* CF BVD / IOSTSCHG */ #endif diff --git a/arch/arm/mach-sa1100/include/mach/cerf.h b/arch/arm/mach-sa1100/include/mach/cerf.h index c3ac3d0f946..88fd9c006ce 100644 --- a/arch/arm/mach-sa1100/include/mach/cerf.h +++ b/arch/arm/mach-sa1100/include/mach/cerf.h @@ -14,15 +14,10 @@ #define CERF_ETH_IO 0xf0000000 #define CERF_ETH_IRQ IRQ_GPIO26 -#define CERF_GPIO_CF_BVD2 GPIO_GPIO (19) -#define CERF_GPIO_CF_BVD1 GPIO_GPIO (20) -#define CERF_GPIO_CF_RESET GPIO_GPIO (21) -#define CERF_GPIO_CF_IRQ GPIO_GPIO (22) -#define CERF_GPIO_CF_CD GPIO_GPIO (23) - -#define CERF_IRQ_GPIO_CF_BVD2 IRQ_GPIO19 -#define CERF_IRQ_GPIO_CF_BVD1 IRQ_GPIO20 -#define CERF_IRQ_GPIO_CF_IRQ IRQ_GPIO22 -#define CERF_IRQ_GPIO_CF_CD IRQ_GPIO23 +#define CERF_GPIO_CF_BVD2 19 +#define CERF_GPIO_CF_BVD1 20 +#define CERF_GPIO_CF_RESET 21 +#define CERF_GPIO_CF_IRQ 22 +#define CERF_GPIO_CF_CD 23 #endif // _INCLUDE_CERF_H_ diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h index 69e962416e3..b478ca180c1 100644 --- a/arch/arm/mach-sa1100/include/mach/collie.h +++ b/arch/arm/mach-sa1100/include/mach/collie.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-sa1100/include/mach/collie.h * - * This file contains the hardware specific definitions for Assabet + * This file contains the hardware specific definitions for Collie * Only include this file from SA1100-specific files. * * ChangeLog: @@ -13,41 +13,54 @@ #ifndef __ASM_ARCH_COLLIE_H #define __ASM_ARCH_COLLIE_H +#include "hardware.h" /* Gives GPIO_MAX */ -#define COLLIE_SCP_CHARGE_ON SCOOP_GPCR_PA11 +extern void locomolcd_power(int on); + +#define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1) +#define COLLIE_GPIO_CHARGE_ON (COLLIE_SCOOP_GPIO_BASE + 0) #define COLLIE_SCP_DIAG_BOOT1 SCOOP_GPCR_PA12 #define COLLIE_SCP_DIAG_BOOT2 SCOOP_GPCR_PA13 #define COLLIE_SCP_MUTE_L SCOOP_GPCR_PA14 #define COLLIE_SCP_MUTE_R SCOOP_GPCR_PA15 #define COLLIE_SCP_5VON SCOOP_GPCR_PA16 #define COLLIE_SCP_AMP_ON SCOOP_GPCR_PA17 -#define COLLIE_SCP_VPEN SCOOP_GPCR_PA18 +#define COLLIE_GPIO_VPEN (COLLIE_SCOOP_GPIO_BASE + 7) #define COLLIE_SCP_LB_VOL_CHG SCOOP_GPCR_PA19 -#define COLLIE_SCOOP_IO_DIR ( COLLIE_SCP_CHARGE_ON | COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \ - COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | COLLIE_SCP_VPEN | \ - COLLIE_SCP_LB_VOL_CHG ) -#define COLLIE_SCOOP_IO_OUT ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | COLLIE_SCP_VPEN | \ - COLLIE_SCP_CHARGE_ON ) +#define COLLIE_SCOOP_IO_DIR (COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \ + COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | \ + COLLIE_SCP_LB_VOL_CHG) +#define COLLIE_SCOOP_IO_OUT (COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R) + +/* GPIOs for gpiolib */ -/* GPIOs for which the generic definition doesn't say much */ +#define COLLIE_GPIO_ON_KEY (0) +#define COLLIE_GPIO_AC_IN (1) +#define COLLIE_GPIO_SDIO_INT (11) +#define COLLIE_GPIO_CF_IRQ (14) +#define COLLIE_GPIO_nREMOCON_INT (15) +#define COLLIE_GPIO_UCB1x00_RESET (16) +#define COLLIE_GPIO_nMIC_ON (17) +#define COLLIE_GPIO_nREMOCON_ON (18) +#define COLLIE_GPIO_CO (20) +#define COLLIE_GPIO_MCP_CLK (21) +#define COLLIE_GPIO_CF_CD (22) +#define COLLIE_GPIO_UCB1x00_IRQ (23) +#define COLLIE_GPIO_WAKEUP (24) +#define COLLIE_GPIO_GA_INT (25) +#define COLLIE_GPIO_MAIN_BAT_LOW (26) -#define COLLIE_GPIO_ON_KEY GPIO_GPIO (0) -#define COLLIE_GPIO_AC_IN GPIO_GPIO (1) -#define COLLIE_GPIO_SDIO_INT GPIO_GPIO (11) -#define COLLIE_GPIO_CF_IRQ GPIO_GPIO (14) -#define COLLIE_GPIO_nREMOCON_INT GPIO_GPIO (15) -#define COLLIE_GPIO_UCB1x00_RESET GPIO_GPIO (16) -#define COLLIE_GPIO_nMIC_ON GPIO_GPIO (17) -#define COLLIE_GPIO_nREMOCON_ON GPIO_GPIO (18) -#define COLLIE_GPIO_CO GPIO_GPIO (20) -#define COLLIE_GPIO_MCP_CLK GPIO_GPIO (21) -#define COLLIE_GPIO_CF_CD GPIO_GPIO (22) -#define COLLIE_GPIO_UCB1x00_IRQ GPIO_GPIO (23) -#define COLLIE_GPIO_WAKEUP GPIO_GPIO (24) -#define COLLIE_GPIO_GA_INT GPIO_GPIO (25) -#define COLLIE_GPIO_MAIN_BAT_LOW GPIO_GPIO (26) +/* GPIO definitions for direct register access */ +#define _COLLIE_GPIO_ON_KEY GPIO_GPIO(0) +#define _COLLIE_GPIO_AC_IN GPIO_GPIO(1) +#define _COLLIE_GPIO_nREMOCON_INT GPIO_GPIO(15) +#define _COLLIE_GPIO_UCB1x00_RESET GPIO_GPIO(16) +#define _COLLIE_GPIO_nMIC_ON GPIO_GPIO(17) +#define _COLLIE_GPIO_nREMOCON_ON GPIO_GPIO(18) +#define _COLLIE_GPIO_CO GPIO_GPIO(20) +#define _COLLIE_GPIO_WAKEUP GPIO_GPIO(24) /* Interrupts */ #define COLLIE_IRQ_GPIO_ON_KEY IRQ_GPIO0 @@ -62,27 +75,21 @@ #define COLLIE_IRQ_GPIO_GA_INT IRQ_GPIO25 #define COLLIE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO26 -#define COLLIE_LCM_IRQ_GPIO_RTS IRQ_LOCOMO_GPIO0 -#define COLLIE_LCM_IRQ_GPIO_CTS IRQ_LOCOMO_GPIO1 -#define COLLIE_LCM_IRQ_GPIO_DSR IRQ_LOCOMO_GPIO2 -#define COLLIE_LCM_IRQ_GPIO_DTR IRQ_LOCOMO_GPIO3 -#define COLLIE_LCM_IRQ_GPIO_nSD_DETECT IRQ_LOCOMO_GPIO13 -#define COLLIE_LCM_IRQ_GPIO_nSD_WP IRQ_LOCOMO_GPIO14 - /* GPIO's on the TC35143AF (Toshiba Analog Frontend) */ -#define COLLIE_TC35143_GPIO_VERSION0 UCB_IO_0 /* GPIO0=Version */ -#define COLLIE_TC35143_GPIO_TBL_CHK UCB_IO_1 /* GPIO1=TBL_CHK */ -#define COLLIE_TC35143_GPIO_VPEN_ON UCB_IO_2 /* GPIO2=VPNE_ON */ -#define COLLIE_TC35143_GPIO_IR_ON UCB_IO_3 /* GPIO3=IR_ON */ -#define COLLIE_TC35143_GPIO_AMP_ON UCB_IO_4 /* GPIO4=AMP_ON */ -#define COLLIE_TC35143_GPIO_VERSION1 UCB_IO_5 /* GPIO5=Version */ -#define COLLIE_TC35143_GPIO_FS8KLPF UCB_IO_5 /* GPIO5=fs 8k LPF */ -#define COLLIE_TC35143_GPIO_BUZZER_BIAS UCB_IO_6 /* GPIO6=BUZZER BIAS */ -#define COLLIE_TC35143_GPIO_MBAT_ON UCB_IO_7 /* GPIO7=MBAT_ON */ -#define COLLIE_TC35143_GPIO_BBAT_ON UCB_IO_8 /* GPIO8=BBAT_ON */ -#define COLLIE_TC35143_GPIO_TMP_ON UCB_IO_9 /* GPIO9=TMP_ON */ -#define COLLIE_TC35143_GPIO_IN ( UCB_IO_0 | UCB_IO_2 | UCB_IO_5 ) -#define COLLIE_TC35143_GPIO_OUT ( UCB_IO_1 | UCB_IO_3 | UCB_IO_4 | UCB_IO_6 | \ - UCB_IO_7 | UCB_IO_8 | UCB_IO_9 ) +#define COLLIE_TC35143_GPIO_BASE (GPIO_MAX + 13) +#define COLLIE_TC35143_GPIO_VERSION0 UCB_IO_0 +#define COLLIE_TC35143_GPIO_TBL_CHK UCB_IO_1 +#define COLLIE_TC35143_GPIO_VPEN_ON UCB_IO_2 +#define COLLIE_GPIO_IR_ON (COLLIE_TC35143_GPIO_BASE + 3) +#define COLLIE_TC35143_GPIO_AMP_ON UCB_IO_4 +#define COLLIE_TC35143_GPIO_VERSION1 UCB_IO_5 +#define COLLIE_TC35143_GPIO_FS8KLPF UCB_IO_5 +#define COLLIE_TC35143_GPIO_BUZZER_BIAS UCB_IO_6 +#define COLLIE_GPIO_MBAT_ON (COLLIE_TC35143_GPIO_BASE + 7) +#define COLLIE_GPIO_BBAT_ON (COLLIE_TC35143_GPIO_BASE + 8) +#define COLLIE_GPIO_TMP_ON (COLLIE_TC35143_GPIO_BASE + 9) +#define COLLIE_TC35143_GPIO_IN (UCB_IO_0 | UCB_IO_2 | UCB_IO_5) +#define COLLIE_TC35143_GPIO_OUT (UCB_IO_1 | UCB_IO_3 | UCB_IO_4 \ + | UCB_IO_6) #endif diff --git a/arch/arm/mach-sa1100/include/mach/debug-macro.S b/arch/arm/mach-sa1100/include/mach/debug-macro.S index 1f0634d9270..530772d937a 100644 --- a/arch/arm/mach-sa1100/include/mach/debug-macro.S +++ b/arch/arm/mach-sa1100/include/mach/debug-macro.S @@ -12,33 +12,37 @@ */ #include <mach/hardware.h> - .macro addruart,rx - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 @ MMU enabled? - moveq \rx, #0x80000000 @ physical base address - movne \rx, #0xf8000000 @ virtual address + .macro addruart, rp, rv, tmp + mrc p15, 0, \rp, c1, c0 + tst \rp, #1 @ MMU enabled? + moveq \rp, #0x80000000 @ physical base address + movne \rp, #0xf8000000 @ virtual address @ We probe for the active serial port here, coherently with @ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h. @ We assume r1 can be clobbered. @ see if Ser3 is active - add \rx, \rx, #0x00050000 - ldr r1, [\rx, #UTCR3] - tst r1, #UTCR3_TXE + add \rp, \rp, #0x00050000 + ldr \rv, [\rp, #UTCR3] + tst \rv, #UTCR3_TXE @ if Ser3 is inactive, then try Ser1 - addeq \rx, \rx, #(0x00010000 - 0x00050000) - ldreq r1, [\rx, #UTCR3] - tsteq r1, #UTCR3_TXE + addeq \rp, \rp, #(0x00010000 - 0x00050000) + ldreq \rv, [\rp, #UTCR3] + tsteq \rv, #UTCR3_TXE @ if Ser1 is inactive, then try Ser2 - addeq \rx, \rx, #(0x00030000 - 0x00010000) - ldreq r1, [\rx, #UTCR3] - tsteq r1, #UTCR3_TXE + addeq \rp, \rp, #(0x00030000 - 0x00010000) + ldreq \rv, [\rp, #UTCR3] + tsteq \rv, #UTCR3_TXE + + @ clear top bits, and generate both phys and virt addresses + lsl \rp, \rp, #8 + lsr \rp, \rp, #8 + orr \rv, \rp, #0xf8000000 @ virtual + orr \rp, \rp, #0x80000000 @ physical - @ if all ports are inactive, then there is nothing we can do - moveq pc, lr .endm .macro senduart,rd,rx diff --git a/arch/arm/mach-sa1100/include/mach/dma.h b/arch/arm/mach-sa1100/include/mach/dma.h deleted file mode 100644 index dda1b351310..00000000000 --- a/arch/arm/mach-sa1100/include/mach/dma.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * arch/arm/mach-sa1100/include/mach/dma.h - * - * Generic SA1100 DMA support - * - * Copyright (C) 2000 Nicolas Pitre - * - */ - -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H - -#include "hardware.h" - - -/* - * The SA1100 has six internal DMA channels. - */ -#define SA1100_DMA_CHANNELS 6 - -/* - * Maximum physical DMA buffer size - */ -#define MAX_DMA_SIZE 0x1fff -#define CUT_DMA_SIZE 0x1000 - -/* - * All possible SA1100 devices a DMA channel can be attached to. - */ -typedef enum { - DMA_Ser0UDCWr = DDAR_Ser0UDCWr, /* Ser. port 0 UDC Write */ - DMA_Ser0UDCRd = DDAR_Ser0UDCRd, /* Ser. port 0 UDC Read */ - DMA_Ser1UARTWr = DDAR_Ser1UARTWr, /* Ser. port 1 UART Write */ - DMA_Ser1UARTRd = DDAR_Ser1UARTRd, /* Ser. port 1 UART Read */ - DMA_Ser1SDLCWr = DDAR_Ser1SDLCWr, /* Ser. port 1 SDLC Write */ - DMA_Ser1SDLCRd = DDAR_Ser1SDLCRd, /* Ser. port 1 SDLC Read */ - DMA_Ser2UARTWr = DDAR_Ser2UARTWr, /* Ser. port 2 UART Write */ - DMA_Ser2UARTRd = DDAR_Ser2UARTRd, /* Ser. port 2 UART Read */ - DMA_Ser2HSSPWr = DDAR_Ser2HSSPWr, /* Ser. port 2 HSSP Write */ - DMA_Ser2HSSPRd = DDAR_Ser2HSSPRd, /* Ser. port 2 HSSP Read */ - DMA_Ser3UARTWr = DDAR_Ser3UARTWr, /* Ser. port 3 UART Write */ - DMA_Ser3UARTRd = DDAR_Ser3UARTRd, /* Ser. port 3 UART Read */ - DMA_Ser4MCP0Wr = DDAR_Ser4MCP0Wr, /* Ser. port 4 MCP 0 Write (audio) */ - DMA_Ser4MCP0Rd = DDAR_Ser4MCP0Rd, /* Ser. port 4 MCP 0 Read (audio) */ - DMA_Ser4MCP1Wr = DDAR_Ser4MCP1Wr, /* Ser. port 4 MCP 1 Write */ - DMA_Ser4MCP1Rd = DDAR_Ser4MCP1Rd, /* Ser. port 4 MCP 1 Read */ - DMA_Ser4SSPWr = DDAR_Ser4SSPWr, /* Ser. port 4 SSP Write (16 bits) */ - DMA_Ser4SSPRd = DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ -} dma_device_t; - -typedef struct { - volatile u_long DDAR; - volatile u_long SetDCSR; - volatile u_long ClrDCSR; - volatile u_long RdDCSR; - volatile dma_addr_t DBSA; - volatile u_long DBTA; - volatile dma_addr_t DBSB; - volatile u_long DBTB; -} dma_regs_t; - -typedef void (*dma_callback_t)(void *data); - -/* - * DMA function prototypes - */ - -extern int sa1100_request_dma( dma_device_t device, const char *device_id, - dma_callback_t callback, void *data, - dma_regs_t **regs ); -extern void sa1100_free_dma( dma_regs_t *regs ); -extern int sa1100_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size ); -extern dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs); -extern void sa1100_reset_dma(dma_regs_t *regs); - -/** - * sa1100_stop_dma - stop DMA in progress - * @regs: identifier for the channel to use - * - * This stops DMA without clearing buffer pointers. Unlike - * sa1100_clear_dma() this allows subsequent use of sa1100_resume_dma() - * or sa1100_get_dma_pos(). - * - * The @regs identifier is provided by a successful call to - * sa1100_request_dma(). - **/ - -#define sa1100_stop_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN) - -/** - * sa1100_resume_dma - resume DMA on a stopped channel - * @regs: identifier for the channel to use - * - * This resumes DMA on a channel previously stopped with - * sa1100_stop_dma(). - * - * The @regs identifier is provided by a successful call to - * sa1100_request_dma(). - **/ - -#define sa1100_resume_dma(regs) ((regs)->SetDCSR = DCSR_IE|DCSR_RUN) - -/** - * sa1100_clear_dma - clear DMA pointers - * @regs: identifier for the channel to use - * - * This clear any DMA state so the DMA engine is ready to restart - * with new buffers through sa1100_start_dma(). Any buffers in flight - * are discarded. - * - * The @regs identifier is provided by a successful call to - * sa1100_request_dma(). - **/ - -#define sa1100_clear_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN|DCSR_STRTA|DCSR_STRTB) - -#endif /* _ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-sa1100/include/mach/entry-macro.S b/arch/arm/mach-sa1100/include/mach/entry-macro.S index 6aa13c46c5d..8cf7630bf02 100644 --- a/arch/arm/mach-sa1100/include/mach/entry-macro.S +++ b/arch/arm/mach-sa1100/include/mach/entry-macro.S @@ -8,17 +8,11 @@ * warranty of any kind, whether express or implied. */ - .macro disable_fiq - .endm - .macro get_irqnr_preamble, base, tmp mov \base, #0xfa000000 @ ICIP = 0xfa050000 add \base, \base, #0x00050000 .endm - .macro arch_ret_to_user, tmp1, tmp2 - .endm - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ldr \irqstat, [\base] @ get irqs ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004 diff --git a/arch/arm/mach-sa1100/include/mach/generic.h b/arch/arm/mach-sa1100/include/mach/generic.h new file mode 100644 index 00000000000..665542e0c9e --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/generic.h @@ -0,0 +1 @@ +#include "../../generic.h" diff --git a/arch/arm/mach-sa1100/include/mach/gpio.h b/arch/arm/mach-sa1100/include/mach/gpio.h deleted file mode 100644 index 582a0c92da5..00000000000 --- a/arch/arm/mach-sa1100/include/mach/gpio.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * arch/arm/mach-sa1100/include/mach/gpio.h - * - * SA1100 GPIO wrappers for arch-neutral GPIO calls - * - * Written by Philipp Zabel <philipp.zabel@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __ASM_ARCH_SA1100_GPIO_H -#define __ASM_ARCH_SA1100_GPIO_H - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm-generic/gpio.h> - -static inline int gpio_get_value(unsigned gpio) -{ - if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) - return GPLR & GPIO_GPIO(gpio); - else - return __gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) - if (value) - GPSR = GPIO_GPIO(gpio); - else - GPCR = GPIO_GPIO(gpio); - else - __gpio_set_value(gpio, value); -} - -#define gpio_cansleep __gpio_cansleep - -static inline unsigned gpio_to_irq(unsigned gpio) -{ - if (gpio < 11) - return IRQ_GPIO0 + gpio; - else - return IRQ_GPIO11 - 11 + gpio; -} - -static inline unsigned irq_to_gpio(unsigned irq) -{ - if (irq < IRQ_GPIO11_27) - return irq - IRQ_GPIO0; - else - return irq - IRQ_GPIO11 + 11; -} - -#endif diff --git a/arch/arm/mach-sa1100/include/mach/h3600.h b/arch/arm/mach-sa1100/include/mach/h3600.h deleted file mode 100644 index 9cc47fddb33..00000000000 --- a/arch/arm/mach-sa1100/include/mach/h3600.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * - * Definitions for H3600 Handheld Computer - * - * Copyright 2000 Compaq Computer Corporation. - * - * Use consistent with the GNU GPL is permitted, - * provided that this copyright notice is - * preserved in its entirety in all copies and derived works. - * - * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, - * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS - * FITNESS FOR ANY PARTICULAR PURPOSE. - * - * Author: Jamey Hicks. - * - * History: - * - * 2001-10-?? Andrew Christian Added support for iPAQ H3800 - * - */ - -#ifndef _INCLUDE_H3600_H_ -#define _INCLUDE_H3600_H_ - -typedef int __bitwise pm_request_t; - -#define PM_SUSPEND ((__force pm_request_t) 1) /* enter D1-D3 */ -#define PM_RESUME ((__force pm_request_t) 2) /* enter D0 */ - -/* generalized support for H3xxx series Compaq Pocket PC's */ -#define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800()) - -/* Physical memory regions corresponding to chip selects */ -#define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000) -#define H3600_BANK_2_PHYS SA1100_CS2_PHYS -#define H3600_BANK_4_PHYS SA1100_CS4_PHYS - -/* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */ -#define H3600_EGPIO_VIRT 0xf0000000 -#define H3600_BANK_2_VIRT 0xf1000000 -#define H3600_BANK_4_VIRT 0xf3800000 - -/* - Machine-independent GPIO definitions - --- these are common across all current iPAQ platforms -*/ - -#define GPIO_H3600_NPOWER_BUTTON GPIO_GPIO (0) /* Also known as the "off button" */ - -#define GPIO_H3600_PCMCIA_CD1 GPIO_GPIO (10) -#define GPIO_H3600_PCMCIA_IRQ1 GPIO_GPIO (11) - -/* UDA1341 L3 Interface */ -#define GPIO_H3600_L3_DATA GPIO_GPIO (14) -#define GPIO_H3600_L3_MODE GPIO_GPIO (15) -#define GPIO_H3600_L3_CLOCK GPIO_GPIO (16) - -#define GPIO_H3600_PCMCIA_CD0 GPIO_GPIO (17) -#define GPIO_H3600_SYS_CLK GPIO_GPIO (19) -#define GPIO_H3600_PCMCIA_IRQ0 GPIO_GPIO (21) - -#define GPIO_H3600_COM_DCD GPIO_GPIO (23) -#define GPIO_H3600_OPT_IRQ GPIO_GPIO (24) -#define GPIO_H3600_COM_CTS GPIO_GPIO (25) -#define GPIO_H3600_COM_RTS GPIO_GPIO (26) - -#define IRQ_GPIO_H3600_NPOWER_BUTTON IRQ_GPIO0 -#define IRQ_GPIO_H3600_PCMCIA_CD1 IRQ_GPIO10 -#define IRQ_GPIO_H3600_PCMCIA_IRQ1 IRQ_GPIO11 -#define IRQ_GPIO_H3600_PCMCIA_CD0 IRQ_GPIO17 -#define IRQ_GPIO_H3600_PCMCIA_IRQ0 IRQ_GPIO21 -#define IRQ_GPIO_H3600_COM_DCD IRQ_GPIO23 -#define IRQ_GPIO_H3600_OPT_IRQ IRQ_GPIO24 -#define IRQ_GPIO_H3600_COM_CTS IRQ_GPIO25 - - -#ifndef __ASSEMBLY__ - -enum ipaq_egpio_type { - IPAQ_EGPIO_LCD_POWER, /* Power to the LCD panel */ - IPAQ_EGPIO_CODEC_NRESET, /* Clear to reset the audio codec (remember to return high) */ - IPAQ_EGPIO_AUDIO_ON, /* Audio power */ - IPAQ_EGPIO_QMUTE, /* Audio muting */ - IPAQ_EGPIO_OPT_NVRAM_ON, /* Non-volatile RAM on extension sleeves (SPI interface) */ - IPAQ_EGPIO_OPT_ON, /* Power to extension sleeves */ - IPAQ_EGPIO_CARD_RESET, /* Reset PCMCIA cards on extension sleeve (???) */ - IPAQ_EGPIO_OPT_RESET, /* Reset option pack (???) */ - IPAQ_EGPIO_IR_ON, /* IR sensor/emitter power */ - IPAQ_EGPIO_IR_FSEL, /* IR speed selection 1->fast, 0->slow */ - IPAQ_EGPIO_RS232_ON, /* Maxim RS232 chip power */ - IPAQ_EGPIO_VPP_ON, /* Turn on power to flash programming */ - IPAQ_EGPIO_LCD_ENABLE, /* Enable/disable LCD controller */ -}; - -struct ipaq_model_ops { - const char *generic_name; - void (*control)(enum ipaq_egpio_type, int); - unsigned long (*read)(void); - void (*blank_callback)(int blank); - int (*pm_callback)(int req); /* Primary model callback */ - int (*pm_callback_aux)(int req); /* Secondary callback (used by HAL modules) */ -}; - -extern struct ipaq_model_ops ipaq_model_ops; - -static __inline__ const char * h3600_generic_name(void) -{ - return ipaq_model_ops.generic_name; -} - -static __inline__ void assign_h3600_egpio(enum ipaq_egpio_type x, int level) -{ - if (ipaq_model_ops.control) - ipaq_model_ops.control(x,level); -} - -static __inline__ void clr_h3600_egpio(enum ipaq_egpio_type x) -{ - if (ipaq_model_ops.control) - ipaq_model_ops.control(x,0); -} - -static __inline__ void set_h3600_egpio(enum ipaq_egpio_type x) -{ - if (ipaq_model_ops.control) - ipaq_model_ops.control(x,1); -} - -static __inline__ unsigned long read_h3600_egpio(void) -{ - if (ipaq_model_ops.read) - return ipaq_model_ops.read(); - return 0; -} - -static __inline__ int h3600_register_blank_callback(void (*f)(int)) -{ - ipaq_model_ops.blank_callback = f; - return 0; -} - -static __inline__ void h3600_unregister_blank_callback(void (*f)(int)) -{ - ipaq_model_ops.blank_callback = NULL; -} - - -static __inline__ int h3600_register_pm_callback(int (*f)(int)) -{ - ipaq_model_ops.pm_callback_aux = f; - return 0; -} - -static __inline__ void h3600_unregister_pm_callback(int (*f)(int)) -{ - ipaq_model_ops.pm_callback_aux = NULL; -} - -static __inline__ int h3600_power_management(int req) -{ - if (ipaq_model_ops.pm_callback) - return ipaq_model_ops.pm_callback(req); - return 0; -} - -#endif /* ASSEMBLY */ - -#endif /* _INCLUDE_H3600_H_ */ diff --git a/arch/arm/mach-sa1100/include/mach/h3600_gpio.h b/arch/arm/mach-sa1100/include/mach/h3600_gpio.h deleted file mode 100644 index 62b0b787968..00000000000 --- a/arch/arm/mach-sa1100/include/mach/h3600_gpio.h +++ /dev/null @@ -1,540 +0,0 @@ -/* - * - * Definitions for H3600 Handheld Computer - * - * Copyright 2000 Compaq Computer Corporation. - * - * Use consistent with the GNU GPL is permitted, - * provided that this copyright notice is - * preserved in its entirety in all copies and derived works. - * - * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, - * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS - * FITNESS FOR ANY PARTICULAR PURPOSE. - * - * Author: Jamey Hicks. - * - * History: - * - * 2001-10-?? Andrew Christian Added support for iPAQ H3800 - * - */ - -#ifndef _INCLUDE_H3600_GPIO_H_ -#define _INCLUDE_H3600_GPIO_H_ - -/* - * GPIO lines that are common across ALL iPAQ models are in "h3600.h" - * This file contains machine-specific definitions - */ - -#define GPIO_H3600_SUSPEND GPIO_GPIO (0) -/* GPIO[2:9] used by LCD on H3600/3800, used as GPIO on H3100 */ -#define GPIO_H3100_BT_ON GPIO_GPIO (2) -#define GPIO_H3100_GPIO3 GPIO_GPIO (3) -#define GPIO_H3100_QMUTE GPIO_GPIO (4) -#define GPIO_H3100_LCD_3V_ON GPIO_GPIO (5) -#define GPIO_H3100_AUD_ON GPIO_GPIO (6) -#define GPIO_H3100_AUD_PWR_ON GPIO_GPIO (7) -#define GPIO_H3100_IR_ON GPIO_GPIO (8) -#define GPIO_H3100_IR_FSEL GPIO_GPIO (9) - -/* for H3600, audio sample rate clock generator */ -#define GPIO_H3600_CLK_SET0 GPIO_GPIO (12) -#define GPIO_H3600_CLK_SET1 GPIO_GPIO (13) - -#define GPIO_H3600_ACTION_BUTTON GPIO_GPIO (18) -#define GPIO_H3600_SOFT_RESET GPIO_GPIO (20) /* Also known as BATT_FAULT */ -#define GPIO_H3600_OPT_LOCK GPIO_GPIO (22) -#define GPIO_H3600_OPT_DET GPIO_GPIO (27) - -/* H3800 specific pins */ -#define GPIO_H3800_AC_IN GPIO_GPIO (12) -#define GPIO_H3800_COM_DSR GPIO_GPIO (13) -#define GPIO_H3800_MMC_INT GPIO_GPIO (18) -#define GPIO_H3800_NOPT_IND GPIO_GPIO (20) /* Almost exactly the same as GPIO_H3600_OPT_DET */ -#define GPIO_H3800_OPT_BAT_FAULT GPIO_GPIO (22) -#define GPIO_H3800_CLK_OUT GPIO_GPIO (27) - -/****************************************************/ - -#define IRQ_GPIO_H3600_ACTION_BUTTON IRQ_GPIO18 -#define IRQ_GPIO_H3600_OPT_DET IRQ_GPIO27 - -#define IRQ_GPIO_H3800_MMC_INT IRQ_GPIO18 -#define IRQ_GPIO_H3800_NOPT_IND IRQ_GPIO20 /* almost same as OPT_DET */ - -/* H3100 / 3600 EGPIO pins */ -#define EGPIO_H3600_VPP_ON (1 << 0) -#define EGPIO_H3600_CARD_RESET (1 << 1) /* reset the attached pcmcia/compactflash card. active high. */ -#define EGPIO_H3600_OPT_RESET (1 << 2) /* reset the attached option pack. active high. */ -#define EGPIO_H3600_CODEC_NRESET (1 << 3) /* reset the onboard UDA1341. active low. */ -#define EGPIO_H3600_OPT_NVRAM_ON (1 << 4) /* apply power to optionpack nvram, active high. */ -#define EGPIO_H3600_OPT_ON (1 << 5) /* full power to option pack. active high. */ -#define EGPIO_H3600_LCD_ON (1 << 6) /* enable 3.3V to LCD. active high. */ -#define EGPIO_H3600_RS232_ON (1 << 7) /* UART3 transceiver force on. Active high. */ - -/* H3600 only EGPIO pins */ -#define EGPIO_H3600_LCD_PCI (1 << 8) /* LCD control IC enable. active high. */ -#define EGPIO_H3600_IR_ON (1 << 9) /* apply power to IR module. active high. */ -#define EGPIO_H3600_AUD_AMP_ON (1 << 10) /* apply power to audio power amp. active high. */ -#define EGPIO_H3600_AUD_PWR_ON (1 << 11) /* apply power to reset of audio circuit. active high. */ -#define EGPIO_H3600_QMUTE (1 << 12) /* mute control for onboard UDA1341. active high. */ -#define EGPIO_H3600_IR_FSEL (1 << 13) /* IR speed select: 1->fast, 0->slow */ -#define EGPIO_H3600_LCD_5V_ON (1 << 14) /* enable 5V to LCD. active high. */ -#define EGPIO_H3600_LVDD_ON (1 << 15) /* enable 9V and -6.5V to LCD. */ - -/********************* H3800, ASIC #2 ********************/ - -#define _H3800_ASIC2_Base (H3600_EGPIO_VIRT) -#define H3800_ASIC2_OFFSET(s,x,y) \ - (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _Base + _H3800_ASIC2_ ## x ## _ ## y))) -#define H3800_ASIC2_NOFFSET(s,x,n,y) \ - (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _ ## n ## _Base + _H3800_ASIC2_ ## x ## _ ## y))) - -#define _H3800_ASIC2_GPIO_Base 0x0000 -#define _H3800_ASIC2_GPIO_Direction 0x0000 /* R/W, 16 bits 1:input, 0:output */ -#define _H3800_ASIC2_GPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */ -#define _H3800_ASIC2_GPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */ -#define _H3800_ASIC2_GPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */ -#define _H3800_ASIC2_GPIO_InterruptClear 0x0010 /* W, 12 bits */ -#define _H3800_ASIC2_GPIO_InterruptFlag 0x0010 /* R, 12 bits - reads int status */ -#define _H3800_ASIC2_GPIO_Data 0x0014 /* R/W, 16 bits */ -#define _H3800_ASIC2_GPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */ -#define _H3800_ASIC2_GPIO_InterruptEnable 0x001c /* R/W, 12 bits 1:enable interrupt */ -#define _H3800_ASIC2_GPIO_Alternate 0x003c /* R/W, 12+1 bits - set alternate functions */ - -#define H3800_ASIC2_GPIO_Direction H3800_ASIC2_OFFSET( u16, GPIO, Direction ) -#define H3800_ASIC2_GPIO_InterruptType H3800_ASIC2_OFFSET( u16, GPIO, InterruptType ) -#define H3800_ASIC2_GPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, GPIO, InterruptEdgeType ) -#define H3800_ASIC2_GPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, GPIO, InterruptLevelType ) -#define H3800_ASIC2_GPIO_InterruptClear H3800_ASIC2_OFFSET( u16, GPIO, InterruptClear ) -#define H3800_ASIC2_GPIO_InterruptFlag H3800_ASIC2_OFFSET( u16, GPIO, InterruptFlag ) -#define H3800_ASIC2_GPIO_Data H3800_ASIC2_OFFSET( u16, GPIO, Data ) -#define H3800_ASIC2_GPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, GPIO, BattFaultOut ) -#define H3800_ASIC2_GPIO_InterruptEnable H3800_ASIC2_OFFSET( u16, GPIO, InterruptEnable ) -#define H3800_ASIC2_GPIO_Alternate H3800_ASIC2_OFFSET( u16, GPIO, Alternate ) - -#define GPIO_H3800_ASIC2_IN_Y1_N (1 << 0) /* Output: Touchscreen Y1 */ -#define GPIO_H3800_ASIC2_IN_X0 (1 << 1) /* Output: Touchscreen X0 */ -#define GPIO_H3800_ASIC2_IN_Y0 (1 << 2) /* Output: Touchscreen Y0 */ -#define GPIO_H3800_ASIC2_IN_X1_N (1 << 3) /* Output: Touchscreen X1 */ -#define GPIO_H3800_ASIC2_BT_RST (1 << 4) /* Output: Bluetooth reset */ -#define GPIO_H3800_ASIC2_PEN_IRQ (1 << 5) /* Input : Pen down */ -#define GPIO_H3800_ASIC2_SD_DETECT (1 << 6) /* Input : SD detect */ -#define GPIO_H3800_ASIC2_EAR_IN_N (1 << 7) /* Input : Audio jack plug inserted */ -#define GPIO_H3800_ASIC2_OPT_PCM_RESET (1 << 8) /* Output: */ -#define GPIO_H3800_ASIC2_OPT_RESET (1 << 9) /* Output: */ -#define GPIO_H3800_ASIC2_USB_DETECT_N (1 << 10) /* Input : */ -#define GPIO_H3800_ASIC2_SD_CON_SLT (1 << 11) /* Input : */ - -#define _H3800_ASIC2_KPIO_Base 0x0200 -#define _H3800_ASIC2_KPIO_Direction 0x0000 /* R/W, 12 bits 1:input, 0:output */ -#define _H3800_ASIC2_KPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */ -#define _H3800_ASIC2_KPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */ -#define _H3800_ASIC2_KPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */ -#define _H3800_ASIC2_KPIO_InterruptClear 0x0010 /* W, 20 bits - 8 special */ -#define _H3800_ASIC2_KPIO_InterruptFlag 0x0010 /* R, 20 bits - 8 special - reads int status */ -#define _H3800_ASIC2_KPIO_Data 0x0014 /* R/W, 16 bits */ -#define _H3800_ASIC2_KPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */ -#define _H3800_ASIC2_KPIO_InterruptEnable 0x001c /* R/W, 20 bits - 8 special */ -#define _H3800_ASIC2_KPIO_Alternate 0x003c /* R/W, 6 bits */ - -#define H3800_ASIC2_KPIO_Direction H3800_ASIC2_OFFSET( u16, KPIO, Direction ) -#define H3800_ASIC2_KPIO_InterruptType H3800_ASIC2_OFFSET( u16, KPIO, InterruptType ) -#define H3800_ASIC2_KPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, KPIO, InterruptEdgeType ) -#define H3800_ASIC2_KPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, KPIO, InterruptLevelType ) -#define H3800_ASIC2_KPIO_InterruptClear H3800_ASIC2_OFFSET( u32, KPIO, InterruptClear ) -#define H3800_ASIC2_KPIO_InterruptFlag H3800_ASIC2_OFFSET( u32, KPIO, InterruptFlag ) -#define H3800_ASIC2_KPIO_Data H3800_ASIC2_OFFSET( u16, KPIO, Data ) -#define H3800_ASIC2_KPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, KPIO, BattFaultOut ) -#define H3800_ASIC2_KPIO_InterruptEnable H3800_ASIC2_OFFSET( u32, KPIO, InterruptEnable ) -#define H3800_ASIC2_KPIO_Alternate H3800_ASIC2_OFFSET( u16, KPIO, Alternate ) - -#define H3800_ASIC2_KPIO_SPI_INT ( 1 << 16 ) -#define H3800_ASIC2_KPIO_OWM_INT ( 1 << 17 ) -#define H3800_ASIC2_KPIO_ADC_INT ( 1 << 18 ) -#define H3800_ASIC2_KPIO_UART_0_INT ( 1 << 19 ) -#define H3800_ASIC2_KPIO_UART_1_INT ( 1 << 20 ) -#define H3800_ASIC2_KPIO_TIMER_0_INT ( 1 << 21 ) -#define H3800_ASIC2_KPIO_TIMER_1_INT ( 1 << 22 ) -#define H3800_ASIC2_KPIO_TIMER_2_INT ( 1 << 23 ) - -#define KPIO_H3800_ASIC2_RECORD_BTN_N (1 << 0) /* Record button */ -#define KPIO_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Keypad */ -#define KPIO_H3800_ASIC2_KEY_5W2_N (1 << 2) /* */ -#define KPIO_H3800_ASIC2_KEY_5W3_N (1 << 3) /* */ -#define KPIO_H3800_ASIC2_KEY_5W4_N (1 << 4) /* */ -#define KPIO_H3800_ASIC2_KEY_5W5_N (1 << 5) /* */ -#define KPIO_H3800_ASIC2_KEY_LEFT_N (1 << 6) /* */ -#define KPIO_H3800_ASIC2_KEY_RIGHT_N (1 << 7) /* */ -#define KPIO_H3800_ASIC2_KEY_AP1_N (1 << 8) /* Old "Calendar" */ -#define KPIO_H3800_ASIC2_KEY_AP2_N (1 << 9) /* Old "Schedule" */ -#define KPIO_H3800_ASIC2_KEY_AP3_N (1 << 10) /* Old "Q" */ -#define KPIO_H3800_ASIC2_KEY_AP4_N (1 << 11) /* Old "Undo" */ - -/* Alternate KPIO functions (set by default) */ -#define KPIO_ALT_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Action key */ -#define KPIO_ALT_H3800_ASIC2_KEY_5W2_N (1 << 2) /* J1 of keypad input */ -#define KPIO_ALT_H3800_ASIC2_KEY_5W3_N (1 << 3) /* J2 of keypad input */ -#define KPIO_ALT_H3800_ASIC2_KEY_5W4_N (1 << 4) /* J3 of keypad input */ -#define KPIO_ALT_H3800_ASIC2_KEY_5W5_N (1 << 5) /* J4 of keypad input */ - -#define _H3800_ASIC2_SPI_Base 0x0400 -#define _H3800_ASIC2_SPI_Control 0x0000 /* R/W 8 bits */ -#define _H3800_ASIC2_SPI_Data 0x0004 /* R/W 8 bits */ -#define _H3800_ASIC2_SPI_ChipSelectDisabled 0x0008 /* W 8 bits */ - -#define H3800_ASIC2_SPI_Control H3800_ASIC2_OFFSET( u8, SPI, Control ) -#define H3800_ASIC2_SPI_Data H3800_ASIC2_OFFSET( u8, SPI, Data ) -#define H3800_ASIC2_SPI_ChipSelectDisabled H3800_ASIC2_OFFSET( u8, SPI, ChipSelectDisabled ) - -#define _H3800_ASIC2_PWM_0_Base 0x0600 -#define _H3800_ASIC2_PWM_1_Base 0x0700 -#define _H3800_ASIC2_PWM_TimeBase 0x0000 /* R/W 6 bits */ -#define _H3800_ASIC2_PWM_PeriodTime 0x0004 /* R/W 12 bits */ -#define _H3800_ASIC2_PWM_DutyTime 0x0008 /* R/W 12 bits */ - -#define H3800_ASIC2_PWM_0_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 0, TimeBase ) -#define H3800_ASIC2_PWM_0_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 0, PeriodTime ) -#define H3800_ASIC2_PWM_0_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 0, DutyTime ) - -#define H3800_ASIC2_PWM_1_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 1, TimeBase ) -#define H3800_ASIC2_PWM_1_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 1, PeriodTime ) -#define H3800_ASIC2_PWM_1_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 1, DutyTime ) - -#define H3800_ASIC2_PWM_TIMEBASE_MASK 0xf /* Low 4 bits sets time base, max = 8 */ -#define H3800_ASIC2_PWM_TIMEBASE_ENABLE ( 1 << 4 ) /* Enable clock */ -#define H3800_ASIC2_PWM_TIMEBASE_CLEAR ( 1 << 5 ) /* Clear the PWM */ - -#define _H3800_ASIC2_LED_0_Base 0x0800 -#define _H3800_ASIC2_LED_1_Base 0x0880 -#define _H3800_ASIC2_LED_2_Base 0x0900 -#define _H3800_ASIC2_LED_TimeBase 0x0000 /* R/W 7 bits */ -#define _H3800_ASIC2_LED_PeriodTime 0x0004 /* R/W 12 bits */ -#define _H3800_ASIC2_LED_DutyTime 0x0008 /* R/W 12 bits */ -#define _H3800_ASIC2_LED_AutoStopCount 0x000c /* R/W 16 bits */ - -#define H3800_ASIC2_LED_0_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 0, TimeBase ) -#define H3800_ASIC2_LED_0_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 0, PeriodTime ) -#define H3800_ASIC2_LED_0_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 0, DutyTime ) -#define H3800_ASIC2_LED_0_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 0, AutoStopClock ) - -#define H3800_ASIC2_LED_1_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 1, TimeBase ) -#define H3800_ASIC2_LED_1_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 1, PeriodTime ) -#define H3800_ASIC2_LED_1_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 1, DutyTime ) -#define H3800_ASIC2_LED_1_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 1, AutoStopClock ) - -#define H3800_ASIC2_LED_2_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 2, TimeBase ) -#define H3800_ASIC2_LED_2_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 2, PeriodTime ) -#define H3800_ASIC2_LED_2_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 2, DutyTime ) -#define H3800_ASIC2_LED_2_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 2, AutoStopClock ) - -#define H3800_ASIC2_LED_TIMEBASE_MASK 0x0f /* Low 4 bits sets time base, max = 13 */ -#define H3800_ASIC2_LED_TIMEBASE_BLINK ( 1 << 4 ) /* Enable blinking */ -#define H3800_ASIC2_LED_TIMEBASE_AUTOSTOP ( 1 << 5 ) -#define H3800_ASIC2_LED_TIMEBASE_ALWAYS ( 1 << 6 ) /* Enable blink always */ - -#define _H3800_ASIC2_UART_0_Base 0x0A00 -#define _H3800_ASIC2_UART_1_Base 0x0C00 -#define _H3800_ASIC2_UART_Receive 0x0000 /* R 8 bits */ -#define _H3800_ASIC2_UART_Transmit 0x0000 /* W 8 bits */ -#define _H3800_ASIC2_UART_IntEnable 0x0004 /* R/W 8 bits */ -#define _H3800_ASIC2_UART_IntVerify 0x0008 /* R/W 8 bits */ -#define _H3800_ASIC2_UART_FIFOControl 0x000c /* R/W 8 bits */ -#define _H3800_ASIC2_UART_LineControl 0x0010 /* R/W 8 bits */ -#define _H3800_ASIC2_UART_ModemStatus 0x0014 /* R/W 8 bits */ -#define _H3800_ASIC2_UART_LineStatus 0x0018 /* R/W 8 bits */ -#define _H3800_ASIC2_UART_ScratchPad 0x001c /* R/W 8 bits */ -#define _H3800_ASIC2_UART_DivisorLatchL 0x0020 /* R/W 8 bits */ -#define _H3800_ASIC2_UART_DivisorLatchH 0x0024 /* R/W 8 bits */ - -#define H3800_ASIC2_UART_0_Receive H3800_ASIC2_NOFFSET( u8, UART, 0, Receive ) -#define H3800_ASIC2_UART_0_Transmit H3800_ASIC2_NOFFSET( u8, UART, 0, Transmit ) -#define H3800_ASIC2_UART_0_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 0, IntEnable ) -#define H3800_ASIC2_UART_0_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 0, IntVerify ) -#define H3800_ASIC2_UART_0_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 0, FIFOControl ) -#define H3800_ASIC2_UART_0_LineControl H3800_ASIC2_NOFFSET( u8, UART, 0, LineControl ) -#define H3800_ASIC2_UART_0_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 0, ModemStatus ) -#define H3800_ASIC2_UART_0_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 0, LineStatus ) -#define H3800_ASIC2_UART_0_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 0, ScratchPad ) -#define H3800_ASIC2_UART_0_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchL ) -#define H3800_ASIC2_UART_0_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchH ) - -#define H3800_ASIC2_UART_1_Receive H3800_ASIC2_NOFFSET( u8, UART, 1, Receive ) -#define H3800_ASIC2_UART_1_Transmit H3800_ASIC2_NOFFSET( u8, UART, 1, Transmit ) -#define H3800_ASIC2_UART_1_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 1, IntEnable ) -#define H3800_ASIC2_UART_1_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 1, IntVerify ) -#define H3800_ASIC2_UART_1_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 1, FIFOControl ) -#define H3800_ASIC2_UART_1_LineControl H3800_ASIC2_NOFFSET( u8, UART, 1, LineControl ) -#define H3800_ASIC2_UART_1_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 1, ModemStatus ) -#define H3800_ASIC2_UART_1_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 1, LineStatus ) -#define H3800_ASIC2_UART_1_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 1, ScratchPad ) -#define H3800_ASIC2_UART_1_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchL ) -#define H3800_ASIC2_UART_1_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchH ) - -#define _H3800_ASIC2_TIMER_Base 0x0E00 -#define _H3800_ASIC2_TIMER_Command 0x0000 /* R/W 8 bits */ - -#define H3800_ASIC2_TIMER_Command H3800_ASIC2_OFFSET( u8, Timer, Command ) - -#define H3800_ASIC2_TIMER_GAT_0 ( 1 << 0 ) /* Gate enable, counter 0 */ -#define H3800_ASIC2_TIMER_GAT_1 ( 1 << 1 ) /* Gate enable, counter 1 */ -#define H3800_ASIC2_TIMER_GAT_2 ( 1 << 2 ) /* Gate enable, counter 2 */ -#define H3800_ASIC2_TIMER_CLK_0 ( 1 << 3 ) /* Clock enable, counter 0 */ -#define H3800_ASIC2_TIMER_CLK_1 ( 1 << 4 ) /* Clock enable, counter 1 */ -#define H3800_ASIC2_TIMER_CLK_2 ( 1 << 5 ) /* Clock enable, counter 2 */ -#define H3800_ASIC2_TIMER_MODE_0 ( 1 << 6 ) /* Mode 0 enable, counter 0 */ -#define H3800_ASIC2_TIMER_MODE_1 ( 1 << 7 ) /* Mode 0 enable, counter 1 */ - -#define _H3800_ASIC2_CLOCK_Base 0x1000 -#define _H3800_ASIC2_CLOCK_Enable 0x0000 /* R/W 18 bits */ - -#define H3800_ASIC2_CLOCK_Enable H3800_ASIC2_OFFSET( u32, CLOCK, Enable ) - -#define H3800_ASIC2_CLOCK_AUDIO_1 0x0001 /* Enable 4.1 MHz clock for 8Khz and 4khz sample rate */ -#define H3800_ASIC2_CLOCK_AUDIO_2 0x0002 /* Enable 12.3 MHz clock for 48Khz and 32khz sample rate */ -#define H3800_ASIC2_CLOCK_AUDIO_3 0x0004 /* Enable 5.6 MHz clock for 11 kHZ sample rate */ -#define H3800_ASIC2_CLOCK_AUDIO_4 0x0008 /* Enable 11.289 MHz clock for 44 and 22 kHz sample rate */ -#define H3800_ASIC2_CLOCK_ADC ( 1 << 4 ) /* 1.024 MHz clock to ADC */ -#define H3800_ASIC2_CLOCK_SPI ( 1 << 5 ) /* 4.096 MHz clock to SPI */ -#define H3800_ASIC2_CLOCK_OWM ( 1 << 6 ) /* 4.096 MHz clock to OWM */ -#define H3800_ASIC2_CLOCK_PWM ( 1 << 7 ) /* 2.048 MHz clock to PWM */ -#define H3800_ASIC2_CLOCK_UART_1 ( 1 << 8 ) /* 24.576 MHz clock to UART1 (turn off bit 16) */ -#define H3800_ASIC2_CLOCK_UART_0 ( 1 << 9 ) /* 24.576 MHz clock to UART0 (turn off bit 17) */ -#define H3800_ASIC2_CLOCK_SD_1 ( 1 << 10 ) /* 16.934 MHz to SD */ -#define H3800_ASIC2_CLOCK_SD_2 ( 2 << 10 ) /* 24.576 MHz to SD */ -#define H3800_ASIC2_CLOCK_SD_3 ( 3 << 10 ) /* 33.869 MHz to SD */ -#define H3800_ASIC2_CLOCK_SD_4 ( 4 << 10 ) /* 49.152 MHz to SD */ -#define H3800_ASIC2_CLOCK_EX0 ( 1 << 13 ) /* Enable 32.768 kHz crystal */ -#define H3800_ASIC2_CLOCK_EX1 ( 1 << 14 ) /* Enable 24.576 MHz crystal */ -#define H3800_ASIC2_CLOCK_EX2 ( 1 << 15 ) /* Enable 33.869 MHz crystal */ -#define H3800_ASIC2_CLOCK_SLOW_UART_1 ( 1 << 16 ) /* Enable 3.686 MHz to UART1 (turn off bit 8) */ -#define H3800_ASIC2_CLOCK_SLOW_UART_0 ( 1 << 17 ) /* Enable 3.686 MHz to UART0 (turn off bit 9) */ - -#define _H3800_ASIC2_ADC_Base 0x1200 -#define _H3800_ASIC2_ADC_Multiplexer 0x0000 /* R/W 4 bits - low 3 bits set channel */ -#define _H3800_ASIC2_ADC_ControlStatus 0x0004 /* R/W 8 bits */ -#define _H3800_ASIC2_ADC_Data 0x0008 /* R 10 bits */ - -#define H3800_ASIC2_ADC_Multiplexer H3800_ASIC2_OFFSET( u8, ADC, Multiplexer ) -#define H3800_ASIC2_ADC_ControlStatus H3800_ASIC2_OFFSET( u8, ADC, ControlStatus ) -#define H3800_ASIC2_ADC_Data H3800_ASIC2_OFFSET( u16, ADC, Data ) - -#define H3600_ASIC2_ADC_MUX_CHANNEL_MASK 0x07 /* Low 3 bits sets channel. max = 4 */ -#define H3600_ASIC2_ADC_MUX_CLKEN ( 1 << 3 ) /* Enable clock */ - -#define H3600_ASIC2_ADC_CSR_ADPS_MASK 0x0f /* Low 4 bits sets prescale, max = 8 */ -#define H3600_ASIC2_ADC_CSR_FREE_RUN ( 1 << 4 ) -#define H3600_ASIC2_ADC_CSR_INT_ENABLE ( 1 << 5 ) -#define H3600_ASIC2_ADC_CSR_START ( 1 << 6 ) /* Set to start conversion. Goes to 0 when done */ -#define H3600_ASIC2_ADC_CSR_ENABLE ( 1 << 7 ) /* 1:power up ADC, 0:power down */ - - -#define _H3800_ASIC2_INTR_Base 0x1600 -#define _H3800_ASIC2_INTR_MaskAndFlag 0x0000 /* R/(W) 8bits */ -#define _H3800_ASIC2_INTR_ClockPrescale 0x0004 /* R/(W) 5bits */ -#define _H3800_ASIC2_INTR_TimerSet 0x0008 /* R/(W) 8bits */ - -#define H3800_ASIC2_INTR_MaskAndFlag H3800_ASIC2_OFFSET( u8, INTR, MaskAndFlag ) -#define H3800_ASIC2_INTR_ClockPrescale H3800_ASIC2_OFFSET( u8, INTR, ClockPrescale ) -#define H3800_ASIC2_INTR_TimerSet H3800_ASIC2_OFFSET( u8, INTR, TimerSet ) - -#define H3800_ASIC2_INTR_GLOBAL_MASK ( 1 << 0 ) /* Global interrupt mask */ -#define H3800_ASIC2_INTR_POWER_ON_RESET ( 1 << 1 ) /* 01: Power on reset (bits 1 & 2 ) */ -#define H3800_ASIC2_INTR_EXTERNAL_RESET ( 2 << 1 ) /* 10: External reset (bits 1 & 2 ) */ -#define H3800_ASIC2_INTR_MASK_UART_0 ( 1 << 4 ) -#define H3800_ASIC2_INTR_MASK_UART_1 ( 1 << 5 ) -#define H3800_ASIC2_INTR_MASK_TIMER ( 1 << 6 ) -#define H3800_ASIC2_INTR_MASK_OWM ( 1 << 7 ) - -#define H3800_ASIC2_INTR_CLOCK_PRESCALE 0x0f /* 4 bits, max 14 */ -#define H3800_ASIC2_INTR_SET ( 1 << 4 ) /* Time base enable */ - - -#define _H3800_ASIC2_OWM_Base 0x1800 -#define _H3800_ASIC2_OWM_Command 0x0000 /* R/W 4 bits command register */ -#define _H3800_ASIC2_OWM_Data 0x0004 /* R/W 8 bits, transmit / receive buffer */ -#define _H3800_ASIC2_OWM_Interrupt 0x0008 /* R/W Command register */ -#define _H3800_ASIC2_OWM_InterruptEnable 0x000c /* R/W Command register */ -#define _H3800_ASIC2_OWM_ClockDivisor 0x0010 /* R/W 5 bits of divisor and pre-scale */ - -#define H3800_ASIC2_OWM_Command H3800_ASIC2_OFFSET( u8, OWM, Command ) -#define H3800_ASIC2_OWM_Data H3800_ASIC2_OFFSET( u8, OWM, Data ) -#define H3800_ASIC2_OWM_Interrupt H3800_ASIC2_OFFSET( u8, OWM, Interrupt ) -#define H3800_ASIC2_OWM_InterruptEnable H3800_ASIC2_OFFSET( u8, OWM, InterruptEnable ) -#define H3800_ASIC2_OWM_ClockDivisor H3800_ASIC2_OFFSET( u8, OWM, ClockDivisor ) - -#define H3800_ASIC2_OWM_CMD_ONE_WIRE_RESET ( 1 << 0 ) /* Set to force reset on 1-wire bus */ -#define H3800_ASIC2_OWM_CMD_SRA ( 1 << 1 ) /* Set to switch to Search ROM accelerator mode */ -#define H3800_ASIC2_OWM_CMD_DQ_OUTPUT ( 1 << 2 ) /* Write only - forces bus low */ -#define H3800_ASIC2_OWM_CMD_DQ_INPUT ( 1 << 3 ) /* Read only - reflects state of bus */ - -#define H3800_ASIC2_OWM_INT_PD ( 1 << 0 ) /* Presence detect */ -#define H3800_ASIC2_OWM_INT_PDR ( 1 << 1 ) /* Presence detect result */ -#define H3800_ASIC2_OWM_INT_TBE ( 1 << 2 ) /* Transmit buffer empty */ -#define H3800_ASIC2_OWM_INT_TEMT ( 1 << 3 ) /* Transmit shift register empty */ -#define H3800_ASIC2_OWM_INT_RBF ( 1 << 4 ) /* Receive buffer full */ - -#define H3800_ASIC2_OWM_INTEN_EPD ( 1 << 0 ) /* Enable receive buffer full interrupt */ -#define H3800_ASIC2_OWM_INTEN_IAS ( 1 << 1 ) /* Enable transmit shift register empty interrupt */ -#define H3800_ASIC2_OWM_INTEN_ETBE ( 1 << 2 ) /* Enable transmit buffer empty interrupt */ -#define H3800_ASIC2_OWM_INTEN_ETMT ( 1 << 3 ) /* INTR active state */ -#define H3800_ASIC2_OWM_INTEN_ERBF ( 1 << 4 ) /* Enable presence detect interrupt */ - -#define _H3800_ASIC2_FlashCtl_Base 0x1A00 - -/****************************************************/ -/* H3800, ASIC #1 - * This ASIC is accesed through ASIC #2, and - * mapped into the 1c00 - 1f00 region - */ - -#define H3800_ASIC1_OFFSET(s,x,y) \ - (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC1_ ## x ## _Base + (_H3800_ASIC1_ ## x ## _ ## y << 1)))) - -#define _H3800_ASIC1_MMC_Base 0x1c00 - -#define _H3800_ASIC1_MMC_StartStopClock 0x00 /* R/W 8bit */ -#define _H3800_ASIC1_MMC_Status 0x02 /* R See below, default 0x0040 */ -#define _H3800_ASIC1_MMC_ClockRate 0x04 /* R/W 8bit, low 3 bits are clock divisor */ -#define _H3800_ASIC1_MMC_SPIRegister 0x08 /* R/W 8bit, see below */ -#define _H3800_ASIC1_MMC_CmdDataCont 0x0a /* R/W 8bit, write to start MMC adapter */ -#define _H3800_ASIC1_MMC_ResponseTimeout 0x0c /* R/W 8bit, clocks before response timeout */ -#define _H3800_ASIC1_MMC_ReadTimeout 0x0e /* R/W 16bit, clocks before received data timeout */ -#define _H3800_ASIC1_MMC_BlockLength 0x10 /* R/W 10bit */ -#define _H3800_ASIC1_MMC_NumOfBlocks 0x12 /* R/W 16bit, in block mode, number of blocks */ -#define _H3800_ASIC1_MMC_InterruptMask 0x1a /* R/W 8bit */ -#define _H3800_ASIC1_MMC_CommandNumber 0x1c /* R/W 6 bits */ -#define _H3800_ASIC1_MMC_ArgumentH 0x1e /* R/W 16 bits */ -#define _H3800_ASIC1_MMC_ArgumentL 0x20 /* R/W 16 bits */ -#define _H3800_ASIC1_MMC_ResFifo 0x22 /* R 8 x 16 bits - contains response FIFO */ -#define _H3800_ASIC1_MMC_BufferPartFull 0x28 /* R/W 8 bits */ - -#define H3800_ASIC1_MMC_StartStopClock H3800_ASIC1_OFFSET( u8, MMC, StartStopClock ) -#define H3800_ASIC1_MMC_Status H3800_ASIC1_OFFSET( u16, MMC, Status ) -#define H3800_ASIC1_MMC_ClockRate H3800_ASIC1_OFFSET( u8, MMC, ClockRate ) -#define H3800_ASIC1_MMC_SPIRegister H3800_ASIC1_OFFSET( u8, MMC, SPIRegister ) -#define H3800_ASIC1_MMC_CmdDataCont H3800_ASIC1_OFFSET( u8, MMC, CmdDataCont ) -#define H3800_ASIC1_MMC_ResponseTimeout H3800_ASIC1_OFFSET( u8, MMC, ResponseTimeout ) -#define H3800_ASIC1_MMC_ReadTimeout H3800_ASIC1_OFFSET( u16, MMC, ReadTimeout ) -#define H3800_ASIC1_MMC_BlockLength H3800_ASIC1_OFFSET( u16, MMC, BlockLength ) -#define H3800_ASIC1_MMC_NumOfBlocks H3800_ASIC1_OFFSET( u16, MMC, NumOfBlocks ) -#define H3800_ASIC1_MMC_InterruptMask H3800_ASIC1_OFFSET( u8, MMC, InterruptMask ) -#define H3800_ASIC1_MMC_CommandNumber H3800_ASIC1_OFFSET( u8, MMC, CommandNumber ) -#define H3800_ASIC1_MMC_ArgumentH H3800_ASIC1_OFFSET( u16, MMC, ArgumentH ) -#define H3800_ASIC1_MMC_ArgumentL H3800_ASIC1_OFFSET( u16, MMC, ArgumentL ) -#define H3800_ASIC1_MMC_ResFifo H3800_ASIC1_OFFSET( u16, MMC, ResFifo ) -#define H3800_ASIC1_MMC_BufferPartFull H3800_ASIC1_OFFSET( u8, MMC, BufferPartFull ) - -#define H3800_ASIC1_MMC_STOP_CLOCK (1 << 0) /* Write to "StartStopClock" register */ -#define H3800_ASIC1_MMC_START_CLOCK (1 << 1) - -#define H3800_ASIC1_MMC_STATUS_READ_TIMEOUT (1 << 0) -#define H3800_ASIC1_MMC_STATUS_RESPONSE_TIMEOUT (1 << 1) -#define H3800_ASIC1_MMC_STATUS_CRC_WRITE_ERROR (1 << 2) -#define H3800_ASIC1_MMC_STATUS_CRC_READ_ERROR (1 << 3) -#define H3800_ASIC1_MMC_STATUS_SPI_READ_ERROR (1 << 4) /* SPI data token error received */ -#define H3800_ASIC1_MMC_STATUS_CRC_RESPONSE_ERROR (1 << 5) -#define H3800_ASIC1_MMC_STATUS_FIFO_EMPTY (1 << 6) -#define H3800_ASIC1_MMC_STATUS_FIFO_FULL (1 << 7) -#define H3800_ASIC1_MMC_STATUS_CLOCK_ENABLE (1 << 8) /* MultiMediaCard clock stopped */ -#define H3800_ASIC1_MMC_STATUS_DATA_TRANSFER_DONE (1 << 11) /* Write operation, indicates transfer finished */ -#define H3800_ASIC1_MMC_STATUS_END_PROGRAM (1 << 12) /* End write and read operations */ -#define H3800_ASIC1_MMC_STATUS_END_COMMAND_RESPONSE (1 << 13) /* End command response */ - -#define H3800_ASIC1_MMC_SPI_REG_SPI_ENABLE (1 << 0) /* Enables SPI mode */ -#define H3800_ASIC1_MMC_SPI_REG_CRC_ON (1 << 1) /* 1:turn on CRC */ -#define H3800_ASIC1_MMC_SPI_REG_SPI_CS_ENABLE (1 << 2) /* 1:turn on SPI CS */ -#define H3800_ASIC1_MMC_SPI_REG_CS_ADDRESS_MASK 0x38 /* Bits 3,4,5 are the SPI CS relative address */ - -#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_NO_RESPONSE 0x00 -#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R1 0x01 -#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R2 0x02 -#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R3 0x03 -#define H3800_ASIC1_MMC_CMD_DATA_CONT_DATA_ENABLE (1 << 2) /* This command contains a data transfer */ -#define H3800_ASIC1_MMC_CMD_DATA_CONT_WRITE (1 << 3) /* This data transfer is a write */ -#define H3800_ASIC1_MMC_CMD_DATA_CONT_STREAM_MODE (1 << 4) /* This data transfer is in stream mode */ -#define H3800_ASIC1_MMC_CMD_DATA_CONT_BUSY_BIT (1 << 5) /* Busy signal expected after current cmd */ -#define H3800_ASIC1_MMC_CMD_DATA_CONT_INITIALIZE (1 << 6) /* Enables the 80 bits for initializing card */ - -#define H3800_ASIC1_MMC_INT_MASK_DATA_TRANSFER_DONE (1 << 0) -#define H3800_ASIC1_MMC_INT_MASK_PROGRAM_DONE (1 << 1) -#define H3800_ASIC1_MMC_INT_MASK_END_COMMAND_RESPONSE (1 << 2) -#define H3800_ASIC1_MMC_INT_MASK_BUFFER_READY (1 << 3) - -#define H3800_ASIC1_MMC_BUFFER_PART_FULL (1 << 0) - -/********* GPIO **********/ - -#define _H3800_ASIC1_GPIO_Base 0x1e00 - -#define _H3800_ASIC1_GPIO_Mask 0x30 /* R/W 0:don't mask, 1:mask interrupt */ -#define _H3800_ASIC1_GPIO_Direction 0x32 /* R/W 0:input, 1:output */ -#define _H3800_ASIC1_GPIO_Out 0x34 /* R/W 0:output low, 1:output high */ -#define _H3800_ASIC1_GPIO_TriggerType 0x36 /* R/W 0:level, 1:edge */ -#define _H3800_ASIC1_GPIO_EdgeTrigger 0x38 /* R/W 0:falling, 1:rising */ -#define _H3800_ASIC1_GPIO_LevelTrigger 0x3A /* R/W 0:low, 1:high level detect */ -#define _H3800_ASIC1_GPIO_LevelStatus 0x3C /* R/W 0:none, 1:detect */ -#define _H3800_ASIC1_GPIO_EdgeStatus 0x3E /* R/W 0:none, 1:detect */ -#define _H3800_ASIC1_GPIO_State 0x40 /* R See masks below (default 0) */ -#define _H3800_ASIC1_GPIO_Reset 0x42 /* R/W See masks below (default 0x04) */ -#define _H3800_ASIC1_GPIO_SleepMask 0x44 /* R/W 0:don't mask, 1:mask trigger in sleep mode */ -#define _H3800_ASIC1_GPIO_SleepDir 0x46 /* R/W direction 0:input, 1:output in sleep mode */ -#define _H3800_ASIC1_GPIO_SleepOut 0x48 /* R/W level 0:low, 1:high in sleep mode */ -#define _H3800_ASIC1_GPIO_Status 0x4A /* R Pin status */ -#define _H3800_ASIC1_GPIO_BattFaultDir 0x4C /* R/W direction 0:input, 1:output in batt_fault */ -#define _H3800_ASIC1_GPIO_BattFaultOut 0x4E /* R/W level 0:low, 1:high in batt_fault */ - -#define H3800_ASIC1_GPIO_Mask H3800_ASIC1_OFFSET( u16, GPIO, Mask ) -#define H3800_ASIC1_GPIO_Direction H3800_ASIC1_OFFSET( u16, GPIO, Direction ) -#define H3800_ASIC1_GPIO_Out H3800_ASIC1_OFFSET( u16, GPIO, Out ) -#define H3800_ASIC1_GPIO_TriggerType H3800_ASIC1_OFFSET( u16, GPIO, TriggerType ) -#define H3800_ASIC1_GPIO_EdgeTrigger H3800_ASIC1_OFFSET( u16, GPIO, EdgeTrigger ) -#define H3800_ASIC1_GPIO_LevelTrigger H3800_ASIC1_OFFSET( u16, GPIO, LevelTrigger ) -#define H3800_ASIC1_GPIO_LevelStatus H3800_ASIC1_OFFSET( u16, GPIO, LevelStatus ) -#define H3800_ASIC1_GPIO_EdgeStatus H3800_ASIC1_OFFSET( u16, GPIO, EdgeStatus ) -#define H3800_ASIC1_GPIO_State H3800_ASIC1_OFFSET( u8, GPIO, State ) -#define H3800_ASIC1_GPIO_Reset H3800_ASIC1_OFFSET( u8, GPIO, Reset ) -#define H3800_ASIC1_GPIO_SleepMask H3800_ASIC1_OFFSET( u16, GPIO, SleepMask ) -#define H3800_ASIC1_GPIO_SleepDir H3800_ASIC1_OFFSET( u16, GPIO, SleepDir ) -#define H3800_ASIC1_GPIO_SleepOut H3800_ASIC1_OFFSET( u16, GPIO, SleepOut ) -#define H3800_ASIC1_GPIO_Status H3800_ASIC1_OFFSET( u16, GPIO, Status ) -#define H3800_ASIC1_GPIO_BattFaultDir H3800_ASIC1_OFFSET( u16, GPIO, BattFaultDir ) -#define H3800_ASIC1_GPIO_BattFaultOut H3800_ASIC1_OFFSET( u16, GPIO, BattFaultOut ) - -#define H3800_ASIC1_GPIO_STATE_MASK (1 << 0) -#define H3800_ASIC1_GPIO_STATE_DIRECTION (1 << 1) -#define H3800_ASIC1_GPIO_STATE_OUT (1 << 2) -#define H3800_ASIC1_GPIO_STATE_TRIGGER_TYPE (1 << 3) -#define H3800_ASIC1_GPIO_STATE_EDGE_TRIGGER (1 << 4) -#define H3800_ASIC1_GPIO_STATE_LEVEL_TRIGGER (1 << 5) - -#define H3800_ASIC1_GPIO_RESET_SOFTWARE (1 << 0) -#define H3800_ASIC1_GPIO_RESET_AUTO_SLEEP (1 << 1) -#define H3800_ASIC1_GPIO_RESET_FIRST_PWR_ON (1 << 2) - -/* These are all outputs */ -#define GPIO_H3800_ASIC1_IR_ON_N (1 << 0) /* Apply power to the IR Module */ -#define GPIO_H3800_ASIC1_SD_PWR_ON (1 << 1) /* Secure Digital power on */ -#define GPIO_H3800_ASIC1_RS232_ON (1 << 2) /* Turn on power to the RS232 chip ? */ -#define GPIO_H3800_ASIC1_PULSE_GEN (1 << 3) /* Goes to speaker / earphone */ -#define GPIO_H3800_ASIC1_CH_TIMER (1 << 4) /* */ -#define GPIO_H3800_ASIC1_LCD_5V_ON (1 << 5) /* Enables LCD_5V */ -#define GPIO_H3800_ASIC1_LCD_ON (1 << 6) /* Enables LCD_3V */ -#define GPIO_H3800_ASIC1_LCD_PCI (1 << 7) /* Connects to PDWN on LCD controller */ -#define GPIO_H3800_ASIC1_VGH_ON (1 << 8) /* Drives VGH on the LCD (+9??) */ -#define GPIO_H3800_ASIC1_VGL_ON (1 << 9) /* Drivers VGL on the LCD (-6??) */ -#define GPIO_H3800_ASIC1_FL_PWR_ON (1 << 10) /* Frontlight power on */ -#define GPIO_H3800_ASIC1_BT_PWR_ON (1 << 11) /* Bluetooth power on */ -#define GPIO_H3800_ASIC1_SPK_ON (1 << 12) /* */ -#define GPIO_H3800_ASIC1_EAR_ON_N (1 << 13) /* */ -#define GPIO_H3800_ASIC1_AUD_PWR_ON (1 << 14) /* */ - -/* Write enable for the flash */ - -#define _H3800_ASIC1_FlashWP_Base 0x1F00 -#define _H3800_ASIC1_FlashWP_VPP_ON 0x00 /* R 1: write, 0: protect */ -#define H3800_ASIC1_FlashWP_VPP_ON H3800_ASIC1_OFFSET( u8, FlashWP, VPP_ON ) - -#endif /* _INCLUDE_H3600_GPIO_H_ */ diff --git a/arch/arm/mach-sa1100/include/mach/h3xxx.h b/arch/arm/mach-sa1100/include/mach/h3xxx.h new file mode 100644 index 00000000000..603d4343f7f --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/h3xxx.h @@ -0,0 +1,85 @@ +/* + * Definitions for Compaq iPAQ H3100 and H3600 handheld computers + * + * (c) 2000 Compaq Computer Corporation. (Author: Jamey Hicks) + * (c) 2009 Dmitry Artamonow <mad_soft@inbox.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_H3XXX_H_ +#define _INCLUDE_H3XXX_H_ + +#include "hardware.h" /* Gives GPIO_MAX */ + +/* Physical memory regions corresponding to chip selects */ +#define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000) +#define H3600_BANK_2_PHYS SA1100_CS2_PHYS +#define H3600_BANK_4_PHYS SA1100_CS4_PHYS + +/* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */ +#define H3600_EGPIO_VIRT 0xf0000000 +#define H3600_BANK_2_VIRT 0xf1000000 +#define H3600_BANK_4_VIRT 0xf3800000 + +/* + * gpiolib numbers for all iPAQs + */ +#define H3XXX_GPIO_PWR_BUTTON 0 +#define H3XXX_GPIO_PCMCIA_CD1 10 +#define H3XXX_GPIO_PCMCIA_IRQ1 11 +#define H3XXX_GPIO_PCMCIA_CD0 17 +#define H3XXX_GPIO_ACTION_BUTTON 18 +#define H3XXX_GPIO_SYS_CLK 19 +#define H3XXX_GPIO_PCMCIA_IRQ0 21 +#define H3XXX_GPIO_COM_DCD 23 +#define H3XXX_GPIO_OPTION 24 +#define H3XXX_GPIO_COM_CTS 25 +#define H3XXX_GPIO_COM_RTS 26 + +/* machine-specific gpios */ + +#define H3100_GPIO_BT_ON 2 +#define H3100_GPIO_QMUTE 4 +#define H3100_GPIO_LCD_3V_ON 5 +#define H3100_GPIO_AUD_ON 6 +#define H3100_GPIO_AUD_PWR_ON 7 +#define H3100_GPIO_IR_ON 8 +#define H3100_GPIO_IR_FSEL 9 + +#define H3600_GPIO_CLK_SET0 12 /* audio sample rate clock generator */ +#define H3600_GPIO_CLK_SET1 13 +#define H3600_GPIO_SOFT_RESET 20 /* also known as BATT_FAULT */ +#define H3600_GPIO_OPT_LOCK 22 +#define H3600_GPIO_OPT_DET 27 + + +/* H3100 / 3600 EGPIO pins */ +#define H3XXX_EGPIO_BASE (GPIO_MAX + 1) + +#define H3XXX_EGPIO_VPP_ON (H3XXX_EGPIO_BASE + 0) +#define H3XXX_EGPIO_CARD_RESET (H3XXX_EGPIO_BASE + 1) /* reset the attached pcmcia/compactflash card. active high. */ +#define H3XXX_EGPIO_OPT_RESET (H3XXX_EGPIO_BASE + 2) /* reset the attached option pack. active high. */ +#define H3XXX_EGPIO_CODEC_NRESET (H3XXX_EGPIO_BASE + 3) /* reset the onboard UDA1341. active low. */ +#define H3XXX_EGPIO_OPT_NVRAM_ON (H3XXX_EGPIO_BASE + 4) /* apply power to optionpack nvram, active high. */ +#define H3XXX_EGPIO_OPT_ON (H3XXX_EGPIO_BASE + 5) /* full power to option pack. active high. */ +#define H3XXX_EGPIO_LCD_ON (H3XXX_EGPIO_BASE + 6) /* enable 3.3V to LCD. active high. */ +#define H3XXX_EGPIO_RS232_ON (H3XXX_EGPIO_BASE + 7) /* UART3 transceiver force on. Active high. */ + +/* H3600 only EGPIO pins */ +#define H3600_EGPIO_LCD_PCI (H3XXX_EGPIO_BASE + 8) /* LCD control IC enable. active high. */ +#define H3600_EGPIO_IR_ON (H3XXX_EGPIO_BASE + 9) /* apply power to IR module. active high. */ +#define H3600_EGPIO_AUD_AMP_ON (H3XXX_EGPIO_BASE + 10) /* apply power to audio power amp. active high. */ +#define H3600_EGPIO_AUD_PWR_ON (H3XXX_EGPIO_BASE + 11) /* apply power to reset of audio circuit. active high. */ +#define H3600_EGPIO_QMUTE (H3XXX_EGPIO_BASE + 12) /* mute control for onboard UDA1341. active high. */ +#define H3600_EGPIO_IR_FSEL (H3XXX_EGPIO_BASE + 13) /* IR speed select: 1->fast, 0->slow */ +#define H3600_EGPIO_LCD_5V_ON (H3XXX_EGPIO_BASE + 14) /* enable 5V to LCD. active high. */ +#define H3600_EGPIO_LVDD_ON (H3XXX_EGPIO_BASE + 15) /* enable 9V and -6.5V to LCD. */ + +void __init h3xxx_map_io(void); +void __init h3xxx_mach_init(void); + +#endif /* _INCLUDE_H3XXX_H_ */ diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h index 60711822b12..cbedd75a9d6 100644 --- a/arch/arm/mach-sa1100/include/mach/hardware.h +++ b/arch/arm/mach-sa1100/include/mach/hardware.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-sa1100/include/mach/hardware.h * - * Copyright (C) 1998 Nicolas Pitre <nico@cam.org> + * Copyright (C) 1998 Nicolas Pitre <nico@fluxnic.net> * * This file contains the hardware definitions for SA1100 architecture * @@ -32,7 +32,7 @@ #define PIO_START 0x80000000 /* physical start of IO space */ #define io_p2v( x ) \ - ( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE ) + IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE ) #define io_v2p( x ) \ ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START ) @@ -47,6 +47,8 @@ #define CPU_SA1110_ID (0x6901b110) #define CPU_SA1110_MASK (0xfffffff0) +#define __MREG(x) IOMEM(io_p2v(x)) + #ifndef __ASSEMBLY__ #include <asm/cputype.h> @@ -56,7 +58,7 @@ #define cpu_is_sa1100() ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID) #define cpu_is_sa1110() ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID) -# define __REG(x) (*((volatile unsigned long *)io_p2v(x))) +# define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x))) # define __PREG(x) (io_v2p((unsigned long)&(x))) static inline unsigned long get_clock_tick_rate(void) diff --git a/arch/arm/mach-sa1100/include/mach/io.h b/arch/arm/mach-sa1100/include/mach/io.h deleted file mode 100644 index d8b43f3dcd2..00000000000 --- a/arch/arm/mach-sa1100/include/mach/io.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * arch/arm/mach-sa1100/include/mach/io.h - * - * Copyright (C) 1997-1999 Russell King - * - * Modifications: - * 06-12-1997 RMK Created. - * 07-04-1999 RMK Major cleanup - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * We don't actually have real ISA nor PCI buses, but there is so many - * drivers out there that might just work if we fake them... - */ -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) - -#endif diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h index 0cb36609b3a..3790298b714 100644 --- a/arch/arm/mach-sa1100/include/mach/irqs.h +++ b/arch/arm/mach-sa1100/include/mach/irqs.h @@ -68,130 +68,22 @@ #define IRQ_BOARD_START 49 #define IRQ_BOARD_END 65 -#define IRQ_SA1111_START (IRQ_BOARD_END) -#define IRQ_GPAIN0 (IRQ_BOARD_END + 0) -#define IRQ_GPAIN1 (IRQ_BOARD_END + 1) -#define IRQ_GPAIN2 (IRQ_BOARD_END + 2) -#define IRQ_GPAIN3 (IRQ_BOARD_END + 3) -#define IRQ_GPBIN0 (IRQ_BOARD_END + 4) -#define IRQ_GPBIN1 (IRQ_BOARD_END + 5) -#define IRQ_GPBIN2 (IRQ_BOARD_END + 6) -#define IRQ_GPBIN3 (IRQ_BOARD_END + 7) -#define IRQ_GPBIN4 (IRQ_BOARD_END + 8) -#define IRQ_GPBIN5 (IRQ_BOARD_END + 9) -#define IRQ_GPCIN0 (IRQ_BOARD_END + 10) -#define IRQ_GPCIN1 (IRQ_BOARD_END + 11) -#define IRQ_GPCIN2 (IRQ_BOARD_END + 12) -#define IRQ_GPCIN3 (IRQ_BOARD_END + 13) -#define IRQ_GPCIN4 (IRQ_BOARD_END + 14) -#define IRQ_GPCIN5 (IRQ_BOARD_END + 15) -#define IRQ_GPCIN6 (IRQ_BOARD_END + 16) -#define IRQ_GPCIN7 (IRQ_BOARD_END + 17) -#define IRQ_MSTXINT (IRQ_BOARD_END + 18) -#define IRQ_MSRXINT (IRQ_BOARD_END + 19) -#define IRQ_MSSTOPERRINT (IRQ_BOARD_END + 20) -#define IRQ_TPTXINT (IRQ_BOARD_END + 21) -#define IRQ_TPRXINT (IRQ_BOARD_END + 22) -#define IRQ_TPSTOPERRINT (IRQ_BOARD_END + 23) -#define SSPXMTINT (IRQ_BOARD_END + 24) -#define SSPRCVINT (IRQ_BOARD_END + 25) -#define SSPROR (IRQ_BOARD_END + 26) -#define AUDXMTDMADONEA (IRQ_BOARD_END + 32) -#define AUDRCVDMADONEA (IRQ_BOARD_END + 33) -#define AUDXMTDMADONEB (IRQ_BOARD_END + 34) -#define AUDRCVDMADONEB (IRQ_BOARD_END + 35) -#define AUDTFSR (IRQ_BOARD_END + 36) -#define AUDRFSR (IRQ_BOARD_END + 37) -#define AUDTUR (IRQ_BOARD_END + 38) -#define AUDROR (IRQ_BOARD_END + 39) -#define AUDDTS (IRQ_BOARD_END + 40) -#define AUDRDD (IRQ_BOARD_END + 41) -#define AUDSTO (IRQ_BOARD_END + 42) -#define IRQ_USBPWR (IRQ_BOARD_END + 43) -#define IRQ_HCIM (IRQ_BOARD_END + 44) -#define IRQ_HCIBUFFACC (IRQ_BOARD_END + 45) -#define IRQ_HCIRMTWKP (IRQ_BOARD_END + 46) -#define IRQ_NHCIMFCIR (IRQ_BOARD_END + 47) -#define IRQ_USB_PORT_RESUME (IRQ_BOARD_END + 48) -#define IRQ_S0_READY_NINT (IRQ_BOARD_END + 49) -#define IRQ_S1_READY_NINT (IRQ_BOARD_END + 50) -#define IRQ_S0_CD_VALID (IRQ_BOARD_END + 51) -#define IRQ_S1_CD_VALID (IRQ_BOARD_END + 52) -#define IRQ_S0_BVD1_STSCHG (IRQ_BOARD_END + 53) -#define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54) - -#define IRQ_LOCOMO_START (IRQ_BOARD_END) -#define IRQ_LOCOMO_KEY (IRQ_BOARD_END + 0) -#define IRQ_LOCOMO_GPIO0 (IRQ_BOARD_END + 1) -#define IRQ_LOCOMO_GPIO1 (IRQ_BOARD_END + 2) -#define IRQ_LOCOMO_GPIO2 (IRQ_BOARD_END + 3) -#define IRQ_LOCOMO_GPIO3 (IRQ_BOARD_END + 4) -#define IRQ_LOCOMO_GPIO4 (IRQ_BOARD_END + 5) -#define IRQ_LOCOMO_GPIO5 (IRQ_BOARD_END + 6) -#define IRQ_LOCOMO_GPIO6 (IRQ_BOARD_END + 7) -#define IRQ_LOCOMO_GPIO7 (IRQ_BOARD_END + 8) -#define IRQ_LOCOMO_GPIO8 (IRQ_BOARD_END + 9) -#define IRQ_LOCOMO_GPIO9 (IRQ_BOARD_END + 10) -#define IRQ_LOCOMO_GPIO10 (IRQ_BOARD_END + 11) -#define IRQ_LOCOMO_GPIO11 (IRQ_BOARD_END + 12) -#define IRQ_LOCOMO_GPIO12 (IRQ_BOARD_END + 13) -#define IRQ_LOCOMO_GPIO13 (IRQ_BOARD_END + 14) -#define IRQ_LOCOMO_GPIO14 (IRQ_BOARD_END + 15) -#define IRQ_LOCOMO_GPIO15 (IRQ_BOARD_END + 16) -#define IRQ_LOCOMO_LT (IRQ_BOARD_END + 17) -#define IRQ_LOCOMO_SPI_RFR (IRQ_BOARD_END + 18) -#define IRQ_LOCOMO_SPI_RFW (IRQ_BOARD_END + 19) -#define IRQ_LOCOMO_SPI_REND (IRQ_BOARD_END + 20) -#define IRQ_LOCOMO_SPI_TEND (IRQ_BOARD_END + 21) - /* * Figure out the MAX IRQ number. * - * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1. - * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1 - * Otherwise, we have the standard IRQs only. + * Neponset, SA1111 and UCB1x00 are sparse IRQ aware, so can dynamically + * allocate their IRQs above NR_IRQS. + * + * LoCoMo has 4 additional IRQs, but is not sparse IRQ aware, and so has + * to be included in the NR_IRQS calculation. */ -#ifdef CONFIG_SA1111 -#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1) -#elif defined(CONFIG_SA1100_H3800) -#define NR_IRQS (IRQ_BOARD_END) -#elif defined(CONFIG_SHARP_LOCOMO) -#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) +#ifdef CONFIG_SHARP_LOCOMO +#define NR_IRQS_LOCOMO 4 #else -#define NR_IRQS (IRQ_BOARD_START) +#define NR_IRQS_LOCOMO 0 #endif -/* - * Board specific IRQs. Define them here. - * Do not surround them with ifdefs. - */ -#define IRQ_NEPONSET_SMC9196 (IRQ_BOARD_START + 0) -#define IRQ_NEPONSET_USAR (IRQ_BOARD_START + 1) -#define IRQ_NEPONSET_SA1111 (IRQ_BOARD_START + 2) - -/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */ -#define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0) -#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1) -#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) -#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) - -/* H3800-specific IRQs (CONFIG_SA1100_H3800) */ -#define H3800_KPIO_IRQ_START (IRQ_BOARD_START) -#define IRQ_H3800_KEY (IRQ_BOARD_START + 0) -#define IRQ_H3800_SPI (IRQ_BOARD_START + 1) -#define IRQ_H3800_OWM (IRQ_BOARD_START + 2) -#define IRQ_H3800_ADC (IRQ_BOARD_START + 3) -#define IRQ_H3800_UART_0 (IRQ_BOARD_START + 4) -#define IRQ_H3800_UART_1 (IRQ_BOARD_START + 5) -#define IRQ_H3800_TIMER_0 (IRQ_BOARD_START + 6) -#define IRQ_H3800_TIMER_1 (IRQ_BOARD_START + 7) -#define IRQ_H3800_TIMER_2 (IRQ_BOARD_START + 8) -#define H3800_KPIO_IRQ_COUNT 9 - -#define H3800_GPIO_IRQ_START (IRQ_BOARD_START + 9) -#define IRQ_H3800_PEN (IRQ_BOARD_START + 9) -#define IRQ_H3800_SD_DETECT (IRQ_BOARD_START + 10) -#define IRQ_H3800_EAR_IN (IRQ_BOARD_START + 11) -#define IRQ_H3800_USB_DETECT (IRQ_BOARD_START + 12) -#define IRQ_H3800_SD_CON_SLT (IRQ_BOARD_START + 13) -#define H3800_GPIO_IRQ_COUNT 5 +#ifndef NR_IRQS +#define NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO) +#endif +#define SA1100_NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO) diff --git a/arch/arm/mach-sa1100/include/mach/lart.h b/arch/arm/mach-sa1100/include/mach/lart.h deleted file mode 100644 index 8a5482d908d..00000000000 --- a/arch/arm/mach-sa1100/include/mach/lart.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _INCLUDE_LART_H -#define _INCLUDE_LART_H - -#define LART_GPIO_ETH0 GPIO_GPIO0 -#define LART_IRQ_ETH0 IRQ_GPIO0 - -#define LART_GPIO_IDE GPIO_GPIO1 -#define LART_IRQ_IDE IRQ_GPIO1 - -#define LART_GPIO_UCB1200 GPIO_GPIO18 -#define LART_IRQ_UCB1200 IRQ_GPIO18 - -#endif diff --git a/arch/arm/mach-sa1100/include/mach/mcp.h b/arch/arm/mach-sa1100/include/mach/mcp.h deleted file mode 100644 index fb8b09a57ad..00000000000 --- a/arch/arm/mach-sa1100/include/mach/mcp.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/mach-sa1100/include/mach/mcp.h - * - * Copyright (C) 2005 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_ARM_ARCH_MCP_H -#define __ASM_ARM_ARCH_MCP_H - -#include <linux/types.h> - -struct mcp_plat_data { - u32 mccr0; - u32 mccr1; - unsigned int sclk_rate; -}; - -#endif diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h index e9f8eed900f..12d376795ab 100644 --- a/arch/arm/mach-sa1100/include/mach/memory.h +++ b/arch/arm/mach-sa1100/include/mach/memory.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-sa1100/include/mach/memory.h * - * Copyright (C) 1999-2000 Nicolas Pitre <nico@cam.org> + * Copyright (C) 1999-2000 Nicolas Pitre <nico@fluxnic.net> */ #ifndef __ASM_ARCH_MEMORY_H @@ -12,21 +12,7 @@ /* * Physical DRAM offset is 0xc0000000 on the SA1100 */ -#define PHYS_OFFSET UL(0xc0000000) - -#ifndef __ASSEMBLY__ - -#ifdef CONFIG_SA1111 -void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes); - -#define arch_adjust_zones(node, size, holes) \ - sa1111_adjust_zones(node, size, holes) - -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_1M) - -#endif -#endif +#define PLAT_PHYS_OFFSET UL(0xc0000000) /* * Because of the wide memory address space between physical RAM banks on the diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h new file mode 100644 index 00000000000..5ebd469a31f --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/nanoengine.h @@ -0,0 +1,52 @@ +/* + * arch/arm/mach-sa1100/include/mach/nanoengine.h + * + * This file contains the hardware specific definitions for nanoEngine. + * Only include this file from SA1100-specific files. + * + * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef __ASM_ARCH_NANOENGINE_H +#define __ASM_ARCH_NANOENGINE_H + +#include <mach/irqs.h> + +#define GPIO_PC_READY0 11 /* ready for socket 0 (active high)*/ +#define GPIO_PC_READY1 12 /* ready for socket 1 (active high) */ +#define GPIO_PC_CD0 13 /* detect for socket 0 (active low) */ +#define GPIO_PC_CD1 14 /* detect for socket 1 (active low) */ +#define GPIO_PC_RESET0 15 /* reset socket 0 */ +#define GPIO_PC_RESET1 16 /* reset socket 1 */ + +#define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0 +#define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11 +#define NANOENGINE_IRQ_GPIO_PC_READY1 IRQ_GPIO12 +#define NANOENGINE_IRQ_GPIO_PC_CD0 IRQ_GPIO13 +#define NANOENGINE_IRQ_GPIO_PC_CD1 IRQ_GPIO14 + +/* + * nanoEngine Memory Map: + * + * 0000.0000 - 003F.0000 - 4 MB Flash + * C000.0000 - C1FF.FFFF - 32 MB SDRAM + * 1860.0000 - 186F.FFFF - 1 MB Internal PCI Memory Read/Write + * 18A1.0000 - 18A1.FFFF - 64 KB Internal PCI Config Space + * 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode + * 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode + * + */ + +#define NANO_PCI_MEM_RW_PHYS 0x18600000 +#define NANO_PCI_MEM_RW_VIRT 0xf1000000 +#define NANO_PCI_MEM_RW_SIZE SZ_1M +#define NANO_PCI_CONFIG_SPACE_PHYS 0x18A10000 +#define NANO_PCI_CONFIG_SPACE_VIRT 0xf2000000 +#define NANO_PCI_CONFIG_SPACE_SIZE SZ_64K + +#endif + diff --git a/arch/arm/mach-sa1100/include/mach/neponset.h b/arch/arm/mach-sa1100/include/mach/neponset.h index d3f044f92c0..5516a52a329 100644 --- a/arch/arm/mach-sa1100/include/mach/neponset.h +++ b/arch/arm/mach-sa1100/include/mach/neponset.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-sa1100/include/mach/neponset.h * - * Created 2000/06/05 by Nicolas Pitre <nico@cam.org> + * Created 2000/06/05 by Nicolas Pitre <nico@fluxnic.net> * * This file contains the hardware specific definitions for Assabet * Only include this file from SA1100-specific files. @@ -15,54 +15,6 @@ /* * Neponset definitions: */ - -#define NEPONSET_CPLD_BASE (0x10000000) -#define Nep_p2v( x ) ((x) - NEPONSET_CPLD_BASE + 0xf3000000) -#define Nep_v2p( x ) ((x) - 0xf3000000 + NEPONSET_CPLD_BASE) - -#define _IRR 0x10000024 /* Interrupt Reason Register */ -#define _AUD_CTL 0x100000c0 /* Audio controls (RW) */ -#define _MDM_CTL_0 0x100000b0 /* Modem control 0 (RW) */ -#define _MDM_CTL_1 0x100000b4 /* Modem control 1 (RW) */ -#define _NCR_0 0x100000a0 /* Control Register (RW) */ -#define _KP_X_OUT 0x10000090 /* Keypad row write (RW) */ -#define _KP_Y_IN 0x10000080 /* Keypad column read (RO) */ -#define _SWPK 0x10000020 /* Switch pack (RO) */ -#define _WHOAMI 0x10000000 /* System ID Register (RO) */ - -#define _LEDS 0x10000010 /* LEDs [31:0] (WO) */ - -#define IRR (*((volatile u_char *) Nep_p2v(_IRR))) -#define AUD_CTL (*((volatile u_char *) Nep_p2v(_AUD_CTL))) -#define MDM_CTL_0 (*((volatile u_char *) Nep_p2v(_MDM_CTL_0))) -#define MDM_CTL_1 (*((volatile u_char *) Nep_p2v(_MDM_CTL_1))) -#define NCR_0 (*((volatile u_char *) Nep_p2v(_NCR_0))) -#define KP_X_OUT (*((volatile u_char *) Nep_p2v(_KP_X_OUT))) -#define KP_Y_IN (*((volatile u_char *) Nep_p2v(_KP_Y_IN))) -#define SWPK (*((volatile u_char *) Nep_p2v(_SWPK))) -#define WHOAMI (*((volatile u_char *) Nep_p2v(_WHOAMI))) - -#define LEDS (*((volatile Word *) Nep_p2v(_LEDS))) - -#define IRR_ETHERNET (1<<0) -#define IRR_USAR (1<<1) -#define IRR_SA1111 (1<<2) - -#define AUD_SEL_1341 (1<<0) -#define AUD_MUTE_1341 (1<<1) - -#define MDM_CTL0_RTS1 (1 << 0) -#define MDM_CTL0_DTR1 (1 << 1) -#define MDM_CTL0_RTS2 (1 << 2) -#define MDM_CTL0_DTR2 (1 << 3) - -#define MDM_CTL1_CTS1 (1 << 0) -#define MDM_CTL1_DSR1 (1 << 1) -#define MDM_CTL1_DCD1 (1 << 2) -#define MDM_CTL1_CTS2 (1 << 3) -#define MDM_CTL1_DSR2 (1 << 4) -#define MDM_CTL1_DCD2 (1 << 5) - #define NCR_GP01_OFF (1<<0) #define NCR_TP_PWR_EN (1<<1) #define NCR_MS_PWR_EN (1<<2) @@ -71,4 +23,8 @@ #define NCR_A0VPP (1<<5) #define NCR_A1VPP (1<<6) +void neponset_ncr_frob(unsigned int, unsigned int); +#define neponset_ncr_set(v) neponset_ncr_frob(0, v) +#define neponset_ncr_clear(v) neponset_ncr_frob(v, 0) + #endif diff --git a/arch/arm/mach-sa1100/include/mach/shannon.h b/arch/arm/mach-sa1100/include/mach/shannon.h index ec27d6e1214..fff39e02b49 100644 --- a/arch/arm/mach-sa1100/include/mach/shannon.h +++ b/arch/arm/mach-sa1100/include/mach/shannon.h @@ -21,16 +21,12 @@ #define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */ #define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */ #define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */ -#define SHANNON_GPIO_DISP_EN GPIO_GPIO (22) /* out */ +#define SHANNON_GPIO_DISP_EN 22 /* out */ /* XXX GPIO 23 unaccounted for */ -#define SHANNON_GPIO_EJECT_0 GPIO_GPIO (24) /* in */ -#define SHANNON_IRQ_GPIO_EJECT_0 IRQ_GPIO24 -#define SHANNON_GPIO_EJECT_1 GPIO_GPIO (25) /* in */ -#define SHANNON_IRQ_GPIO_EJECT_1 IRQ_GPIO25 -#define SHANNON_GPIO_RDY_0 GPIO_GPIO (26) /* in */ -#define SHANNON_IRQ_GPIO_RDY_0 IRQ_GPIO26 -#define SHANNON_GPIO_RDY_1 GPIO_GPIO (27) /* in */ -#define SHANNON_IRQ_GPIO_RDY_1 IRQ_GPIO27 +#define SHANNON_GPIO_EJECT_0 24 /* in */ +#define SHANNON_GPIO_EJECT_1 25 /* in */ +#define SHANNON_GPIO_RDY_0 26 /* in */ +#define SHANNON_GPIO_RDY_1 27 /* in */ /* MCP UCB codec GPIO pins... */ diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h index 9296c4513ce..ac2ea767215 100644 --- a/arch/arm/mach-sa1100/include/mach/simpad.h +++ b/arch/arm/mach-sa1100/include/mach/simpad.h @@ -39,41 +39,87 @@ /*--- PCMCIA ---*/ -#define GPIO_CF_CD GPIO_GPIO24 -#define GPIO_CF_IRQ GPIO_GPIO1 -#define IRQ_GPIO_CF_IRQ IRQ_GPIO1 -#define IRQ_GPIO_CF_CD IRQ_GPIO24 +#define GPIO_CF_CD 24 +#define GPIO_CF_IRQ 1 /*--- SmartCard ---*/ #define GPIO_SMART_CARD GPIO_GPIO10 #define IRQ_GPIO_SMARD_CARD IRQ_GPIO10 -// CS3 Latch is write only, a shadow is necessary - -#define CS3BUSTYPE unsigned volatile long -#define CS3_BASE 0xf1000000 - -#define VCC_5V_EN 0x0001 // For 5V PCMCIA -#define VCC_3V_EN 0x0002 // FOR 3.3V PCMCIA -#define EN1 0x0004 // This is only for EPROM's -#define EN0 0x0008 // Both should be enable for 3.3V or 5V -#define DISPLAY_ON 0x0010 -#define PCMCIA_BUFF_DIS 0x0020 -#define MQ_RESET 0x0040 -#define PCMCIA_RESET 0x0080 -#define DECT_POWER_ON 0x0100 -#define IRDA_SD 0x0200 // Shutdown for powersave -#define RS232_ON 0x0400 -#define SD_MEDIAQ 0x0800 // Shutdown for powersave -#define LED2_ON 0x1000 -#define IRDA_MODE 0x2000 // Fast/Slow IrDA mode -#define ENABLE_5V 0x4000 // Enable 5V circuit -#define RESET_SIMCARD 0x8000 - -#define RS232_ENABLE 0x0440 -#define PCMCIAMASK 0x402f - - +/*--- ucb1x00 GPIO ---*/ +#define SIMPAD_UCB1X00_GPIO_BASE (GPIO_MAX + 1) +#define SIMPAD_UCB1X00_GPIO_PROG1 (SIMPAD_UCB1X00_GPIO_BASE) +#define SIMPAD_UCB1X00_GPIO_PROG2 (SIMPAD_UCB1X00_GPIO_BASE + 1) +#define SIMPAD_UCB1X00_GPIO_UP (SIMPAD_UCB1X00_GPIO_BASE + 2) +#define SIMPAD_UCB1X00_GPIO_DOWN (SIMPAD_UCB1X00_GPIO_BASE + 3) +#define SIMPAD_UCB1X00_GPIO_LEFT (SIMPAD_UCB1X00_GPIO_BASE + 4) +#define SIMPAD_UCB1X00_GPIO_RIGHT (SIMPAD_UCB1X00_GPIO_BASE + 5) +#define SIMPAD_UCB1X00_GPIO_6 (SIMPAD_UCB1X00_GPIO_BASE + 6) +#define SIMPAD_UCB1X00_GPIO_7 (SIMPAD_UCB1X00_GPIO_BASE + 7) +#define SIMPAD_UCB1X00_GPIO_HEADSET (SIMPAD_UCB1X00_GPIO_BASE + 8) +#define SIMPAD_UCB1X00_GPIO_SPEAKER (SIMPAD_UCB1X00_GPIO_BASE + 9) + +/*--- CS3 Latch ---*/ +#define SIMPAD_CS3_GPIO_BASE (GPIO_MAX + 11) +#define SIMPAD_CS3_VCC_5V_EN (SIMPAD_CS3_GPIO_BASE) +#define SIMPAD_CS3_VCC_3V_EN (SIMPAD_CS3_GPIO_BASE + 1) +#define SIMPAD_CS3_EN1 (SIMPAD_CS3_GPIO_BASE + 2) +#define SIMPAD_CS3_EN0 (SIMPAD_CS3_GPIO_BASE + 3) +#define SIMPAD_CS3_DISPLAY_ON (SIMPAD_CS3_GPIO_BASE + 4) +#define SIMPAD_CS3_PCMCIA_BUFF_DIS (SIMPAD_CS3_GPIO_BASE + 5) +#define SIMPAD_CS3_MQ_RESET (SIMPAD_CS3_GPIO_BASE + 6) +#define SIMPAD_CS3_PCMCIA_RESET (SIMPAD_CS3_GPIO_BASE + 7) +#define SIMPAD_CS3_DECT_POWER_ON (SIMPAD_CS3_GPIO_BASE + 8) +#define SIMPAD_CS3_IRDA_SD (SIMPAD_CS3_GPIO_BASE + 9) +#define SIMPAD_CS3_RS232_ON (SIMPAD_CS3_GPIO_BASE + 10) +#define SIMPAD_CS3_SD_MEDIAQ (SIMPAD_CS3_GPIO_BASE + 11) +#define SIMPAD_CS3_LED2_ON (SIMPAD_CS3_GPIO_BASE + 12) +#define SIMPAD_CS3_IRDA_MODE (SIMPAD_CS3_GPIO_BASE + 13) +#define SIMPAD_CS3_ENABLE_5V (SIMPAD_CS3_GPIO_BASE + 14) +#define SIMPAD_CS3_RESET_SIMCARD (SIMPAD_CS3_GPIO_BASE + 15) + +#define SIMPAD_CS3_PCMCIA_BVD1 (SIMPAD_CS3_GPIO_BASE + 16) +#define SIMPAD_CS3_PCMCIA_BVD2 (SIMPAD_CS3_GPIO_BASE + 17) +#define SIMPAD_CS3_PCMCIA_VS1 (SIMPAD_CS3_GPIO_BASE + 18) +#define SIMPAD_CS3_PCMCIA_VS2 (SIMPAD_CS3_GPIO_BASE + 19) +#define SIMPAD_CS3_LOCK_IND (SIMPAD_CS3_GPIO_BASE + 20) +#define SIMPAD_CS3_CHARGING_STATE (SIMPAD_CS3_GPIO_BASE + 21) +#define SIMPAD_CS3_PCMCIA_SHORT (SIMPAD_CS3_GPIO_BASE + 22) +#define SIMPAD_CS3_GPIO_23 (SIMPAD_CS3_GPIO_BASE + 23) + +#define CS3_BASE IOMEM(0xf1000000) + +long simpad_get_cs3_ro(void); +long simpad_get_cs3_shadow(void); +void simpad_set_cs3_bit(int value); +void simpad_clear_cs3_bit(int value); + +#define VCC_5V_EN 0x0001 /* For 5V PCMCIA */ +#define VCC_3V_EN 0x0002 /* FOR 3.3V PCMCIA */ +#define EN1 0x0004 /* This is only for EPROM's */ +#define EN0 0x0008 /* Both should be enable for 3.3V or 5V */ +#define DISPLAY_ON 0x0010 +#define PCMCIA_BUFF_DIS 0x0020 +#define MQ_RESET 0x0040 +#define PCMCIA_RESET 0x0080 +#define DECT_POWER_ON 0x0100 +#define IRDA_SD 0x0200 /* Shutdown for powersave */ +#define RS232_ON 0x0400 +#define SD_MEDIAQ 0x0800 /* Shutdown for powersave */ +#define LED2_ON 0x1000 +#define IRDA_MODE 0x2000 /* Fast/Slow IrDA mode */ +#define ENABLE_5V 0x4000 /* Enable 5V circuit */ +#define RESET_SIMCARD 0x8000 + +#define PCMCIA_BVD1 0x01 +#define PCMCIA_BVD2 0x02 +#define PCMCIA_VS1 0x04 +#define PCMCIA_VS2 0x08 +#define LOCK_IND 0x10 +#define CHARGING_STATE 0x20 +#define PCMCIA_SHORT 0x40 + +/*--- Battery ---*/ struct simpad_battery { unsigned char ac_status; /* line connected yes/no */ unsigned char status; /* battery loading yes/no */ diff --git a/arch/arm/mach-sa1100/include/mach/system.h b/arch/arm/mach-sa1100/include/mach/system.h deleted file mode 100644 index 63755ca5b1b..00000000000 --- a/arch/arm/mach-sa1100/include/mach/system.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * arch/arm/mach-sa1100/include/mach/system.h - * - * Copyright (c) 1999 Nicolas Pitre <nico@cam.org> - */ -#include <mach/hardware.h> - -static inline void arch_idle(void) -{ - cpu_do_idle(); -} - -static inline void arch_reset(char mode) -{ - if (mode == 's') { - /* Jump into ROM at address 0 */ - cpu_reset(0); - } else { - /* Use on-chip reset capability */ - RSRR = RSRR_SWR; - } -} diff --git a/arch/arm/mach-sa1100/include/mach/timex.h b/arch/arm/mach-sa1100/include/mach/timex.h deleted file mode 100644 index 7a5d017b58b..00000000000 --- a/arch/arm/mach-sa1100/include/mach/timex.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * arch/arm/mach-sa1100/include/mach/timex.h - * - * SA1100 architecture timex specifications - * - * Copyright (C) 1998 - */ - -/* - * SA1100 timer - */ -#define CLOCK_TICK_RATE 3686400 diff --git a/arch/arm/mach-sa1100/include/mach/uncompress.h b/arch/arm/mach-sa1100/include/mach/uncompress.h index 714160b03d7..73093dc8982 100644 --- a/arch/arm/mach-sa1100/include/mach/uncompress.h +++ b/arch/arm/mach-sa1100/include/mach/uncompress.h @@ -1,13 +1,15 @@ /* * arch/arm/mach-sa1100/include/mach/uncompress.h * - * (C) 1999 Nicolas Pitre <nico@cam.org> + * (C) 1999 Nicolas Pitre <nico@fluxnic.net> * * Reorganised to be machine independent. */ #include "hardware.h" +#define IOMEM(x) (x) + /* * The following code assumes the serial port has already been * initialized by the bootloader. We search for the first enabled @@ -47,4 +49,3 @@ static inline void flush(void) * Nothing to do for these */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-sa1100/include/mach/vmalloc.h b/arch/arm/mach-sa1100/include/mach/vmalloc.h deleted file mode 100644 index ec8fdc5a360..00000000000 --- a/arch/arm/mach-sa1100/include/mach/vmalloc.h +++ /dev/null @@ -1,4 +0,0 @@ -/* - * arch/arm/mach-sa1100/include/mach/vmalloc.h - */ -#define VMALLOC_END (0xe8000000) diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index 3093d46a9c6..2124f1fc2fb 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c @@ -12,11 +12,13 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/interrupt.h> +#include <linux/io.h> #include <linux/irq.h> #include <linux/ioport.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <mach/hardware.h> +#include <mach/irqs.h> #include <asm/mach/irq.h> #include "generic.h" @@ -37,14 +39,14 @@ static int GPIO_IRQ_mask = (1 << 11) - 1; #define GPIO_11_27_IRQ(i) ((i) - 21) #define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq)) -static int sa1100_gpio_type(unsigned int irq, unsigned int type) +static int sa1100_gpio_type(struct irq_data *d, unsigned int type) { unsigned int mask; - if (irq <= 10) - mask = 1 << irq; + if (d->irq <= 10) + mask = 1 << d->irq; else - mask = GPIO11_27_MASK(irq); + mask = GPIO11_27_MASK(d->irq); if (type == IRQ_TYPE_PROBE) { if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) @@ -70,37 +72,37 @@ static int sa1100_gpio_type(unsigned int irq, unsigned int type) /* * GPIO IRQs must be acknowledged. This is for IRQs from 0 to 10. */ -static void sa1100_low_gpio_ack(unsigned int irq) +static void sa1100_low_gpio_ack(struct irq_data *d) { - GEDR = (1 << irq); + GEDR = (1 << d->irq); } -static void sa1100_low_gpio_mask(unsigned int irq) +static void sa1100_low_gpio_mask(struct irq_data *d) { - ICMR &= ~(1 << irq); + ICMR &= ~(1 << d->irq); } -static void sa1100_low_gpio_unmask(unsigned int irq) +static void sa1100_low_gpio_unmask(struct irq_data *d) { - ICMR |= 1 << irq; + ICMR |= 1 << d->irq; } -static int sa1100_low_gpio_wake(unsigned int irq, unsigned int on) +static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on) { if (on) - PWER |= 1 << irq; + PWER |= 1 << d->irq; else - PWER &= ~(1 << irq); + PWER &= ~(1 << d->irq); return 0; } static struct irq_chip sa1100_low_gpio_chip = { .name = "GPIO-l", - .ack = sa1100_low_gpio_ack, - .mask = sa1100_low_gpio_mask, - .unmask = sa1100_low_gpio_unmask, - .set_type = sa1100_gpio_type, - .set_wake = sa1100_low_gpio_wake, + .irq_ack = sa1100_low_gpio_ack, + .irq_mask = sa1100_low_gpio_mask, + .irq_unmask = sa1100_low_gpio_unmask, + .irq_set_type = sa1100_gpio_type, + .irq_set_wake = sa1100_low_gpio_wake, }; /* @@ -139,16 +141,16 @@ sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc) * In addition, the IRQs are all collected up into one bit in the * interrupt controller registers. */ -static void sa1100_high_gpio_ack(unsigned int irq) +static void sa1100_high_gpio_ack(struct irq_data *d) { - unsigned int mask = GPIO11_27_MASK(irq); + unsigned int mask = GPIO11_27_MASK(d->irq); GEDR = mask; } -static void sa1100_high_gpio_mask(unsigned int irq) +static void sa1100_high_gpio_mask(struct irq_data *d) { - unsigned int mask = GPIO11_27_MASK(irq); + unsigned int mask = GPIO11_27_MASK(d->irq); GPIO_IRQ_mask &= ~mask; @@ -156,9 +158,9 @@ static void sa1100_high_gpio_mask(unsigned int irq) GFER &= ~mask; } -static void sa1100_high_gpio_unmask(unsigned int irq) +static void sa1100_high_gpio_unmask(struct irq_data *d) { - unsigned int mask = GPIO11_27_MASK(irq); + unsigned int mask = GPIO11_27_MASK(d->irq); GPIO_IRQ_mask |= mask; @@ -166,44 +168,44 @@ static void sa1100_high_gpio_unmask(unsigned int irq) GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; } -static int sa1100_high_gpio_wake(unsigned int irq, unsigned int on) +static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on) { if (on) - PWER |= GPIO11_27_MASK(irq); + PWER |= GPIO11_27_MASK(d->irq); else - PWER &= ~GPIO11_27_MASK(irq); + PWER &= ~GPIO11_27_MASK(d->irq); return 0; } static struct irq_chip sa1100_high_gpio_chip = { .name = "GPIO-h", - .ack = sa1100_high_gpio_ack, - .mask = sa1100_high_gpio_mask, - .unmask = sa1100_high_gpio_unmask, - .set_type = sa1100_gpio_type, - .set_wake = sa1100_high_gpio_wake, + .irq_ack = sa1100_high_gpio_ack, + .irq_mask = sa1100_high_gpio_mask, + .irq_unmask = sa1100_high_gpio_unmask, + .irq_set_type = sa1100_gpio_type, + .irq_set_wake = sa1100_high_gpio_wake, }; /* * We don't need to ACK IRQs on the SA1100 unless they're GPIOs * this is for internal IRQs i.e. from 11 to 31. */ -static void sa1100_mask_irq(unsigned int irq) +static void sa1100_mask_irq(struct irq_data *d) { - ICMR &= ~(1 << irq); + ICMR &= ~(1 << d->irq); } -static void sa1100_unmask_irq(unsigned int irq) +static void sa1100_unmask_irq(struct irq_data *d) { - ICMR |= (1 << irq); + ICMR |= (1 << d->irq); } /* * Apart form GPIOs, only the RTC alarm can be a wakeup event. */ -static int sa1100_set_wake(unsigned int irq, unsigned int on) +static int sa1100_set_wake(struct irq_data *d, unsigned int on) { - if (irq == IRQ_RTCAlrm) { + if (d->irq == IRQ_RTCAlrm) { if (on) PWER |= PWER_RTC; else @@ -215,17 +217,14 @@ static int sa1100_set_wake(unsigned int irq, unsigned int on) static struct irq_chip sa1100_normal_chip = { .name = "SC", - .ack = sa1100_mask_irq, - .mask = sa1100_mask_irq, - .unmask = sa1100_unmask_irq, - .set_wake = sa1100_set_wake, + .irq_ack = sa1100_mask_irq, + .irq_mask = sa1100_mask_irq, + .irq_unmask = sa1100_unmask_irq, + .irq_set_wake = sa1100_set_wake, }; -static struct resource irq_resource = { - .name = "irqs", - .start = 0x90050000, - .end = 0x9005ffff, -}; +static struct resource irq_resource = + DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs"); static struct sa1100irq_state { unsigned int saved; @@ -234,7 +233,7 @@ static struct sa1100irq_state { unsigned int iccr; } sa1100irq_state; -static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state) +static int sa1100irq_suspend(void) { struct sa1100irq_state *st = &sa1100irq_state; @@ -264,7 +263,7 @@ static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int sa1100irq_resume(struct sys_device *dev) +static void sa1100irq_resume(void) { struct sa1100irq_state *st = &sa1100irq_state; @@ -277,24 +276,17 @@ static int sa1100irq_resume(struct sys_device *dev) ICMR = st->icmr; } - return 0; } -static struct sysdev_class sa1100irq_sysclass = { - .name = "sa11x0-irq", +static struct syscore_ops sa1100irq_syscore_ops = { .suspend = sa1100irq_suspend, .resume = sa1100irq_resume, }; -static struct sys_device sa1100irq_device = { - .id = 0, - .cls = &sa1100irq_sysclass, -}; - static int __init sa1100irq_init_devicefs(void) { - sysdev_class_register(&sa1100irq_sysclass); - return sysdev_register(&sa1100irq_device); + register_syscore_ops(&sa1100irq_syscore_ops); + return 0; } device_initcall(sa1100irq_init_devicefs); @@ -323,28 +315,28 @@ void __init sa1100_init_irq(void) ICCR = 1; for (irq = 0; irq <= 10; irq++) { - set_irq_chip(irq, &sa1100_low_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } for (irq = 12; irq <= 31; irq++) { - set_irq_chip(irq, &sa1100_normal_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &sa1100_normal_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } for (irq = 32; irq <= 48; irq++) { - set_irq_chip(irq, &sa1100_high_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* * Install handler for GPIO 11-27 edge detect interrupts */ - set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip); - set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); + irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip); + irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); sa1100_init_gpio(); } diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c index 81848aa9642..c0b1f5bafae 100644 --- a/arch/arm/mach-sa1100/jornada720.c +++ b/arch/arm/mach-sa1100/jornada720.c @@ -17,21 +17,23 @@ #include <linux/kernel.h> #include <linux/tty.h> #include <linux/delay.h> +#include <linux/platform_data/sa11x0-serial.h> #include <linux/platform_device.h> #include <linux/ioport.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <video/s1d13xxxfb.h> -#include <mach/hardware.h> #include <asm/hardware/sa1111.h> -#include <asm/irq.h> +#include <asm/page.h> #include <asm/mach-types.h> #include <asm/setup.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> #include <asm/mach/map.h> -#include <asm/mach/serial_sa1100.h> + +#include <mach/hardware.h> +#include <mach/irqs.h> #include "generic.h" @@ -45,7 +47,7 @@ /* memory space (line 52 of HP's doc) */ #define SA1111REGSTART 0x40000000 -#define SA1111REGLEN 0x00001fff +#define SA1111REGLEN 0x00002000 #define EPSONREGSTART 0x48000000 #define EPSONREGLEN 0x00100000 #define EPSONFBSTART 0x48200000 @@ -173,16 +175,8 @@ static struct s1d13xxxfb_pdata s1d13xxxfb_data = { }; static struct resource s1d13xxxfb_resources[] = { - [0] = { - .start = EPSONFBSTART, - .end = EPSONFBSTART + EPSONFBLEN, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = EPSONREGSTART, - .end = EPSONREGSTART + EPSONREGLEN, - .flags = IORESOURCE_MEM, - } + [0] = DEFINE_RES_MEM(EPSONFBSTART, EPSONFBLEN), + [1] = DEFINE_RES_MEM(EPSONREGSTART, EPSONREGLEN), }; static struct platform_device s1d13xxxfb_device = { @@ -196,16 +190,12 @@ static struct platform_device s1d13xxxfb_device = { }; static struct resource sa1111_resources[] = { - [0] = { - .start = SA1111REGSTART, - .end = SA1111REGSTART + SA1111REGLEN, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_GPIO1, - .end = IRQ_GPIO1, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(SA1111REGSTART, SA1111REGLEN), + [1] = DEFINE_RES_IRQ(IRQ_GPIO1), +}; + +static struct sa1111_platform_data sa1111_info = { + .disable_devs = SA1111_DEVID_PS2_MSE, }; static u64 sa1111_dmamask = 0xffffffffUL; @@ -216,6 +206,7 @@ static struct platform_device sa1111_device = { .dev = { .dma_mask = &sa1111_dmamask, .coherent_dma_mask = 0xffffffff, + .platform_data = &sa1111_info, }, .num_resources = ARRAY_SIZE(sa1111_resources), .resource = sa1111_resources, @@ -226,12 +217,22 @@ static struct platform_device jornada_ssp_device = { .id = -1, }; +static struct platform_device jornada_kbd_device = { + .name = "jornada720_kbd", + .id = -1, +}; + +static struct platform_device jornada_ts_device = { + .name = "jornada_ts", + .id = -1, +}; + static struct platform_device *devices[] __initdata = { &sa1111_device, -#ifdef CONFIG_SA1100_JORNADA720_SSP &jornada_ssp_device, -#endif &s1d13xxxfb_device, + &jornada_kbd_device, + &jornada_ts_device, }; static int __init jornada720_init(void) @@ -268,11 +269,6 @@ static struct map_desc jornada720_io_desc[] __initdata = { .pfn = __phys_to_pfn(EPSONFBSTART), .length = EPSONFBLEN, .type = MT_DEVICE - }, { /* SA-1111 */ - .virtual = 0xf4000000, - .pfn = __phys_to_pfn(SA1111REGSTART), - .length = SA1111REGLEN, - .type = MT_DEVICE } }; @@ -336,24 +332,25 @@ static struct flash_platform_data jornada720_flash_data = { .nr_parts = ARRAY_SIZE(jornada720_partitions), }; -static struct resource jornada720_flash_resource = { - .start = SA1100_CS0_PHYS, - .end = SA1100_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource jornada720_flash_resource = + DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); static void __init jornada720_mach_init(void) { - sa11x0_set_flash_data(&jornada720_flash_data, &jornada720_flash_resource, 1); + sa11x0_register_mtd(&jornada720_flash_data, &jornada720_flash_resource, 1); } MACHINE_START(JORNADA720, "HP Jornada 720") /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */ - .phys_io = 0x80000000, - .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc, - .boot_params = 0xc0000100, + .atag_offset = 0x100, .map_io = jornada720_map_io, + .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = jornada720_mach_init, + .init_late = sa11x0_init_late, +#ifdef CONFIG_SA1111 + .dma_zone_size = SZ_1M, +#endif + .restart = sa11x0_restart, MACHINE_END diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c index 28cf3696797..b143c465934 100644 --- a/arch/arm/mach-sa1100/jornada720_ssp.c +++ b/arch/arm/mach-sa1100/jornada720_ssp.c @@ -18,7 +18,7 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/sched.h> -#include <linux/slab.h> +#include <linux/io.h> #include <mach/hardware.h> #include <mach/jornada720.h> @@ -30,7 +30,7 @@ static unsigned long jornada_ssp_flags; /** * jornada_ssp_reverse - reverses input byte * - * we need to reverse all data we recieve from the mcu due to its physical location + * we need to reverse all data we receive from the mcu due to its physical location * returns : 01110111 -> 11101110 */ u8 inline jornada_ssp_reverse(u8 byte) @@ -54,7 +54,7 @@ EXPORT_SYMBOL(jornada_ssp_reverse); * timeout after <timeout> rounds. Needs mcu running before its called. * * returns : %mcu output on success - * : %-ETIMEOUT on timeout + * : %-ETIMEDOUT on timeout */ int jornada_ssp_byte(u8 byte) { @@ -82,7 +82,7 @@ EXPORT_SYMBOL(jornada_ssp_byte); * jornada_ssp_inout - decide if input is command or trading byte * * returns : (jornada_ssp_byte(byte)) on success - * : %-ETIMEOUT on timeout failure + * : %-ETIMEDOUT on timeout failure */ int jornada_ssp_inout(u8 byte) { @@ -130,7 +130,7 @@ void jornada_ssp_end(void) }; EXPORT_SYMBOL(jornada_ssp_end); -static int __init jornada_ssp_probe(struct platform_device *dev) +static int jornada_ssp_probe(struct platform_device *dev) { int ret; @@ -180,7 +180,7 @@ static int __init jornada_ssp_probe(struct platform_device *dev) static int jornada_ssp_remove(struct platform_device *dev) { - /* Note that this doesnt actually remove the driver, since theres nothing to remove + /* Note that this doesn't actually remove the driver, since theres nothing to remove * It just makes sure everything is turned off */ GPSR = GPIO_GPIO25; ssp_exit(); @@ -199,3 +199,5 @@ static int __init jornada_ssp_init(void) { return platform_driver_register(&jornadassp_driver); } + +module_init(jornada_ssp_init); diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c index 0cd52692d2f..51b0eb52c01 100644 --- a/arch/arm/mach-sa1100/lart.c +++ b/arch/arm/mach-sa1100/lart.c @@ -4,30 +4,112 @@ #include <linux/init.h> #include <linux/kernel.h> +#include <linux/platform_data/sa11x0-serial.h> #include <linux/tty.h> +#include <linux/gpio.h> +#include <linux/leds.h> +#include <linux/platform_device.h> + +#include <video/sa1100fb.h> #include <mach/hardware.h> #include <asm/setup.h> #include <asm/mach-types.h> +#include <asm/page.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <asm/mach/serial_sa1100.h> -#include <mach/mcp.h> +#include <linux/platform_data/mfd-mcp-sa11x0.h> +#include <mach/irqs.h> #include "generic.h" - -#warning "include/asm/arch-sa1100/ide.h needs fixing for lart" - static struct mcp_plat_data lart_mcp_data = { .mccr0 = MCCR0_ADM, .sclk_rate = 11981000, }; +#ifdef LART_GREY_LCD +static struct sa1100fb_mach_info lart_grey_info = { + .pixclock = 150000, .bpp = 4, + .xres = 320, .yres = 240, + + .hsync_len = 1, .vsync_len = 1, + .left_margin = 4, .upper_margin = 0, + .right_margin = 2, .lower_margin = 0, + + .cmap_greyscale = 1, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + + .lccr0 = LCCR0_Mono | LCCR0_Sngl | LCCR0_Pas | LCCR0_4PixMono, + .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512), +}; +#endif +#ifdef LART_COLOR_LCD +static struct sa1100fb_mach_info lart_color_info = { + .pixclock = 150000, .bpp = 16, + .xres = 320, .yres = 240, + + .hsync_len = 2, .vsync_len = 3, + .left_margin = 69, .upper_margin = 14, + .right_margin = 8, .lower_margin = 4, + + .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act, + .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512), +}; +#endif +#ifdef LART_VIDEO_OUT +static struct sa1100fb_mach_info lart_video_info = { + .pixclock = 39721, .bpp = 16, + .xres = 640, .yres = 480, + + .hsync_len = 95, .vsync_len = 2, + .left_margin = 40, .upper_margin = 32, + .right_margin = 24, .lower_margin = 11, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + + .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act, + .lccr3 = LCCR3_OutEnL | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512), +}; +#endif + +#ifdef LART_KIT01_LCD +static struct sa1100fb_mach_info lart_kit01_info = { + .pixclock = 63291, .bpp = 16, + .xres = 640, .yres = 480, + + .hsync_len = 64, .vsync_len = 3, + .left_margin = 122, .upper_margin = 45, + .right_margin = 10, .lower_margin = 10, + + .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act, + .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg +}; +#endif + static void __init lart_init(void) { - sa11x0_set_mcp_data(&lart_mcp_data); + struct sa1100fb_mach_info *inf = NULL; + +#ifdef LART_GREY_LCD + inf = &lart_grey_info; +#endif +#ifdef LART_COLOR_LCD + inf = &lart_color_info; +#endif +#ifdef LART_VIDEO_OUT + inf = &lart_video_info; +#endif +#ifdef LART_KIT01_LCD + inf = &lart_kit01_info; +#endif + + if (inf) + sa11x0_register_lcd(inf); + + sa11x0_ppc_configure_mcp(); + sa11x0_register_mcp(&lart_mcp_data); } static struct map_desc lart_io_desc[] __initdata = { @@ -44,6 +126,27 @@ static struct map_desc lart_io_desc[] __initdata = { } }; +/* LEDs */ +struct gpio_led lart_gpio_leds[] = { + { + .name = "lart:red", + .default_trigger = "cpu0", + .gpio = 23, + }, +}; + +static struct gpio_led_platform_data lart_gpio_led_info = { + .leds = lart_gpio_leds, + .num_leds = ARRAY_SIZE(lart_gpio_leds), +}; + +static struct platform_device lart_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &lart_gpio_led_info, + } +}; static void __init lart_map_io(void) { sa1100_map_io(); @@ -57,14 +160,17 @@ static void __init lart_map_io(void) GPDR |= GPIO_UART_TXD; GPDR &= ~GPIO_UART_RXD; PPAR |= PPAR_UPR; + + platform_device_register(&lart_leds); } MACHINE_START(LART, "LART") - .phys_io = 0x80000000, - .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc, - .boot_params = 0xc0000100, + .atag_offset = 0x100, .map_io = lart_map_io, + .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, .init_machine = lart_init, - .timer = &sa1100_timer, + .init_late = sa11x0_init_late, + .init_time = sa1100_timer_init, + .restart = sa11x0_restart, MACHINE_END diff --git a/arch/arm/mach-sa1100/leds-assabet.c b/arch/arm/mach-sa1100/leds-assabet.c deleted file mode 100644 index 64e9b4b11b5..00000000000 --- a/arch/arm/mach-sa1100/leds-assabet.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * linux/arch/arm/mach-sa1100/leds-assabet.c - * - * Copyright (C) 2000 John Dorsey <john+@cs.cmu.edu> - * - * Original (leds-footbridge.c) by Russell King - * - * Assabet uses the LEDs as follows: - * - Green - toggles state every 50 timer interrupts - * - Red - on if system is not idle - */ -#include <linux/init.h> - -#include <mach/hardware.h> -#include <asm/leds.h> -#include <asm/system.h> -#include <mach/assabet.h> - -#include "leds.h" - - -#define LED_STATE_ENABLED 1 -#define LED_STATE_CLAIMED 2 - -static unsigned int led_state; -static unsigned int hw_led_state; - -#define ASSABET_BCR_LED_MASK (ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED) - -void assabet_leds_event(led_event_t evt) -{ - unsigned long flags; - - local_irq_save(flags); - - switch (evt) { - case led_start: - hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN; - led_state = LED_STATE_ENABLED; - break; - - case led_stop: - led_state &= ~LED_STATE_ENABLED; - hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN; - ASSABET_BCR_frob(ASSABET_BCR_LED_MASK, hw_led_state); - break; - - case led_claim: - led_state |= LED_STATE_CLAIMED; - hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN; - break; - - case led_release: - led_state &= ~LED_STATE_CLAIMED; - hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN; - break; - -#ifdef CONFIG_LEDS_TIMER - case led_timer: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state ^= ASSABET_BCR_LED_GREEN; - break; -#endif - -#ifdef CONFIG_LEDS_CPU - case led_idle_start: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state |= ASSABET_BCR_LED_RED; - break; - - case led_idle_end: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state &= ~ASSABET_BCR_LED_RED; - break; -#endif - - case led_halted: - break; - - case led_green_on: - if (led_state & LED_STATE_CLAIMED) - hw_led_state &= ~ASSABET_BCR_LED_GREEN; - break; - - case led_green_off: - if (led_state & LED_STATE_CLAIMED) - hw_led_state |= ASSABET_BCR_LED_GREEN; - break; - - case led_amber_on: - break; - - case led_amber_off: - break; - - case led_red_on: - if (led_state & LED_STATE_CLAIMED) - hw_led_state &= ~ASSABET_BCR_LED_RED; - break; - - case led_red_off: - if (led_state & LED_STATE_CLAIMED) - hw_led_state |= ASSABET_BCR_LED_RED; - break; - - default: - break; - } - - if (led_state & LED_STATE_ENABLED) - ASSABET_BCR_frob(ASSABET_BCR_LED_MASK, hw_led_state); - - local_irq_restore(flags); -} diff --git a/arch/arm/mach-sa1100/leds-badge4.c b/arch/arm/mach-sa1100/leds-badge4.c deleted file mode 100644 index cf1e38458b8..00000000000 --- a/arch/arm/mach-sa1100/leds-badge4.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * linux/arch/arm/mach-sa1100/leds-badge4.c - * - * Author: Christopher Hoover <ch@hpl.hp.com> - * Copyright (C) 2002 Hewlett-Packard Company - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/init.h> - -#include <mach/hardware.h> -#include <asm/leds.h> -#include <asm/system.h> - -#include "leds.h" - -#define LED_STATE_ENABLED 1 -#define LED_STATE_CLAIMED 2 - -static unsigned int led_state; -static unsigned int hw_led_state; - -#define LED_RED GPIO_GPIO(7) -#define LED_GREEN GPIO_GPIO(9) -#define LED_MASK (LED_RED|LED_GREEN) - -#define LED_IDLE LED_GREEN -#define LED_TIMER LED_RED - -void badge4_leds_event(led_event_t evt) -{ - unsigned long flags; - - local_irq_save(flags); - - switch (evt) { - case led_start: - GPDR |= LED_MASK; - hw_led_state = LED_MASK; - led_state = LED_STATE_ENABLED; - break; - - case led_stop: - led_state &= ~LED_STATE_ENABLED; - break; - - case led_claim: - led_state |= LED_STATE_CLAIMED; - hw_led_state = LED_MASK; - break; - - case led_release: - led_state &= ~LED_STATE_CLAIMED; - hw_led_state = LED_MASK; - break; - -#ifdef CONFIG_LEDS_TIMER - case led_timer: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state ^= LED_TIMER; - break; -#endif - -#ifdef CONFIG_LEDS_CPU - case led_idle_start: - /* LED off when system is idle */ - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state &= ~LED_IDLE; - break; - - case led_idle_end: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state |= LED_IDLE; - break; -#endif - - case led_red_on: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state &= ~LED_RED; - break; - - case led_red_off: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state |= LED_RED; - break; - - case led_green_on: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state &= ~LED_GREEN; - break; - - case led_green_off: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state |= LED_GREEN; - break; - - default: - break; - } - - if (led_state & LED_STATE_ENABLED) { - GPSR = hw_led_state; - GPCR = hw_led_state ^ LED_MASK; - } - - local_irq_restore(flags); -} diff --git a/arch/arm/mach-sa1100/leds-cerf.c b/arch/arm/mach-sa1100/leds-cerf.c deleted file mode 100644 index 259b48e0be8..00000000000 --- a/arch/arm/mach-sa1100/leds-cerf.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * linux/arch/arm/mach-sa1100/leds-cerf.c - * - * Author: ??? - */ -#include <linux/init.h> - -#include <mach/hardware.h> -#include <asm/leds.h> -#include <asm/system.h> - -#include "leds.h" - - -#define LED_STATE_ENABLED 1 -#define LED_STATE_CLAIMED 2 - -static unsigned int led_state; -static unsigned int hw_led_state; - -#define LED_D0 GPIO_GPIO(0) -#define LED_D1 GPIO_GPIO(1) -#define LED_D2 GPIO_GPIO(2) -#define LED_D3 GPIO_GPIO(3) -#define LED_MASK (LED_D0|LED_D1|LED_D2|LED_D3) - -void cerf_leds_event(led_event_t evt) -{ - unsigned long flags; - - local_irq_save(flags); - - switch (evt) { - case led_start: - hw_led_state = LED_MASK; - led_state = LED_STATE_ENABLED; - break; - - case led_stop: - led_state &= ~LED_STATE_ENABLED; - break; - - case led_claim: - led_state |= LED_STATE_CLAIMED; - hw_led_state = LED_MASK; - break; - case led_release: - led_state &= ~LED_STATE_CLAIMED; - hw_led_state = LED_MASK; - break; - -#ifdef CONFIG_LEDS_TIMER - case led_timer: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state ^= LED_D0; - break; -#endif - -#ifdef CONFIG_LEDS_CPU - case led_idle_start: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state &= ~LED_D1; - break; - - case led_idle_end: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state |= LED_D1; - break; -#endif - case led_green_on: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state &= ~LED_D2; - break; - - case led_green_off: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state |= LED_D2; - break; - - case led_amber_on: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state &= ~LED_D3; - break; - - case led_amber_off: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state |= LED_D3; - break; - - case led_red_on: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state &= ~LED_D1; - break; - - case led_red_off: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state |= LED_D1; - break; - - default: - break; - } - - if (led_state & LED_STATE_ENABLED) { - GPSR = hw_led_state; - GPCR = hw_led_state ^ LED_MASK; - } - - local_irq_restore(flags); -} diff --git a/arch/arm/mach-sa1100/leds-hackkit.c b/arch/arm/mach-sa1100/leds-hackkit.c deleted file mode 100644 index 2bce137462e..00000000000 --- a/arch/arm/mach-sa1100/leds-hackkit.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * linux/arch/arm/mach-sa1100/leds-hackkit.c - * - * based on leds-lart.c - * - * (C) Erik Mouw (J.A.K.Mouw@its.tudelft.nl), April 21, 2000 - * (C) Stefan Eletzhofer <stefan.eletzhofer@eletztrick.de>, 2002 - * - * The HackKit has two leds (GPIO 22/23). The red led (gpio 22) is used - * as cpu led, the green one is used as timer led. - */ -#include <linux/init.h> - -#include <mach/hardware.h> -#include <asm/leds.h> -#include <asm/system.h> - -#include "leds.h" - - -#define LED_STATE_ENABLED 1 -#define LED_STATE_CLAIMED 2 - -static unsigned int led_state; -static unsigned int hw_led_state; - -#define LED_GREEN GPIO_GPIO23 -#define LED_RED GPIO_GPIO22 -#define LED_MASK (LED_RED | LED_GREEN) - -void hackkit_leds_event(led_event_t evt) -{ - unsigned long flags; - - local_irq_save(flags); - - switch(evt) { - case led_start: - /* pin 22/23 are outputs */ - GPDR |= LED_MASK; - hw_led_state = LED_MASK; - led_state = LED_STATE_ENABLED; - break; - - case led_stop: - led_state &= ~LED_STATE_ENABLED; - break; - - case led_claim: - led_state |= LED_STATE_CLAIMED; - hw_led_state = LED_MASK; - break; - - case led_release: - led_state &= ~LED_STATE_CLAIMED; - hw_led_state = LED_MASK; - break; - -#ifdef CONFIG_LEDS_TIMER - case led_timer: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state ^= LED_GREEN; - break; -#endif - -#ifdef CONFIG_LEDS_CPU - case led_idle_start: - /* The LART people like the LED to be off when the - system is idle... */ - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state &= ~LED_RED; - break; - - case led_idle_end: - /* ... and on if the system is not idle */ - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state |= LED_RED; - break; -#endif - - case led_red_on: - if (led_state & LED_STATE_CLAIMED) - hw_led_state &= ~LED_RED; - break; - - case led_red_off: - if (led_state & LED_STATE_CLAIMED) - hw_led_state |= LED_RED; - break; - - case led_green_on: - if (led_state & LED_STATE_CLAIMED) - hw_led_state &= ~LED_GREEN; - break; - - case led_green_off: - if (led_state & LED_STATE_CLAIMED) - hw_led_state |= LED_GREEN; - break; - - default: - break; - } - - /* Now set the GPIO state, or nothing will happen at all */ - if (led_state & LED_STATE_ENABLED) { - GPSR = hw_led_state; - GPCR = hw_led_state ^ LED_MASK; - } - - local_irq_restore(flags); -} diff --git a/arch/arm/mach-sa1100/leds-lart.c b/arch/arm/mach-sa1100/leds-lart.c deleted file mode 100644 index 0505a1fdcdb..00000000000 --- a/arch/arm/mach-sa1100/leds-lart.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * linux/arch/arm/mach-sa1100/leds-lart.c - * - * (C) Erik Mouw (J.A.K.Mouw@its.tudelft.nl), April 21, 2000 - * - * LART uses the LED as follows: - * - GPIO23 is the LED, on if system is not idle - * You can use both CONFIG_LEDS_CPU and CONFIG_LEDS_TIMER at the same - * time, but in that case the timer events will still dictate the - * pace of the LED. - */ -#include <linux/init.h> - -#include <mach/hardware.h> -#include <asm/leds.h> -#include <asm/system.h> - -#include "leds.h" - - -#define LED_STATE_ENABLED 1 -#define LED_STATE_CLAIMED 2 - -static unsigned int led_state; -static unsigned int hw_led_state; - -#define LED_23 GPIO_GPIO23 -#define LED_MASK (LED_23) - -void lart_leds_event(led_event_t evt) -{ - unsigned long flags; - - local_irq_save(flags); - - switch(evt) { - case led_start: - /* pin 23 is output pin */ - GPDR |= LED_23; - hw_led_state = LED_MASK; - led_state = LED_STATE_ENABLED; - break; - - case led_stop: - led_state &= ~LED_STATE_ENABLED; - break; - - case led_claim: - led_state |= LED_STATE_CLAIMED; - hw_led_state = LED_MASK; - break; - - case led_release: - led_state &= ~LED_STATE_CLAIMED; - hw_led_state = LED_MASK; - break; - -#ifdef CONFIG_LEDS_TIMER - case led_timer: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state ^= LED_23; - break; -#endif - -#ifdef CONFIG_LEDS_CPU - case led_idle_start: - /* The LART people like the LED to be off when the - system is idle... */ - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state &= ~LED_23; - break; - - case led_idle_end: - /* ... and on if the system is not idle */ - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state |= LED_23; - break; -#endif - - case led_red_on: - if (led_state & LED_STATE_CLAIMED) - hw_led_state &= ~LED_23; - break; - - case led_red_off: - if (led_state & LED_STATE_CLAIMED) - hw_led_state |= LED_23; - break; - - default: - break; - } - - /* Now set the GPIO state, or nothing will happen at all */ - if (led_state & LED_STATE_ENABLED) { - GPSR = hw_led_state; - GPCR = hw_led_state ^ LED_MASK; - } - - local_irq_restore(flags); -} diff --git a/arch/arm/mach-sa1100/leds-simpad.c b/arch/arm/mach-sa1100/leds-simpad.c deleted file mode 100644 index d50f4eeaa12..00000000000 --- a/arch/arm/mach-sa1100/leds-simpad.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * linux/arch/arm/mach-sa1100/leds-simpad.c - * - * Author: Juergen Messerer <juergen.messerer@siemens.ch> - */ -#include <linux/init.h> - -#include <mach/hardware.h> -#include <asm/leds.h> -#include <asm/system.h> -#include <mach/simpad.h> - -#include "leds.h" - - -#define LED_STATE_ENABLED 1 -#define LED_STATE_CLAIMED 2 - -static unsigned int led_state; -static unsigned int hw_led_state; - -#define LED_GREEN (1) -#define LED_MASK (1) - -extern void set_cs3_bit(int value); -extern void clear_cs3_bit(int value); - -void simpad_leds_event(led_event_t evt) -{ - switch (evt) - { - case led_start: - hw_led_state = LED_GREEN; - led_state = LED_STATE_ENABLED; - break; - - case led_stop: - led_state &= ~LED_STATE_ENABLED; - break; - - case led_claim: - led_state |= LED_STATE_CLAIMED; - hw_led_state = LED_GREEN; - break; - - case led_release: - led_state &= ~LED_STATE_CLAIMED; - hw_led_state = LED_GREEN; - break; - -#ifdef CONFIG_LEDS_TIMER - case led_timer: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state ^= LED_GREEN; - break; -#endif - -#ifdef CONFIG_LEDS_CPU - case led_idle_start: - break; - - case led_idle_end: - break; -#endif - - case led_halted: - break; - - case led_green_on: - if (led_state & LED_STATE_CLAIMED) - hw_led_state |= LED_GREEN; - break; - - case led_green_off: - if (led_state & LED_STATE_CLAIMED) - hw_led_state &= ~LED_GREEN; - break; - - case led_amber_on: - break; - - case led_amber_off: - break; - - case led_red_on: - break; - - case led_red_off: - break; - - default: - break; - } - - if (led_state & LED_STATE_ENABLED) - set_cs3_bit(LED2_ON); - else - clear_cs3_bit(LED2_ON); -} - diff --git a/arch/arm/mach-sa1100/leds.c b/arch/arm/mach-sa1100/leds.c deleted file mode 100644 index 4cf7c565aae..00000000000 --- a/arch/arm/mach-sa1100/leds.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * linux/arch/arm/mach-sa1100/leds.c - * - * SA1100 LEDs dispatcher - * - * Copyright (C) 2001 Nicolas Pitre - */ -#include <linux/compiler.h> -#include <linux/init.h> - -#include <asm/leds.h> -#include <asm/mach-types.h> - -#include "leds.h" - -static int __init -sa1100_leds_init(void) -{ - if (machine_is_assabet()) - leds_event = assabet_leds_event; - if (machine_is_consus()) - leds_event = consus_leds_event; - if (machine_is_badge4()) - leds_event = badge4_leds_event; - if (machine_is_brutus()) - leds_event = brutus_leds_event; - if (machine_is_cerf()) - leds_event = cerf_leds_event; - if (machine_is_flexanet()) - leds_event = flexanet_leds_event; - if (machine_is_graphicsclient()) - leds_event = graphicsclient_leds_event; - if (machine_is_hackkit()) - leds_event = hackkit_leds_event; - if (machine_is_lart()) - leds_event = lart_leds_event; - if (machine_is_pfs168()) - leds_event = pfs168_leds_event; - if (machine_is_graphicsmaster()) - leds_event = graphicsmaster_leds_event; - if (machine_is_adsbitsy()) - leds_event = adsbitsy_leds_event; - if (machine_is_pt_system3()) - leds_event = system3_leds_event; - if (machine_is_simpad()) - leds_event = simpad_leds_event; /* what about machine registry? including led, apm... -zecke */ - - leds_event(led_start); - return 0; -} - -core_initcall(sa1100_leds_init); diff --git a/arch/arm/mach-sa1100/leds.h b/arch/arm/mach-sa1100/leds.h deleted file mode 100644 index 68cc9f773d6..00000000000 --- a/arch/arm/mach-sa1100/leds.h +++ /dev/null @@ -1,14 +0,0 @@ -extern void assabet_leds_event(led_event_t evt); -extern void badge4_leds_event(led_event_t evt); -extern void consus_leds_event(led_event_t evt); -extern void brutus_leds_event(led_event_t evt); -extern void cerf_leds_event(led_event_t evt); -extern void flexanet_leds_event(led_event_t evt); -extern void graphicsclient_leds_event(led_event_t evt); -extern void hackkit_leds_event(led_event_t evt); -extern void lart_leds_event(led_event_t evt); -extern void pfs168_leds_event(led_event_t evt); -extern void graphicsmaster_leds_event(led_event_t evt); -extern void adsbitsy_leds_event(led_event_t evt); -extern void system3_leds_event(led_event_t evt); -extern void simpad_leds_event(led_event_t evt); diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c new file mode 100644 index 00000000000..f1cb3784d52 --- /dev/null +++ b/arch/arm/mach-sa1100/nanoengine.c @@ -0,0 +1,117 @@ +/* + * linux/arch/arm/mach-sa1100/nanoengine.c + * + * Bright Star Engineering's nanoEngine board init code. + * + * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/platform_data/sa11x0-serial.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/root_dev.h> + +#include <asm/mach-types.h> +#include <asm/setup.h> +#include <asm/page.h> + +#include <asm/mach/arch.h> +#include <asm/mach/flash.h> +#include <asm/mach/map.h> + +#include <mach/hardware.h> +#include <mach/nanoengine.h> +#include <mach/irqs.h> + +#include "generic.h" + +/* Flash bank 0 */ +static struct mtd_partition nanoengine_partitions[] = { + { + .name = "nanoEngine boot firmware and parameter table", + .size = 0x00010000, /* 32K */ + .offset = 0, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel/initrd reserved", + .size = 0x002f0000, + .offset = 0x00010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "experimental filesystem allocation", + .size = 0x00100000, + .offset = 0x00300000, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct flash_platform_data nanoengine_flash_data = { + .map_name = "jedec_probe", + .parts = nanoengine_partitions, + .nr_parts = ARRAY_SIZE(nanoengine_partitions), +}; + +static struct resource nanoengine_flash_resources[] = { + DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M), + DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M), +}; + +static struct map_desc nanoengine_io_desc[] __initdata = { + { + /* System Registers */ + .virtual = 0xf0000000, + .pfn = __phys_to_pfn(0x10000000), + .length = 0x00100000, + .type = MT_DEVICE + }, { + /* Internal PCI Memory Read/Write */ + .virtual = NANO_PCI_MEM_RW_VIRT, + .pfn = __phys_to_pfn(NANO_PCI_MEM_RW_PHYS), + .length = NANO_PCI_MEM_RW_SIZE, + .type = MT_DEVICE + }, { + /* Internal PCI Config Space */ + .virtual = NANO_PCI_CONFIG_SPACE_VIRT, + .pfn = __phys_to_pfn(NANO_PCI_CONFIG_SPACE_PHYS), + .length = NANO_PCI_CONFIG_SPACE_SIZE, + .type = MT_DEVICE + } +}; + +static void __init nanoengine_map_io(void) +{ + sa1100_map_io(); + iotable_init(nanoengine_io_desc, ARRAY_SIZE(nanoengine_io_desc)); + + sa1100_register_uart(0, 1); + sa1100_register_uart(1, 2); + sa1100_register_uart(2, 3); + Ser1SDCR0 |= SDCR0_UART; + /* disable IRDA -- UART2 is used as a normal serial port */ + Ser2UTCR4 = 0; + Ser2HSCR0 = 0; +} + +static void __init nanoengine_init(void) +{ + sa11x0_register_mtd(&nanoengine_flash_data, nanoengine_flash_resources, + ARRAY_SIZE(nanoengine_flash_resources)); +} + +MACHINE_START(NANOENGINE, "BSE nanoEngine") + .atag_offset = 0x100, + .map_io = nanoengine_map_io, + .nr_irqs = SA1100_NR_IRQS, + .init_irq = sa1100_init_irq, + .init_time = sa1100_timer_init, + .init_machine = nanoengine_init, + .init_late = sa11x0_init_late, + .restart = sa11x0_restart, +MACHINE_END diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 6ccd175bc4c..400f8033204 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c @@ -1,90 +1,105 @@ /* * linux/arch/arm/mach-sa1100/neponset.c - * */ -#include <linux/kernel.h> +#include <linux/err.h> #include <linux/init.h> -#include <linux/tty.h> #include <linux/ioport.h> -#include <linux/serial_core.h> +#include <linux/irq.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/platform_data/sa11x0-serial.h> #include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/serial_core.h> #include <linux/slab.h> -#include <mach/hardware.h> #include <asm/mach-types.h> -#include <asm/irq.h> #include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/serial_sa1100.h> -#include <mach/assabet.h> -#include <mach/neponset.h> #include <asm/hardware/sa1111.h> #include <asm/sizes.h> -/* - * Install handler for Neponset IRQ. Note that we have to loop here - * since the ETHERNET and USAR IRQs are level based, and we need to - * ensure that the IRQ signal is deasserted before returning. This - * is rather unfortunate. - */ -static void -neponset_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - unsigned int irr; - - while (1) { - /* - * Acknowledge the parent IRQ. - */ - desc->chip->ack(irq); - - /* - * Read the interrupt reason register. Let's have all - * active IRQ bits high. Note: there is a typo in the - * Neponset user's guide for the SA1111 IRR level. - */ - irr = IRR ^ (IRR_ETHERNET | IRR_USAR); - - if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0) - break; - - /* - * Since there is no individual mask, we have to - * mask the parent IRQ. This is safe, since we'll - * recheck the register for any pending IRQs. - */ - if (irr & (IRR_ETHERNET | IRR_USAR)) { - desc->chip->mask(irq); - - /* - * Ack the interrupt now to prevent re-entering - * this neponset handler. Again, this is safe - * since we'll check the IRR register prior to - * leaving. - */ - desc->chip->ack(irq); +#include <mach/hardware.h> +#include <mach/assabet.h> +#include <mach/neponset.h> +#include <mach/irqs.h> + +#define NEP_IRQ_SMC91X 0 +#define NEP_IRQ_USAR 1 +#define NEP_IRQ_SA1111 2 +#define NEP_IRQ_NR 3 + +#define WHOAMI 0x00 +#define LEDS 0x10 +#define SWPK 0x20 +#define IRR 0x24 +#define KP_Y_IN 0x80 +#define KP_X_OUT 0x90 +#define NCR_0 0xa0 +#define MDM_CTL_0 0xb0 +#define MDM_CTL_1 0xb4 +#define AUD_CTL 0xc0 + +#define IRR_ETHERNET (1 << 0) +#define IRR_USAR (1 << 1) +#define IRR_SA1111 (1 << 2) + +#define MDM_CTL0_RTS1 (1 << 0) +#define MDM_CTL0_DTR1 (1 << 1) +#define MDM_CTL0_RTS2 (1 << 2) +#define MDM_CTL0_DTR2 (1 << 3) + +#define MDM_CTL1_CTS1 (1 << 0) +#define MDM_CTL1_DSR1 (1 << 1) +#define MDM_CTL1_DCD1 (1 << 2) +#define MDM_CTL1_CTS2 (1 << 3) +#define MDM_CTL1_DSR2 (1 << 4) +#define MDM_CTL1_DCD2 (1 << 5) + +#define AUD_SEL_1341 (1 << 0) +#define AUD_MUTE_1341 (1 << 1) - if (irr & IRR_ETHERNET) { - generic_handle_irq(IRQ_NEPONSET_SMC9196); - } +extern void sa1110_mb_disable(void); - if (irr & IRR_USAR) { - generic_handle_irq(IRQ_NEPONSET_USAR); - } +struct neponset_drvdata { + void __iomem *base; + struct platform_device *sa1111; + struct platform_device *smc91x; + unsigned irq_base; +#ifdef CONFIG_PM_SLEEP + u32 ncr0; + u32 mdm_ctl_0; +#endif +}; - desc->chip->unmask(irq); - } +static void __iomem *nep_base; - if (irr & IRR_SA1111) { - generic_handle_irq(IRQ_NEPONSET_SA1111); - } +void neponset_ncr_frob(unsigned int mask, unsigned int val) +{ + void __iomem *base = nep_base; + + if (base) { + unsigned long flags; + unsigned v; + + local_irq_save(flags); + v = readb_relaxed(base + NCR_0); + writeb_relaxed((v & ~mask) | val, base + NCR_0); + local_irq_restore(flags); + } else { + WARN(1, "nep_base unset\n"); } } +EXPORT_SYMBOL(neponset_ncr_frob); static void neponset_set_mctrl(struct uart_port *port, u_int mctrl) { - u_int mdm_ctl0 = MDM_CTL_0; + void __iomem *base = nep_base; + u_int mdm_ctl0; + if (!base) + return; + + mdm_ctl0 = readb_relaxed(base + MDM_CTL_0); if (port->mapbase == _Ser1UTCR0) { if (mctrl & TIOCM_RTS) mdm_ctl0 &= ~MDM_CTL0_RTS2; @@ -107,14 +122,19 @@ static void neponset_set_mctrl(struct uart_port *port, u_int mctrl) mdm_ctl0 |= MDM_CTL0_DTR1; } - MDM_CTL_0 = mdm_ctl0; + writeb_relaxed(mdm_ctl0, base + MDM_CTL_0); } static u_int neponset_get_mctrl(struct uart_port *port) { + void __iomem *base = nep_base; u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; - u_int mdm_ctl1 = MDM_CTL_1; + u_int mdm_ctl1; + + if (!base) + return ret; + mdm_ctl1 = readb_relaxed(base + MDM_CTL_1); if (port->mapbase == _Ser1UTCR0) { if (mdm_ctl1 & MDM_CTL1_DCD2) ret &= ~TIOCM_CD; @@ -134,209 +154,283 @@ static u_int neponset_get_mctrl(struct uart_port *port) return ret; } -static struct sa1100_port_fns neponset_port_fns __devinitdata = { +static struct sa1100_port_fns neponset_port_fns = { .set_mctrl = neponset_set_mctrl, .get_mctrl = neponset_get_mctrl, }; -static int __devinit neponset_probe(struct platform_device *dev) +/* + * Install handler for Neponset IRQ. Note that we have to loop here + * since the ETHERNET and USAR IRQs are level based, and we need to + * ensure that the IRQ signal is deasserted before returning. This + * is rather unfortunate. + */ +static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc) { - sa1100_register_uart_fns(&neponset_port_fns); + struct neponset_drvdata *d = irq_desc_get_handler_data(desc); + unsigned int irr; - /* - * Install handler for GPIO25. - */ - set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING); - set_irq_chained_handler(IRQ_GPIO25, neponset_irq_handler); + while (1) { + /* + * Acknowledge the parent IRQ. + */ + desc->irq_data.chip->irq_ack(&desc->irq_data); - /* - * We would set IRQ_GPIO25 to be a wake-up IRQ, but - * unfortunately something on the Neponset activates - * this IRQ on sleep (ethernet?) - */ -#if 0 - enable_irq_wake(IRQ_GPIO25); -#endif + /* + * Read the interrupt reason register. Let's have all + * active IRQ bits high. Note: there is a typo in the + * Neponset user's guide for the SA1111 IRR level. + */ + irr = readb_relaxed(d->base + IRR); + irr ^= IRR_ETHERNET | IRR_USAR; - /* - * Setup other Neponset IRQs. SA1111 will be done by the - * generic SA1111 code. - */ - set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq); - set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE); - set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq); - set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE); + if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0) + break; - /* - * Disable GPIO 0/1 drivers so the buttons work on the module. - */ - NCR_0 = NCR_GP01_OFF; + /* + * Since there is no individual mask, we have to + * mask the parent IRQ. This is safe, since we'll + * recheck the register for any pending IRQs. + */ + if (irr & (IRR_ETHERNET | IRR_USAR)) { + desc->irq_data.chip->irq_mask(&desc->irq_data); - return 0; -} + /* + * Ack the interrupt now to prevent re-entering + * this neponset handler. Again, this is safe + * since we'll check the IRR register prior to + * leaving. + */ + desc->irq_data.chip->irq_ack(&desc->irq_data); -#ifdef CONFIG_PM + if (irr & IRR_ETHERNET) + generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X); -/* - * LDM power management. - */ -static unsigned int neponset_saved_state; + if (irr & IRR_USAR) + generic_handle_irq(d->irq_base + NEP_IRQ_USAR); -static int neponset_suspend(struct platform_device *dev, pm_message_t state) -{ - /* - * Save state. - */ - neponset_saved_state = NCR_0; + desc->irq_data.chip->irq_unmask(&desc->irq_data); + } - return 0; + if (irr & IRR_SA1111) + generic_handle_irq(d->irq_base + NEP_IRQ_SA1111); + } } -static int neponset_resume(struct platform_device *dev) +/* Yes, we really do not have any kind of masking or unmasking */ +static void nochip_noop(struct irq_data *irq) { - NCR_0 = neponset_saved_state; - - return 0; } -#else -#define neponset_suspend NULL -#define neponset_resume NULL -#endif - -static struct platform_driver neponset_device_driver = { - .probe = neponset_probe, - .suspend = neponset_suspend, - .resume = neponset_resume, - .driver = { - .name = "neponset", - }, +static struct irq_chip nochip = { + .name = "neponset", + .irq_ack = nochip_noop, + .irq_mask = nochip_noop, + .irq_unmask = nochip_noop, }; -static struct resource neponset_resources[] = { - [0] = { - .start = 0x10000000, - .end = 0x17ffffff, - .flags = IORESOURCE_MEM, - }, +static struct sa1111_platform_data sa1111_info = { + .disable_devs = SA1111_DEVID_PS2_MSE, }; -static struct platform_device neponset_device = { - .name = "neponset", - .id = 0, - .num_resources = ARRAY_SIZE(neponset_resources), - .resource = neponset_resources, -}; +static int neponset_probe(struct platform_device *dev) +{ + struct neponset_drvdata *d; + struct resource *nep_res, *sa1111_res, *smc91x_res; + struct resource sa1111_resources[] = { + DEFINE_RES_MEM(0x40000000, SZ_8K), + { .flags = IORESOURCE_IRQ }, + }; + struct platform_device_info sa1111_devinfo = { + .parent = &dev->dev, + .name = "sa1111", + .id = 0, + .res = sa1111_resources, + .num_res = ARRAY_SIZE(sa1111_resources), + .data = &sa1111_info, + .size_data = sizeof(sa1111_info), + .dma_mask = 0xffffffffUL, + }; + struct resource smc91x_resources[] = { + DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS, + 0x02000000, "smc91x-regs"), + DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000, + 0x02000000, "smc91x-attrib"), + { .flags = IORESOURCE_IRQ }, + }; + struct platform_device_info smc91x_devinfo = { + .parent = &dev->dev, + .name = "smc91x", + .id = 0, + .res = smc91x_resources, + .num_res = ARRAY_SIZE(smc91x_resources), + }; + int ret, irq; + + if (nep_base) + return -EBUSY; + + irq = ret = platform_get_irq(dev, 0); + if (ret < 0) + goto err_alloc; + + nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0); + smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1); + sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2); + if (!nep_res || !smc91x_res || !sa1111_res) { + ret = -ENXIO; + goto err_alloc; + } -static struct resource sa1111_resources[] = { - [0] = { - .start = 0x40000000, - .end = 0x40001fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_NEPONSET_SA1111, - .end = IRQ_NEPONSET_SA1111, - .flags = IORESOURCE_IRQ, - }, -}; + d = kzalloc(sizeof(*d), GFP_KERNEL); + if (!d) { + ret = -ENOMEM; + goto err_alloc; + } -static u64 sa1111_dmamask = 0xffffffffUL; + d->base = ioremap(nep_res->start, SZ_4K); + if (!d->base) { + ret = -ENOMEM; + goto err_ioremap; + } -static struct platform_device sa1111_device = { - .name = "sa1111", - .id = 0, - .dev = { - .dma_mask = &sa1111_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(sa1111_resources), - .resource = sa1111_resources, -}; + if (readb_relaxed(d->base + WHOAMI) != 0x11) { + dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n", + readb_relaxed(d->base + WHOAMI)); + ret = -ENODEV; + goto err_id; + } -static struct resource smc91x_resources[] = { - [0] = { - .name = "smc91x-regs", - .start = SA1100_CS3_PHYS, - .end = SA1100_CS3_PHYS + 0x01ffffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_NEPONSET_SMC9196, - .end = IRQ_NEPONSET_SMC9196, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .name = "smc91x-attrib", - .start = SA1100_CS3_PHYS + 0x02000000, - .end = SA1100_CS3_PHYS + 0x03ffffff, - .flags = IORESOURCE_MEM, - }, -}; + ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1); + if (ret <= 0) { + dev_err(&dev->dev, "unable to allocate %u irqs: %d\n", + NEP_IRQ_NR, ret); + if (ret == 0) + ret = -ENOMEM; + goto err_irq_alloc; + } -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; + d->irq_base = ret; -static struct platform_device *devices[] __initdata = { - &neponset_device, - &sa1111_device, - &smc91x_device, -}; + irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip, + handle_simple_irq); + set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID | IRQF_PROBE); + irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip, + handle_simple_irq); + set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID | IRQF_PROBE); + irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip); -extern void sa1110_mb_disable(void); - -static int __init neponset_init(void) -{ - platform_driver_register(&neponset_device_driver); + irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); + irq_set_handler_data(irq, d); + irq_set_chained_handler(irq, neponset_irq_handler); /* - * The Neponset is only present on the Assabet machine type. + * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately + * something on the Neponset activates this IRQ on sleep (eth?) */ - if (!machine_is_assabet()) - return -ENODEV; +#if 0 + enable_irq_wake(irq); +#endif - /* - * Ensure that the memory bus request/grant signals are setup, - * and the grant is held in its inactive state, whether or not - * we actually have a Neponset attached. - */ + dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n", + d->irq_base, d->irq_base + NEP_IRQ_NR - 1); + nep_base = d->base; + + sa1100_register_uart_fns(&neponset_port_fns); + + /* Ensure that the memory bus request/grant signals are setup */ sa1110_mb_disable(); - if (!machine_has_neponset()) { - printk(KERN_DEBUG "Neponset expansion board not present\n"); - return -ENODEV; - } + /* Disable GPIO 0/1 drivers so the buttons work on the Assabet */ + writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0); - if (WHOAMI != 0x11) { - printk(KERN_WARNING "Neponset board detected, but " - "wrong ID: %02x\n", WHOAMI); - return -ENODEV; - } + sa1111_resources[0].parent = sa1111_res; + sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111; + sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111; + d->sa1111 = platform_device_register_full(&sa1111_devinfo); + + smc91x_resources[0].parent = smc91x_res; + smc91x_resources[1].parent = smc91x_res; + smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X; + smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X; + d->smc91x = platform_device_register_full(&smc91x_devinfo); + + platform_set_drvdata(dev, d); - return platform_add_devices(devices, ARRAY_SIZE(devices)); + return 0; + + err_irq_alloc: + err_id: + iounmap(d->base); + err_ioremap: + kfree(d); + err_alloc: + return ret; } -subsys_initcall(neponset_init); +static int neponset_remove(struct platform_device *dev) +{ + struct neponset_drvdata *d = platform_get_drvdata(dev); + int irq = platform_get_irq(dev, 0); + + if (!IS_ERR(d->sa1111)) + platform_device_unregister(d->sa1111); + if (!IS_ERR(d->smc91x)) + platform_device_unregister(d->smc91x); + irq_set_chained_handler(irq, NULL); + irq_free_descs(d->irq_base, NEP_IRQ_NR); + nep_base = NULL; + iounmap(d->base); + kfree(d); -static struct map_desc neponset_io_desc[] __initdata = { - { /* System Registers */ - .virtual = 0xf3000000, - .pfn = __phys_to_pfn(0x10000000), - .length = SZ_1M, - .type = MT_DEVICE - }, { /* SA-1111 */ - .virtual = 0xf4000000, - .pfn = __phys_to_pfn(0x40000000), - .length = SZ_1M, - .type = MT_DEVICE - } + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int neponset_suspend(struct device *dev) +{ + struct neponset_drvdata *d = dev_get_drvdata(dev); + + d->ncr0 = readb_relaxed(d->base + NCR_0); + d->mdm_ctl_0 = readb_relaxed(d->base + MDM_CTL_0); + + return 0; +} + +static int neponset_resume(struct device *dev) +{ + struct neponset_drvdata *d = dev_get_drvdata(dev); + + writeb_relaxed(d->ncr0, d->base + NCR_0); + writeb_relaxed(d->mdm_ctl_0, d->base + MDM_CTL_0); + + return 0; +} + +static const struct dev_pm_ops neponset_pm_ops = { + .suspend_noirq = neponset_suspend, + .resume_noirq = neponset_resume, + .freeze_noirq = neponset_suspend, + .restore_noirq = neponset_resume, +}; +#define PM_OPS &neponset_pm_ops +#else +#define PM_OPS NULL +#endif + +static struct platform_driver neponset_device_driver = { + .probe = neponset_probe, + .remove = neponset_remove, + .driver = { + .name = "neponset", + .owner = THIS_MODULE, + .pm = PM_OPS, + }, }; -void __init neponset_map_io(void) +static int __init neponset_init(void) { - iotable_init(neponset_io_desc, ARRAY_SIZE(neponset_io_desc)); + return platform_driver_register(&neponset_device_driver); } + +subsys_initcall(neponset_init); diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c new file mode 100644 index 00000000000..ff02e2da99f --- /dev/null +++ b/arch/arm/mach-sa1100/pci-nanoengine.c @@ -0,0 +1,282 @@ +/* + * linux/arch/arm/mach-sa1100/pci-nanoengine.c + * + * PCI functions for BSE nanoEngine PCI + * + * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/kernel.h> +#include <linux/irq.h> +#include <linux/pci.h> +#include <linux/spinlock.h> + +#include <asm/mach/pci.h> +#include <asm/mach-types.h> + +#include <mach/nanoengine.h> +#include <mach/hardware.h> + +static DEFINE_SPINLOCK(nano_lock); + +static int nanoengine_get_pci_address(struct pci_bus *bus, + unsigned int devfn, int where, unsigned long *address) +{ + int ret = PCIBIOS_DEVICE_NOT_FOUND; + unsigned int busnr = bus->number; + + *address = NANO_PCI_CONFIG_SPACE_VIRT + + ((bus->number << 16) | (devfn << 8) | (where & ~3)); + + ret = (busnr > 255 || devfn > 255 || where > 255) ? + PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; + + return ret; +} + +static int nanoengine_read_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 *val) +{ + int ret; + unsigned long address; + unsigned long flags; + u32 v; + + /* nanoEngine PCI bridge does not return -1 for a non-existing + * device. We must fake the answer. We know that the only valid + * device is device zero at bus 0, which is the network chip. */ + if (bus->number != 0 || (devfn >> 3) != 0) { + v = -1; + nanoengine_get_pci_address(bus, devfn, where, &address); + goto exit_function; + } + + spin_lock_irqsave(&nano_lock, flags); + + ret = nanoengine_get_pci_address(bus, devfn, where, &address); + if (ret != PCIBIOS_SUCCESSFUL) + return ret; + v = __raw_readl(address); + + spin_unlock_irqrestore(&nano_lock, flags); + + v >>= ((where & 3) * 8); + v &= (unsigned long)(-1) >> ((4 - size) * 8); + +exit_function: + *val = v; + return PCIBIOS_SUCCESSFUL; +} + +static int nanoengine_write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 val) +{ + int ret; + unsigned long address; + unsigned long flags; + unsigned shift; + u32 v; + + shift = (where & 3) * 8; + + spin_lock_irqsave(&nano_lock, flags); + + ret = nanoengine_get_pci_address(bus, devfn, where, &address); + if (ret != PCIBIOS_SUCCESSFUL) + return ret; + v = __raw_readl(address); + switch (size) { + case 1: + v &= ~(0xFF << shift); + v |= val << shift; + break; + case 2: + v &= ~(0xFFFF << shift); + v |= val << shift; + break; + case 4: + v = val; + break; + } + __raw_writel(v, address); + + spin_unlock_irqrestore(&nano_lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops pci_nano_ops = { + .read = nanoengine_read_config, + .write = nanoengine_write_config, +}; + +static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot, + u8 pin) +{ + return NANOENGINE_IRQ_GPIO_PCI; +} + +static struct resource pci_io_ports = + DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO"); + +static struct resource pci_non_prefetchable_memory = { + .name = "PCI non-prefetchable", + .start = NANO_PCI_MEM_RW_PHYS, + /* nanoEngine documentation says there is a 1 Megabyte window here, + * but PCI reports just 128 + 8 kbytes. */ + .end = NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1, +/* .end = NANO_PCI_MEM_RW_PHYS + SZ_128K + SZ_8K - 1,*/ + .flags = IORESOURCE_MEM, +}; + +/* + * nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it + * overlaps with previously defined memory. + * + * Here is what happens: + * +# dmesg +... +pci 0000:00:00.0: [8086:1209] type 0 class 0x000200 +pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff] +pci 0000:00:00.0: reg 14: [io 0x0000-0x003f] +pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff] +pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref] +pci 0000:00:00.0: supports D1 D2 +pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot +pci 0000:00:00.0: PME# disabled +PCI: bus0: Fast back to back transfers enabled +pci 0000:00:00.0: BAR 6: can't assign mem pref (size 0x100000) +pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff] +pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff]) +pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff] +pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff]) +pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f] +pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f]) + * + * On the other hand, if we do not request the prefetchable memory resource, + * linux will alloc it first and the two non-prefetchable memory areas that + * are our real interest will not be mapped. So we choose to map it to an + * unused area. It gets recognized as expansion ROM, but becomes disabled. + * + * Here is what happens then: + * +# dmesg +... +pci 0000:00:00.0: [8086:1209] type 0 class 0x000200 +pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff] +pci 0000:00:00.0: reg 14: [io 0x0000-0x003f] +pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff] +pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref] +pci 0000:00:00.0: supports D1 D2 +pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot +pci 0000:00:00.0: PME# disabled +PCI: bus0: Fast back to back transfers enabled +pci 0000:00:00.0: BAR 6: assigned [mem 0x78000000-0x780fffff pref] +pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff] +pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff]) +pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff] +pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff]) +pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f] +pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f]) + +# lspci -vv -s 0000:00:00.0 +00:00.0 Class 0200: Device 8086:1209 (rev 09) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR+ <PERR+ INTx- + Latency: 0 (2000ns min, 14000ns max), Cache Line Size: 32 bytes + Interrupt: pin A routed to IRQ 0 + Region 0: Memory at 18620000 (32-bit, non-prefetchable) [size=4K] + Region 1: I/O ports at 0400 [size=64] + Region 2: [virtual] Memory at 18600000 (32-bit, non-prefetchable) [size=128K] + [virtual] Expansion ROM at 78000000 [disabled] [size=1M] + Capabilities: [dc] Power Management version 2 + Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME- + Kernel driver in use: e100 + Kernel modules: e100 + * + */ +static struct resource pci_prefetchable_memory = { + .name = "PCI prefetchable", + .start = 0x78000000, + .end = 0x78000000 + NANO_PCI_MEM_RW_SIZE - 1, + .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, +}; + +static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys) +{ + if (request_resource(&ioport_resource, &pci_io_ports)) { + printk(KERN_ERR "PCI: unable to allocate io port region\n"); + return -EBUSY; + } + if (request_resource(&iomem_resource, &pci_non_prefetchable_memory)) { + release_resource(&pci_io_ports); + printk(KERN_ERR "PCI: unable to allocate non prefetchable\n"); + return -EBUSY; + } + if (request_resource(&iomem_resource, &pci_prefetchable_memory)) { + release_resource(&pci_io_ports); + release_resource(&pci_non_prefetchable_memory); + printk(KERN_ERR "PCI: unable to allocate prefetchable\n"); + return -EBUSY; + } + pci_add_resource_offset(&sys->resources, &pci_io_ports, sys->io_offset); + pci_add_resource_offset(&sys->resources, + &pci_non_prefetchable_memory, sys->mem_offset); + pci_add_resource_offset(&sys->resources, + &pci_prefetchable_memory, sys->mem_offset); + + return 1; +} + +int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys) +{ + int ret = 0; + + pcibios_min_io = 0; + pcibios_min_mem = 0; + + if (nr == 0) { + sys->mem_offset = NANO_PCI_MEM_RW_PHYS; + sys->io_offset = 0x400; + ret = pci_nanoengine_setup_resources(sys); + /* Enable alternate memory bus master mode, see + * "Intel StrongARM SA1110 Developer's Manual", + * section 10.8, "Alternate Memory Bus Master Mode". */ + GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; + GAFR |= GPIO_MBGNT | GPIO_MBREQ; + TUCR |= TUCR_MBGPIO; + } + + return ret; +} + +static struct hw_pci nanoengine_pci __initdata = { + .map_irq = pci_nanoengine_map_irq, + .nr_controllers = 1, + .ops = &pci_nano_ops, + .setup = pci_nanoengine_setup, +}; + +static int __init nanoengine_pci_init(void) +{ + if (machine_is_nanoengine()) + pci_common_init(&nanoengine_pci); + return 0; +} + +subsys_initcall(nanoengine_pci_init); diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c index e1458bc1868..091261878ef 100644 --- a/arch/arm/mach-sa1100/pleb.c +++ b/arch/arm/mach-sa1100/pleb.c @@ -6,6 +6,7 @@ #include <linux/kernel.h> #include <linux/tty.h> #include <linux/ioport.h> +#include <linux/platform_data/sa11x0-serial.h> #include <linux/platform_device.h> #include <linux/irq.h> #include <linux/io.h> @@ -18,7 +19,6 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/flash.h> -#include <asm/mach/serial_sa1100.h> #include <mach/irqs.h> #include "generic.h" @@ -37,17 +37,9 @@ #define IRQ_GPIO_ETH0_IRQ IRQ_GPIO21 static struct resource smc91x_resources[] = { - [0] = { - .start = PLEB_ETH0_P, - .end = PLEB_ETH0_P | 0x03ffffff, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM(PLEB_ETH0_P, 0x04000000), #if 0 /* Autoprobe instead, to get rising/falling edge characteristic right */ - [1] = { - .start = IRQ_GPIO_ETH0_IRQ, - .end = IRQ_GPIO_ETH0_IRQ, - .flags = IORESOURCE_IRQ, - }, + [1] = DEFINE_RES_IRQ(IRQ_GPIO_ETH0_IRQ), #endif }; @@ -70,16 +62,8 @@ static struct platform_device *devices[] __initdata = { * the two SA1100 lowest chip select outputs. */ static struct resource pleb_flash_resources[] = { - [0] = { - .start = SA1100_CS0_PHYS, - .end = SA1100_CS0_PHYS + SZ_8M - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = SA1100_CS1_PHYS, - .end = SA1100_CS1_PHYS + SZ_8M - 1, - .flags = IORESOURCE_MEM, - } + [0] = DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_8M), + [1] = DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_8M), }; @@ -109,7 +93,7 @@ static struct flash_platform_data pleb_flash_data = { static void __init pleb_init(void) { - sa11x0_set_flash_data(&pleb_flash_data, pleb_flash_resources, + sa11x0_register_mtd(&pleb_flash_data, pleb_flash_resources, ARRAY_SIZE(pleb_flash_resources)); @@ -142,14 +126,15 @@ static void __init pleb_map_io(void) GPDR &= ~GPIO_ETH0_IRQ; - set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING); } MACHINE_START(PLEB, "PLEB") - .phys_io = 0x80000000, - .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc, .map_io = pleb_map_io, + .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = pleb_init, + .init_late = sa11x0_init_late, + .restart = sa11x0_restart, MACHINE_END diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c index 111cce67ad2..6645d1e31f1 100644 --- a/arch/arm/mach-sa1100/pm.c +++ b/arch/arm/mach-sa1100/pm.c @@ -15,7 +15,7 @@ * Save more value for the resume function! Support * Bitsy/Assabet/Freebird board * - * 2001-08-29: Nicolas Pitre <nico@cam.org> + * 2001-08-29: Nicolas Pitre <nico@fluxnic.net> * Cleaned up, pushed platform dependent stuff * in the platform specific files. * @@ -23,17 +23,17 @@ * Storage is local on the stack now. */ #include <linux/init.h> +#include <linux/io.h> #include <linux/suspend.h> #include <linux/errno.h> #include <linux/time.h> #include <mach/hardware.h> #include <asm/memory.h> -#include <asm/system.h> +#include <asm/suspend.h> #include <asm/mach/time.h> -extern void sa1100_cpu_suspend(void); -extern void sa1100_cpu_resume(void); +extern int sa1100_finish_suspend(unsigned long); #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] @@ -73,12 +73,10 @@ static int sa11x0_pm_enter(suspend_state_t state) RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR; /* set resume return address */ - PSPR = virt_to_phys(sa1100_cpu_resume); + PSPR = virt_to_phys(cpu_resume); /* go zzz */ - sa1100_cpu_suspend(); - - cpu_init(); + cpu_suspend(0, sa1100_finish_suspend); /* * Ensure not to come back here if it wasn't intended @@ -115,20 +113,13 @@ static int sa11x0_pm_enter(suspend_state_t state) return 0; } -unsigned long sleep_phys_sp(void *sp) -{ - return virt_to_phys(sp); -} - -static struct platform_suspend_ops sa11x0_pm_ops = { +static const struct platform_suspend_ops sa11x0_pm_ops = { .enter = sa11x0_pm_enter, .valid = suspend_valid_only_mem, }; -static int __init sa11x0_pm_init(void) +int __init sa11x0_pm_init(void) { suspend_set_ops(&sa11x0_pm_ops); return 0; } - -late_initcall(sa11x0_pm_init); diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c index ddd917d1083..c8866bce738 100644 --- a/arch/arm/mach-sa1100/shannon.c +++ b/arch/arm/mach-sa1100/shannon.c @@ -5,10 +5,13 @@ #include <linux/init.h> #include <linux/device.h> #include <linux/kernel.h> +#include <linux/platform_data/sa11x0-serial.h> #include <linux/tty.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <video/sa1100fb.h> + #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/setup.h> @@ -16,9 +19,9 @@ #include <asm/mach/arch.h> #include <asm/mach/flash.h> #include <asm/mach/map.h> -#include <asm/mach/serial_sa1100.h> -#include <mach/mcp.h> +#include <linux/platform_data/mfd-mcp-sa11x0.h> #include <mach/shannon.h> +#include <mach/irqs.h> #include "generic.h" @@ -46,21 +49,34 @@ static struct flash_platform_data shannon_flash_data = { .nr_parts = ARRAY_SIZE(shannon_partitions), }; -static struct resource shannon_flash_resource = { - .start = SA1100_CS0_PHYS, - .end = SA1100_CS0_PHYS + SZ_4M - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource shannon_flash_resource = + DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_4M); static struct mcp_plat_data shannon_mcp_data = { .mccr0 = MCCR0_ADM, .sclk_rate = 11981000, }; +static struct sa1100fb_mach_info shannon_lcd_info = { + .pixclock = 152500, .bpp = 8, + .xres = 640, .yres = 480, + + .hsync_len = 4, .vsync_len = 3, + .left_margin = 2, .upper_margin = 0, + .right_margin = 1, .lower_margin = 0, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + + .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas, + .lccr3 = LCCR3_ACBsDiv(512), +}; + static void __init shannon_init(void) { - sa11x0_set_flash_data(&shannon_flash_data, &shannon_flash_resource, 1); - sa11x0_set_mcp_data(&shannon_mcp_data); + sa11x0_ppc_configure_mcp(); + sa11x0_register_lcd(&shannon_lcd_info); + sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1); + sa11x0_register_mcp(&shannon_mcp_data); } static void __init shannon_map_io(void) @@ -82,11 +98,12 @@ static void __init shannon_map_io(void) } MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)") - .phys_io = 0x80000000, - .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc, - .boot_params = 0xc0000100, + .atag_offset = 0x100, .map_io = shannon_map_io, + .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = shannon_init, + .init_late = sa11x0_init_late, + .restart = sa11x0_restart, MACHINE_END diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c index 3c74534f7fe..41e476e571d 100644 --- a/arch/arm/mach-sa1100/simpad.c +++ b/arch/arm/mach-sa1100/simpad.c @@ -7,56 +7,116 @@ #include <linux/kernel.h> #include <linux/tty.h> #include <linux/proc_fs.h> -#include <linux/string.h> +#include <linux/string.h> #include <linux/pm.h> +#include <linux/platform_data/sa11x0-serial.h> #include <linux/platform_device.h> +#include <linux/mfd/ucb1x00.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/io.h> +#include <linux/gpio.h> -#include <asm/irq.h> #include <mach/hardware.h> #include <asm/setup.h> +#include <asm/irq.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> #include <asm/mach/map.h> -#include <asm/mach/serial_sa1100.h> -#include <mach/mcp.h> +#include <linux/platform_data/mfd-mcp-sa11x0.h> #include <mach/simpad.h> +#include <mach/irqs.h> #include <linux/serial_core.h> #include <linux/ioport.h> +#include <linux/input.h> +#include <linux/gpio_keys.h> +#include <linux/leds.h> +#include <linux/i2c-gpio.h> #include "generic.h" -long cs3_shadow; +/* + * CS3 support + */ + +static long cs3_shadow; +static spinlock_t cs3_lock; +static struct gpio_chip cs3_gpio; -long get_cs3_shadow(void) +long simpad_get_cs3_ro(void) +{ + return readl(CS3_BASE); +} +EXPORT_SYMBOL(simpad_get_cs3_ro); + +long simpad_get_cs3_shadow(void) { return cs3_shadow; } +EXPORT_SYMBOL(simpad_get_cs3_shadow); -void set_cs3(long value) +static void __simpad_write_cs3(void) { - *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow = value; + writel(cs3_shadow, CS3_BASE); } -void set_cs3_bit(int value) +void simpad_set_cs3_bit(int value) { + unsigned long flags; + + spin_lock_irqsave(&cs3_lock, flags); cs3_shadow |= value; - *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow; + __simpad_write_cs3(); + spin_unlock_irqrestore(&cs3_lock, flags); } +EXPORT_SYMBOL(simpad_set_cs3_bit); -void clear_cs3_bit(int value) +void simpad_clear_cs3_bit(int value) { + unsigned long flags; + + spin_lock_irqsave(&cs3_lock, flags); cs3_shadow &= ~value; - *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow; + __simpad_write_cs3(); + spin_unlock_irqrestore(&cs3_lock, flags); } +EXPORT_SYMBOL(simpad_clear_cs3_bit); + +static void cs3_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + if (offset > 15) + return; + if (value) + simpad_set_cs3_bit(1 << offset); + else + simpad_clear_cs3_bit(1 << offset); +}; + +static int cs3_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + if (offset > 15) + return simpad_get_cs3_ro() & (1 << (offset - 16)); + return simpad_get_cs3_shadow() & (1 << offset); +}; + +static int cs3_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + if (offset > 15) + return 0; + return -EINVAL; +}; -EXPORT_SYMBOL(set_cs3_bit); -EXPORT_SYMBOL(clear_cs3_bit); +static int cs3_gpio_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + if (offset > 15) + return -EINVAL; + cs3_gpio_set(chip, offset, value); + return 0; +}; static struct map_desc simpad_io_desc[] __initdata = { { /* MQ200 */ @@ -64,9 +124,9 @@ static struct map_desc simpad_io_desc[] __initdata = { .pfn = __phys_to_pfn(0x4b800000), .length = 0x00800000, .type = MT_DEVICE - }, { /* Paules CS3, write only */ - .virtual = 0xf1000000, - .pfn = __phys_to_pfn(0x18000000), + }, { /* Simpad CS3 */ + .virtual = (unsigned long)CS3_BASE, + .pfn = __phys_to_pfn(SA1100_CS3_PHYS), .length = 0x00100000, .type = MT_DEVICE }, @@ -78,12 +138,12 @@ static void simpad_uart_pm(struct uart_port *port, u_int state, u_int oldstate) if (port->mapbase == (u_int)&Ser1UTCR0) { if (state) { - clear_cs3_bit(RS232_ON); - clear_cs3_bit(DECT_POWER_ON); + simpad_clear_cs3_bit(RS232_ON); + simpad_clear_cs3_bit(DECT_POWER_ON); }else { - set_cs3_bit(RS232_ON); - set_cs3_bit(DECT_POWER_ON); + simpad_set_cs3_bit(RS232_ON); + simpad_set_cs3_bit(DECT_POWER_ON); } } } @@ -118,20 +178,18 @@ static struct flash_platform_data simpad_flash_data = { static struct resource simpad_flash_resources [] = { - { - .start = SA1100_CS0_PHYS, - .end = SA1100_CS0_PHYS + SZ_16M -1, - .flags = IORESOURCE_MEM, - }, { - .start = SA1100_CS1_PHYS, - .end = SA1100_CS1_PHYS + SZ_16M -1, - .flags = IORESOURCE_MEM, - } + DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_16M), + DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_16M), +}; + +static struct ucb1x00_plat_data simpad_ucb1x00_data = { + .gpio_base = SIMPAD_UCB1X00_GPIO_BASE, }; static struct mcp_plat_data simpad_mcp_data = { .mccr0 = MCCR0_ADM, .sclk_rate = 11981000, + .codec_pdata = &simpad_ucb1x00_data, }; @@ -142,9 +200,10 @@ static void __init simpad_map_io(void) iotable_init(simpad_io_desc, ARRAY_SIZE(simpad_io_desc)); - set_cs3_bit (EN1 | EN0 | LED2_ON | DISPLAY_ON | RS232_ON | - ENABLE_5V | RESET_SIMCARD | DECT_POWER_ON); - + /* Initialize CS3 */ + cs3_shadow = (EN1 | EN0 | LED2_ON | DISPLAY_ON | + RS232_ON | ENABLE_5V | RESET_SIMCARD | DECT_POWER_ON); + __simpad_write_cs3(); /* Spinlocks not yet initialized */ sa1100_register_uart_fns(&simpad_port_fns); sa1100_register_uart(0, 3); /* serial interface */ @@ -166,20 +225,18 @@ static void __init simpad_map_io(void) PCFR = 0; PSDR = 0; - sa11x0_set_flash_data(&simpad_flash_data, simpad_flash_resources, - ARRAY_SIZE(simpad_flash_resources)); - sa11x0_set_mcp_data(&simpad_mcp_data); } static void simpad_power_off(void) { - local_irq_disable(); // was cli - set_cs3(0x800); /* only SD_MEDIAQ */ + local_irq_disable(); + cs3_shadow = SD_MEDIAQ; + __simpad_write_cs3(); /* Bypass spinlock here */ /* disable internal oscillator, float CS lines */ PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS); - /* enable wake-up on GPIO0 (Assabet...) */ - PWER = GFER = GRER = 1; + /* enable wake-up on GPIO0 */ + PWER = GFER = GRER = PWER_GPIO0; /* * set scratchpad to zero, just in case it is used as a * restart address by the bootloader. @@ -195,6 +252,91 @@ static void simpad_power_off(void) } +/* + * gpio_keys +*/ + +static struct gpio_keys_button simpad_button_table[] = { + { KEY_POWER, IRQ_GPIO_POWER_BUTTON, 1, "power button" }, +}; + +static struct gpio_keys_platform_data simpad_keys_data = { + .buttons = simpad_button_table, + .nbuttons = ARRAY_SIZE(simpad_button_table), +}; + +static struct platform_device simpad_keys = { + .name = "gpio-keys", + .dev = { + .platform_data = &simpad_keys_data, + }, +}; + +static struct gpio_keys_button simpad_polled_button_table[] = { + { KEY_PROG1, SIMPAD_UCB1X00_GPIO_PROG1, 1, "prog1 button" }, + { KEY_PROG2, SIMPAD_UCB1X00_GPIO_PROG2, 1, "prog2 button" }, + { KEY_UP, SIMPAD_UCB1X00_GPIO_UP, 1, "up button" }, + { KEY_DOWN, SIMPAD_UCB1X00_GPIO_DOWN, 1, "down button" }, + { KEY_LEFT, SIMPAD_UCB1X00_GPIO_LEFT, 1, "left button" }, + { KEY_RIGHT, SIMPAD_UCB1X00_GPIO_RIGHT, 1, "right button" }, +}; + +static struct gpio_keys_platform_data simpad_polled_keys_data = { + .buttons = simpad_polled_button_table, + .nbuttons = ARRAY_SIZE(simpad_polled_button_table), + .poll_interval = 50, +}; + +static struct platform_device simpad_polled_keys = { + .name = "gpio-keys-polled", + .dev = { + .platform_data = &simpad_polled_keys_data, + }, +}; + +/* + * GPIO LEDs + */ + +static struct gpio_led simpad_leds[] = { + { + .name = "simpad:power", + .gpio = SIMPAD_CS3_LED2_ON, + .active_low = 0, + .default_trigger = "default-on", + }, +}; + +static struct gpio_led_platform_data simpad_led_data = { + .num_leds = ARRAY_SIZE(simpad_leds), + .leds = simpad_leds, +}; + +static struct platform_device simpad_gpio_leds = { + .name = "leds-gpio", + .id = 0, + .dev = { + .platform_data = &simpad_led_data, + }, +}; + +/* + * i2c + */ +static struct i2c_gpio_platform_data simpad_i2c_data = { + .sda_pin = GPIO_GPIO21, + .scl_pin = GPIO_GPIO25, + .udelay = 10, + .timeout = HZ, +}; + +static struct platform_device simpad_i2c = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &simpad_i2c_data, + }, +}; /* * MediaQ Video Device @@ -205,7 +347,11 @@ static struct platform_device simpad_mq200fb = { }; static struct platform_device *devices[] __initdata = { - &simpad_mq200fb + &simpad_keys, + &simpad_polled_keys, + &simpad_mq200fb, + &simpad_gpio_leds, + &simpad_i2c, }; @@ -214,8 +360,26 @@ static int __init simpad_init(void) { int ret; + spin_lock_init(&cs3_lock); + + cs3_gpio.label = "simpad_cs3"; + cs3_gpio.base = SIMPAD_CS3_GPIO_BASE; + cs3_gpio.ngpio = 24; + cs3_gpio.set = cs3_gpio_set; + cs3_gpio.get = cs3_gpio_get; + cs3_gpio.direction_input = cs3_gpio_direction_input; + cs3_gpio.direction_output = cs3_gpio_direction_output; + ret = gpiochip_add(&cs3_gpio); + if (ret) + printk(KERN_WARNING "simpad: Unable to register cs3 GPIO device"); + pm_power_off = simpad_power_off; + sa11x0_ppc_configure_mcp(); + sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources, + ARRAY_SIZE(simpad_flash_resources)); + sa11x0_register_mcp(&simpad_mcp_data); + ret = platform_add_devices(devices, ARRAY_SIZE(devices)); if(ret) printk(KERN_WARNING "simpad: Unable to register mq200 framebuffer device"); @@ -228,10 +392,11 @@ arch_initcall(simpad_init); MACHINE_START(SIMPAD, "Simpad") /* Maintainer: Holger Freyther */ - .phys_io = 0x80000000, - .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc, - .boot_params = 0xc0000100, + .atag_offset = 0x100, .map_io = simpad_map_io, + .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_late = sa11x0_init_late, + .init_time = sa1100_timer_init, + .restart = sa11x0_restart, MACHINE_END diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S index 80f31bad707..85863741ef8 100644 --- a/arch/arm/mach-sa1100/sleep.S +++ b/arch/arm/mach-sa1100/sleep.S @@ -20,62 +20,44 @@ #include <asm/assembler.h> #include <mach/hardware.h> - - .text - - - /* - * sa1100_cpu_suspend() + * sa1100_finish_suspend() * * Causes sa11x0 to enter sleep state * + * Must be aligned to a cacheline. */ + .balign 32 +ENTRY(sa1100_finish_suspend) + @ disable clock switching + mcr p15, 0, r1, c15, c2, 2 -ENTRY(sa1100_cpu_suspend) - - stmfd sp!, {r4 - r12, lr} @ save registers on stack - - @ get coprocessor registers - mrc p15, 0, r4, c3, c0, 0 @ domain ID - mrc p15, 0, r5, c2, c0, 0 @ translation table base addr - mrc p15, 0, r6, c13, c0, 0 @ PID - mrc p15, 0, r7, c1, c0, 0 @ control reg - - @ store them plus current virtual stack ptr on stack - mov r8, sp - stmfd sp!, {r4 - r8} - - @ preserve phys address of stack - mov r0, sp - bl sleep_phys_sp - ldr r1, =sleep_save_sp - str r0, [r1] + ldr r6, =MDREFR + ldr r4, [r6] + orr r4, r4, #MDREFR_K1DB2 + ldr r5, =PPCR - @ clean data cache and invalidate WB - bl v4wb_flush_kern_cache_all + @ Pre-load __loop_udelay into the I-cache + mov r0, #1 + bl __loop_udelay + mov r0, r0 - @ disable clock switching - mcr p15, 0, r1, c15, c2, 2 + @ The following must all exist in a single cache line to + @ avoid accessing memory until this sequence is complete, + @ otherwise we occasionally hang. - @ Adjust memory timing before lowering CPU clock - @ Clock speed adjustment without changing memory timing makes - @ CPU hang in some cases - ldr r0, =MDREFR - ldr r1, [r0] - orr r1, r1, #MDREFR_K1DB2 - str r1, [r0] + @ Adjust memory timing before lowering CPU clock + str r4, [r6] @ delay 90us and set CPU PLL to lowest speed @ fixes resume problem on high speed SA1110 mov r0, #90 - bl __udelay - ldr r0, =PPCR + bl __loop_udelay mov r1, #0 - str r1, [r0] + str r1, [r5] mov r0, #90 - bl __udelay + bl __loop_udelay /* * SA1110 SDRAM controller workaround. register values: @@ -112,12 +94,10 @@ ENTRY(sa1100_cpu_suspend) bic r5, r5, #FMsk(MSC_RT) bic r5, r5, #FMsk(MSC_RT)<<16 - ldr r6, =MDREFR - ldr r7, [r6] -bic r7, r7, #0x0000FF00 -bic r7, r7, #0x000000F0 -orr r8, r7, #MDREFR_SLFRSH + bic r7, r7, #0x0000FF00 + bic r7, r7, #0x000000F0 + orr r8, r7, #MDREFR_SLFRSH ldr r9, =MDCNFG ldr r10, [r9] @@ -161,55 +141,3 @@ sa1110_sdram_controller_fix: str r13, [r12] 20: b 20b @ loop waiting for sleep - -/* - * cpu_sa1100_resume() - * - * entry point from bootloader into kernel during resume - * - * Note: Yes, part of the following code is located into the .data section. - * This is to allow sleep_save_sp to be accessed with a relative load - * while we can't rely on any MMU translation. We could have put - * sleep_save_sp in the .text section as well, but some setups might - * insist on it to be truly read-only. - */ - - .data - .align 5 -ENTRY(sa1100_cpu_resume) - mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE - msr cpsr_c, r0 @ set SVC, irqs off - - ldr r0, sleep_save_sp @ stack phys addr - ldr r2, =resume_after_mmu @ its absolute virtual address - ldmfd r0, {r4 - r7, sp} @ CP regs + virt stack ptr - - mov r1, #0 - mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs - mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache - mcr p15, 0, r1, c9, c0, 0 @ invalidate RB - mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB - - mcr p15, 0, r4, c3, c0, 0 @ domain ID - mcr p15, 0, r5, c2, c0, 0 @ translation table base addr - mcr p15, 0, r6, c13, c0, 0 @ PID - b resume_turn_on_mmu @ cache align execution - - .align 5 -resume_turn_on_mmu: - mcr p15, 0, r7, c1, c0, 0 @ turn on MMU, caches, etc. - nop - mov pc, r2 @ jump to virtual addr - nop - nop - nop - -sleep_save_sp: - .word 0 @ preserve stack phys ptr here - - .text -resume_after_mmu: - mcr p15, 0, r1, c15, c1, 2 @ enable clock switching - ldmfd sp!, {r4 - r12, pc} @ return to caller - - diff --git a/arch/arm/mach-sa1100/ssp.c b/arch/arm/mach-sa1100/ssp.c index b20ff93b84a..e22fca9ad5e 100644 --- a/arch/arm/mach-sa1100/ssp.c +++ b/arch/arm/mach-sa1100/ssp.c @@ -19,8 +19,8 @@ #include <linux/init.h> #include <linux/io.h> -#include <asm/irq.h> #include <mach/hardware.h> +#include <mach/irqs.h> #include <asm/hardware/ssp.h> #define TIMEOUT 100000 diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index 711c0295c66..1dea6cfafb3 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c @@ -4,19 +4,30 @@ * Copyright (C) 1998 Deborah Wallach. * Twiddles (C) 1999 Hugo Fiennes <hugo@empeg.com> * - * 2000/03/29 (C) Nicolas Pitre <nico@cam.org> + * 2000/03/29 (C) Nicolas Pitre <nico@fluxnic.net> * Rewritten: big cleanup, much simpler, better HZ accuracy. * */ #include <linux/init.h> +#include <linux/kernel.h> #include <linux/errno.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/timex.h> #include <linux/clockchips.h> +#include <linux/sched_clock.h> #include <asm/mach/time.h> #include <mach/hardware.h> +#include <mach/irqs.h> + +#define SA1100_CLOCK_FREQ 3686400 +#define SA1100_LATCH DIV_ROUND_CLOSEST(SA1100_CLOCK_FREQ, HZ) + +static u64 notrace sa1100_read_sched_clock(void) +{ + return readl_relaxed(OSCR); +} #define MIN_OSCR_DELTA 2 @@ -25,8 +36,8 @@ static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id) struct clock_event_device *c = dev_id; /* Disarm the compare/match, signal the event. */ - OIER &= ~OIER_E0; - OSSR = OSSR_M0; + writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER); + writel_relaxed(OSSR_M0, OSSR); c->event_handler(c); return IRQ_HANDLED; @@ -35,14 +46,12 @@ static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id) static int sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c) { - unsigned long flags, next, oscr; + unsigned long next, oscr; - raw_local_irq_save(flags); - OIER |= OIER_E0; - next = OSCR + delta; - OSMR0 = next; - oscr = OSCR; - raw_local_irq_restore(flags); + writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER); + next = readl_relaxed(OSCR) + delta; + writel_relaxed(next, OSMR0); + oscr = readl_relaxed(OSCR); return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0; } @@ -50,16 +59,12 @@ sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c) static void sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c) { - unsigned long flags; - switch (mode) { case CLOCK_EVT_MODE_ONESHOT: case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: - raw_local_irq_save(flags); - OIER &= ~OIER_E0; - OSSR = OSSR_M0; - raw_local_irq_restore(flags); + writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER); + writel_relaxed(OSSR_M0, OSSR); break; case CLOCK_EVT_MODE_RESUME: @@ -68,91 +73,67 @@ sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c) } } -static struct clock_event_device ckevt_sa1100_osmr0 = { - .name = "osmr0", - .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, - .rating = 200, - .set_next_event = sa1100_osmr0_set_next_event, - .set_mode = sa1100_osmr0_set_mode, -}; - -static cycle_t sa1100_read_oscr(void) -{ - return OSCR; -} - -static struct clocksource cksrc_sa1100_oscr = { - .name = "oscr", - .rating = 200, - .read = sa1100_read_oscr, - .mask = CLOCKSOURCE_MASK(32), - .shift = 20, - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static struct irqaction sa1100_timer_irq = { - .name = "ost0", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = sa1100_ost0_interrupt, - .dev_id = &ckevt_sa1100_osmr0, -}; - -static void __init sa1100_timer_init(void) -{ - OIER = 0; /* disable any timer interrupts */ - OSSR = 0xf; /* clear status on all timers */ - - ckevt_sa1100_osmr0.mult = - div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift); - ckevt_sa1100_osmr0.max_delta_ns = - clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0); - ckevt_sa1100_osmr0.min_delta_ns = - clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1; - ckevt_sa1100_osmr0.cpumask = cpumask_of(0); - - cksrc_sa1100_oscr.mult = - clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_sa1100_oscr.shift); - - setup_irq(IRQ_OST0, &sa1100_timer_irq); - - clocksource_register(&cksrc_sa1100_oscr); - clockevents_register_device(&ckevt_sa1100_osmr0); -} - #ifdef CONFIG_PM unsigned long osmr[4], oier; -static void sa1100_timer_suspend(void) +static void sa1100_timer_suspend(struct clock_event_device *cedev) { - osmr[0] = OSMR0; - osmr[1] = OSMR1; - osmr[2] = OSMR2; - osmr[3] = OSMR3; - oier = OIER; + osmr[0] = readl_relaxed(OSMR0); + osmr[1] = readl_relaxed(OSMR1); + osmr[2] = readl_relaxed(OSMR2); + osmr[3] = readl_relaxed(OSMR3); + oier = readl_relaxed(OIER); } -static void sa1100_timer_resume(void) +static void sa1100_timer_resume(struct clock_event_device *cedev) { - OSSR = 0x0f; - OSMR0 = osmr[0]; - OSMR1 = osmr[1]; - OSMR2 = osmr[2]; - OSMR3 = osmr[3]; - OIER = oier; + writel_relaxed(0x0f, OSSR); + writel_relaxed(osmr[0], OSMR0); + writel_relaxed(osmr[1], OSMR1); + writel_relaxed(osmr[2], OSMR2); + writel_relaxed(osmr[3], OSMR3); + writel_relaxed(oier, OIER); /* * OSMR0 is the system timer: make sure OSCR is sufficiently behind */ - OSCR = OSMR0 - LATCH; + writel_relaxed(OSMR0 - SA1100_LATCH, OSCR); } #else #define sa1100_timer_suspend NULL #define sa1100_timer_resume NULL #endif -struct sys_timer sa1100_timer = { - .init = sa1100_timer_init, +static struct clock_event_device ckevt_sa1100_osmr0 = { + .name = "osmr0", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 200, + .set_next_event = sa1100_osmr0_set_next_event, + .set_mode = sa1100_osmr0_set_mode, .suspend = sa1100_timer_suspend, .resume = sa1100_timer_resume, }; + +static struct irqaction sa1100_timer_irq = { + .name = "ost0", + .flags = IRQF_TIMER | IRQF_IRQPOLL, + .handler = sa1100_ost0_interrupt, + .dev_id = &ckevt_sa1100_osmr0, +}; + +void __init sa1100_timer_init(void) +{ + writel_relaxed(0, OIER); + writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR); + + sched_clock_register(sa1100_read_sched_clock, 32, 3686400); + + ckevt_sa1100_osmr0.cpumask = cpumask_of(0); + + setup_irq(IRQ_OST0, &sa1100_timer_irq); + + clocksource_mmio_init(OSCR, "oscr", SA1100_CLOCK_FREQ, 200, 32, + clocksource_mmio_readl_up); + clockevents_config_and_register(&ckevt_sa1100_osmr0, 3686400, + MIN_OSCR_DELTA * 2, 0x7fffffff); +} |