diff options
Diffstat (limited to 'arch/arm/mach-s5pv210')
50 files changed, 3799 insertions, 1951 deletions
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 0761eac9aae..f60f2862856 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -11,9 +11,11 @@ if ARCH_S5PV210 config CPU_S5PV210 bool - select PLAT_S5P - select S3C_PL330_DMA + select ARM_AMBA + select PL330_DMA if DMADEVICES select S5P_EXT_INT + select S5P_PM if PM + select S5P_SLEEP if PM help Enable S5PV210 CPU support @@ -27,11 +29,21 @@ config S5PV210_SETUP_I2C2 help Common setup code for i2c bus 2. +config S5PV210_SETUP_IDE + bool + help + Common setup code for S5PV210 IDE GPIO configurations + config S5PV210_SETUP_FB_24BPP bool help Common setup code for S5PV210 with an 24bpp RGB display helper. +config S5PV210_SETUP_KEYPAD + bool + help + Common setup code for keypad. + config S5PV210_SETUP_SDHCI bool select S5PV210_SETUP_SDHCI_GPIO @@ -43,49 +55,145 @@ config S5PV210_SETUP_SDHCI_GPIO help Common setup code for SDHCI gpio. -# machine support +config S5PV210_SETUP_FIMC + bool + help + Common setup code for the camera interfaces. + +config S5PV210_SETUP_SPI + bool + help + Common setup code for SPI GPIO configurations. + +config S5PV210_SETUP_USB_PHY + bool + help + Common setup code for USB PHY controller + +menu "S5PC110 Machines" config MACH_AQUILA - bool "Samsung Aquila" + bool "Aquila" select CPU_S5PV210 - select ARCH_SPARSEMEM_ENABLE - select S5PV210_SETUP_FB_24BPP select S3C_DEV_FB + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C_DEV_HSMMC2 + select S5PV210_SETUP_FB_24BPP + select S5PV210_SETUP_SDHCI + select S5PV210_SETUP_USB_PHY + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 + select S5P_DEV_ONENAND help Machine support for the Samsung Aquila target based on S5PC110 SoC config MACH_GONI bool "GONI" select CPU_S5PV210 - select ARCH_SPARSEMEM_ENABLE + select S3C_DEV_FB + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C_DEV_HSMMC2 + select S3C_DEV_I2C1 + select S3C_DEV_I2C2 + select S3C_DEV_USB_HSOTG + select S5PV210_SETUP_FB_24BPP + select S5PV210_SETUP_FIMC + select S5PV210_SETUP_I2C1 + select S5PV210_SETUP_I2C2 + select S5PV210_SETUP_KEYPAD + select S5PV210_SETUP_SDHCI + select S5PV210_SETUP_USB_PHY + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 + select S5P_DEV_MFC + select S5P_DEV_ONENAND + select S5P_DEV_TV + select S5P_GPIO_INT + select SAMSUNG_DEV_KEYPAD help Machine support for Samsung GONI board S5PC110(MCP) is one of package option of S5PV210 -config S5PC110_DEV_ONENAND - bool +config MACH_SMDKC110 + bool "SMDKC110" + select CPU_S5PV210 + select S3C_DEV_I2C1 + select S3C_DEV_I2C2 + select S3C_DEV_RTC + select S3C_DEV_WDT + select S5PV210_SETUP_I2C1 + select S5PV210_SETUP_I2C2 + select S5PV210_SETUP_IDE + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 + select S5P_DEV_MFC + select SAMSUNG_DEV_IDE help - Compile in platform device definition for OneNAND1 controller + Machine support for Samsung SMDKC110 + S5PC110(MCP) is one of package option of S5PV210 + +endmenu + +menu "S5PV210 Machines" config MACH_SMDKV210 bool "SMDKV210" select CPU_S5PV210 - select ARCH_SPARSEMEM_ENABLE + select S3C_DEV_FB + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C_DEV_HSMMC2 + select S3C_DEV_HSMMC3 + select S3C_DEV_I2C1 + select S3C_DEV_I2C2 + select S3C_DEV_RTC + select S3C_DEV_USB_HSOTG + select S3C_DEV_WDT + select S5PV210_SETUP_FB_24BPP + select S5PV210_SETUP_I2C1 + select S5PV210_SETUP_I2C2 + select S5PV210_SETUP_IDE + select S5PV210_SETUP_KEYPAD + select S5PV210_SETUP_SDHCI + select S5PV210_SETUP_USB_PHY + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 + select S5P_DEV_JPEG + select S5P_DEV_MFC select SAMSUNG_DEV_ADC + select SAMSUNG_DEV_BACKLIGHT + select SAMSUNG_DEV_IDE + select SAMSUNG_DEV_KEYPAD + select SAMSUNG_DEV_PWM select SAMSUNG_DEV_TS - select S3C_DEV_WDT - select HAVE_S3C2410_WATCHDOG help Machine support for Samsung SMDKV210 -config MACH_SMDKC110 - bool "SMDKC110" - select CPU_S5PV210 +config MACH_TORBRECK + bool "Torbreck" select ARCH_SPARSEMEM_ENABLE + select CPU_S5PV210 + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C_DEV_HSMMC2 + select S3C_DEV_HSMMC3 + select S3C_DEV_I2C1 + select S3C_DEV_I2C2 + select S3C_DEV_RTC select S3C_DEV_WDT - select HAVE_S3C2410_WATCHDOG + select S5PV210_SETUP_I2C1 + select S5PV210_SETUP_I2C2 + select S5PV210_SETUP_SDHCI + select SAMSUNG_DEV_IDE help - Machine support for Samsung SMDKC110 - S5PC110(MCP) is one of package option of S5PV210 + Machine support for aESOP Torbreck + +endmenu endif diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index 30be9a6a462..1c4e41998a1 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -10,26 +10,33 @@ obj-m := obj-n := obj- := -# Core support for S5PV210 system +# Core -obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o gpiolib.o -obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o +obj-y += common.o clock.o + +obj-$(CONFIG_PM) += pm.o + +obj-y += dma.o # machine support obj-$(CONFIG_MACH_AQUILA) += mach-aquila.o -obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o -obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o obj-$(CONFIG_MACH_GONI) += mach-goni.o +obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o +obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o +obj-$(CONFIG_MACH_TORBRECK) += mach-torbreck.o # device support obj-y += dev-audio.o -obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o -obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o +obj-y += setup-i2c0.o obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o -obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o -obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o -obj-$(CONFIG_S5PV210_SETUP_SDHCI) += setup-sdhci.o +obj-$(CONFIG_S5PV210_SETUP_FIMC) += setup-fimc.o +obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o +obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o +obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o +obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o +obj-$(CONFIG_S5PV210_SETUP_SPI) += setup-spi.o +obj-$(CONFIG_S5PV210_SETUP_USB_PHY) += setup-usb-phy.o diff --git a/arch/arm/mach-s5pv210/Makefile.boot b/arch/arm/mach-s5pv210/Makefile.boot index ff90aa13bd6..79ece4055b0 100644 --- a/arch/arm/mach-s5pv210/Makefile.boot +++ b/arch/arm/mach-s5pv210/Makefile.boot @@ -1,2 +1,2 @@ - zreladdr-y := 0x20008000 + zreladdr-y += 0x20008000 params_phys-y := 0x20000100 diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index af91fefef2c..ca463724a3d 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -17,7 +17,7 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/clk.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/io.h> #include <mach/map.h> @@ -29,12 +29,14 @@ #include <plat/pll.h> #include <plat/s5p-clock.h> #include <plat/clock-clksrc.h> -#include <plat/s5pv210.h> + +#include "common.h" + +static unsigned long xtal; static struct clksrc_clk clk_mout_apll = { .clk = { .name = "mout_apll", - .id = -1, }, .sources = &clk_src_apll, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, @@ -43,7 +45,6 @@ static struct clksrc_clk clk_mout_apll = { static struct clksrc_clk clk_mout_epll = { .clk = { .name = "mout_epll", - .id = -1, }, .sources = &clk_src_epll, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, @@ -52,7 +53,6 @@ static struct clksrc_clk clk_mout_epll = { static struct clksrc_clk clk_mout_mpll = { .clk = { .name = "mout_mpll", - .id = -1, }, .sources = &clk_src_mpll, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, @@ -71,7 +71,6 @@ static struct clksrc_sources clkset_armclk = { static struct clksrc_clk clk_armclk = { .clk = { .name = "armclk", - .id = -1, }, .sources = &clkset_armclk, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, @@ -81,7 +80,6 @@ static struct clksrc_clk clk_armclk = { static struct clksrc_clk clk_hclk_msys = { .clk = { .name = "hclk_msys", - .id = -1, .parent = &clk_armclk.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, @@ -90,7 +88,6 @@ static struct clksrc_clk clk_hclk_msys = { static struct clksrc_clk clk_pclk_msys = { .clk = { .name = "pclk_msys", - .id = -1, .parent = &clk_hclk_msys.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, @@ -99,7 +96,6 @@ static struct clksrc_clk clk_pclk_msys = { static struct clksrc_clk clk_sclk_a2m = { .clk = { .name = "sclk_a2m", - .id = -1, .parent = &clk_mout_apll.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, @@ -118,7 +114,6 @@ static struct clksrc_sources clkset_hclk_sys = { static struct clksrc_clk clk_hclk_dsys = { .clk = { .name = "hclk_dsys", - .id = -1, }, .sources = &clkset_hclk_sys, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, @@ -128,7 +123,6 @@ static struct clksrc_clk clk_hclk_dsys = { static struct clksrc_clk clk_pclk_dsys = { .clk = { .name = "pclk_dsys", - .id = -1, .parent = &clk_hclk_dsys.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, @@ -137,7 +131,6 @@ static struct clksrc_clk clk_pclk_dsys = { static struct clksrc_clk clk_hclk_psys = { .clk = { .name = "hclk_psys", - .id = -1, }, .sources = &clkset_hclk_sys, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, @@ -147,7 +140,6 @@ static struct clksrc_clk clk_hclk_psys = { static struct clksrc_clk clk_pclk_psys = { .clk = { .name = "pclk_psys", - .id = -1, .parent = &clk_hclk_psys.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, @@ -173,11 +165,6 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); } -static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable); -} - static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); @@ -188,40 +175,43 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); } +static int s5pv210_clk_hdmiphy_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); +} + +static int exynos4_clk_dac_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable); +} + static struct clk clk_sclk_hdmi27m = { .name = "sclk_hdmi27m", - .id = -1, .rate = 27000000, }; static struct clk clk_sclk_hdmiphy = { .name = "sclk_hdmiphy", - .id = -1, }; static struct clk clk_sclk_usbphy0 = { .name = "sclk_usbphy0", - .id = -1, }; static struct clk clk_sclk_usbphy1 = { .name = "sclk_usbphy1", - .id = -1, }; static struct clk clk_pcmcdclk0 = { .name = "pcmcdclk", - .id = -1, }; static struct clk clk_pcmcdclk1 = { .name = "pcmcdclk", - .id = -1, }; static struct clk clk_pcmcdclk2 = { .name = "pcmcdclk", - .id = -1, }; static struct clk *clkset_vpllsrc_list[] = { @@ -237,7 +227,6 @@ static struct clksrc_sources clkset_vpllsrc = { static struct clksrc_clk clk_vpllsrc = { .clk = { .name = "vpll_src", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 7), }, @@ -258,12 +247,39 @@ static struct clksrc_sources clkset_sclk_vpll = { static struct clksrc_clk clk_sclk_vpll = { .clk = { .name = "sclk_vpll", - .id = -1, }, .sources = &clkset_sclk_vpll, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, }; +static struct clk *clkset_moutdmc0src_list[] = { + [0] = &clk_sclk_a2m.clk, + [1] = &clk_mout_mpll.clk, + [2] = NULL, + [3] = NULL, +}; + +static struct clksrc_sources clkset_moutdmc0src = { + .sources = clkset_moutdmc0src_list, + .nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list), +}; + +static struct clksrc_clk clk_mout_dmc0 = { + .clk = { + .name = "mout_dmc0", + }, + .sources = &clkset_moutdmc0src, + .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, +}; + +static struct clksrc_clk clk_sclk_dmc0 = { + .clk = { + .name = "sclk_dmc0", + .parent = &clk_mout_dmc0.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, +}; + static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk) { return clk_get_rate(clk->parent) / 2; @@ -273,189 +289,287 @@ static struct clk_ops clk_hclk_imem_ops = { .get_rate = s5pv210_clk_imem_get_rate, }; -static struct clk init_clocks_disable[] = { +static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk) +{ + return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); +} + +static struct clk_ops clk_fout_apll_ops = { + .get_rate = s5pv210_clk_fout_apll_get_rate, +}; + +static struct clk init_clocks_off[] = { { .name = "rot", - .id = -1, .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1<<29), }, { + .name = "fimc", + .devname = "s5pv210-fimc.0", + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 24), + }, { + .name = "fimc", + .devname = "s5pv210-fimc.1", + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 25), + }, { + .name = "fimc", + .devname = "s5pv210-fimc.2", + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 26), + }, { + .name = "jpeg", + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 28), + }, { + .name = "mfc", + .devname = "s5p-mfc", + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 16), + }, { + .name = "dac", + .devname = "s5p-sdo", + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 10), + }, { + .name = "mixer", + .devname = "s5p-mixer", + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 9), + }, { + .name = "vp", + .devname = "s5p-mixer", + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "hdmi", + .devname = "s5pv210-hdmi", + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 11), + }, { + .name = "hdmiphy", + .devname = "s5pv210-hdmi", + .enable = s5pv210_clk_hdmiphy_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "dacphy", + .devname = "s5p-sdo", + .enable = exynos4_clk_dac_ctrl, + .ctrlbit = (1 << 0), + }, { .name = "otg", - .id = -1, .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<16), }, { .name = "usb-host", - .id = -1, .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<17), }, { .name = "lcd", - .id = -1, .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<0), }, { .name = "cfcon", - .id = 0, .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<25), }, { - .name = "hsmmc", - .id = 0, - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1<<16), - }, { - .name = "hsmmc", - .id = 1, - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1<<17), - }, { - .name = "hsmmc", - .id = 2, - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1<<18), - }, { - .name = "hsmmc", - .id = 3, - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1<<19), - }, { .name = "systimer", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<16), }, { .name = "watchdog", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<22), }, { .name = "rtc", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<15), }, { .name = "i2c", - .id = 0, + .devname = "s3c2440-i2c.0", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<7), }, { .name = "i2c", - .id = 1, + .devname = "s3c2440-i2c.1", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1<<8), + .ctrlbit = (1 << 10), }, { .name = "i2c", - .id = 2, + .devname = "s3c2440-i2c.2", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<9), }, { + .name = "i2c", + .devname = "s3c2440-hdmiphy-i2c", + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 11), + }, { .name = "spi", - .id = 0, + .devname = "s5pv210-spi.0", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<12), }, { .name = "spi", - .id = 1, + .devname = "s5pv210-spi.1", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<13), }, { .name = "spi", - .id = 2, + .devname = "s5pv210-spi.2", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<14), }, { .name = "timers", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<23), }, { .name = "adc", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<24), }, { .name = "keypad", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<21), }, { - .name = "i2s_v50", - .id = 0, + .name = "iis", + .devname = "samsung-i2s.0", .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<4), }, { - .name = "i2s_v32", - .id = 0, + .name = "iis", + .devname = "samsung-i2s.1", .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 5), }, { - .name = "i2s_v32", - .id = 1, + .name = "iis", + .devname = "samsung-i2s.2", .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 6), + }, { + .name = "spdif", + .parent = &clk_p, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 0), }, }; static struct clk init_clocks[] = { { .name = "hclk_imem", - .id = -1, .parent = &clk_hclk_msys.clk, .ctrlbit = (1 << 5), .enable = s5pv210_clk_ip0_ctrl, .ops = &clk_hclk_imem_ops, }, { .name = "uart", - .id = 0, + .devname = "s5pv210-uart.0", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 17), }, { .name = "uart", - .id = 1, + .devname = "s5pv210-uart.1", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 18), }, { .name = "uart", - .id = 2, + .devname = "s5pv210-uart.2", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 19), }, { .name = "uart", - .id = 3, + .devname = "s5pv210-uart.3", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 20), + }, { + .name = "sromc", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 26), }, }; +static struct clk clk_hsmmc0 = { + .name = "hsmmc", + .devname = "s3c-sdhci.0", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1<<16), +}; + +static struct clk clk_hsmmc1 = { + .name = "hsmmc", + .devname = "s3c-sdhci.1", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1<<17), +}; + +static struct clk clk_hsmmc2 = { + .name = "hsmmc", + .devname = "s3c-sdhci.2", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1<<18), +}; + +static struct clk clk_hsmmc3 = { + .name = "hsmmc", + .devname = "s3c-sdhci.3", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1<<19), +}; + +static struct clk clk_pdma0 = { + .name = "pdma0", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 3), +}; + +static struct clk clk_pdma1 = { + .name = "pdma1", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 4), +}; + static struct clk *clkset_uart_list[] = { [6] = &clk_mout_mpll.clk, [7] = &clk_mout_epll.clk, @@ -501,7 +615,6 @@ static struct clksrc_sources clkset_sclk_dac = { static struct clksrc_clk clk_sclk_dac = { .clk = { .name = "sclk_dac", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 2), }, @@ -512,7 +625,6 @@ static struct clksrc_clk clk_sclk_dac = { static struct clksrc_clk clk_sclk_pixel = { .clk = { .name = "sclk_pixel", - .id = -1, .parent = &clk_sclk_vpll.clk, }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, @@ -531,7 +643,6 @@ static struct clksrc_sources clkset_sclk_hdmi = { static struct clksrc_clk clk_sclk_hdmi = { .clk = { .name = "sclk_hdmi", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 0), }, @@ -549,6 +660,23 @@ static struct clksrc_sources clkset_sclk_mixer = { .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list), }; +static struct clksrc_clk clk_sclk_mixer = { + .clk = { + .name = "sclk_mixer", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 1), + }, + .sources = &clkset_sclk_mixer, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 }, +}; + +static struct clksrc_clk *sclk_tv[] = { + &clk_sclk_dac, + &clk_sclk_pixel, + &clk_sclk_hdmi, + &clk_sclk_mixer, +}; + static struct clk *clkset_sclk_audio0_list[] = { [0] = &clk_ext_xtal_mux, [1] = &clk_pcmcdclk0, @@ -569,7 +697,7 @@ static struct clksrc_sources clkset_sclk_audio0 = { static struct clksrc_clk clk_sclk_audio0 = { .clk = { .name = "sclk_audio", - .id = 0, + .devname = "soc-audio.0", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 24), }, @@ -598,7 +726,7 @@ static struct clksrc_sources clkset_sclk_audio1 = { static struct clksrc_clk clk_sclk_audio1 = { .clk = { .name = "sclk_audio", - .id = 1, + .devname = "soc-audio.1", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 25), }, @@ -627,7 +755,7 @@ static struct clksrc_sources clkset_sclk_audio2 = { static struct clksrc_clk clk_sclk_audio2 = { .clk = { .name = "sclk_audio", - .id = 2, + .devname = "soc-audio.2", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 26), }, @@ -647,6 +775,17 @@ static struct clksrc_sources clkset_sclk_spdif = { .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list), }; +static struct clksrc_clk clk_sclk_spdif = { + .clk = { + .name = "sclk_spdif", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 27), + .ops = &s5p_sclk_spdif_ops, + }, + .sources = &clkset_sclk_spdif, + .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, +}; + static struct clk *clkset_group2_list[] = { [0] = &clk_ext_xtal_mux, [1] = &clk_xusbxti, @@ -668,7 +807,6 @@ static struct clksrc_clk clksrcs[] = { { .clk = { .name = "sclk_dmc", - .id = -1, }, .sources = &clkset_group1, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, @@ -676,73 +814,14 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_onenand", - .id = -1, }, .sources = &clkset_sclk_onenand, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 }, }, { .clk = { - .name = "uclk1", - .id = 0, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 12), - }, - .sources = &clkset_uart, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .id = 1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 13), - }, - .sources = &clkset_uart, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .id = 2, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 14), - }, - .sources = &clkset_uart, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .id = 3, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 15), - }, - .sources = &clkset_uart, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, - }, { - .clk = { - .name = "sclk_mixer", - .id = -1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 1), - }, - .sources = &clkset_sclk_mixer, - .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 }, - }, { - .clk = { - .name = "sclk_spdif", - .id = -1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 27), - }, - .sources = &clkset_sclk_spdif, - .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, - }, { - .clk = { .name = "sclk_fimc", - .id = 0, + .devname = "s5pv210-fimc.0", .enable = s5pv210_clk_mask1_ctrl, .ctrlbit = (1 << 2), }, @@ -752,7 +831,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimc", - .id = 1, + .devname = "s5pv210-fimc.1", .enable = s5pv210_clk_mask1_ctrl, .ctrlbit = (1 << 3), }, @@ -762,7 +841,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimc", - .id = 2, + .devname = "s5pv210-fimc.2", .enable = s5pv210_clk_mask1_ctrl, .ctrlbit = (1 << 4), }, @@ -771,8 +850,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 }, }, { .clk = { - .name = "sclk_cam", - .id = 0, + .name = "sclk_cam0", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 3), }, @@ -781,8 +859,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 }, }, { .clk = { - .name = "sclk_cam", - .id = 1, + .name = "sclk_cam1", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 4), }, @@ -792,7 +869,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimd", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 5), }, @@ -801,48 +877,8 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, }, { .clk = { - .name = "sclk_mmc", - .id = 0, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 8), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .id = 1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 9), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .id = 2, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 10), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .id = 3, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 11), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, - }, { - .clk = { .name = "sclk_mfc", - .id = -1, + .devname = "s5p-mfc", .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 16), }, @@ -852,7 +888,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_g2d", - .id = -1, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 12), }, @@ -862,7 +897,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_g3d", - .id = -1, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 8), }, @@ -872,7 +906,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_csis", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 6), }, @@ -881,28 +914,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 }, }, { .clk = { - .name = "sclk_spi", - .id = 0, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 16), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_spi", - .id = 1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 17), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 }, - }, { - .clk = { .name = "sclk_pwi", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 29), }, @@ -912,7 +924,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_pwm", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 19), }, @@ -922,6 +933,149 @@ static struct clksrc_clk clksrcs[] = { }, }; +static struct clksrc_clk clk_sclk_uart0 = { + .clk = { + .name = "uclk1", + .devname = "s5pv210-uart.0", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 12), + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_uart1 = { + .clk = { + .name = "uclk1", + .devname = "s5pv210-uart.1", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 13), + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_uart2 = { + .clk = { + .name = "uclk1", + .devname = "s5pv210-uart.2", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 14), + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_uart3 = { + .clk = { + .name = "uclk1", + .devname = "s5pv210-uart.3", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 15), + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc0 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.0", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc1 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.1", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 9), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc2 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.2", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 10), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc3 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.3", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 11), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_spi0 = { + .clk = { + .name = "sclk_spi", + .devname = "s5pv210-spi.0", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 16), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 }, + }; + +static struct clksrc_clk clk_sclk_spi1 = { + .clk = { + .name = "sclk_spi", + .devname = "s5pv210-spi.1", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 17), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 }, + }; + + +static struct clksrc_clk *clksrc_cdev[] = { + &clk_sclk_uart0, + &clk_sclk_uart1, + &clk_sclk_uart2, + &clk_sclk_uart3, + &clk_sclk_mmc0, + &clk_sclk_mmc1, + &clk_sclk_mmc2, + &clk_sclk_mmc3, + &clk_sclk_spi0, + &clk_sclk_spi1, +}; + +static struct clk *clk_cdev[] = { + &clk_hsmmc0, + &clk_hsmmc1, + &clk_hsmmc2, + &clk_hsmmc3, + &clk_pdma0, + &clk_pdma1, +}; + /* Clock initialisation code */ static struct clksrc_clk *sysclks[] = { &clk_mout_apll, @@ -937,15 +1091,148 @@ static struct clksrc_clk *sysclks[] = { &clk_pclk_psys, &clk_vpllsrc, &clk_sclk_vpll, - &clk_sclk_dac, - &clk_sclk_pixel, - &clk_sclk_hdmi, + &clk_mout_dmc0, + &clk_sclk_dmc0, + &clk_sclk_audio0, + &clk_sclk_audio1, + &clk_sclk_audio2, + &clk_sclk_spdif, +}; + +static u32 epll_div[][6] = { + { 48000000, 0, 48, 3, 3, 0 }, + { 96000000, 0, 48, 3, 2, 0 }, + { 144000000, 1, 72, 3, 2, 0 }, + { 192000000, 0, 48, 3, 1, 0 }, + { 288000000, 1, 72, 3, 1, 0 }, + { 32750000, 1, 65, 3, 4, 35127 }, + { 32768000, 1, 65, 3, 4, 35127 }, + { 45158400, 0, 45, 3, 3, 10355 }, + { 45000000, 0, 45, 3, 3, 10355 }, + { 45158000, 0, 45, 3, 3, 10355 }, + { 49125000, 0, 49, 3, 3, 9961 }, + { 49152000, 0, 49, 3, 3, 9961 }, + { 67737600, 1, 67, 3, 3, 48366 }, + { 67738000, 1, 67, 3, 3, 48366 }, + { 73800000, 1, 73, 3, 3, 47710 }, + { 73728000, 1, 73, 3, 3, 47710 }, + { 36000000, 1, 32, 3, 4, 0 }, + { 60000000, 1, 60, 3, 3, 0 }, + { 72000000, 1, 72, 3, 3, 0 }, + { 80000000, 1, 80, 3, 3, 0 }, + { 84000000, 0, 42, 3, 2, 0 }, + { 50000000, 0, 50, 3, 3, 0 }, +}; + +static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int epll_con, epll_con_k; + unsigned int i; + + /* Return if nothing changed */ + if (clk->rate == rate) + return 0; + + epll_con = __raw_readl(S5P_EPLL_CON); + epll_con_k = __raw_readl(S5P_EPLL_CON1); + + epll_con_k &= ~PLL46XX_KDIV_MASK; + epll_con &= ~(1 << 27 | + PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | + PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | + PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); + + for (i = 0; i < ARRAY_SIZE(epll_div); i++) { + if (epll_div[i][0] == rate) { + epll_con_k |= epll_div[i][5] << 0; + epll_con |= (epll_div[i][1] << 27 | + epll_div[i][2] << PLL46XX_MDIV_SHIFT | + epll_div[i][3] << PLL46XX_PDIV_SHIFT | + epll_div[i][4] << PLL46XX_SDIV_SHIFT); + break; + } + } + + if (i == ARRAY_SIZE(epll_div)) { + printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", + __func__); + return -EINVAL; + } + + __raw_writel(epll_con, S5P_EPLL_CON); + __raw_writel(epll_con_k, S5P_EPLL_CON1); + + printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n", + clk->rate, rate); + + clk->rate = rate; + + return 0; +} + +static struct clk_ops s5pv210_epll_ops = { + .set_rate = s5pv210_epll_set_rate, + .get_rate = s5p_epll_get_rate, +}; + +static u32 vpll_div[][5] = { + { 54000000, 3, 53, 3, 0 }, + { 108000000, 3, 53, 2, 0 }, +}; + +static unsigned long s5pv210_vpll_get_rate(struct clk *clk) +{ + return clk->rate; +} + +static int s5pv210_vpll_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int vpll_con; + unsigned int i; + + /* Return if nothing changed */ + if (clk->rate == rate) + return 0; + + vpll_con = __raw_readl(S5P_VPLL_CON); + vpll_con &= ~(0x1 << 27 | \ + PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT | \ + PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT | \ + PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT); + + for (i = 0; i < ARRAY_SIZE(vpll_div); i++) { + if (vpll_div[i][0] == rate) { + vpll_con |= vpll_div[i][1] << PLL90XX_PDIV_SHIFT; + vpll_con |= vpll_div[i][2] << PLL90XX_MDIV_SHIFT; + vpll_con |= vpll_div[i][3] << PLL90XX_SDIV_SHIFT; + vpll_con |= vpll_div[i][4] << 27; + break; + } + } + + if (i == ARRAY_SIZE(vpll_div)) { + printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n", + __func__); + return -EINVAL; + } + + __raw_writel(vpll_con, S5P_VPLL_CON); + + /* Wait for VPLL lock */ + while (!(__raw_readl(S5P_VPLL_CON) & (1 << PLL90XX_LOCKED_SHIFT))) + continue; + + clk->rate = rate; + return 0; +} +static struct clk_ops s5pv210_vpll_ops = { + .get_rate = s5pv210_vpll_get_rate, + .set_rate = s5pv210_vpll_set_rate, }; void __init_or_cpufreq s5pv210_setup_clocks(void) { struct clk *xtal_clk; - unsigned long xtal; unsigned long vpllsrc; unsigned long armclk; unsigned long hclk_msys; @@ -961,6 +1248,10 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) unsigned int ptr; u32 clkdiv0, clkdiv1; + /* Set functions for clk_fout_epll */ + clk_fout_epll.enable = s5p_epll_enable; + clk_fout_epll.ops = &s5pv210_epll_ops; + printk(KERN_DEBUG "%s: registering clocks\n", __func__); clkdiv0 = __raw_readl(S5P_CLK_DIV0); @@ -979,13 +1270,15 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); - epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); + epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON), + __raw_readl(S5P_EPLL_CON1), pll_4600); vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502); - clk_fout_apll.rate = apll; + clk_fout_apll.ops = &clk_fout_apll_ops; clk_fout_mpll.rate = mpll; clk_fout_epll.rate = epll; + clk_fout_vpll.ops = &s5pv210_vpll_ops; clk_fout_vpll.rate = vpll; printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", @@ -1022,31 +1315,51 @@ static struct clk *clks[] __initdata = { &clk_pcmcdclk2, }; +static struct clk_lookup s5pv210_clk_lookup[] = { + CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p), + CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk), + CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk), + CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk), + CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), + CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), + CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), + CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), + CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), + CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), + CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0), + CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1), +}; + void __init s5pv210_register_clocks(void) { - struct clk *clkp; - int ret; int ptr; - ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); - if (ret > 0) - printk(KERN_ERR "Failed to register %u clocks\n", ret); + s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) s3c_register_clksrc(sysclks[ptr], 1); + for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) + s3c_register_clksrc(sclk_tv[ptr], 1); + + for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++) + s3c_register_clksrc(clksrc_cdev[ptr], 1); + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); - clkp = init_clocks_disable; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - (clkp->enable)(clkp, 0); - } + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup)); + + s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); + for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++) + s3c_disable_clocks(clk_cdev[ptr], 1); - s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c new file mode 100644 index 00000000000..7024dcd0e40 --- /dev/null +++ b/arch/arm/mach-s5pv210/common.c @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Common Codes for S5PV210 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/device.h> +#include <clocksource/samsung_pwm.h> +#include <linux/platform_device.h> +#include <linux/sched.h> +#include <linux/dma-mapping.h> +#include <linux/serial_core.h> +#include <linux/serial_s3c.h> + +#include <asm/proc-fns.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <mach/map.h> +#include <mach/regs-clock.h> + +#include <plat/cpu.h> +#include <plat/clock.h> +#include <plat/devs.h> +#include <plat/sdhci.h> +#include <plat/adc-core.h> +#include <plat/ata-core.h> +#include <plat/fb-core.h> +#include <plat/fimc-core.h> +#include <plat/iic-core.h> +#include <plat/keypad-core.h> +#include <plat/pwm-core.h> +#include <plat/tv-core.h> +#include <plat/spi-core.h> + +#include "common.h" + +static const char name_s5pv210[] = "S5PV210/S5PC110"; + +static struct cpu_table cpu_ids[] __initdata = { + { + .idcode = S5PV210_CPU_ID, + .idmask = S5PV210_CPU_MASK, + .map_io = s5pv210_map_io, + .init_clocks = s5pv210_init_clocks, + .init_uarts = s5pv210_init_uarts, + .init = s5pv210_init, + .name = name_s5pv210, + }, +}; + +/* Initial IO mappings */ + +static struct map_desc s5pv210_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_CHIPID, + .pfn = __phys_to_pfn(S5PV210_PA_CHIPID), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_SYS, + .pfn = __phys_to_pfn(S5PV210_PA_SYSCON), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_TIMER, + .pfn = __phys_to_pfn(S5PV210_PA_TIMER), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_WATCHDOG, + .pfn = __phys_to_pfn(S5PV210_PA_WATCHDOG), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SROMC, + .pfn = __phys_to_pfn(S5PV210_PA_SROMC), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SYSTIMER, + .pfn = __phys_to_pfn(S5PV210_PA_SYSTIMER), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_GPIO, + .pfn = __phys_to_pfn(S5PV210_PA_GPIO), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)VA_VIC0, + .pfn = __phys_to_pfn(S5PV210_PA_VIC0), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)VA_VIC1, + .pfn = __phys_to_pfn(S5PV210_PA_VIC1), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)VA_VIC2, + .pfn = __phys_to_pfn(S5PV210_PA_VIC2), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)VA_VIC3, + .pfn = __phys_to_pfn(S5PV210_PA_VIC3), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_UART, + .pfn = __phys_to_pfn(S3C_PA_UART), + .length = SZ_512K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_DMC0, + .pfn = __phys_to_pfn(S5PV210_PA_DMC0), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_DMC1, + .pfn = __phys_to_pfn(S5PV210_PA_DMC1), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_USB_HSPHY, + .pfn =__phys_to_pfn(S5PV210_PA_HSPHY), + .length = SZ_4K, + .type = MT_DEVICE, + } +}; + +void s5pv210_restart(enum reboot_mode mode, const char *cmd) +{ + __raw_writel(0x1, S5P_SWRESET); +} + +static struct samsung_pwm_variant s5pv210_pwm_variant = { + .bits = 32, + .div_base = 0, + .has_tint_cstat = true, + .tclk_mask = (1 << 5), +}; + +void __init samsung_set_timer_source(unsigned int event, unsigned int source) +{ + s5pv210_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; + s5pv210_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); +} + +void __init samsung_timer_init(void) +{ + unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { + IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, + IRQ_TIMER3_VIC, IRQ_TIMER4_VIC, + }; + + samsung_pwm_clocksource_init(S3C_VA_TIMER, + timer_irqs, &s5pv210_pwm_variant); +} + +/* + * s5pv210_map_io + * + * register the standard cpu IO areas + */ + +void __init s5pv210_init_io(struct map_desc *mach_desc, int size) +{ + /* initialize the io descriptors we need for initialization */ + iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc)); + if (mach_desc) + iotable_init(mach_desc, size); + + /* detect cpu id and rev. */ + s5p_init_cpu(S5P_VA_CHIPID); + + s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); + + samsung_pwm_set_platdata(&s5pv210_pwm_variant); +} + +void __init s5pv210_map_io(void) +{ + /* initialise device information early */ + s5pv210_default_sdhci0(); + s5pv210_default_sdhci1(); + s5pv210_default_sdhci2(); + s5pv210_default_sdhci3(); + + s3c_adc_setname("samsung-adc-v3"); + + s3c_cfcon_setname("s5pv210-pata"); + + s3c_fimc_setname(0, "s5pv210-fimc"); + s3c_fimc_setname(1, "s5pv210-fimc"); + s3c_fimc_setname(2, "s5pv210-fimc"); + + /* the i2c devices are directly compatible with s3c2440 */ + s3c_i2c0_setname("s3c2440-i2c"); + s3c_i2c1_setname("s3c2440-i2c"); + s3c_i2c2_setname("s3c2440-i2c"); + + s3c_fb_setname("s5pv210-fb"); + + /* Use s5pv210-keypad instead of samsung-keypad */ + samsung_keypad_setname("s5pv210-keypad"); + + /* setup TV devices */ + s5p_hdmi_setname("s5pv210-hdmi"); + + s3c64xx_spi_setname("s5pv210-spi"); +} + +void __init s5pv210_init_clocks(int xtal) +{ + printk(KERN_DEBUG "%s: initializing clocks\n", __func__); + + s3c24xx_register_baseclocks(xtal); + s5p_register_clocks(xtal); + s5pv210_register_clocks(); + s5pv210_setup_clocks(); +} + +void __init s5pv210_init_irq(void) +{ + u32 vic[4]; /* S5PV210 supports 4 VIC */ + + /* All the VICs are fully populated. */ + vic[0] = ~0; + vic[1] = ~0; + vic[2] = ~0; + vic[3] = ~0; + + s5p_init_irq(vic, ARRAY_SIZE(vic)); +} + +struct bus_type s5pv210_subsys = { + .name = "s5pv210-core", + .dev_name = "s5pv210-core", +}; + +static struct device s5pv210_dev = { + .bus = &s5pv210_subsys, +}; + +static int __init s5pv210_core_init(void) +{ + return subsys_system_register(&s5pv210_subsys, NULL); +} +core_initcall(s5pv210_core_init); + +int __init s5pv210_init(void) +{ + printk(KERN_INFO "S5PV210: Initializing architecture\n"); + return device_register(&s5pv210_dev); +} + +/* uart registration process */ + +void __init s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no) +{ + s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no); +} diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h new file mode 100644 index 00000000000..fe1beb54e54 --- /dev/null +++ b/arch/arm/mach-s5pv210/common.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Common Header for S5PV210 machines + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H +#define __ARCH_ARM_MACH_S5PV210_COMMON_H + +#include <linux/reboot.h> + +void s5pv210_init_io(struct map_desc *mach_desc, int size); +void s5pv210_init_irq(void); + +void s5pv210_register_clocks(void); +void s5pv210_setup_clocks(void); + +void s5pv210_restart(enum reboot_mode mode, const char *cmd); + +extern int s5pv210_init(void); +extern void s5pv210_map_io(void); +extern void s5pv210_init_clocks(int xtal); +extern void s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no); + +#endif /* __ARCH_ARM_MACH_S5PV210_COMMON_H */ diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c deleted file mode 100644 index 411a4a9cbfc..00000000000 --- a/arch/arm/mach-s5pv210/cpu.c +++ /dev/null @@ -1,142 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/cpu.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/module.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/sysdev.h> -#include <linux/platform_device.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <asm/proc-fns.h> -#include <mach/map.h> -#include <mach/regs-clock.h> - -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/clock.h> -#include <plat/s5pv210.h> -#include <plat/iic-core.h> -#include <plat/sdhci.h> - -/* Initial IO mappings */ - -static struct map_desc s5pv210_iodesc[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SYSTIMER, - .pfn = __phys_to_pfn(S5PV210_PA_SYSTIMER), - .length = SZ_1M, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)VA_VIC2, - .pfn = __phys_to_pfn(S5PV210_PA_VIC2), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)VA_VIC3, - .pfn = __phys_to_pfn(S5PV210_PA_VIC3), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_SROMC, - .pfn = __phys_to_pfn(S5PV210_PA_SROMC), - .length = SZ_4K, - .type = MT_DEVICE, - } -}; - -static void s5pv210_idle(void) -{ - if (!need_resched()) - cpu_do_idle(); - - local_irq_enable(); -} - -/* s5pv210_map_io - * - * register the standard cpu IO areas -*/ - -void __init s5pv210_map_io(void) -{ -#ifdef CONFIG_S3C_DEV_ADC - s3c_device_adc.name = "s3c64xx-adc"; -#endif - - iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc)); - - /* initialise device information early */ - s5pv210_default_sdhci0(); - s5pv210_default_sdhci1(); - s5pv210_default_sdhci2(); - - /* the i2c devices are directly compatible with s3c2440 */ - s3c_i2c0_setname("s3c2440-i2c"); - s3c_i2c1_setname("s3c2440-i2c"); - s3c_i2c2_setname("s3c2440-i2c"); -} - -void __init s5pv210_init_clocks(int xtal) -{ - printk(KERN_DEBUG "%s: initializing clocks\n", __func__); - - s3c24xx_register_baseclocks(xtal); - s5p_register_clocks(xtal); - s5pv210_register_clocks(); - s5pv210_setup_clocks(); -} - -void __init s5pv210_init_irq(void) -{ - u32 vic[4]; /* S5PV210 supports 4 VIC */ - - /* All the VICs are fully populated. */ - vic[0] = ~0; - vic[1] = ~0; - vic[2] = ~0; - vic[3] = ~0; - - s5p_init_irq(vic, ARRAY_SIZE(vic)); -} - -struct sysdev_class s5pv210_sysclass = { - .name = "s5pv210-core", -}; - -static struct sys_device s5pv210_sysdev = { - .cls = &s5pv210_sysclass, -}; - -static int __init s5pv210_core_init(void) -{ - return sysdev_class_register(&s5pv210_sysclass); -} - -core_initcall(s5pv210_core_init); - -int __init s5pv210_init(void) -{ - printk(KERN_INFO "S5PV210: Initializing architecture\n"); - - /* set idle function */ - pm_idle = s5pv210_idle; - - return sysdev_register(&s5pv210_sysdev); -} diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c index 6e215330a1b..2d67361ef43 100644 --- a/arch/arm/mach-s5pv210/dev-audio.c +++ b/arch/arm/mach-s5pv210/dev-audio.c @@ -10,45 +10,30 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/gpio.h> #include <plat/gpio-cfg.h> -#include <plat/audio.h> +#include <linux/platform_data/asoc-s3c.h> -#include <mach/gpio.h> #include <mach/map.h> #include <mach/dma.h> #include <mach/irqs.h> +#define S5PV210_AUDSS_INT_MEM (0xC0000000) + static int s5pv210_cfg_i2s(struct platform_device *pdev) { /* configure GPIO for i2s port */ switch (pdev->id) { + case 0: + s3c_gpio_cfgpin_range(S5PV210_GPI(0), 7, S3C_GPIO_SFN(2)); + break; case 1: - s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(2)); break; - case 2: - s3c_gpio_cfgpin(S5PV210_GPC1(0), S3C_GPIO_SFN(4)); - s3c_gpio_cfgpin(S5PV210_GPC1(1), S3C_GPIO_SFN(4)); - s3c_gpio_cfgpin(S5PV210_GPC1(2), S3C_GPIO_SFN(4)); - s3c_gpio_cfgpin(S5PV210_GPC1(3), S3C_GPIO_SFN(4)); - s3c_gpio_cfgpin(S5PV210_GPC1(4), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(4)); break; - - case -1: - s3c_gpio_cfgpin(S5PV210_GPI(0), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPI(1), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPI(2), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPI(3), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPI(4), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPI(5), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPI(6), S3C_GPIO_SFN(2)); - break; - default: printk(KERN_ERR "Invalid Device %d\n", pdev->id); return -EINVAL; @@ -57,91 +42,67 @@ static int s5pv210_cfg_i2s(struct platform_device *pdev) return 0; } -static struct s3c_audio_pdata s3c_i2s_pdata = { +static struct s3c_audio_pdata i2sv5_pdata = { .cfg_gpio = s5pv210_cfg_i2s, + .type = { + .i2s = { + .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI + | QUIRK_NEED_RSTCLR, + .idma_addr = S5PV210_AUDSS_INT_MEM, + }, + }, }; static struct resource s5pv210_iis0_resource[] = { - [0] = { - .start = S5PV210_PA_IIS0, - .end = S5PV210_PA_IIS0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S0_TX, - .end = DMACH_I2S0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S0_RX, - .end = DMACH_I2S0_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PV210_PA_IIS0, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S0_TX), + [2] = DEFINE_RES_DMA(DMACH_I2S0_RX), + [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX), }; struct platform_device s5pv210_device_iis0 = { - .name = "s3c64xx-iis-v4", - .id = -1, + .name = "samsung-i2s", + .id = 0, .num_resources = ARRAY_SIZE(s5pv210_iis0_resource), .resource = s5pv210_iis0_resource, .dev = { - .platform_data = &s3c_i2s_pdata, + .platform_data = &i2sv5_pdata, }, }; +static struct s3c_audio_pdata i2sv3_pdata = { + .cfg_gpio = s5pv210_cfg_i2s, +}; + static struct resource s5pv210_iis1_resource[] = { - [0] = { - .start = S5PV210_PA_IIS1, - .end = S5PV210_PA_IIS1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S1_TX, - .end = DMACH_I2S1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S1_RX, - .end = DMACH_I2S1_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PV210_PA_IIS1, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S1_TX), + [2] = DEFINE_RES_DMA(DMACH_I2S1_RX), }; struct platform_device s5pv210_device_iis1 = { - .name = "s3c64xx-iis", + .name = "samsung-i2s", .id = 1, .num_resources = ARRAY_SIZE(s5pv210_iis1_resource), .resource = s5pv210_iis1_resource, .dev = { - .platform_data = &s3c_i2s_pdata, + .platform_data = &i2sv3_pdata, }, }; static struct resource s5pv210_iis2_resource[] = { - [0] = { - .start = S5PV210_PA_IIS2, - .end = S5PV210_PA_IIS2 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S2_TX, - .end = DMACH_I2S2_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S2_RX, - .end = DMACH_I2S2_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PV210_PA_IIS2, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S2_TX), + [2] = DEFINE_RES_DMA(DMACH_I2S2_RX), }; struct platform_device s5pv210_device_iis2 = { - .name = "s3c64xx-iis", + .name = "samsung-i2s", .id = 2, .num_resources = ARRAY_SIZE(s5pv210_iis2_resource), .resource = s5pv210_iis2_resource, .dev = { - .platform_data = &s3c_i2s_pdata, + .platform_data = &i2sv3_pdata, }, }; @@ -151,25 +112,13 @@ static int s5pv210_pcm_cfg_gpio(struct platform_device *pdev) { switch (pdev->id) { case 0: - s3c_gpio_cfgpin(S5PV210_GPI(0), S3C_GPIO_SFN(3)); - s3c_gpio_cfgpin(S5PV210_GPI(1), S3C_GPIO_SFN(3)); - s3c_gpio_cfgpin(S5PV210_GPI(2), S3C_GPIO_SFN(3)); - s3c_gpio_cfgpin(S5PV210_GPI(3), S3C_GPIO_SFN(3)); - s3c_gpio_cfgpin(S5PV210_GPI(4), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin_range(S5PV210_GPI(0), 5, S3C_GPIO_SFN(3)); break; case 1: - s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(3)); - s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(3)); - s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(3)); - s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(3)); - s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(3)); break; case 2: - s3c_gpio_cfgpin(S5PV210_GPC1(0), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPC1(1), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPC1(2), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPC1(3), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPC1(4), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(2)); break; default: printk(KERN_DEBUG "Invalid PCM Controller number!"); @@ -184,21 +133,9 @@ static struct s3c_audio_pdata s3c_pcm_pdata = { }; static struct resource s5pv210_pcm0_resource[] = { - [0] = { - .start = S5PV210_PA_PCM0, - .end = S5PV210_PA_PCM0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM0_TX, - .end = DMACH_PCM0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM0_RX, - .end = DMACH_PCM0_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PV210_PA_PCM0, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_PCM0_TX), + [2] = DEFINE_RES_DMA(DMACH_PCM0_RX), }; struct platform_device s5pv210_device_pcm0 = { @@ -212,21 +149,9 @@ struct platform_device s5pv210_device_pcm0 = { }; static struct resource s5pv210_pcm1_resource[] = { - [0] = { - .start = S5PV210_PA_PCM1, - .end = S5PV210_PA_PCM1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM1_TX, - .end = DMACH_PCM1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM1_RX, - .end = DMACH_PCM1_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PV210_PA_PCM1, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_PCM1_TX), + [2] = DEFINE_RES_DMA(DMACH_PCM1_RX), }; struct platform_device s5pv210_device_pcm1 = { @@ -240,21 +165,9 @@ struct platform_device s5pv210_device_pcm1 = { }; static struct resource s5pv210_pcm2_resource[] = { - [0] = { - .start = S5PV210_PA_PCM2, - .end = S5PV210_PA_PCM2 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM2_TX, - .end = DMACH_PCM2_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM2_RX, - .end = DMACH_PCM2_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PV210_PA_PCM2, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_PCM2_TX), + [2] = DEFINE_RES_DMA(DMACH_PCM2_RX), }; struct platform_device s5pv210_device_pcm2 = { @@ -271,41 +184,15 @@ struct platform_device s5pv210_device_pcm2 = { static int s5pv210_ac97_cfg_gpio(struct platform_device *pdev) { - s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(4)); - s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(4)); - s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(4)); - s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(4)); - s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(4)); - - return 0; + return s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(4)); } static struct resource s5pv210_ac97_resource[] = { - [0] = { - .start = S5PV210_PA_AC97, - .end = S5PV210_PA_AC97 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_AC97_PCMOUT, - .end = DMACH_AC97_PCMOUT, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_AC97_PCMIN, - .end = DMACH_AC97_PCMIN, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = DMACH_AC97_MICIN, - .end = DMACH_AC97_MICIN, - .flags = IORESOURCE_DMA, - }, - [4] = { - .start = IRQ_AC97, - .end = IRQ_AC97, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(S5PV210_PA_AC97, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT), + [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN), + [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN), + [4] = DEFINE_RES_IRQ(IRQ_AC97), }; static struct s3c_audio_pdata s3c_ac97_pdata = { @@ -315,7 +202,7 @@ static struct s3c_audio_pdata s3c_ac97_pdata = { static u64 s5pv210_ac97_dmamask = DMA_BIT_MASK(32); struct platform_device s5pv210_device_ac97 = { - .name = "s3c-ac97", + .name = "samsung-ac97", .id = -1, .num_resources = ARRAY_SIZE(s5pv210_ac97_resource), .resource = s5pv210_ac97_resource, @@ -325,3 +212,35 @@ struct platform_device s5pv210_device_ac97 = { .coherent_dma_mask = DMA_BIT_MASK(32), }, }; + +/* S/PDIF Controller platform_device */ + +static int s5pv210_spdif_cfg_gpio(struct platform_device *pdev) +{ + s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 2, S3C_GPIO_SFN(3)); + + return 0; +} + +static struct resource s5pv210_spdif_resource[] = { + [0] = DEFINE_RES_MEM(S5PV210_PA_SPDIF, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_SPDIF), +}; + +static struct s3c_audio_pdata samsung_spdif_pdata = { + .cfg_gpio = s5pv210_spdif_cfg_gpio, +}; + +static u64 s5pv210_spdif_dmamask = DMA_BIT_MASK(32); + +struct platform_device s5pv210_device_spdif = { + .name = "samsung-spdif", + .id = -1, + .num_resources = ARRAY_SIZE(s5pv210_spdif_resource), + .resource = s5pv210_spdif_resource, + .dev = { + .platform_data = &samsung_spdif_pdata, + .dma_mask = &s5pv210_spdif_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; diff --git a/arch/arm/mach-s5pv210/dev-onenand.c b/arch/arm/mach-s5pv210/dev-onenand.c deleted file mode 100644 index 34997b752f9..00000000000 --- a/arch/arm/mach-s5pv210/dev-onenand.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * linux/arch/arm/mach-s5pv210/dev-onenand.c - * - * Copyright (c) 2008-2010 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * S5PC110 series device definition for OneNAND devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/onenand.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -static struct resource s5pc110_onenand_resources[] = { - [0] = { - .start = S5PC110_PA_ONENAND, - .end = S5PC110_PA_ONENAND + SZ_128K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = S5PC110_PA_ONENAND_DMA, - .end = S5PC110_PA_ONENAND_DMA + SZ_2K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device s5pc110_device_onenand = { - .name = "s5pc110-onenand", - .id = -1, - .num_resources = ARRAY_SIZE(s5pc110_onenand_resources), - .resource = s5pc110_onenand_resources, -}; - -void s5pc110_onenand_set_platdata(struct onenand_platform_data *pdata) -{ - struct onenand_platform_data *pd; - - pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL); - if (!pd) - printk(KERN_ERR "%s: no memory for platform data\n", __func__); - s5pc110_device_onenand.dev.platform_data = pd; -} diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c deleted file mode 100644 index 337a62b57a0..00000000000 --- a/arch/arm/mach-s5pv210/dev-spi.c +++ /dev/null @@ -1,178 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/dev-spi.c - * - * Copyright (C) 2010 Samsung Electronics Co. Ltd. - * Jaswinder Singh <jassi.brar@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> - -#include <mach/dma.h> -#include <mach/map.h> -#include <mach/irqs.h> -#include <mach/gpio.h> -#include <mach/spi-clocks.h> - -#include <plat/s3c64xx-spi.h> -#include <plat/gpio-cfg.h> - -static char *spi_src_clks[] = { - [S5PV210_SPI_SRCCLK_PCLK] = "pclk", - [S5PV210_SPI_SRCCLK_SCLK] = "sclk_spi", -}; - -/* SPI Controller platform_devices */ - -/* Since we emulate multi-cs capability, we do not touch the CS. - * The emulated CS is toggled by board specific mechanism, as it can - * be either some immediate GPIO or some signal out of some other - * chip in between ... or some yet another way. - * We simply do not assume anything about CS. - */ -static int s5pv210_spi_cfg_gpio(struct platform_device *pdev) -{ - switch (pdev->id) { - case 0: - s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPB(1), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPB(2), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5PV210_GPB(1), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5PV210_GPB(2), S3C_GPIO_PULL_UP); - break; - - case 1: - s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPB(5), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PV210_GPB(6), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5PV210_GPB(5), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5PV210_GPB(6), S3C_GPIO_PULL_UP); - break; - - default: - dev_err(&pdev->dev, "Invalid SPI Controller number!"); - return -EINVAL; - } - - return 0; -} - -static struct resource s5pv210_spi0_resource[] = { - [0] = { - .start = S5PV210_PA_SPI0, - .end = S5PV210_PA_SPI0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_SPI0_TX, - .end = DMACH_SPI0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_SPI0_RX, - .end = DMACH_SPI0_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = IRQ_SPI0, - .end = IRQ_SPI0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct s3c64xx_spi_info s5pv210_spi0_pdata = { - .cfg_gpio = s5pv210_spi_cfg_gpio, - .fifo_lvl_mask = 0x1ff, - .rx_lvl_offset = 15, - .high_speed = 1, -}; - -static u64 spi_dmamask = DMA_BIT_MASK(32); - -struct platform_device s5pv210_device_spi0 = { - .name = "s3c64xx-spi", - .id = 0, - .num_resources = ARRAY_SIZE(s5pv210_spi0_resource), - .resource = s5pv210_spi0_resource, - .dev = { - .dma_mask = &spi_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &s5pv210_spi0_pdata, - }, -}; - -static struct resource s5pv210_spi1_resource[] = { - [0] = { - .start = S5PV210_PA_SPI1, - .end = S5PV210_PA_SPI1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_SPI1_TX, - .end = DMACH_SPI1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_SPI1_RX, - .end = DMACH_SPI1_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = IRQ_SPI1, - .end = IRQ_SPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct s3c64xx_spi_info s5pv210_spi1_pdata = { - .cfg_gpio = s5pv210_spi_cfg_gpio, - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 15, - .high_speed = 1, -}; - -struct platform_device s5pv210_device_spi1 = { - .name = "s3c64xx-spi", - .id = 1, - .num_resources = ARRAY_SIZE(s5pv210_spi1_resource), - .resource = s5pv210_spi1_resource, - .dev = { - .dma_mask = &spi_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &s5pv210_spi1_pdata, - }, -}; - -void __init s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) -{ - struct s3c64xx_spi_info *pd; - - /* Reject invalid configuration */ - if (!num_cs || src_clk_nr < 0 - || src_clk_nr > S5PV210_SPI_SRCCLK_SCLK) { - printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); - return; - } - - switch (cntrlr) { - case 0: - pd = &s5pv210_spi0_pdata; - break; - case 1: - pd = &s5pv210_spi1_pdata; - break; - default: - printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", - __func__, cntrlr); - return; - } - - pd->num_cs = num_cs; - pd->src_clk_nr = src_clk_nr; - pd->src_clk_name = spi_src_clks[src_clk_nr]; -} diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c index 778ad5fe231..b8337e248b0 100644 --- a/arch/arm/mach-s5pv210/dma.c +++ b/arch/arm/mach-s5pv210/dma.c @@ -1,4 +1,8 @@ -/* +/* linux/arch/arm/mach-s5pv210/dma.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * * Copyright (C) 2010 Samsung Electronics Co. Ltd. * Jaswinder Singh <jassi.brar@samsung.com> * @@ -17,151 +21,109 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/amba/bus.h> +#include <linux/amba/pl330.h> +#include <asm/irq.h> #include <plat/devs.h> #include <plat/irqs.h> #include <mach/map.h> #include <mach/irqs.h> +#include <mach/dma.h> -#include <plat/s3c-pl330-pdata.h> - -static u64 dma_dmamask = DMA_BIT_MASK(32); - -static struct resource s5pv210_pdma0_resource[] = { - [0] = { - .start = S5PV210_PA_PDMA0, - .end = S5PV210_PA_PDMA0 + SZ_4K, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_PDMA0, - .end = IRQ_PDMA0, - .flags = IORESOURCE_IRQ, - }, +static u8 pdma0_peri[] = { + DMACH_UART0_RX, + DMACH_UART0_TX, + DMACH_UART1_RX, + DMACH_UART1_TX, + DMACH_UART2_RX, + DMACH_UART2_TX, + DMACH_UART3_RX, + DMACH_UART3_TX, + DMACH_MAX, + DMACH_I2S0_RX, + DMACH_I2S0_TX, + DMACH_I2S0S_TX, + DMACH_I2S1_RX, + DMACH_I2S1_TX, + DMACH_MAX, + DMACH_MAX, + DMACH_SPI0_RX, + DMACH_SPI0_TX, + DMACH_SPI1_RX, + DMACH_SPI1_TX, + DMACH_MAX, + DMACH_MAX, + DMACH_AC97_MICIN, + DMACH_AC97_PCMIN, + DMACH_AC97_PCMOUT, + DMACH_MAX, + DMACH_PWM, + DMACH_SPDIF, }; -static struct s3c_pl330_platdata s5pv210_pdma0_pdata = { - .peri = { - [0] = DMACH_UART0_RX, - [1] = DMACH_UART0_TX, - [2] = DMACH_UART1_RX, - [3] = DMACH_UART1_TX, - [4] = DMACH_UART2_RX, - [5] = DMACH_UART2_TX, - [6] = DMACH_UART3_RX, - [7] = DMACH_UART3_TX, - [8] = DMACH_MAX, - [9] = DMACH_I2S0_RX, - [10] = DMACH_I2S0_TX, - [11] = DMACH_I2S0S_TX, - [12] = DMACH_I2S1_RX, - [13] = DMACH_I2S1_TX, - [14] = DMACH_MAX, - [15] = DMACH_MAX, - [16] = DMACH_SPI0_RX, - [17] = DMACH_SPI0_TX, - [18] = DMACH_SPI1_RX, - [19] = DMACH_SPI1_TX, - [20] = DMACH_MAX, - [21] = DMACH_MAX, - [22] = DMACH_AC97_MICIN, - [23] = DMACH_AC97_PCMIN, - [24] = DMACH_AC97_PCMOUT, - [25] = DMACH_MAX, - [26] = DMACH_PWM, - [27] = DMACH_SPDIF, - [28] = DMACH_MAX, - [29] = DMACH_MAX, - [30] = DMACH_MAX, - [31] = DMACH_MAX, - }, +static struct dma_pl330_platdata s5pv210_pdma0_pdata = { + .nr_valid_peri = ARRAY_SIZE(pdma0_peri), + .peri_id = pdma0_peri, }; -static struct platform_device s5pv210_device_pdma0 = { - .name = "s3c-pl330", - .id = 1, - .num_resources = ARRAY_SIZE(s5pv210_pdma0_resource), - .resource = s5pv210_pdma0_resource, - .dev = { - .dma_mask = &dma_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &s5pv210_pdma0_pdata, - }, -}; +static AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330, + S5PV210_PA_PDMA0, {IRQ_PDMA0}, &s5pv210_pdma0_pdata); -static struct resource s5pv210_pdma1_resource[] = { - [0] = { - .start = S5PV210_PA_PDMA1, - .end = S5PV210_PA_PDMA1 + SZ_4K, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_PDMA1, - .end = IRQ_PDMA1, - .flags = IORESOURCE_IRQ, - }, +static u8 pdma1_peri[] = { + DMACH_UART0_RX, + DMACH_UART0_TX, + DMACH_UART1_RX, + DMACH_UART1_TX, + DMACH_UART2_RX, + DMACH_UART2_TX, + DMACH_UART3_RX, + DMACH_UART3_TX, + DMACH_MAX, + DMACH_I2S0_RX, + DMACH_I2S0_TX, + DMACH_I2S0S_TX, + DMACH_I2S1_RX, + DMACH_I2S1_TX, + DMACH_I2S2_RX, + DMACH_I2S2_TX, + DMACH_SPI0_RX, + DMACH_SPI0_TX, + DMACH_SPI1_RX, + DMACH_SPI1_TX, + DMACH_MAX, + DMACH_MAX, + DMACH_PCM0_RX, + DMACH_PCM0_TX, + DMACH_PCM1_RX, + DMACH_PCM1_TX, + DMACH_MSM_REQ0, + DMACH_MSM_REQ1, + DMACH_MSM_REQ2, + DMACH_MSM_REQ3, + DMACH_PCM2_RX, + DMACH_PCM2_TX, }; -static struct s3c_pl330_platdata s5pv210_pdma1_pdata = { - .peri = { - [0] = DMACH_UART0_RX, - [1] = DMACH_UART0_TX, - [2] = DMACH_UART1_RX, - [3] = DMACH_UART1_TX, - [4] = DMACH_UART2_RX, - [5] = DMACH_UART2_TX, - [6] = DMACH_UART3_RX, - [7] = DMACH_UART3_TX, - [8] = DMACH_MAX, - [9] = DMACH_I2S0_RX, - [10] = DMACH_I2S0_TX, - [11] = DMACH_I2S0S_TX, - [12] = DMACH_I2S1_RX, - [13] = DMACH_I2S1_TX, - [14] = DMACH_I2S2_RX, - [15] = DMACH_I2S2_TX, - [16] = DMACH_SPI0_RX, - [17] = DMACH_SPI0_TX, - [18] = DMACH_SPI1_RX, - [19] = DMACH_SPI1_TX, - [20] = DMACH_MAX, - [21] = DMACH_MAX, - [22] = DMACH_PCM0_RX, - [23] = DMACH_PCM0_TX, - [24] = DMACH_PCM1_RX, - [25] = DMACH_PCM1_TX, - [26] = DMACH_MSM_REQ0, - [27] = DMACH_MSM_REQ1, - [28] = DMACH_MSM_REQ2, - [29] = DMACH_MSM_REQ3, - [30] = DMACH_PCM2_RX, - [31] = DMACH_PCM2_TX, - }, +static struct dma_pl330_platdata s5pv210_pdma1_pdata = { + .nr_valid_peri = ARRAY_SIZE(pdma1_peri), + .peri_id = pdma1_peri, }; -static struct platform_device s5pv210_device_pdma1 = { - .name = "s3c-pl330", - .id = 2, - .num_resources = ARRAY_SIZE(s5pv210_pdma1_resource), - .resource = s5pv210_pdma1_resource, - .dev = { - .dma_mask = &dma_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &s5pv210_pdma1_pdata, - }, -}; - -static struct platform_device *s5pv210_dmacs[] __initdata = { - &s5pv210_device_pdma0, - &s5pv210_device_pdma1, -}; +static AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330, + S5PV210_PA_PDMA1, {IRQ_PDMA1}, &s5pv210_pdma1_pdata); static int __init s5pv210_dma_init(void) { - platform_add_devices(s5pv210_dmacs, ARRAY_SIZE(s5pv210_dmacs)); + dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask); + dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask); + amba_device_register(&s5pv210_pdma0_device, &iomem_resource); + + dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask); + dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask); + amba_device_register(&s5pv210_pdma1_device, &iomem_resource); return 0; } diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c deleted file mode 100644 index 9ea8972e023..00000000000 --- a/arch/arm/mach-s5pv210/gpiolib.c +++ /dev/null @@ -1,261 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/gpiolib.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5PV210 - GPIOlib support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> -#include <mach/map.h> - -static struct s3c_gpio_cfg gpio_cfg = { - .set_config = s3c_gpio_setcfg_s3c64xx_4bit, - .set_pull = s3c_gpio_setpull_updown, - .get_pull = s3c_gpio_getpull_updown, -}; - -static struct s3c_gpio_cfg gpio_cfg_noint = { - .set_config = s3c_gpio_setcfg_s3c64xx_4bit, - .set_pull = s3c_gpio_setpull_updown, - .get_pull = s3c_gpio_getpull_updown, -}; - -/* GPIO bank's base address given the index of the bank in the - * list of all gpio banks. - */ -#define S5PV210_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20)) - -/* - * Following are the gpio banks in v210. - * - * The 'config' member when left to NULL, is initialized to the default - * structure gpio_cfg in the init function below. - * - * The 'base' member is also initialized in the init function below. - * Note: The initialization of 'base' member of s3c_gpio_chip structure - * uses the above macro and depends on the banks being listed in order here. - */ -static struct s3c_gpio_chip s5pv210_gpio_4bit[] = { - { - .chip = { - .base = S5PV210_GPA0(0), - .ngpio = S5PV210_GPIO_A0_NR, - .label = "GPA0", - }, - }, { - .chip = { - .base = S5PV210_GPA1(0), - .ngpio = S5PV210_GPIO_A1_NR, - .label = "GPA1", - }, - }, { - .chip = { - .base = S5PV210_GPB(0), - .ngpio = S5PV210_GPIO_B_NR, - .label = "GPB", - }, - }, { - .chip = { - .base = S5PV210_GPC0(0), - .ngpio = S5PV210_GPIO_C0_NR, - .label = "GPC0", - }, - }, { - .chip = { - .base = S5PV210_GPC1(0), - .ngpio = S5PV210_GPIO_C1_NR, - .label = "GPC1", - }, - }, { - .chip = { - .base = S5PV210_GPD0(0), - .ngpio = S5PV210_GPIO_D0_NR, - .label = "GPD0", - }, - }, { - .chip = { - .base = S5PV210_GPD1(0), - .ngpio = S5PV210_GPIO_D1_NR, - .label = "GPD1", - }, - }, { - .chip = { - .base = S5PV210_GPE0(0), - .ngpio = S5PV210_GPIO_E0_NR, - .label = "GPE0", - }, - }, { - .chip = { - .base = S5PV210_GPE1(0), - .ngpio = S5PV210_GPIO_E1_NR, - .label = "GPE1", - }, - }, { - .chip = { - .base = S5PV210_GPF0(0), - .ngpio = S5PV210_GPIO_F0_NR, - .label = "GPF0", - }, - }, { - .chip = { - .base = S5PV210_GPF1(0), - .ngpio = S5PV210_GPIO_F1_NR, - .label = "GPF1", - }, - }, { - .chip = { - .base = S5PV210_GPF2(0), - .ngpio = S5PV210_GPIO_F2_NR, - .label = "GPF2", - }, - }, { - .chip = { - .base = S5PV210_GPF3(0), - .ngpio = S5PV210_GPIO_F3_NR, - .label = "GPF3", - }, - }, { - .chip = { - .base = S5PV210_GPG0(0), - .ngpio = S5PV210_GPIO_G0_NR, - .label = "GPG0", - }, - }, { - .chip = { - .base = S5PV210_GPG1(0), - .ngpio = S5PV210_GPIO_G1_NR, - .label = "GPG1", - }, - }, { - .chip = { - .base = S5PV210_GPG2(0), - .ngpio = S5PV210_GPIO_G2_NR, - .label = "GPG2", - }, - }, { - .chip = { - .base = S5PV210_GPG3(0), - .ngpio = S5PV210_GPIO_G3_NR, - .label = "GPG3", - }, - }, { - .chip = { - .base = S5PV210_GPI(0), - .ngpio = S5PV210_GPIO_I_NR, - .label = "GPI", - }, - }, { - .chip = { - .base = S5PV210_GPJ0(0), - .ngpio = S5PV210_GPIO_J0_NR, - .label = "GPJ0", - }, - }, { - .chip = { - .base = S5PV210_GPJ1(0), - .ngpio = S5PV210_GPIO_J1_NR, - .label = "GPJ1", - }, - }, { - .chip = { - .base = S5PV210_GPJ2(0), - .ngpio = S5PV210_GPIO_J2_NR, - .label = "GPJ2", - }, - }, { - .chip = { - .base = S5PV210_GPJ3(0), - .ngpio = S5PV210_GPIO_J3_NR, - .label = "GPJ3", - }, - }, { - .chip = { - .base = S5PV210_GPJ4(0), - .ngpio = S5PV210_GPIO_J4_NR, - .label = "GPJ4", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PV210_MP01(0), - .ngpio = S5PV210_GPIO_MP01_NR, - .label = "MP01", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PV210_MP02(0), - .ngpio = S5PV210_GPIO_MP02_NR, - .label = "MP02", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PV210_MP03(0), - .ngpio = S5PV210_GPIO_MP03_NR, - .label = "MP03", - }, - }, { - .base = (S5P_VA_GPIO + 0xC00), - .config = &gpio_cfg_noint, - .chip = { - .base = S5PV210_GPH0(0), - .ngpio = S5PV210_GPIO_H0_NR, - .label = "GPH0", - }, - }, { - .base = (S5P_VA_GPIO + 0xC20), - .config = &gpio_cfg_noint, - .chip = { - .base = S5PV210_GPH1(0), - .ngpio = S5PV210_GPIO_H1_NR, - .label = "GPH1", - }, - }, { - .base = (S5P_VA_GPIO + 0xC40), - .config = &gpio_cfg_noint, - .chip = { - .base = S5PV210_GPH2(0), - .ngpio = S5PV210_GPIO_H2_NR, - .label = "GPH2", - }, - }, { - .base = (S5P_VA_GPIO + 0xC60), - .config = &gpio_cfg_noint, - .chip = { - .base = S5PV210_GPH3(0), - .ngpio = S5PV210_GPIO_H3_NR, - .label = "GPH3", - }, - }, -}; - -static __init int s5pv210_gpiolib_init(void) -{ - struct s3c_gpio_chip *chip = s5pv210_gpio_4bit; - int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit); - int i = 0; - - for (i = 0; i < nr_chips; i++, chip++) { - if (chip->config == NULL) - chip->config = &gpio_cfg; - if (chip->base == NULL) - chip->base = S5PV210_BANK_BASE(i); - } - - samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips); - - return 0; -} -core_initcall(s5pv210_gpiolib_init); diff --git a/arch/arm/mach-s5pv210/include/mach/debug-macro.S b/arch/arm/mach-s5pv210/include/mach/debug-macro.S index 7872f5c3dfc..30b511a580a 100644 --- a/arch/arm/mach-s5pv210/include/mach/debug-macro.S +++ b/arch/arm/mach-s5pv210/include/mach/debug-macro.S @@ -12,8 +12,8 @@ /* pull in the relevant register and map files. */ +#include <linux/serial_s3c.h> #include <mach/map.h> -#include <plat/regs-serial.h> /* note, for the boot process to work we have to keep the UART * virtual address aligned to an 1MiB boundary for the L1 @@ -21,13 +21,12 @@ * aligned and add in the offset when we load the value here. */ - .macro addruart, rx, tmp - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 - ldreq \rx, = S3C_PA_UART - ldrne \rx, = S3C_VA_UART + .macro addruart, rp, rv, tmp + ldr \rp, = S3C_PA_UART + ldr \rv, = S3C_VA_UART #if CONFIG_DEBUG_S3C_UART != 0 - add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) + add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART) + add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART) #endif .endm @@ -39,4 +38,4 @@ * will be fine with us. */ -#include <plat/debug-macro.S> +#include <debug/samsung.S> diff --git a/arch/arm/mach-s5pv210/include/mach/dma.h b/arch/arm/mach-s5pv210/include/mach/dma.h index 81209eb1409..201842a3769 100644 --- a/arch/arm/mach-s5pv210/include/mach/dma.h +++ b/arch/arm/mach-s5pv210/include/mach/dma.h @@ -20,7 +20,7 @@ #ifndef __MACH_DMA_H #define __MACH_DMA_H -/* This platform uses the common S3C DMA API driver for PL330 */ -#include <plat/s3c-dma-pl330.h> +/* This platform uses the common DMA API driver for PL330 */ +#include <plat/dma-pl330.h> #endif /* __MACH_DMA_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/entry-macro.S b/arch/arm/mach-s5pv210/include/mach/entry-macro.S deleted file mode 100644 index 3aa41ac59f0..00000000000 --- a/arch/arm/mach-s5pv210/include/mach/entry-macro.S +++ /dev/null @@ -1,54 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/include/mach/entry-macro.S - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Low-level IRQ helper macros for the Samsung S5PV210 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <asm/hardware/vic.h> -#include <mach/map.h> -#include <plat/irqs.h> - - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - ldr \base, =VA_VIC0 - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - @ check the vic0 - mov \irqnr, # S5P_IRQ_OFFSET + 31 - ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] - teq \irqstat, #0 - - @ otherwise try vic1 - addeq \tmp, \base, #(VA_VIC1 - VA_VIC0) - addeq \irqnr, \irqnr, #32 - ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] - teqeq \irqstat, #0 - - @ otherwise try vic2 - addeq \tmp, \base, #(VA_VIC2 - VA_VIC0) - addeq \irqnr, \irqnr, #32 - ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] - teqeq \irqstat, #0 - - @ otherwise try vic3 - addeq \tmp, \base, #(VA_VIC3 - VA_VIC0) - addeq \irqnr, \irqnr, #32 - ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] - teqeq \irqstat, #0 - - clzne \irqstat, \irqstat - subne \irqnr, \irqnr, \irqstat - .endm diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h index d6461ba2b71..6c8b903c02e 100644 --- a/arch/arm/mach-s5pv210/include/mach/gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/gpio.h @@ -13,12 +13,7 @@ #ifndef __ASM_ARCH_GPIO_H #define __ASM_ARCH_GPIO_H __FILE__ -#define gpio_get_value __gpio_get_value -#define gpio_set_value __gpio_set_value -#define gpio_cansleep __gpio_cansleep -#define gpio_to_irq __gpio_to_irq - -/* Practically, GPIO banks upto MP03 are the configurable gpio banks */ +/* Practically, GPIO banks up to MP03 are the configurable gpio banks */ /* GPIO bank sizes */ #define S5PV210_GPIO_A0_NR (8) @@ -52,6 +47,8 @@ #define S5PV210_GPIO_MP01_NR (8) #define S5PV210_GPIO_MP02_NR (4) #define S5PV210_GPIO_MP03_NR (8) +#define S5PV210_GPIO_MP04_NR (8) +#define S5PV210_GPIO_MP05_NR (8) /* GPIO bank numbers */ @@ -94,6 +91,8 @@ enum s5p_gpio_number { S5PV210_GPIO_MP01_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J4), S5PV210_GPIO_MP02_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01), S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02), + S5PV210_GPIO_MP04_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP03), + S5PV210_GPIO_MP05_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP04), }; /* S5PV210 GPIO number definitions */ @@ -127,15 +126,15 @@ enum s5p_gpio_number { #define S5PV210_MP01(_nr) (S5PV210_GPIO_MP01_START + (_nr)) #define S5PV210_MP02(_nr) (S5PV210_GPIO_MP02_START + (_nr)) #define S5PV210_MP03(_nr) (S5PV210_GPIO_MP03_START + (_nr)) +#define S5PV210_MP04(_nr) (S5PV210_GPIO_MP04_START + (_nr)) +#define S5PV210_MP05(_nr) (S5PV210_GPIO_MP05_START + (_nr)) /* the end of the S5PV210 specific gpios */ -#define S5PV210_GPIO_END (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + 1) +#define S5PV210_GPIO_END (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + 1) #define S3C_GPIO_END S5PV210_GPIO_END -/* define the number of gpios we need to the one after the MP03() range */ -#define ARCH_NR_GPIOS (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + \ +/* define the number of gpios we need to the one after the MP05() range */ +#define ARCH_NR_GPIOS (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + \ CONFIG_SAMSUNG_GPIO_EXTRA + 1) -#include <asm-generic/gpio.h> - #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/io.h b/arch/arm/mach-s5pv210/include/mach/io.h deleted file mode 100644 index 5ab9d560bc8..00000000000 --- a/arch/arm/mach-s5pv210/include/mach/io.h +++ /dev/null @@ -1,26 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/include/mach/io.h - * - * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org> - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Based on arch/arm/mach-s5p6442/include/mach/io.h - * - * Default IO routines for S5PV210 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H __FILE__ - -/* No current ISA/PCI bus support. */ -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) - -#define IO_SPACE_LIMIT (0xFFFFFFFF) - -#endif /* __ASM_ARM_ARCH_IO_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index 96895378ea2..5e0de3a31f3 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -36,7 +36,7 @@ /* VIC1: ARM, Power, Memory, Connectivity, Storage */ -#define IRQ_CORTEX0 S5P_IRQ_VIC1(0) +#define IRQ_PMU S5P_IRQ_VIC1(0) #define IRQ_CORTEX1 S5P_IRQ_VIC1(1) #define IRQ_CORTEX2 S5P_IRQ_VIC1(2) #define IRQ_CORTEX3 S5P_IRQ_VIC1(3) @@ -45,7 +45,7 @@ #define IRQ_IEMIEC S5P_IRQ_VIC1(6) #define IRQ_ONENAND S5P_IRQ_VIC1(7) #define IRQ_NFC S5P_IRQ_VIC1(8) -#define IRQ_CFC S5P_IRQ_VIC1(9) +#define IRQ_CFCON S5P_IRQ_VIC1(9) #define IRQ_UART0 S5P_IRQ_VIC1(10) #define IRQ_UART1 S5P_IRQ_VIC1(11) #define IRQ_UART2 S5P_IRQ_VIC1(12) @@ -55,8 +55,8 @@ #define IRQ_SPI1 S5P_IRQ_VIC1(16) #define IRQ_SPI2 S5P_IRQ_VIC1(17) #define IRQ_IRDA S5P_IRQ_VIC1(18) -#define IRQ_CAN0 S5P_IRQ_VIC1(19) -#define IRQ_CAN1 S5P_IRQ_VIC1(20) +#define IRQ_IIC2 S5P_IRQ_VIC1(19) +#define IRQ_IIC_HDMIPHY S5P_IRQ_VIC1(20) #define IRQ_HSIRX S5P_IRQ_VIC1(21) #define IRQ_HSITX S5P_IRQ_VIC1(22) #define IRQ_UHOST S5P_IRQ_VIC1(23) @@ -65,7 +65,7 @@ #define IRQ_HSMMC0 S5P_IRQ_VIC1(26) #define IRQ_HSMMC1 S5P_IRQ_VIC1(27) #define IRQ_HSMMC2 S5P_IRQ_VIC1(28) -#define IRQ_MIPICSI S5P_IRQ_VIC1(29) +#define IRQ_MIPI_CSIS S5P_IRQ_VIC1(29) #define IRQ_MIPIDSI S5P_IRQ_VIC1(30) #define IRQ_ONENAND_AUDI S5P_IRQ_VIC1(31) @@ -86,7 +86,7 @@ #define IRQ_HDMI S5P_IRQ_VIC2(12) #define IRQ_IIC1 S5P_IRQ_VIC2(13) #define IRQ_MFC S5P_IRQ_VIC2(14) -#define IRQ_TVENC S5P_IRQ_VIC2(15) +#define IRQ_SDO S5P_IRQ_VIC2(15) #define IRQ_I2S0 S5P_IRQ_VIC2(16) #define IRQ_I2S1 S5P_IRQ_VIC2(17) #define IRQ_I2S2 S5P_IRQ_VIC2(18) @@ -99,9 +99,9 @@ #define IRQ_TC IRQ_PENDN #define IRQ_KEYPAD S5P_IRQ_VIC2(25) #define IRQ_CG S5P_IRQ_VIC2(26) -#define IRQ_SEC S5P_IRQ_VIC2(27) -#define IRQ_SECRX S5P_IRQ_VIC2(28) -#define IRQ_SECTX S5P_IRQ_VIC2(29) +#define IRQ_SSS_INT S5P_IRQ_VIC2(27) +#define IRQ_SSS_HASH S5P_IRQ_VIC2(28) +#define IRQ_PCM2 S5P_IRQ_VIC2(29) #define IRQ_SDMIRQ S5P_IRQ_VIC2(30) #define IRQ_SDMFIQ S5P_IRQ_VIC2(31) @@ -109,7 +109,7 @@ #define IRQ_IPC S5P_IRQ_VIC3(0) #define IRQ_HOSTIF S5P_IRQ_VIC3(1) -#define IRQ_MMC3 S5P_IRQ_VIC3(2) +#define IRQ_HSMMC3 S5P_IRQ_VIC3(2) #define IRQ_CEC S5P_IRQ_VIC3(3) #define IRQ_TSI S5P_IRQ_VIC3(4) #define IRQ_MDNIE0 S5P_IRQ_VIC3(5) @@ -121,12 +121,17 @@ #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) +/* GPIO interrupt */ +#define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1) +#define S5P_GPIOINT_GROUP_MAXNR 22 + /* Set the default NR_IRQS */ -#define NR_IRQS (IRQ_EINT(31) + 1) +#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1) /* Compatibility */ #define IRQ_LCD_FIFO IRQ_LCD0 #define IRQ_LCD_VSYNC IRQ_LCD1 #define IRQ_LCD_SYSTEM IRQ_LCD2 +#define IRQ_MIPI_CSIS0 IRQ_MIPI_CSIS #endif /* ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index 34eb168ec95..763929aca52 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -1,6 +1,6 @@ /* linux/arch/arm/mach-s5pv210/include/mach/map.h * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. * http://www.samsung.com/ * * S5PV210 - Memory map definitions @@ -16,93 +16,143 @@ #include <plat/map-base.h> #include <plat/map-s5p.h> -#define S5PC110_PA_ONENAND (0xB0000000) -#define S5PC110_PA_ONENAND_DMA (0xB0600000) +#define S5PV210_PA_SDRAM 0x20000000 -#define S5PV210_PA_CHIPID (0xE0000000) -#define S5P_PA_CHIPID S5PV210_PA_CHIPID +#define S5PV210_PA_SROM_BANK5 0xA8000000 -#define S5PV210_PA_SYSCON (0xE0100000) -#define S5P_PA_SYSCON S5PV210_PA_SYSCON +#define S5PC110_PA_ONENAND 0xB0000000 +#define S5PC110_PA_ONENAND_DMA 0xB0600000 -#define S5PV210_PA_GPIO (0xE0200000) -#define S5P_PA_GPIO S5PV210_PA_GPIO +#define S5PV210_PA_CHIPID 0xE0000000 -/* SPI */ -#define S5PV210_PA_SPI0 0xE1300000 -#define S5PV210_PA_SPI1 0xE1400000 +#define S5PV210_PA_SYSCON 0xE0100000 -#define S5PV210_PA_IIC0 (0xE1800000) -#define S5PV210_PA_IIC1 (0xFAB00000) -#define S5PV210_PA_IIC2 (0xE1A00000) +#define S5PV210_PA_GPIO 0xE0200000 -#define S5PV210_PA_TIMER (0xE2500000) -#define S5P_PA_TIMER S5PV210_PA_TIMER +#define S5PV210_PA_SPDIF 0xE1100000 -#define S5PV210_PA_SYSTIMER (0xE2600000) +#define S5PV210_PA_SPI0 0xE1300000 +#define S5PV210_PA_SPI1 0xE1400000 -#define S5PV210_PA_WATCHDOG (0xE2700000) +#define S5PV210_PA_KEYPAD 0xE1600000 -#define S5PV210_PA_UART (0xE2900000) +#define S5PV210_PA_ADC 0xE1700000 -#define S5P_PA_UART0 (S5PV210_PA_UART + 0x0) -#define S5P_PA_UART1 (S5PV210_PA_UART + 0x400) -#define S5P_PA_UART2 (S5PV210_PA_UART + 0x800) -#define S5P_PA_UART3 (S5PV210_PA_UART + 0xC00) +#define S5PV210_PA_IIC0 0xE1800000 +#define S5PV210_PA_IIC1 0xFAB00000 +#define S5PV210_PA_IIC2 0xE1A00000 -#define S5P_SZ_UART SZ_256 +#define S5PV210_PA_AC97 0xE2200000 -#define S5PV210_PA_SROMC (0xE8000000) +#define S5PV210_PA_PCM0 0xE2300000 +#define S5PV210_PA_PCM1 0xE1200000 +#define S5PV210_PA_PCM2 0xE2B00000 -#define S5PV210_PA_MDMA 0xFA200000 -#define S5PV210_PA_PDMA0 0xE0900000 -#define S5PV210_PA_PDMA1 0xE0A00000 +#define S5PV210_PA_TIMER 0xE2500000 +#define S5PV210_PA_SYSTIMER 0xE2600000 +#define S5PV210_PA_WATCHDOG 0xE2700000 +#define S5PV210_PA_RTC 0xE2800000 -#define S5PV210_PA_FB (0xF8000000) +#define S5PV210_PA_UART 0xE2900000 -#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) +#define S5PV210_PA_SROMC 0xE8000000 -#define S5PV210_PA_VIC0 (0xF2000000) -#define S5P_PA_VIC0 S5PV210_PA_VIC0 +#define S5PV210_PA_CFCON 0xE8200000 -#define S5PV210_PA_VIC1 (0xF2100000) -#define S5P_PA_VIC1 S5PV210_PA_VIC1 +#define S5PV210_PA_MFC 0xF1700000 -#define S5PV210_PA_VIC2 (0xF2200000) -#define S5P_PA_VIC2 S5PV210_PA_VIC2 +#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) -#define S5PV210_PA_VIC3 (0xF2300000) -#define S5P_PA_VIC3 S5PV210_PA_VIC3 +#define S5PV210_PA_HSOTG 0xEC000000 +#define S5PV210_PA_HSPHY 0xEC100000 -#define S5PV210_PA_SDRAM (0x20000000) -#define S5P_PA_SDRAM S5PV210_PA_SDRAM +#define S5PV210_PA_IIS0 0xEEE30000 +#define S5PV210_PA_IIS1 0xE2100000 +#define S5PV210_PA_IIS2 0xE2A00000 -/* I2S */ -#define S5PV210_PA_IIS0 0xEEE30000 -#define S5PV210_PA_IIS1 0xE2100000 -#define S5PV210_PA_IIS2 0xE2A00000 +#define S5PV210_PA_DMC0 0xF0000000 +#define S5PV210_PA_DMC1 0xF1400000 -/* PCM */ -#define S5PV210_PA_PCM0 0xE2300000 -#define S5PV210_PA_PCM1 0xE1200000 -#define S5PV210_PA_PCM2 0xE2B00000 +#define S5PV210_PA_VIC0 0xF2000000 +#define S5PV210_PA_VIC1 0xF2100000 +#define S5PV210_PA_VIC2 0xF2200000 +#define S5PV210_PA_VIC3 0xF2300000 -/* AC97 */ -#define S5PV210_PA_AC97 0xE2200000 +#define S5PV210_PA_FB 0xF8000000 -#define S5PV210_PA_ADC (0xE1700000) +#define S5PV210_PA_MDMA 0xFA200000 +#define S5PV210_PA_PDMA0 0xE0900000 +#define S5PV210_PA_PDMA1 0xE0A00000 -/* compatibiltiy defines. */ -#define S3C_PA_UART S5PV210_PA_UART -#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0) -#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1) -#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2) -#define S3C_PA_IIC S5PV210_PA_IIC0 -#define S3C_PA_IIC1 S5PV210_PA_IIC1 -#define S3C_PA_IIC2 S5PV210_PA_IIC2 -#define S3C_PA_FB S5PV210_PA_FB -#define S3C_PA_WDT S5PV210_PA_WATCHDOG +#define S5PV210_PA_MIPI_CSIS 0xFA600000 -#define SAMSUNG_PA_ADC S5PV210_PA_ADC +#define S5PV210_PA_FIMC0 0xFB200000 +#define S5PV210_PA_FIMC1 0xFB300000 +#define S5PV210_PA_FIMC2 0xFB400000 + +#define S5PV210_PA_JPEG 0xFB600000 + +#define S5PV210_PA_SDO 0xF9000000 +#define S5PV210_PA_VP 0xF9100000 +#define S5PV210_PA_MIXER 0xF9200000 +#define S5PV210_PA_HDMI 0xFA100000 +#define S5PV210_PA_IIC_HDMIPHY 0xFA900000 + +/* Compatibiltiy Defines */ + +#define S3C_PA_FB S5PV210_PA_FB +#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0) +#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1) +#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2) +#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3) +#define S3C_PA_IIC S5PV210_PA_IIC0 +#define S3C_PA_IIC1 S5PV210_PA_IIC1 +#define S3C_PA_IIC2 S5PV210_PA_IIC2 +#define S3C_PA_RTC S5PV210_PA_RTC +#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG +#define S3C_PA_WDT S5PV210_PA_WATCHDOG +#define S3C_PA_SPI0 S5PV210_PA_SPI0 +#define S3C_PA_SPI1 S5PV210_PA_SPI1 + +#define S5P_PA_CHIPID S5PV210_PA_CHIPID +#define S5P_PA_FIMC0 S5PV210_PA_FIMC0 +#define S5P_PA_FIMC1 S5PV210_PA_FIMC1 +#define S5P_PA_FIMC2 S5PV210_PA_FIMC2 +#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS +#define S5P_PA_MFC S5PV210_PA_MFC +#define S5P_PA_IIC_HDMIPHY S5PV210_PA_IIC_HDMIPHY + +#define S5P_PA_SDO S5PV210_PA_SDO +#define S5P_PA_VP S5PV210_PA_VP +#define S5P_PA_MIXER S5PV210_PA_MIXER +#define S5P_PA_HDMI S5PV210_PA_HDMI + +#define S5P_PA_ONENAND S5PC110_PA_ONENAND +#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA +#define S5P_PA_SDRAM S5PV210_PA_SDRAM +#define S5P_PA_SROMC S5PV210_PA_SROMC +#define S5P_PA_SYSCON S5PV210_PA_SYSCON +#define S5P_PA_TIMER S5PV210_PA_TIMER + +#define S5P_PA_JPEG S5PV210_PA_JPEG + +#define SAMSUNG_PA_ADC S5PV210_PA_ADC +#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON +#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD +#define SAMSUNG_PA_TIMER S5PV210_PA_TIMER + +/* UART */ + +#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) + +#define S3C_PA_UART S5PV210_PA_UART + +#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) +#define S5P_PA_UART0 S5P_PA_UART(0) +#define S5P_PA_UART1 S5P_PA_UART(1) +#define S5P_PA_UART2 S5P_PA_UART(2) +#define S5P_PA_UART3 S5P_PA_UART(3) + +#define S5P_SZ_UART SZ_256 #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/memory.h b/arch/arm/mach-s5pv210/include/mach/memory.h index 379117e2760..2d3cfa221d5 100644 --- a/arch/arm/mach-s5pv210/include/mach/memory.h +++ b/arch/arm/mach-s5pv210/include/mach/memory.h @@ -13,11 +13,15 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x20000000) -#define CONSISTENT_DMA_SIZE (SZ_8M + SZ_4M + SZ_2M) +#define PLAT_PHYS_OFFSET UL(0x20000000) -/* Maximum of 256MiB in one bank */ -#define MAX_PHYSMEM_BITS 32 +/* + * Sparsemem support + * Physical memory can be located from 0x20000000 to 0x7fffffff, + * so MAX_PHYSMEM_BITS is 31. + */ + +#define MAX_PHYSMEM_BITS 31 #define SECTION_SIZE_BITS 28 #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h new file mode 100644 index 00000000000..eba8aea63ed --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h @@ -0,0 +1,46 @@ +/* linux/arch/arm/mach-s5pv210/include/mach/pm-core.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h, + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S5PV210 - PM core support for arch/arm/plat-s5p/pm.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +static inline void s3c_pm_debug_init_uart(void) +{ + /* nothing here yet */ +} + +static inline void s3c_pm_arch_prepare_irqs(void) +{ + __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK); + __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK); +} + +static inline void s3c_pm_arch_stop_clocks(void) +{ + /* nothing here yet */ +} + +static inline void s3c_pm_arch_show_resume_irqs(void) +{ + /* nothing here yet */ +} + +static inline void s3c_pm_arch_update_uart(void __iomem *regs, + struct pm_uart_save *save) +{ + /* nothing here yet */ +} + +static inline void s3c_pm_restored_gpios(void) { } +static inline void samsung_pm_saved_gpios(void) { } diff --git a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h b/arch/arm/mach-s5pv210/include/mach/pwm-clock.h deleted file mode 100644 index f8a9f1b330e..00000000000 --- a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h +++ /dev/null @@ -1,70 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/include/mach/pwm-clock.h - * - * Copyright (c) 2009 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h - * - * S5PV210 - pwm clock and timer support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_PWMCLK_H -#define __ASM_ARCH_PWMCLK_H __FILE__ - -/** - * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk - * @tcfg: The timer TCFG1 register bits shifted down to 0. - * - * Return true if the given configuration from TCFG1 is a TCLK instead - * any of the TDIV clocks. - */ -static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) -{ - return tcfg == S3C64XX_TCFG1_MUX_TCLK; -} - -/** - * tcfg_to_divisor() - convert tcfg1 setting to a divisor - * @tcfg1: The tcfg1 setting, shifted down. - * - * Get the divisor value for the given tcfg1 setting. We assume the - * caller has already checked to see if this is not a TCLK source. - */ -static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) -{ - return 1 << tcfg1; -} - -/** - * pwm_tdiv_has_div1() - does the tdiv setting have a /1 - * - * Return true if we have a /1 in the tdiv setting. - */ -static inline unsigned int pwm_tdiv_has_div1(void) -{ - return 1; -} - -/** - * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. - * @div: The divisor to calculate the bit information for. - * - * Turn a divisor into the necessary bit field for TCFG1. - */ -static inline unsigned long pwm_tdiv_div_bits(unsigned int div) -{ - return ilog2(div); -} - -#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK - -#endif /* __ASM_ARCH_PWMCLK_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h index 2a25ab40c86..e345584d4c3 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h @@ -25,6 +25,7 @@ #define S5P_APLL_CON S5P_CLKREG(0x100) #define S5P_MPLL_CON S5P_CLKREG(0x108) #define S5P_EPLL_CON S5P_CLKREG(0x110) +#define S5P_EPLL_CON1 S5P_CLKREG(0x114) #define S5P_VPLL_CON S5P_CLKREG(0x120) #define S5P_CLK_SRC0 S5P_CLKREG(0x200) @@ -67,11 +68,28 @@ #define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488) #define S5P_CLK_OUT S5P_CLKREG(0x500) +/* DIV/MUX STATUS */ +#define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000) +#define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004) +#define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100) +#define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1104) + /* CLKSRC0 */ -#define S5P_CLKSRC0_MUX200_MASK (0x1<<16) +#define S5P_CLKSRC0_MUX200_SHIFT (16) +#define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT) #define S5P_CLKSRC0_MUX166_MASK (0x1<<20) #define S5P_CLKSRC0_MUX133_MASK (0x1<<24) +/* CLKSRC2 */ +#define S5P_CLKSRC2_G3D_SHIFT (0) +#define S5P_CLKSRC2_G3D_MASK (0x3 << S5P_CLKSRC2_G3D_SHIFT) +#define S5P_CLKSRC2_MFC_SHIFT (4) +#define S5P_CLKSRC2_MFC_MASK (0x3 << S5P_CLKSRC2_MFC_SHIFT) + +/* CLKSRC6*/ +#define S5P_CLKSRC6_ONEDRAM_SHIFT (24) +#define S5P_CLKSRC6_ONEDRAM_MASK (0x3 << S5P_CLKSRC6_ONEDRAM_SHIFT) + /* CLKDIV0 */ #define S5P_CLKDIV0_APLL_SHIFT (0) #define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT) @@ -90,10 +108,24 @@ #define S5P_CLKDIV0_PCLK66_SHIFT (28) #define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT) +/* CLKDIV2 */ +#define S5P_CLKDIV2_G3D_SHIFT (0) +#define S5P_CLKDIV2_G3D_MASK (0xF << S5P_CLKDIV2_G3D_SHIFT) +#define S5P_CLKDIV2_MFC_SHIFT (4) +#define S5P_CLKDIV2_MFC_MASK (0xF << S5P_CLKDIV2_MFC_SHIFT) + +/* CLKDIV6 */ +#define S5P_CLKDIV6_ONEDRAM_SHIFT (28) +#define S5P_CLKDIV6_ONEDRAM_MASK (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT) + +#define S5P_SWRESET S5P_CLKREG(0x2000) + +#define S5P_ARM_MCS_CON S5P_CLKREG(0x6100) + /* Registers related to power management */ #define S5P_PWR_CFG S5P_CLKREG(0xC000) #define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004) -#define S5P_WAKEUP_MASK S5P_CLKREG(0xC008) +#define S5P_WAKEUP_MASK S5P_CLKREG(0xC008) #define S5P_PWR_MODE S5P_CLKREG(0xC00C) #define S5P_NORMAL_CFG S5P_CLKREG(0xC010) #define S5P_IDLE_CFG S5P_CLKREG(0xC020) @@ -112,8 +144,9 @@ #define S5P_OTHERS S5P_CLKREG(0xE000) #define S5P_OM_STAT S5P_CLKREG(0xE100) +#define S5P_HDMI_PHY_CONTROL S5P_CLKREG(0xE804) #define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) -#define S5P_DAC_CONTROL S5P_CLKREG(0xE810) +#define S5P_DAC_PHY_CONTROL S5P_CLKREG(0xE810) #define S5P_INFORM0 S5P_CLKREG(0xF000) #define S5P_INFORM1 S5P_CLKREG(0xF004) @@ -129,7 +162,6 @@ #define S5P_MDNIE_SEL S5P_CLKREG(0x7008) #define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) #define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) -#define S5P_MIPI_CONTROL S5P_CLKREG(0xE814) #define S5P_IDLE_CFG_TL_MASK (3 << 30) #define S5P_IDLE_CFG_TM_MASK (3 << 28) @@ -157,11 +189,11 @@ #define S5P_SLEEP_CFG_USBOSC_EN (1 << 1) /* OTHERS Resgister */ +#define S5P_OTHERS_RET_IO (1 << 31) +#define S5P_OTHERS_RET_CF (1 << 30) +#define S5P_OTHERS_RET_MMC (1 << 29) +#define S5P_OTHERS_RET_UART (1 << 28) #define S5P_OTHERS_USB_SIG_MASK (1 << 16) -#define S5P_OTHERS_MIPI_DPHY_EN (1 << 28) - -/* MIPI */ -#define S5P_MIPI_DPHY_EN (3) /* S5P_DAC_CONTROL */ #define S5P_DAC_ENABLE (1) diff --git a/arch/arm/mach-s5pv210/include/mach/regs-fb.h b/arch/arm/mach-s5pv210/include/mach/regs-fb.h deleted file mode 100644 index 60d992989bd..00000000000 --- a/arch/arm/mach-s5pv210/include/mach/regs-fb.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright 2010 Ben Dooks <ben-linux@fluff.org> - * - * Dummy framebuffer to allow build for the moment. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_MACH_REGS_FB_H -#define __ASM_ARCH_MACH_REGS_FB_H __FILE__ - -#include <plat/regs-fb-v4.h> - -static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) -{ - return 0x2400 + (window * 256 *4 ) + reg; -} - -#endif /* __ASM_ARCH_MACH_REGS_FB_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h index 49e029b4978..de0c8997607 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h @@ -31,13 +31,6 @@ #define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7)) -/* values for S5P_EXTINT0 */ -#define S5P_EXTINT_LOWLEV (0x00) -#define S5P_EXTINT_HILEV (0x01) -#define S5P_EXTINT_FALLEDGE (0x02) -#define S5P_EXTINT_RISEEDGE (0x03) -#define S5P_EXTINT_BOTHEDGE (0x04) - #define EINT_MODE S3C_GPIO_SFN(0xf) #define EINT_GPIO_0(x) S5PV210_GPH0(x) diff --git a/arch/arm/mach-s5pv210/include/mach/regs-irq.h b/arch/arm/mach-s5pv210/include/mach/regs-irq.h index 5c3b104a7c8..d8bc1e6c7aa 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-irq.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-irq.h @@ -13,7 +13,6 @@ #ifndef __ASM_ARCH_REGS_IRQ_H #define __ASM_ARCH_REGS_IRQ_H __FILE__ -#include <asm/hardware/vic.h> #include <mach/map.h> #endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/spi-clocks.h b/arch/arm/mach-s5pv210/include/mach/spi-clocks.h deleted file mode 100644 index 02acded5f73..00000000000 --- a/arch/arm/mach-s5pv210/include/mach/spi-clocks.h +++ /dev/null @@ -1,17 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/include/mach/spi-clocks.h - * - * Copyright (C) 2010 Samsung Electronics Co. Ltd. - * Jaswinder Singh <jassi.brar@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __S5PV210_PLAT_SPI_CLKS_H -#define __S5PV210_PLAT_SPI_CLKS_H __FILE__ - -#define S5PV210_SPI_SRCCLK_PCLK 0 -#define S5PV210_SPI_SRCCLK_SCLK 1 - -#endif /* __S5PV210_PLAT_SPI_CLKS_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/system.h b/arch/arm/mach-s5pv210/include/mach/system.h deleted file mode 100644 index 1ca04d5025b..00000000000 --- a/arch/arm/mach-s5pv210/include/mach/system.h +++ /dev/null @@ -1,26 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/include/mach/system.h - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5PV210 - system support header - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H __FILE__ - -static void arch_idle(void) -{ - /* nothing here yet */ -} - -static void arch_reset(char mode, const char *cmd) -{ - /* nothing here yet */ -} - -#endif /* __ASM_ARCH_SYSTEM_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/tick.h b/arch/arm/mach-s5pv210/include/mach/tick.h deleted file mode 100644 index 7993b3603cc..00000000000 --- a/arch/arm/mach-s5pv210/include/mach/tick.h +++ /dev/null @@ -1,26 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/include/mach/tick.h - * - * Copyright (c) 2009 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Based on arch/arm/mach-s3c6400/include/mach/tick.h - * - * S5PV210 - Timer tick support definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_TICK_H -#define __ASM_ARCH_TICK_H __FILE__ - -static inline u32 s3c24xx_ostimer_pending(void) -{ - u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS); - return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0))); -} - -#define TICK_MAX (0xffffffff) - -#endif /* __ASM_ARCH_TICK_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/timex.h b/arch/arm/mach-s5pv210/include/mach/timex.h deleted file mode 100644 index 73dc85496a8..00000000000 --- a/arch/arm/mach-s5pv210/include/mach/timex.h +++ /dev/null @@ -1,29 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/include/mach/timex.h - * - * Copyright (c) 2003-2010 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Based on arch/arm/mach-s5p6442/include/mach/timex.h - * - * S5PV210 - time parameters - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H __FILE__ - -/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it - * a variable is useless. It seems as long as we make our timers an - * exact multiple of HZ, any value that makes a 1->1 correspondence - * for the time conversion functions to/from jiffies is acceptable. -*/ - -#define CLOCK_TICK_RATE 12000000 - -#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/uncompress.h b/arch/arm/mach-s5pv210/include/mach/uncompress.h deleted file mode 100644 index 08ff2fda1fb..00000000000 --- a/arch/arm/mach-s5pv210/include/mach/uncompress.h +++ /dev/null @@ -1,24 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/include/mach/uncompress.h - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5PV210 - uncompress code - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include <mach/map.h> -#include <plat/uncompress.h> - -static void arch_detect_cpu(void) -{ - /* we do not need to do any cpu detection here at the moment. */ -} - -#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/vmalloc.h b/arch/arm/mach-s5pv210/include/mach/vmalloc.h deleted file mode 100644 index 58f515e0747..00000000000 --- a/arch/arm/mach-s5pv210/include/mach/vmalloc.h +++ /dev/null @@ -1,22 +0,0 @@ -/* linux/arch/arm/mach-s5p6442/include/mach/vmalloc.h - * - * Copyright 2010 Ben Dooks <ben-linux@fluff.org> - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Based on arch/arm/mach-s5p6442/include/mach/vmalloc.h - * - * S5PV210 vmalloc definition - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_VMALLOC_H -#define __ASM_ARCH_VMALLOC_H __FILE__ - -#define VMALLOC_END (0xE0000000) - -#endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-s5pv210/init.c b/arch/arm/mach-s5pv210/init.c deleted file mode 100644 index 4865ae2c475..00000000000 --- a/arch/arm/mach-s5pv210/init.c +++ /dev/null @@ -1,44 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/init.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/serial_core.h> - -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/s5pv210.h> -#include <plat/regs-serial.h> - -static struct s3c24xx_uart_clksrc s5pv210_serial_clocks[] = { - [0] = { - .name = "pclk", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - }, -}; - -/* uart registration process */ -void __init s5pv210_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) -{ - struct s3c2410_uartcfg *tcfg = cfg; - u32 ucnt; - - for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { - if (!tcfg->clocks) { - tcfg->clocks = s5pv210_serial_clocks; - tcfg->clocks_size = ARRAY_SIZE(s5pv210_serial_clocks); - } - } - - s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no); -} diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c index 10bc76ec402..cc37edacda2 100644 --- a/arch/arm/mach-s5pv210/mach-aquila.c +++ b/arch/arm/mach-s5pv210/mach-aquila.c @@ -12,123 +12,662 @@ #include <linux/types.h> #include <linux/init.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/fb.h> +#include <linux/i2c.h> +#include <linux/i2c-gpio.h> +#include <linux/mfd/max8998.h> +#include <linux/mfd/wm8994/pdata.h> +#include <linux/regulator/fixed.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/gpio.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/setup.h> #include <asm/mach-types.h> +#include <video/samsung_fimd.h> #include <mach/map.h> #include <mach/regs-clock.h> -#include <mach/regs-fb.h> -#include <plat/regs-serial.h> -#include <plat/s5pv210.h> +#include <plat/gpio-cfg.h> #include <plat/devs.h> #include <plat/cpu.h> #include <plat/fb.h> +#include <plat/fimc-core.h> +#include <plat/sdhci.h> +#include <plat/samsung-time.h> + +#include "common.h" /* Following are default values for UCON, ULCON and UFCON UART registers */ -#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ +#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXFIFO_TOI | \ S3C2443_UCON_RXERR_IRQEN) -#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 +#define AQUILA_ULCON_DEFAULT S3C2410_LCON_CS8 -#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) +#define AQUILA_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE -static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { +static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = { [0] = { .hwport = 0, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = AQUILA_UCON_DEFAULT, + .ulcon = AQUILA_ULCON_DEFAULT, + /* + * Actually UART0 can support 256 bytes fifo, but aquila board + * supports 128 bytes fifo because of initial chip bug + */ + .ufcon = AQUILA_UFCON_DEFAULT | + S5PV210_UFCON_TXTRIG128 | S5PV210_UFCON_RXTRIG128, }, [1] = { .hwport = 1, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = AQUILA_UCON_DEFAULT, + .ulcon = AQUILA_ULCON_DEFAULT, + .ufcon = AQUILA_UFCON_DEFAULT | + S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64, }, [2] = { .hwport = 2, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = AQUILA_UCON_DEFAULT, + .ulcon = AQUILA_ULCON_DEFAULT, + .ufcon = AQUILA_UFCON_DEFAULT | + S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, }, [3] = { .hwport = 3, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = AQUILA_UCON_DEFAULT, + .ulcon = AQUILA_ULCON_DEFAULT, + .ufcon = AQUILA_UFCON_DEFAULT | + S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, }, }; /* Frame Buffer */ static struct s3c_fb_pd_win aquila_fb_win0 = { - .win_mode = { - .pixclock = 1000000000000ULL / ((16+16+2+480)*(28+3+2+800)*60), - .left_margin = 16, - .right_margin = 16, - .upper_margin = 3, - .lower_margin = 28, - .hsync_len = 2, - .vsync_len = 2, - .xres = 480, - .yres = 800, - }, .max_bpp = 32, .default_bpp = 16, + .xres = 480, + .yres = 800, }; static struct s3c_fb_pd_win aquila_fb_win1 = { - .win_mode = { - .pixclock = 1000000000000ULL / ((16+16+2+480)*(28+3+2+800)*60), - .left_margin = 16, - .right_margin = 16, - .upper_margin = 3, - .lower_margin = 28, - .hsync_len = 2, - .vsync_len = 2, - .xres = 480, - .yres = 800, - }, .max_bpp = 32, .default_bpp = 16, + .xres = 480, + .yres = 800, +}; + +static struct fb_videomode aquila_lcd_timing = { + .left_margin = 16, + .right_margin = 16, + .upper_margin = 3, + .lower_margin = 28, + .hsync_len = 2, + .vsync_len = 2, + .xres = 480, + .yres = 800, }; static struct s3c_fb_platdata aquila_lcd_pdata __initdata = { .win[0] = &aquila_fb_win0, .win[1] = &aquila_fb_win1, + .vtiming = &aquila_lcd_timing, .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | VIDCON1_INV_VCLK | VIDCON1_INV_VDEN, .setup_gpio = s5pv210_fb_gpio_setup_24bpp, }; +/* MAX8998 regulators */ +#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE) + +static struct regulator_init_data aquila_ldo2_data = { + .constraints = { + .name = "VALIVE_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .always_on = 1, + .state_mem = { + .enabled = 1, + }, + }, +}; + +static struct regulator_init_data aquila_ldo3_data = { + .constraints = { + .name = "VUSB+MIPI_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo4_data = { + .constraints = { + .name = "VDAC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data aquila_ldo5_data = { + .constraints = { + .name = "VTF_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data aquila_ldo6_data = { + .constraints = { + .name = "VCC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data aquila_ldo7_data = { + .constraints = { + .name = "VCC_3.0V", + .min_uV = 3000000, + .max_uV = 3000000, + .apply_uV = 1, + .boot_on = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo8_data = { + .constraints = { + .name = "VUSB+VADC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo9_data = { + .constraints = { + .name = "VCC+VCAM_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo10_data = { + .constraints = { + .name = "VPLL_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .boot_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo11_data = { + .constraints = { + .name = "CAM_IO_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo12_data = { + .constraints = { + .name = "CAM_ISP_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo13_data = { + .constraints = { + .name = "CAM_A_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo14_data = { + .constraints = { + .name = "CAM_CIF_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo15_data = { + .constraints = { + .name = "CAM_AF_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo16_data = { + .constraints = { + .name = "VMIPI_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo17_data = { + .constraints = { + .name = "CAM_8M_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +/* BUCK */ +static struct regulator_consumer_supply buck1_consumer = + REGULATOR_SUPPLY("vddarm", NULL); + +static struct regulator_consumer_supply buck2_consumer = + REGULATOR_SUPPLY("vddint", NULL); + +static struct regulator_init_data aquila_buck1_data = { + .constraints = { + .name = "VARM_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &buck1_consumer, +}; + +static struct regulator_init_data aquila_buck2_data = { + .constraints = { + .name = "VINT_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &buck2_consumer, +}; + +static struct regulator_init_data aquila_buck3_data = { + .constraints = { + .name = "VCC_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .state_mem = { + .enabled = 1, + }, + }, +}; + +static struct regulator_init_data aquila_buck4_data = { + .constraints = { + .name = "CAM_CORE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct max8998_regulator_data aquila_regulators[] = { + { MAX8998_LDO2, &aquila_ldo2_data }, + { MAX8998_LDO3, &aquila_ldo3_data }, + { MAX8998_LDO4, &aquila_ldo4_data }, + { MAX8998_LDO5, &aquila_ldo5_data }, + { MAX8998_LDO6, &aquila_ldo6_data }, + { MAX8998_LDO7, &aquila_ldo7_data }, + { MAX8998_LDO8, &aquila_ldo8_data }, + { MAX8998_LDO9, &aquila_ldo9_data }, + { MAX8998_LDO10, &aquila_ldo10_data }, + { MAX8998_LDO11, &aquila_ldo11_data }, + { MAX8998_LDO12, &aquila_ldo12_data }, + { MAX8998_LDO13, &aquila_ldo13_data }, + { MAX8998_LDO14, &aquila_ldo14_data }, + { MAX8998_LDO15, &aquila_ldo15_data }, + { MAX8998_LDO16, &aquila_ldo16_data }, + { MAX8998_LDO17, &aquila_ldo17_data }, + { MAX8998_BUCK1, &aquila_buck1_data }, + { MAX8998_BUCK2, &aquila_buck2_data }, + { MAX8998_BUCK3, &aquila_buck3_data }, + { MAX8998_BUCK4, &aquila_buck4_data }, +}; + +static struct max8998_platform_data aquila_max8998_pdata = { + .num_regulators = ARRAY_SIZE(aquila_regulators), + .regulators = aquila_regulators, + .buck1_set1 = S5PV210_GPH0(3), + .buck1_set2 = S5PV210_GPH0(4), + .buck2_set3 = S5PV210_GPH0(5), + .buck1_voltage = { 1200000, 1200000, 1200000, 1200000 }, + .buck2_voltage = { 1200000, 1200000 }, +}; +#endif + +static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = { + REGULATOR_SUPPLY("DBVDD", "5-001a"), + REGULATOR_SUPPLY("AVDD2", "5-001a"), + REGULATOR_SUPPLY("CPVDD", "5-001a"), +}; + +static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = { + REGULATOR_SUPPLY("SPKVDD1", "5-001a"), + REGULATOR_SUPPLY("SPKVDD2", "5-001a"), +}; + +static struct regulator_init_data wm8994_fixed_voltage0_init_data = { + .constraints = { + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies), + .consumer_supplies = wm8994_fixed_voltage0_supplies, +}; + +static struct regulator_init_data wm8994_fixed_voltage1_init_data = { + .constraints = { + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies), + .consumer_supplies = wm8994_fixed_voltage1_supplies, +}; + +static struct fixed_voltage_config wm8994_fixed_voltage0_config = { + .supply_name = "VCC_1.8V_PDA", + .microvolts = 1800000, + .gpio = -EINVAL, + .init_data = &wm8994_fixed_voltage0_init_data, +}; + +static struct fixed_voltage_config wm8994_fixed_voltage1_config = { + .supply_name = "V_BAT", + .microvolts = 3700000, + .gpio = -EINVAL, + .init_data = &wm8994_fixed_voltage1_init_data, +}; + +static struct platform_device wm8994_fixed_voltage0 = { + .name = "reg-fixed-voltage", + .id = 0, + .dev = { + .platform_data = &wm8994_fixed_voltage0_config, + }, +}; + +static struct platform_device wm8994_fixed_voltage1 = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &wm8994_fixed_voltage1_config, + }, +}; + +static struct regulator_consumer_supply wm8994_avdd1_supply = + REGULATOR_SUPPLY("AVDD1", "5-001a"); + +static struct regulator_consumer_supply wm8994_dcvdd_supply = + REGULATOR_SUPPLY("DCVDD", "5-001a"); + +static struct regulator_init_data wm8994_ldo1_data = { + .constraints = { + .name = "AVDD1_3.0V", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &wm8994_avdd1_supply, +}; + +static struct regulator_init_data wm8994_ldo2_data = { + .constraints = { + .name = "DCVDD_1.0V", + }, + .num_consumer_supplies = 1, + .consumer_supplies = &wm8994_dcvdd_supply, +}; + +static struct wm8994_pdata wm8994_platform_data = { + /* configure gpio1 function: 0x0001(Logic level input/output) */ + .gpio_defaults[0] = 0x0001, + /* configure gpio3/4/5/7 function for AIF2 voice */ + .gpio_defaults[2] = 0x8100, + .gpio_defaults[3] = 0x8100, + .gpio_defaults[4] = 0x8100, + .gpio_defaults[6] = 0x0100, + /* configure gpio8/9/10/11 function for AIF3 BT */ + .gpio_defaults[7] = 0x8100, + .gpio_defaults[8] = 0x0100, + .gpio_defaults[9] = 0x0100, + .gpio_defaults[10] = 0x0100, + .ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data }, /* XM0FRNB_2 */ + .ldo[1] = { 0, &wm8994_ldo2_data }, +}; + +/* GPIO I2C PMIC */ +#define AP_I2C_GPIO_PMIC_BUS_4 4 +static struct i2c_gpio_platform_data aquila_i2c_gpio_pmic_data = { + .sda_pin = S5PV210_GPJ4(0), /* XMSMCSN */ + .scl_pin = S5PV210_GPJ4(3), /* XMSMIRQN */ +}; + +static struct platform_device aquila_i2c_gpio_pmic = { + .name = "i2c-gpio", + .id = AP_I2C_GPIO_PMIC_BUS_4, + .dev = { + .platform_data = &aquila_i2c_gpio_pmic_data, + }, +}; + +static struct i2c_board_info i2c_gpio_pmic_devs[] __initdata = { +#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE) + { + /* 0xCC when SRAD = 0 */ + I2C_BOARD_INFO("max8998", 0xCC >> 1), + .platform_data = &aquila_max8998_pdata, + }, +#endif +}; + +/* GPIO I2C AP 1.8V */ +#define AP_I2C_GPIO_BUS_5 5 +static struct i2c_gpio_platform_data aquila_i2c_gpio5_data = { + .sda_pin = S5PV210_MP05(3), /* XM0ADDR_11 */ + .scl_pin = S5PV210_MP05(2), /* XM0ADDR_10 */ +}; + +static struct platform_device aquila_i2c_gpio5 = { + .name = "i2c-gpio", + .id = AP_I2C_GPIO_BUS_5, + .dev = { + .platform_data = &aquila_i2c_gpio5_data, + }, +}; + +static struct i2c_board_info i2c_gpio5_devs[] __initdata = { + { + /* CS/ADDR = low 0x34 (FYI: high = 0x36) */ + I2C_BOARD_INFO("wm8994", 0x1a), + .platform_data = &wm8994_platform_data, + }, +}; + +/* PMIC Power button */ +static struct gpio_keys_button aquila_gpio_keys_table[] = { + { + .code = KEY_POWER, + .gpio = S5PV210_GPH2(6), + .desc = "gpio-keys: KEY_POWER", + .type = EV_KEY, + .active_low = 1, + .wakeup = 1, + .debounce_interval = 1, + }, +}; + +static struct gpio_keys_platform_data aquila_gpio_keys_data = { + .buttons = aquila_gpio_keys_table, + .nbuttons = ARRAY_SIZE(aquila_gpio_keys_table), +}; + +static struct platform_device aquila_device_gpiokeys = { + .name = "gpio-keys", + .dev = { + .platform_data = &aquila_gpio_keys_data, + }, +}; + +static void __init aquila_pmic_init(void) +{ + /* AP_PMIC_IRQ: EINT7 */ + s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP); + + /* nPower: EINT22 */ + s3c_gpio_cfgpin(S5PV210_GPH2(6), S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(S5PV210_GPH2(6), S3C_GPIO_PULL_UP); +} + +/* MoviNAND */ +static struct s3c_sdhci_platdata aquila_hsmmc0_data __initdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_PERMANENT, +}; + +/* Wireless LAN */ +static struct s3c_sdhci_platdata aquila_hsmmc1_data __initdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_EXTERNAL, + /* ext_cd_{init,cleanup} callbacks will be added later */ +}; + +/* External Flash */ +#define AQUILA_EXT_FLASH_EN S5PV210_MP05(4) +#define AQUILA_EXT_FLASH_CD S5PV210_GPH3(4) +static struct s3c_sdhci_platdata aquila_hsmmc2_data __initdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = AQUILA_EXT_FLASH_CD, + .ext_cd_gpio_invert = 1, +}; + +static void aquila_setup_sdhci(void) +{ + gpio_request_one(AQUILA_EXT_FLASH_EN, GPIOF_OUT_INIT_HIGH, "FLASH_EN"); + + s3c_sdhci0_set_platdata(&aquila_hsmmc0_data); + s3c_sdhci1_set_platdata(&aquila_hsmmc1_data); + s3c_sdhci2_set_platdata(&aquila_hsmmc2_data); +}; + +/* Audio device */ +static struct platform_device aquila_device_audio = { + .name = "smdk-audio", + .id = -1, +}; + static struct platform_device *aquila_devices[] __initdata = { + &aquila_i2c_gpio_pmic, + &aquila_i2c_gpio5, + &aquila_device_gpiokeys, + &aquila_device_audio, &s3c_device_fb, + &s5p_device_onenand, + &s3c_device_hsmmc0, + &s3c_device_hsmmc1, + &s3c_device_hsmmc2, + &s5p_device_fimc0, + &s5p_device_fimc1, + &s5p_device_fimc2, + &s5p_device_fimc_md, + &s5pv210_device_iis0, + &wm8994_fixed_voltage0, + &wm8994_fixed_voltage1, }; +static void __init aquila_sound_init(void) +{ + unsigned int gpio; + + /* CODEC_XTAL_EN + * + * The Aquila board have a oscillator which provide main clock + * to WM8994 codec. The oscillator provide 24MHz clock to WM8994 + * clock. Set gpio setting of "CODEC_XTAL_EN" to enable a oscillator. + * */ + gpio = S5PV210_GPH3(2); /* XEINT_26 */ + gpio_request(gpio, "CODEC_XTAL_EN"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + + /* Ths main clock of WM8994 codec uses the output of CLKOUT pin. + * The CLKOUT[9:8] set to 0x3(XUSBXTI) of 0xE010E000(OTHERS) + * because it needs 24MHz clock to operate WM8994 codec. + */ + __raw_writel(__raw_readl(S5P_OTHERS) | (0x3 << 8), S5P_OTHERS); +} + static void __init aquila_map_io(void) { - s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s5pv210_init_io(NULL, 0); s3c24xx_init_clocks(24000000); - s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs)); + s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs)); + samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init aquila_machine_init(void) { + /* PMIC */ + aquila_pmic_init(); + i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs, + ARRAY_SIZE(i2c_gpio_pmic_devs)); + /* SDHCI */ + aquila_setup_sdhci(); + + s3c_fimc_setname(0, "s5p-fimc"); + s3c_fimc_setname(1, "s5p-fimc"); + s3c_fimc_setname(2, "s5p-fimc"); + + /* SOUND */ + aquila_sound_init(); + i2c_register_board_info(AP_I2C_GPIO_BUS_5, i2c_gpio5_devs, + ARRAY_SIZE(i2c_gpio5_devs)); + /* FB */ s3c_fb_set_platdata(&aquila_lcd_pdata); @@ -139,11 +678,10 @@ MACHINE_START(AQUILA, "Aquila") /* Maintainers: Marek Szyprowski <m.szyprowski@samsung.com> Kyungmin Park <kyungmin.park@samsung.com> */ - .phys_io = S3C_PA_UART & 0xfff00000, - .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, - .boot_params = S5P_PA_SDRAM + 0x100, + .atag_offset = 0x100, .init_irq = s5pv210_init_irq, .map_io = aquila_map_io, .init_machine = aquila_machine_init, - .timer = &s3c24xx_timer, + .init_time = samsung_timer_init, + .restart = s5pv210_restart, MACHINE_END diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index 4863b13824e..c1ce921c408 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c @@ -12,87 +12,905 @@ #include <linux/types.h> #include <linux/init.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> +#include <linux/fb.h> +#include <linux/i2c.h> +#include <linux/i2c-gpio.h> +#include <linux/i2c/atmel_mxt_ts.h> +#include <linux/mfd/max8998.h> +#include <linux/mfd/wm8994/pdata.h> +#include <linux/regulator/fixed.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi_gpio.h> +#include <linux/lcd.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/gpio.h> +#include <linux/mmc/host.h> +#include <linux/interrupt.h> +#include <linux/platform_data/s3c-hsotg.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/setup.h> #include <asm/mach-types.h> +#include <video/samsung_fimd.h> #include <mach/map.h> #include <mach/regs-clock.h> -#include <plat/regs-serial.h> -#include <plat/s5pv210.h> +#include <plat/gpio-cfg.h> #include <plat/devs.h> #include <plat/cpu.h> +#include <plat/fb.h> +#include <linux/platform_data/i2c-s3c2410.h> +#include <plat/keypad.h> +#include <plat/sdhci.h> +#include <plat/clock.h> +#include <plat/samsung-time.h> +#include <plat/mfc.h> + +#include "common.h" /* Following are default values for UCON, ULCON and UFCON UART registers */ -#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ +#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXFIFO_TOI | \ S3C2443_UCON_RXERR_IRQEN) -#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 +#define GONI_ULCON_DEFAULT S3C2410_LCON_CS8 -#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) +#define GONI_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = { [0] = { .hwport = 0, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = GONI_UCON_DEFAULT, + .ulcon = GONI_ULCON_DEFAULT, + .ufcon = GONI_UFCON_DEFAULT | + S5PV210_UFCON_TXTRIG256 | S5PV210_UFCON_RXTRIG256, }, [1] = { .hwport = 1, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = GONI_UCON_DEFAULT, + .ulcon = GONI_ULCON_DEFAULT, + .ufcon = GONI_UFCON_DEFAULT | + S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64, }, [2] = { .hwport = 2, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = GONI_UCON_DEFAULT, + .ulcon = GONI_ULCON_DEFAULT, + .ufcon = GONI_UFCON_DEFAULT | + S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, }, [3] = { .hwport = 3, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = GONI_UCON_DEFAULT, + .ulcon = GONI_ULCON_DEFAULT, + .ufcon = GONI_UFCON_DEFAULT | + S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, + }, +}; + +/* Frame Buffer */ +static struct s3c_fb_pd_win goni_fb_win0 = { + .max_bpp = 32, + .default_bpp = 16, + .xres = 480, + .yres = 800, + .virtual_x = 480, + .virtual_y = 2 * 800, +}; + +static struct fb_videomode goni_lcd_timing = { + .left_margin = 16, + .right_margin = 16, + .upper_margin = 2, + .lower_margin = 28, + .hsync_len = 2, + .vsync_len = 1, + .xres = 480, + .yres = 800, + .refresh = 55, +}; + +static struct s3c_fb_platdata goni_lcd_pdata __initdata = { + .win[0] = &goni_fb_win0, + .vtiming = &goni_lcd_timing, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB | + VIDCON0_CLKSEL_LCD, + .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN + | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, + .setup_gpio = s5pv210_fb_gpio_setup_24bpp, +}; + +static int lcd_power_on(struct lcd_device *ld, int enable) +{ + return 1; +} + +static int reset_lcd(struct lcd_device *ld) +{ + static unsigned int first = 1; + int reset_gpio = -1; + + reset_gpio = S5PV210_MP05(5); + + if (first) { + gpio_request(reset_gpio, "MLCD_RST"); + first = 0; + } + + gpio_direction_output(reset_gpio, 1); + return 1; +} + +static struct lcd_platform_data goni_lcd_platform_data = { + .reset = reset_lcd, + .power_on = lcd_power_on, + .lcd_enabled = 0, + .reset_delay = 120, /* 120ms */ + .power_on_delay = 25, /* 25ms */ + .power_off_delay = 200, /* 200ms */ +}; + +#define LCD_BUS_NUM 3 +static struct spi_board_info spi_board_info[] __initdata = { + { + .modalias = "s6e63m0", + .platform_data = &goni_lcd_platform_data, + .max_speed_hz = 1200000, + .bus_num = LCD_BUS_NUM, + .chip_select = 0, + .mode = SPI_MODE_3, + .controller_data = (void *)S5PV210_MP01(1), /* DISPLAY_CS */ + }, +}; + +static struct spi_gpio_platform_data lcd_spi_gpio_data = { + .sck = S5PV210_MP04(1), /* DISPLAY_CLK */ + .mosi = S5PV210_MP04(3), /* DISPLAY_SI */ + .miso = SPI_GPIO_NO_MISO, + .num_chipselect = 1, +}; + +static struct platform_device goni_spi_gpio = { + .name = "spi_gpio", + .id = LCD_BUS_NUM, + .dev = { + .parent = &s3c_device_fb.dev, + .platform_data = &lcd_spi_gpio_data, + }, +}; + +/* KEYPAD */ +static uint32_t keymap[] __initdata = { + /* KEY(row, col, keycode) */ + KEY(0, 1, KEY_MENU), /* Send */ + KEY(0, 2, KEY_BACK), /* End */ + KEY(1, 1, KEY_CONFIG), /* Half shot */ + KEY(1, 2, KEY_VOLUMEUP), + KEY(2, 1, KEY_CAMERA), /* Full shot */ + KEY(2, 2, KEY_VOLUMEDOWN), +}; + +static struct matrix_keymap_data keymap_data __initdata = { + .keymap = keymap, + .keymap_size = ARRAY_SIZE(keymap), +}; + +static struct samsung_keypad_platdata keypad_data __initdata = { + .keymap_data = &keymap_data, + .rows = 3, + .cols = 3, +}; + +/* Radio */ +static struct i2c_board_info i2c1_devs[] __initdata = { + { + I2C_BOARD_INFO("si470x", 0x10), + }, +}; + +static void __init goni_radio_init(void) +{ + int gpio; + + gpio = S5PV210_GPJ2(4); /* XMSMDATA_4 */ + gpio_request(gpio, "FM_INT"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); + i2c1_devs[0].irq = gpio_to_irq(gpio); + + gpio = S5PV210_GPJ2(5); /* XMSMDATA_5 */ + gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "FM_RST"); +} + +/* TSP */ +static struct mxt_platform_data qt602240_platform_data = { + .irqflags = IRQF_TRIGGER_FALLING, +}; + +static struct s3c2410_platform_i2c i2c2_data __initdata = { + .flags = 0, + .bus_num = 2, + .slave_addr = 0x10, + .frequency = 400 * 1000, + .sda_delay = 100, +}; + +static struct i2c_board_info i2c2_devs[] __initdata = { + { + I2C_BOARD_INFO("qt602240_ts", 0x4a), + .platform_data = &qt602240_platform_data, + }, +}; + +static void __init goni_tsp_init(void) +{ + int gpio; + + gpio = S5PV210_GPJ1(3); /* XMSMADDR_11 */ + gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON"); + gpio_export(gpio, 0); + + gpio = S5PV210_GPJ0(5); /* XMSMADDR_5 */ + gpio_request(gpio, "TSP_INT"); + + s5p_register_gpio_interrupt(gpio); + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + i2c2_devs[0].irq = gpio_to_irq(gpio); +} + +/* USB OTG */ +static struct s3c_hsotg_plat goni_hsotg_pdata; + +/* MAX8998 regulators */ +#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE) + +static struct regulator_consumer_supply goni_ldo3_consumers[] = { + REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), +}; + +static struct regulator_consumer_supply goni_ldo5_consumers[] = { + REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"), +}; + +static struct regulator_consumer_supply goni_ldo8_consumers[] = { + REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), + REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"), +}; + +static struct regulator_consumer_supply goni_ldo11_consumers[] = { + REGULATOR_SUPPLY("vddio", "0-0030"), /* "CAM_IO_2.8V" */ +}; + +static struct regulator_consumer_supply goni_ldo13_consumers[] = { + REGULATOR_SUPPLY("vdda", "0-0030"), /* "CAM_A_2.8V" */ +}; + +static struct regulator_consumer_supply goni_ldo14_consumers[] = { + REGULATOR_SUPPLY("vdd_core", "0-0030"), /* "CAM_CIF_1.8V" */ +}; + +static struct regulator_init_data goni_ldo2_data = { + .constraints = { + .name = "VALIVE_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .always_on = 1, + .state_mem = { + .enabled = 1, + }, + }, +}; + +static struct regulator_init_data goni_ldo3_data = { + .constraints = { + .name = "VUSB+MIPI_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(goni_ldo3_consumers), + .consumer_supplies = goni_ldo3_consumers, +}; + +static struct regulator_init_data goni_ldo4_data = { + .constraints = { + .name = "VDAC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data goni_ldo5_data = { + .constraints = { + .name = "VTF_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(goni_ldo5_consumers), + .consumer_supplies = goni_ldo5_consumers, +}; + +static struct regulator_init_data goni_ldo6_data = { + .constraints = { + .name = "VCC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data goni_ldo7_data = { + .constraints = { + .name = "VLCD_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data goni_ldo8_data = { + .constraints = { + .name = "VUSB+VADC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(goni_ldo8_consumers), + .consumer_supplies = goni_ldo8_consumers, +}; + +static struct regulator_init_data goni_ldo9_data = { + .constraints = { + .name = "VCC+VCAM_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, }, }; +static struct regulator_init_data goni_ldo10_data = { + .constraints = { + .name = "VPLL_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .boot_on = 1, + }, +}; + +static struct regulator_init_data goni_ldo11_data = { + .constraints = { + .name = "CAM_IO_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(goni_ldo11_consumers), + .consumer_supplies = goni_ldo11_consumers, +}; + +static struct regulator_init_data goni_ldo12_data = { + .constraints = { + .name = "CAM_ISP_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data goni_ldo13_data = { + .constraints = { + .name = "CAM_A_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(goni_ldo13_consumers), + .consumer_supplies = goni_ldo13_consumers, +}; + +static struct regulator_init_data goni_ldo14_data = { + .constraints = { + .name = "CAM_CIF_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(goni_ldo14_consumers), + .consumer_supplies = goni_ldo14_consumers, +}; + +static struct regulator_init_data goni_ldo15_data = { + .constraints = { + .name = "CAM_AF_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data goni_ldo16_data = { + .constraints = { + .name = "VMIPI_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data goni_ldo17_data = { + .constraints = { + .name = "VCC_3.0V_LCD", + .min_uV = 3000000, + .max_uV = 3000000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +/* BUCK */ +static struct regulator_consumer_supply buck1_consumer = + REGULATOR_SUPPLY("vddarm", NULL); + +static struct regulator_consumer_supply buck2_consumer = + REGULATOR_SUPPLY("vddint", NULL); + +static struct regulator_consumer_supply buck3_consumer = + REGULATOR_SUPPLY("vdet", "s5p-sdo"); + + +static struct regulator_init_data goni_buck1_data = { + .constraints = { + .name = "VARM_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &buck1_consumer, +}; + +static struct regulator_init_data goni_buck2_data = { + .constraints = { + .name = "VINT_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &buck2_consumer, +}; + +static struct regulator_init_data goni_buck3_data = { + .constraints = { + .name = "VCC_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .state_mem = { + .enabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &buck3_consumer, +}; + +static struct regulator_init_data goni_buck4_data = { + .constraints = { + .name = "CAM_CORE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct max8998_regulator_data goni_regulators[] = { + { MAX8998_LDO2, &goni_ldo2_data }, + { MAX8998_LDO3, &goni_ldo3_data }, + { MAX8998_LDO4, &goni_ldo4_data }, + { MAX8998_LDO5, &goni_ldo5_data }, + { MAX8998_LDO6, &goni_ldo6_data }, + { MAX8998_LDO7, &goni_ldo7_data }, + { MAX8998_LDO8, &goni_ldo8_data }, + { MAX8998_LDO9, &goni_ldo9_data }, + { MAX8998_LDO10, &goni_ldo10_data }, + { MAX8998_LDO11, &goni_ldo11_data }, + { MAX8998_LDO12, &goni_ldo12_data }, + { MAX8998_LDO13, &goni_ldo13_data }, + { MAX8998_LDO14, &goni_ldo14_data }, + { MAX8998_LDO15, &goni_ldo15_data }, + { MAX8998_LDO16, &goni_ldo16_data }, + { MAX8998_LDO17, &goni_ldo17_data }, + { MAX8998_BUCK1, &goni_buck1_data }, + { MAX8998_BUCK2, &goni_buck2_data }, + { MAX8998_BUCK3, &goni_buck3_data }, + { MAX8998_BUCK4, &goni_buck4_data }, +}; + +static struct max8998_platform_data goni_max8998_pdata = { + .num_regulators = ARRAY_SIZE(goni_regulators), + .regulators = goni_regulators, + .buck1_set1 = S5PV210_GPH0(3), + .buck1_set2 = S5PV210_GPH0(4), + .buck2_set3 = S5PV210_GPH0(5), + .buck1_voltage = { 1200000, 1200000, 1200000, 1200000 }, + .buck2_voltage = { 1200000, 1200000 }, +}; +#endif + +static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = { + REGULATOR_SUPPLY("DBVDD", "5-001a"), + REGULATOR_SUPPLY("AVDD2", "5-001a"), + REGULATOR_SUPPLY("CPVDD", "5-001a"), +}; + +static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = { + REGULATOR_SUPPLY("SPKVDD1", "5-001a"), + REGULATOR_SUPPLY("SPKVDD2", "5-001a"), +}; + +static struct regulator_init_data wm8994_fixed_voltage0_init_data = { + .constraints = { + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies), + .consumer_supplies = wm8994_fixed_voltage0_supplies, +}; + +static struct regulator_init_data wm8994_fixed_voltage1_init_data = { + .constraints = { + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies), + .consumer_supplies = wm8994_fixed_voltage1_supplies, +}; + +static struct fixed_voltage_config wm8994_fixed_voltage0_config = { + .supply_name = "VCC_1.8V_PDA", + .microvolts = 1800000, + .gpio = -EINVAL, + .init_data = &wm8994_fixed_voltage0_init_data, +}; + +static struct fixed_voltage_config wm8994_fixed_voltage1_config = { + .supply_name = "V_BAT", + .microvolts = 3700000, + .gpio = -EINVAL, + .init_data = &wm8994_fixed_voltage1_init_data, +}; + +static struct platform_device wm8994_fixed_voltage0 = { + .name = "reg-fixed-voltage", + .id = 0, + .dev = { + .platform_data = &wm8994_fixed_voltage0_config, + }, +}; + +static struct platform_device wm8994_fixed_voltage1 = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &wm8994_fixed_voltage1_config, + }, +}; + +static struct regulator_consumer_supply wm8994_avdd1_supply = + REGULATOR_SUPPLY("AVDD1", "5-001a"); + +static struct regulator_consumer_supply wm8994_dcvdd_supply = + REGULATOR_SUPPLY("DCVDD", "5-001a"); + +static struct regulator_init_data wm8994_ldo1_data = { + .constraints = { + .name = "AVDD1_3.0V", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &wm8994_avdd1_supply, +}; + +static struct regulator_init_data wm8994_ldo2_data = { + .constraints = { + .name = "DCVDD_1.0V", + }, + .num_consumer_supplies = 1, + .consumer_supplies = &wm8994_dcvdd_supply, +}; + +static struct wm8994_pdata wm8994_platform_data = { + /* configure gpio1 function: 0x0001(Logic level input/output) */ + .gpio_defaults[0] = 0x0001, + /* configure gpio3/4/5/7 function for AIF2 voice */ + .gpio_defaults[2] = 0x8100, + .gpio_defaults[3] = 0x8100, + .gpio_defaults[4] = 0x8100, + .gpio_defaults[6] = 0x0100, + /* configure gpio8/9/10/11 function for AIF3 BT */ + .gpio_defaults[7] = 0x8100, + .gpio_defaults[8] = 0x0100, + .gpio_defaults[9] = 0x0100, + .gpio_defaults[10] = 0x0100, + .ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data }, /* XM0FRNB_2 */ + .ldo[1] = { 0, &wm8994_ldo2_data }, +}; + +/* GPIO I2C PMIC */ +#define AP_I2C_GPIO_PMIC_BUS_4 4 +static struct i2c_gpio_platform_data goni_i2c_gpio_pmic_data = { + .sda_pin = S5PV210_GPJ4(0), /* XMSMCSN */ + .scl_pin = S5PV210_GPJ4(3), /* XMSMIRQN */ +}; + +static struct platform_device goni_i2c_gpio_pmic = { + .name = "i2c-gpio", + .id = AP_I2C_GPIO_PMIC_BUS_4, + .dev = { + .platform_data = &goni_i2c_gpio_pmic_data, + }, +}; + +static struct i2c_board_info i2c_gpio_pmic_devs[] __initdata = { +#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE) + { + /* 0xCC when SRAD = 0 */ + I2C_BOARD_INFO("max8998", 0xCC >> 1), + .platform_data = &goni_max8998_pdata, + }, +#endif +}; + +/* GPIO I2C AP 1.8V */ +#define AP_I2C_GPIO_BUS_5 5 +static struct i2c_gpio_platform_data goni_i2c_gpio5_data = { + .sda_pin = S5PV210_MP05(3), /* XM0ADDR_11 */ + .scl_pin = S5PV210_MP05(2), /* XM0ADDR_10 */ +}; + +static struct platform_device goni_i2c_gpio5 = { + .name = "i2c-gpio", + .id = AP_I2C_GPIO_BUS_5, + .dev = { + .platform_data = &goni_i2c_gpio5_data, + }, +}; + +static struct i2c_board_info i2c_gpio5_devs[] __initdata = { + { + /* CS/ADDR = low 0x34 (FYI: high = 0x36) */ + I2C_BOARD_INFO("wm8994", 0x1a), + .platform_data = &wm8994_platform_data, + }, +}; + +/* PMIC Power button */ +static struct gpio_keys_button goni_gpio_keys_table[] = { + { + .code = KEY_POWER, + .gpio = S5PV210_GPH2(6), + .desc = "gpio-keys: KEY_POWER", + .type = EV_KEY, + .active_low = 1, + .wakeup = 1, + .debounce_interval = 1, + }, +}; + +static struct gpio_keys_platform_data goni_gpio_keys_data = { + .buttons = goni_gpio_keys_table, + .nbuttons = ARRAY_SIZE(goni_gpio_keys_table), +}; + +static struct platform_device goni_device_gpiokeys = { + .name = "gpio-keys", + .dev = { + .platform_data = &goni_gpio_keys_data, + }, +}; + +static void __init goni_pmic_init(void) +{ + /* AP_PMIC_IRQ: EINT7 */ + s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP); + + /* nPower: EINT22 */ + s3c_gpio_cfgpin(S5PV210_GPH2(6), S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(S5PV210_GPH2(6), S3C_GPIO_PULL_UP); +} + +/* MoviNAND */ +static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_PERMANENT, +}; + +/* Wireless LAN */ +static struct s3c_sdhci_platdata goni_hsmmc1_data __initdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_EXTERNAL, + /* ext_cd_{init,cleanup} callbacks will be added later */ +}; + +/* External Flash */ +#define GONI_EXT_FLASH_EN S5PV210_MP05(4) +#define GONI_EXT_FLASH_CD S5PV210_GPH3(4) +static struct s3c_sdhci_platdata goni_hsmmc2_data __initdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = GONI_EXT_FLASH_CD, + .ext_cd_gpio_invert = 1, +}; + +static struct regulator_consumer_supply mmc2_supplies[] = { + REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), +}; + +static struct regulator_init_data mmc2_fixed_voltage_init_data = { + .constraints = { + .name = "V_TF_2.8V", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(mmc2_supplies), + .consumer_supplies = mmc2_supplies, +}; + +static struct fixed_voltage_config mmc2_fixed_voltage_config = { + .supply_name = "EXT_FLASH_EN", + .microvolts = 2800000, + .gpio = GONI_EXT_FLASH_EN, + .enable_high = true, + .init_data = &mmc2_fixed_voltage_init_data, +}; + +static struct platform_device mmc2_fixed_voltage = { + .name = "reg-fixed-voltage", + .id = 2, + .dev = { + .platform_data = &mmc2_fixed_voltage_config, + }, +}; + +static void goni_setup_sdhci(void) +{ + s3c_sdhci0_set_platdata(&goni_hsmmc0_data); + s3c_sdhci1_set_platdata(&goni_hsmmc1_data); + s3c_sdhci2_set_platdata(&goni_hsmmc2_data); +}; + +/* Audio device */ +static struct platform_device goni_device_audio = { + .name = "smdk-audio", + .id = -1, +}; + static struct platform_device *goni_devices[] __initdata = { + &s3c_device_fb, + &s5p_device_onenand, + &goni_spi_gpio, + &goni_i2c_gpio_pmic, + &goni_i2c_gpio5, + &goni_device_audio, + &mmc2_fixed_voltage, + &goni_device_gpiokeys, + &s5p_device_mfc, + &s5p_device_mfc_l, + &s5p_device_mfc_r, + &s5p_device_mixer, + &s5p_device_sdo, + &s3c_device_i2c0, + &s3c_device_hsmmc0, + &s3c_device_hsmmc1, + &s3c_device_hsmmc2, + &s5pv210_device_iis0, + &s3c_device_usb_hsotg, + &samsung_device_keypad, + &s3c_device_i2c1, + &s3c_device_i2c2, + &wm8994_fixed_voltage0, + &wm8994_fixed_voltage1, }; +static void __init goni_sound_init(void) +{ + /* Ths main clock of WM8994 codec uses the output of CLKOUT pin. + * The CLKOUT[9:8] set to 0x3(XUSBXTI) of 0xE010E000(OTHERS) + * because it needs 24MHz clock to operate WM8994 codec. + */ + __raw_writel(__raw_readl(S5P_OTHERS) | (0x3 << 8), S5P_OTHERS); +} + static void __init goni_map_io(void) { - s5p_init_io(NULL, 0, S5P_VA_CHIPID); - s3c24xx_init_clocks(24000000); + s5pv210_init_io(NULL, 0); + s3c24xx_init_clocks(clk_xusbxti.rate); s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs)); + samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); +} + +static void __init goni_reserve(void) +{ + s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); } static void __init goni_machine_init(void) { + /* Radio: call before I2C 1 registeration */ + goni_radio_init(); + + /* I2C0 */ + s3c_i2c0_set_platdata(NULL); + + /* I2C1 */ + s3c_i2c1_set_platdata(NULL); + i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); + + /* TSP: call before I2C 2 registeration */ + goni_tsp_init(); + + /* I2C2 */ + s3c_i2c2_set_platdata(&i2c2_data); + i2c_register_board_info(2, i2c2_devs, ARRAY_SIZE(i2c2_devs)); + + /* PMIC */ + goni_pmic_init(); + i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs, + ARRAY_SIZE(i2c_gpio_pmic_devs)); + /* SDHCI */ + goni_setup_sdhci(); + + /* SOUND */ + goni_sound_init(); + i2c_register_board_info(AP_I2C_GPIO_BUS_5, i2c_gpio5_devs, + ARRAY_SIZE(i2c_gpio5_devs)); + + /* FB */ + s3c_fb_set_platdata(&goni_lcd_pdata); + + s3c_hsotg_set_platdata(&goni_hsotg_pdata); + + /* SPI */ + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); + + /* KEYPAD */ + samsung_keypad_set_platdata(&keypad_data); + platform_add_devices(goni_devices, ARRAY_SIZE(goni_devices)); } MACHINE_START(GONI, "GONI") /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */ - .phys_io = S3C_PA_UART & 0xfff00000, - .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, - .boot_params = S5P_PA_SDRAM + 0x100, + .atag_offset = 0x100, .init_irq = s5pv210_init_irq, .map_io = goni_map_io, .init_machine = goni_machine_init, - .timer = &s3c24xx_timer, + .init_time = samsung_timer_init, + .reserve = &goni_reserve, + .restart = s5pv210_restart, MACHINE_END diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c index 4c8903c6d10..448e1d2eeed 100644 --- a/arch/arm/mach-s5pv210/mach-smdkc110.c +++ b/arch/arm/mach-s5pv210/mach-smdkc110.c @@ -12,6 +12,9 @@ #include <linux/types.h> #include <linux/init.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> +#include <linux/i2c.h> +#include <linux/device.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -21,22 +24,27 @@ #include <mach/map.h> #include <mach/regs-clock.h> -#include <plat/regs-serial.h> -#include <plat/s5pv210.h> #include <plat/devs.h> #include <plat/cpu.h> +#include <linux/platform_data/ata-samsung_cf.h> +#include <linux/platform_data/i2c-s3c2410.h> +#include <plat/pm.h> +#include <plat/samsung-time.h> +#include <plat/mfc.h> + +#include "common.h" /* Following are default values for UCON, ULCON and UFCON UART registers */ -#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ +#define SMDKC110_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXFIFO_TOI | \ S3C2443_UCON_RXERR_IRQEN) -#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 +#define SMDKC110_ULCON_DEFAULT S3C2410_LCON_CS8 -#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ +#define SMDKC110_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ S5PV210_UFCON_TXTRIG4 | \ S5PV210_UFCON_RXTRIG4) @@ -44,58 +52,108 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { [0] = { .hwport = 0, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = SMDKC110_UCON_DEFAULT, + .ulcon = SMDKC110_ULCON_DEFAULT, + .ufcon = SMDKC110_UFCON_DEFAULT, }, [1] = { .hwport = 1, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = SMDKC110_UCON_DEFAULT, + .ulcon = SMDKC110_ULCON_DEFAULT, + .ufcon = SMDKC110_UFCON_DEFAULT, }, [2] = { .hwport = 2, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = SMDKC110_UCON_DEFAULT, + .ulcon = SMDKC110_ULCON_DEFAULT, + .ufcon = SMDKC110_UFCON_DEFAULT, }, [3] = { .hwport = 3, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = SMDKC110_UCON_DEFAULT, + .ulcon = SMDKC110_ULCON_DEFAULT, + .ufcon = SMDKC110_UFCON_DEFAULT, }, }; +static struct s3c_ide_platdata smdkc110_ide_pdata __initdata = { + .setup_gpio = s5pv210_ide_setup_gpio, +}; + static struct platform_device *smdkc110_devices[] __initdata = { &s5pv210_device_iis0, &s5pv210_device_ac97, + &s5pv210_device_spdif, + &s3c_device_cfcon, + &s3c_device_i2c0, + &s3c_device_i2c1, + &s3c_device_i2c2, + &s3c_device_rtc, &s3c_device_wdt, + &s5p_device_fimc0, + &s5p_device_fimc1, + &s5p_device_fimc2, + &s5p_device_fimc_md, + &s5p_device_mfc, + &s5p_device_mfc_l, + &s5p_device_mfc_r, +}; + +static struct i2c_board_info smdkc110_i2c_devs0[] __initdata = { + { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */ + { I2C_BOARD_INFO("wm8580", 0x1b), }, +}; + +static struct i2c_board_info smdkc110_i2c_devs1[] __initdata = { + /* To Be Updated */ +}; + +static struct i2c_board_info smdkc110_i2c_devs2[] __initdata = { + /* To Be Updated */ }; static void __init smdkc110_map_io(void) { - s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s5pv210_init_io(NULL, 0); s3c24xx_init_clocks(24000000); s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs)); + samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); +} + +static void __init smdkc110_reserve(void) +{ + s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); } static void __init smdkc110_machine_init(void) { + s3c_pm_init(); + + s3c_i2c0_set_platdata(NULL); + s3c_i2c1_set_platdata(NULL); + s3c_i2c2_set_platdata(NULL); + i2c_register_board_info(0, smdkc110_i2c_devs0, + ARRAY_SIZE(smdkc110_i2c_devs0)); + i2c_register_board_info(1, smdkc110_i2c_devs1, + ARRAY_SIZE(smdkc110_i2c_devs1)); + i2c_register_board_info(2, smdkc110_i2c_devs2, + ARRAY_SIZE(smdkc110_i2c_devs2)); + + s3c_ide_set_platdata(&smdkc110_ide_pdata); + platform_add_devices(smdkc110_devices, ARRAY_SIZE(smdkc110_devices)); } MACHINE_START(SMDKC110, "SMDKC110") /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ - .phys_io = S3C_PA_UART & 0xfff00000, - .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, - .boot_params = S5P_PA_SDRAM + 0x100, + .atag_offset = 0x100, .init_irq = s5pv210_init_irq, .map_io = smdkc110_map_io, .init_machine = smdkc110_machine_init, - .timer = &s3c24xx_timer, + .init_time = samsung_timer_init, + .restart = s5pv210_restart, + .reserve = &smdkc110_reserve, MACHINE_END diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index 0d462794804..2a6655fb63e 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -10,35 +10,58 @@ #include <linux/kernel.h> #include <linux/types.h> +#include <linux/i2c.h> #include <linux/init.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> +#include <linux/device.h> +#include <linux/dm9000.h> +#include <linux/fb.h> +#include <linux/gpio.h> +#include <linux/delay.h> +#include <linux/pwm_backlight.h> +#include <linux/platform_data/s3c-hsotg.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/setup.h> #include <asm/mach-types.h> +#include <video/platform_lcd.h> +#include <video/samsung_fimd.h> + #include <mach/map.h> #include <mach/regs-clock.h> -#include <plat/regs-serial.h> -#include <plat/s5pv210.h> +#include <plat/regs-srom.h> +#include <plat/gpio-cfg.h> #include <plat/devs.h> #include <plat/cpu.h> #include <plat/adc.h> -#include <plat/ts.h> +#include <linux/platform_data/touchscreen-s3c2410.h> +#include <linux/platform_data/ata-samsung_cf.h> +#include <linux/platform_data/i2c-s3c2410.h> +#include <plat/keypad.h> +#include <plat/pm.h> +#include <plat/fb.h> +#include <plat/samsung-time.h> +#include <plat/backlight.h> +#include <plat/mfc.h> +#include <plat/clock.h> + +#include "common.h" /* Following are default values for UCON, ULCON and UFCON UART registers */ -#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ +#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXFIFO_TOI | \ S3C2443_UCON_RXERR_IRQEN) -#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 +#define SMDKV210_ULCON_DEFAULT S3C2410_LCON_CS8 -#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ +#define SMDKV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ S5PV210_UFCON_TXTRIG4 | \ S5PV210_UFCON_RXTRIG4) @@ -46,67 +69,269 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { [0] = { .hwport = 0, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = SMDKV210_UCON_DEFAULT, + .ulcon = SMDKV210_ULCON_DEFAULT, + .ufcon = SMDKV210_UFCON_DEFAULT, }, [1] = { .hwport = 1, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = SMDKV210_UCON_DEFAULT, + .ulcon = SMDKV210_ULCON_DEFAULT, + .ufcon = SMDKV210_UFCON_DEFAULT, }, [2] = { .hwport = 2, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = SMDKV210_UCON_DEFAULT, + .ulcon = SMDKV210_ULCON_DEFAULT, + .ufcon = SMDKV210_UFCON_DEFAULT, }, [3] = { .hwport = 3, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = SMDKV210_UCON_DEFAULT, + .ulcon = SMDKV210_ULCON_DEFAULT, + .ufcon = SMDKV210_UFCON_DEFAULT, + }, +}; + +static struct s3c_ide_platdata smdkv210_ide_pdata __initdata = { + .setup_gpio = s5pv210_ide_setup_gpio, +}; + +static uint32_t smdkv210_keymap[] __initdata = { + /* KEY(row, col, keycode) */ + KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3), + KEY(0, 6, KEY_4), KEY(0, 7, KEY_5), + KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C), + KEY(1, 6, KEY_D), KEY(1, 7, KEY_E) +}; + +static struct matrix_keymap_data smdkv210_keymap_data __initdata = { + .keymap = smdkv210_keymap, + .keymap_size = ARRAY_SIZE(smdkv210_keymap), +}; + +static struct samsung_keypad_platdata smdkv210_keypad_data __initdata = { + .keymap_data = &smdkv210_keymap_data, + .rows = 8, + .cols = 8, +}; + +static struct resource smdkv210_dm9000_resources[] = { + [0] = DEFINE_RES_MEM(S5PV210_PA_SROM_BANK5, 1), + [1] = DEFINE_RES_MEM(S5PV210_PA_SROM_BANK5 + 2, 1), + [2] = DEFINE_RES_NAMED(IRQ_EINT(9), 1, NULL, IORESOURCE_IRQ \ + | IORESOURCE_IRQ_HIGHLEVEL), +}; + +static struct dm9000_plat_data smdkv210_dm9000_platdata = { + .flags = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM, + .dev_addr = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 }, +}; + +static struct platform_device smdkv210_dm9000 = { + .name = "dm9000", + .id = -1, + .num_resources = ARRAY_SIZE(smdkv210_dm9000_resources), + .resource = smdkv210_dm9000_resources, + .dev = { + .platform_data = &smdkv210_dm9000_platdata, }, }; +static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd, + unsigned int power) +{ + if (power) { +#if !defined(CONFIG_BACKLIGHT_PWM) + gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_HIGH, "GPD0"); + gpio_free(S5PV210_GPD0(3)); +#endif + + /* fire nRESET on power up */ + gpio_request_one(S5PV210_GPH0(6), GPIOF_OUT_INIT_HIGH, "GPH0"); + + gpio_set_value(S5PV210_GPH0(6), 0); + mdelay(10); + + gpio_set_value(S5PV210_GPH0(6), 1); + mdelay(10); + + gpio_free(S5PV210_GPH0(6)); + } else { +#if !defined(CONFIG_BACKLIGHT_PWM) + gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_LOW, "GPD0"); + gpio_free(S5PV210_GPD0(3)); +#endif + } +} + +static struct plat_lcd_data smdkv210_lcd_lte480wv_data = { + .set_power = smdkv210_lte480wv_set_power, +}; + +static struct platform_device smdkv210_lcd_lte480wv = { + .name = "platform-lcd", + .dev.parent = &s3c_device_fb.dev, + .dev.platform_data = &smdkv210_lcd_lte480wv_data, +}; + +static struct s3c_fb_pd_win smdkv210_fb_win0 = { + .max_bpp = 32, + .default_bpp = 24, + .xres = 800, + .yres = 480, +}; + +static struct fb_videomode smdkv210_lcd_timing = { + .left_margin = 13, + .right_margin = 8, + .upper_margin = 7, + .lower_margin = 5, + .hsync_len = 3, + .vsync_len = 1, + .xres = 800, + .yres = 480, +}; + +static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = { + .win[0] = &smdkv210_fb_win0, + .vtiming = &smdkv210_lcd_timing, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, + .setup_gpio = s5pv210_fb_gpio_setup_24bpp, +}; + +/* USB OTG */ +static struct s3c_hsotg_plat smdkv210_hsotg_pdata; + static struct platform_device *smdkv210_devices[] __initdata = { - &s5pv210_device_iis0, - &s5pv210_device_ac97, &s3c_device_adc, + &s3c_device_cfcon, + &s3c_device_fb, + &s3c_device_hsmmc0, + &s3c_device_hsmmc1, + &s3c_device_hsmmc2, + &s3c_device_hsmmc3, + &s3c_device_i2c0, + &s3c_device_i2c1, + &s3c_device_i2c2, + &samsung_device_pwm, + &s3c_device_rtc, &s3c_device_ts, + &s3c_device_usb_hsotg, &s3c_device_wdt, + &s5p_device_fimc0, + &s5p_device_fimc1, + &s5p_device_fimc2, + &s5p_device_fimc_md, + &s5p_device_jpeg, + &s5p_device_mfc, + &s5p_device_mfc_l, + &s5p_device_mfc_r, + &s5pv210_device_ac97, + &s5pv210_device_iis0, + &s5pv210_device_spdif, + &samsung_asoc_idma, + &samsung_device_keypad, + &smdkv210_dm9000, + &smdkv210_lcd_lte480wv, +}; + +static void __init smdkv210_dm9000_init(void) +{ + unsigned int tmp; + + gpio_request(S5PV210_MP01(5), "nCS5"); + s3c_gpio_cfgpin(S5PV210_MP01(5), S3C_GPIO_SFN(2)); + gpio_free(S5PV210_MP01(5)); + + tmp = (5 << S5P_SROM_BCX__TACC__SHIFT); + __raw_writel(tmp, S5P_SROM_BC5); + + tmp = __raw_readl(S5P_SROM_BW); + tmp &= (S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS5__SHIFT); + tmp |= (1 << S5P_SROM_BW__NCS5__SHIFT); + __raw_writel(tmp, S5P_SROM_BW); +} + +static struct i2c_board_info smdkv210_i2c_devs0[] __initdata = { + { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */ + { I2C_BOARD_INFO("wm8580", 0x1b), }, +}; + +static struct i2c_board_info smdkv210_i2c_devs1[] __initdata = { + /* To Be Updated */ +}; + +static struct i2c_board_info smdkv210_i2c_devs2[] __initdata = { + /* To Be Updated */ +}; + +/* LCD Backlight data */ +static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = { + .no = S5PV210_GPD0(3), + .func = S3C_GPIO_SFN(2), }; -static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { - .delay = 10000, - .presc = 49, - .oversampling_shift = 2, +static struct platform_pwm_backlight_data smdkv210_bl_data = { + .pwm_id = 3, + .pwm_period_ns = 1000, + .enable_gpio = -1, }; static void __init smdkv210_map_io(void) { - s5p_init_io(NULL, 0, S5P_VA_CHIPID); - s3c24xx_init_clocks(24000000); + s5pv210_init_io(NULL, 0); + s3c24xx_init_clocks(clk_xusbxti.rate); s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs)); + samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4); +} + +static void __init smdkv210_reserve(void) +{ + s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); } static void __init smdkv210_machine_init(void) { - s3c24xx_ts_set_platdata(&s3c_ts_platform); + s3c_pm_init(); + + smdkv210_dm9000_init(); + + samsung_keypad_set_platdata(&smdkv210_keypad_data); + s3c24xx_ts_set_platdata(NULL); + + s3c_i2c0_set_platdata(NULL); + s3c_i2c1_set_platdata(NULL); + s3c_i2c2_set_platdata(NULL); + i2c_register_board_info(0, smdkv210_i2c_devs0, + ARRAY_SIZE(smdkv210_i2c_devs0)); + i2c_register_board_info(1, smdkv210_i2c_devs1, + ARRAY_SIZE(smdkv210_i2c_devs1)); + i2c_register_board_info(2, smdkv210_i2c_devs2, + ARRAY_SIZE(smdkv210_i2c_devs2)); + + s3c_ide_set_platdata(&smdkv210_ide_pdata); + + s3c_fb_set_platdata(&smdkv210_lcd0_pdata); + + s3c_hsotg_set_platdata(&smdkv210_hsotg_pdata); + platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices)); + + samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data); } MACHINE_START(SMDKV210, "SMDKV210") /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ - .phys_io = S3C_PA_UART & 0xfff00000, - .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, - .boot_params = S5P_PA_SDRAM + 0x100, + .atag_offset = 0x100, .init_irq = s5pv210_init_irq, .map_io = smdkv210_map_io, .init_machine = smdkv210_machine_init, - .timer = &s3c24xx_timer, + .init_time = samsung_timer_init, + .restart = s5pv210_restart, + .reserve = &smdkv210_reserve, MACHINE_END diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c new file mode 100644 index 00000000000..157805529f2 --- /dev/null +++ b/arch/arm/mach-s5pv210/mach-torbreck.c @@ -0,0 +1,135 @@ +/* linux/arch/arm/mach-s5pv210/mach-torbreck.c + * + * Copyright (c) 2010 aESOP Community + * http://www.aesop.or.kr/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/i2c.h> +#include <linux/init.h> +#include <linux/serial_core.h> +#include <linux/serial_s3c.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/setup.h> +#include <asm/mach-types.h> + +#include <mach/map.h> +#include <mach/regs-clock.h> + +#include <plat/devs.h> +#include <plat/cpu.h> +#include <linux/platform_data/i2c-s3c2410.h> +#include <plat/samsung-time.h> + +#include "common.h" + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define TORBRECK_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define TORBRECK_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define TORBRECK_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +static struct s3c2410_uartcfg torbreck_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = TORBRECK_UCON_DEFAULT, + .ulcon = TORBRECK_ULCON_DEFAULT, + .ufcon = TORBRECK_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = TORBRECK_UCON_DEFAULT, + .ulcon = TORBRECK_ULCON_DEFAULT, + .ufcon = TORBRECK_UFCON_DEFAULT, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = TORBRECK_UCON_DEFAULT, + .ulcon = TORBRECK_ULCON_DEFAULT, + .ufcon = TORBRECK_UFCON_DEFAULT, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = TORBRECK_UCON_DEFAULT, + .ulcon = TORBRECK_ULCON_DEFAULT, + .ufcon = TORBRECK_UFCON_DEFAULT, + }, +}; + +static struct platform_device *torbreck_devices[] __initdata = { + &s5pv210_device_iis0, + &s3c_device_cfcon, + &s3c_device_hsmmc0, + &s3c_device_hsmmc1, + &s3c_device_hsmmc2, + &s3c_device_hsmmc3, + &s3c_device_i2c0, + &s3c_device_i2c1, + &s3c_device_i2c2, + &s3c_device_rtc, + &s3c_device_wdt, +}; + +static struct i2c_board_info torbreck_i2c_devs0[] __initdata = { + /* To Be Updated */ +}; + +static struct i2c_board_info torbreck_i2c_devs1[] __initdata = { + /* To Be Updated */ +}; + +static struct i2c_board_info torbreck_i2c_devs2[] __initdata = { + /* To Be Updated */ +}; + +static void __init torbreck_map_io(void) +{ + s5pv210_init_io(NULL, 0); + s3c24xx_init_clocks(24000000); + s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs)); + samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); +} + +static void __init torbreck_machine_init(void) +{ + s3c_i2c0_set_platdata(NULL); + s3c_i2c1_set_platdata(NULL); + s3c_i2c2_set_platdata(NULL); + i2c_register_board_info(0, torbreck_i2c_devs0, + ARRAY_SIZE(torbreck_i2c_devs0)); + i2c_register_board_info(1, torbreck_i2c_devs1, + ARRAY_SIZE(torbreck_i2c_devs1)); + i2c_register_board_info(2, torbreck_i2c_devs2, + ARRAY_SIZE(torbreck_i2c_devs2)); + + platform_add_devices(torbreck_devices, ARRAY_SIZE(torbreck_devices)); +} + +MACHINE_START(TORBRECK, "TORBRECK") + /* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */ + .atag_offset = 0x100, + .init_irq = s5pv210_init_irq, + .map_io = torbreck_map_io, + .init_machine = torbreck_machine_init, + .init_time = samsung_timer_init, + .restart = s5pv210_restart, +MACHINE_END diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c new file mode 100644 index 00000000000..3cf3f9c8ddd --- /dev/null +++ b/arch/arm/mach-s5pv210/pm.c @@ -0,0 +1,167 @@ +/* linux/arch/arm/mach-s5pv210/pm.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV210 - Power Management support + * + * Based on arch/arm/mach-s3c2410/pm.c + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/suspend.h> +#include <linux/syscore_ops.h> +#include <linux/io.h> + +#include <plat/cpu.h> +#include <plat/pm.h> + +#include <mach/regs-irq.h> +#include <mach/regs-clock.h> + +static struct sleep_save s5pv210_core_save[] = { + /* Clock source */ + SAVE_ITEM(S5P_CLK_SRC0), + SAVE_ITEM(S5P_CLK_SRC1), + SAVE_ITEM(S5P_CLK_SRC2), + SAVE_ITEM(S5P_CLK_SRC3), + SAVE_ITEM(S5P_CLK_SRC4), + SAVE_ITEM(S5P_CLK_SRC5), + SAVE_ITEM(S5P_CLK_SRC6), + + /* Clock source Mask */ + SAVE_ITEM(S5P_CLK_SRC_MASK0), + SAVE_ITEM(S5P_CLK_SRC_MASK1), + + /* Clock Divider */ + SAVE_ITEM(S5P_CLK_DIV0), + SAVE_ITEM(S5P_CLK_DIV1), + SAVE_ITEM(S5P_CLK_DIV2), + SAVE_ITEM(S5P_CLK_DIV3), + SAVE_ITEM(S5P_CLK_DIV4), + SAVE_ITEM(S5P_CLK_DIV5), + SAVE_ITEM(S5P_CLK_DIV6), + SAVE_ITEM(S5P_CLK_DIV7), + + /* Clock Main Gate */ + SAVE_ITEM(S5P_CLKGATE_MAIN0), + SAVE_ITEM(S5P_CLKGATE_MAIN1), + SAVE_ITEM(S5P_CLKGATE_MAIN2), + + /* Clock source Peri Gate */ + SAVE_ITEM(S5P_CLKGATE_PERI0), + SAVE_ITEM(S5P_CLKGATE_PERI1), + + /* Clock source SCLK Gate */ + SAVE_ITEM(S5P_CLKGATE_SCLK0), + SAVE_ITEM(S5P_CLKGATE_SCLK1), + + /* Clock IP Clock gate */ + SAVE_ITEM(S5P_CLKGATE_IP0), + SAVE_ITEM(S5P_CLKGATE_IP1), + SAVE_ITEM(S5P_CLKGATE_IP2), + SAVE_ITEM(S5P_CLKGATE_IP3), + SAVE_ITEM(S5P_CLKGATE_IP4), + + /* Clock Blcok and Bus gate */ + SAVE_ITEM(S5P_CLKGATE_BLOCK), + SAVE_ITEM(S5P_CLKGATE_BUS0), + + /* Clock ETC */ + SAVE_ITEM(S5P_CLK_OUT), + SAVE_ITEM(S5P_MDNIE_SEL), +}; + +static int s5pv210_cpu_suspend(unsigned long arg) +{ + unsigned long tmp; + + /* issue the standby signal into the pm unit. Note, we + * issue a write-buffer drain just in case */ + + tmp = 0; + + asm("b 1f\n\t" + ".align 5\n\t" + "1:\n\t" + "mcr p15, 0, %0, c7, c10, 5\n\t" + "mcr p15, 0, %0, c7, c10, 4\n\t" + "wfi" : : "r" (tmp)); + + pr_info("Failed to suspend the system\n"); + return 1; /* Aborting suspend */ +} + +static void s5pv210_pm_prepare(void) +{ + unsigned int tmp; + + /* ensure at least INFORM0 has the resume address */ + __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0); + + tmp = __raw_readl(S5P_SLEEP_CFG); + tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN); + __raw_writel(tmp, S5P_SLEEP_CFG); + + /* WFI for SLEEP mode configuration by SYSCON */ + tmp = __raw_readl(S5P_PWR_CFG); + tmp &= S5P_CFG_WFI_CLEAN; + tmp |= S5P_CFG_WFI_SLEEP; + __raw_writel(tmp, S5P_PWR_CFG); + + /* SYSCON interrupt handling disable */ + tmp = __raw_readl(S5P_OTHERS); + tmp |= S5P_OTHER_SYSC_INTOFF; + __raw_writel(tmp, S5P_OTHERS); + + s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); +} + +static int s5pv210_pm_add(struct device *dev, struct subsys_interface *sif) +{ + pm_cpu_prep = s5pv210_pm_prepare; + pm_cpu_sleep = s5pv210_cpu_suspend; + + return 0; +} + +static struct subsys_interface s5pv210_pm_interface = { + .name = "s5pv210_pm", + .subsys = &s5pv210_subsys, + .add_dev = s5pv210_pm_add, +}; + +static __init int s5pv210_pm_drvinit(void) +{ + return subsys_interface_register(&s5pv210_pm_interface); +} +arch_initcall(s5pv210_pm_drvinit); + +static void s5pv210_pm_resume(void) +{ + u32 tmp; + + tmp = __raw_readl(S5P_OTHERS); + tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF |\ + S5P_OTHERS_RET_MMC | S5P_OTHERS_RET_UART); + __raw_writel(tmp , S5P_OTHERS); + + s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); +} + +static struct syscore_ops s5pv210_pm_syscore_ops = { + .resume = s5pv210_pm_resume, +}; + +static __init int s5pv210_pm_syscore_init(void) +{ + register_syscore_ops(&s5pv210_pm_syscore_ops); + return 0; +} +arch_initcall(s5pv210_pm_syscore_init); diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c index a50cbac8720..55103c8220b 100644 --- a/arch/arm/mach-s5pv210/setup-fb-24bpp.c +++ b/arch/arm/mach-s5pv210/setup-fb-24bpp.c @@ -13,41 +13,28 @@ #include <linux/kernel.h> #include <linux/types.h> #include <linux/fb.h> +#include <linux/gpio.h> -#include <mach/regs-fb.h> -#include <mach/gpio.h> #include <mach/map.h> #include <plat/fb.h> #include <mach/regs-clock.h> #include <plat/gpio-cfg.h> -void s5pv210_fb_gpio_setup_24bpp(void) +static void s5pv210_fb_cfg_gpios(unsigned int base, unsigned int nr) { - unsigned int gpio = 0; - - for (gpio = S5PV210_GPF0(0); gpio <= S5PV210_GPF0(7); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } + s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2)); - for (gpio = S5PV210_GPF1(0); gpio <= S5PV210_GPF1(7); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } + for (; nr > 0; nr--, base++) + s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4); +} - for (gpio = S5PV210_GPF2(0); gpio <= S5PV210_GPF2(7); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - for (gpio = S5PV210_GPF3(0); gpio <= S5PV210_GPF3(3); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } +void s5pv210_fb_gpio_setup_24bpp(void) +{ + s5pv210_fb_cfg_gpios(S5PV210_GPF0(0), 8); + s5pv210_fb_cfg_gpios(S5PV210_GPF1(0), 8); + s5pv210_fb_cfg_gpios(S5PV210_GPF2(0), 8); + s5pv210_fb_cfg_gpios(S5PV210_GPF3(0), 4); /* Set DISPLAY_CONTROL register for Display path selection. * diff --git a/arch/arm/mach-s5pv210/setup-fimc.c b/arch/arm/mach-s5pv210/setup-fimc.c new file mode 100644 index 00000000000..54cc5b11be0 --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-fimc.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co., Ltd. + * + * S5PV210 camera interface GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <plat/gpio-cfg.h> +#include <plat/camport.h> + +int s5pv210_fimc_setup_gpio(enum s5p_camport_id id) +{ + u32 gpio8, gpio5; + int ret; + + switch (id) { + case S5P_CAMPORT_A: + gpio8 = S5PV210_GPE0(0); + gpio5 = S5PV210_GPE1(0); + break; + + case S5P_CAMPORT_B: + gpio8 = S5PV210_GPJ0(0); + gpio5 = S5PV210_GPJ1(0); + break; + + default: + WARN(1, "Wrong camport id: %d\n", id); + return -EINVAL; + } + + ret = s3c_gpio_cfgall_range(gpio8, 8, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_UP); + if (ret) + return ret; + + return s3c_gpio_cfgall_range(gpio5, 5, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c index c718253c70b..4a15849766c 100644 --- a/arch/arm/mach-s5pv210/setup-i2c0.c +++ b/arch/arm/mach-s5pv210/setup-i2c0.c @@ -14,17 +14,15 @@ #include <linux/kernel.h> #include <linux/types.h> +#include <linux/gpio.h> struct platform_device; /* don't need the contents */ -#include <mach/gpio.h> -#include <plat/iic.h> +#include <linux/platform_data/i2c-s3c2410.h> #include <plat/gpio-cfg.h> void s3c_i2c0_cfg_gpio(struct platform_device *dev) { - s3c_gpio_cfgpin(S5PV210_GPD1(0), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PV210_GPD1(0), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPD1(1), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PV210_GPD1(1), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(S5PV210_GPD1(0), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); } diff --git a/arch/arm/mach-s5pv210/setup-i2c1.c b/arch/arm/mach-s5pv210/setup-i2c1.c index 45e0e6ed2ed..4777f6b97a9 100644 --- a/arch/arm/mach-s5pv210/setup-i2c1.c +++ b/arch/arm/mach-s5pv210/setup-i2c1.c @@ -14,17 +14,15 @@ #include <linux/kernel.h> #include <linux/types.h> +#include <linux/gpio.h> struct platform_device; /* don't need the contents */ -#include <mach/gpio.h> -#include <plat/iic.h> +#include <linux/platform_data/i2c-s3c2410.h> #include <plat/gpio-cfg.h> void s3c_i2c1_cfg_gpio(struct platform_device *dev) { - s3c_gpio_cfgpin(S5PV210_GPD1(2), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PV210_GPD1(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPD1(3), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PV210_GPD1(3), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(S5PV210_GPD1(2), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); } diff --git a/arch/arm/mach-s5pv210/setup-i2c2.c b/arch/arm/mach-s5pv210/setup-i2c2.c index b11b4bff69a..bbce6c74b91 100644 --- a/arch/arm/mach-s5pv210/setup-i2c2.c +++ b/arch/arm/mach-s5pv210/setup-i2c2.c @@ -14,17 +14,15 @@ #include <linux/kernel.h> #include <linux/types.h> +#include <linux/gpio.h> struct platform_device; /* don't need the contents */ -#include <mach/gpio.h> -#include <plat/iic.h> +#include <linux/platform_data/i2c-s3c2410.h> #include <plat/gpio-cfg.h> void s3c_i2c2_cfg_gpio(struct platform_device *dev) { - s3c_gpio_cfgpin(S5PV210_GPD1(4), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PV210_GPD1(4), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPD1(5), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PV210_GPD1(5), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(S5PV210_GPD1(4), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); } diff --git a/arch/arm/mach-s5pv210/setup-ide.c b/arch/arm/mach-s5pv210/setup-ide.c new file mode 100644 index 00000000000..ea123d546bd --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-ide.c @@ -0,0 +1,39 @@ +/* linux/arch/arm/mach-s5pv210/setup-ide.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV210 setup information for IDE + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/gpio.h> + +#include <plat/gpio-cfg.h> + +static void s5pv210_ide_cfg_gpios(unsigned int base, unsigned int nr) +{ + s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4)); + + for (; nr > 0; nr--, base++) + s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4); +} + +void s5pv210_ide_setup_gpio(void) +{ + /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */ + s5pv210_ide_cfg_gpios(S5PV210_GPJ0(0), 8); + + /* CF_Data[0 - 7] */ + s5pv210_ide_cfg_gpios(S5PV210_GPJ2(0), 8); + + /* CF_Data[8 - 15] */ + s5pv210_ide_cfg_gpios(S5PV210_GPJ3(0), 8); + + /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */ + s5pv210_ide_cfg_gpios(S5PV210_GPJ4(0), 4); +} diff --git a/arch/arm/mach-s5pv210/setup-keypad.c b/arch/arm/mach-s5pv210/setup-keypad.c new file mode 100644 index 00000000000..c56420a52f4 --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-keypad.c @@ -0,0 +1,24 @@ +/* + * linux/arch/arm/mach-s5pv210/setup-keypad.c + * + * Copyright (C) 2010 Samsung Electronics Co.Ltd + * Author: Joonyoung Shim <jy0922.shim@samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include <linux/gpio.h> +#include <plat/gpio-cfg.h> + +void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) +{ + /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */ + s3c_gpio_cfgrange_nopull(S5PV210_GPH3(0), rows, S3C_GPIO_SFN(3)); + + /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */ + s3c_gpio_cfgrange_nopull(S5PV210_GPH2(0), cols, S3C_GPIO_SFN(3)); +} diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c index fe7d86dad14..0512ada0052 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c +++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c @@ -15,90 +15,89 @@ #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/gpio.h> #include <linux/mmc/host.h> #include <linux/mmc/card.h> -#include <mach/gpio.h> #include <plat/gpio-cfg.h> -#include <plat/regs-sdhci.h> +#include <plat/sdhci.h> void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) { - unsigned int gpio; + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; /* Set all the necessary GPG0/GPG1 pins to special-function 2 */ - for (gpio = S5PV210_GPG0(0); gpio < S5PV210_GPG0(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } + s3c_gpio_cfgrange_nopull(S5PV210_GPG0(0), 2, S3C_GPIO_SFN(2)); + switch (width) { case 8: - /* GPG1[3:6] special-funtion 3 */ - for (gpio = S5PV210_GPG1(3); gpio <= S5PV210_GPG1(6); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } + /* GPG1[3:6] special-function 3 */ + s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(3)); case 4: - /* GPG0[3:6] special-funtion 2 */ - for (gpio = S5PV210_GPG0(3); gpio <= S5PV210_GPG0(6); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } + /* GPG0[3:6] special-function 2 */ + s3c_gpio_cfgrange_nopull(S5PV210_GPG0(3), 4, S3C_GPIO_SFN(2)); default: break; } - s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2)); + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2)); + } } void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) { - unsigned int gpio; + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; /* Set all the necessary GPG1[0:1] pins to special-function 2 */ - for (gpio = S5PV210_GPG1(0); gpio < S5PV210_GPG1(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } + s3c_gpio_cfgrange_nopull(S5PV210_GPG1(0), 2, S3C_GPIO_SFN(2)); /* Data pin GPG1[3:6] to special-function 2 */ - for (gpio = S5PV210_GPG1(3); gpio <= S5PV210_GPG1(6); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } + s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2)); + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2)); + } } void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) { - unsigned int gpio; + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; /* Set all the necessary GPG2[0:1] pins to special-function 2 */ - for (gpio = S5PV210_GPG2(0); gpio < S5PV210_GPG2(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } + s3c_gpio_cfgrange_nopull(S5PV210_GPG2(0), 2, S3C_GPIO_SFN(2)); switch (width) { case 8: /* Data pin GPG3[3:6] to special-function 3 */ - for (gpio = S5PV210_GPG3(3); gpio <= S5PV210_GPG3(6); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } + s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(3)); case 4: /* Data pin GPG2[3:6] to special-function 2 */ - for (gpio = S5PV210_GPG2(3); gpio <= S5PV210_GPG2(6); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } + s3c_gpio_cfgrange_nopull(S5PV210_GPG2(3), 4, S3C_GPIO_SFN(2)); default: break; } - s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2)); + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2)); + } +} + +void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width) +{ + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + + /* Set all the necessary GPG3[0:1] pins to special-function 2 */ + s3c_gpio_cfgrange_nopull(S5PV210_GPG3(0), 2, S3C_GPIO_SFN(2)); + + /* Data pin GPG3[3:6] to special-function 2 */ + s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(2)); + + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_setpull(S5PV210_GPG3(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV210_GPG3(2), S3C_GPIO_SFN(2)); + } } diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c deleted file mode 100644 index 51815ec60c2..00000000000 --- a/arch/arm/mach-s5pv210/setup-sdhci.c +++ /dev/null @@ -1,63 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/setup-sdhci.c - * - * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5PV210 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <linux/mmc/card.h> -#include <linux/mmc/host.h> - -#include <plat/regs-sdhci.h> -#include <plat/sdhci.h> - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s5pv210_hsmmc_clksrcs[4] = { - [0] = "hsmmc", /* HCLK */ - [1] = "hsmmc", /* HCLK */ - [2] = "sclk_mmc", /* mmc_bus */ - /*[4] = reserved */ -}; - -void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card) -{ - u32 ctrl2, ctrl3; - - /* don't need to alter anything acording to card-type */ - - writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); - - ctrl2 = readl(r + S3C_SDHCI_CONTROL2); - ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; - ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | - S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | - S3C_SDHCI_CTRL2_ENFBCLKRX | - S3C_SDHCI_CTRL2_DFCNT_NONE | - S3C_SDHCI_CTRL2_ENCLKOUTHOLD); - - if (ios->clock < 25 * 1000000) - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | - S3C_SDHCI_CTRL3_FCSEL2 | - S3C_SDHCI_CTRL3_FCSEL1 | - S3C_SDHCI_CTRL3_FCSEL0); - else - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); - - writel(ctrl2, r + S3C_SDHCI_CONTROL2); - writel(ctrl3, r + S3C_SDHCI_CONTROL3); -} diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c new file mode 100644 index 00000000000..81aecc162f8 --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-spi.c @@ -0,0 +1,34 @@ +/* linux/arch/arm/mach-s5pv210/setup-spi.c + * + * Copyright (C) 2011 Samsung Electronics Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <plat/gpio-cfg.h> + +#ifdef CONFIG_S3C64XX_DEV_SPI0 +int s3c64xx_spi0_cfg_gpio(void) +{ + s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(S5PV210_GPB(2), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + return 0; +} +#endif + +#ifdef CONFIG_S3C64XX_DEV_SPI1 +int s3c64xx_spi1_cfg_gpio(void) +{ + s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(S5PV210_GPB(6), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + return 0; +} +#endif diff --git a/arch/arm/mach-s5pv210/setup-usb-phy.c b/arch/arm/mach-s5pv210/setup-usb-phy.c new file mode 100644 index 00000000000..b2ee5333f89 --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-usb-phy.c @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2012 Samsung Electronics Co.Ltd + * Author: Joonyoung Shim <jy0922.shim@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundationr + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/platform_device.h> + +#include <mach/map.h> + +#include <plat/cpu.h> +#include <plat/regs-usb-hsotg-phy.h> +#include <plat/usb-phy.h> + +#define S5PV210_USB_PHY_CON (S3C_VA_SYS + 0xE80C) +#define S5PV210_USB_PHY0_EN (1 << 0) +#define S5PV210_USB_PHY1_EN (1 << 1) + +static int s5pv210_usb_otgphy_init(struct platform_device *pdev) +{ + struct clk *xusbxti; + u32 phyclk; + + writel(readl(S5PV210_USB_PHY_CON) | S5PV210_USB_PHY0_EN, + S5PV210_USB_PHY_CON); + + /* set clock frequency for PLL */ + phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK; + + xusbxti = clk_get(&pdev->dev, "xusbxti"); + if (xusbxti && !IS_ERR(xusbxti)) { + switch (clk_get_rate(xusbxti)) { + case 12 * MHZ: + phyclk |= S3C_PHYCLK_CLKSEL_12M; + break; + case 24 * MHZ: + phyclk |= S3C_PHYCLK_CLKSEL_24M; + break; + default: + case 48 * MHZ: + /* default reference clock */ + break; + } + clk_put(xusbxti); + } + + /* TODO: select external clock/oscillator */ + writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK); + + /* set to normal OTG PHY */ + writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR); + mdelay(1); + + /* reset OTG PHY and Link */ + writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK, + S3C_RSTCON); + udelay(20); /* at-least 10uS */ + writel(0, S3C_RSTCON); + + return 0; +} + +static int s5pv210_usb_otgphy_exit(struct platform_device *pdev) +{ + writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN | + S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR); + + writel(readl(S5PV210_USB_PHY_CON) & ~S5PV210_USB_PHY0_EN, + S5PV210_USB_PHY_CON); + + return 0; +} + +int s5p_usb_phy_init(struct platform_device *pdev, int type) +{ + if (type == USB_PHY_TYPE_DEVICE) + return s5pv210_usb_otgphy_init(pdev); + + return -EINVAL; +} + +int s5p_usb_phy_exit(struct platform_device *pdev, int type) +{ + if (type == USB_PHY_TYPE_DEVICE) + return s5pv210_usb_otgphy_exit(pdev); + + return -EINVAL; +} |