diff options
Diffstat (limited to 'arch/arm/mach-s3c24xx')
80 files changed, 881 insertions, 5348 deletions
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index f2f7088bfd2..ad5316ae524 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -12,12 +12,14 @@ if ARCH_S3C24XX config PLAT_S3C24XX def_bool y select ARCH_REQUIRE_GPIOLIB - select NO_IOPORT + select NO_IOPORT_MAP select S3C_DEV_NAND select IRQ_DOMAIN help Base platform code for any Samsung S3C24XX device + + menu "SAMSUNG S3C24XX SoCs Support" comment "S3C24XX SoCs" @@ -26,11 +28,11 @@ config CPU_S3C2410 bool "SAMSUNG S3C2410" default y select CPU_ARM920T - select CPU_LLSERIAL_S3C2410 - select S3C2410_CLOCK - select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX + select S3C2410_COMMON_CLK + select S3C2410_DMA if S3C24XX_DMA + select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ select S3C2410_PM if PM - select SAMSUNG_HRT + select SAMSUNG_WDT_RESET help Support for S3C2410 and S3C2410A family from the S3C24XX line of Samsung Mobile CPUs. @@ -38,74 +40,54 @@ config CPU_S3C2410 config CPU_S3C2412 bool "SAMSUNG S3C2412" select CPU_ARM926T - select CPU_LLSERIAL_S3C2440 + select S3C2412_COMMON_CLK select S3C2412_DMA if S3C24XX_DMA select S3C2412_PM if PM - select SAMSUNG_HRT help Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line config CPU_S3C2416 bool "SAMSUNG S3C2416/S3C2450" select CPU_ARM926T - select CPU_LLSERIAL_S3C2440 select S3C2416_PM if PM - select S3C2443_COMMON + select S3C2443_COMMON_CLK select S3C2443_DMA if S3C24XX_DMA - select SAMSUNG_CLKSRC - select SAMSUNG_HRT help Support for the S3C2416 SoC from the S3C24XX line config CPU_S3C2440 bool "SAMSUNG S3C2440" select CPU_ARM920T - select CPU_LLSERIAL_S3C2440 - select S3C2410_CLOCK + select S3C2410_COMMON_CLK select S3C2410_PM if PM select S3C2440_DMA if S3C24XX_DMA - select SAMSUNG_HRT help Support for S3C2440 Samsung Mobile CPU based systems. config CPU_S3C2442 bool "SAMSUNG S3C2442" select CPU_ARM920T - select CPU_LLSERIAL_S3C2440 - select S3C2410_CLOCK + select S3C2410_COMMON_CLK + select S3C2410_DMA if S3C24XX_DMA select S3C2410_PM if PM - select SAMSUNG_HRT help Support for S3C2442 Samsung Mobile CPU based systems. config CPU_S3C244X def_bool y depends on CPU_S3C2440 || CPU_S3C2442 + select SAMSUNG_WDT_RESET config CPU_S3C2443 bool "SAMSUNG S3C2443" select CPU_ARM920T - select CPU_LLSERIAL_S3C2440 - select S3C2443_COMMON + select S3C2443_COMMON_CLK select S3C2443_DMA if S3C24XX_DMA - select SAMSUNG_CLKSRC - select SAMSUNG_HRT help Support for the S3C2443 SoC from the S3C24XX line # common code -config S3C2410_CLOCK - bool - help - Clock code for the S3C2410, and similar processors which - is currently includes the S3C2410, S3C2440, S3C2442. - -config S3C24XX_DCLK - bool - help - Clock code for supporting DCLK/CLKOUT on S3C24XX architectures - config S3C24XX_SMDK bool help @@ -135,7 +117,7 @@ config S3C24XX_SETUP_TS Compile in platform device definition for Samsung TouchScreen. config S3C24XX_DMA - bool "S3C2410 DMA support" + bool "S3C2410 DMA support (deprecated)" select S3C_DMA help S3C2410 DMA support. This is needed for drivers like sound which @@ -152,7 +134,6 @@ config S3C2410_DMA_DEBUG config S3C2410_DMA bool depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442) - default y if CPU_S3C2410 || CPU_S3C2442 help DMA device selection for S3C2410 and compatible CPUs @@ -161,70 +142,38 @@ config S3C2410_PM help Power Management code common to S3C2410 and better -# low-level serial option nodes - -config CPU_LLSERIAL_S3C2410_ONLY - bool - default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440 - -config CPU_LLSERIAL_S3C2440_ONLY - bool - default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410 - -config CPU_LLSERIAL_S3C2410 - bool - help - Selected if there is an S3C2410 (or register compatible) serial - low-level implementation needed - -config CPU_LLSERIAL_S3C2440 - bool +config S3C24XX_PLL + bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" + depends on ARM_S3C24XX_CPUFREQ help - Selected if there is an S3C2440 (or register compatible) serial - low-level implementation needed - -# gpio configurations - -config S3C24XX_GPIO_EXTRA - int - default 128 if S3C24XX_GPIO_EXTRA128 - default 64 if S3C24XX_GPIO_EXTRA64 - default 16 if ARCH_H1940 - default 0 + Compile in support for changing the PLL frequency from the + S3C24XX series CPUfreq driver. The PLL takes time to settle + after a frequency change, so by default it is not enabled. -config S3C24XX_GPIO_EXTRA64 - bool - help - Add an extra 64 gpio numbers to the available GPIO pool. This is - available for boards that need extra gpios for external devices. - -config S3C24XX_GPIO_EXTRA128 - bool - help - Add an extra 128 gpio numbers to the available GPIO pool. This is - available for boards that need extra gpios for external devices. + This also means that the PLL tables for the selected CPU(s) will + be built which may increase the size of the kernel image. # cpu frequency items common between s3c2410 and s3c2440/s3c2442 config S3C2410_IOTIMING bool - depends on CPU_FREQ_S3C24XX + depends on ARM_S3C24XX_CPUFREQ help Internal node to select io timing code that is common to the s3c2410 and s3c2440/s3c2442 cpu frequency support. config S3C2410_CPUFREQ_UTILS - bool - depends on CPU_FREQ_S3C24XX - help - Internal node to select timing code that is common to the s3c2410 - and s3c2440/s3c244 cpu frequency support. + bool + depends on ARM_S3C24XX_CPUFREQ + help + Internal node to select timing code that is common to the s3c2410 + and s3c2440/s3c244 cpu frequency support. # cpu frequency support common to s3c2412, s3c2413 and s3c2442 config S3C2412_IOTIMING bool - depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443) + depends on ARM_S3C24XX_CPUFREQ && (CPU_S3C2412 || CPU_S3C2443) help Intel node to select io timing code that is common to the s3c2412 and the s3c2443. @@ -233,16 +182,9 @@ config S3C2412_IOTIMING if CPU_S3C2410 -config S3C2410_CPUFREQ - bool - depends on CPU_FREQ_S3C24XX - select S3C2410_CPUFREQ_UTILS - help - CPU Frequency scaling support for S3C2410 - config S3C2410_PLL bool - depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL + depends on ARM_S3C2410_CPUFREQ && S3C24XX_PLL default y help Select the PLL table for the S3C2410 @@ -278,8 +220,8 @@ config ARCH_BAST bool "Simtec Electronics BAST (EB2410ITX)" select ISA select MACH_BAST_IDE - select S3C2410_IOTIMING if S3C2410_CPUFREQ - select S3C24XX_DCLK + select S3C2410_COMMON_DCLK + select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ select S3C24XX_SIMTEC_NOR select S3C24XX_SIMTEC_PM if PM select S3C24XX_SIMTEC_USB @@ -360,7 +302,7 @@ config MACH_TCT_HAMMER config MACH_VR1000 bool "Thorcom VR1000" select MACH_BAST_IDE - select S3C24XX_DCLK + select S3C2410_COMMON_DCLK select S3C24XX_SIMTEC_NOR select S3C24XX_SIMTEC_PM if PM select S3C24XX_SIMTEC_USB @@ -385,14 +327,6 @@ config CPU_S3C2412_ONLY !CPU_S3C2442 && !CPU_S3C2443 default y -config S3C2412_CPUFREQ - bool - depends on CPU_FREQ_S3C24XX - default y - select S3C2412_IOTIMING - help - CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs. - config S3C2412_DMA bool help @@ -490,18 +424,22 @@ config MACH_SMDK2416 help Say Y here if you are using an SMDK2416 +config MACH_S3C2416_DT + bool "Samsung S3C2416 machine using devicetree" + select CLKSRC_OF + select USE_OF + select PINCTRL + select PINCTRL_S3C24XX + help + Machine support for Samsung S3C2416 machines with device tree enabled. + Select this if a fdt blob is available for the S3C2416 SoC based board. + Note: This is under development and not all peripherals can be supported + with this machine file. + endif # CPU_S3C2416 if CPU_S3C2440 -config S3C2440_CPUFREQ - bool "S3C2440/S3C2442 CPU Frequency scaling support" - depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442) - default y - select S3C2410_CPUFREQ_UTILS - help - CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs. - config S3C2440_DMA bool help @@ -521,15 +459,15 @@ config S3C2440_XTAL_16934400 config S3C2440_PLL_12000000 bool - depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000 - default y if CPU_FREQ_S3C24XX_PLL + depends on ARM_S3C2440_CPUFREQ && S3C2440_XTAL_12000000 + default y if S3C24XX_PLL help PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals. config S3C2440_PLL_16934400 bool - depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400 - default y if CPU_FREQ_S3C24XX_PLL + depends on ARM_S3C2440_CPUFREQ && S3C2440_XTAL_16934400 + default y if S3C24XX_PLL help PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals. @@ -543,9 +481,8 @@ comment "S3C2440 Boards" config MACH_ANUBIS bool "Simtec Electronics ANUBIS" select HAVE_PATA_PLATFORM + select S3C2410_COMMON_DCLK select S3C2440_XTAL_12000000 - select S3C24XX_DCLK - select S3C24XX_GPIO_EXTRA64 select S3C24XX_SIMTEC_PM if PM select S3C_DEV_USB_HOST help @@ -561,7 +498,7 @@ config MACH_AT2440EVB config MACH_MINI2440 bool "MINI2440 development board" - select EEPROM_AT24 + select EEPROM_AT24 if I2C select LEDS_CLASS select LEDS_TRIGGERS select LEDS_TRIGGER_BACKLIGHT @@ -583,10 +520,9 @@ config MACH_NEXCODER_2440 config MACH_OSIRIS bool "Simtec IM2440D20 (OSIRIS) module" - select S3C2410_IOTIMING if S3C2440_CPUFREQ + select S3C2410_COMMON_DCLK + select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ select S3C2440_XTAL_12000000 - select S3C24XX_DCLK - select S3C24XX_GPIO_EXTRA128 select S3C24XX_SIMTEC_PM if PM select S3C_DEV_NAND select S3C_DEV_USB_HOST @@ -597,7 +533,7 @@ config MACH_OSIRIS config MACH_OSIRIS_DVS tristate "Simtec IM2440D20 (OSIRIS) Dynamic Voltage Scaling driver" depends on MACH_OSIRIS - select TPS65010 + depends on TPS65010 help Say Y/M here if you want to have dynamic voltage scaling support on the Simtec IM2440D20 (OSIRIS) module via the TPS65011. @@ -655,9 +591,9 @@ config MACH_RX1950 bool "HP iPAQ rx1950" select I2C select PM_H1940 if PM - select S3C2410_IOTIMING if S3C2440_CPUFREQ + select S3C2410_COMMON_DCLK + select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ select S3C2440_XTAL_16934400 - select S3C24XX_DCLK select S3C24XX_PWM select S3C_DEV_NAND help @@ -667,12 +603,6 @@ endif # CPU_S3C2442 if CPU_S3C2443 || CPU_S3C2416 -config S3C2443_COMMON - bool - help - Common code for the S3C2443 and similar processors, which includes - the S3C2416 and S3C2450. - config S3C2443_DMA bool help diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile index 6f46ecfc839..2235d0d3b38 100644 --- a/arch/arm/mach-s3c24xx/Makefile +++ b/arch/arm/mach-s3c24xx/Makefile @@ -17,29 +17,26 @@ obj- := obj-y += common.o obj-$(CONFIG_CPU_S3C2410) += s3c2410.o -obj-$(CONFIG_S3C2410_CPUFREQ) += cpufreq-s3c2410.o obj-$(CONFIG_S3C2410_DMA) += dma-s3c2410.o obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o -obj-$(CONFIG_CPU_S3C2412) += s3c2412.o clock-s3c2412.o -obj-$(CONFIG_S3C2412_CPUFREQ) += cpufreq-s3c2412.o +obj-$(CONFIG_CPU_S3C2412) += s3c2412.o obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o -obj-$(CONFIG_CPU_S3C2416) += s3c2416.o clock-s3c2416.o +obj-$(CONFIG_CPU_S3C2416) += s3c2416.o obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o -obj-$(CONFIG_CPU_S3C2440) += s3c2440.o clock-s3c2440.o +obj-$(CONFIG_CPU_S3C2440) += s3c2440.o obj-$(CONFIG_CPU_S3C2442) += s3c2442.o -obj-$(CONFIG_CPU_S3C244X) += s3c244x.o clock-s3c244x.o -obj-$(CONFIG_S3C2440_CPUFREQ) += cpufreq-s3c2440.o +obj-$(CONFIG_CPU_S3C244X) += s3c244x.o obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o -obj-$(CONFIG_CPU_S3C2443) += s3c2443.o clock-s3c2443.o +obj-$(CONFIG_CPU_S3C2443) += s3c2443.o # PM @@ -47,21 +44,15 @@ obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o # common code -obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o obj-$(CONFIG_S3C24XX_DMA) += dma.o -obj-$(CONFIG_S3C2410_CLOCK) += clock-s3c2410.o obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o -obj-$(CONFIG_S3C2443_COMMON) += common-s3c2443.o obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o -obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpufreq.o -obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpufreq-debugfs.o - # # machine support # following is ordered alphabetically by option text. @@ -85,6 +76,7 @@ obj-$(CONFIG_MACH_SMDK2413) += mach-smdk2413.o obj-$(CONFIG_MACH_VSTMS) += mach-vstms.o obj-$(CONFIG_MACH_SMDK2416) += mach-smdk2416.o +obj-$(CONFIG_MACH_S3C2416_DT) += mach-s3c2416-dt.o obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o diff --git a/arch/arm/mach-s3c24xx/clock-dclk.c b/arch/arm/mach-s3c24xx/clock-dclk.c deleted file mode 100644 index 1edd9b2369c..00000000000 --- a/arch/arm/mach-s3c24xx/clock-dclk.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2004-2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C24XX - definitions for DCLK and CLKOUT registers - */ - -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/clk.h> -#include <linux/io.h> - -#include <mach/regs-clock.h> -#include <mach/regs-gpio.h> - -#include <plat/clock.h> -#include <plat/cpu.h> - -/* clocks that could be registered by external code */ - -static int s3c24xx_dclk_enable(struct clk *clk, int enable) -{ - unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON); - - if (enable) - dclkcon |= clk->ctrlbit; - else - dclkcon &= ~clk->ctrlbit; - - __raw_writel(dclkcon, S3C24XX_DCLKCON); - - return 0; -} - -static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent) -{ - unsigned long dclkcon; - unsigned int uclk; - - if (parent == &clk_upll) - uclk = 1; - else if (parent == &clk_p) - uclk = 0; - else - return -EINVAL; - - clk->parent = parent; - - dclkcon = __raw_readl(S3C24XX_DCLKCON); - - if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) { - if (uclk) - dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK; - else - dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK; - } else { - if (uclk) - dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK; - else - dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK; - } - - __raw_writel(dclkcon, S3C24XX_DCLKCON); - - return 0; -} -static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate) -{ - unsigned long div; - - if ((rate == 0) || !clk->parent) - return 0; - - div = clk_get_rate(clk->parent) / rate; - if (div < 2) - div = 2; - else if (div > 16) - div = 16; - - return div; -} - -static unsigned long s3c24xx_round_dclk_rate(struct clk *clk, - unsigned long rate) -{ - unsigned long div = s3c24xx_calc_div(clk, rate); - - if (div == 0) - return 0; - - return clk_get_rate(clk->parent) / div; -} - -static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate) -{ - unsigned long mask, data, div = s3c24xx_calc_div(clk, rate); - - if (div == 0) - return -EINVAL; - - if (clk == &s3c24xx_dclk0) { - mask = S3C2410_DCLKCON_DCLK0_DIV_MASK | - S3C2410_DCLKCON_DCLK0_CMP_MASK; - data = S3C2410_DCLKCON_DCLK0_DIV(div) | - S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2); - } else if (clk == &s3c24xx_dclk1) { - mask = S3C2410_DCLKCON_DCLK1_DIV_MASK | - S3C2410_DCLKCON_DCLK1_CMP_MASK; - data = S3C2410_DCLKCON_DCLK1_DIV(div) | - S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2); - } else - return -EINVAL; - - clk->rate = clk_get_rate(clk->parent) / div; - __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data), - S3C24XX_DCLKCON); - return clk->rate; -} -static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) -{ - unsigned long mask; - unsigned long source; - - /* calculate the MISCCR setting for the clock */ - - if (parent == &clk_mpll) - source = S3C2410_MISCCR_CLK0_MPLL; - else if (parent == &clk_upll) - source = S3C2410_MISCCR_CLK0_UPLL; - else if (parent == &clk_f) - source = S3C2410_MISCCR_CLK0_FCLK; - else if (parent == &clk_h) - source = S3C2410_MISCCR_CLK0_HCLK; - else if (parent == &clk_p) - source = S3C2410_MISCCR_CLK0_PCLK; - else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0) - source = S3C2410_MISCCR_CLK0_DCLK0; - else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1) - source = S3C2410_MISCCR_CLK0_DCLK0; - else - return -EINVAL; - - clk->parent = parent; - - if (clk == &s3c24xx_clkout0) - mask = S3C2410_MISCCR_CLK0_MASK; - else { - source <<= 4; - mask = S3C2410_MISCCR_CLK1_MASK; - } - - s3c2410_modify_misccr(mask, source); - return 0; -} - -/* external clock definitions */ - -static struct clk_ops dclk_ops = { - .set_parent = s3c24xx_dclk_setparent, - .set_rate = s3c24xx_set_dclk_rate, - .round_rate = s3c24xx_round_dclk_rate, -}; - -struct clk s3c24xx_dclk0 = { - .name = "dclk0", - .ctrlbit = S3C2410_DCLKCON_DCLK0EN, - .enable = s3c24xx_dclk_enable, - .ops = &dclk_ops, -}; - -struct clk s3c24xx_dclk1 = { - .name = "dclk1", - .ctrlbit = S3C2410_DCLKCON_DCLK1EN, - .enable = s3c24xx_dclk_enable, - .ops = &dclk_ops, -}; - -static struct clk_ops clkout_ops = { - .set_parent = s3c24xx_clkout_setparent, -}; - -struct clk s3c24xx_clkout0 = { - .name = "clkout0", - .ops = &clkout_ops, -}; - -struct clk s3c24xx_clkout1 = { - .name = "clkout1", - .ops = &clkout_ops, -}; diff --git a/arch/arm/mach-s3c24xx/clock-s3c2410.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c deleted file mode 100644 index 34fffdf6fc1..00000000000 --- a/arch/arm/mach-s3c24xx/clock-s3c2410.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410,S3C2440,S3C2442 Clock control support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/device.h> -#include <linux/clk.h> -#include <linux/mutex.h> -#include <linux/delay.h> -#include <linux/serial_core.h> -#include <linux/io.h> - -#include <asm/mach/map.h> - -#include <mach/hardware.h> - -#include <plat/regs-serial.h> -#include <mach/regs-clock.h> -#include <mach/regs-gpio.h> - -#include <plat/clock.h> -#include <plat/cpu.h> - -int s3c2410_clkcon_enable(struct clk *clk, int enable) -{ - unsigned int clocks = clk->ctrlbit; - unsigned long clkcon; - - clkcon = __raw_readl(S3C2410_CLKCON); - - if (enable) - clkcon |= clocks; - else - clkcon &= ~clocks; - - /* ensure none of the special function bits set */ - clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER); - - __raw_writel(clkcon, S3C2410_CLKCON); - - return 0; -} - -static int s3c2410_upll_enable(struct clk *clk, int enable) -{ - unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); - unsigned long orig = clkslow; - - if (enable) - clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF; - else - clkslow |= S3C2410_CLKSLOW_UCLK_OFF; - - __raw_writel(clkslow, S3C2410_CLKSLOW); - - /* if we started the UPLL, then allow to settle */ - - if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF)) - udelay(200); - - return 0; -} - -/* standard clock definitions */ - -static struct clk init_clocks_off[] = { - { - .name = "nand", - .parent = &clk_h, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_NAND, - }, { - .name = "sdi", - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_SDI, - }, { - .name = "adc", - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_ADC, - }, { - .name = "i2c", - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_IIC, - }, { - .name = "iis", - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_IIS, - }, { - .name = "spi", - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_SPI, - } -}; - -static struct clk init_clocks[] = { - { - .name = "lcd", - .parent = &clk_h, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_LCDC, - }, { - .name = "gpio", - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_GPIO, - }, { - .name = "usb-host", - .parent = &clk_h, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_USBH, - }, { - .name = "usb-device", - .parent = &clk_h, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_USBD, - }, { - .name = "timers", - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_PWMT, - }, { - .name = "uart", - .devname = "s3c2410-uart.0", - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_UART0, - }, { - .name = "uart", - .devname = "s3c2410-uart.1", - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_UART1, - }, { - .name = "uart", - .devname = "s3c2410-uart.2", - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_UART2, - }, { - .name = "rtc", - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_RTC, - }, { - .name = "watchdog", - .parent = &clk_p, - .ctrlbit = 0, - }, { - .name = "usb-bus-host", - .parent = &clk_usb_bus, - }, { - .name = "usb-bus-gadget", - .parent = &clk_usb_bus, - }, -}; - -/* s3c2410_baseclk_add() - * - * Add all the clocks used by the s3c2410 or compatible CPUs - * such as the S3C2440 and S3C2442. - * - * We cannot use a system device as we are needed before any - * of the init-calls that initialise the devices are actually - * done. -*/ - -int __init s3c2410_baseclk_add(void) -{ - unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); - unsigned long clkcon = __raw_readl(S3C2410_CLKCON); - struct clk *clkp; - struct clk *xtal; - int ret; - int ptr; - - clk_upll.enable = s3c2410_upll_enable; - - if (s3c24xx_register_clock(&clk_usb_bus) < 0) - printk(KERN_ERR "failed to register usb bus clock\n"); - - /* register clocks from clock array */ - - clkp = init_clocks; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { - /* ensure that we note the clock state */ - - clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0; - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } - - /* We must be careful disabling the clocks we are not intending to - * be using at boot time, as subsystems such as the LCD which do - * their own DMA requests to the bus can cause the system to lockup - * if they where in the middle of requesting bus access. - * - * Disabling the LCD clock if the LCD is active is very dangerous, - * and therefore the bootloader should be careful to not enable - * the LCD clock if it is not needed. - */ - - /* install (and disable) the clocks we do not need immediately */ - - s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - - /* show the clock-slow value */ - - xtal = clk_get(NULL, "xtal"); - - printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n", - print_mhz(clk_get_rate(xtal) / - ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))), - (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast", - (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on", - (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on"); - - s3c_pwmclk_init(); - return 0; -} diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c deleted file mode 100644 index 2cc017da88f..00000000000 --- a/arch/arm/mach-s3c24xx/clock-s3c2412.c +++ /dev/null @@ -1,762 +0,0 @@ -/* linux/arch/arm/mach-s3c2412/clock.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2412,S3C2413 Clock control support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/device.h> -#include <linux/clk.h> -#include <linux/mutex.h> -#include <linux/delay.h> -#include <linux/serial_core.h> -#include <linux/io.h> - -#include <asm/mach/map.h> - -#include <mach/hardware.h> - -#include <plat/regs-serial.h> -#include <mach/regs-clock.h> -#include <mach/regs-gpio.h> - -#include <plat/clock.h> -#include <plat/cpu.h> - -/* We currently have to assume that the system is running - * from the XTPll input, and that all ***REFCLKs are being - * fed from it, as we cannot read the state of OM[4] from - * software. - * - * It would be possible for each board initialisation to - * set the correct muxing at initialisation -*/ - -static int s3c2412_clkcon_enable(struct clk *clk, int enable) -{ - unsigned int clocks = clk->ctrlbit; - unsigned long clkcon; - - clkcon = __raw_readl(S3C2410_CLKCON); - - if (enable) - clkcon |= clocks; - else - clkcon &= ~clocks; - - __raw_writel(clkcon, S3C2410_CLKCON); - - return 0; -} - -static int s3c2412_upll_enable(struct clk *clk, int enable) -{ - unsigned long upllcon = __raw_readl(S3C2410_UPLLCON); - unsigned long orig = upllcon; - - if (!enable) - upllcon |= S3C2412_PLLCON_OFF; - else - upllcon &= ~S3C2412_PLLCON_OFF; - - __raw_writel(upllcon, S3C2410_UPLLCON); - - /* allow ~150uS for the PLL to settle and lock */ - - if (enable && (orig & S3C2412_PLLCON_OFF)) - udelay(150); - - return 0; -} - -/* clock selections */ - -static struct clk clk_erefclk = { - .name = "erefclk", -}; - -static struct clk clk_urefclk = { - .name = "urefclk", -}; - -static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_urefclk) - clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL; - else if (parent == &clk_upll) - clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} - -static struct clk clk_usysclk = { - .name = "usysclk", - .parent = &clk_xtal, - .ops = &(struct clk_ops) { - .set_parent = s3c2412_setparent_usysclk, - }, -}; - -static struct clk clk_mrefclk = { - .name = "mrefclk", - .parent = &clk_xtal, -}; - -static struct clk clk_mdivclk = { - .name = "mdivclk", - .parent = &clk_xtal, -}; - -static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_usysclk) - clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK; - else if (parent == &clk_h) - clksrc |= S3C2412_CLKSRC_USBCLK_HCLK; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} - -static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - int div; - - if (rate > parent_rate) - return parent_rate; - - div = parent_rate / rate; - if (div > 2) - div = 2; - - return parent_rate / div; -} - -static unsigned long s3c2412_getrate_usbsrc(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2410_CLKDIVN); - - return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1); -} - -static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN); - - rate = s3c2412_roundrate_usbsrc(clk, rate); - - if ((parent_rate / rate) == 2) - clkdivn |= S3C2412_CLKDIVN_USB48DIV; - else - clkdivn &= ~S3C2412_CLKDIVN_USB48DIV; - - __raw_writel(clkdivn, S3C2410_CLKDIVN); - return 0; -} - -static struct clk clk_usbsrc = { - .name = "usbsrc", - .ops = &(struct clk_ops) { - .get_rate = s3c2412_getrate_usbsrc, - .set_rate = s3c2412_setrate_usbsrc, - .round_rate = s3c2412_roundrate_usbsrc, - .set_parent = s3c2412_setparent_usbsrc, - }, -}; - -static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_mdivclk) - clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL; - else if (parent == &clk_mpll) - clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} - -static struct clk clk_msysclk = { - .name = "msysclk", - .ops = &(struct clk_ops) { - .set_parent = s3c2412_setparent_msysclk, - }, -}; - -static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent) -{ - unsigned long flags; - unsigned long clkdiv; - unsigned long dvs; - - /* Note, we current equate fclk andf msysclk for S3C2412 */ - - if (parent == &clk_msysclk || parent == &clk_f) - dvs = 0; - else if (parent == &clk_h) - dvs = S3C2412_CLKDIVN_DVSEN; - else - return -EINVAL; - - clk->parent = parent; - - /* update this under irq lockdown, clkdivn is not protected - * by the clock system. */ - - local_irq_save(flags); - - clkdiv = __raw_readl(S3C2410_CLKDIVN); - clkdiv &= ~S3C2412_CLKDIVN_DVSEN; - clkdiv |= dvs; - __raw_writel(clkdiv, S3C2410_CLKDIVN); - - local_irq_restore(flags); - - return 0; -} - -static struct clk clk_armclk = { - .name = "armclk", - .parent = &clk_msysclk, - .ops = &(struct clk_ops) { - .set_parent = s3c2412_setparent_armclk, - }, -}; - -/* these next clocks have an divider immediately after them, - * so we can register them with their divider and leave out the - * intermediate clock stage -*/ -static unsigned long s3c2412_roundrate_clksrc(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - int div; - - if (rate > parent_rate) - return parent_rate; - - /* note, we remove the +/- 1 calculations as they cancel out */ - - div = (rate / parent_rate); - - if (div < 1) - div = 1; - else if (div > 16) - div = 16; - - return parent_rate / div; -} - -static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_erefclk) - clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL; - else if (parent == &clk_mpll) - clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} - -static unsigned long s3c2412_getrate_uart(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2410_CLKDIVN); - - div &= S3C2412_CLKDIVN_UARTDIV_MASK; - div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT; - - return parent_rate / (div + 1); -} - -static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN); - - rate = s3c2412_roundrate_clksrc(clk, rate); - - clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK; - clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT; - - __raw_writel(clkdivn, S3C2410_CLKDIVN); - return 0; -} - -static struct clk clk_uart = { - .name = "uartclk", - .ops = &(struct clk_ops) { - .get_rate = s3c2412_getrate_uart, - .set_rate = s3c2412_setrate_uart, - .set_parent = s3c2412_setparent_uart, - .round_rate = s3c2412_roundrate_clksrc, - }, -}; - -static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_erefclk) - clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL; - else if (parent == &clk_mpll) - clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} - -static unsigned long s3c2412_getrate_i2s(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2410_CLKDIVN); - - div &= S3C2412_CLKDIVN_I2SDIV_MASK; - div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT; - - return parent_rate / (div + 1); -} - -static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN); - - rate = s3c2412_roundrate_clksrc(clk, rate); - - clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK; - clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT; - - __raw_writel(clkdivn, S3C2410_CLKDIVN); - return 0; -} - -static struct clk clk_i2s = { - .name = "i2sclk", - .ops = &(struct clk_ops) { - .get_rate = s3c2412_getrate_i2s, - .set_rate = s3c2412_setrate_i2s, - .set_parent = s3c2412_setparent_i2s, - .round_rate = s3c2412_roundrate_clksrc, - }, -}; - -static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_usysclk) - clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK; - else if (parent == &clk_h) - clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} -static unsigned long s3c2412_getrate_cam(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2410_CLKDIVN); - - div &= S3C2412_CLKDIVN_CAMDIV_MASK; - div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT; - - return parent_rate / (div + 1); -} - -static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN); - - rate = s3c2412_roundrate_clksrc(clk, rate); - - clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK; - clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT; - - __raw_writel(clkdivn, S3C2410_CLKDIVN); - return 0; -} - -static struct clk clk_cam = { - .name = "camif-upll", /* same as 2440 name */ - .ops = &(struct clk_ops) { - .get_rate = s3c2412_getrate_cam, - .set_rate = s3c2412_setrate_cam, - .set_parent = s3c2412_setparent_cam, - .round_rate = s3c2412_roundrate_clksrc, - }, -}; - -/* standard clock definitions */ - -static struct clk init_clocks_disable[] = { - { - .name = "nand", - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_NAND, - }, { - .name = "sdi", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_SDI, - }, { - .name = "adc", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_ADC, - }, { - .name = "i2c", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_IIC, - }, { - .name = "iis", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_IIS, - }, { - .name = "spi", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_SPI, - } -}; - -static struct clk init_clocks[] = { - { - .name = "dma", - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_DMA0, - }, { - .name = "dma", - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_DMA1, - }, { - .name = "dma", - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_DMA2, - }, { - .name = "dma", - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_DMA3, - }, { - .name = "lcd", - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_LCDC, - }, { - .name = "gpio", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_GPIO, - }, { - .name = "usb-host", - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_USBH, - }, { - .name = "usb-device", - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_USBD, - }, { - .name = "timers", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_PWMT, - }, { - .name = "uart", - .devname = "s3c2412-uart.0", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_UART0, - }, { - .name = "uart", - .devname = "s3c2412-uart.1", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_UART1, - }, { - .name = "uart", - .devname = "s3c2412-uart.2", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_UART2, - }, { - .name = "rtc", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_RTC, - }, { - .name = "watchdog", - .parent = &clk_p, - .ctrlbit = 0, - }, { - .name = "usb-bus-gadget", - .parent = &clk_usb_bus, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_USB_DEV48, - }, { - .name = "usb-bus-host", - .parent = &clk_usb_bus, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_USB_HOST48, - } -}; - -/* clocks to add where we need to check their parentage */ - -struct clk_init { - struct clk *clk; - unsigned int bit; - struct clk *src_0; - struct clk *src_1; -}; - -static struct clk_init clks_src[] __initdata = { - { - .clk = &clk_usysclk, - .bit = S3C2412_CLKSRC_USBCLK_HCLK, - .src_0 = &clk_urefclk, - .src_1 = &clk_upll, - }, { - .clk = &clk_i2s, - .bit = S3C2412_CLKSRC_I2SCLK_MPLL, - .src_0 = &clk_erefclk, - .src_1 = &clk_mpll, - }, { - .clk = &clk_cam, - .bit = S3C2412_CLKSRC_CAMCLK_HCLK, - .src_0 = &clk_usysclk, - .src_1 = &clk_h, - }, { - .clk = &clk_msysclk, - .bit = S3C2412_CLKSRC_MSYSCLK_MPLL, - .src_0 = &clk_mdivclk, - .src_1 = &clk_mpll, - }, { - .clk = &clk_uart, - .bit = S3C2412_CLKSRC_UARTCLK_MPLL, - .src_0 = &clk_erefclk, - .src_1 = &clk_mpll, - }, { - .clk = &clk_usbsrc, - .bit = S3C2412_CLKSRC_USBCLK_HCLK, - .src_0 = &clk_usysclk, - .src_1 = &clk_h, - /* here we assume OM[4] select xtal */ - }, { - .clk = &clk_erefclk, - .bit = S3C2412_CLKSRC_EREFCLK_EXTCLK, - .src_0 = &clk_xtal, - .src_1 = &clk_ext, - }, { - .clk = &clk_urefclk, - .bit = S3C2412_CLKSRC_UREFCLK_EXTCLK, - .src_0 = &clk_xtal, - .src_1 = &clk_ext, - }, -}; - -/* s3c2412_clk_initparents - * - * Initialise the parents for the clocks that we get at start-time -*/ - -static void __init s3c2412_clk_initparents(void) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - struct clk_init *cip = clks_src; - struct clk *src; - int ptr; - int ret; - - for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) { - ret = s3c24xx_register_clock(cip->clk); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - cip->clk->name, ret); - } - - src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0; - - printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name); - clk_set_parent(cip->clk, src); - } -} - -/* clocks to add straight away */ - -static struct clk *clks[] __initdata = { - &clk_ext, - &clk_usb_bus, - &clk_mrefclk, - &clk_armclk, -}; - -static struct clk_lookup s3c2412_clk_lookup[] = { - CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), - CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), - CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk), -}; - -int __init s3c2412_baseclk_add(void) -{ - unsigned long clkcon = __raw_readl(S3C2410_CLKCON); - unsigned int dvs; - struct clk *clkp; - int ret; - int ptr; - - clk_upll.enable = s3c2412_upll_enable; - clk_usb_bus.parent = &clk_usbsrc; - clk_usb_bus.rate = 0x0; - - clk_f.parent = &clk_msysclk; - - s3c2412_clk_initparents(); - - for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { - clkp = clks[ptr]; - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } - - /* set the dvs state according to what we got at boot time */ - - dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN; - - if (dvs) - clk_armclk.parent = &clk_h; - - printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off"); - - /* ensure usb bus clock is within correct rate of 48MHz */ - - if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) { - printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n"); - - /* for the moment, let's use the UPLL, and see if we can - * get 48MHz */ - - clk_set_parent(&clk_usysclk, &clk_upll); - clk_set_parent(&clk_usbsrc, &clk_usysclk); - clk_set_rate(&clk_usbsrc, 48*1000*1000); - } - - printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n", - (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on", - print_mhz(clk_get_rate(&clk_upll)), - print_mhz(clk_get_rate(&clk_usb_bus))); - - /* register clocks from clock array */ - - clkp = init_clocks; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { - /* ensure that we note the clock state */ - - clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0; - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } - - /* We must be careful disabling the clocks we are not intending to - * be using at boot time, as subsystems such as the LCD which do - * their own DMA requests to the bus can cause the system to lockup - * if they where in the middle of requesting bus access. - * - * Disabling the LCD clock if the LCD is active is very dangerous, - * and therefore the bootloader should be careful to not enable - * the LCD clock if it is not needed. - */ - - /* install (and disable) the clocks we do not need immediately */ - - clkp = init_clocks_disable; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - - s3c2412_clkcon_enable(clkp, 0); - } - - clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup)); - s3c_pwmclk_init(); - return 0; -} diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c deleted file mode 100644 index 036056cea57..00000000000 --- a/arch/arm/mach-s3c24xx/clock-s3c2416.c +++ /dev/null @@ -1,173 +0,0 @@ -/* linux/arch/arm/mach-s3c2416/clock.c - * - * Copyright (c) 2010 Simtec Electronics - * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org> - * - * S3C2416 Clock control support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include <linux/init.h> -#include <linux/clk.h> - -#include <plat/clock.h> -#include <plat/clock-clksrc.h> -#include <plat/cpu.h> - -#include <plat/cpu-freq.h> -#include <plat/pll.h> - -#include <asm/mach/map.h> - -#include <mach/regs-clock.h> -#include <mach/regs-s3c2443-clock.h> - -/* armdiv - * - * this clock is sourced from msysclk and can have a number of - * divider values applied to it to then be fed into armclk. - * The real clock definition is done in s3c2443-clock.c, - * only the armdiv divisor table must be defined here. -*/ - -static unsigned int armdiv[8] = { - [0] = 1, - [1] = 2, - [2] = 3, - [3] = 4, - [5] = 6, - [7] = 8, -}; - -static struct clksrc_clk hsspi_eplldiv = { - .clk = { - .name = "hsspi-eplldiv", - .parent = &clk_esysclk.clk, - .ctrlbit = (1 << 14), - .enable = s3c2443_clkcon_enable_s, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 }, -}; - -static struct clk *hsspi_sources[] = { - [0] = &hsspi_eplldiv.clk, - [1] = NULL, /* to fix */ -}; - -static struct clksrc_clk hsspi_mux = { - .clk = { - .name = "hsspi-if", - }, - .sources = &(struct clksrc_sources) { - .sources = hsspi_sources, - .nr_sources = ARRAY_SIZE(hsspi_sources), - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 }, -}; - -static struct clksrc_clk hsmmc_div[] = { - [0] = { - .clk = { - .name = "hsmmc-div", - .devname = "s3c-sdhci.0", - .parent = &clk_esysclk.clk, - }, - .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 }, - }, - [1] = { - .clk = { - .name = "hsmmc-div", - .devname = "s3c-sdhci.1", - .parent = &clk_esysclk.clk, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, - }, -}; - -static struct clksrc_clk hsmmc_mux0 = { - .clk = { - .name = "hsmmc-if", - .devname = "s3c-sdhci.0", - .ctrlbit = (1 << 6), - .enable = s3c2443_clkcon_enable_s, - }, - .sources = &(struct clksrc_sources) { - .nr_sources = 2, - .sources = (struct clk * []) { - [0] = &hsmmc_div[0].clk, - [1] = NULL, /* to fix */ - }, - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 }, -}; - -static struct clksrc_clk hsmmc_mux1 = { - .clk = { - .name = "hsmmc-if", - .devname = "s3c-sdhci.1", - .ctrlbit = (1 << 12), - .enable = s3c2443_clkcon_enable_s, - }, - .sources = &(struct clksrc_sources) { - .nr_sources = 2, - .sources = (struct clk * []) { - [0] = &hsmmc_div[1].clk, - [1] = NULL, /* to fix */ - }, - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 }, -}; - -static struct clk hsmmc0_clk = { - .name = "hsmmc", - .devname = "s3c-sdhci.0", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2416_HCLKCON_HSMMC0, -}; - -static struct clksrc_clk *clksrcs[] __initdata = { - &hsspi_eplldiv, - &hsspi_mux, - &hsmmc_div[0], - &hsmmc_div[1], - &hsmmc_mux0, - &hsmmc_mux1, -}; - -static struct clk_lookup s3c2416_clk_lookup[] = { - CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk), - CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk), - CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk), - /* s3c2443-spi.0 is used on s3c2416 and s3c2450 as well */ - CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk), -}; - -void __init s3c2416_init_clocks(int xtal) -{ - u32 epllcon = __raw_readl(S3C2443_EPLLCON); - u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4); - int ptr; - - /* s3c2416 EPLL compatible with s3c64xx */ - clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1); - - clk_epll.parent = &clk_epllref.clk; - - s3c2443_common_init_clocks(xtal, s3c2416_get_pll, - armdiv, ARRAY_SIZE(armdiv), - S3C2416_CLKDIV0_ARMDIV_MASK); - - for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) - s3c_register_clksrc(clksrcs[ptr], 1); - - s3c24xx_register_clock(&hsmmc0_clk); - clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup)); - - s3c_pwmclk_init(); - -} diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c deleted file mode 100644 index 1069b568082..00000000000 --- a/arch/arm/mach-s3c24xx/clock-s3c2440.c +++ /dev/null @@ -1,214 +0,0 @@ -/* linux/arch/arm/mach-s3c2440/clock.c - * - * Copyright (c) 2004-2005 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2440 Clock support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/device.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/mutex.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/serial_core.h> - -#include <mach/hardware.h> -#include <linux/atomic.h> -#include <asm/irq.h> - -#include <mach/regs-clock.h> - -#include <plat/clock.h> -#include <plat/cpu.h> -#include <plat/regs-serial.h> - -/* S3C2440 extended clock support */ - -static unsigned long s3c2440_camif_upll_round(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - int div; - - if (rate > parent_rate) - return parent_rate; - - /* note, we remove the +/- 1 calculations for the divisor */ - - div = (parent_rate / rate) / 2; - - if (div < 1) - div = 1; - else if (div > 16) - div = 16; - - return parent_rate / (div * 2); -} - -static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); - - rate = s3c2440_camif_upll_round(clk, rate); - - camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK); - - if (rate != parent_rate) { - camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; - camdivn |= (((parent_rate / rate) / 2) - 1); - } - - __raw_writel(camdivn, S3C2440_CAMDIVN); - - return 0; -} - -static unsigned long s3c2440_camif_upll_getrate(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); - - if (!(camdivn & S3C2440_CAMDIVN_CAMCLK_SEL)) - return parent_rate; - - camdivn &= S3C2440_CAMDIVN_CAMCLK_MASK; - - return parent_rate / (camdivn + 1) / 2; -} - -/* Extra S3C2440 clocks */ - -static struct clk s3c2440_clk_cam = { - .name = "camif", - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2440_CLKCON_CAMERA, -}; - -static struct clk s3c2440_clk_cam_upll = { - .name = "camif-upll", - .ops = &(struct clk_ops) { - .set_rate = s3c2440_camif_upll_setrate, - .get_rate = s3c2440_camif_upll_getrate, - .round_rate = s3c2440_camif_upll_round, - }, -}; - -static struct clk s3c2440_clk_ac97 = { - .name = "ac97", - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2440_CLKCON_AC97, -}; - -#define S3C24XX_VA_UART0 (S3C_VA_UART) -#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 ) -#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 ) -#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 ) - -static unsigned long s3c2440_fclk_n_getrate(struct clk *clk) -{ - unsigned long ucon0, ucon1, ucon2, divisor; - - /* the fun of calculating the uart divisors on the s3c2440 */ - ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON); - ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON); - ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON); - - ucon0 &= S3C2440_UCON0_DIVMASK; - ucon1 &= S3C2440_UCON1_DIVMASK; - ucon2 &= S3C2440_UCON2_DIVMASK; - - if (ucon0 != 0) - divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6; - else if (ucon1 != 0) - divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21; - else if (ucon2 != 0) - divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36; - else - /* manual calims 44, seems to be 9 */ - divisor = 9; - - return clk_get_rate(clk->parent) / divisor; -} - -static struct clk s3c2440_clk_fclk_n = { - .name = "fclk_n", - .parent = &clk_f, - .ops = &(struct clk_ops) { - .get_rate = s3c2440_fclk_n_getrate, - }, -}; - -static struct clk_lookup s3c2440_clk_lookup[] = { - CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), - CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), - CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n), - CLKDEV_INIT("s3c2440-camif", "camera", &s3c2440_clk_cam_upll), -}; - -static int __init_refok s3c2440_clk_add(struct device *dev, struct subsys_interface *sif) -{ - struct clk *clock_upll; - struct clk *clock_h; - struct clk *clock_p; - - clock_p = clk_get(NULL, "pclk"); - clock_h = clk_get(NULL, "hclk"); - clock_upll = clk_get(NULL, "upll"); - - if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) { - printk(KERN_ERR "S3C2440: Failed to get parent clocks\n"); - return -EINVAL; - } - - s3c2440_clk_cam.parent = clock_h; - s3c2440_clk_ac97.parent = clock_p; - s3c2440_clk_cam_upll.parent = clock_upll; - s3c24xx_register_clock(&s3c2440_clk_fclk_n); - - s3c24xx_register_clock(&s3c2440_clk_ac97); - s3c24xx_register_clock(&s3c2440_clk_cam); - s3c24xx_register_clock(&s3c2440_clk_cam_upll); - clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup)); - - clk_disable(&s3c2440_clk_ac97); - clk_disable(&s3c2440_clk_cam); - - return 0; -} - -static struct subsys_interface s3c2440_clk_interface = { - .name = "s3c2440_clk", - .subsys = &s3c2440_subsys, - .add_dev = s3c2440_clk_add, -}; - -static __init int s3c24xx_clk_init(void) -{ - return subsys_interface_register(&s3c2440_clk_interface); -} - -arch_initcall(s3c24xx_clk_init); diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c deleted file mode 100644 index 0a53051b078..00000000000 --- a/arch/arm/mach-s3c24xx/clock-s3c2443.c +++ /dev/null @@ -1,214 +0,0 @@ -/* linux/arch/arm/mach-s3c2443/clock.c - * - * Copyright (c) 2007, 2010 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2443 Clock control support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include <linux/init.h> - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/device.h> -#include <linux/clk.h> -#include <linux/mutex.h> -#include <linux/serial_core.h> -#include <linux/io.h> - -#include <asm/mach/map.h> - -#include <mach/hardware.h> - -#include <mach/regs-s3c2443-clock.h> - -#include <plat/cpu-freq.h> - -#include <plat/clock.h> -#include <plat/clock-clksrc.h> -#include <plat/cpu.h> - -/* We currently have to assume that the system is running - * from the XTPll input, and that all ***REFCLKs are being - * fed from it, as we cannot read the state of OM[4] from - * software. - * - * It would be possible for each board initialisation to - * set the correct muxing at initialisation -*/ - -/* clock selections */ - -/* armdiv - * - * this clock is sourced from msysclk and can have a number of - * divider values applied to it to then be fed into armclk. - * The real clock definition is done in s3c2443-clock.c, - * only the armdiv divisor table must be defined here. -*/ - -static unsigned int armdiv[16] = { - [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1, - [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2, - [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3, - [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4, - [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6, - [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8, - [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12, - [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16, -}; - -/* hsspi - * - * high-speed spi clock, sourced from esysclk -*/ - -static struct clksrc_clk clk_hsspi = { - .clk = { - .name = "hsspi-if", - .parent = &clk_esysclk.clk, - .ctrlbit = S3C2443_SCLKCON_HSSPICLK, - .enable = s3c2443_clkcon_enable_s, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 }, -}; - - -/* clk_hsmcc_div - * - * this clock is sourced from epll, and is fed through a divider, - * to a mux controlled by sclkcon where either it or a extclk can - * be fed to the hsmmc block -*/ - -static struct clksrc_clk clk_hsmmc_div = { - .clk = { - .name = "hsmmc-div", - .devname = "s3c-sdhci.1", - .parent = &clk_esysclk.clk, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, -}; - -static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2443_SCLKCON); - - clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT | - S3C2443_SCLKCON_HSMMCCLK_EPLL); - - if (parent == &clk_epll) - clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL; - else if (parent == &clk_ext) - clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT; - else - return -EINVAL; - - if (clk->usage > 0) { - __raw_writel(clksrc, S3C2443_SCLKCON); - } - - clk->parent = parent; - return 0; -} - -static int s3c2443_enable_hsmmc(struct clk *clk, int enable) -{ - return s3c2443_setparent_hsmmc(clk, clk->parent); -} - -static struct clk clk_hsmmc = { - .name = "hsmmc-if", - .devname = "s3c-sdhci.1", - .parent = &clk_hsmmc_div.clk, - .enable = s3c2443_enable_hsmmc, - .ops = &(struct clk_ops) { - .set_parent = s3c2443_setparent_hsmmc, - }, -}; - -/* standard clock definitions */ - -static struct clk init_clocks_off[] = { - { - .name = "sdi", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_SDI, - }, { - .name = "spi", - .devname = "s3c2410-spi.0", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_SPI1, - } -}; - -/* clocks to add straight away */ - -static struct clksrc_clk *clksrcs[] __initdata = { - &clk_hsspi, - &clk_hsmmc_div, -}; - -static struct clk *clks[] __initdata = { - &clk_hsmmc, -}; - -static struct clk_lookup s3c2443_clk_lookup[] = { - CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc), - CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk), -}; - -void __init s3c2443_init_clocks(int xtal) -{ - unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); - int ptr; - - clk_epll.rate = s3c2443_get_epll(epllcon, xtal); - clk_epll.parent = &clk_epllref.clk; - - s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, - armdiv, ARRAY_SIZE(armdiv), - S3C2443_CLKDIV0_ARMDIV_MASK); - - s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); - - for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) - s3c_register_clksrc(clksrcs[ptr], 1); - - /* We must be careful disabling the clocks we are not intending to - * be using at boot time, as subsystems such as the LCD which do - * their own DMA requests to the bus can cause the system to lockup - * if they where in the middle of requesting bus access. - * - * Disabling the LCD clock if the LCD is active is very dangerous, - * and therefore the bootloader should be careful to not enable - * the LCD clock if it is not needed. - */ - - /* install (and disable) the clocks we do not need immediately */ - - s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup)); - - s3c_pwmclk_init(); -} diff --git a/arch/arm/mach-s3c24xx/clock-s3c244x.c b/arch/arm/mach-s3c24xx/clock-s3c244x.c deleted file mode 100644 index 6d9b688c442..00000000000 --- a/arch/arm/mach-s3c24xx/clock-s3c244x.c +++ /dev/null @@ -1,141 +0,0 @@ -/* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c - * - * Copyright (c) 2004-2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2440/S3C2442 Common clock support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/device.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/clk.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <linux/atomic.h> -#include <asm/irq.h> - -#include <mach/regs-clock.h> - -#include <plat/clock.h> -#include <plat/cpu.h> - -static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent) -{ - unsigned long camdivn; - unsigned long dvs; - - if (parent == &clk_f) - dvs = 0; - else if (parent == &clk_h) - dvs = S3C2440_CAMDIVN_DVSEN; - else - return -EINVAL; - - clk->parent = parent; - - camdivn = __raw_readl(S3C2440_CAMDIVN); - camdivn &= ~S3C2440_CAMDIVN_DVSEN; - camdivn |= dvs; - __raw_writel(camdivn, S3C2440_CAMDIVN); - - return 0; -} - -static struct clk clk_arm = { - .name = "armclk", - .id = -1, - .ops = &(struct clk_ops) { - .set_parent = s3c2440_setparent_armclk, - }, -}; - -static int s3c244x_clk_add(struct device *dev, struct subsys_interface *sif) -{ - unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); - unsigned long clkdivn; - struct clk *clock_upll; - int ret; - - printk("S3C244X: Clock Support, DVS %s\n", - (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off"); - - clk_arm.parent = (camdivn & S3C2440_CAMDIVN_DVSEN) ? &clk_h : &clk_f; - - ret = s3c24xx_register_clock(&clk_arm); - if (ret < 0) { - printk(KERN_ERR "S3C24XX: Failed to add armclk (%d)\n", ret); - return ret; - } - - clock_upll = clk_get(NULL, "upll"); - if (IS_ERR(clock_upll)) { - printk(KERN_ERR "S3C244X: Failed to get upll clock\n"); - return -ENOENT; - } - - /* check rate of UPLL, and if it is near 96MHz, then change - * to using half the UPLL rate for the system */ - - if (clk_get_rate(clock_upll) > (94 * MHZ)) { - clk_usb_bus.rate = clk_get_rate(clock_upll) / 2; - - spin_lock(&clocks_lock); - - clkdivn = __raw_readl(S3C2410_CLKDIVN); - clkdivn |= S3C2440_CLKDIVN_UCLK; - __raw_writel(clkdivn, S3C2410_CLKDIVN); - - spin_unlock(&clocks_lock); - } - - return 0; -} - -static struct subsys_interface s3c2440_clk_interface = { - .name = "s3c2440_clk", - .subsys = &s3c2440_subsys, - .add_dev = s3c244x_clk_add, -}; - -static int s3c2440_clk_init(void) -{ - return subsys_interface_register(&s3c2440_clk_interface); -} - -arch_initcall(s3c2440_clk_init); - -static struct subsys_interface s3c2442_clk_interface = { - .name = "s3c2442_clk", - .subsys = &s3c2442_subsys, - .add_dev = s3c244x_clk_add, -}; - -static int s3c2442_clk_init(void) -{ - return subsys_interface_register(&s3c2442_clk_interface); -} - -arch_initcall(s3c2442_clk_init); diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c deleted file mode 100644 index f6b9f2ef01b..00000000000 --- a/arch/arm/mach-s3c24xx/common-s3c2443.c +++ /dev/null @@ -1,675 +0,0 @@ -/* - * Common code for SoCs starting with the S3C2443 - * - * Copyright (c) 2007, 2010 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/io.h> - -#include <mach/regs-s3c2443-clock.h> - -#include <plat/clock.h> -#include <plat/clock-clksrc.h> -#include <plat/cpu.h> - -#include <plat/cpu-freq.h> - - -static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable) -{ - u32 ctrlbit = clk->ctrlbit; - u32 con = __raw_readl(reg); - - if (enable) - con |= ctrlbit; - else - con &= ~ctrlbit; - - __raw_writel(con, reg); - return 0; -} - -int s3c2443_clkcon_enable_h(struct clk *clk, int enable) -{ - return s3c2443_gate(S3C2443_HCLKCON, clk, enable); -} - -int s3c2443_clkcon_enable_p(struct clk *clk, int enable) -{ - return s3c2443_gate(S3C2443_PCLKCON, clk, enable); -} - -int s3c2443_clkcon_enable_s(struct clk *clk, int enable) -{ - return s3c2443_gate(S3C2443_SCLKCON, clk, enable); -} - -/* mpllref is a direct descendant of clk_xtal by default, but it is not - * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as - * such directly equating the two source clocks is impossible. - */ -static struct clk clk_mpllref = { - .name = "mpllref", - .parent = &clk_xtal, -}; - -static struct clk *clk_epllref_sources[] = { - [0] = &clk_mpllref, - [1] = &clk_mpllref, - [2] = &clk_xtal, - [3] = &clk_ext, -}; - -struct clksrc_clk clk_epllref = { - .clk = { - .name = "epllref", - }, - .sources = &(struct clksrc_sources) { - .sources = clk_epllref_sources, - .nr_sources = ARRAY_SIZE(clk_epllref_sources), - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 }, -}; - -/* esysclk - * - * this is sourced from either the EPLL or the EPLLref clock -*/ - -static struct clk *clk_sysclk_sources[] = { - [0] = &clk_epllref.clk, - [1] = &clk_epll, -}; - -struct clksrc_clk clk_esysclk = { - .clk = { - .name = "esysclk", - .parent = &clk_epll, - }, - .sources = &(struct clksrc_sources) { - .sources = clk_sysclk_sources, - .nr_sources = ARRAY_SIZE(clk_sysclk_sources), - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 }, -}; - -static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2443_CLKDIV0); - - div &= S3C2443_CLKDIV0_EXTDIV_MASK; - div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */ - - return parent_rate / (div + 1); -} - -static struct clk clk_mdivclk = { - .name = "mdivclk", - .parent = &clk_mpllref, - .ops = &(struct clk_ops) { - .get_rate = s3c2443_getrate_mdivclk, - }, -}; - -static struct clk *clk_msysclk_sources[] = { - [0] = &clk_mpllref, - [1] = &clk_mpll, - [2] = &clk_mdivclk, - [3] = &clk_mpllref, -}; - -static struct clksrc_clk clk_msysclk = { - .clk = { - .name = "msysclk", - .parent = &clk_xtal, - }, - .sources = &(struct clksrc_sources) { - .sources = clk_msysclk_sources, - .nr_sources = ARRAY_SIZE(clk_msysclk_sources), - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 }, -}; - -/* prediv - * - * this divides the msysclk down to pass to h/p/etc. - */ - -static unsigned long s3c2443_prediv_getrate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); - - clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK; - clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT; - - return rate / (clkdiv0 + 1); -} - -static struct clk clk_prediv = { - .name = "prediv", - .parent = &clk_msysclk.clk, - .ops = &(struct clk_ops) { - .get_rate = s3c2443_prediv_getrate, - }, -}; - -/* hclk divider - * - * divides the prediv and provides the hclk. - */ - -static unsigned long s3c2443_hclkdiv_getrate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); - - clkdiv0 &= S3C2443_CLKDIV0_HCLKDIV_MASK; - - return rate / (clkdiv0 + 1); -} - -static struct clk_ops clk_h_ops = { - .get_rate = s3c2443_hclkdiv_getrate, -}; - -/* pclk divider - * - * divides the hclk and provides the pclk. - */ - -static unsigned long s3c2443_pclkdiv_getrate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); - - clkdiv0 = ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 1 : 0); - - return rate / (clkdiv0 + 1); -} - -static struct clk_ops clk_p_ops = { - .get_rate = s3c2443_pclkdiv_getrate, -}; - -/* armdiv - * - * this clock is sourced from msysclk and can have a number of - * divider values applied to it to then be fed into armclk. -*/ - -static unsigned int *armdiv; -static int nr_armdiv; -static int armdivmask; - -static unsigned long s3c2443_armclk_roundrate(struct clk *clk, - unsigned long rate) -{ - unsigned long parent = clk_get_rate(clk->parent); - unsigned long calc; - unsigned best = 256; /* bigger than any value */ - unsigned div; - int ptr; - - if (!nr_armdiv) - return -EINVAL; - - for (ptr = 0; ptr < nr_armdiv; ptr++) { - div = armdiv[ptr]; - if (div) { - /* cpufreq provides 266mhz as 266666000 not 266666666 */ - calc = (parent / div / 1000) * 1000; - if (calc <= rate && div < best) - best = div; - } - } - - return parent / best; -} - -static unsigned long s3c2443_armclk_getrate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned long clkcon0; - int val; - - if (!nr_armdiv || !armdivmask) - return -EINVAL; - - clkcon0 = __raw_readl(S3C2443_CLKDIV0); - clkcon0 &= armdivmask; - val = clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT; - - return rate / armdiv[val]; -} - -static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate) -{ - unsigned long parent = clk_get_rate(clk->parent); - unsigned long calc; - unsigned div; - unsigned best = 256; /* bigger than any value */ - int ptr; - int val = -1; - - if (!nr_armdiv || !armdivmask) - return -EINVAL; - - for (ptr = 0; ptr < nr_armdiv; ptr++) { - div = armdiv[ptr]; - if (div) { - /* cpufreq provides 266mhz as 266666000 not 266666666 */ - calc = (parent / div / 1000) * 1000; - if (calc <= rate && div < best) { - best = div; - val = ptr; - } - } - } - - if (val >= 0) { - unsigned long clkcon0; - - clkcon0 = __raw_readl(S3C2443_CLKDIV0); - clkcon0 &= ~armdivmask; - clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT; - __raw_writel(clkcon0, S3C2443_CLKDIV0); - } - - return (val == -1) ? -EINVAL : 0; -} - -static struct clk clk_armdiv = { - .name = "armdiv", - .parent = &clk_msysclk.clk, - .ops = &(struct clk_ops) { - .round_rate = s3c2443_armclk_roundrate, - .get_rate = s3c2443_armclk_getrate, - .set_rate = s3c2443_armclk_setrate, - }, -}; - -/* armclk - * - * this is the clock fed into the ARM core itself, from armdiv or from hclk. - */ - -static struct clk *clk_arm_sources[] = { - [0] = &clk_armdiv, - [1] = &clk_h, -}; - -static struct clksrc_clk clk_arm = { - .clk = { - .name = "armclk", - }, - .sources = &(struct clksrc_sources) { - .sources = clk_arm_sources, - .nr_sources = ARRAY_SIZE(clk_arm_sources), - }, - .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 }, -}; - -/* usbhost - * - * usb host bus-clock, usually 48MHz to provide USB bus clock timing -*/ - -static struct clksrc_clk clk_usb_bus_host = { - .clk = { - .name = "usb-bus-host-parent", - .parent = &clk_esysclk.clk, - .ctrlbit = S3C2443_SCLKCON_USBHOST, - .enable = s3c2443_clkcon_enable_s, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 }, -}; - -/* common clksrc clocks */ - -static struct clksrc_clk clksrc_clks[] = { - { - /* camera interface bus-clock, divided down from esysclk */ - .clk = { - .name = "camif-upll", /* same as 2440 name */ - .parent = &clk_esysclk.clk, - .ctrlbit = S3C2443_SCLKCON_CAMCLK, - .enable = s3c2443_clkcon_enable_s, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 }, - }, { - .clk = { - .name = "display-if", - .parent = &clk_esysclk.clk, - .ctrlbit = S3C2443_SCLKCON_DISPCLK, - .enable = s3c2443_clkcon_enable_s, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 }, - }, -}; - -static struct clksrc_clk clk_esys_uart = { - /* ART baud-rate clock sourced from esysclk via a divisor */ - .clk = { - .name = "uartclk", - .parent = &clk_esysclk.clk, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, -}; - -static struct clk clk_i2s_ext = { - .name = "i2s-ext", -}; - -/* i2s_eplldiv - * - * This clock is the output from the I2S divisor of ESYSCLK, and is separate - * from the mux that comes after it (cannot merge into one single clock) -*/ - -static struct clksrc_clk clk_i2s_eplldiv = { - .clk = { - .name = "i2s-eplldiv", - .parent = &clk_esysclk.clk, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, }, -}; - -/* i2s-ref - * - * i2s bus reference clock, selectable from external, esysclk or epllref - * - * Note, this used to be two clocks, but was compressed into one. -*/ - -static struct clk *clk_i2s_srclist[] = { - [0] = &clk_i2s_eplldiv.clk, - [1] = &clk_i2s_ext, - [2] = &clk_epllref.clk, - [3] = &clk_epllref.clk, -}; - -static struct clksrc_clk clk_i2s = { - .clk = { - .name = "i2s-if", - .ctrlbit = S3C2443_SCLKCON_I2SCLK, - .enable = s3c2443_clkcon_enable_s, - - }, - .sources = &(struct clksrc_sources) { - .sources = clk_i2s_srclist, - .nr_sources = ARRAY_SIZE(clk_i2s_srclist), - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 }, -}; - -static struct clk init_clocks_off[] = { - { - .name = "iis", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_IIS, - }, { - .name = "adc", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_ADC, - }, { - .name = "i2c", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_IIC, - } -}; - -static struct clk init_clocks[] = { - { - .name = "dma", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA0, - }, { - .name = "dma", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA1, - }, { - .name = "dma", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA2, - }, { - .name = "dma", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA3, - }, { - .name = "dma", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA4, - }, { - .name = "dma", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA5, - }, { - .name = "gpio", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_GPIO, - }, { - .name = "usb-host", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_USBH, - }, { - .name = "usb-device", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_USBD, - }, { - .name = "lcd", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_LCDC, - - }, { - .name = "timers", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_PWMT, - }, { - .name = "cfc", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_CFC, - }, { - .name = "ssmc", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_SSMC, - }, { - .name = "uart", - .devname = "s3c2440-uart.0", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_UART0, - }, { - .name = "uart", - .devname = "s3c2440-uart.1", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_UART1, - }, { - .name = "uart", - .devname = "s3c2440-uart.2", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_UART2, - }, { - .name = "uart", - .devname = "s3c2440-uart.3", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_UART3, - }, { - .name = "rtc", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_RTC, - }, { - .name = "watchdog", - .parent = &clk_p, - .ctrlbit = S3C2443_PCLKCON_WDT, - }, { - .name = "ac97", - .parent = &clk_p, - .ctrlbit = S3C2443_PCLKCON_AC97, - }, { - .name = "nand", - .parent = &clk_h, - }, { - .name = "usb-bus-host", - .parent = &clk_usb_bus_host.clk, - } -}; - -static struct clk hsmmc1_clk = { - .name = "hsmmc", - .devname = "s3c-sdhci.1", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_HSMMC, -}; - -static struct clk hsspi_clk = { - .name = "spi", - .devname = "s3c2443-spi.0", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_HSSPI, -}; - -/* EPLLCON compatible enough to get on/off information */ - -void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll) -{ - unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); - unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); - struct clk *xtal_clk; - unsigned long xtal; - unsigned long pll; - int ptr; - - xtal_clk = clk_get(NULL, "xtal"); - xtal = clk_get_rate(xtal_clk); - clk_put(xtal_clk); - - pll = get_mpll(mpllcon, xtal); - clk_msysclk.clk.rate = pll; - clk_mpll.rate = pll; - - printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n", - (mpllcon & S3C2443_PLLCON_OFF) ? "off" : "on", - print_mhz(pll), print_mhz(clk_get_rate(&clk_armdiv)), - print_mhz(clk_get_rate(&clk_h)), - print_mhz(clk_get_rate(&clk_p))); - - for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++) - s3c_set_clksrc(&clksrc_clks[ptr], true); - - /* ensure usb bus clock is within correct rate of 48MHz */ - - if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) { - printk(KERN_INFO "Warning: USB host bus not at 48MHz\n"); - clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000); - } - - printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n", - (epllcon & S3C2443_PLLCON_OFF) ? "off" : "on", - print_mhz(clk_get_rate(&clk_epll)), - print_mhz(clk_get_rate(&clk_usb_bus))); -} - -static struct clk *clks[] __initdata = { - &clk_prediv, - &clk_mpllref, - &clk_mdivclk, - &clk_ext, - &clk_epll, - &clk_usb_bus, - &clk_armdiv, - &hsmmc1_clk, - &hsspi_clk, -}; - -static struct clksrc_clk *clksrcs[] __initdata = { - &clk_i2s_eplldiv, - &clk_i2s, - &clk_usb_bus_host, - &clk_epllref, - &clk_esysclk, - &clk_msysclk, - &clk_arm, -}; - -static struct clk_lookup s3c2443_clk_lookup[] = { - CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), - CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), - CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), - CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk), - CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk), -}; - -void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, - unsigned int *divs, int nr_divs, - int divmask) -{ - int ptr; - - armdiv = divs; - nr_armdiv = nr_divs; - armdivmask = divmask; - - /* s3c2443 parents h clock from prediv */ - clk_h.parent = &clk_prediv; - clk_h.ops = &clk_h_ops; - - /* and p clock from h clock */ - clk_p.parent = &clk_h; - clk_p.ops = &clk_p_ops; - - clk_usb_bus.parent = &clk_usb_bus_host.clk; - clk_epll.parent = &clk_epllref.clk; - - s3c24xx_register_baseclocks(xtal); - s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); - - for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) - s3c_register_clksrc(clksrcs[ptr], 1); - - s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks)); - s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); - - /* See s3c2443/etc notes on disabling clocks at init time */ - s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup)); - - s3c2443_common_setup_clocks(get_mpll); -} diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c index 404444dd384..e9fbcc91c5c 100644 --- a/arch/arm/mach-s3c24xx/common-smdk.c +++ b/arch/arm/mach-s3c24xx/common-smdk.c @@ -37,8 +37,8 @@ #include <asm/irq.h> #include <mach/regs-gpio.h> +#include <mach/gpio-samsung.h> #include <linux/platform_data/leds-s3c24xx.h> - #include <linux/platform_data/mtd-nand-s3c2410.h> #include <plat/gpio-cfg.h> diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c index c157103ed8e..c0763b83774 100644 --- a/arch/arm/mach-s3c24xx/common.c +++ b/arch/arm/mach-s3c24xx/common.c @@ -27,9 +27,12 @@ #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> +#include <clocksource/samsung_pwm.h> #include <linux/platform_device.h> #include <linux/delay.h> #include <linux/io.h> +#include <linux/platform_data/dma-s3c24xx.h> #include <mach/hardware.h> #include <mach/regs-clock.h> @@ -42,13 +45,15 @@ #include <asm/mach/map.h> #include <mach/regs-gpio.h> -#include <plat/regs-serial.h> +#include <mach/dma.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/clock.h> #include <plat/cpu-freq.h> #include <plat/pll.h> +#include <plat/pwm-core.h> +#include <plat/watchdog-reset.h> #include "common.h" @@ -69,7 +74,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = 0x32410000, .idmask = 0xffffffff, .map_io = s3c2410_map_io, - .init_clocks = s3c2410_init_clocks, .init_uarts = s3c2410_init_uarts, .init = s3c2410_init, .name = name_s3c2410 @@ -78,7 +82,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = 0x32410002, .idmask = 0xffffffff, .map_io = s3c2410_map_io, - .init_clocks = s3c2410_init_clocks, .init_uarts = s3c2410_init_uarts, .init = s3c2410a_init, .name = name_s3c2410a @@ -87,7 +90,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = 0x32440000, .idmask = 0xffffffff, .map_io = s3c2440_map_io, - .init_clocks = s3c244x_init_clocks, .init_uarts = s3c244x_init_uarts, .init = s3c2440_init, .name = name_s3c2440 @@ -96,7 +98,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = 0x32440001, .idmask = 0xffffffff, .map_io = s3c2440_map_io, - .init_clocks = s3c244x_init_clocks, .init_uarts = s3c244x_init_uarts, .init = s3c2440_init, .name = name_s3c2440a @@ -105,7 +106,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = 0x32440aaa, .idmask = 0xffffffff, .map_io = s3c2442_map_io, - .init_clocks = s3c244x_init_clocks, .init_uarts = s3c244x_init_uarts, .init = s3c2442_init, .name = name_s3c2442 @@ -114,7 +114,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = 0x32440aab, .idmask = 0xffffffff, .map_io = s3c2442_map_io, - .init_clocks = s3c244x_init_clocks, .init_uarts = s3c244x_init_uarts, .init = s3c2442_init, .name = name_s3c2442b @@ -123,7 +122,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = 0x32412001, .idmask = 0xffffffff, .map_io = s3c2412_map_io, - .init_clocks = s3c2412_init_clocks, .init_uarts = s3c2412_init_uarts, .init = s3c2412_init, .name = name_s3c2412, @@ -132,7 +130,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = 0x32412003, .idmask = 0xffffffff, .map_io = s3c2412_map_io, - .init_clocks = s3c2412_init_clocks, .init_uarts = s3c2412_init_uarts, .init = s3c2412_init, .name = name_s3c2412, @@ -141,7 +138,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = 0x32450003, .idmask = 0xffffffff, .map_io = s3c2416_map_io, - .init_clocks = s3c2416_init_clocks, .init_uarts = s3c2416_init_uarts, .init = s3c2416_init, .name = name_s3c2416, @@ -150,7 +146,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = 0x32443001, .idmask = 0xffffffff, .map_io = s3c2443_map_io, - .init_clocks = s3c2443_init_clocks, .init_uarts = s3c2443_init_uarts, .init = s3c2443_init, .name = name_s3c2443, @@ -216,6 +211,13 @@ static void s3c24xx_default_idle(void) S3C2410_CLKCON); } +static struct samsung_pwm_variant s3c24xx_pwm_variant = { + .bits = 16, + .div_base = 1, + .has_tint_cstat = false, + .tclk_mask = (1 << 4), +}; + void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) { arm_pm_idle = s3c24xx_default_idle; @@ -229,9 +231,26 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) } else { samsung_cpu_id = s3c24xx_read_idcode_v4(); } - s3c24xx_init_cpu(); s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); + + samsung_pwm_set_platdata(&s3c24xx_pwm_variant); +} + +void __init samsung_set_timer_source(unsigned int event, unsigned int source) +{ + s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; + s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); +} + +void __init samsung_timer_init(void) +{ + unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { + IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4, + }; + + samsung_pwm_clocksource_init(S3C_VA_TIMER, + timer_irqs, &s3c24xx_pwm_variant); } /* Serial port registrations */ @@ -288,17 +307,265 @@ struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { }, }; -/* initialise all the clocks */ +#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ + defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) +static struct resource s3c2410_dma_resource[] = { + [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA), + [1] = DEFINE_RES_IRQ(IRQ_DMA0), + [2] = DEFINE_RES_IRQ(IRQ_DMA1), + [3] = DEFINE_RES_IRQ(IRQ_DMA2), + [4] = DEFINE_RES_IRQ(IRQ_DMA3), +}; +#endif + +#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442) +static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = { + [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), }, + [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), }, + [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) | + S3C24XX_DMA_CHANREQ(2, 2) | + S3C24XX_DMA_CHANREQ(1, 3), + }, + [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), }, + [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), }, + [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), }, + [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), }, + [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), }, + [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) | + S3C24XX_DMA_CHANREQ(3, 2) | + S3C24XX_DMA_CHANREQ(3, 3), + }, + [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) | + S3C24XX_DMA_CHANREQ(1, 2), + }, + [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), }, + [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), }, + [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), }, + [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), }, + [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), }, +}; + +static struct s3c24xx_dma_platdata s3c2410_dma_platdata = { + .num_phy_channels = 4, + .channels = s3c2410_dma_channels, + .num_channels = DMACH_MAX, +}; -void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, - unsigned long hclk, - unsigned long pclk) +struct platform_device s3c2410_device_dma = { + .name = "s3c2410-dma", + .id = 0, + .num_resources = ARRAY_SIZE(s3c2410_dma_resource), + .resource = s3c2410_dma_resource, + .dev = { + .platform_data = &s3c2410_dma_platdata, + }, +}; +#endif + +#ifdef CONFIG_CPU_S3C2412 +static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = { + [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 }, + [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 }, + [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 }, + [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 }, + [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 }, + [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 }, + [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 }, + [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 }, + [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 }, + [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 }, + [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 }, + [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 }, + [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 }, + [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 }, + [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 }, + [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 }, + [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 }, + [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 }, + [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 }, + [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 }, +}; + +static struct s3c24xx_dma_platdata s3c2412_dma_platdata = { + .num_phy_channels = 4, + .channels = s3c2412_dma_channels, + .num_channels = DMACH_MAX, +}; + +struct platform_device s3c2412_device_dma = { + .name = "s3c2412-dma", + .id = 0, + .num_resources = ARRAY_SIZE(s3c2410_dma_resource), + .resource = s3c2410_dma_resource, + .dev = { + .platform_data = &s3c2412_dma_platdata, + }, +}; +#endif + +#if defined(CONFIG_CPU_S3C2440) +static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = { + [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), }, + [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), }, + [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) | + S3C24XX_DMA_CHANREQ(6, 1) | + S3C24XX_DMA_CHANREQ(2, 2) | + S3C24XX_DMA_CHANREQ(1, 3), + }, + [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), }, + [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), }, + [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), }, + [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), }, + [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), }, + [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) | + S3C24XX_DMA_CHANREQ(3, 2) | + S3C24XX_DMA_CHANREQ(3, 3), + }, + [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) | + S3C24XX_DMA_CHANREQ(1, 2), + }, + [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) | + S3C24XX_DMA_CHANREQ(0, 2), + }, + [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) | + S3C24XX_DMA_CHANREQ(5, 2), + }, + [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) | + S3C24XX_DMA_CHANREQ(6, 3), + }, + [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) | + S3C24XX_DMA_CHANREQ(5, 3), + }, + [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), }, + [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), }, + [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), }, + [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), }, +}; + +static struct s3c24xx_dma_platdata s3c2440_dma_platdata = { + .num_phy_channels = 4, + .channels = s3c2440_dma_channels, + .num_channels = DMACH_MAX, +}; + +struct platform_device s3c2440_device_dma = { + .name = "s3c2410-dma", + .id = 0, + .num_resources = ARRAY_SIZE(s3c2410_dma_resource), + .resource = s3c2410_dma_resource, + .dev = { + .platform_data = &s3c2440_dma_platdata, + }, +}; +#endif + +#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) +static struct resource s3c2443_dma_resource[] = { + [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA), + [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0), + [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1), + [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2), + [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3), + [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4), + [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5), +}; + +static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = { + [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 }, + [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 }, + [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 }, + [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 }, + [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 }, + [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 }, + [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 }, + [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 }, + [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 }, + [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 }, + [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 }, + [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 }, + [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 }, + [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 }, + [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 }, + [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 }, + [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 }, + [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 }, + [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 }, + [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 }, + [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 }, +}; + +static struct s3c24xx_dma_platdata s3c2443_dma_platdata = { + .num_phy_channels = 6, + .channels = s3c2443_dma_channels, + .num_channels = DMACH_MAX, +}; + +struct platform_device s3c2443_device_dma = { + .name = "s3c2443-dma", + .id = 0, + .num_resources = ARRAY_SIZE(s3c2443_dma_resource), + .resource = s3c2443_dma_resource, + .dev = { + .platform_data = &s3c2443_dma_platdata, + }, +}; +#endif + +#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410) +void __init s3c2410_init_clocks(int xtal) +{ + s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR); + samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG); +} +#endif + +#ifdef CONFIG_CPU_S3C2412 +void __init s3c2412_init_clocks(int xtal) +{ + s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR); +} +#endif + +#ifdef CONFIG_CPU_S3C2416 +void __init s3c2416_init_clocks(int xtal) +{ + s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR); +} +#endif + +#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440) +void __init s3c2440_init_clocks(int xtal) +{ + s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR); + samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG); +} +#endif + +#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442) +void __init s3c2442_init_clocks(int xtal) { - clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), - clk_xtal.rate); + s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR); + samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG); +} +#endif - clk_mpll.rate = fclk; - clk_h.rate = hclk; - clk_p.rate = pclk; - clk_f.rate = fclk; +#ifdef CONFIG_CPU_S3C2443 +void __init s3c2443_init_clocks(int xtal) +{ + s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR); } +#endif + +#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \ + defined(CONFIG_CPU_S3C2442) +static struct resource s3c2410_dclk_resource[] = { + [0] = DEFINE_RES_MEM(0x56000084, 0x4), +}; + +struct platform_device s3c2410_device_dclk = { + .name = "s3c2410-dclk", + .id = 0, + .num_resources = ARRAY_SIZE(s3c2410_dclk_resource), + .resource = s3c2410_dclk_resource, +}; +#endif diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h index 307c3714be5..ac3ff12a060 100644 --- a/arch/arm/mach-s3c24xx/common.h +++ b/arch/arm/mach-s3c24xx/common.h @@ -12,6 +12,8 @@ #ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__ +#include <linux/reboot.h> + struct s3c2410_uartcfg; #ifdef CONFIG_CPU_S3C2410 @@ -20,7 +22,7 @@ extern int s3c2410a_init(void); extern void s3c2410_map_io(void); extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); extern void s3c2410_init_clocks(int xtal); -extern void s3c2410_restart(char mode, const char *cmd); +extern void s3c2410_restart(enum reboot_mode mode, const char *cmd); extern void s3c2410_init_irq(void); #else #define s3c2410_init_clocks NULL @@ -36,7 +38,7 @@ extern void s3c2412_map_io(void); extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); extern void s3c2412_init_clocks(int xtal); extern int s3c2412_baseclk_add(void); -extern void s3c2412_restart(char mode, const char *cmd); +extern void s3c2412_restart(enum reboot_mode mode, const char *cmd); extern void s3c2412_init_irq(void); #else #define s3c2412_init_clocks NULL @@ -51,7 +53,7 @@ extern void s3c2416_map_io(void); extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no); extern void s3c2416_init_clocks(int xtal); extern int s3c2416_baseclk_add(void); -extern void s3c2416_restart(char mode, const char *cmd); +extern void s3c2416_restart(enum reboot_mode mode, const char *cmd); extern void s3c2416_init_irq(void); extern struct syscore_ops s3c2416_irq_syscore_ops; @@ -65,16 +67,15 @@ extern struct syscore_ops s3c2416_irq_syscore_ops; #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) extern void s3c244x_map_io(void); extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c244x_init_clocks(int xtal); -extern void s3c244x_restart(char mode, const char *cmd); +extern void s3c244x_restart(enum reboot_mode mode, const char *cmd); #else -#define s3c244x_init_clocks NULL #define s3c244x_init_uarts NULL #endif #ifdef CONFIG_CPU_S3C2440 extern int s3c2440_init(void); extern void s3c2440_map_io(void); +extern void s3c2440_init_clocks(int xtal); extern void s3c2440_init_irq(void); #else #define s3c2440_init NULL @@ -84,6 +85,7 @@ extern void s3c2440_init_irq(void); #ifdef CONFIG_CPU_S3C2442 extern int s3c2442_init(void); extern void s3c2442_map_io(void); +extern void s3c2442_init_clocks(int xtal); extern void s3c2442_init_irq(void); #else #define s3c2442_init NULL @@ -96,7 +98,7 @@ extern void s3c2443_map_io(void); extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no); extern void s3c2443_init_clocks(int xtal); extern int s3c2443_baseclk_add(void); -extern void s3c2443_restart(char mode, const char *cmd); +extern void s3c2443_restart(enum reboot_mode mode, const char *cmd); extern void s3c2443_init_irq(void); #else #define s3c2443_init_clocks NULL @@ -107,4 +109,26 @@ extern void s3c2443_init_irq(void); extern struct syscore_ops s3c24xx_irq_syscore_ops; +extern struct platform_device s3c2410_device_dma; +extern struct platform_device s3c2412_device_dma; +extern struct platform_device s3c2440_device_dma; +extern struct platform_device s3c2443_device_dma; + +extern struct platform_device s3c2410_device_dclk; + +#ifdef CONFIG_S3C2410_COMMON_CLK +void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f, + int current_soc, + void __iomem *reg_base); +#endif +#ifdef CONFIG_S3C2412_COMMON_CLK +void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f, + unsigned long ext_f, void __iomem *reg_base); +#endif +#ifdef CONFIG_S3C2443_COMMON_CLK +void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f, + int current_soc, + void __iomem *reg_base); +#endif + #endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */ diff --git a/arch/arm/mach-s3c24xx/cpufreq-debugfs.c b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c deleted file mode 100644 index 9b7b4289d66..00000000000 --- a/arch/arm/mach-s3c24xx/cpufreq-debugfs.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (c) 2009 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C24XX CPU Frequency scaling - debugfs status support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/init.h> -#include <linux/export.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/cpufreq.h> -#include <linux/debugfs.h> -#include <linux/seq_file.h> -#include <linux/err.h> - -#include <plat/cpu-freq-core.h> - -static struct dentry *dbgfs_root; -static struct dentry *dbgfs_file_io; -static struct dentry *dbgfs_file_info; -static struct dentry *dbgfs_file_board; - -#define print_ns(x) ((x) / 10), ((x) % 10) - -static void show_max(struct seq_file *seq, struct s3c_freq *f) -{ - seq_printf(seq, "MAX: F=%lu, H=%lu, P=%lu, A=%lu\n", - f->fclk, f->hclk, f->pclk, f->armclk); -} - -static int board_show(struct seq_file *seq, void *p) -{ - struct s3c_cpufreq_config *cfg; - struct s3c_cpufreq_board *brd; - - cfg = s3c_cpufreq_getconfig(); - if (!cfg) { - seq_printf(seq, "no configuration registered\n"); - return 0; - } - - brd = cfg->board; - if (!brd) { - seq_printf(seq, "no board definition set?\n"); - return 0; - } - - seq_printf(seq, "SDRAM refresh %u ns\n", brd->refresh); - seq_printf(seq, "auto_io=%u\n", brd->auto_io); - seq_printf(seq, "need_io=%u\n", brd->need_io); - - show_max(seq, &brd->max); - - - return 0; -} - -static int fops_board_open(struct inode *inode, struct file *file) -{ - return single_open(file, board_show, NULL); -} - -static const struct file_operations fops_board = { - .open = fops_board_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, - .owner = THIS_MODULE, -}; - -static int info_show(struct seq_file *seq, void *p) -{ - struct s3c_cpufreq_config *cfg; - - cfg = s3c_cpufreq_getconfig(); - if (!cfg) { - seq_printf(seq, "no configuration registered\n"); - return 0; - } - - seq_printf(seq, " FCLK %ld Hz\n", cfg->freq.fclk); - seq_printf(seq, " HCLK %ld Hz (%lu.%lu ns)\n", - cfg->freq.hclk, print_ns(cfg->freq.hclk_tns)); - seq_printf(seq, " PCLK %ld Hz\n", cfg->freq.hclk); - seq_printf(seq, "ARMCLK %ld Hz\n", cfg->freq.armclk); - seq_printf(seq, "\n"); - - show_max(seq, &cfg->max); - - seq_printf(seq, "Divisors: P=%d, H=%d, A=%d, dvs=%s\n", - cfg->divs.h_divisor, cfg->divs.p_divisor, - cfg->divs.arm_divisor, cfg->divs.dvs ? "on" : "off"); - seq_printf(seq, "\n"); - - seq_printf(seq, "lock_pll=%u\n", cfg->lock_pll); - - return 0; -} - -static int fops_info_open(struct inode *inode, struct file *file) -{ - return single_open(file, info_show, NULL); -} - -static const struct file_operations fops_info = { - .open = fops_info_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, - .owner = THIS_MODULE, -}; - -static int io_show(struct seq_file *seq, void *p) -{ - void (*show_bank)(struct seq_file *, struct s3c_cpufreq_config *, union s3c_iobank *); - struct s3c_cpufreq_config *cfg; - struct s3c_iotimings *iot; - union s3c_iobank *iob; - int bank; - - cfg = s3c_cpufreq_getconfig(); - if (!cfg) { - seq_printf(seq, "no configuration registered\n"); - return 0; - } - - show_bank = cfg->info->debug_io_show; - if (!show_bank) { - seq_printf(seq, "no code to show bank timing\n"); - return 0; - } - - iot = s3c_cpufreq_getiotimings(); - if (!iot) { - seq_printf(seq, "no io timings registered\n"); - return 0; - } - - seq_printf(seq, "hclk period is %lu.%lu ns\n", print_ns(cfg->freq.hclk_tns)); - - for (bank = 0; bank < MAX_BANKS; bank++) { - iob = &iot->bank[bank]; - - seq_printf(seq, "bank %d: ", bank); - - if (!iob->io_2410) { - seq_printf(seq, "nothing set\n"); - continue; - } - - show_bank(seq, cfg, iob); - } - - return 0; -} - -static int fops_io_open(struct inode *inode, struct file *file) -{ - return single_open(file, io_show, NULL); -} - -static const struct file_operations fops_io = { - .open = fops_io_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, - .owner = THIS_MODULE, -}; - - -static int __init s3c_freq_debugfs_init(void) -{ - dbgfs_root = debugfs_create_dir("s3c-cpufreq", NULL); - if (IS_ERR(dbgfs_root)) { - printk(KERN_ERR "%s: error creating debugfs root\n", __func__); - return PTR_ERR(dbgfs_root); - } - - dbgfs_file_io = debugfs_create_file("io-timing", S_IRUGO, dbgfs_root, - NULL, &fops_io); - - dbgfs_file_info = debugfs_create_file("info", S_IRUGO, dbgfs_root, - NULL, &fops_info); - - dbgfs_file_board = debugfs_create_file("board", S_IRUGO, dbgfs_root, - NULL, &fops_board); - - return 0; -} - -late_initcall(s3c_freq_debugfs_init); - diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c deleted file mode 100644 index cfa0dd8723e..00000000000 --- a/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (c) 2006-2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 CPU Frequency scaling - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/cpufreq.h> -#include <linux/device.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include <mach/regs-clock.h> - -#include <plat/cpu.h> -#include <plat/clock.h> -#include <plat/cpu-freq-core.h> - -/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */ - -static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) -{ - u32 clkdiv = 0; - - if (cfg->divs.h_divisor == 2) - clkdiv |= S3C2410_CLKDIVN_HDIVN; - - if (cfg->divs.p_divisor != cfg->divs.h_divisor) - clkdiv |= S3C2410_CLKDIVN_PDIVN; - - __raw_writel(clkdiv, S3C2410_CLKDIVN); -} - -static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) -{ - unsigned long hclk, fclk, pclk; - unsigned int hdiv, pdiv; - unsigned long hclk_max; - - fclk = cfg->freq.fclk; - hclk_max = cfg->max.hclk; - - cfg->freq.armclk = fclk; - - s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n", - __func__, fclk, hclk_max); - - hdiv = (fclk > cfg->max.hclk) ? 2 : 1; - hclk = fclk / hdiv; - - if (hclk > cfg->max.hclk) { - s3c_freq_dbg("%s: hclk too big\n", __func__); - return -EINVAL; - } - - pdiv = (hclk > cfg->max.pclk) ? 2 : 1; - pclk = hclk / pdiv; - - if (pclk > cfg->max.pclk) { - s3c_freq_dbg("%s: pclk too big\n", __func__); - return -EINVAL; - } - - pdiv *= hdiv; - - /* record the result */ - cfg->divs.p_divisor = pdiv; - cfg->divs.h_divisor = hdiv; - - return 0; -} - -static struct s3c_cpufreq_info s3c2410_cpufreq_info = { - .max = { - .fclk = 200000000, - .hclk = 100000000, - .pclk = 50000000, - }, - - /* transition latency is about 5ms worst-case, so - * set 10ms to be sure */ - .latency = 10000000, - - .locktime_m = 150, - .locktime_u = 150, - .locktime_bits = 12, - - .need_pll = 1, - - .name = "s3c2410", - .calc_iotiming = s3c2410_iotiming_calc, - .set_iotiming = s3c2410_iotiming_set, - .get_iotiming = s3c2410_iotiming_get, - .resume_clocks = s3c2410_setup_clocks, - - .set_fvco = s3c2410_set_fvco, - .set_refresh = s3c2410_cpufreq_setrefresh, - .set_divs = s3c2410_cpufreq_setdivs, - .calc_divs = s3c2410_cpufreq_calcdivs, - - .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), -}; - -static int s3c2410_cpufreq_add(struct device *dev, - struct subsys_interface *sif) -{ - return s3c_cpufreq_register(&s3c2410_cpufreq_info); -} - -static struct subsys_interface s3c2410_cpufreq_interface = { - .name = "s3c2410_cpufreq", - .subsys = &s3c2410_subsys, - .add_dev = s3c2410_cpufreq_add, -}; - -static int __init s3c2410_cpufreq_init(void) -{ - return subsys_interface_register(&s3c2410_cpufreq_interface); -} -arch_initcall(s3c2410_cpufreq_init); - -static int s3c2410a_cpufreq_add(struct device *dev, - struct subsys_interface *sif) -{ - /* alter the maximum freq settings for S3C2410A. If a board knows - * it only has a maximum of 200, then it should register its own - * limits. */ - - s3c2410_cpufreq_info.max.fclk = 266000000; - s3c2410_cpufreq_info.max.hclk = 133000000; - s3c2410_cpufreq_info.max.pclk = 66500000; - s3c2410_cpufreq_info.name = "s3c2410a"; - - return s3c2410_cpufreq_add(dev, sif); -} - -static struct subsys_interface s3c2410a_cpufreq_interface = { - .name = "s3c2410a_cpufreq", - .subsys = &s3c2410a_subsys, - .add_dev = s3c2410a_cpufreq_add, -}; - -static int __init s3c2410a_cpufreq_init(void) -{ - return subsys_interface_register(&s3c2410a_cpufreq_interface); -} -arch_initcall(s3c2410a_cpufreq_init); diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c deleted file mode 100644 index 8bf0f3a7747..00000000000 --- a/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2412 CPU Frequency scalling - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/cpufreq.h> -#include <linux/device.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include <mach/regs-clock.h> - -#include <plat/cpu.h> -#include <plat/clock.h> -#include <plat/cpu-freq-core.h> - -#include "s3c2412.h" - -/* our clock resources. */ -static struct clk *xtal; -static struct clk *fclk; -static struct clk *hclk; -static struct clk *armclk; - -/* HDIV: 1, 2, 3, 4, 6, 8 */ - -static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) -{ - unsigned int hdiv, pdiv, armdiv, dvs; - unsigned long hclk, fclk, armclk, armdiv_clk; - unsigned long hclk_max; - - fclk = cfg->freq.fclk; - armclk = cfg->freq.armclk; - hclk_max = cfg->max.hclk; - - /* We can't run hclk above armclk as at the best we have to - * have armclk and hclk in dvs mode. */ - - if (hclk_max > armclk) - hclk_max = armclk; - - s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n", - __func__, fclk, armclk, hclk_max); - s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n", - __func__, cfg->freq.fclk, cfg->freq.armclk, - cfg->freq.hclk, cfg->freq.pclk); - - armdiv = fclk / armclk; - - if (armdiv < 1) - armdiv = 1; - if (armdiv > 2) - armdiv = 2; - - cfg->divs.arm_divisor = armdiv; - armdiv_clk = fclk / armdiv; - - hdiv = armdiv_clk / hclk_max; - if (hdiv < 1) - hdiv = 1; - - cfg->freq.hclk = hclk = armdiv_clk / hdiv; - - /* set dvs depending on whether we reached armclk or not. */ - cfg->divs.dvs = dvs = armclk < armdiv_clk; - - /* update the actual armclk we achieved. */ - cfg->freq.armclk = dvs ? hclk : armdiv_clk; - - s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n", - __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs); - - if (hdiv > 4) - goto invalid; - - pdiv = (hclk > cfg->max.pclk) ? 2 : 1; - - if ((hclk / pdiv) > cfg->max.pclk) - pdiv++; - - cfg->freq.pclk = hclk / pdiv; - - s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv); - - if (pdiv > 2) - goto invalid; - - pdiv *= hdiv; - - /* store the result, and then return */ - - cfg->divs.h_divisor = hdiv * armdiv; - cfg->divs.p_divisor = pdiv * armdiv; - - return 0; - -invalid: - return -EINVAL; -} - -static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) -{ - unsigned long clkdiv; - unsigned long olddiv; - - olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN); - - /* clear off current clock info */ - - clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN; - clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK; - clkdiv &= ~S3C2412_CLKDIVN_PDIVN; - - if (cfg->divs.arm_divisor == 2) - clkdiv |= S3C2412_CLKDIVN_ARMDIVN; - - clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1); - - if (cfg->divs.p_divisor != cfg->divs.h_divisor) - clkdiv |= S3C2412_CLKDIVN_PDIVN; - - s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv); - __raw_writel(clkdiv, S3C2410_CLKDIVN); - - clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); -} - -static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) -{ - struct s3c_cpufreq_board *board = cfg->board; - unsigned long refresh; - - s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__, - board->refresh, cfg->freq.hclk); - - /* Reduce both the refresh time (in ns) and the frequency (in MHz) - * by 10 each to ensure that we do not overflow 32 bit numbers. This - * should work for HCLK up to 133MHz and refresh period up to 30usec. - */ - - refresh = (board->refresh / 10); - refresh *= (cfg->freq.hclk / 100); - refresh /= (1 * 1000 * 1000); /* 10^6 */ - - s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh); - __raw_writel(refresh, S3C2412_REFRESH); -} - -/* set the default cpu frequency information, based on an 200MHz part - * as we have no other way of detecting the speed rating in software. - */ - -static struct s3c_cpufreq_info s3c2412_cpufreq_info = { - .max = { - .fclk = 200000000, - .hclk = 100000000, - .pclk = 50000000, - }, - - .latency = 5000000, /* 5ms */ - - .locktime_m = 150, - .locktime_u = 150, - .locktime_bits = 16, - - .name = "s3c2412", - .set_refresh = s3c2412_cpufreq_setrefresh, - .set_divs = s3c2412_cpufreq_setdivs, - .calc_divs = s3c2412_cpufreq_calcdivs, - - .calc_iotiming = s3c2412_iotiming_calc, - .set_iotiming = s3c2412_iotiming_set, - .get_iotiming = s3c2412_iotiming_get, - - .resume_clocks = s3c2412_setup_clocks, - - .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs), -}; - -static int s3c2412_cpufreq_add(struct device *dev, - struct subsys_interface *sif) -{ - unsigned long fclk_rate; - - hclk = clk_get(NULL, "hclk"); - if (IS_ERR(hclk)) { - printk(KERN_ERR "%s: cannot find hclk clock\n", __func__); - return -ENOENT; - } - - fclk = clk_get(NULL, "fclk"); - if (IS_ERR(fclk)) { - printk(KERN_ERR "%s: cannot find fclk clock\n", __func__); - goto err_fclk; - } - - fclk_rate = clk_get_rate(fclk); - if (fclk_rate > 200000000) { - printk(KERN_INFO - "%s: fclk %ld MHz, assuming 266MHz capable part\n", - __func__, fclk_rate / 1000000); - s3c2412_cpufreq_info.max.fclk = 266000000; - s3c2412_cpufreq_info.max.hclk = 133000000; - s3c2412_cpufreq_info.max.pclk = 66000000; - } - - armclk = clk_get(NULL, "armclk"); - if (IS_ERR(armclk)) { - printk(KERN_ERR "%s: cannot find arm clock\n", __func__); - goto err_armclk; - } - - xtal = clk_get(NULL, "xtal"); - if (IS_ERR(xtal)) { - printk(KERN_ERR "%s: cannot find xtal clock\n", __func__); - goto err_xtal; - } - - return s3c_cpufreq_register(&s3c2412_cpufreq_info); - -err_xtal: - clk_put(armclk); -err_armclk: - clk_put(fclk); -err_fclk: - clk_put(hclk); - - return -ENOENT; -} - -static struct subsys_interface s3c2412_cpufreq_interface = { - .name = "s3c2412_cpufreq", - .subsys = &s3c2412_subsys, - .add_dev = s3c2412_cpufreq_add, -}; - -static int s3c2412_cpufreq_init(void) -{ - return subsys_interface_register(&s3c2412_cpufreq_interface); -} -arch_initcall(s3c2412_cpufreq_init); diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c deleted file mode 100644 index 72b2cc8a5a8..00000000000 --- a/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c +++ /dev/null @@ -1,312 +0,0 @@ -/* - * Copyright (c) 2006-2009 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * Vincent Sanders <vince@simtec.co.uk> - * - * S3C2440/S3C2442 CPU Frequency scaling - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/cpufreq.h> -#include <linux/device.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> - -#include <mach/hardware.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include <mach/regs-clock.h> - -#include <plat/cpu.h> -#include <plat/cpu-freq-core.h> -#include <plat/clock.h> - -static struct clk *xtal; -static struct clk *fclk; -static struct clk *hclk; -static struct clk *armclk; - -/* HDIV: 1, 2, 3, 4, 6, 8 */ - -static inline int within_khz(unsigned long a, unsigned long b) -{ - long diff = a - b; - - return (diff >= -1000 && diff <= 1000); -} - -/** - * s3c2440_cpufreq_calcdivs - calculate divider settings - * @cfg: The cpu frequency settings. - * - * Calcualte the divider values for the given frequency settings - * specified in @cfg. The values are stored in @cfg for later use - * by the relevant set routine if the request settings can be reached. - */ -int s3c2440_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) -{ - unsigned int hdiv, pdiv; - unsigned long hclk, fclk, armclk; - unsigned long hclk_max; - - fclk = cfg->freq.fclk; - armclk = cfg->freq.armclk; - hclk_max = cfg->max.hclk; - - s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n", - __func__, fclk, armclk, hclk_max); - - if (armclk > fclk) { - printk(KERN_WARNING "%s: armclk > fclk\n", __func__); - armclk = fclk; - } - - /* if we are in DVS, we need HCLK to be <= ARMCLK */ - if (armclk < fclk && armclk < hclk_max) - hclk_max = armclk; - - for (hdiv = 1; hdiv < 9; hdiv++) { - if (hdiv == 5 || hdiv == 7) - hdiv++; - - hclk = (fclk / hdiv); - if (hclk <= hclk_max || within_khz(hclk, hclk_max)) - break; - } - - s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv); - - if (hdiv > 8) - goto invalid; - - pdiv = (hclk > cfg->max.pclk) ? 2 : 1; - - if ((hclk / pdiv) > cfg->max.pclk) - pdiv++; - - s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv); - - if (pdiv > 2) - goto invalid; - - pdiv *= hdiv; - - /* calculate a valid armclk */ - - if (armclk < hclk) - armclk = hclk; - - /* if we're running armclk lower than fclk, this really means - * that the system should go into dvs mode, which means that - * armclk is connected to hclk. */ - if (armclk < fclk) { - cfg->divs.dvs = 1; - armclk = hclk; - } else - cfg->divs.dvs = 0; - - cfg->freq.armclk = armclk; - - /* store the result, and then return */ - - cfg->divs.h_divisor = hdiv; - cfg->divs.p_divisor = pdiv; - - return 0; - - invalid: - return -EINVAL; -} - -#define CAMDIVN_HCLK_HALF (S3C2440_CAMDIVN_HCLK3_HALF | \ - S3C2440_CAMDIVN_HCLK4_HALF) - -/** - * s3c2440_cpufreq_setdivs - set the cpu frequency divider settings - * @cfg: The cpu frequency settings. - * - * Set the divisors from the settings in @cfg, which where generated - * during the calculation phase by s3c2440_cpufreq_calcdivs(). - */ -static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) -{ - unsigned long clkdiv, camdiv; - - s3c_freq_dbg("%s: divsiors: h=%d, p=%d\n", __func__, - cfg->divs.h_divisor, cfg->divs.p_divisor); - - clkdiv = __raw_readl(S3C2410_CLKDIVN); - camdiv = __raw_readl(S3C2440_CAMDIVN); - - clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN); - camdiv &= ~CAMDIVN_HCLK_HALF; - - switch (cfg->divs.h_divisor) { - case 1: - clkdiv |= S3C2440_CLKDIVN_HDIVN_1; - break; - - case 2: - clkdiv |= S3C2440_CLKDIVN_HDIVN_2; - break; - - case 6: - camdiv |= S3C2440_CAMDIVN_HCLK3_HALF; - case 3: - clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6; - break; - - case 8: - camdiv |= S3C2440_CAMDIVN_HCLK4_HALF; - case 4: - clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8; - break; - - default: - BUG(); /* we don't expect to get here. */ - } - - if (cfg->divs.p_divisor != cfg->divs.h_divisor) - clkdiv |= S3C2440_CLKDIVN_PDIVN; - - /* todo - set pclk. */ - - /* Write the divisors first with hclk intentionally halved so that - * when we write clkdiv we will under-frequency instead of over. We - * then make a short delay and remove the hclk halving if necessary. - */ - - __raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN); - __raw_writel(clkdiv, S3C2410_CLKDIVN); - - ndelay(20); - __raw_writel(camdiv, S3C2440_CAMDIVN); - - clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); -} - -static int run_freq_for(unsigned long max_hclk, unsigned long fclk, - int *divs, - struct cpufreq_frequency_table *table, - size_t table_size) -{ - unsigned long freq; - int index = 0; - int div; - - for (div = *divs; div > 0; div = *divs++) { - freq = fclk / div; - - if (freq > max_hclk && div != 1) - continue; - - freq /= 1000; /* table is in kHz */ - index = s3c_cpufreq_addfreq(table, index, table_size, freq); - if (index < 0) - break; - } - - return index; -} - -static int hclk_divs[] = { 1, 2, 3, 4, 6, 8, -1 }; - -static int s3c2440_cpufreq_calctable(struct s3c_cpufreq_config *cfg, - struct cpufreq_frequency_table *table, - size_t table_size) -{ - int ret; - - WARN_ON(cfg->info == NULL); - WARN_ON(cfg->board == NULL); - - ret = run_freq_for(cfg->info->max.hclk, - cfg->info->max.fclk, - hclk_divs, - table, table_size); - - s3c_freq_dbg("%s: returning %d\n", __func__, ret); - - return ret; -} - -struct s3c_cpufreq_info s3c2440_cpufreq_info = { - .max = { - .fclk = 400000000, - .hclk = 133333333, - .pclk = 66666666, - }, - - .locktime_m = 300, - .locktime_u = 300, - .locktime_bits = 16, - - .name = "s3c244x", - .calc_iotiming = s3c2410_iotiming_calc, - .set_iotiming = s3c2410_iotiming_set, - .get_iotiming = s3c2410_iotiming_get, - .set_fvco = s3c2410_set_fvco, - - .set_refresh = s3c2410_cpufreq_setrefresh, - .set_divs = s3c2440_cpufreq_setdivs, - .calc_divs = s3c2440_cpufreq_calcdivs, - .calc_freqtable = s3c2440_cpufreq_calctable, - - .resume_clocks = s3c244x_setup_clocks, - - .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), -}; - -static int s3c2440_cpufreq_add(struct device *dev, - struct subsys_interface *sif) -{ - xtal = s3c_cpufreq_clk_get(NULL, "xtal"); - hclk = s3c_cpufreq_clk_get(NULL, "hclk"); - fclk = s3c_cpufreq_clk_get(NULL, "fclk"); - armclk = s3c_cpufreq_clk_get(NULL, "armclk"); - - if (IS_ERR(xtal) || IS_ERR(hclk) || IS_ERR(fclk) || IS_ERR(armclk)) { - printk(KERN_ERR "%s: failed to get clocks\n", __func__); - return -ENOENT; - } - - return s3c_cpufreq_register(&s3c2440_cpufreq_info); -} - -static struct subsys_interface s3c2440_cpufreq_interface = { - .name = "s3c2440_cpufreq", - .subsys = &s3c2440_subsys, - .add_dev = s3c2440_cpufreq_add, -}; - -static int s3c2440_cpufreq_init(void) -{ - return subsys_interface_register(&s3c2440_cpufreq_interface); -} - -/* arch_initcall adds the clocks we need, so use subsys_initcall. */ -subsys_initcall(s3c2440_cpufreq_init); - -static struct subsys_interface s3c2442_cpufreq_interface = { - .name = "s3c2442_cpufreq", - .subsys = &s3c2442_subsys, - .add_dev = s3c2440_cpufreq_add, -}; - -static int s3c2442_cpufreq_init(void) -{ - return subsys_interface_register(&s3c2442_cpufreq_interface); -} -subsys_initcall(s3c2442_cpufreq_init); diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c index ddd8280e387..d4d9514335f 100644 --- a/arch/arm/mach-s3c24xx/cpufreq-utils.c +++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c @@ -14,6 +14,7 @@ #include <linux/errno.h> #include <linux/cpufreq.h> #include <linux/io.h> +#include <linux/clk.h> #include <mach/map.h> #include <mach/regs-clock.h> @@ -60,5 +61,6 @@ void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) */ void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg) { - __raw_writel(cfg->pll.index, S3C2410_MPLLCON); + if (!IS_ERR(cfg->mpll)) + clk_set_rate(cfg->mpll, cfg->pll.frequency); } diff --git a/arch/arm/mach-s3c24xx/cpufreq.c b/arch/arm/mach-s3c24xx/cpufreq.c deleted file mode 100644 index 3c0e78ede0d..00000000000 --- a/arch/arm/mach-s3c24xx/cpufreq.c +++ /dev/null @@ -1,711 +0,0 @@ -/* - * Copyright (c) 2006-2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C24XX CPU Frequency scaling - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/cpufreq.h> -#include <linux/cpu.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/device.h> -#include <linux/sysfs.h> -#include <linux/slab.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include <plat/cpu.h> -#include <plat/clock.h> -#include <plat/cpu-freq-core.h> - -#include <mach/regs-clock.h> - -/* note, cpufreq support deals in kHz, no Hz */ - -static struct cpufreq_driver s3c24xx_driver; -static struct s3c_cpufreq_config cpu_cur; -static struct s3c_iotimings s3c24xx_iotiming; -static struct cpufreq_frequency_table *pll_reg; -static unsigned int last_target = ~0; -static unsigned int ftab_size; -static struct cpufreq_frequency_table *ftab; - -static struct clk *_clk_mpll; -static struct clk *_clk_xtal; -static struct clk *clk_fclk; -static struct clk *clk_hclk; -static struct clk *clk_pclk; -static struct clk *clk_arm; - -#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS -struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void) -{ - return &cpu_cur; -} - -struct s3c_iotimings *s3c_cpufreq_getiotimings(void) -{ - return &s3c24xx_iotiming; -} -#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUGFS */ - -static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg) -{ - unsigned long fclk, pclk, hclk, armclk; - - cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); - cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); - cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); - cfg->freq.armclk = armclk = clk_get_rate(clk_arm); - - cfg->pll.index = __raw_readl(S3C2410_MPLLCON); - cfg->pll.frequency = fclk; - - cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); - - cfg->divs.h_divisor = fclk / hclk; - cfg->divs.p_divisor = fclk / pclk; -} - -static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg) -{ - unsigned long pll = cfg->pll.frequency; - - cfg->freq.fclk = pll; - cfg->freq.hclk = pll / cfg->divs.h_divisor; - cfg->freq.pclk = pll / cfg->divs.p_divisor; - - /* convert hclk into 10ths of nanoseconds for io calcs */ - cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); -} - -static inline int closer(unsigned int target, unsigned int n, unsigned int c) -{ - int diff_cur = abs(target - c); - int diff_new = abs(target - n); - - return (diff_new < diff_cur); -} - -static void s3c_cpufreq_show(const char *pfx, - struct s3c_cpufreq_config *cfg) -{ - s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n", - pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk, - cfg->freq.hclk, cfg->divs.h_divisor, - cfg->freq.pclk, cfg->divs.p_divisor); -} - -/* functions to wrapper the driver info calls to do the cpu specific work */ - -static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg) -{ - if (cfg->info->set_iotiming) - (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming); -} - -static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg) -{ - if (cfg->info->calc_iotiming) - return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming); - - return 0; -} - -static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) -{ - (cfg->info->set_refresh)(cfg); -} - -static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) -{ - (cfg->info->set_divs)(cfg); -} - -static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) -{ - return (cfg->info->calc_divs)(cfg); -} - -static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg) -{ - (cfg->info->set_fvco)(cfg); -} - -static inline void s3c_cpufreq_resume_clocks(void) -{ - cpu_cur.info->resume_clocks(); -} - -static inline void s3c_cpufreq_updateclk(struct clk *clk, - unsigned int freq) -{ - clk_set_rate(clk, freq); -} - -static int s3c_cpufreq_settarget(struct cpufreq_policy *policy, - unsigned int target_freq, - struct cpufreq_frequency_table *pll) -{ - struct s3c_cpufreq_freqs freqs; - struct s3c_cpufreq_config cpu_new; - unsigned long flags; - - cpu_new = cpu_cur; /* copy new from current */ - - s3c_cpufreq_show("cur", &cpu_cur); - - /* TODO - check for DMA currently outstanding */ - - cpu_new.pll = pll ? *pll : cpu_cur.pll; - - if (pll) - freqs.pll_changing = 1; - - /* update our frequencies */ - - cpu_new.freq.armclk = target_freq; - cpu_new.freq.fclk = cpu_new.pll.frequency; - - if (s3c_cpufreq_calcdivs(&cpu_new) < 0) { - printk(KERN_ERR "no divisors for %d\n", target_freq); - goto err_notpossible; - } - - s3c_freq_dbg("%s: got divs\n", __func__); - - s3c_cpufreq_calc(&cpu_new); - - s3c_freq_dbg("%s: calculated frequencies for new\n", __func__); - - if (cpu_new.freq.hclk != cpu_cur.freq.hclk) { - if (s3c_cpufreq_calcio(&cpu_new) < 0) { - printk(KERN_ERR "%s: no IO timings\n", __func__); - goto err_notpossible; - } - } - - s3c_cpufreq_show("new", &cpu_new); - - /* setup our cpufreq parameters */ - - freqs.old = cpu_cur.freq; - freqs.new = cpu_new.freq; - - freqs.freqs.old = cpu_cur.freq.armclk / 1000; - freqs.freqs.new = cpu_new.freq.armclk / 1000; - - /* update f/h/p clock settings before we issue the change - * notification, so that drivers do not need to do anything - * special if they want to recalculate on CPUFREQ_PRECHANGE. */ - - s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency); - s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk); - s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk); - s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk); - - /* start the frequency change */ - cpufreq_notify_transition(policy, &freqs.freqs, CPUFREQ_PRECHANGE); - - /* If hclk is staying the same, then we do not need to - * re-write the IO or the refresh timings whilst we are changing - * speed. */ - - local_irq_save(flags); - - /* is our memory clock slowing down? */ - if (cpu_new.freq.hclk < cpu_cur.freq.hclk) { - s3c_cpufreq_setrefresh(&cpu_new); - s3c_cpufreq_setio(&cpu_new); - } - - if (cpu_new.freq.fclk == cpu_cur.freq.fclk) { - /* not changing PLL, just set the divisors */ - - s3c_cpufreq_setdivs(&cpu_new); - } else { - if (cpu_new.freq.fclk < cpu_cur.freq.fclk) { - /* slow the cpu down, then set divisors */ - - s3c_cpufreq_setfvco(&cpu_new); - s3c_cpufreq_setdivs(&cpu_new); - } else { - /* set the divisors, then speed up */ - - s3c_cpufreq_setdivs(&cpu_new); - s3c_cpufreq_setfvco(&cpu_new); - } - } - - /* did our memory clock speed up */ - if (cpu_new.freq.hclk > cpu_cur.freq.hclk) { - s3c_cpufreq_setrefresh(&cpu_new); - s3c_cpufreq_setio(&cpu_new); - } - - /* update our current settings */ - cpu_cur = cpu_new; - - local_irq_restore(flags); - - /* notify everyone we've done this */ - cpufreq_notify_transition(policy, &freqs.freqs, CPUFREQ_POSTCHANGE); - - s3c_freq_dbg("%s: finished\n", __func__); - return 0; - - err_notpossible: - printk(KERN_ERR "no compatible settings for %d\n", target_freq); - return -EINVAL; -} - -/* s3c_cpufreq_target - * - * called by the cpufreq core to adjust the frequency that the CPU - * is currently running at. - */ - -static int s3c_cpufreq_target(struct cpufreq_policy *policy, - unsigned int target_freq, - unsigned int relation) -{ - struct cpufreq_frequency_table *pll; - unsigned int index; - - /* avoid repeated calls which cause a needless amout of duplicated - * logging output (and CPU time as the calculation process is - * done) */ - if (target_freq == last_target) - return 0; - - last_target = target_freq; - - s3c_freq_dbg("%s: policy %p, target %u, relation %u\n", - __func__, policy, target_freq, relation); - - if (ftab) { - if (cpufreq_frequency_table_target(policy, ftab, - target_freq, relation, - &index)) { - s3c_freq_dbg("%s: table failed\n", __func__); - return -EINVAL; - } - - s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__, - target_freq, index, ftab[index].frequency); - target_freq = ftab[index].frequency; - } - - target_freq *= 1000; /* convert target to Hz */ - - /* find the settings for our new frequency */ - - if (!pll_reg || cpu_cur.lock_pll) { - /* either we've not got any PLL values, or we've locked - * to the current one. */ - pll = NULL; - } else { - struct cpufreq_policy tmp_policy; - int ret; - - /* we keep the cpu pll table in Hz, to ensure we get an - * accurate value for the PLL output. */ - - tmp_policy.min = policy->min * 1000; - tmp_policy.max = policy->max * 1000; - tmp_policy.cpu = policy->cpu; - - /* cpufreq_frequency_table_target uses a pointer to 'index' - * which is the number of the table entry, not the value of - * the table entry's index field. */ - - ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg, - target_freq, relation, - &index); - - if (ret < 0) { - printk(KERN_ERR "%s: no PLL available\n", __func__); - goto err_notpossible; - } - - pll = pll_reg + index; - - s3c_freq_dbg("%s: target %u => %u\n", - __func__, target_freq, pll->frequency); - - target_freq = pll->frequency; - } - - return s3c_cpufreq_settarget(policy, target_freq, pll); - - err_notpossible: - printk(KERN_ERR "no compatible settings for %d\n", target_freq); - return -EINVAL; -} - -static unsigned int s3c_cpufreq_get(unsigned int cpu) -{ - return clk_get_rate(clk_arm) / 1000; -} - -struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name) -{ - struct clk *clk; - - clk = clk_get(dev, name); - if (IS_ERR(clk)) - printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name); - - return clk; -} - -static int s3c_cpufreq_init(struct cpufreq_policy *policy) -{ - printk(KERN_INFO "%s: initialising policy %p\n", __func__, policy); - - if (policy->cpu != 0) - return -EINVAL; - - policy->cur = s3c_cpufreq_get(0); - policy->min = policy->cpuinfo.min_freq = 0; - policy->max = policy->cpuinfo.max_freq = cpu_cur.info->max.fclk / 1000; - policy->governor = CPUFREQ_DEFAULT_GOVERNOR; - - /* feed the latency information from the cpu driver */ - policy->cpuinfo.transition_latency = cpu_cur.info->latency; - - if (ftab) - cpufreq_frequency_table_cpuinfo(policy, ftab); - - return 0; -} - -static __init int s3c_cpufreq_initclks(void) -{ - _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll"); - _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal"); - clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk"); - clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk"); - clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk"); - clk_arm = s3c_cpufreq_clk_get(NULL, "armclk"); - - if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) || - IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) { - printk(KERN_ERR "%s: could not get clock(s)\n", __func__); - return -ENOENT; - } - - printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__, - clk_get_rate(clk_fclk) / 1000, - clk_get_rate(clk_hclk) / 1000, - clk_get_rate(clk_pclk) / 1000, - clk_get_rate(clk_arm) / 1000); - - return 0; -} - -static int s3c_cpufreq_verify(struct cpufreq_policy *policy) -{ - if (policy->cpu != 0) - return -EINVAL; - - return 0; -} - -#ifdef CONFIG_PM -static struct cpufreq_frequency_table suspend_pll; -static unsigned int suspend_freq; - -static int s3c_cpufreq_suspend(struct cpufreq_policy *policy) -{ - suspend_pll.frequency = clk_get_rate(_clk_mpll); - suspend_pll.index = __raw_readl(S3C2410_MPLLCON); - suspend_freq = s3c_cpufreq_get(0) * 1000; - - return 0; -} - -static int s3c_cpufreq_resume(struct cpufreq_policy *policy) -{ - int ret; - - s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy); - - last_target = ~0; /* invalidate last_target setting */ - - /* first, find out what speed we resumed at. */ - s3c_cpufreq_resume_clocks(); - - /* whilst we will be called later on, we try and re-set the - * cpu frequencies as soon as possible so that we do not end - * up resuming devices and then immediately having to re-set - * a number of settings once these devices have restarted. - * - * as a note, it is expected devices are not used until they - * have been un-suspended and at that time they should have - * used the updated clock settings. - */ - - ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll); - if (ret) { - printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__); - return ret; - } - - return 0; -} -#else -#define s3c_cpufreq_resume NULL -#define s3c_cpufreq_suspend NULL -#endif - -static struct cpufreq_driver s3c24xx_driver = { - .flags = CPUFREQ_STICKY, - .verify = s3c_cpufreq_verify, - .target = s3c_cpufreq_target, - .get = s3c_cpufreq_get, - .init = s3c_cpufreq_init, - .suspend = s3c_cpufreq_suspend, - .resume = s3c_cpufreq_resume, - .name = "s3c24xx", -}; - - -int __init s3c_cpufreq_register(struct s3c_cpufreq_info *info) -{ - if (!info || !info->name) { - printk(KERN_ERR "%s: failed to pass valid information\n", - __func__); - return -EINVAL; - } - - printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n", - info->name); - - /* check our driver info has valid data */ - - BUG_ON(info->set_refresh == NULL); - BUG_ON(info->set_divs == NULL); - BUG_ON(info->calc_divs == NULL); - - /* info->set_fvco is optional, depending on whether there - * is a need to set the clock code. */ - - cpu_cur.info = info; - - /* Note, driver registering should probably update locktime */ - - return 0; -} - -int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) -{ - struct s3c_cpufreq_board *ours; - - if (!board) { - printk(KERN_INFO "%s: no board data\n", __func__); - return -EINVAL; - } - - /* Copy the board information so that each board can make this - * initdata. */ - - ours = kzalloc(sizeof(struct s3c_cpufreq_board), GFP_KERNEL); - if (ours == NULL) { - printk(KERN_ERR "%s: no memory\n", __func__); - return -ENOMEM; - } - - *ours = *board; - cpu_cur.board = ours; - - return 0; -} - -int __init s3c_cpufreq_auto_io(void) -{ - int ret; - - if (!cpu_cur.info->get_iotiming) { - printk(KERN_ERR "%s: get_iotiming undefined\n", __func__); - return -ENOENT; - } - - printk(KERN_INFO "%s: working out IO settings\n", __func__); - - ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming); - if (ret) - printk(KERN_ERR "%s: failed to get timings\n", __func__); - - return ret; -} - -/* if one or is zero, then return the other, otherwise return the min */ -#define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b)) - -/** - * s3c_cpufreq_freq_min - find the minimum settings for the given freq. - * @dst: The destination structure - * @a: One argument. - * @b: The other argument. - * - * Create a minimum of each frequency entry in the 'struct s3c_freq', - * unless the entry is zero when it is ignored and the non-zero argument - * used. - */ -static void s3c_cpufreq_freq_min(struct s3c_freq *dst, - struct s3c_freq *a, struct s3c_freq *b) -{ - dst->fclk = do_min(a->fclk, b->fclk); - dst->hclk = do_min(a->hclk, b->hclk); - dst->pclk = do_min(a->pclk, b->pclk); - dst->armclk = do_min(a->armclk, b->armclk); -} - -static inline u32 calc_locktime(u32 freq, u32 time_us) -{ - u32 result; - - result = freq * time_us; - result = DIV_ROUND_UP(result, 1000 * 1000); - - return result; -} - -static void s3c_cpufreq_update_loctkime(void) -{ - unsigned int bits = cpu_cur.info->locktime_bits; - u32 rate = (u32)clk_get_rate(_clk_xtal); - u32 val; - - if (bits == 0) { - WARN_ON(1); - return; - } - - val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits; - val |= calc_locktime(rate, cpu_cur.info->locktime_m); - - printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val); - __raw_writel(val, S3C2410_LOCKTIME); -} - -static int s3c_cpufreq_build_freq(void) -{ - int size, ret; - - if (!cpu_cur.info->calc_freqtable) - return -EINVAL; - - kfree(ftab); - ftab = NULL; - - size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0); - size++; - - ftab = kmalloc(sizeof(struct cpufreq_frequency_table) * size, GFP_KERNEL); - if (!ftab) { - printk(KERN_ERR "%s: no memory for tables\n", __func__); - return -ENOMEM; - } - - ftab_size = size; - - ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size); - s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END); - - return 0; -} - -static int __init s3c_cpufreq_initcall(void) -{ - int ret = 0; - - if (cpu_cur.info && cpu_cur.board) { - ret = s3c_cpufreq_initclks(); - if (ret) - goto out; - - /* get current settings */ - s3c_cpufreq_getcur(&cpu_cur); - s3c_cpufreq_show("cur", &cpu_cur); - - if (cpu_cur.board->auto_io) { - ret = s3c_cpufreq_auto_io(); - if (ret) { - printk(KERN_ERR "%s: failed to get io timing\n", - __func__); - goto out; - } - } - - if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) { - printk(KERN_ERR "%s: no IO support registered\n", - __func__); - ret = -EINVAL; - goto out; - } - - if (!cpu_cur.info->need_pll) - cpu_cur.lock_pll = 1; - - s3c_cpufreq_update_loctkime(); - - s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max, - &cpu_cur.info->max); - - if (cpu_cur.info->calc_freqtable) - s3c_cpufreq_build_freq(); - - ret = cpufreq_register_driver(&s3c24xx_driver); - } - - out: - return ret; -} - -late_initcall(s3c_cpufreq_initcall); - -/** - * s3c_plltab_register - register CPU PLL table. - * @plls: The list of PLL entries. - * @plls_no: The size of the PLL entries @plls. - * - * Register the given set of PLLs with the system. - */ -int __init s3c_plltab_register(struct cpufreq_frequency_table *plls, - unsigned int plls_no) -{ - struct cpufreq_frequency_table *vals; - unsigned int size; - - size = sizeof(struct cpufreq_frequency_table) * (plls_no + 1); - - vals = kmalloc(size, GFP_KERNEL); - if (vals) { - memcpy(vals, plls, size); - pll_reg = vals; - - /* write a terminating entry, we don't store it in the - * table that is stored in the kernel */ - vals += plls_no; - vals->frequency = CPUFREQ_TABLE_END; - - printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no); - } else - printk(KERN_ERR "cpufreq: no memory for PLL tables\n"); - - return vals ? 0 : -ENOMEM; -} diff --git a/arch/arm/mach-s3c24xx/dma-s3c2410.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c index 30aa53ff07a..09aa12da178 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2410.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2410.c @@ -16,6 +16,7 @@ #include <linux/init.h> #include <linux/device.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <mach/map.h> #include <mach/dma.h> @@ -23,7 +24,6 @@ #include <plat/cpu.h> #include <plat/dma-s3c24xx.h> -#include <plat/regs-serial.h> #include <mach/regs-gpio.h> #include <plat/regs-dma.h> #include <mach/regs-lcd.h> diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c index ab1700ec8e6..0c0106d1a4d 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2412.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c @@ -16,6 +16,7 @@ #include <linux/init.h> #include <linux/device.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/io.h> #include <mach/dma.h> @@ -23,7 +24,6 @@ #include <plat/dma-s3c24xx.h> #include <plat/cpu.h> -#include <plat/regs-serial.h> #include <mach/regs-gpio.h> #include <plat/regs-dma.h> #include <mach/regs-lcd.h> @@ -35,121 +35,95 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = { [DMACH_XD0] = { .name = "xdreq0", .channels = MAP(S3C2412_DMAREQSEL_XDREQ0), - .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ0), }, [DMACH_XD1] = { .name = "xdreq1", .channels = MAP(S3C2412_DMAREQSEL_XDREQ1), - .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ1), }, [DMACH_SDI] = { .name = "sdi", .channels = MAP(S3C2412_DMAREQSEL_SDI), - .channels_rx = MAP(S3C2412_DMAREQSEL_SDI), }, - [DMACH_SPI0] = { - .name = "spi0", + [DMACH_SPI0_RX] = { + .name = "spi0-rx", + .channels = MAP(S3C2412_DMAREQSEL_SPI0RX), + }, + [DMACH_SPI0_TX] = { + .name = "spi0-tx", .channels = MAP(S3C2412_DMAREQSEL_SPI0TX), - .channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX), }, - [DMACH_SPI1] = { - .name = "spi1", + [DMACH_SPI1_RX] = { + .name = "spi1-rx", + .channels = MAP(S3C2412_DMAREQSEL_SPI1RX), + }, + [DMACH_SPI1_TX] = { + .name = "spi1-tx", .channels = MAP(S3C2412_DMAREQSEL_SPI1TX), - .channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX), }, [DMACH_UART0] = { .name = "uart0", .channels = MAP(S3C2412_DMAREQSEL_UART0_0), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0), }, [DMACH_UART1] = { .name = "uart1", .channels = MAP(S3C2412_DMAREQSEL_UART1_0), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0), }, [DMACH_UART2] = { .name = "uart2", .channels = MAP(S3C2412_DMAREQSEL_UART2_0), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0), }, [DMACH_UART0_SRC2] = { .name = "uart0", .channels = MAP(S3C2412_DMAREQSEL_UART0_1), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1), }, [DMACH_UART1_SRC2] = { .name = "uart1", .channels = MAP(S3C2412_DMAREQSEL_UART1_1), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1), }, [DMACH_UART2_SRC2] = { .name = "uart2", .channels = MAP(S3C2412_DMAREQSEL_UART2_1), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1), }, [DMACH_TIMER] = { .name = "timer", .channels = MAP(S3C2412_DMAREQSEL_TIMER), - .channels_rx = MAP(S3C2412_DMAREQSEL_TIMER), }, [DMACH_I2S_IN] = { .name = "i2s-sdi", .channels = MAP(S3C2412_DMAREQSEL_I2SRX), - .channels_rx = MAP(S3C2412_DMAREQSEL_I2SRX), }, [DMACH_I2S_OUT] = { .name = "i2s-sdo", .channels = MAP(S3C2412_DMAREQSEL_I2STX), - .channels_rx = MAP(S3C2412_DMAREQSEL_I2STX), }, [DMACH_USB_EP1] = { .name = "usb-ep1", .channels = MAP(S3C2412_DMAREQSEL_USBEP1), - .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP1), }, [DMACH_USB_EP2] = { .name = "usb-ep2", .channels = MAP(S3C2412_DMAREQSEL_USBEP2), - .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP2), }, [DMACH_USB_EP3] = { .name = "usb-ep3", .channels = MAP(S3C2412_DMAREQSEL_USBEP3), - .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP3), }, [DMACH_USB_EP4] = { .name = "usb-ep4", .channels = MAP(S3C2412_DMAREQSEL_USBEP4), - .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP4), }, }; -static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan, - struct s3c24xx_dma_map *map, - enum dma_data_direction dir) -{ - unsigned long chsel; - - if (dir == DMA_FROM_DEVICE) - chsel = map->channels_rx[0]; - else - chsel = map->channels[0]; - - chsel &= ~DMA_CH_VALID; - chsel |= S3C2412_DMAREQSEL_HW; - - writel(chsel, chan->regs + S3C2412_DMA_DMAREQSEL); -} - static void s3c2412_dma_select(struct s3c2410_dma_chan *chan, struct s3c24xx_dma_map *map) { - s3c2412_dma_direction(chan, map, chan->source); + unsigned long chsel = map->channels[0] & (~DMA_CH_VALID); + writel(chsel | S3C2412_DMAREQSEL_HW, + chan->regs + S3C2412_DMA_DMAREQSEL); } static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = { .select = s3c2412_dma_select, - .direction = s3c2412_dma_direction, .dcon_mask = 0, .map = s3c2412_dma_mappings, .map_size = ARRAY_SIZE(s3c2412_dma_mappings), diff --git a/arch/arm/mach-s3c24xx/dma-s3c2440.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c index cd25de28804..2f8e8a3017d 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2440.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2440.c @@ -16,6 +16,7 @@ #include <linux/init.h> #include <linux/device.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <mach/map.h> #include <mach/dma.h> @@ -23,7 +24,6 @@ #include <plat/dma-s3c24xx.h> #include <plat/cpu.h> -#include <plat/regs-serial.h> #include <mach/regs-gpio.h> #include <plat/regs-dma.h> #include <mach/regs-lcd.h> diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c index 5fe3539dc2b..f4096ec0700 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2443.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c @@ -16,6 +16,7 @@ #include <linux/init.h> #include <linux/device.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/io.h> #include <mach/dma.h> @@ -23,7 +24,6 @@ #include <plat/dma-s3c24xx.h> #include <plat/cpu.h> -#include <plat/regs-serial.h> #include <mach/regs-gpio.h> #include <plat/regs-dma.h> #include <mach/regs-lcd.h> @@ -128,7 +128,8 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = { static void s3c2443_dma_select(struct s3c2410_dma_chan *chan, struct s3c24xx_dma_map *map) { - writel(map->channels[0] | S3C2443_DMAREQSEL_HW, + unsigned long chsel = map->channels[0] & (~DMA_CH_VALID); + writel(chsel | S3C2443_DMAREQSEL_HW, chan->regs + S3C2443_DMA_DMAREQSEL); } diff --git a/arch/arm/mach-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c index aab64909e9a..a8dafc174fe 100644 --- a/arch/arm/mach-s3c24xx/dma.c +++ b/arch/arm/mach-s3c24xx/dma.c @@ -742,7 +742,7 @@ int s3c2410_dma_request(enum dma_ch channel, chan->irq_claimed = 1; local_irq_restore(flags); - err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED, + err = request_irq(chan->irq, s3c2410_dma_irq, 0, client->name, (void *)chan); local_irq_save(flags); @@ -1159,9 +1159,6 @@ int s3c2410_dma_devconfig(enum dma_ch channel, return -EINVAL; } - if (dma_sel.direction != NULL) - (dma_sel.direction)(chan, chan->map, source); - return 0; } diff --git a/arch/arm/mach-s3c24xx/h1940-bluetooth.c b/arch/arm/mach-s3c24xx/h1940-bluetooth.c index 5b98bfd1df4..b4d14b86436 100644 --- a/arch/arm/mach-s3c24xx/h1940-bluetooth.c +++ b/arch/arm/mach-s3c24xx/h1940-bluetooth.c @@ -19,8 +19,10 @@ #include <linux/gpio.h> #include <linux/rfkill.h> +#include <plat/gpio-cfg.h> #include <mach/hardware.h> #include <mach/regs-gpio.h> +#include <mach/gpio-samsung.h> #include "h1940.h" diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S deleted file mode 100644 index 2558952e314..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S +++ /dev/null @@ -1,101 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Copyright (C) 2005 Simtec Electronics - * - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <mach/map.h> -#include <mach/regs-gpio.h> -#include <plat/regs-serial.h> - -#define S3C2410_UART1_OFF (0x4000) -#define SHIFT_2440TXF (14-9) - - .macro addruart, rp, rv, tmp - ldr \rp, = S3C24XX_PA_UART - ldr \rv, = S3C24XX_VA_UART -#if CONFIG_DEBUG_S3C_UART != 0 - add \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) - add \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) -#endif - .endm - - .macro fifo_full_s3c24xx rd, rx - @ check for arm920 vs arm926. currently assume all arm926 - @ devices have an 64 byte FIFO identical to the s3c2440 - mrc p15, 0, \rd, c0, c0 - and \rd, \rd, #0xff0 - teq \rd, #0x260 - beq 1004f - mrc p15, 0, \rd, c1, c0 - tst \rd, #1 - addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) - addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) - bic \rd, \rd, #0xff000 - ldr \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)] - and \rd, \rd, #0x00ff0000 - teq \rd, #0x00440000 @ is it 2440? -1004: - ldr \rd, [\rx, # S3C2410_UFSTAT] - moveq \rd, \rd, lsr #SHIFT_2440TXF - tst \rd, #S3C2410_UFSTAT_TXFULL - .endm - - .macro fifo_full_s3c2410 rd, rx - ldr \rd, [\rx, # S3C2410_UFSTAT] - tst \rd, #S3C2410_UFSTAT_TXFULL - .endm - -/* fifo level reading */ - - .macro fifo_level_s3c24xx rd, rx - @ check for arm920 vs arm926. currently assume all arm926 - @ devices have an 64 byte FIFO identical to the s3c2440 - mrc p15, 0, \rd, c0, c0 - and \rd, \rd, #0xff0 - teq \rd, #0x260 - beq 10000f - mrc p15, 0, \rd, c1, c0 - tst \rd, #1 - addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) - addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) - bic \rd, \rd, #0xff000 - ldr \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)] - and \rd, \rd, #0x00ff0000 - teq \rd, #0x00440000 @ is it 2440? - -10000: - ldr \rd, [\rx, # S3C2410_UFSTAT] - andne \rd, \rd, #S3C2410_UFSTAT_TXMASK - andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK - .endm - - .macro fifo_level_s3c2410 rd, rx - ldr \rd, [\rx, # S3C2410_UFSTAT] - and \rd, \rd, #S3C2410_UFSTAT_TXMASK - .endm - -/* Select the correct implementation depending on the configuration. The - * S3C2440 will get selected by default, as these are the most widely - * used variants of these -*/ - -#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY) -#define fifo_full fifo_full_s3c2410 -#define fifo_level fifo_level_s3c2410 -#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY) -#define fifo_full fifo_full_s3c24xx -#define fifo_level fifo_level_s3c24xx -#endif - -/* include the reset of the code which will do the work */ - -#include <debug/samsung.S> diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio.h b/arch/arm/mach-s3c24xx/include/mach/gpio-samsung.h index 14591563ca7..528fcdc4f63 100644 --- a/arch/arm/mach-s3c24xx/include/mach/gpio.h +++ b/arch/arm/mach-s3c24xx/include/mach/gpio-samsung.h @@ -14,16 +14,8 @@ * devices that need GPIO. */ -#ifndef __MACH_GPIO_H -#define __MACH_GPIO_H __FILE__ - -#ifdef CONFIG_CPU_S3C244X -#define ARCH_NR_GPIOS (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA) -#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) -#define ARCH_NR_GPIOS (32 * 12 + CONFIG_S3C24XX_GPIO_EXTRA) -#else -#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA) -#endif +#ifndef GPIO_SAMSUNG_S3C24XX_H +#define GPIO_SAMSUNG_S3C24XX_H /* * GPIO sizes for various SoCs: @@ -31,17 +23,17 @@ * 2410 2412 2440 2443 2416 * 2442 * ---- ---- ---- ---- ---- - * A 23 22 25 16 25 - * B 11 11 11 11 9 - * C 16 15 16 16 16 + * A 23 22 25 16 27 + * B 11 11 11 11 11 + * C 16 16 16 16 16 * D 16 16 16 16 16 * E 16 16 16 16 16 * F 8 8 8 8 8 * G 16 16 16 16 8 - * H 11 11 9 15 15 + * H 11 11 11 15 15 * J -- -- 13 16 -- * K -- -- -- -- 16 - * L -- -- -- 15 7 + * L -- -- -- 15 14 * M -- -- -- 2 2 */ @@ -101,8 +93,6 @@ enum s3c_gpio_number { #define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr)) #define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr)) -#include <plat/gpio-cfg.h> - #ifdef CONFIG_CPU_S3C244X #define S3C_GPIO_END (S3C2410_GPJ(0) + 32) #elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) @@ -111,4 +101,4 @@ enum s3c_gpio_number { #define S3C_GPIO_END (S3C2410_GPH(0) + 32) #endif -#endif /* __MACH_GPIO_H */ +#endif /* GPIO_SAMSUNG_S3C24XX_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/hardware.h b/arch/arm/mach-s3c24xx/include/mach/hardware.h index a6cc14a092f..dedd3837c19 100644 --- a/arch/arm/mach-s3c24xx/include/mach/hardware.h +++ b/arch/arm/mach-s3c24xx/include/mach/hardware.h @@ -1,5 +1,4 @@ -/* arch/arm/mach-s3c2410/include/mach/hardware.h - * +/* * Copyright (c) 2003 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * @@ -17,20 +16,9 @@ extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); -#ifdef CONFIG_CPU_S3C2440 - -extern int s3c2440_set_dsc(unsigned int pin, unsigned int value); - -#endif /* CONFIG_CPU_S3C2440 */ - #endif /* __ASSEMBLY__ */ #include <asm/sizes.h> #include <mach/map.h> -/* machine specific hardware definitions should go after this */ - -/* currently here until moved into config (todo) */ -#define CONFIG_NO_MULTIWORD_IO - #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/map.h b/arch/arm/mach-s3c24xx/include/mach/map.h index 8ba381f2dbe..444793f0f5f 100644 --- a/arch/arm/mach-s3c24xx/include/mach/map.h +++ b/arch/arm/mach-s3c24xx/include/mach/map.h @@ -167,4 +167,6 @@ #define S3C_PA_SPI0 S3C2443_PA_SPI0 #define S3C_PA_SPI1 S3C2443_PA_SPI1 +#define SAMSUNG_PA_TIMER S3C2410_PA_TIMER + #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-clock.h b/arch/arm/mach-s3c24xx/include/mach/regs-clock.h index 3415b60082d..3db6c10de02 100644 --- a/arch/arm/mach-s3c24xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c24xx/include/mach/regs-clock.h @@ -42,24 +42,6 @@ #define S3C2410_CLKCON_IIS (1<<17) #define S3C2410_CLKCON_SPI (1<<18) -/* DCLKCON register addresses in gpio.h */ - -#define S3C2410_DCLKCON_DCLK0EN (1<<0) -#define S3C2410_DCLKCON_DCLK0_PCLK (0<<1) -#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1) -#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4) -#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8) -#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4) -#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8) - -#define S3C2410_DCLKCON_DCLK1EN (1<<16) -#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17) -#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17) -#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20) -#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24) -#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20) -#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24) - #define S3C2410_CLKDIVN_PDIVN (1<<0) #define S3C2410_CLKDIVN_HDIVN (1<<1) diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h index c2ef016032a..c6583cfa583 100644 --- a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h @@ -457,9 +457,6 @@ /* miscellaneous control */ #define S3C2410_MISCCR S3C2410_GPIOREG(0x80) -#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) - -#define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84) /* see clock.h for dclk definitions */ diff --git a/arch/arm/mach-s3c24xx/include/mach/rtc-core.h b/arch/arm/mach-s3c24xx/include/mach/rtc-core.h new file mode 100644 index 00000000000..4d5f5768f70 --- /dev/null +++ b/arch/arm/mach-s3c24xx/include/mach/rtc-core.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2011 Heiko Stuebner <heiko@sntech.de> + * + * Samsung RTC Controller core functions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __RTC_CORE_H +#define __RTC_CORE_H __FILE__ + +/* These functions are only for use with the core support code, such as + * the cpu specific initialisation code + */ + +extern struct platform_device s3c_device_rtc; + +/* re-define device name depending on support. */ +static inline void s3c_rtc_setname(char *name) +{ + s3c_device_rtc.name = name; +} + +#endif /* __RTC_CORE_H */ diff --git a/arch/arm/mach-s3c24xx/s3c2412.h b/arch/arm/mach-s3c24xx/include/mach/s3c2412.h index 548ced42cbb..548ced42cbb 100644 --- a/arch/arm/mach-s3c24xx/s3c2412.h +++ b/arch/arm/mach-s3c24xx/include/mach/s3c2412.h diff --git a/arch/arm/mach-s3c24xx/include/mach/tick.h b/arch/arm/mach-s3c24xx/include/mach/tick.h deleted file mode 100644 index 544da41979d..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/tick.h +++ /dev/null @@ -1,15 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/include/mach/tick.h - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C2410 - timer tick support - */ - -#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0)) - -static inline int s3c24xx_ostimer_pending(void) -{ - return __raw_readl(S3C2410_SRCPND) & SRCPND_TIMER4; -} diff --git a/arch/arm/mach-s3c24xx/include/mach/timex.h b/arch/arm/mach-s3c24xx/include/mach/timex.h deleted file mode 100644 index fe9ca1ffd51..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/timex.h +++ /dev/null @@ -1,24 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/timex.h - * - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - time parameters - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it - * a variable is useless. It seems as long as we make our timers an - * exact multiple of HZ, any value that makes a 1->1 correspondence - * for the time conversion functions to/from jiffies is acceptable. -*/ - -#define CLOCK_TICK_RATE 12000000 - -#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/uncompress.h b/arch/arm/mach-s3c24xx/include/mach/uncompress.h deleted file mode 100644 index 8b283f847da..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/uncompress.h +++ /dev/null @@ -1,54 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/uncompress.h - * - * Copyright (c) 2003-2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - uncompress code - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include <mach/regs-gpio.h> -#include <mach/map.h> - -/* working in physical space... */ -#undef S3C2410_GPIOREG -#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x))) - -#include <plat/uncompress.h> - -static inline int is_arm926(void) -{ - unsigned int cpuid; - - asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid)); - - return ((cpuid & 0xff0) == 0x260); -} - -static void arch_detect_cpu(void) -{ - unsigned int cpuid; - - cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1); - cpuid &= S3C2410_GSTATUS1_IDMASK; - - if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 || - cpuid == S3C2410_GSTATUS1_2442 || - cpuid == S3C2410_GSTATUS1_2416 || - cpuid == S3C2410_GSTATUS1_2450) { - fifo_mask = S3C2440_UFSTAT_TXMASK; - fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; - } else { - fifo_mask = S3C2410_UFSTAT_TXMASK; - fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT; - } -} - -#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c index 663436d9db0..bd064c05c47 100644 --- a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c +++ b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c @@ -31,7 +31,7 @@ #include <plat/cpu-freq-core.h> #include <plat/clock.h> -#include "s3c2412.h" +#include <mach/s3c2412.h> #define print_ns(x) ((x) / 10), ((x) % 10) diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c index e27b5c91b3d..5157e250dd1 100644 --- a/arch/arm/mach-s3c24xx/mach-amlm5900.c +++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c @@ -37,6 +37,7 @@ #include <linux/platform_device.h> #include <linux/proc_fs.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/io.h> #include <asm/mach/arch.h> @@ -49,9 +50,9 @@ #include <asm/mach-types.h> #include <mach/fb.h> -#include <plat/regs-serial.h> #include <mach/regs-lcd.h> #include <mach/regs-gpio.h> +#include <mach/gpio-samsung.h> #include <linux/platform_data/i2c-s3c2410.h> #include <plat/devs.h> @@ -160,11 +161,16 @@ static struct platform_device *amlm5900_devices[] __initdata = { static void __init amlm5900_map_io(void) { s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc)); - s3c24xx_init_clocks(0); s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init amlm5900_init_time(void) +{ + s3c2410_init_clocks(12000000); + samsung_timer_init(); +} + #ifdef CONFIG_FB_S3C2410 static struct s3c2410fb_display __initdata amlm5900_lcd_info = { .width = 160, @@ -240,6 +246,6 @@ MACHINE_START(AML_M5900, "AML_M5900") .map_io = amlm5900_map_io, .init_irq = s3c2410_init_irq, .init_machine = amlm5900_init, - .init_time = samsung_timer_init, + .init_time = amlm5900_init_time, .restart = s3c2410_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c index c1fb6c37867..e053581cab0 100644 --- a/arch/arm/mach-s3c24xx/mach-anubis.c +++ b/arch/arm/mach-s3c24xx/mach-anubis.c @@ -17,6 +17,7 @@ #include <linux/init.h> #include <linux/gpio.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> #include <linux/ata_platform.h> #include <linux/i2c.h> @@ -32,9 +33,9 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <plat/regs-serial.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> +#include <mach/gpio-samsung.h> #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/i2c-s3c2410.h> @@ -45,7 +46,6 @@ #include <net/ax88796.h> -#include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> #include <linux/platform_data/asoc-s3c24xx_simtec.h> @@ -351,6 +351,7 @@ static struct platform_device anubis_device_sm501 = { /* Standard Anubis devices */ static struct platform_device *anubis_devices[] __initdata = { + &s3c2410_device_dclk, &s3c_device_ohci, &s3c_device_wdt, &s3c_device_adc, @@ -363,14 +364,6 @@ static struct platform_device *anubis_devices[] __initdata = { &anubis_device_sm501, }; -static struct clk *anubis_clocks[] __initdata = { - &s3c24xx_dclk0, - &s3c24xx_dclk1, - &s3c24xx_clkout0, - &s3c24xx_clkout1, - &s3c24xx_uclk, -}; - /* I2C devices. */ static struct i2c_board_info anubis_i2c_devs[] __initdata = { @@ -393,23 +386,7 @@ static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = { static void __init anubis_map_io(void) { - /* initialise the clocks */ - - s3c24xx_dclk0.parent = &clk_upll; - s3c24xx_dclk0.rate = 12*1000*1000; - - s3c24xx_dclk1.parent = &clk_upll; - s3c24xx_dclk1.rate = 24*1000*1000; - - s3c24xx_clkout0.parent = &s3c24xx_dclk0; - s3c24xx_clkout1.parent = &s3c24xx_dclk1; - - s3c24xx_uclk.parent = &s3c24xx_clkout1; - - s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks)); - s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc)); - s3c24xx_init_clocks(0); s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); @@ -427,6 +404,12 @@ static void __init anubis_map_io(void) } } +static void __init anubis_init_time(void) +{ + s3c2440_init_clocks(12000000); + samsung_timer_init(); +} + static void __init anubis_init(void) { s3c_i2c0_set_platdata(NULL); @@ -446,6 +429,6 @@ MACHINE_START(ANUBIS, "Simtec-Anubis") .map_io = anubis_map_io, .init_machine = anubis_init, .init_irq = s3c2440_init_irq, - .init_time = samsung_timer_init, + .init_time = anubis_init_time, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c index 6dfeeb7ef46..9db768f448a 100644 --- a/arch/arm/mach-s3c24xx/mach-at2440evb.c +++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c @@ -21,6 +21,7 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/dm9000.h> #include <linux/platform_device.h> @@ -33,9 +34,9 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <plat/regs-serial.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> +#include <mach/gpio-samsung.h> #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/i2c-s3c2410.h> @@ -44,7 +45,6 @@ #include <linux/mtd/nand_ecc.h> #include <linux/mtd/partitions.h> -#include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> #include <linux/platform_data/mmc-s3cmci.h> @@ -191,11 +191,16 @@ static struct platform_device *at2440evb_devices[] __initdata = { static void __init at2440evb_map_io(void) { s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc)); - s3c24xx_init_clocks(16934400); s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init at2440evb_init_time(void) +{ + s3c2440_init_clocks(16934400); + samsung_timer_init(); +} + static void __init at2440evb_init(void) { s3c24xx_fb_set_platdata(&at2440evb_fb_info); @@ -212,6 +217,6 @@ MACHINE_START(AT2440EVB, "AT2440EVB") .map_io = at2440evb_map_io, .init_machine = at2440evb_init, .init_irq = s3c2440_init_irq, - .init_time = samsung_timer_init, + .init_time = at2440evb_init_time, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c index 22d6ae926d9..f9112b801a3 100644 --- a/arch/arm/mach-s3c24xx/mach-bast.c +++ b/arch/arm/mach-s3c24xx/mach-bast.c @@ -19,6 +19,7 @@ #include <linux/gpio.h> #include <linux/syscore_ops.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> #include <linux/dm9000.h> #include <linux/ata_platform.h> @@ -48,13 +49,12 @@ #include <mach/hardware.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> +#include <mach/gpio-samsung.h> -#include <plat/clock.h> #include <plat/cpu.h> #include <plat/cpu-freq.h> #include <plat/devs.h> #include <plat/gpio-cfg.h> -#include <plat/regs-serial.h> #include <plat/samsung-time.h> #include "bast.h" @@ -522,6 +522,7 @@ static struct s3c_hwmon_pdata bast_hwmon_info = { // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0 static struct platform_device *bast_devices[] __initdata = { + &s3c2410_device_dclk, &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, @@ -536,14 +537,6 @@ static struct platform_device *bast_devices[] __initdata = { &bast_sio, }; -static struct clk *bast_clocks[] __initdata = { - &s3c24xx_dclk0, - &s3c24xx_dclk1, - &s3c24xx_clkout0, - &s3c24xx_clkout1, - &s3c24xx_uclk, -}; - static struct s3c_cpufreq_board __initdata bast_cpufreq = { .refresh = 7800, /* 7.8usec */ .auto_io = 1, @@ -557,29 +550,19 @@ static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = { static void __init bast_map_io(void) { - /* initialise the clocks */ - - s3c24xx_dclk0.parent = &clk_upll; - s3c24xx_dclk0.rate = 12*1000*1000; - - s3c24xx_dclk1.parent = &clk_upll; - s3c24xx_dclk1.rate = 24*1000*1000; - - s3c24xx_clkout0.parent = &s3c24xx_dclk0; - s3c24xx_clkout1.parent = &s3c24xx_dclk1; - - s3c24xx_uclk.parent = &s3c24xx_clkout1; - - s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); - s3c_hwmon_set_platdata(&bast_hwmon_info); s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); - s3c24xx_init_clocks(0); s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init bast_init_time(void) +{ + s3c2410_init_clocks(12000000); + samsung_timer_init(); +} + static void __init bast_init(void) { register_syscore_ops(&bast_pm_syscore_ops); @@ -607,6 +590,6 @@ MACHINE_START(BAST, "Simtec-BAST") .map_io = bast_map_io, .init_irq = s3c2410_init_irq, .init_machine = bast_init, - .init_time = samsung_timer_init, + .init_time = bast_init_time, .restart = s3c2410_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c index 13d8d073675..fc3a08d0cb3 100644 --- a/arch/arm/mach-s3c24xx/mach-gta02.c +++ b/arch/arm/mach-s3c24xx/mach-gta02.c @@ -35,6 +35,7 @@ #include <linux/workqueue.h> #include <linux/platform_device.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/input.h> #include <linux/io.h> #include <linux/i2c.h> @@ -75,12 +76,12 @@ #include <mach/hardware.h> #include <mach/regs-gpio.h> #include <mach/regs-irq.h> +#include <mach/gpio-samsung.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/gpio-cfg.h> #include <plat/pm.h> -#include <plat/regs-serial.h> #include <plat/samsung-time.h> #include "common.h" @@ -195,7 +196,7 @@ static void gta02_charger_worker(struct work_struct *work) * If the PCF50633 ADC is disabled we fallback to a * 100mA limit for safety. */ - pcf50633_mbc_usb_curlim_set(pcf, 100); + pcf50633_mbc_usb_curlim_set(gta02_pcf, 100); #endif } @@ -500,7 +501,6 @@ static struct platform_device gta02_buttons_device = { static void __init gta02_map_io(void) { s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc)); - s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } @@ -584,6 +584,11 @@ static void __init gta02_machine_init(void) regulator_has_full_constraints(); } +static void __init gta02_init_time(void) +{ + s3c2442_init_clocks(12000000); + samsung_timer_init(); +} MACHINE_START(NEO1973_GTA02, "GTA02") /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */ @@ -591,6 +596,6 @@ MACHINE_START(NEO1973_GTA02, "GTA02") .map_io = gta02_map_io, .init_irq = s3c2442_init_irq, .init_machine = gta02_machine_init, - .init_time = samsung_timer_init, + .init_time = gta02_init_time, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c index af4334d6b4d..fbf5487ae5d 100644 --- a/arch/arm/mach-s3c24xx/mach-h1940.c +++ b/arch/arm/mach-s3c24xx/mach-h1940.c @@ -19,6 +19,7 @@ #include <linux/init.h> #include <linux/device.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/gpio.h> @@ -54,14 +55,13 @@ #include <mach/regs-clock.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> +#include <mach/gpio-samsung.h> -#include <plat/clock.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/gpio-cfg.h> #include <plat/pll.h> #include <plat/pm.h> -#include <plat/regs-serial.h> #include <plat/samsung-time.h> #include "common.h" @@ -504,6 +504,7 @@ static struct platform_pwm_backlight_data backlight_data = { .dft_brightness = 50, /* tcnt = 0x31 */ .pwm_period_ns = 36296, + .enable_gpio = -1, .init = h1940_backlight_init, .notify = h1940_backlight_notify, .exit = h1940_backlight_exit, @@ -512,7 +513,7 @@ static struct platform_pwm_backlight_data backlight_data = { static struct platform_device h1940_backlight = { .name = "pwm-backlight", .dev = { - .parent = &s3c_device_timer[0].dev, + .parent = &samsung_device_pwm.dev, .platform_data = &backlight_data, }, .id = -1, @@ -632,7 +633,7 @@ static struct platform_device *h1940_devices[] __initdata = { &h1940_device_bluetooth, &s3c_device_sdi, &s3c_device_rtc, - &s3c_device_timer[0], + &samsung_device_pwm, &h1940_backlight, &h1940_lcd_powerdev, &s3c_device_adc, @@ -644,7 +645,6 @@ static struct platform_device *h1940_devices[] __initdata = { static void __init h1940_map_io(void) { s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc)); - s3c24xx_init_clocks(0); s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); @@ -660,6 +660,12 @@ static void __init h1940_map_io(void) WARN_ON(gpiochip_add(&h1940_latch_gpiochip)); } +static void __init h1940_init_time(void) +{ + s3c2410_init_clocks(12000000); + samsung_timer_init(); +} + /* H1940 and RX3715 need to reserve this for suspend */ static void __init h1940_reserve(void) { @@ -737,6 +743,6 @@ MACHINE_START(H1940, "IPAQ-H1940") .reserve = h1940_reserve, .init_irq = s3c2410_init_irq, .init_machine = h1940_init, - .init_time = samsung_timer_init, + .init_time = h1940_init_time, .restart = s3c2410_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c index a45fcd8ccf7..e81ea82c55f 100644 --- a/arch/arm/mach-s3c24xx/mach-jive.c +++ b/arch/arm/mach-s3c24xx/mach-jive.c @@ -19,6 +19,7 @@ #include <linux/gpio.h> #include <linux/syscore_ops.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> #include <linux/i2c.h> @@ -31,13 +32,13 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <plat/regs-serial.h> #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/i2c-s3c2410.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> #include <mach/fb.h> +#include <mach/gpio-samsung.h> #include <asm/mach-types.h> @@ -466,6 +467,7 @@ static struct platform_device *jive_devices[] __initdata = { &jive_device_wm8750, &s3c_device_nand, &s3c_device_usbgadget, + &s3c2412_device_dma, }; static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = { @@ -505,11 +507,16 @@ static struct syscore_ops jive_pm_syscore_ops = { static void __init jive_map_io(void) { s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc)); - s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init jive_init_time(void) +{ + s3c2412_init_clocks(12000000); + samsung_timer_init(); +} + static void jive_power_off(void) { printk(KERN_INFO "powering system down...\n"); @@ -663,6 +670,6 @@ MACHINE_START(JIVE, "JIVE") .init_irq = s3c2412_init_irq, .map_io = jive_map_io, .init_machine = jive_machine_init, - .init_time = samsung_timer_init, + .init_time = jive_init_time, .restart = s3c2412_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c index a83db46320b..5cc40ec1d25 100644 --- a/arch/arm/mach-s3c24xx/mach-mini2440.c +++ b/arch/arm/mach-s3c24xx/mach-mini2440.c @@ -23,8 +23,9 @@ #include <linux/input.h> #include <linux/io.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/dm9000.h> -#include <linux/i2c/at24.h> +#include <linux/platform_data/at24.h> #include <linux/platform_device.h> #include <linux/gpio_keys.h> #include <linux/i2c.h> @@ -37,11 +38,11 @@ #include <mach/fb.h> #include <asm/mach-types.h> -#include <plat/regs-serial.h> #include <mach/regs-gpio.h> #include <linux/platform_data/leds-s3c24xx.h> #include <mach/regs-lcd.h> #include <mach/irqs.h> +#include <mach/gpio-samsung.h> #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/i2c-s3c2410.h> #include <linux/platform_data/mmc-s3cmci.h> @@ -53,7 +54,6 @@ #include <linux/mtd/partitions.h> #include <plat/gpio-cfg.h> -#include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> #include <plat/samsung-time.h> @@ -524,11 +524,16 @@ static struct platform_device *mini2440_devices[] __initdata = { static void __init mini2440_map_io(void) { s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc)); - s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init mini2440_init_time(void) +{ + s3c2440_init_clocks(12000000); + samsung_timer_init(); +} + /* * mini2440_features string * @@ -689,6 +694,6 @@ MACHINE_START(MINI2440, "MINI2440") .map_io = mini2440_map_io, .init_machine = mini2440_init, .init_irq = s3c2440_init_irq, - .init_time = samsung_timer_init, + .init_time = mini2440_init_time, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c index 2cb46c37c92..3ac2a54348d 100644 --- a/arch/arm/mach-s3c24xx/mach-n30.c +++ b/arch/arm/mach-s3c24xx/mach-n30.c @@ -24,6 +24,7 @@ #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/timer.h> #include <linux/io.h> #include <linux/mmc/host.h> @@ -36,15 +37,14 @@ #include <linux/platform_data/leds-s3c24xx.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> +#include <mach/gpio-samsung.h> #include <asm/mach/arch.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/regs-serial.h> -#include <plat/clock.h> #include <plat/cpu.h> #include <plat/devs.h> #include <linux/platform_data/mmc-s3cmci.h> @@ -534,11 +534,16 @@ static void __init n30_map_io(void) { s3c24xx_init_io(n30_iodesc, ARRAY_SIZE(n30_iodesc)); n30_hwinit(); - s3c24xx_init_clocks(0); s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init n30_init_time(void) +{ + s3c2410_init_clocks(12000000); + samsung_timer_init(); +} + /* GPB3 is the line that controls the pull-up for the USB D+ line */ static void __init n30_init(void) @@ -590,7 +595,7 @@ MACHINE_START(N30, "Acer-N30") Ben Dooks <ben-linux@fluff.org> */ .atag_offset = 0x100, - .init_time = samsung_timer_init, + .init_time = n30_init_time, .init_machine = n30_init, .init_irq = s3c2410_init_irq, .map_io = n30_map_io, @@ -601,7 +606,7 @@ MACHINE_START(N35, "Acer-N35") /* Maintainer: Christer Weinigel <christer@weinigel.se> */ .atag_offset = 0x100, - .init_time = samsung_timer_init, + .init_time = n30_init_time, .init_machine = n30_init, .init_irq = s3c2410_init_irq, .map_io = n30_map_io, diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c index 01f4354206f..c82c281ce35 100644 --- a/arch/arm/mach-s3c24xx/mach-nexcoder.c +++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c @@ -21,6 +21,7 @@ #include <linux/gpio.h> #include <linux/string.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> #include <linux/io.h> @@ -37,11 +38,10 @@ //#include <asm/debug-ll.h> #include <mach/regs-gpio.h> -#include <plat/regs-serial.h> +#include <mach/gpio-samsung.h> #include <linux/platform_data/i2c-s3c2410.h> #include <plat/gpio-cfg.h> -#include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> #include <plat/samsung-time.h> @@ -134,13 +134,18 @@ static void __init nexcoder_sensorboard_init(void) static void __init nexcoder_map_io(void) { s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc)); - s3c24xx_init_clocks(0); s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); nexcoder_sensorboard_init(); } +static void __init nexcoder_init_time(void) +{ + s3c2440_init_clocks(12000000); + samsung_timer_init(); +} + static void __init nexcoder_init(void) { s3c_i2c0_set_platdata(NULL); @@ -153,6 +158,6 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440") .map_io = nexcoder_map_io, .init_machine = nexcoder_init, .init_irq = s3c2440_init_irq, - .init_time = samsung_timer_init, + .init_time = nexcoder_init_time, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c index 45e74363aaa..33afb919009 100644 --- a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c +++ b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c @@ -20,6 +20,7 @@ #include <linux/i2c/tps65010.h> #include <plat/cpu-freq.h> +#include <mach/gpio-samsung.h> #define OSIRIS_GPIO_DVS S3C2410_GPB(5) diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c index 58d6fbe5bf1..189147b80ec 100644 --- a/arch/arm/mach-s3c24xx/mach-osiris.c +++ b/arch/arm/mach-s3c24xx/mach-osiris.c @@ -18,6 +18,7 @@ #include <linux/device.h> #include <linux/syscore_ops.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/clk.h> #include <linux/i2c.h> #include <linux/io.h> @@ -39,17 +40,16 @@ #include <linux/mtd/nand_ecc.h> #include <linux/mtd/partitions.h> -#include <plat/clock.h> #include <plat/cpu.h> #include <plat/cpu-freq.h> #include <plat/devs.h> #include <plat/gpio-cfg.h> -#include <plat/regs-serial.h> #include <plat/samsung-time.h> #include <mach/hardware.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> +#include <mach/gpio-samsung.h> #include "common.h" #include "osiris.h" @@ -343,20 +343,13 @@ static struct i2c_board_info osiris_i2c_devs[] __initdata = { /* Standard Osiris devices */ static struct platform_device *osiris_devices[] __initdata = { + &s3c2410_device_dclk, &s3c_device_i2c0, &s3c_device_wdt, &s3c_device_nand, &osiris_pcmcia, }; -static struct clk *osiris_clocks[] __initdata = { - &s3c24xx_dclk0, - &s3c24xx_dclk1, - &s3c24xx_clkout0, - &s3c24xx_clkout1, - &s3c24xx_uclk, -}; - static struct s3c_cpufreq_board __initdata osiris_cpufreq = { .refresh = 7800, /* refresh period is 7.8usec */ .auto_io = 1, @@ -367,23 +360,7 @@ static void __init osiris_map_io(void) { unsigned long flags; - /* initialise the clocks */ - - s3c24xx_dclk0.parent = &clk_upll; - s3c24xx_dclk0.rate = 12*1000*1000; - - s3c24xx_dclk1.parent = &clk_upll; - s3c24xx_dclk1.rate = 24*1000*1000; - - s3c24xx_clkout0.parent = &s3c24xx_dclk0; - s3c24xx_clkout1.parent = &s3c24xx_dclk1; - - s3c24xx_uclk.parent = &s3c24xx_clkout1; - - s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks)); - s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc)); - s3c24xx_init_clocks(0); s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); @@ -407,6 +384,12 @@ static void __init osiris_map_io(void) local_irq_restore(flags); } +static void __init osiris_init_time(void) +{ + s3c2440_init_clocks(12000000); + samsung_timer_init(); +} + static void __init osiris_init(void) { register_syscore_ops(&osiris_pm_syscore_ops); @@ -428,6 +411,6 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS") .map_io = osiris_map_io, .init_irq = s3c2440_init_irq, .init_machine = osiris_init, - .init_time = samsung_timer_init, + .init_time = osiris_init_time, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c index 7e16b0740ec..45833001186 100644 --- a/arch/arm/mach-s3c24xx/mach-otom.c +++ b/arch/arm/mach-s3c24xx/mach-otom.c @@ -15,6 +15,7 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> #include <linux/io.h> @@ -29,10 +30,8 @@ #include <mach/hardware.h> #include <mach/regs-gpio.h> -#include <plat/clock.h> #include <plat/cpu.h> #include <plat/devs.h> -#include <plat/regs-serial.h> #include <plat/samsung-time.h> #include "common.h" @@ -100,11 +99,16 @@ static struct platform_device *otom11_devices[] __initdata = { static void __init otom11_map_io(void) { s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc)); - s3c24xx_init_clocks(0); s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init otom11_init_time(void) +{ + s3c2410_init_clocks(12000000); + samsung_timer_init(); +} + static void __init otom11_init(void) { s3c_i2c0_set_platdata(NULL); @@ -117,6 +121,6 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1") .map_io = otom11_map_io, .init_machine = otom11_init, .init_irq = s3c2410_init_irq, - .init_time = samsung_timer_init, + .init_time = otom11_init_time, .restart = s3c2410_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c index f8feaeadb55..228c9094519 100644 --- a/arch/arm/mach-s3c24xx/mach-qt2410.c +++ b/arch/arm/mach-s3c24xx/mach-qt2410.c @@ -31,6 +31,7 @@ #include <linux/device.h> #include <linux/platform_device.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/spi/spi.h> #include <linux/spi/spi_gpio.h> #include <linux/io.h> @@ -49,11 +50,11 @@ #include <linux/platform_data/leds-s3c24xx.h> #include <mach/regs-lcd.h> -#include <plat/regs-serial.h> #include <mach/fb.h> #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/usb-s3c2410_udc.h> #include <linux/platform_data/i2c-s3c2410.h> +#include <mach/gpio-samsung.h> #include <plat/gpio-cfg.h> #include <plat/devs.h> @@ -303,11 +304,16 @@ __setup("tft=", qt2410_tft_setup); static void __init qt2410_map_io(void) { s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc)); - s3c24xx_init_clocks(12*1000*1000); s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init qt2410_init_time(void) +{ + s3c2410_init_clocks(12000000); + samsung_timer_init(); +} + static void __init qt2410_machine_init(void) { s3c_nand_set_platdata(&qt2410_nand_info); @@ -345,6 +351,6 @@ MACHINE_START(QT2410, "QT2410") .map_io = qt2410_map_io, .init_irq = s3c2410_init_irq, .init_machine = qt2410_machine_init, - .init_time = samsung_timer_init, + .init_time = qt2410_init_time, .restart = s3c2410_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c index 44ca018e1f9..e2c6541909c 100644 --- a/arch/arm/mach-s3c24xx/mach-rx1950.c +++ b/arch/arm/mach-s3c24xx/mach-rx1950.c @@ -21,6 +21,7 @@ #include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/input.h> #include <linux/gpio_keys.h> #include <linux/device.h> @@ -51,13 +52,13 @@ #include <mach/fb.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> +#include <mach/gpio-samsung.h> -#include <plat/clock.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/pm.h> -#include <plat/regs-serial.h> #include <plat/samsung-time.h> +#include <plat/gpio-cfg.h> #include "common.h" #include "h1940.h" @@ -522,6 +523,7 @@ static struct platform_pwm_backlight_data rx1950_backlight_data = { .max_brightness = 24, .dft_brightness = 4, .pwm_period_ns = 48000, + .enable_gpio = -1, .init = rx1950_backlight_init, .notify = rx1950_backlight_notify, .exit = rx1950_backlight_exit, @@ -530,7 +532,7 @@ static struct platform_pwm_backlight_data rx1950_backlight_data = { static struct platform_device rx1950_backlight = { .name = "pwm-backlight", .dev = { - .parent = &s3c_device_timer[0].dev, + .parent = &samsung_device_pwm.dev, .platform_data = &rx1950_backlight_data, }, }; @@ -707,6 +709,7 @@ static struct i2c_board_info rx1950_i2c_devices[] = { }; static struct platform_device *rx1950_devices[] __initdata = { + &s3c2410_device_dclk, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, @@ -717,8 +720,7 @@ static struct platform_device *rx1950_devices[] __initdata = { &s3c_device_sdi, &s3c_device_adc, &s3c_device_ts, - &s3c_device_timer[0], - &s3c_device_timer[1], + &samsung_device_pwm, &rx1950_backlight, &rx1950_device_gpiokeys, &power_supply, @@ -726,20 +728,9 @@ static struct platform_device *rx1950_devices[] __initdata = { &rx1950_leds, }; -static struct clk *rx1950_clocks[] __initdata = { - &s3c24xx_clkout0, - &s3c24xx_clkout1, -}; - static void __init rx1950_map_io(void) { - s3c24xx_clkout0.parent = &clk_h; - s3c24xx_clkout1.parent = &clk_f; - - s3c24xx_register_clocks(rx1950_clocks, ARRAY_SIZE(rx1950_clocks)); - s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc)); - s3c24xx_init_clocks(16934000); s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); @@ -752,6 +743,12 @@ static void __init rx1950_map_io(void) s3c_pm_init(); } +static void __init rx1950_init_time(void) +{ + s3c2442_init_clocks(16934000); + samsung_timer_init(); +} + static void __init rx1950_init_machine(void) { int i; @@ -814,6 +811,6 @@ MACHINE_START(RX1950, "HP iPAQ RX1950") .reserve = rx1950_reserve, .init_irq = s3c2442_init_irq, .init_machine = rx1950_init_machine, - .init_time = samsung_timer_init, + .init_time = rx1950_init_time, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c index 3bc6231d0a1..6e749ec3a2e 100644 --- a/arch/arm/mach-s3c24xx/mach-rx3715.c +++ b/arch/arm/mach-s3c24xx/mach-rx3715.c @@ -23,6 +23,7 @@ #include <linux/device.h> #include <linux/platform_device.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/serial.h> #include <linux/io.h> #include <linux/mtd/mtd.h> @@ -43,12 +44,11 @@ #include <mach/hardware.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> +#include <mach/gpio-samsung.h> -#include <plat/clock.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/pm.h> -#include <plat/regs-serial.h> #include <plat/samsung-time.h> #include "common.h" @@ -178,11 +178,16 @@ static struct platform_device *rx3715_devices[] __initdata = { static void __init rx3715_map_io(void) { s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc)); - s3c24xx_init_clocks(16934000); s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init rx3715_init_time(void) +{ + s3c2440_init_clocks(16934000); + samsung_timer_init(); +} + /* H1940 and RX3715 need to reserve this for suspend */ static void __init rx3715_reserve(void) { @@ -209,6 +214,6 @@ MACHINE_START(RX3715, "IPAQ-RX3715") .reserve = rx3715_reserve, .init_irq = s3c2440_init_irq, .init_machine = rx3715_init_machine, - .init_time = samsung_timer_init, + .init_time = rx3715_init_time, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c new file mode 100644 index 00000000000..e4dcb9aa2ca --- /dev/null +++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c @@ -0,0 +1,55 @@ +/* + * Samsung's S3C2416 flattened device tree enabled machine + * + * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de> + * + * based on mach-exynos/mach-exynos4-dt.c + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/clocksource.h> +#include <linux/irqchip.h> +#include <linux/of_platform.h> +#include <linux/serial_s3c.h> + +#include <asm/mach/arch.h> +#include <mach/map.h> + +#include <plat/cpu.h> +#include <plat/pm.h> + +#include "common.h" + +static void __init s3c2416_dt_map_io(void) +{ + s3c24xx_init_io(NULL, 0); +} + +static void __init s3c2416_dt_machine_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + s3c_pm_init(); +} + +static char const *s3c2416_dt_compat[] __initdata = { + "samsung,s3c2416", + "samsung,s3c2450", + NULL +}; + +DT_MACHINE_START(S3C2416_DT, "Samsung S3C2416 (Flattened Device Tree)") + /* Maintainer: Heiko Stuebner <heiko@sntech.de> */ + .dt_compat = s3c2416_dt_compat, + .map_io = s3c2416_dt_map_io, + .init_irq = irqchip_init, + .init_machine = s3c2416_dt_machine_init, + .restart = s3c2416_restart, +MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c index a773789e4f3..419fadd6e44 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2410.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c @@ -35,6 +35,7 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> #include <linux/io.h> @@ -46,7 +47,6 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <plat/regs-serial.h> #include <linux/platform_data/i2c-s3c2410.h> #include <plat/devs.h> @@ -99,11 +99,16 @@ static struct platform_device *smdk2410_devices[] __initdata = { static void __init smdk2410_map_io(void) { s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc)); - s3c24xx_init_clocks(0); s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init smdk2410_init_time(void) +{ + s3c2410_init_clocks(12000000); + samsung_timer_init(); +} + static void __init smdk2410_init(void) { s3c_i2c0_set_platdata(NULL); @@ -118,6 +123,6 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc .map_io = smdk2410_map_io, .init_irq = s3c2410_init_irq, .init_machine = smdk2410_init, - .init_time = samsung_timer_init, + .init_time = smdk2410_init_time, .restart = s3c2410_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c index 8146e920f10..fb3b80e4459 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2413.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c @@ -19,8 +19,10 @@ #include <linux/init.h> #include <linux/gpio.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/memblock.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -33,12 +35,12 @@ #include <asm/mach-types.h> //#include <asm/debug-ll.h> -#include <plat/regs-serial.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> #include <linux/platform_data/usb-s3c2410_udc.h> #include <linux/platform_data/i2c-s3c2410.h> +#include <mach/gpio-samsung.h> #include <mach/fb.h> #include <plat/clock.h> @@ -89,26 +91,29 @@ static struct platform_device *smdk2413_devices[] __initdata = { &s3c_device_i2c0, &s3c_device_iis, &s3c_device_usbgadget, + &s3c2412_device_dma, }; -static void __init smdk2413_fixup(struct tag *tags, char **cmdline, - struct meminfo *mi) +static void __init smdk2413_fixup(struct tag *tags, char **cmdline) { if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) { - mi->nr_banks=1; - mi->bank[0].start = 0x30000000; - mi->bank[0].size = SZ_64M; + memblock_add(0x30000000, SZ_64M); } } static void __init smdk2413_map_io(void) { s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc)); - s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init smdk2413_init_time(void) +{ + s3c2412_init_clocks(12000000); + samsung_timer_init(); +} + static void __init smdk2413_machine_init(void) { /* Turn off suspend on both USB ports, and switch the * selectable USB port to USB device mode. */ @@ -157,6 +162,6 @@ MACHINE_START(SMDK2413, "SMDK2413") .init_irq = s3c2412_init_irq, .map_io = smdk2413_map_io, .init_machine = smdk2413_machine_init, - .init_time = samsung_timer_init, + .init_time = smdk2413_init_time, .restart = s3c2412_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c index cb46847c66b..fa6f30d2360 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2416.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c @@ -18,6 +18,7 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/mtd/partitions.h> @@ -34,10 +35,10 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <plat/regs-serial.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> #include <mach/regs-s3c2443-clock.h> +#include <mach/gpio-samsung.h> #include <linux/platform_data/leds-s3c24xx.h> #include <linux/platform_data/i2c-s3c2410.h> @@ -215,12 +216,18 @@ static struct platform_device *smdk2416_devices[] __initdata = { &s3c_device_hsmmc0, &s3c_device_hsmmc1, &s3c_device_usb_hsudc, + &s3c2443_device_dma, }; +static void __init smdk2416_init_time(void) +{ + s3c2416_init_clocks(12000000); + samsung_timer_init(); +} + static void __init smdk2416_map_io(void) { s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc)); - s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } @@ -255,6 +262,6 @@ MACHINE_START(SMDK2416, "SMDK2416") .init_irq = s3c2416_init_irq, .map_io = smdk2416_map_io, .init_machine = smdk2416_machine_init, - .init_time = samsung_timer_init, + .init_time = smdk2416_init_time, .restart = s3c2416_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c index de2e5d39a84..5fb89c0ae17 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2440.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c @@ -20,6 +20,7 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> #include <linux/io.h> @@ -31,14 +32,12 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <plat/regs-serial.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> #include <mach/fb.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> #include <plat/samsung-time.h> @@ -159,11 +158,16 @@ static struct platform_device *smdk2440_devices[] __initdata = { static void __init smdk2440_map_io(void) { s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc)); - s3c24xx_init_clocks(16934400); s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init smdk2440_init_time(void) +{ + s3c2440_init_clocks(16934400); + samsung_timer_init(); +} + static void __init smdk2440_machine_init(void) { s3c24xx_fb_set_platdata(&smdk2440_fb_info); @@ -180,6 +184,6 @@ MACHINE_START(S3C2440, "SMDK2440") .init_irq = s3c2440_init_irq, .map_io = smdk2440_map_io, .init_machine = smdk2440_machine_init, - .init_time = samsung_timer_init, + .init_time = smdk2440_init_time, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c index 9435c3bef18..ef5d5ea3318 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2443.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c @@ -20,6 +20,7 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> #include <linux/io.h> @@ -31,7 +32,6 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <plat/regs-serial.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> @@ -115,16 +115,22 @@ static struct platform_device *smdk2443_devices[] __initdata = { #ifdef CONFIG_SND_SOC_SMDK2443_WM9710 &s3c_device_ac97, #endif + &s3c2443_device_dma, }; static void __init smdk2443_map_io(void) { s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc)); - s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init smdk2443_init_time(void) +{ + s3c2443_init_clocks(12000000); + samsung_timer_init(); +} + static void __init smdk2443_machine_init(void) { s3c_i2c0_set_platdata(NULL); @@ -144,6 +150,6 @@ MACHINE_START(SMDK2443, "SMDK2443") .init_irq = s3c2443_init_irq, .map_io = smdk2443_map_io, .init_machine = smdk2443_machine_init, - .init_time = samsung_timer_init, + .init_time = smdk2443_init_time, .restart = s3c2443_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c index 7fad8f055ca..c616ca2d409 100644 --- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c +++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c @@ -33,6 +33,7 @@ #include <linux/device.h> #include <linux/platform_device.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/io.h> #include <asm/mach/arch.h> @@ -44,7 +45,6 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <plat/regs-serial.h> #include <linux/platform_data/i2c-s3c2410.h> #include <plat/devs.h> #include <plat/cpu.h> @@ -135,11 +135,16 @@ static struct platform_device *tct_hammer_devices[] __initdata = { static void __init tct_hammer_map_io(void) { s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc)); - s3c24xx_init_clocks(0); s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init tct_hammer_init_time(void) +{ + s3c2410_init_clocks(12000000); + samsung_timer_init(); +} + static void __init tct_hammer_init(void) { s3c_i2c0_set_platdata(NULL); @@ -151,6 +156,6 @@ MACHINE_START(TCT_HAMMER, "TCT_HAMMER") .map_io = tct_hammer_map_io, .init_irq = s3c2410_init_irq, .init_machine = tct_hammer_init, - .init_time = samsung_timer_init, + .init_time = tct_hammer_init_time, .restart = s3c2410_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c index 42e7187fed6..f88c584c300 100644 --- a/arch/arm/mach-s3c24xx/mach-vr1000.c +++ b/arch/arm/mach-s3c24xx/mach-vr1000.c @@ -25,6 +25,7 @@ #include <linux/tty.h> #include <linux/serial_8250.h> #include <linux/serial_reg.h> +#include <linux/serial_s3c.h> #include <linux/io.h> #include <asm/mach/arch.h> @@ -40,11 +41,10 @@ #include <mach/hardware.h> #include <mach/regs-gpio.h> +#include <mach/gpio-samsung.h> -#include <plat/clock.h> #include <plat/cpu.h> #include <plat/devs.h> -#include <plat/regs-serial.h> #include <plat/samsung-time.h> #include "bast.h" @@ -285,6 +285,7 @@ static struct i2c_board_info vr1000_i2c_devs[] __initdata = { /* devices for this board */ static struct platform_device *vr1000_devices[] __initdata = { + &s3c2410_device_dclk, &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, @@ -298,14 +299,6 @@ static struct platform_device *vr1000_devices[] __initdata = { &vr1000_led3, }; -static struct clk *vr1000_clocks[] __initdata = { - &s3c24xx_dclk0, - &s3c24xx_dclk1, - &s3c24xx_clkout0, - &s3c24xx_clkout1, - &s3c24xx_uclk, -}; - static void vr1000_power_off(void) { gpio_direction_output(S3C2410_GPB(9), 1); @@ -313,29 +306,19 @@ static void vr1000_power_off(void) static void __init vr1000_map_io(void) { - /* initialise clock sources */ - - s3c24xx_dclk0.parent = &clk_upll; - s3c24xx_dclk0.rate = 12*1000*1000; - - s3c24xx_dclk1.parent = NULL; - s3c24xx_dclk1.rate = 3692307; - - s3c24xx_clkout0.parent = &s3c24xx_dclk0; - s3c24xx_clkout1.parent = &s3c24xx_dclk1; - - s3c24xx_uclk.parent = &s3c24xx_clkout1; - - s3c24xx_register_clocks(vr1000_clocks, ARRAY_SIZE(vr1000_clocks)); - pm_power_off = vr1000_power_off; s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc)); - s3c24xx_init_clocks(0); s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init vr1000_init_time(void) +{ + s3c2410_init_clocks(12000000); + samsung_timer_init(); +} + static void __init vr1000_init(void) { s3c_i2c0_set_platdata(NULL); @@ -356,6 +339,6 @@ MACHINE_START(VR1000, "Thorcom-VR1000") .map_io = vr1000_map_io, .init_machine = vr1000_init, .init_irq = s3c2410_init_irq, - .init_time = samsung_timer_init, + .init_time = vr1000_init_time, .restart = s3c2410_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c index b66588428ec..9104c2be36c 100644 --- a/arch/arm/mach-s3c24xx/mach-vstms.c +++ b/arch/arm/mach-s3c24xx/mach-vstms.c @@ -16,12 +16,14 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/nand_ecc.h> #include <linux/mtd/partitions.h> +#include <linux/memblock.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -32,7 +34,6 @@ #include <asm/irq.h> #include <asm/mach-types.h> -#include <plat/regs-serial.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> @@ -126,26 +127,29 @@ static struct platform_device *vstms_devices[] __initdata = { &s3c_device_iis, &s3c_device_rtc, &s3c_device_nand, + &s3c2412_device_dma, }; -static void __init vstms_fixup(struct tag *tags, char **cmdline, - struct meminfo *mi) +static void __init vstms_fixup(struct tag *tags, char **cmdline) { if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) { - mi->nr_banks=1; - mi->bank[0].start = 0x30000000; - mi->bank[0].size = SZ_64M; + memblock_add(0x30000000, SZ_64M); } } static void __init vstms_map_io(void) { s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc)); - s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init vstms_init_time(void) +{ + s3c2412_init_clocks(12000000); + samsung_timer_init(); +} + static void __init vstms_init(void) { s3c_i2c0_set_platdata(NULL); @@ -161,6 +165,6 @@ MACHINE_START(VSTMS, "VSTMS") .init_irq = s3c2412_init_irq, .init_machine = vstms_init, .map_io = vstms_map_io, - .init_time = samsung_timer_init, + .init_time = vstms_init_time, .restart = s3c2412_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/pll-s3c2410.c b/arch/arm/mach-s3c24xx/pll-s3c2410.c index dcf3420a327..5e37d368594 100644 --- a/arch/arm/mach-s3c24xx/pll-s3c2410.c +++ b/arch/arm/mach-s3c24xx/pll-s3c2410.c @@ -33,36 +33,36 @@ #include <plat/cpu-freq-core.h> static struct cpufreq_frequency_table pll_vals_12MHz[] = { - { .frequency = 34000000, .index = PLLVAL(82, 2, 3), }, - { .frequency = 45000000, .index = PLLVAL(82, 1, 3), }, - { .frequency = 51000000, .index = PLLVAL(161, 3, 3), }, - { .frequency = 48000000, .index = PLLVAL(120, 2, 3), }, - { .frequency = 56000000, .index = PLLVAL(142, 2, 3), }, - { .frequency = 68000000, .index = PLLVAL(82, 2, 2), }, - { .frequency = 79000000, .index = PLLVAL(71, 1, 2), }, - { .frequency = 85000000, .index = PLLVAL(105, 2, 2), }, - { .frequency = 90000000, .index = PLLVAL(112, 2, 2), }, - { .frequency = 101000000, .index = PLLVAL(127, 2, 2), }, - { .frequency = 113000000, .index = PLLVAL(105, 1, 2), }, - { .frequency = 118000000, .index = PLLVAL(150, 2, 2), }, - { .frequency = 124000000, .index = PLLVAL(116, 1, 2), }, - { .frequency = 135000000, .index = PLLVAL(82, 2, 1), }, - { .frequency = 147000000, .index = PLLVAL(90, 2, 1), }, - { .frequency = 152000000, .index = PLLVAL(68, 1, 1), }, - { .frequency = 158000000, .index = PLLVAL(71, 1, 1), }, - { .frequency = 170000000, .index = PLLVAL(77, 1, 1), }, - { .frequency = 180000000, .index = PLLVAL(82, 1, 1), }, - { .frequency = 186000000, .index = PLLVAL(85, 1, 1), }, - { .frequency = 192000000, .index = PLLVAL(88, 1, 1), }, - { .frequency = 203000000, .index = PLLVAL(161, 3, 1), }, + { .frequency = 34000000, .driver_data = PLLVAL(82, 2, 3), }, + { .frequency = 45000000, .driver_data = PLLVAL(82, 1, 3), }, + { .frequency = 51000000, .driver_data = PLLVAL(161, 3, 3), }, + { .frequency = 48000000, .driver_data = PLLVAL(120, 2, 3), }, + { .frequency = 56000000, .driver_data = PLLVAL(142, 2, 3), }, + { .frequency = 68000000, .driver_data = PLLVAL(82, 2, 2), }, + { .frequency = 79000000, .driver_data = PLLVAL(71, 1, 2), }, + { .frequency = 85000000, .driver_data = PLLVAL(105, 2, 2), }, + { .frequency = 90000000, .driver_data = PLLVAL(112, 2, 2), }, + { .frequency = 101000000, .driver_data = PLLVAL(127, 2, 2), }, + { .frequency = 113000000, .driver_data = PLLVAL(105, 1, 2), }, + { .frequency = 118000000, .driver_data = PLLVAL(150, 2, 2), }, + { .frequency = 124000000, .driver_data = PLLVAL(116, 1, 2), }, + { .frequency = 135000000, .driver_data = PLLVAL(82, 2, 1), }, + { .frequency = 147000000, .driver_data = PLLVAL(90, 2, 1), }, + { .frequency = 152000000, .driver_data = PLLVAL(68, 1, 1), }, + { .frequency = 158000000, .driver_data = PLLVAL(71, 1, 1), }, + { .frequency = 170000000, .driver_data = PLLVAL(77, 1, 1), }, + { .frequency = 180000000, .driver_data = PLLVAL(82, 1, 1), }, + { .frequency = 186000000, .driver_data = PLLVAL(85, 1, 1), }, + { .frequency = 192000000, .driver_data = PLLVAL(88, 1, 1), }, + { .frequency = 203000000, .driver_data = PLLVAL(161, 3, 1), }, /* 2410A extras */ - { .frequency = 210000000, .index = PLLVAL(132, 2, 1), }, - { .frequency = 226000000, .index = PLLVAL(105, 1, 1), }, - { .frequency = 266000000, .index = PLLVAL(125, 1, 1), }, - { .frequency = 268000000, .index = PLLVAL(126, 1, 1), }, - { .frequency = 270000000, .index = PLLVAL(127, 1, 1), }, + { .frequency = 210000000, .driver_data = PLLVAL(132, 2, 1), }, + { .frequency = 226000000, .driver_data = PLLVAL(105, 1, 1), }, + { .frequency = 266000000, .driver_data = PLLVAL(125, 1, 1), }, + { .frequency = 268000000, .driver_data = PLLVAL(126, 1, 1), }, + { .frequency = 270000000, .driver_data = PLLVAL(127, 1, 1), }, }; static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif) diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c index 67378175831..a19460e6e7b 100644 --- a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c +++ b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c @@ -21,33 +21,33 @@ #include <plat/cpu-freq-core.h> static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = { - { .frequency = 75000000, .index = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */ - { .frequency = 80000000, .index = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */ - { .frequency = 90000000, .index = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */ - { .frequency = 100000000, .index = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */ - { .frequency = 110000000, .index = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */ - { .frequency = 120000000, .index = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */ - { .frequency = 150000000, .index = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */ - { .frequency = 160000000, .index = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */ - { .frequency = 170000000, .index = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */ - { .frequency = 180000000, .index = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */ - { .frequency = 190000000, .index = PLLVAL(0x57, 1, 2), }, /* FVco 760.000000 */ - { .frequency = 200000000, .index = PLLVAL(0x5c, 1, 2), }, /* FVco 800.000000 */ - { .frequency = 210000000, .index = PLLVAL(0x84, 2, 2), }, /* FVco 840.000000 */ - { .frequency = 220000000, .index = PLLVAL(0x66, 1, 2), }, /* FVco 880.000000 */ - { .frequency = 230000000, .index = PLLVAL(0x6b, 1, 2), }, /* FVco 920.000000 */ - { .frequency = 240000000, .index = PLLVAL(0x70, 1, 2), }, /* FVco 960.000000 */ - { .frequency = 300000000, .index = PLLVAL(0x75, 3, 1), }, /* FVco 600.000000 */ - { .frequency = 310000000, .index = PLLVAL(0x93, 4, 1), }, /* FVco 620.000000 */ - { .frequency = 320000000, .index = PLLVAL(0x98, 4, 1), }, /* FVco 640.000000 */ - { .frequency = 330000000, .index = PLLVAL(0x66, 2, 1), }, /* FVco 660.000000 */ - { .frequency = 340000000, .index = PLLVAL(0x4d, 1, 1), }, /* FVco 680.000000 */ - { .frequency = 350000000, .index = PLLVAL(0xa7, 4, 1), }, /* FVco 700.000000 */ - { .frequency = 360000000, .index = PLLVAL(0x70, 2, 1), }, /* FVco 720.000000 */ - { .frequency = 370000000, .index = PLLVAL(0xb1, 4, 1), }, /* FVco 740.000000 */ - { .frequency = 380000000, .index = PLLVAL(0x57, 1, 1), }, /* FVco 760.000000 */ - { .frequency = 390000000, .index = PLLVAL(0x7a, 2, 1), }, /* FVco 780.000000 */ - { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ + { .frequency = 75000000, .driver_data = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */ + { .frequency = 80000000, .driver_data = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */ + { .frequency = 90000000, .driver_data = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */ + { .frequency = 100000000, .driver_data = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */ + { .frequency = 110000000, .driver_data = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */ + { .frequency = 120000000, .driver_data = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */ + { .frequency = 150000000, .driver_data = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */ + { .frequency = 160000000, .driver_data = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */ + { .frequency = 170000000, .driver_data = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */ + { .frequency = 180000000, .driver_data = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */ + { .frequency = 190000000, .driver_data = PLLVAL(0x57, 1, 2), }, /* FVco 760.000000 */ + { .frequency = 200000000, .driver_data = PLLVAL(0x5c, 1, 2), }, /* FVco 800.000000 */ + { .frequency = 210000000, .driver_data = PLLVAL(0x84, 2, 2), }, /* FVco 840.000000 */ + { .frequency = 220000000, .driver_data = PLLVAL(0x66, 1, 2), }, /* FVco 880.000000 */ + { .frequency = 230000000, .driver_data = PLLVAL(0x6b, 1, 2), }, /* FVco 920.000000 */ + { .frequency = 240000000, .driver_data = PLLVAL(0x70, 1, 2), }, /* FVco 960.000000 */ + { .frequency = 300000000, .driver_data = PLLVAL(0x75, 3, 1), }, /* FVco 600.000000 */ + { .frequency = 310000000, .driver_data = PLLVAL(0x93, 4, 1), }, /* FVco 620.000000 */ + { .frequency = 320000000, .driver_data = PLLVAL(0x98, 4, 1), }, /* FVco 640.000000 */ + { .frequency = 330000000, .driver_data = PLLVAL(0x66, 2, 1), }, /* FVco 660.000000 */ + { .frequency = 340000000, .driver_data = PLLVAL(0x4d, 1, 1), }, /* FVco 680.000000 */ + { .frequency = 350000000, .driver_data = PLLVAL(0xa7, 4, 1), }, /* FVco 700.000000 */ + { .frequency = 360000000, .driver_data = PLLVAL(0x70, 2, 1), }, /* FVco 720.000000 */ + { .frequency = 370000000, .driver_data = PLLVAL(0xb1, 4, 1), }, /* FVco 740.000000 */ + { .frequency = 380000000, .driver_data = PLLVAL(0x57, 1, 1), }, /* FVco 760.000000 */ + { .frequency = 390000000, .driver_data = PLLVAL(0x7a, 2, 1), }, /* FVco 780.000000 */ + { .frequency = 400000000, .driver_data = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ }; static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif) diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c index debfa106289..1191b290562 100644 --- a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c +++ b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c @@ -21,61 +21,61 @@ #include <plat/cpu-freq-core.h> static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = { - { .frequency = 78019200, .index = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */ - { .frequency = 84067200, .index = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */ - { .frequency = 90115200, .index = PLLVAL(141, 5, 3), }, /* FVco 720.921600 */ - { .frequency = 96163200, .index = PLLVAL(151, 5, 3), }, /* FVco 769.305600 */ - { .frequency = 102135600, .index = PLLVAL(185, 6, 3), }, /* FVco 817.084800 */ - { .frequency = 108259200, .index = PLLVAL(171, 5, 3), }, /* FVco 866.073600 */ - { .frequency = 114307200, .index = PLLVAL(127, 3, 3), }, /* FVco 914.457600 */ - { .frequency = 120234240, .index = PLLVAL(134, 3, 3), }, /* FVco 961.873920 */ - { .frequency = 126161280, .index = PLLVAL(141, 3, 3), }, /* FVco 1009.290240 */ - { .frequency = 132088320, .index = PLLVAL(148, 3, 3), }, /* FVco 1056.706560 */ - { .frequency = 138015360, .index = PLLVAL(155, 3, 3), }, /* FVco 1104.122880 */ - { .frequency = 144789120, .index = PLLVAL(163, 3, 3), }, /* FVco 1158.312960 */ - { .frequency = 150100363, .index = PLLVAL(187, 9, 2), }, /* FVco 600.401454 */ - { .frequency = 156038400, .index = PLLVAL(121, 5, 2), }, /* FVco 624.153600 */ - { .frequency = 162086400, .index = PLLVAL(126, 5, 2), }, /* FVco 648.345600 */ - { .frequency = 168134400, .index = PLLVAL(131, 5, 2), }, /* FVco 672.537600 */ - { .frequency = 174048000, .index = PLLVAL(177, 7, 2), }, /* FVco 696.192000 */ - { .frequency = 180230400, .index = PLLVAL(141, 5, 2), }, /* FVco 720.921600 */ - { .frequency = 186278400, .index = PLLVAL(124, 4, 2), }, /* FVco 745.113600 */ - { .frequency = 192326400, .index = PLLVAL(151, 5, 2), }, /* FVco 769.305600 */ - { .frequency = 198132480, .index = PLLVAL(109, 3, 2), }, /* FVco 792.529920 */ - { .frequency = 204271200, .index = PLLVAL(185, 6, 2), }, /* FVco 817.084800 */ - { .frequency = 210268800, .index = PLLVAL(141, 4, 2), }, /* FVco 841.075200 */ - { .frequency = 216518400, .index = PLLVAL(171, 5, 2), }, /* FVco 866.073600 */ - { .frequency = 222264000, .index = PLLVAL(97, 2, 2), }, /* FVco 889.056000 */ - { .frequency = 228614400, .index = PLLVAL(127, 3, 2), }, /* FVco 914.457600 */ - { .frequency = 234259200, .index = PLLVAL(158, 4, 2), }, /* FVco 937.036800 */ - { .frequency = 240468480, .index = PLLVAL(134, 3, 2), }, /* FVco 961.873920 */ - { .frequency = 246960000, .index = PLLVAL(167, 4, 2), }, /* FVco 987.840000 */ - { .frequency = 252322560, .index = PLLVAL(141, 3, 2), }, /* FVco 1009.290240 */ - { .frequency = 258249600, .index = PLLVAL(114, 2, 2), }, /* FVco 1032.998400 */ - { .frequency = 264176640, .index = PLLVAL(148, 3, 2), }, /* FVco 1056.706560 */ - { .frequency = 270950400, .index = PLLVAL(120, 2, 2), }, /* FVco 1083.801600 */ - { .frequency = 276030720, .index = PLLVAL(155, 3, 2), }, /* FVco 1104.122880 */ - { .frequency = 282240000, .index = PLLVAL(92, 1, 2), }, /* FVco 1128.960000 */ - { .frequency = 289578240, .index = PLLVAL(163, 3, 2), }, /* FVco 1158.312960 */ - { .frequency = 294235200, .index = PLLVAL(131, 2, 2), }, /* FVco 1176.940800 */ - { .frequency = 300200727, .index = PLLVAL(187, 9, 1), }, /* FVco 600.401454 */ - { .frequency = 306358690, .index = PLLVAL(191, 9, 1), }, /* FVco 612.717380 */ - { .frequency = 312076800, .index = PLLVAL(121, 5, 1), }, /* FVco 624.153600 */ - { .frequency = 318366720, .index = PLLVAL(86, 3, 1), }, /* FVco 636.733440 */ - { .frequency = 324172800, .index = PLLVAL(126, 5, 1), }, /* FVco 648.345600 */ - { .frequency = 330220800, .index = PLLVAL(109, 4, 1), }, /* FVco 660.441600 */ - { .frequency = 336268800, .index = PLLVAL(131, 5, 1), }, /* FVco 672.537600 */ - { .frequency = 342074880, .index = PLLVAL(93, 3, 1), }, /* FVco 684.149760 */ - { .frequency = 348096000, .index = PLLVAL(177, 7, 1), }, /* FVco 696.192000 */ - { .frequency = 355622400, .index = PLLVAL(118, 4, 1), }, /* FVco 711.244800 */ - { .frequency = 360460800, .index = PLLVAL(141, 5, 1), }, /* FVco 720.921600 */ - { .frequency = 366206400, .index = PLLVAL(165, 6, 1), }, /* FVco 732.412800 */ - { .frequency = 372556800, .index = PLLVAL(124, 4, 1), }, /* FVco 745.113600 */ - { .frequency = 378201600, .index = PLLVAL(126, 4, 1), }, /* FVco 756.403200 */ - { .frequency = 384652800, .index = PLLVAL(151, 5, 1), }, /* FVco 769.305600 */ - { .frequency = 391608000, .index = PLLVAL(177, 6, 1), }, /* FVco 783.216000 */ - { .frequency = 396264960, .index = PLLVAL(109, 3, 1), }, /* FVco 792.529920 */ - { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */ + { .frequency = 78019200, .driver_data = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */ + { .frequency = 84067200, .driver_data = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */ + { .frequency = 90115200, .driver_data = PLLVAL(141, 5, 3), }, /* FVco 720.921600 */ + { .frequency = 96163200, .driver_data = PLLVAL(151, 5, 3), }, /* FVco 769.305600 */ + { .frequency = 102135600, .driver_data = PLLVAL(185, 6, 3), }, /* FVco 817.084800 */ + { .frequency = 108259200, .driver_data = PLLVAL(171, 5, 3), }, /* FVco 866.073600 */ + { .frequency = 114307200, .driver_data = PLLVAL(127, 3, 3), }, /* FVco 914.457600 */ + { .frequency = 120234240, .driver_data = PLLVAL(134, 3, 3), }, /* FVco 961.873920 */ + { .frequency = 126161280, .driver_data = PLLVAL(141, 3, 3), }, /* FVco 1009.290240 */ + { .frequency = 132088320, .driver_data = PLLVAL(148, 3, 3), }, /* FVco 1056.706560 */ + { .frequency = 138015360, .driver_data = PLLVAL(155, 3, 3), }, /* FVco 1104.122880 */ + { .frequency = 144789120, .driver_data = PLLVAL(163, 3, 3), }, /* FVco 1158.312960 */ + { .frequency = 150100363, .driver_data = PLLVAL(187, 9, 2), }, /* FVco 600.401454 */ + { .frequency = 156038400, .driver_data = PLLVAL(121, 5, 2), }, /* FVco 624.153600 */ + { .frequency = 162086400, .driver_data = PLLVAL(126, 5, 2), }, /* FVco 648.345600 */ + { .frequency = 168134400, .driver_data = PLLVAL(131, 5, 2), }, /* FVco 672.537600 */ + { .frequency = 174048000, .driver_data = PLLVAL(177, 7, 2), }, /* FVco 696.192000 */ + { .frequency = 180230400, .driver_data = PLLVAL(141, 5, 2), }, /* FVco 720.921600 */ + { .frequency = 186278400, .driver_data = PLLVAL(124, 4, 2), }, /* FVco 745.113600 */ + { .frequency = 192326400, .driver_data = PLLVAL(151, 5, 2), }, /* FVco 769.305600 */ + { .frequency = 198132480, .driver_data = PLLVAL(109, 3, 2), }, /* FVco 792.529920 */ + { .frequency = 204271200, .driver_data = PLLVAL(185, 6, 2), }, /* FVco 817.084800 */ + { .frequency = 210268800, .driver_data = PLLVAL(141, 4, 2), }, /* FVco 841.075200 */ + { .frequency = 216518400, .driver_data = PLLVAL(171, 5, 2), }, /* FVco 866.073600 */ + { .frequency = 222264000, .driver_data = PLLVAL(97, 2, 2), }, /* FVco 889.056000 */ + { .frequency = 228614400, .driver_data = PLLVAL(127, 3, 2), }, /* FVco 914.457600 */ + { .frequency = 234259200, .driver_data = PLLVAL(158, 4, 2), }, /* FVco 937.036800 */ + { .frequency = 240468480, .driver_data = PLLVAL(134, 3, 2), }, /* FVco 961.873920 */ + { .frequency = 246960000, .driver_data = PLLVAL(167, 4, 2), }, /* FVco 987.840000 */ + { .frequency = 252322560, .driver_data = PLLVAL(141, 3, 2), }, /* FVco 1009.290240 */ + { .frequency = 258249600, .driver_data = PLLVAL(114, 2, 2), }, /* FVco 1032.998400 */ + { .frequency = 264176640, .driver_data = PLLVAL(148, 3, 2), }, /* FVco 1056.706560 */ + { .frequency = 270950400, .driver_data = PLLVAL(120, 2, 2), }, /* FVco 1083.801600 */ + { .frequency = 276030720, .driver_data = PLLVAL(155, 3, 2), }, /* FVco 1104.122880 */ + { .frequency = 282240000, .driver_data = PLLVAL(92, 1, 2), }, /* FVco 1128.960000 */ + { .frequency = 289578240, .driver_data = PLLVAL(163, 3, 2), }, /* FVco 1158.312960 */ + { .frequency = 294235200, .driver_data = PLLVAL(131, 2, 2), }, /* FVco 1176.940800 */ + { .frequency = 300200727, .driver_data = PLLVAL(187, 9, 1), }, /* FVco 600.401454 */ + { .frequency = 306358690, .driver_data = PLLVAL(191, 9, 1), }, /* FVco 612.717380 */ + { .frequency = 312076800, .driver_data = PLLVAL(121, 5, 1), }, /* FVco 624.153600 */ + { .frequency = 318366720, .driver_data = PLLVAL(86, 3, 1), }, /* FVco 636.733440 */ + { .frequency = 324172800, .driver_data = PLLVAL(126, 5, 1), }, /* FVco 648.345600 */ + { .frequency = 330220800, .driver_data = PLLVAL(109, 4, 1), }, /* FVco 660.441600 */ + { .frequency = 336268800, .driver_data = PLLVAL(131, 5, 1), }, /* FVco 672.537600 */ + { .frequency = 342074880, .driver_data = PLLVAL(93, 3, 1), }, /* FVco 684.149760 */ + { .frequency = 348096000, .driver_data = PLLVAL(177, 7, 1), }, /* FVco 696.192000 */ + { .frequency = 355622400, .driver_data = PLLVAL(118, 4, 1), }, /* FVco 711.244800 */ + { .frequency = 360460800, .driver_data = PLLVAL(141, 5, 1), }, /* FVco 720.921600 */ + { .frequency = 366206400, .driver_data = PLLVAL(165, 6, 1), }, /* FVco 732.412800 */ + { .frequency = 372556800, .driver_data = PLLVAL(124, 4, 1), }, /* FVco 745.113600 */ + { .frequency = 378201600, .driver_data = PLLVAL(126, 4, 1), }, /* FVco 756.403200 */ + { .frequency = 384652800, .driver_data = PLLVAL(151, 5, 1), }, /* FVco 769.305600 */ + { .frequency = 391608000, .driver_data = PLLVAL(177, 6, 1), }, /* FVco 783.216000 */ + { .frequency = 396264960, .driver_data = PLLVAL(109, 3, 1), }, /* FVco 792.529920 */ + { .frequency = 402192000, .driver_data = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */ }; static int s3c2440_plls169344_add(struct device *dev, diff --git a/arch/arm/mach-s3c24xx/pm-s3c2410.c b/arch/arm/mach-s3c24xx/pm-s3c2410.c index 2d82c4f116c..20e481d8a33 100644 --- a/arch/arm/mach-s3c24xx/pm-s3c2410.c +++ b/arch/arm/mach-s3c24xx/pm-s3c2410.c @@ -33,7 +33,9 @@ #include <mach/hardware.h> #include <mach/regs-gpio.h> +#include <mach/gpio-samsung.h> +#include <plat/gpio-cfg.h> #include <plat/cpu.h> #include <plat/pm.h> diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c24xx/pm.c index caa5b721138..b19256ec8d4 100644 --- a/arch/arm/mach-s3c24xx/pm.c +++ b/arch/arm/mach-s3c24xx/pm.c @@ -33,12 +33,13 @@ #include <linux/gpio.h> #include <linux/interrupt.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/io.h> -#include <plat/regs-serial.h> #include <mach/regs-clock.h> #include <mach/regs-gpio.h> #include <mach/regs-irq.h> +#include <mach/gpio-samsung.h> #include <asm/mach/time.h> @@ -50,9 +51,6 @@ #define PFX "s3c24xx-pm: " static struct sleep_save core_save[] = { - SAVE_ITEM(S3C2410_LOCKTIME), - SAVE_ITEM(S3C2410_CLKCON), - /* we restore the timings here, with the proviso that the board * brings the system up in an slower, or equal frequency setting * to the original system. @@ -68,18 +66,6 @@ static struct sleep_save core_save[] = { SAVE_ITEM(S3C2410_BANKCON3), SAVE_ITEM(S3C2410_BANKCON4), SAVE_ITEM(S3C2410_BANKCON5), - -#ifndef CONFIG_CPU_FREQ - SAVE_ITEM(S3C2410_CLKDIVN), - SAVE_ITEM(S3C2410_MPLLCON), - SAVE_ITEM(S3C2410_REFRESH), -#endif - SAVE_ITEM(S3C2410_UPLLCON), - SAVE_ITEM(S3C2410_CLKSLOW), -}; - -static struct sleep_save misc_save[] = { - SAVE_ITEM(S3C2410_DCLKCON), }; /* s3c_pm_check_resume_pin @@ -139,12 +125,10 @@ void s3c_pm_configure_extint(void) void s3c_pm_restore_core(void) { s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); - s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); } void s3c_pm_save_core(void) { - s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); } diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c index d850ea5adac..7eab8882988 100644 --- a/arch/arm/mach-s3c24xx/s3c2410.c +++ b/arch/arm/mach-s3c24xx/s3c2410.c @@ -21,7 +21,9 @@ #include <linux/device.h> #include <linux/syscore_ops.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> +#include <linux/reboot.h> #include <linux/io.h> #include <asm/mach/arch.h> @@ -29,13 +31,13 @@ #include <asm/mach/irq.h> #include <mach/hardware.h> +#include <mach/gpio-samsung.h> #include <asm/irq.h> #include <asm/system_misc.h> #include <plat/cpu-freq.h> #include <mach/regs-clock.h> -#include <plat/regs-serial.h> #include <plat/cpu.h> #include <plat/devs.h> @@ -83,61 +85,6 @@ void __init s3c2410_map_io(void) void __init_or_cpufreq s3c2410_setup_clocks(void) { - struct clk *xtal_clk; - unsigned long tmp; - unsigned long xtal; - unsigned long fclk; - unsigned long hclk; - unsigned long pclk; - - xtal_clk = clk_get(NULL, "xtal"); - xtal = clk_get_rate(xtal_clk); - clk_put(xtal_clk); - - /* now we've got our machine bits initialised, work out what - * clocks we've got */ - - fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal); - - tmp = __raw_readl(S3C2410_CLKDIVN); - - /* work out clock scalings */ - - hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1); - pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1); - - /* print brieft summary of clocks, etc */ - - printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", - print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); - - /* initialise the clocks here, to allow other things like the - * console to use them - */ - - s3c24xx_setup_clocks(fclk, hclk, pclk); -} - -/* fake ARMCLK for use with cpufreq, etc. */ - -static struct clk s3c2410_armclk = { - .name = "armclk", - .parent = &clk_f, - .id = -1, -}; - -static struct clk_lookup s3c2410_clk_lookup[] = { - CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p), - CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), -}; - -void __init s3c2410_init_clocks(int xtal) -{ - s3c24xx_register_baseclocks(xtal); - s3c2410_setup_clocks(); - s3c2410_baseclk_add(); - s3c24xx_register_clock(&s3c2410_armclk); - clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup)); } struct bus_type s3c2410_subsys = { @@ -195,13 +142,13 @@ int __init s3c2410a_init(void) return s3c2410_init(); } -void s3c2410_restart(char mode, const char *cmd) +void s3c2410_restart(enum reboot_mode mode, const char *cmd) { - if (mode == 's') { + if (mode == REBOOT_SOFT) { soft_restart(0); } - arch_wdt_reset(); + samsung_wdt_reset(); /* we'll take a jump through zero as a poor second */ soft_restart(0); diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c index 0f864d4c97d..d49f52fbc84 100644 --- a/arch/arm/mach-s3c24xx/s3c2412.c +++ b/arch/arm/mach-s3c24xx/s3c2412.c @@ -20,8 +20,10 @@ #include <linux/device.h> #include <linux/syscore_ops.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/reboot.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -42,7 +44,6 @@ #include <plat/nand-core.h> #include <plat/pll.h> #include <plat/pm.h> -#include <plat/regs-serial.h> #include <plat/regs-spi.h> #include "common.h" @@ -129,9 +130,9 @@ static void s3c2412_idle(void) cpu_do_idle(); } -void s3c2412_restart(char mode, const char *cmd) +void s3c2412_restart(enum reboot_mode mode, const char *cmd) { - if (mode == 's') + if (mode == REBOOT_SOFT) soft_restart(0); /* errata "Watch-dog/Software Reset Problem" specifies that @@ -172,49 +173,6 @@ void __init s3c2412_map_io(void) void __init_or_cpufreq s3c2412_setup_clocks(void) { - struct clk *xtal_clk; - unsigned long tmp; - unsigned long xtal; - unsigned long fclk; - unsigned long hclk; - unsigned long pclk; - - xtal_clk = clk_get(NULL, "xtal"); - xtal = clk_get_rate(xtal_clk); - clk_put(xtal_clk); - - /* now we've got our machine bits initialised, work out what - * clocks we've got */ - - fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2); - - clk_mpll.rate = fclk; - - tmp = __raw_readl(S3C2410_CLKDIVN); - - /* work out clock scalings */ - - hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1); - hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1); - pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1); - - /* print brieft summary of clocks, etc */ - - printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", - print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); - - s3c24xx_setup_clocks(fclk, hclk, pclk); -} - -void __init s3c2412_init_clocks(int xtal) -{ - /* initialise the clocks here, to allow other things like the - * console to use them - */ - - s3c24xx_register_baseclocks(xtal); - s3c2412_setup_clocks(); - s3c2412_baseclk_add(); } /* need to register the subsystem before we actually register the device, and diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c index b9c5d382daf..9fe260ae11e 100644 --- a/arch/arm/mach-s3c24xx/s3c2416.c +++ b/arch/arm/mach-s3c24xx/s3c2416.c @@ -35,17 +35,20 @@ #include <linux/syscore_ops.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/reboot.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> #include <mach/hardware.h> +#include <mach/gpio-samsung.h> #include <asm/proc-fns.h> #include <asm/irq.h> #include <asm/system_misc.h> #include <mach/regs-s3c2443-clock.h> +#include <mach/rtc-core.h> #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> @@ -59,7 +62,6 @@ #include <plat/fb-core.h> #include <plat/nand-core.h> #include <plat/adc-core.h> -#include <plat/rtc-core.h> #include <plat/spi-core.h> #include "common.h" @@ -79,9 +81,9 @@ static struct device s3c2416_dev = { .bus = &s3c2416_subsys, }; -void s3c2416_restart(char mode, const char *cmd) +void s3c2416_restart(enum reboot_mode mode, const char *cmd) { - if (mode == 's') + if (mode == REBOOT_SOFT) soft_restart(0); __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST); diff --git a/arch/arm/mach-s3c24xx/s3c2440.c b/arch/arm/mach-s3c24xx/s3c2440.c index 5f9d6569475..03d379f1fc5 100644 --- a/arch/arm/mach-s3c24xx/s3c2440.c +++ b/arch/arm/mach-s3c24xx/s3c2440.c @@ -29,6 +29,7 @@ #include <asm/mach/irq.h> #include <mach/hardware.h> +#include <mach/gpio-samsung.h> #include <asm/irq.h> #include <plat/devs.h> diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c index 6819961f6b1..fb9da2b603a 100644 --- a/arch/arm/mach-s3c24xx/s3c2442.c +++ b/arch/arm/mach-s3c24xx/s3c2442.c @@ -37,6 +37,7 @@ #include <linux/io.h> #include <mach/hardware.h> +#include <mach/gpio-samsung.h> #include <linux/atomic.h> #include <asm/irq.h> @@ -52,117 +53,6 @@ #include "common.h" -/* S3C2442 extended clock support */ - -static unsigned long s3c2442_camif_upll_round(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - int div; - - if (rate > parent_rate) - return parent_rate; - - div = parent_rate / rate; - - if (div == 3) - return parent_rate / 3; - - /* note, we remove the +/- 1 calculations for the divisor */ - - div /= 2; - - if (div < 1) - div = 1; - else if (div > 16) - div = 16; - - return parent_rate / (div * 2); -} - -static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); - - rate = s3c2442_camif_upll_round(clk, rate); - - camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3; - - if (rate == parent_rate) { - camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL; - } else if ((parent_rate / rate) == 3) { - camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; - camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3; - } else { - camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK; - camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; - camdivn |= (((parent_rate / rate) / 2) - 1); - } - - __raw_writel(camdivn, S3C2440_CAMDIVN); - - return 0; -} - -/* Extra S3C2442 clocks */ - -static struct clk s3c2442_clk_cam = { - .name = "camif", - .id = -1, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2440_CLKCON_CAMERA, -}; - -static struct clk s3c2442_clk_cam_upll = { - .name = "camif-upll", - .id = -1, - .ops = &(struct clk_ops) { - .set_rate = s3c2442_camif_upll_setrate, - .round_rate = s3c2442_camif_upll_round, - }, -}; - -static int s3c2442_clk_add(struct device *dev, struct subsys_interface *sif) -{ - struct clk *clock_upll; - struct clk *clock_h; - struct clk *clock_p; - - clock_p = clk_get(NULL, "pclk"); - clock_h = clk_get(NULL, "hclk"); - clock_upll = clk_get(NULL, "upll"); - - if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) { - printk(KERN_ERR "S3C2442: Failed to get parent clocks\n"); - return -EINVAL; - } - - s3c2442_clk_cam.parent = clock_h; - s3c2442_clk_cam_upll.parent = clock_upll; - - s3c24xx_register_clock(&s3c2442_clk_cam); - s3c24xx_register_clock(&s3c2442_clk_cam_upll); - - clk_disable(&s3c2442_clk_cam); - - return 0; -} - -static struct subsys_interface s3c2442_clk_interface = { - .name = "s3c2442_clk", - .subsys = &s3c2442_subsys, - .add_dev = s3c2442_clk_add, -}; - -static __init int s3c2442_clk_init(void) -{ - return subsys_interface_register(&s3c2442_clk_interface); -} - -arch_initcall(s3c2442_clk_init); - - static struct device s3c2442_dev = { .bus = &s3c2442_subsys, }; diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c index 8328cd65bf3..c7a804d0348 100644 --- a/arch/arm/mach-s3c24xx/s3c2443.c +++ b/arch/arm/mach-s3c24xx/s3c2443.c @@ -22,16 +22,19 @@ #include <linux/device.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/reboot.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> #include <mach/hardware.h> +#include <mach/gpio-samsung.h> #include <asm/irq.h> #include <asm/system_misc.h> #include <mach/regs-s3c2443-clock.h> +#include <mach/rtc-core.h> #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> @@ -41,7 +44,6 @@ #include <plat/fb-core.h> #include <plat/nand-core.h> #include <plat/adc-core.h> -#include <plat/rtc-core.h> #include <plat/spi-core.h> static struct map_desc s3c2443_iodesc[] __initdata = { @@ -59,9 +61,9 @@ static struct device s3c2443_dev = { .bus = &s3c2443_subsys, }; -void s3c2443_restart(char mode, const char *cmd) +void s3c2443_restart(enum reboot_mode mode, const char *cmd) { - if (mode == 's') + if (mode == REBOOT_SOFT) soft_restart(0); __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST); diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c index 2a35edb6735..4a64bcc9eb5 100644 --- a/arch/arm/mach-s3c24xx/s3c244x.c +++ b/arch/arm/mach-s3c24xx/s3c244x.c @@ -17,7 +17,9 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/serial_core.h> +#include <linux/serial_s3c.h> #include <linux/platform_device.h> +#include <linux/reboot.h> #include <linux/device.h> #include <linux/syscore_ops.h> #include <linux/clk.h> @@ -34,7 +36,6 @@ #include <plat/cpu-freq.h> #include <mach/regs-clock.h> -#include <plat/regs-serial.h> #include <mach/regs-gpio.h> #include <plat/clock.h> @@ -45,6 +46,7 @@ #include <plat/nand-core.h> #include <plat/watchdog-reset.h> +#include "common.h" #include "regs-dsc.h" static struct map_desc s3c244x_iodesc[] __initdata = { @@ -73,66 +75,11 @@ void __init s3c244x_map_io(void) s3c_nand_setname("s3c2440-nand"); s3c_device_ts.name = "s3c2440-ts"; s3c_device_usbgadget.name = "s3c2440-usbgadget"; + s3c2410_device_dclk.name = "s3c2440-dclk"; } void __init_or_cpufreq s3c244x_setup_clocks(void) { - struct clk *xtal_clk; - unsigned long clkdiv; - unsigned long camdiv; - unsigned long xtal; - unsigned long hclk, fclk, pclk; - int hdiv = 1; - - xtal_clk = clk_get(NULL, "xtal"); - xtal = clk_get_rate(xtal_clk); - clk_put(xtal_clk); - - fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; - - clkdiv = __raw_readl(S3C2410_CLKDIVN); - camdiv = __raw_readl(S3C2440_CAMDIVN); - - /* work out clock scalings */ - - switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) { - case S3C2440_CLKDIVN_HDIVN_1: - hdiv = 1; - break; - - case S3C2440_CLKDIVN_HDIVN_2: - hdiv = 2; - break; - - case S3C2440_CLKDIVN_HDIVN_4_8: - hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4; - break; - - case S3C2440_CLKDIVN_HDIVN_3_6: - hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3; - break; - } - - hclk = fclk / hdiv; - pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1); - - /* print brief summary of clocks, etc */ - - printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", - print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); - - s3c24xx_setup_clocks(fclk, hclk, pclk); -} - -void __init s3c244x_init_clocks(int xtal) -{ - /* initialise the clocks here, to allow other things like the - * console to use them, and to add new ones after the initialisation - */ - - s3c24xx_register_baseclocks(xtal); - s3c244x_setup_clocks(); - s3c2410_baseclk_add(); } /* Since the S3C2442 and S3C2440 share items, put both subsystems here */ @@ -197,12 +144,12 @@ struct syscore_ops s3c244x_pm_syscore_ops = { .resume = s3c244x_resume, }; -void s3c244x_restart(char mode, const char *cmd) +void s3c244x_restart(enum reboot_mode mode, const char *cmd) { - if (mode == 's') + if (mode == REBOOT_SOFT) soft_restart(0); - arch_wdt_reset(); + samsung_wdt_reset(); /* we'll take a jump through zero as a poor second */ soft_restart(0); diff --git a/arch/arm/mach-s3c24xx/setup-i2c.c b/arch/arm/mach-s3c24xx/setup-i2c.c index 7b4f33332d1..1852696ca16 100644 --- a/arch/arm/mach-s3c24xx/setup-i2c.c +++ b/arch/arm/mach-s3c24xx/setup-i2c.c @@ -19,6 +19,7 @@ struct platform_device; #include <linux/platform_data/i2c-s3c2410.h> #include <mach/hardware.h> #include <mach/regs-gpio.h> +#include <mach/gpio-samsung.h> void s3c_i2c0_cfg_gpio(struct platform_device *dev) { diff --git a/arch/arm/mach-s3c24xx/setup-sdhci-gpio.c b/arch/arm/mach-s3c24xx/setup-sdhci-gpio.c index f65cb3ef16c..c99b0f664db 100644 --- a/arch/arm/mach-s3c24xx/setup-sdhci-gpio.c +++ b/arch/arm/mach-s3c24xx/setup-sdhci-gpio.c @@ -20,6 +20,7 @@ #include <linux/gpio.h> #include <mach/regs-gpio.h> +#include <mach/gpio-samsung.h> #include <plat/gpio-cfg.h> void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) diff --git a/arch/arm/mach-s3c24xx/setup-ts.c b/arch/arm/mach-s3c24xx/setup-ts.c index 4e11affce3a..46466d20257 100644 --- a/arch/arm/mach-s3c24xx/setup-ts.c +++ b/arch/arm/mach-s3c24xx/setup-ts.c @@ -15,7 +15,9 @@ struct platform_device; /* don't need the contents */ +#include <plat/gpio-cfg.h> #include <mach/hardware.h> +#include <mach/gpio-samsung.h> /** * s3c24xx_ts_cfg_gpio - configure gpio for s3c2410 systems diff --git a/arch/arm/mach-s3c24xx/simtec-usb.c b/arch/arm/mach-s3c24xx/simtec-usb.c index 2ed2e32430d..b70aa66efeb 100644 --- a/arch/arm/mach-s3c24xx/simtec-usb.c +++ b/arch/arm/mach-s3c24xx/simtec-usb.c @@ -29,6 +29,7 @@ #include <asm/mach/irq.h> #include <mach/hardware.h> +#include <mach/gpio-samsung.h> #include <asm/irq.h> #include <linux/platform_data/usb-ohci-s3c2410.h> @@ -78,8 +79,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on) if (on) { ret = request_irq(BAST_IRQ_USBOC, usb_simtec_ocirq, - IRQF_DISABLED | IRQF_TRIGGER_RISING | - IRQF_TRIGGER_FALLING, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "USB Over-current", info); if (ret != 0) { printk(KERN_ERR "failed to request usb oc irq\n"); diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2410.S b/arch/arm/mach-s3c24xx/sleep-s3c2410.S index dd47c8fa07f..c9b91223697 100644 --- a/arch/arm/mach-s3c24xx/sleep-s3c2410.S +++ b/arch/arm/mach-s3c24xx/sleep-s3c2410.S @@ -25,13 +25,13 @@ */ #include <linux/linkage.h> +#include <linux/serial_s3c.h> #include <asm/assembler.h> #include <mach/hardware.h> #include <mach/map.h> #include <mach/regs-gpio.h> #include <mach/regs-clock.h> -#include <plat/regs-serial.h> #include "regs-mem.h" diff --git a/arch/arm/mach-s3c24xx/sleep.S b/arch/arm/mach-s3c24xx/sleep.S index 7f378b662da..d833d616bd2 100644 --- a/arch/arm/mach-s3c24xx/sleep.S +++ b/arch/arm/mach-s3c24xx/sleep.S @@ -25,13 +25,13 @@ */ #include <linux/linkage.h> +#include <linux/serial_s3c.h> #include <asm/assembler.h> #include <mach/hardware.h> #include <mach/map.h> #include <mach/regs-gpio.h> #include <mach/regs-clock.h> -#include <plat/regs-serial.h> /* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not * reset the UART configuration, only enable if you really need this! |