1 files changed, 208 insertions, 232 deletions

diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 539b596005f..0eecd83c624 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -1,7 +1,7 @@
 /*
  *  linux/arch/arm/mach-pxa/irq.c
  *
- *  Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc.
+ *  Generic PXA IRQ handling
  *
  *  Author:	Nicolas Pitre
  *  Created:	Jun 15, 2001
@@ -11,303 +11,279 @@
  *  it under the terms of the GNU General Public License version 2 as
  *  published by the Free Software Foundation.
  */
-
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
-#include <linux/ptrace.h>
+#include <linux/syscore_ops.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include <asm/exception.h>
 
-#include <asm/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
 
 #include "generic.h"
 
+#define ICIP			(0x000)
+#define ICMR			(0x004)
+#define ICLR			(0x008)
+#define ICFR			(0x00c)
+#define ICPR			(0x010)
+#define ICCR			(0x014)
+#define ICHP			(0x018)
+#define IPR(i)			(((i) < 32) ? (0x01c + ((i) << 2)) :		\
+				((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) :	\
+				      (0x144 + (((i) - 64) << 2)))
+#define ICHP_VAL_IRQ		(1 << 31)
+#define ICHP_IRQ(i)		(((i) >> 16) & 0x7fff)
+#define IPR_VALID		(1 << 31)
+#define IRQ_BIT(n)		(((n) - PXA_IRQ(0)) & 0x1f)
+
+#define MAX_INTERNAL_IRQS	128
 
 /*
  * This is for peripheral IRQs internal to the PXA chip.
  */
 
-static void pxa_mask_low_irq(unsigned int irq)
+static void __iomem *pxa_irq_base;
+static int pxa_internal_irq_nr;
+static bool cpu_has_ipr;
+
+static inline void __iomem *irq_base(int i)
 {
-	ICMR &= ~(1 << (irq + PXA_IRQ_SKIP));
+	static unsigned long phys_base_offset[] = {
+		0x0,
+		0x9c,
+		0x130,
+	};
+
+	return pxa_irq_base + phys_base_offset[i];
 }
 
-static void pxa_unmask_low_irq(unsigned int irq)
+void pxa_mask_irq(struct irq_data *d)
 {
-	ICMR |= (1 << (irq + PXA_IRQ_SKIP));
+	void __iomem *base = irq_data_get_irq_chip_data(d);
+	uint32_t icmr = __raw_readl(base + ICMR);
+
+	icmr &= ~(1 << IRQ_BIT(d->irq));
+	__raw_writel(icmr, base + ICMR);
 }
 
-static struct irqchip pxa_internal_chip_low = {
-	.ack		= pxa_mask_low_irq,
-	.mask		= pxa_mask_low_irq,
-	.unmask		= pxa_unmask_low_irq,
-};
+void pxa_unmask_irq(struct irq_data *d)
+{
+	void __iomem *base = irq_data_get_irq_chip_data(d);
+	uint32_t icmr = __raw_readl(base + ICMR);
 
-#if PXA_INTERNAL_IRQS > 32
+	icmr |= 1 << IRQ_BIT(d->irq);
+	__raw_writel(icmr, base + ICMR);
+}
 
-/*
- * This is for the second set of internal IRQs as found on the PXA27x.
- */
+static struct irq_chip pxa_internal_irq_chip = {
+	.name		= "SC",
+	.irq_ack	= pxa_mask_irq,
+	.irq_mask	= pxa_mask_irq,
+	.irq_unmask	= pxa_unmask_irq,
+};
 
-static void pxa_mask_high_irq(unsigned int irq)
+asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
 {
-	ICMR2 &= ~(1 << (irq - 32 + PXA_IRQ_SKIP));
-}
+	uint32_t icip, icmr, mask;
 
-static void pxa_unmask_high_irq(unsigned int irq)
-{
-	ICMR2 |= (1 << (irq - 32 + PXA_IRQ_SKIP));
+	do {
+		icip = __raw_readl(pxa_irq_base + ICIP);
+		icmr = __raw_readl(pxa_irq_base + ICMR);
+		mask = icip & icmr;
+
+		if (mask == 0)
+			break;
+
+		handle_IRQ(PXA_IRQ(fls(mask) - 1), regs);
+	} while (1);
 }
 
-static struct irqchip pxa_internal_chip_high = {
-	.ack		= pxa_mask_high_irq,
-	.mask		= pxa_mask_high_irq,
-	.unmask		= pxa_unmask_high_irq,
-};
+asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
+{
+	uint32_t ichp;
 
-#endif
+	do {
+		__asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp));
 
-/*
- * PXA GPIO edge detection for IRQs:
- * IRQs are generated on Falling-Edge, Rising-Edge, or both.
- * Use this instead of directly setting GRER/GFER.
- */
+		if ((ichp & ICHP_VAL_IRQ) == 0)
+			break;
 
-static long GPIO_IRQ_rising_edge[4];
-static long GPIO_IRQ_falling_edge[4];
-static long GPIO_IRQ_mask[4];
+		handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs);
+	} while (1);
+}
 
-static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
+void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
 {
-	int gpio, idx;
-
-	gpio = IRQ_TO_GPIO(irq);
-	idx = gpio >> 5;
-
-	if (type == IRQT_PROBE) {
-	    /* Don't mess with enabled GPIOs using preconfigured edges or
-	       GPIOs set to alternate function during probe */
-		if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx]) &
-		    GPIO_bit(gpio))
-			return 0;
-		if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
-			return 0;
-		type = __IRQT_RISEDGE | __IRQT_FALEDGE;
-	}
+	int irq, i, n;
 
-	/* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */
+	BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
 
-	pxa_gpio_mode(gpio | GPIO_IN);
+	pxa_internal_irq_nr = irq_nr;
+	cpu_has_ipr = !cpu_is_pxa25x();
+	pxa_irq_base = io_p2v(0x40d00000);
 
-	if (type & __IRQT_RISEDGE) {
-		/* printk("rising "); */
-		__set_bit (gpio, GPIO_IRQ_rising_edge);
-	} else
-		__clear_bit (gpio, GPIO_IRQ_rising_edge);
+	for (n = 0; n < irq_nr; n += 32) {
+		void __iomem *base = irq_base(n >> 5);
 
-	if (type & __IRQT_FALEDGE) {
-		/* printk("falling "); */
-		__set_bit (gpio, GPIO_IRQ_falling_edge);
-	} else
-		__clear_bit (gpio, GPIO_IRQ_falling_edge);
+		__raw_writel(0, base + ICMR);	/* disable all IRQs */
+		__raw_writel(0, base + ICLR);	/* all IRQs are IRQ, not FIQ */
+		for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
+			/* initialize interrupt priority */
+			if (cpu_has_ipr)
+				__raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i));
 
-	/* printk("edges\n"); */
+			irq = PXA_IRQ(i);
+			irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
+						 handle_level_irq);
+			irq_set_chip_data(irq, base);
+			set_irq_flags(irq, IRQF_VALID);
+		}
+	}
 
-	GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
-	GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
-	return 0;
+	/* only unmasked interrupts kick us out of idle */
+	__raw_writel(1, irq_base(0) + ICCR);
+
+	pxa_internal_irq_chip.irq_set_wake = fn;
 }
 
-/*
- * GPIO IRQs must be acknowledged.  This is for GPIO 0 and 1.
- */
+#ifdef CONFIG_PM
+static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
+static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
 
-static void pxa_ack_low_gpio(unsigned int irq)
+static int pxa_irq_suspend(void)
 {
-	GEDR0 = (1 << (irq - IRQ_GPIO0));
-}
+	int i;
 
-static struct irqchip pxa_low_gpio_chip = {
-	.ack		= pxa_ack_low_gpio,
-	.mask		= pxa_mask_low_irq,
-	.unmask		= pxa_unmask_low_irq,
-	.set_type	= pxa_gpio_irq_type,
-};
+	for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
+		void __iomem *base = irq_base(i);
 
-/*
- * Demux handler for GPIO>=2 edge detect interrupts
- */
+		saved_icmr[i] = __raw_readl(base + ICMR);
+		__raw_writel(0, base + ICMR);
+	}
 
-static void pxa_gpio_demux_handler(unsigned int irq, struct irqdesc *desc,
-				   struct pt_regs *regs)
+	if (cpu_has_ipr) {
+		for (i = 0; i < pxa_internal_irq_nr; i++)
+			saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i));
+	}
+
+	return 0;
+}
+
+static void pxa_irq_resume(void)
 {
-	unsigned int mask;
-	int loop;
+	int i;
 
-	do {
-		loop = 0;
-
-		mask = GEDR0 & ~3;
-		if (mask) {
-			GEDR0 = mask;
-			irq = IRQ_GPIO(2);
-			desc = irq_desc + irq;
-			mask >>= 2;
-			do {
-				if (mask & 1)
-					desc_handle_irq(irq, desc, regs);
-				irq++;
-				desc++;
-				mask >>= 1;
-			} while (mask);
-			loop = 1;
-		}
+	for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
+		void __iomem *base = irq_base(i);
 
-		mask = GEDR1;
-		if (mask) {
-			GEDR1 = mask;
-			irq = IRQ_GPIO(32);
-			desc = irq_desc + irq;
-			do {
-				if (mask & 1)
-					desc_handle_irq(irq, desc, regs);
-				irq++;
-				desc++;
-				mask >>= 1;
-			} while (mask);
-			loop = 1;
-		}
+		__raw_writel(saved_icmr[i], base + ICMR);
+		__raw_writel(0, base + ICLR);
+	}
 
-		mask = GEDR2;
-		if (mask) {
-			GEDR2 = mask;
-			irq = IRQ_GPIO(64);
-			desc = irq_desc + irq;
-			do {
-				if (mask & 1)
-					desc_handle_irq(irq, desc, regs);
-				irq++;
-				desc++;
-				mask >>= 1;
-			} while (mask);
-			loop = 1;
-		}
+	if (cpu_has_ipr)
+		for (i = 0; i < pxa_internal_irq_nr; i++)
+			__raw_writel(saved_ipr[i], pxa_irq_base + IPR(i));
 
-#if PXA_LAST_GPIO >= 96
-		mask = GEDR3;
-		if (mask) {
-			GEDR3 = mask;
-			irq = IRQ_GPIO(96);
-			desc = irq_desc + irq;
-			do {
-				if (mask & 1)
-					desc_handle_irq(irq, desc, regs);
-				irq++;
-				desc++;
-				mask >>= 1;
-			} while (mask);
-			loop = 1;
-		}
-#endif
-	} while (loop);
+	__raw_writel(1, pxa_irq_base + ICCR);
 }
+#else
+#define pxa_irq_suspend		NULL
+#define pxa_irq_resume		NULL
+#endif
 
-static void pxa_ack_muxed_gpio(unsigned int irq)
-{
-	int gpio = irq - IRQ_GPIO(2) + 2;
-	GEDR(gpio) = GPIO_bit(gpio);
-}
+struct syscore_ops pxa_irq_syscore_ops = {
+	.suspend	= pxa_irq_suspend,
+	.resume		= pxa_irq_resume,
+};
 
-static void pxa_mask_muxed_gpio(unsigned int irq)
-{
-	int gpio = irq - IRQ_GPIO(2) + 2;
-	__clear_bit(gpio, GPIO_IRQ_mask);
-	GRER(gpio) &= ~GPIO_bit(gpio);
-	GFER(gpio) &= ~GPIO_bit(gpio);
-}
+#ifdef CONFIG_OF
+static struct irq_domain *pxa_irq_domain;
 
-static void pxa_unmask_muxed_gpio(unsigned int irq)
+static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
+		       irq_hw_number_t hw)
 {
-	int gpio = irq - IRQ_GPIO(2) + 2;
-	int idx = gpio >> 5;
-	__set_bit(gpio, GPIO_IRQ_mask);
-	GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
-	GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
+	void __iomem *base = irq_base(hw / 32);
+
+	/* initialize interrupt priority */
+	if (cpu_has_ipr)
+		__raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
+
+	irq_set_chip_and_handler(hw, &pxa_internal_irq_chip,
+				 handle_level_irq);
+	irq_set_chip_data(hw, base);
+	set_irq_flags(hw, IRQF_VALID);
+
+	return 0;
 }
 
-static struct irqchip pxa_muxed_gpio_chip = {
-	.ack		= pxa_ack_muxed_gpio,
-	.mask		= pxa_mask_muxed_gpio,
-	.unmask		= pxa_unmask_muxed_gpio,
-	.set_type	= pxa_gpio_irq_type,
+static struct irq_domain_ops pxa_irq_ops = {
+	.map    = pxa_irq_map,
+	.xlate  = irq_domain_xlate_onecell,
 };
 
+static const struct of_device_id intc_ids[] __initconst = {
+	{ .compatible = "marvell,pxa-intc", },
+	{}
+};
 
-void __init pxa_init_irq(void)
+void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
 {
-	int irq;
-
-	/* disable all IRQs */
-	ICMR = 0;
-
-	/* all IRQs are IRQ, not FIQ */
-	ICLR = 0;
-
-	/* clear all GPIO edge detects */
-	GFER0 = 0;
-	GFER1 = 0;
-	GFER2 = 0;
-	GRER0 = 0;
-	GRER1 = 0;
-	GRER2 = 0;
-	GEDR0 = GEDR0;
-	GEDR1 = GEDR1;
-	GEDR2 = GEDR2;
-
-#ifdef CONFIG_PXA27x
-	/* And similarly for the extra regs on the PXA27x */
-	ICMR2 = 0;
-	ICLR2 = 0;
-	GFER3 = 0;
-	GRER3 = 0;
-	GEDR3 = GEDR3;
-#endif
-
-	/* only unmasked interrupts kick us out of idle */
-	ICCR = 1;
-
-	/* GPIO 0 and 1 must have their mask bit always set */
-	GPIO_IRQ_mask[0] = 3;
+	struct device_node *node;
+	struct resource res;
+	int n, ret;
+
+	node = of_find_matching_node(NULL, intc_ids);
+	if (!node) {
+		pr_err("Failed to find interrupt controller in arch-pxa\n");
+		return;
+	}
 
-	for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) {
-		set_irq_chip(irq, &pxa_internal_chip_low);
-		set_irq_handler(irq, do_level_IRQ);
-		set_irq_flags(irq, IRQF_VALID);
+	ret = of_property_read_u32(node, "marvell,intc-nr-irqs",
+				   &pxa_internal_irq_nr);
+	if (ret) {
+		pr_err("Not found marvell,intc-nr-irqs property\n");
+		return;
 	}
 
-#if PXA_INTERNAL_IRQS > 32
-	for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) {
-		set_irq_chip(irq, &pxa_internal_chip_high);
-		set_irq_handler(irq, do_level_IRQ);
-		set_irq_flags(irq, IRQF_VALID);
+	ret = of_address_to_resource(node, 0, &res);
+	if (ret < 0) {
+		pr_err("No registers defined for node\n");
+		return;
 	}
-#endif
+	pxa_irq_base = io_p2v(res.start);
 
-	for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
-		set_irq_chip(irq, &pxa_low_gpio_chip);
-		set_irq_handler(irq, do_edge_IRQ);
-		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+	if (of_find_property(node, "marvell,intc-priority", NULL))
+		cpu_has_ipr = 1;
+
+	ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0);
+	if (ret < 0) {
+		pr_err("Failed to allocate IRQ numbers\n");
+		return;
 	}
 
-	for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) {
-		set_irq_chip(irq, &pxa_muxed_gpio_chip);
-		set_irq_handler(irq, do_edge_IRQ);
-		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+	pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0,
+					       &pxa_irq_ops, NULL);
+	if (!pxa_irq_domain)
+		panic("Unable to add PXA IRQ domain\n");
+
+	irq_set_default_host(pxa_irq_domain);
+
+	for (n = 0; n < pxa_internal_irq_nr; n += 32) {
+		void __iomem *base = irq_base(n >> 5);
+
+		__raw_writel(0, base + ICMR);	/* disable all IRQs */
+		__raw_writel(0, base + ICLR);	/* all IRQs are IRQ, not FIQ */
 	}
 
-	/* Install handler for GPIO>=2 edge detect interrupts */
-	set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low);
-	set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
+	/* only unmasked interrupts kick us out of idle */
+	__raw_writel(1, irq_base(0) + ICCR);
+
+	pxa_internal_irq_chip.irq_set_wake = fn;
 }
+#endif /* CONFIG_OF */