diff options
Diffstat (limited to 'arch/arm/mach-pxa/include/mach')
89 files changed, 1727 insertions, 2476 deletions
diff --git a/arch/arm/mach-pxa/include/mach/addr-map.h b/arch/arm/mach-pxa/include/mach/addr-map.h new file mode 100644 index 00000000000..bbf9df37ad4 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/addr-map.h @@ -0,0 +1,48 @@ +#ifndef __ASM_MACH_ADDR_MAP_H +#define __ASM_MACH_ADDR_MAP_H + +/* + * Chip Selects + */ +#define PXA_CS0_PHYS 0x00000000 +#define PXA_CS1_PHYS 0x04000000 +#define PXA_CS2_PHYS 0x08000000 +#define PXA_CS3_PHYS 0x0C000000 +#define PXA_CS4_PHYS 0x10000000 +#define PXA_CS5_PHYS 0x14000000 + +#define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */ +#define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */ +#define PXA3xx_CS2_PHYS 0x10000000 +#define PXA3xx_CS3_PHYS 0x14000000 + +/* + * Peripheral Bus + */ +#define PERIPH_PHYS 0x40000000 +#define PERIPH_VIRT IOMEM(0xf2000000) +#define PERIPH_SIZE 0x02000000 + +/* + * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x) + */ +#define PXA2XX_SMEMC_PHYS 0x48000000 +#define PXA3XX_SMEMC_PHYS 0x4a000000 +#define SMEMC_VIRT IOMEM(0xf6000000) +#define SMEMC_SIZE 0x00100000 + +/* + * Dynamic Memory Controller (only on PXA3xx) + */ +#define DMEMC_PHYS 0x48100000 +#define DMEMC_VIRT IOMEM(0xf6100000) +#define DMEMC_SIZE 0x00100000 + +/* + * Internal Memory Controller (PXA27x and later) + */ +#define IMEMC_PHYS 0x58000000 +#define IMEMC_VIRT IOMEM(0xfe000000) +#define IMEMC_SIZE 0x00100000 + +#endif /* __ASM_MACH_ADDR_MAP_H */ diff --git a/arch/arm/mach-pxa/include/mach/audio.h b/arch/arm/mach-pxa/include/mach/audio.h index 16eb02552d5..a3449e35a6f 100644 --- a/arch/arm/mach-pxa/include/mach/audio.h +++ b/arch/arm/mach-pxa/include/mach/audio.h @@ -3,10 +3,12 @@ #include <sound/core.h> #include <sound/pcm.h> +#include <sound/ac97_codec.h> /* * @reset_gpio: AC97 reset gpio (normally gpio113 or gpio95) * a -1 value means no gpio will be used for reset + * @codec_pdata: AC97 codec platform_data * reset_gpio should only be specified for pxa27x CPUs where a silicon * bug prevents correct operation of the reset line. If not specified, @@ -20,6 +22,7 @@ typedef struct { void (*resume)(void *); void *priv; int reset_gpio; + void *codec_pdata[AC97_BUS_MAX_DEVICES]; } pxa2xx_audio_ops_t; extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops); diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h new file mode 100644 index 00000000000..1b0825911e6 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/balloon3.h @@ -0,0 +1,184 @@ +/* + * linux/include/asm-arm/arch-pxa/balloon3.h + * + * Authors: Nick Bane and Wookey + * Created: Oct, 2005 + * Copyright: Toby Churchill Ltd + * Cribbed from mainstone.c, by Nicholas Pitre + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef ASM_ARCH_BALLOON3_H +#define ASM_ARCH_BALLOON3_H + +#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ + +enum balloon3_features { + BALLOON3_FEATURE_OHCI, + BALLOON3_FEATURE_MMC, + BALLOON3_FEATURE_CF, + BALLOON3_FEATURE_AUDIO, + BALLOON3_FEATURE_TOPPOLY, +}; + +#define BALLOON3_FPGA_PHYS PXA_CS4_PHYS +#define BALLOON3_FPGA_VIRT IOMEM(0xf1000000) /* as per balloon2 */ +#define BALLOON3_FPGA_LENGTH 0x01000000 + +#define BALLOON3_FPGA_SETnCLR (0x1000) + +/* FPGA / CPLD registers for CF socket */ +#define BALLOON3_CF_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00e00008) +#define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008) +/* FPGA / CPLD version register */ +#define BALLOON3_FPGA_VER (BALLOON3_FPGA_VIRT + 0x00e0001c) +/* FPGA / CPLD registers for NAND flash */ +#define BALLOON3_NAND_BASE (PXA_CS4_PHYS + 0x00e00000) +#define BALLOON3_NAND_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000) +#define BALLOON3_NAND_CONTROL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010) +#define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00014) +#define BALLOON3_NAND_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00014) + +/* fpga/cpld interrupt control register */ +#define BALLOON3_INT_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e0000C) +#define BALLOON3_VERSION_REG (BALLOON3_FPGA_VIRT + 0x00e0001c) + +#define BALLOON3_SAMOSA_ADDR_REG (BALLOON3_FPGA_VIRT + 0x00c00000) +#define BALLOON3_SAMOSA_DATA_REG (BALLOON3_FPGA_VIRT + 0x00c00004) +#define BALLOON3_SAMOSA_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00c0001c) + +/* CF Status Register bits (read-only) bits */ +#define BALLOON3_CF_nIRQ (1 << 0) +#define BALLOON3_CF_nSTSCHG_BVD1 (1 << 1) + +/* CF Control Set Register bits / CF Control Clear Register bits (write-only) */ +#define BALLOON3_CF_RESET (1 << 0) +#define BALLOON3_CF_ENABLE (1 << 1) +#define BALLOON3_CF_ADD_ENABLE (1 << 2) + +/* CF Interrupt sources */ +#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0) +#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1) + +/* NAND Control register */ +#define BALLOON3_NAND_CONTROL_FLWP (1 << 7) +#define BALLOON3_NAND_CONTROL_FLSE (1 << 6) +#define BALLOON3_NAND_CONTROL_FLCE3 (1 << 5) +#define BALLOON3_NAND_CONTROL_FLCE2 (1 << 4) +#define BALLOON3_NAND_CONTROL_FLCE1 (1 << 3) +#define BALLOON3_NAND_CONTROL_FLCE0 (1 << 2) +#define BALLOON3_NAND_CONTROL_FLALE (1 << 1) +#define BALLOON3_NAND_CONTROL_FLCLE (1 << 0) + +/* NAND Status register */ +#define BALLOON3_NAND_STAT_RNB (1 << 0) + +/* NAND Control2 register */ +#define BALLOON3_NAND_CONTROL2_16BIT (1 << 0) + +/* GPIOs for irqs */ +#define BALLOON3_GPIO_AUX_NIRQ (94) +#define BALLOON3_GPIO_CODEC_IRQ (95) + +/* Timer and Idle LED locations */ +#define BALLOON3_GPIO_LED_NAND (9) +#define BALLOON3_GPIO_LED_IDLE (10) + +/* backlight control */ +#define BALLOON3_GPIO_RUN_BACKLIGHT (99) + +#define BALLOON3_GPIO_S0_CD (105) + +/* NAND */ +#define BALLOON3_GPIO_RUN_NAND (102) + +/* PCF8574A Leds */ +#define BALLOON3_PCF_GPIO_BASE 160 +#define BALLOON3_PCF_GPIO_LED0 (BALLOON3_PCF_GPIO_BASE + 0) +#define BALLOON3_PCF_GPIO_LED1 (BALLOON3_PCF_GPIO_BASE + 1) +#define BALLOON3_PCF_GPIO_LED2 (BALLOON3_PCF_GPIO_BASE + 2) +#define BALLOON3_PCF_GPIO_LED3 (BALLOON3_PCF_GPIO_BASE + 3) +#define BALLOON3_PCF_GPIO_LED4 (BALLOON3_PCF_GPIO_BASE + 4) +#define BALLOON3_PCF_GPIO_LED5 (BALLOON3_PCF_GPIO_BASE + 5) +#define BALLOON3_PCF_GPIO_LED6 (BALLOON3_PCF_GPIO_BASE + 6) +#define BALLOON3_PCF_GPIO_LED7 (BALLOON3_PCF_GPIO_BASE + 7) + +/* FPGA Interrupt Mask/Acknowledge Register */ +#define BALLOON3_INT_S0_IRQ (1 << 0) /* PCMCIA 0 IRQ */ +#define BALLOON3_INT_S0_STSCHG (1 << 1) /* PCMCIA 0 status changed */ + +/* CPLD (and FPGA) interface definitions */ +#define CPLD_LCD0_DATA_SET 0x00 +#define CPLD_LCD0_DATA_CLR 0x10 +#define CPLD_LCD0_COMMAND_SET 0x01 +#define CPLD_LCD0_COMMAND_CLR 0x11 +#define CPLD_LCD1_DATA_SET 0x02 +#define CPLD_LCD1_DATA_CLR 0x12 +#define CPLD_LCD1_COMMAND_SET 0x03 +#define CPLD_LCD1_COMMAND_CLR 0x13 + +#define CPLD_MISC_SET 0x07 +#define CPLD_MISC_CLR 0x17 +#define CPLD_MISC_LOON_NRESET_BIT 0 +#define CPLD_MISC_LOON_UNSUSP_BIT 1 +#define CPLD_MISC_RUN_5V_BIT 2 +#define CPLD_MISC_CHG_D0_BIT 3 +#define CPLD_MISC_CHG_D1_BIT 4 +#define CPLD_MISC_DAC_NCS_BIT 5 + +#define CPLD_LCD_SET 0x08 +#define CPLD_LCD_CLR 0x18 +#define CPLD_LCD_BACKLIGHT_EN_0_BIT 0 +#define CPLD_LCD_BACKLIGHT_EN_1_BIT 1 +#define CPLD_LCD_LED_RED_BIT 4 +#define CPLD_LCD_LED_GREEN_BIT 5 +#define CPLD_LCD_NRESET_BIT 7 + +#define CPLD_LCD_RO_SET 0x09 +#define CPLD_LCD_RO_CLR 0x19 +#define CPLD_LCD_RO_LCD0_nWAIT_BIT 0 +#define CPLD_LCD_RO_LCD1_nWAIT_BIT 1 + +#define CPLD_SERIAL_SET 0x0a +#define CPLD_SERIAL_CLR 0x1a +#define CPLD_SERIAL_GSM_RI_BIT 0 +#define CPLD_SERIAL_GSM_CTS_BIT 1 +#define CPLD_SERIAL_GSM_DTR_BIT 2 +#define CPLD_SERIAL_LPR_CTS_BIT 3 +#define CPLD_SERIAL_TC232_CTS_BIT 4 +#define CPLD_SERIAL_TC232_DSR_BIT 5 + +#define CPLD_SROUTING_SET 0x0b +#define CPLD_SROUTING_CLR 0x1b +#define CPLD_SROUTING_MSP430_LPR 0 +#define CPLD_SROUTING_MSP430_TC232 1 +#define CPLD_SROUTING_MSP430_GSM 2 +#define CPLD_SROUTING_LOON_LPR (0 << 4) +#define CPLD_SROUTING_LOON_TC232 (1 << 4) +#define CPLD_SROUTING_LOON_GSM (2 << 4) + +#define CPLD_AROUTING_SET 0x0c +#define CPLD_AROUTING_CLR 0x1c +#define CPLD_AROUTING_MIC2PHONE_BIT 0 +#define CPLD_AROUTING_PHONE2INT_BIT 1 +#define CPLD_AROUTING_PHONE2EXT_BIT 2 +#define CPLD_AROUTING_LOONL2INT_BIT 3 +#define CPLD_AROUTING_LOONL2EXT_BIT 4 +#define CPLD_AROUTING_LOONR2PHONE_BIT 5 +#define CPLD_AROUTING_LOONR2INT_BIT 6 +#define CPLD_AROUTING_LOONR2EXT_BIT 7 + +/* Balloon3 Interrupts */ +#define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x)) + +#define BALLOON3_AUX_NIRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_AUX_NIRQ) +#define BALLOON3_CODEC_IRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ) + +#define BALLOON3_NR_IRQS (IRQ_BOARD_START + 16) + +extern int balloon3_has(enum balloon3_features feature); + +#endif diff --git a/arch/arm/mach-pxa/include/mach/camera.h b/arch/arm/mach-pxa/include/mach/camera.h deleted file mode 100644 index 31abe6d514b..00000000000 --- a/arch/arm/mach-pxa/include/mach/camera.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - camera.h - PXA camera driver header file - - Copyright (C) 2003, Intel Corporation - Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -*/ - -#ifndef __ASM_ARCH_CAMERA_H_ -#define __ASM_ARCH_CAMERA_H_ - -#define PXA_CAMERA_MASTER 1 -#define PXA_CAMERA_DATAWIDTH_4 2 -#define PXA_CAMERA_DATAWIDTH_5 4 -#define PXA_CAMERA_DATAWIDTH_8 8 -#define PXA_CAMERA_DATAWIDTH_9 0x10 -#define PXA_CAMERA_DATAWIDTH_10 0x20 -#define PXA_CAMERA_PCLK_EN 0x40 -#define PXA_CAMERA_MCLK_EN 0x80 -#define PXA_CAMERA_PCP 0x100 -#define PXA_CAMERA_HSP 0x200 -#define PXA_CAMERA_VSP 0x400 - -struct pxacamera_platform_data { - int (*init)(struct device *); - - unsigned long flags; - unsigned long mclk_10khz; -}; - -extern void pxa_set_camera_info(struct pxacamera_platform_data *); - -#endif /* __ASM_ARCH_CAMERA_H_ */ diff --git a/arch/arm/mach-pxa/include/mach/clkdev.h b/arch/arm/mach-pxa/include/mach/clkdev.h deleted file mode 100644 index 04b37a89801..00000000000 --- a/arch/arm/mach-pxa/include/mach/clkdev.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __ASM_MACH_CLKDEV_H -#define __ASM_MACH_CLKDEV_H - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do { } while (0) - -#endif diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h index a88d7caff0d..cb4236e98a0 100644 --- a/arch/arm/mach-pxa/include/mach/colibri.h +++ b/arch/arm/mach-pxa/include/mach/colibri.h @@ -2,6 +2,28 @@ #define _COLIBRI_H_ #include <net/ax88796.h> +#include <mach/mfp.h> + +/* + * base board glue for PXA270 module + */ + +enum { + COLIBRI_EVALBOARD = 0, + COLIBRI_PXA270_INCOME, +}; + +#if defined(CONFIG_MACH_COLIBRI_EVALBOARD) +extern void colibri_evalboard_init(void); +#else +static inline void colibri_evalboard_init(void) {} +#endif + +#if defined(CONFIG_MACH_COLIBRI_PXA270_INCOME) +extern void colibri_pxa270_income_boardinit(void); +#else +static inline void colibri_pxa270_income_boardinit(void) {} +#endif /* * common settings for all modules @@ -23,16 +45,25 @@ static inline void colibri_pxa3xx_init_lcd(int bl_pin) {} extern void colibri_pxa3xx_init_eth(struct ax_plat_data *plat_data); #endif +#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE) +extern void colibri_pxa3xx_init_nand(void); +#else +static inline void colibri_pxa3xx_init_nand(void) {} +#endif + /* physical memory regions */ #define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */ -/* definitions for Colibri PXA270 */ +/* GPIO definitions for Colibri PXA270 */ +#define GPIO114_COLIBRI_PXA270_ETH_IRQ 114 +#define GPIO0_COLIBRI_PXA270_SD_DETECT 0 +#define GPIO113_COLIBRI_PXA270_TS_IRQ 113 + +/* GPIO definitions for Colibri PXA300/310 */ +#define GPIO13_COLIBRI_PXA300_SD_DETECT 13 -#define COLIBRI_PXA270_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ -#define COLIBRI_PXA270_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet */ -#define COLIBRI_PXA270_ETH_IRQ_GPIO 114 -#define COLIBRI_PXA270_ETH_IRQ \ - gpio_to_irq(mfp_to_gpio(COLIBRI_PXA270_ETH_IRQ_GPIO)) +/* GPIO definitions for Colibri PXA320 */ +#define GPIO28_COLIBRI_PXA320_SD_DETECT 28 #endif /* _COLIBRI_H_ */ diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h index 7239281788d..c030d955bbd 100644 --- a/arch/arm/mach-pxa/include/mach/corgi.h +++ b/arch/arm/mach-pxa/include/mach/corgi.h @@ -13,6 +13,7 @@ #ifndef __ASM_ARCH_CORGI_H #define __ASM_ARCH_CORGI_H 1 +#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ /* * Corgi (Non Standard) GPIO Definitions @@ -34,7 +35,7 @@ #define CORGI_GPIO_LCDCON_CS (19) /* LCD Control Chip Select */ #define CORGI_GPIO_MAX1111_CS (20) /* MAX1111 Chip Select */ #define CORGI_GPIO_ADC_TEMP_ON (21) /* Select battery voltage or temperature */ -#define CORGI_GPIO_IR_ON (22) /* Enable IR Transciever */ +#define CORGI_GPIO_IR_ON (22) /* Enable IR Transceiver */ #define CORGI_GPIO_ADS7846_CS (24) /* ADS7846 Chip Select */ #define CORGI_GPIO_SD_PWR (33) /* MMC/SD Power */ #define CORGI_GPIO_CHRG_ON (38) /* Enable battery Charging */ @@ -66,18 +67,18 @@ /* * Corgi Interrupts */ -#define CORGI_IRQ_GPIO_KEY_INT IRQ_GPIO(0) -#define CORGI_IRQ_GPIO_AC_IN IRQ_GPIO(1) -#define CORGI_IRQ_GPIO_WAKEUP IRQ_GPIO(3) -#define CORGI_IRQ_GPIO_AK_INT IRQ_GPIO(4) -#define CORGI_IRQ_GPIO_TP_INT IRQ_GPIO(5) -#define CORGI_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9) -#define CORGI_IRQ_GPIO_nSD_INT IRQ_GPIO(10) -#define CORGI_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(11) -#define CORGI_IRQ_GPIO_CF_CD IRQ_GPIO(14) -#define CORGI_IRQ_GPIO_CHRG_FULL IRQ_GPIO(16) /* Battery fully charged */ -#define CORGI_IRQ_GPIO_CF_IRQ IRQ_GPIO(17) -#define CORGI_IRQ_GPIO_KEY_SENSE(a) IRQ_GPIO(58+(a)) /* Keyboard Sense lines */ +#define CORGI_IRQ_GPIO_KEY_INT PXA_GPIO_TO_IRQ(0) +#define CORGI_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(1) +#define CORGI_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(3) +#define CORGI_IRQ_GPIO_AK_INT PXA_GPIO_TO_IRQ(4) +#define CORGI_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(5) +#define CORGI_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(9) +#define CORGI_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(10) +#define CORGI_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(11) +#define CORGI_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(14) +#define CORGI_IRQ_GPIO_CHRG_FULL PXA_GPIO_TO_IRQ(16) /* Battery fully charged */ +#define CORGI_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(17) +#define CORGI_IRQ_GPIO_KEY_SENSE(a) PXA_GPIO_TO_IRQ(58+(a)) /* Keyboard Sense lines */ /* @@ -98,7 +99,7 @@ CORGI_SCP_MIC_BIAS ) #define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R ) -#define CORGI_SCOOP_GPIO_BASE (NR_BUILTIN_GPIO) +#define CORGI_SCOOP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) #define CORGI_GPIO_LED_GREEN (CORGI_SCOOP_GPIO_BASE + 0) #define CORGI_GPIO_SWA (CORGI_SCOOP_GPIO_BASE + 1) /* Hinge Switch A */ #define CORGI_GPIO_SWB (CORGI_SCOOP_GPIO_BASE + 2) /* Hinge Switch B */ @@ -109,11 +110,5 @@ #define CORGI_GPIO_BACKLIGHT_CONT (CORGI_SCOOP_GPIO_BASE + 7) #define CORGI_GPIO_MIC_BIAS (CORGI_SCOOP_GPIO_BASE + 8) -/* - * Shared data structures - */ -extern struct platform_device corgiscoop_device; -extern struct platform_device corgissp_device; - #endif /* __ASM_ARCH_CORGI_H */ diff --git a/arch/arm/mach-pxa/include/mach/csb726.h b/arch/arm/mach-pxa/include/mach/csb726.h index 747ab1a71f2..00cfbbbf73f 100644 --- a/arch/arm/mach-pxa/include/mach/csb726.h +++ b/arch/arm/mach-pxa/include/mach/csb726.h @@ -11,6 +11,8 @@ #ifndef CSB726_H #define CSB726_H +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + #define CSB726_GPIO_IRQ_LAN 52 #define CSB726_GPIO_IRQ_SM501 53 #define CSB726_GPIO_MMC_DETECT 100 @@ -19,8 +21,8 @@ #define CSB726_FLASH_SIZE (64 * 1024 * 1024) #define CSB726_FLASH_uMON (8 * 1024 * 1024) -#define CSB726_IRQ_LAN gpio_to_irq(CSB726_GPIO_IRQ_LAN) -#define CSB726_IRQ_SM501 gpio_to_irq(CSB726_GPIO_IRQ_SM501) +#define CSB726_IRQ_LAN PXA_GPIO_TO_IRQ(CSB726_GPIO_IRQ_LAN) +#define CSB726_IRQ_SM501 PXA_GPIO_TO_IRQ(CSB726_GPIO_IRQ_SM501) #endif diff --git a/arch/arm/mach-pxa/include/mach/debug-macro.S b/arch/arm/mach-pxa/include/mach/debug-macro.S deleted file mode 100644 index 55d6a175ab1..00000000000 --- a/arch/arm/mach-pxa/include/mach/debug-macro.S +++ /dev/null @@ -1,25 +0,0 @@ -/* arch/arm/mach-pxa/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include "hardware.h" - - .macro addruart,rx - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 @ MMU enabled? - moveq \rx, #0x40000000 @ physical - movne \rx, #io_p2v(0x40000000) @ virtual - orr \rx, \rx, #0x00100000 - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-pxa/include/mach/entry-macro.S b/arch/arm/mach-pxa/include/mach/entry-macro.S deleted file mode 100644 index f6b4bf3e73d..00000000000 --- a/arch/arm/mach-pxa/include/mach/entry-macro.S +++ /dev/null @@ -1,57 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for PXA-based platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <mach/hardware.h> -#include <mach/irqs.h> - - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mrc p15, 0, \tmp, c0, c0, 0 @ CPUID - mov \tmp, \tmp, lsr #13 - and \tmp, \tmp, #0x7 @ Core G - cmp \tmp, #1 - bhi 1004f - - mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000 - add \base, \base, #0x00d00000 - ldr \irqstat, [\base, #0] @ ICIP - ldr \irqnr, [\base, #4] @ ICMR - b 1002f - -1004: - mrc p6, 0, \irqstat, c6, c0, 0 @ ICIP2 - mrc p6, 0, \irqnr, c7, c0, 0 @ ICMR2 - ands \irqnr, \irqstat, \irqnr - beq 1003f - rsb \irqstat, \irqnr, #0 - and \irqstat, \irqstat, \irqnr - clz \irqnr, \irqstat - rsb \irqnr, \irqnr, #31 - add \irqnr, \irqnr, #(32 + PXA_IRQ(0)) - b 1001f -1003: - mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP - mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR -1002: - ands \irqnr, \irqstat, \irqnr - beq 1001f - rsb \irqstat, \irqnr, #0 - and \irqstat, \irqstat, \irqnr - clz \irqnr, \irqstat - rsb \irqnr, \irqnr, #(31 + PXA_IRQ(0)) -1001: - .endm diff --git a/arch/arm/mach-pxa/include/mach/eseries-irq.h b/arch/arm/mach-pxa/include/mach/eseries-irq.h index f2a93d5e31d..de292b269c6 100644 --- a/arch/arm/mach-pxa/include/mach/eseries-irq.h +++ b/arch/arm/mach-pxa/include/mach/eseries-irq.h @@ -25,3 +25,4 @@ #define TMIO_SD_IRQ IRQ_TMIO(1) #define TMIO_USB_IRQ IRQ_TMIO(2) +#define ESERIES_NR_IRQS (IRQ_BOARD_START + 16) diff --git a/arch/arm/mach-pxa/include/mach/generic.h b/arch/arm/mach-pxa/include/mach/generic.h new file mode 100644 index 00000000000..665542e0c9e --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/generic.h @@ -0,0 +1 @@ +#include "../../generic.h" diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h deleted file mode 100644 index b024a8b3743..00000000000 --- a/arch/arm/mach-pxa/include/mach/gpio.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/gpio.h - * - * PXA GPIO wrappers for arch-neutral GPIO calls - * - * Written by Philipp Zabel <philipp.zabel@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __ASM_ARCH_PXA_GPIO_H -#define __ASM_ARCH_PXA_GPIO_H - -#include <mach/irqs.h> -#include <mach/hardware.h> -#include <asm-generic/gpio.h> - -#define GPIO_REGS_VIRT io_p2v(0x40E00000) - -#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) -#define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x))) - -/* GPIO Pin Level Registers */ -#define GPLR0 GPIO_REG(BANK_OFF(0) + 0x00) -#define GPLR1 GPIO_REG(BANK_OFF(1) + 0x00) -#define GPLR2 GPIO_REG(BANK_OFF(2) + 0x00) -#define GPLR3 GPIO_REG(BANK_OFF(3) + 0x00) - -/* GPIO Pin Direction Registers */ -#define GPDR0 GPIO_REG(BANK_OFF(0) + 0x0c) -#define GPDR1 GPIO_REG(BANK_OFF(1) + 0x0c) -#define GPDR2 GPIO_REG(BANK_OFF(2) + 0x0c) -#define GPDR3 GPIO_REG(BANK_OFF(3) + 0x0c) - -/* GPIO Pin Output Set Registers */ -#define GPSR0 GPIO_REG(BANK_OFF(0) + 0x18) -#define GPSR1 GPIO_REG(BANK_OFF(1) + 0x18) -#define GPSR2 GPIO_REG(BANK_OFF(2) + 0x18) -#define GPSR3 GPIO_REG(BANK_OFF(3) + 0x18) - -/* GPIO Pin Output Clear Registers */ -#define GPCR0 GPIO_REG(BANK_OFF(0) + 0x24) -#define GPCR1 GPIO_REG(BANK_OFF(1) + 0x24) -#define GPCR2 GPIO_REG(BANK_OFF(2) + 0x24) -#define GPCR3 GPIO_REG(BANK_OFF(3) + 0x24) - -/* GPIO Rising Edge Detect Registers */ -#define GRER0 GPIO_REG(BANK_OFF(0) + 0x30) -#define GRER1 GPIO_REG(BANK_OFF(1) + 0x30) -#define GRER2 GPIO_REG(BANK_OFF(2) + 0x30) -#define GRER3 GPIO_REG(BANK_OFF(3) + 0x30) - -/* GPIO Falling Edge Detect Registers */ -#define GFER0 GPIO_REG(BANK_OFF(0) + 0x3c) -#define GFER1 GPIO_REG(BANK_OFF(1) + 0x3c) -#define GFER2 GPIO_REG(BANK_OFF(2) + 0x3c) -#define GFER3 GPIO_REG(BANK_OFF(3) + 0x3c) - -/* GPIO Edge Detect Status Registers */ -#define GEDR0 GPIO_REG(BANK_OFF(0) + 0x48) -#define GEDR1 GPIO_REG(BANK_OFF(1) + 0x48) -#define GEDR2 GPIO_REG(BANK_OFF(2) + 0x48) -#define GEDR3 GPIO_REG(BANK_OFF(3) + 0x48) - -/* GPIO Alternate Function Select Registers */ -#define GAFR0_L GPIO_REG(0x0054) -#define GAFR0_U GPIO_REG(0x0058) -#define GAFR1_L GPIO_REG(0x005C) -#define GAFR1_U GPIO_REG(0x0060) -#define GAFR2_L GPIO_REG(0x0064) -#define GAFR2_U GPIO_REG(0x0068) -#define GAFR3_L GPIO_REG(0x006C) -#define GAFR3_U GPIO_REG(0x0070) - -/* More handy macros. The argument is a literal GPIO number. */ - -#define GPIO_bit(x) (1 << ((x) & 0x1f)) - -#define GPLR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x00) -#define GPDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x0c) -#define GPSR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x18) -#define GPCR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x24) -#define GRER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x30) -#define GFER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x3c) -#define GEDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x48) -#define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2)) - - -#define NR_BUILTIN_GPIO 128 - -#define gpio_to_bank(gpio) ((gpio) >> 5) -#define gpio_to_irq(gpio) IRQ_GPIO(gpio) -#define irq_to_gpio(irq) IRQ_TO_GPIO(irq) - -#ifdef CONFIG_CPU_PXA26x -/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, - * as well as their Alternate Function value being '1' for GPIO in GAFRx. - */ -static inline int __gpio_is_inverted(unsigned gpio) -{ - return cpu_is_pxa25x() && gpio > 85; -} -#else -static inline int __gpio_is_inverted(unsigned gpio) { return 0; } -#endif - -/* - * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate - * function of a GPIO, and GPDRx cannot be altered once configured. It - * is attributed as "occupied" here (I know this terminology isn't - * accurate, you are welcome to propose a better one :-) - */ -static inline int __gpio_is_occupied(unsigned gpio) -{ - if (cpu_is_pxa27x() || cpu_is_pxa25x()) { - int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3; - int dir = GPDR(gpio) & GPIO_bit(gpio); - - if (__gpio_is_inverted(gpio)) - return af != 1 || dir == 0; - else - return af != 0 || dir != 0; - } else - return GPDR(gpio) & GPIO_bit(gpio); -} - -#include <plat/gpio.h> -#endif diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h index 06abd416060..f7df27bbb42 100644 --- a/arch/arm/mach-pxa/include/mach/gumstix.h +++ b/arch/arm/mach-pxa/include/mach/gumstix.h @@ -6,6 +6,7 @@ * published by the Free Software Foundation. */ +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ /* BTRESET - Reset line to Bluetooth module, active low signal. */ #define GPIO_GUMSTIX_BTRESET 7 @@ -14,27 +15,17 @@ /* GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean -interrupt signal for determining cable presence. On the original gumstix, -this is GPIO81, and GPIO83 needs to be defined as well. On the gumstix F, +interrupt signal for determining cable presence. On the gumstix F, this moves to GPIO17 and GPIO37. */ /* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn has detected a cable insertion; driven low otherwise. */ -#ifdef CONFIG_ARCH_GUMSTIX_ORIG - -#define GPIO_GUMSTIX_USB_GPIOn 81 -#define GPIO_GUMSTIX_USB_GPIOx 83 - -#else - #define GPIO_GUMSTIX_USB_GPIOn 35 #define GPIO_GUMSTIX_USB_GPIOx 41 -#endif - /* usb state change */ -#define GUMSTIX_USB_INTR_IRQ IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn) +#define GUMSTIX_USB_INTR_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_USB_GPIOn) #define GPIO_GUMSTIX_USB_GPIOn_MD (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN) #define GPIO_GUMSTIX_USB_GPIOx_CON_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT) @@ -45,7 +36,7 @@ has detected a cable insertion; driven low otherwise. */ */ #define GUMSTIX_GPIO_nSD_WP 22 /* SD Write Protect */ #define GUMSTIX_GPIO_nSD_DETECT 11 /* MMC/SD Card Detect */ -#define GUMSTIX_IRQ_GPIO_nSD_DETECT IRQ_GPIO(GUMSTIX_GPIO_nSD_DETECT) +#define GUMSTIX_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(GUMSTIX_GPIO_nSD_DETECT) /* * SMC Ethernet definitions @@ -59,10 +50,10 @@ has detected a cable insertion; driven low otherwise. */ #define GPIO_GUMSTIX_ETH0 36 #define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN) -#define GUMSTIX_ETH0_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH0) +#define GUMSTIX_ETH0_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0) #define GPIO_GUMSTIX_ETH1 27 #define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN) -#define GUMSTIX_ETH1_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH1) +#define GUMSTIX_ETH1_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH1) /* CF reset line */ @@ -73,18 +64,18 @@ has detected a cable insertion; driven low otherwise. */ #define GPIO4_nSTSCHG GPIO4_nBVD1 #define GPIO11_nCD 11 #define GPIO26_PRDY_nBSY 26 -#define GUMSTIX_S0_nSTSCHG_IRQ IRQ_GPIO(GPIO4_nSTSCHG) -#define GUMSTIX_S0_nCD_IRQ IRQ_GPIO(GPIO11_nCD) -#define GUMSTIX_S0_PRDY_nBSY_IRQ IRQ_GPIO(GPIO26_PRDY_nBSY) +#define GUMSTIX_S0_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO4_nSTSCHG) +#define GUMSTIX_S0_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO11_nCD) +#define GUMSTIX_S0_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO26_PRDY_nBSY) /* CF slot 1 */ #define GPIO18_nBVD1 18 #define GPIO18_nSTSCHG GPIO18_nBVD1 #define GPIO36_nCD 36 #define GPIO27_PRDY_nBSY 27 -#define GUMSTIX_S1_nSTSCHG_IRQ IRQ_GPIO(GPIO18_nSTSCHG) -#define GUMSTIX_S1_nCD_IRQ IRQ_GPIO(GPIO36_nCD) -#define GUMSTIX_S1_PRDY_nBSY_IRQ IRQ_GPIO(GPIO27_PRDY_nBSY) +#define GUMSTIX_S1_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO18_nSTSCHG) +#define GUMSTIX_S1_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO36_nCD) +#define GUMSTIX_S1_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO27_PRDY_nBSY) /* CF GPIO line modes */ #define GPIO4_nSTSCHG_MD (GPIO4_nSTSCHG | GPIO_IN) diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index 16ab79547da..ccb06e48552 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h @@ -13,10 +13,7 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H -/* - * We requires absolute addresses. - */ -#define PCIO_BASE 0 +#include <mach/addr-map.h> /* * Workarounds for at least 2 errata so far require this. @@ -39,17 +36,16 @@ * Note that not all PXA2xx chips implement all those addresses, and the * kernel only maps the minimum needed range of this mapping. */ -#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1)) +#define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) #ifndef __ASSEMBLY__ - -# define __REG(x) (*((volatile u32 *)io_p2v(x))) +# define __REG(x) (*((volatile u32 __iomem *)io_p2v(x))) /* With indexed regs we don't want to feed the index through io_p2v() especially if it is a variable, otherwise horrible code will result. */ # define __REG2(x,y) \ - (*(volatile u32 *)((u32)&__REG(x) + (y))) + (*(volatile u32 __iomem*)((u32)&__REG(x) + (y))) # define __PREG(x) (io_v2p((u32)&(x))) @@ -105,6 +101,7 @@ * * PXA935 A0 0x56056931 0x1E653013 * PXA935 B0 0x56056936 0x6E653013 + * PXA935 B1 0x56056938 0x8E653013 */ #ifdef CONFIG_PXA25x #define __cpu_is_pxa210(id) \ @@ -239,38 +236,51 @@ #define cpu_is_pxa930() \ ({ \ - unsigned int id = read_cpuid(CPUID_ID); \ - __cpu_is_pxa930(id); \ + __cpu_is_pxa930(read_cpuid_id()); \ }) #define cpu_is_pxa935() \ ({ \ - unsigned int id = read_cpuid(CPUID_ID); \ - __cpu_is_pxa935(id); \ + __cpu_is_pxa935(read_cpuid_id()); \ }) + + /* * CPUID Core Generation Bit * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x - * == 0x3 for pxa300/pxa310/pxa320 */ +#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) #define __cpu_is_pxa2xx(id) \ ({ \ unsigned int _id = (id) >> 13 & 0x7; \ _id <= 0x2; \ }) +#else +#define __cpu_is_pxa2xx(id) (0) +#endif +#ifdef CONFIG_PXA3xx #define __cpu_is_pxa3xx(id) \ ({ \ - unsigned int _id = (id) >> 13 & 0x7; \ - _id == 0x3; \ + __cpu_is_pxa300(id) \ + || __cpu_is_pxa310(id) \ + || __cpu_is_pxa320(id) \ + || __cpu_is_pxa93x(id); \ }) +#else +#define __cpu_is_pxa3xx(id) (0) +#endif -#define __cpu_is_pxa9xx(id) \ +#if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935) +#define __cpu_is_pxa93x(id) \ ({ \ - unsigned int _id = (id) >> 4 & 0xfff; \ - _id == 0x683 || _id == 0x693; \ + __cpu_is_pxa930(id) \ + || __cpu_is_pxa935(id); \ }) +#else +#define __cpu_is_pxa93x(id) (0) +#endif #define cpu_is_pxa2xx() \ ({ \ @@ -282,10 +292,12 @@ __cpu_is_pxa3xx(read_cpuid_id()); \ }) -#define cpu_is_pxa9xx() \ +#define cpu_is_pxa93x() \ ({ \ - __cpu_is_pxa9xx(read_cpuid_id()); \ + __cpu_is_pxa93x(read_cpuid_id()); \ }) + + /* * return current memory and LCD clock frequency in units of 10kHz */ @@ -295,12 +307,4 @@ extern unsigned int get_memclk_frequency_10khz(void); extern unsigned long get_clock_tick_rate(void); #endif -#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) -#define PCIBIOS_MIN_IO 0 -#define PCIBIOS_MIN_MEM 0 -#define pcibios_assign_all_busses() 1 -#define HAVE_ARCH_PCI_SET_DMA_MASK 1 -#endif - - #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-pxa/include/mach/hx4700.h b/arch/arm/mach-pxa/include/mach/hx4700.h new file mode 100644 index 00000000000..0e1bb46264f --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/hx4700.h @@ -0,0 +1,133 @@ +/* + * GPIO and IRQ definitions for HP iPAQ hx4700 + * + * Copyright (c) 2008 Philipp Zabel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _HX4700_H_ +#define _HX4700_H_ + +#include <linux/gpio.h> +#include <linux/mfd/asic3.h> +#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ + +#define HX4700_ASIC3_GPIO_BASE PXA_NR_BUILTIN_GPIO +#define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS) +#define HX4700_NR_IRQS (IRQ_BOARD_START + 70) + +/* + * PXA GPIOs + */ + +#define GPIO0_HX4700_nKEY_POWER 0 +#define GPIO12_HX4700_ASIC3_IRQ 12 +#define GPIO13_HX4700_W3220_IRQ 13 +#define GPIO14_HX4700_nWLAN_IRQ 14 +#define GPIO18_HX4700_RDY 18 +#define GPIO22_HX4700_LCD_RL 22 +#define GPIO27_HX4700_CODEC_ON 27 +#define GPIO32_HX4700_RS232_ON 32 +#define GPIO52_HX4700_CPU_nBATT_FAULT 52 +#define GPIO58_HX4700_TSC2046_nPENIRQ 58 +#define GPIO59_HX4700_LCD_PC1 59 +#define GPIO60_HX4700_CF_RNB 60 +#define GPIO61_HX4700_W3220_nRESET 61 +#define GPIO62_HX4700_LCD_nRESET 62 +#define GPIO63_HX4700_CPU_SS_nRESET 63 +#define GPIO65_HX4700_TSC2046_PEN_PU 65 +#define GPIO66_HX4700_ASIC3_nSDIO_IRQ 66 +#define GPIO67_HX4700_EUART_PS 67 +#define GPIO70_HX4700_LCD_SLIN1 70 +#define GPIO71_HX4700_ASIC3_nRESET 71 +#define GPIO72_HX4700_BQ24022_nCHARGE_EN 72 +#define GPIO73_HX4700_LCD_UD_1 73 +#define GPIO75_HX4700_EARPHONE_nDET 75 +#define GPIO76_HX4700_USBC_PUEN 76 +#define GPIO81_HX4700_CPU_GP_nRESET 81 +#define GPIO82_HX4700_EUART_RESET 82 +#define GPIO83_HX4700_WLAN_nRESET 83 +#define GPIO84_HX4700_LCD_SQN 84 +#define GPIO85_HX4700_nPCE1 85 +#define GPIO88_HX4700_TSC2046_CS 88 +#define GPIO91_HX4700_FLASH_VPEN 91 +#define GPIO92_HX4700_HP_DRIVER 92 +#define GPIO93_HX4700_EUART_INT 93 +#define GPIO94_HX4700_KEY_MAIL 94 +#define GPIO95_HX4700_BATT_OFF 95 +#define GPIO96_HX4700_BQ24022_ISET2 96 +#define GPIO97_HX4700_nBL_DETECT 97 +#define GPIO99_HX4700_KEY_CONTACTS 99 +#define GPIO100_HX4700_AUTO_SENSE 100 /* BL auto brightness */ +#define GPIO102_HX4700_SYNAPTICS_POWER_ON 102 +#define GPIO103_HX4700_SYNAPTICS_INT 103 +#define GPIO105_HX4700_nIR_ON 105 +#define GPIO106_HX4700_CPU_BT_nRESET 106 +#define GPIO107_HX4700_SPK_nSD 107 +#define GPIO109_HX4700_CODEC_nPDN 109 +#define GPIO110_HX4700_LCD_LVDD_3V3_ON 110 +#define GPIO111_HX4700_LCD_AVDD_3V3_ON 111 +#define GPIO112_HX4700_LCD_N2V7_7V3_ON 112 +#define GPIO114_HX4700_CF_RESET 114 +#define GPIO116_HX4700_CPU_HW_nRESET 116 + +/* + * ASIC3 GPIOs + */ + +#define GPIOC_BASE (HX4700_ASIC3_GPIO_BASE + 32) +#define GPIOD_BASE (HX4700_ASIC3_GPIO_BASE + 48) + +#define GPIOC0_LED_RED (GPIOC_BASE + 0) +#define GPIOC1_LED_GREEN (GPIOC_BASE + 1) +#define GPIOC2_LED_BLUE (GPIOC_BASE + 2) +#define GPIOC3_nSD_CS (GPIOC_BASE + 3) +#define GPIOC4_CF_nCD (GPIOC_BASE + 4) /* Input */ +#define GPIOC5_nCIOW (GPIOC_BASE + 5) /* Output, to CF */ +#define GPIOC6_nCIOR (GPIOC_BASE + 6) /* Output, to CF */ +#define GPIOC7_nPCE1 (GPIOC_BASE + 7) /* Input, from CPU */ +#define GPIOC8_nPCE2 (GPIOC_BASE + 8) /* Input, from CPU */ +#define GPIOC9_nPOE (GPIOC_BASE + 9) /* Input, from CPU */ +#define GPIOC10_CF_nPWE (GPIOC_BASE + 10) /* Input */ +#define GPIOC11_PSKTSEL (GPIOC_BASE + 11) /* Input, from CPU */ +#define GPIOC12_nPREG (GPIOC_BASE + 12) /* Input, from CPU */ +#define GPIOC13_nPWAIT (GPIOC_BASE + 13) /* Output, to CPU */ +#define GPIOC14_nPIOIS16 (GPIOC_BASE + 14) /* Output, to CPU */ +#define GPIOC15_nPIOR (GPIOC_BASE + 15) /* Input, from CPU */ + +#define GPIOD0_CPU_SS_INT (GPIOD_BASE + 0) /* Input */ +#define GPIOD1_nKEY_CALENDAR (GPIOD_BASE + 1) +#define GPIOD2_BLUETOOTH_WAKEUP (GPIOD_BASE + 2) +#define GPIOD3_nKEY_HOME (GPIOD_BASE + 3) +#define GPIOD4_CF_nCD (GPIOD_BASE + 4) /* Input, from CF */ +#define GPIOD5_nPIO (GPIOD_BASE + 5) /* Input */ +#define GPIOD6_nKEY_RECORD (GPIOD_BASE + 6) +#define GPIOD7_nSDIO_DETECT (GPIOD_BASE + 7) +#define GPIOD8_COM_DCD (GPIOD_BASE + 8) /* Input */ +#define GPIOD9_nAC_IN (GPIOD_BASE + 9) +#define GPIOD10_nSDIO_IRQ (GPIOD_BASE + 10) /* Input */ +#define GPIOD11_nCIOIS16 (GPIOD_BASE + 11) /* Input, from CF */ +#define GPIOD12_nCWAIT (GPIOD_BASE + 12) /* Input, from CF */ +#define GPIOD13_CF_RNB (GPIOD_BASE + 13) /* Input */ +#define GPIOD14_nUSBC_DETECT (GPIOD_BASE + 14) +#define GPIOD15_nPIOW (GPIOD_BASE + 15) /* Input, from CPU */ + +/* + * EGPIOs + */ + +#define EGPIO0_VCC_3V3_EN (HX4700_EGPIO_BASE + 0) /* WLAN support chip */ +#define EGPIO1_WL_VREG_EN (HX4700_EGPIO_BASE + 1) /* WLAN power */ +#define EGPIO2_VCC_2V1_WL_EN (HX4700_EGPIO_BASE + 2) /* unused */ +#define EGPIO3_SS_PWR_ON (HX4700_EGPIO_BASE + 3) /* smart slot power */ +#define EGPIO4_CF_3V3_ON (HX4700_EGPIO_BASE + 4) /* CF 3.3V enable */ +#define EGPIO5_BT_3V3_ON (HX4700_EGPIO_BASE + 5) /* BT 3.3V enable */ +#define EGPIO6_WL1V8_EN (HX4700_EGPIO_BASE + 6) /* WLAN 1.8V enable */ +#define EGPIO7_VCC_3V3_WL_EN (HX4700_EGPIO_BASE + 7) /* WLAN 3.3V enable */ +#define EGPIO8_USB_3V3_ON (HX4700_EGPIO_BASE + 8) /* unused */ + +#endif /* _HX4700_H_ */ diff --git a/arch/arm/mach-pxa/include/mach/i2c.h b/arch/arm/mach-pxa/include/mach/i2c.h deleted file mode 100644 index 1a9f65e6ec0..00000000000 --- a/arch/arm/mach-pxa/include/mach/i2c.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * i2c_pxa.h - * - * Copyright (C) 2002 Intrinsyc Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#ifndef _I2C_PXA_H_ -#define _I2C_PXA_H_ - -#if 0 -#define DEF_TIMEOUT 3 -#else -/* need a longer timeout if we're dealing with the fact we may well be - * looking at a multi-master environment -*/ -#define DEF_TIMEOUT 32 -#endif - -#define BUS_ERROR (-EREMOTEIO) -#define XFER_NAKED (-ECONNREFUSED) -#define I2C_RETRY (-2000) /* an error has occurred retry transmit */ - -/* ICR initialize bit values -* -* 15. FM 0 (100 Khz operation) -* 14. UR 0 (No unit reset) -* 13. SADIE 0 (Disables the unit from interrupting on slave addresses -* matching its slave address) -* 12. ALDIE 0 (Disables the unit from interrupt when it loses arbitration -* in master mode) -* 11. SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode) -* 10. BEIE 1 (Enable interrupts from detected bus errors, no ACK sent) -* 9. IRFIE 1 (Enable interrupts from full buffer received) -* 8. ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty) -* 7. GCD 1 (Disables i2c unit response to general call messages as a slave) -* 6. IUE 0 (Disable unit until we change settings) -* 5. SCLE 1 (Enables the i2c clock output for master mode (drives SCL) -* 4. MA 0 (Only send stop with the ICR stop bit) -* 3. TB 0 (We are not transmitting a byte initially) -* 2. ACKNAK 0 (Send an ACK after the unit receives a byte) -* 1. STOP 0 (Do not send a STOP) -* 0. START 0 (Do not send a START) -* -*/ -#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) - -/* I2C status register init values - * - * 10. BED 1 (Clear bus error detected) - * 9. SAD 1 (Clear slave address detected) - * 7. IRF 1 (Clear IDBR Receive Full) - * 6. ITE 1 (Clear IDBR Transmit Empty) - * 5. ALD 1 (Clear Arbitration Loss Detected) - * 4. SSD 1 (Clear Slave Stop Detected) - */ -#define I2C_ISR_INIT 0x7FF /* status register init */ - -struct i2c_slave_client; - -struct i2c_pxa_platform_data { - unsigned int slave_addr; - struct i2c_slave_client *slave; - unsigned int class; - unsigned int use_pio :1; - unsigned int fast_mode :1; -}; - -extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info); - -#ifdef CONFIG_PXA27x -extern void pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info); -#endif - -#ifdef CONFIG_PXA3xx -extern void pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info); -#endif - -#endif diff --git a/arch/arm/mach-pxa/include/mach/idp.h b/arch/arm/mach-pxa/include/mach/idp.h index 5eff96fcc94..7e63f468027 100644 --- a/arch/arm/mach-pxa/include/mach/idp.h +++ b/arch/arm/mach-pxa/include/mach/idp.h @@ -23,6 +23,7 @@ * IDP hardware. */ +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ #define IDP_FLASH_PHYS (PXA_CS0_PHYS) #define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS) @@ -131,28 +132,26 @@ #define PCC_VS2 (1 << 1) #define PCC_VS1 (1 << 0) -#define PCC_DETECT(x) (GPLR(7 + (x)) & GPIO_bit(7 + (x))) - /* A listing of interrupts used by external hardware devices */ -#define TOUCH_PANEL_IRQ IRQ_GPIO(5) -#define IDE_IRQ IRQ_GPIO(21) +#define TOUCH_PANEL_IRQ PXA_GPIO_TO_IRQ(5) +#define IDE_IRQ PXA_GPIO_TO_IRQ(21) #define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING -#define ETHERNET_IRQ IRQ_GPIO(4) +#define ETHERNET_IRQ PXA_GPIO_TO_IRQ(4) #define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING #define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING -#define PCMCIA_S0_CD_VALID IRQ_GPIO(7) +#define PCMCIA_S0_CD_VALID PXA_GPIO_TO_IRQ(7) #define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH -#define PCMCIA_S1_CD_VALID IRQ_GPIO(8) +#define PCMCIA_S1_CD_VALID PXA_GPIO_TO_IRQ(8) #define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH -#define PCMCIA_S0_RDYINT IRQ_GPIO(19) -#define PCMCIA_S1_RDYINT IRQ_GPIO(22) +#define PCMCIA_S0_RDYINT PXA_GPIO_TO_IRQ(19) +#define PCMCIA_S1_RDYINT PXA_GPIO_TO_IRQ(22) /* diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h index 262691fb97d..cd78b7fe356 100644 --- a/arch/arm/mach-pxa/include/mach/io.h +++ b/arch/arm/mach-pxa/include/mach/io.h @@ -13,6 +13,5 @@ * drivers out there that might just work if we fake them... */ #define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) #endif diff --git a/arch/arm/mach-pxa/include/mach/irda.h b/arch/arm/mach-pxa/include/mach/irda.h deleted file mode 100644 index 0a50c3c763d..00000000000 --- a/arch/arm/mach-pxa/include/mach/irda.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef ASMARM_ARCH_IRDA_H -#define ASMARM_ARCH_IRDA_H - -/* board specific transceiver capabilities */ - -#define IR_OFF 1 -#define IR_SIRMODE 2 -#define IR_FIRMODE 4 - -struct pxaficp_platform_data { - int transceiver_cap; - void (*transceiver_mode)(struct device *dev, int mode); - int (*startup)(struct device *dev); - void (*shutdown)(struct device *dev); -}; - -extern void pxa_set_ficp_info(struct pxaficp_platform_data *info); - -#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) -void pxa2xx_transceiver_mode(struct device *dev, int mode); -#endif - -#endif diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index 32bb4a2eb7f..48c2fd85168 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h @@ -21,16 +21,14 @@ #define PXA_IRQ(x) (PXA_ISA_IRQ_NUM + (x)) -#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) #define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ #define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ -#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */ -#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI) */ +#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI,PXA27x) */ +#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */ #define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ -#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */ +#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt (PXA27x) */ +#define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */ #define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ -#endif - #define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ #define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ #define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ @@ -38,7 +36,8 @@ #define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */ #define IRQ_USB PXA_IRQ(11) /* USB Service */ #define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */ -#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt */ +#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt (PXA27x) */ +#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request (PXA3xx) */ #define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */ #define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */ #define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */ @@ -47,6 +46,7 @@ #define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */ #define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */ #define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */ +#define IRQ_ACIPC2 PXA_IRQ(19) /* AP-CP Communication (PXA930) */ #define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */ #define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */ #define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/ @@ -60,18 +60,17 @@ #define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */ #define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */ -#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) #define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ #define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ -#endif - -#ifdef CONFIG_PXA3xx -#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request */ #define IRQ_CIR PXA_IRQ(34) /* Consumer IR */ +#define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */ #define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */ +#define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */ #define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */ -#define IRQ_GRPHICS PXA_IRQ(39) /* Graphics Controller */ +#define IRQ_GCU PXA_IRQ(39) /* Graphics Controller (PXA3xx) */ +#define IRQ_ACIPC1 PXA_IRQ(40) /* AP-CP Communication (PXA930) */ #define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */ +#define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball (PXA930) */ #define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */ #define IRQ_NAND PXA_IRQ(45) /* NAND Controller */ #define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */ @@ -79,191 +78,39 @@ #define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */ #define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */ #define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */ -#endif - -#define PXA_GPIO_IRQ_BASE PXA_IRQ(64) -#define PXA_GPIO_IRQ_NUM (128) -#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) -#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x)) +#define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */ +#define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */ +#define IRQ_PXA935_MMC0 PXA_IRQ(72) /* MMC0 Controller (PXA935) */ +#define IRQ_PXA935_MMC1 PXA_IRQ(73) /* MMC1 Controller (PXA935) */ +#define IRQ_PXA935_MMC2 PXA_IRQ(74) /* MMC2 Controller (PXA935) */ +#define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */ -#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE) -#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) +#define PXA_GPIO_IRQ_BASE PXA_IRQ(96) +#define PXA_NR_BUILTIN_GPIO (192) +#define PXA_GPIO_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) /* - * The next 16 interrupts are for board specific purposes. Since + * The following interrupts are for board specific purposes. Since * the kernel can only run on one machine at a time, we can re-use - * these. If you need more, increase IRQ_BOARD_END, but keep it - * within sensible limits. + * these. + * By default, no board IRQ is reserved. It should be finished in + * custom board since sparse IRQ is already enabled. */ -#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM) -#define IRQ_BOARD_END (IRQ_BOARD_START + 16) +#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_NR_BUILTIN_GPIO) -#define IRQ_SA1111_START (IRQ_BOARD_END) -#define IRQ_GPAIN0 (IRQ_BOARD_END + 0) -#define IRQ_GPAIN1 (IRQ_BOARD_END + 1) -#define IRQ_GPAIN2 (IRQ_BOARD_END + 2) -#define IRQ_GPAIN3 (IRQ_BOARD_END + 3) -#define IRQ_GPBIN0 (IRQ_BOARD_END + 4) -#define IRQ_GPBIN1 (IRQ_BOARD_END + 5) -#define IRQ_GPBIN2 (IRQ_BOARD_END + 6) -#define IRQ_GPBIN3 (IRQ_BOARD_END + 7) -#define IRQ_GPBIN4 (IRQ_BOARD_END + 8) -#define IRQ_GPBIN5 (IRQ_BOARD_END + 9) -#define IRQ_GPCIN0 (IRQ_BOARD_END + 10) -#define IRQ_GPCIN1 (IRQ_BOARD_END + 11) -#define IRQ_GPCIN2 (IRQ_BOARD_END + 12) -#define IRQ_GPCIN3 (IRQ_BOARD_END + 13) -#define IRQ_GPCIN4 (IRQ_BOARD_END + 14) -#define IRQ_GPCIN5 (IRQ_BOARD_END + 15) -#define IRQ_GPCIN6 (IRQ_BOARD_END + 16) -#define IRQ_GPCIN7 (IRQ_BOARD_END + 17) -#define IRQ_MSTXINT (IRQ_BOARD_END + 18) -#define IRQ_MSRXINT (IRQ_BOARD_END + 19) -#define IRQ_MSSTOPERRINT (IRQ_BOARD_END + 20) -#define IRQ_TPTXINT (IRQ_BOARD_END + 21) -#define IRQ_TPRXINT (IRQ_BOARD_END + 22) -#define IRQ_TPSTOPERRINT (IRQ_BOARD_END + 23) -#define SSPXMTINT (IRQ_BOARD_END + 24) -#define SSPRCVINT (IRQ_BOARD_END + 25) -#define SSPROR (IRQ_BOARD_END + 26) -#define AUDXMTDMADONEA (IRQ_BOARD_END + 32) -#define AUDRCVDMADONEA (IRQ_BOARD_END + 33) -#define AUDXMTDMADONEB (IRQ_BOARD_END + 34) -#define AUDRCVDMADONEB (IRQ_BOARD_END + 35) -#define AUDTFSR (IRQ_BOARD_END + 36) -#define AUDRFSR (IRQ_BOARD_END + 37) -#define AUDTUR (IRQ_BOARD_END + 38) -#define AUDROR (IRQ_BOARD_END + 39) -#define AUDDTS (IRQ_BOARD_END + 40) -#define AUDRDD (IRQ_BOARD_END + 41) -#define AUDSTO (IRQ_BOARD_END + 42) -#define IRQ_USBPWR (IRQ_BOARD_END + 43) -#define IRQ_HCIM (IRQ_BOARD_END + 44) -#define IRQ_HCIBUFFACC (IRQ_BOARD_END + 45) -#define IRQ_HCIRMTWKP (IRQ_BOARD_END + 46) -#define IRQ_NHCIMFCIR (IRQ_BOARD_END + 47) -#define IRQ_USB_PORT_RESUME (IRQ_BOARD_END + 48) -#define IRQ_S0_READY_NINT (IRQ_BOARD_END + 49) -#define IRQ_S1_READY_NINT (IRQ_BOARD_END + 50) -#define IRQ_S0_CD_VALID (IRQ_BOARD_END + 51) -#define IRQ_S1_CD_VALID (IRQ_BOARD_END + 52) -#define IRQ_S0_BVD1_STSCHG (IRQ_BOARD_END + 53) -#define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54) +#define PXA_NR_IRQS (IRQ_BOARD_START) -#define IRQ_LOCOMO_START (IRQ_BOARD_END) -#define IRQ_LOCOMO_KEY (IRQ_BOARD_END + 0) -#define IRQ_LOCOMO_GPIO0 (IRQ_BOARD_END + 1) -#define IRQ_LOCOMO_GPIO1 (IRQ_BOARD_END + 2) -#define IRQ_LOCOMO_GPIO2 (IRQ_BOARD_END + 3) -#define IRQ_LOCOMO_GPIO3 (IRQ_BOARD_END + 4) -#define IRQ_LOCOMO_GPIO4 (IRQ_BOARD_END + 5) -#define IRQ_LOCOMO_GPIO5 (IRQ_BOARD_END + 6) -#define IRQ_LOCOMO_GPIO6 (IRQ_BOARD_END + 7) -#define IRQ_LOCOMO_GPIO7 (IRQ_BOARD_END + 8) -#define IRQ_LOCOMO_GPIO8 (IRQ_BOARD_END + 9) -#define IRQ_LOCOMO_GPIO9 (IRQ_BOARD_END + 10) -#define IRQ_LOCOMO_GPIO10 (IRQ_BOARD_END + 11) -#define IRQ_LOCOMO_GPIO11 (IRQ_BOARD_END + 12) -#define IRQ_LOCOMO_GPIO12 (IRQ_BOARD_END + 13) -#define IRQ_LOCOMO_GPIO13 (IRQ_BOARD_END + 14) -#define IRQ_LOCOMO_GPIO14 (IRQ_BOARD_END + 15) -#define IRQ_LOCOMO_GPIO15 (IRQ_BOARD_END + 16) -#define IRQ_LOCOMO_LT (IRQ_BOARD_END + 17) -#define IRQ_LOCOMO_SPI_RFR (IRQ_BOARD_END + 18) -#define IRQ_LOCOMO_SPI_RFW (IRQ_BOARD_END + 19) -#define IRQ_LOCOMO_SPI_OVRN (IRQ_BOARD_END + 20) -#define IRQ_LOCOMO_SPI_TEND (IRQ_BOARD_END + 21) +#ifndef __ASSEMBLY__ +struct irq_data; +struct pt_regs; -/* - * Figure out the MAX IRQ number. - * - * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1. - * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1 - * Otherwise, we have the standard IRQs only. - */ -#ifdef CONFIG_SA1111 -#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1) -#elif defined(CONFIG_SHARP_LOCOMO) -#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) -#elif defined(CONFIG_PXA_HAVE_BOARD_IRQS) -#define NR_IRQS (IRQ_BOARD_END) -#elif defined(CONFIG_MACH_ZYLONITE) -#define NR_IRQS (IRQ_BOARD_START + 32) -#else -#define NR_IRQS (IRQ_BOARD_START) -#endif +void pxa_mask_irq(struct irq_data *); +void pxa_unmask_irq(struct irq_data *); +void icip_handle_irq(struct pt_regs *); +void ichp_handle_irq(struct pt_regs *); -/* - * Board specific IRQs. Define them here. - * Do not surround them with ifdefs. - */ -#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x)) -#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0) -#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1) -#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */ -#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3) -#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4) -#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5) -#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ -#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) - -#define LPD270_IRQ(x) (IRQ_BOARD_START + (x)) -#define LPD270_USBC_IRQ LPD270_IRQ(2) -#define LPD270_ETHERNET_IRQ LPD270_IRQ(3) -#define LPD270_AC97_IRQ LPD270_IRQ(4) - -#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x)) -#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) -#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) -#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2) -#define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3) -#define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4) -#define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5) -#define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6) -#define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7) -#define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9) -#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10) -#define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11) -#define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13) -#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) -#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) - -/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */ -#define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0) -#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1) -#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) -#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) - -/* phyCORE-PXA270 (PCM027) Interrupts */ -#define PCM027_IRQ(x) (IRQ_BOARD_START + (x)) -#define PCM027_BTDET_IRQ PCM027_IRQ(0) -#define PCM027_FF_RI_IRQ PCM027_IRQ(1) -#define PCM027_MMCDET_IRQ PCM027_IRQ(2) -#define PCM027_PM_5V_IRQ PCM027_IRQ(3) - -/* ITE8152 irqs */ -/* add IT8152 IRQs beyond BOARD_END */ -#ifdef CONFIG_PCI_HOST_ITE8152 -#define IT8152_IRQ(x) (IRQ_BOARD_END + (x)) - -/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */ -#define IT8152_LD_IRQ_COUNT 9 -#define IT8152_LP_IRQ_COUNT 16 -#define IT8152_PD_IRQ_COUNT 15 - -/* Priorities: */ -#define IT8152_PD_IRQ(i) IT8152_IRQ(i) -#define IT8152_LP_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT) -#define IT8152_LD_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT) - -#define IT8152_LAST_IRQ IT8152_LD_IRQ(IT8152_LD_IRQ_COUNT - 1) - -#if NR_IRQS < (IT8152_LAST_IRQ+1) -#undef NR_IRQS -#define NR_IRQS (IT8152_LAST_IRQ+1) +void pxa_init_irq(int irq_nr, int (*set_wake)(struct irq_data *, unsigned int)); #endif -#endif /* CONFIG_PCI_HOST_ITE8152 */ - #endif /* __ASM_MACH_IRQS_H */ diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h index 6c9b21c5132..8066be54e9f 100644 --- a/arch/arm/mach-pxa/include/mach/littleton.h +++ b/arch/arm/mach-pxa/include/mach/littleton.h @@ -1,13 +1,13 @@ #ifndef __ASM_ARCH_LITTLETON_H #define __ASM_ARCH_LITTLETON_H -#include <mach/gpio.h> - #define LITTLETON_ETH_PHYS 0x30000000 #define LITTLETON_GPIO_LCD_CS (17) -#define EXT0_GPIO_BASE (NR_BUILTIN_GPIO) +#define EXT0_GPIO_BASE (PXA_NR_BUILTIN_GPIO) #define EXT0_GPIO(x) (EXT0_GPIO_BASE + (x)) +#define LITTLETON_NR_IRQS (IRQ_BOARD_START + 8) + #endif /* __ASM_ARCH_LITTLETON_H */ diff --git a/arch/arm/mach-pxa/include/mach/lpd270.h b/arch/arm/mach-pxa/include/mach/lpd270.h index f89fb715266..4edc712a2de 100644 --- a/arch/arm/mach-pxa/include/mach/lpd270.h +++ b/arch/arm/mach-pxa/include/mach/lpd270.h @@ -13,13 +13,13 @@ #define __ASM_ARCH_LPD270_H #define LPD270_CPLD_PHYS PXA_CS2_PHYS -#define LPD270_CPLD_VIRT 0xf0000000 +#define LPD270_CPLD_VIRT IOMEM(0xf0000000) #define LPD270_CPLD_SIZE 0x00100000 #define LPD270_ETH_PHYS (PXA_CS2_PHYS + 0x01000000) /* CPLD registers */ -#define LPD270_CPLD_REG(x) ((unsigned long)(LPD270_CPLD_VIRT + (x))) +#define LPD270_CPLD_REG(x) (LPD270_CPLD_VIRT + (x)) #define LPD270_CONTROL LPD270_CPLD_REG(0x00) #define LPD270_PERIPHERAL0 LPD270_CPLD_REG(0x04) #define LPD270_PERIPHERAL1 LPD270_CPLD_REG(0x08) @@ -34,5 +34,10 @@ #define LPD270_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ #define LPD270_INT_USBC (1 << 2) /* USB client cable detection IRQ */ +#define LPD270_IRQ(x) (IRQ_BOARD_START + (x)) +#define LPD270_USBC_IRQ LPD270_IRQ(2) +#define LPD270_ETHERNET_IRQ LPD270_IRQ(3) +#define LPD270_AC97_IRQ LPD270_IRQ(4) +#define LPD270_NR_IRQS (IRQ_BOARD_START + 5) #endif diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h index 751b74811d0..958cd6af938 100644 --- a/arch/arm/mach-pxa/include/mach/lubbock.h +++ b/arch/arm/mach-pxa/include/mach/lubbock.h @@ -10,6 +10,8 @@ * published by the Free Software Foundation. */ +#include <mach/irqs.h> + #define LUBBOCK_ETH_PHYS PXA_CS3_PHYS #define LUBBOCK_FPGA_PHYS PXA_CS2_PHYS @@ -34,6 +36,20 @@ #define LUB_IRQ_SET_CLR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0) #define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100) +/* Board specific IRQs */ +#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x)) +#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0) +#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1) +#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */ +#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3) +#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4) +#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5) +#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ +#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) + +#define LUBBOCK_SA1111_IRQ_BASE (IRQ_BOARD_START + 16) +#define LUBBOCK_NR_IRQS (IRQ_BOARD_START + 16 + 55) + #ifndef __ASSEMBLY__ extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set); #endif diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h index 20ef37d4a9a..ba6a6e1d29e 100644 --- a/arch/arm/mach-pxa/include/mach/magician.h +++ b/arch/arm/mach-pxa/include/mach/magician.h @@ -12,6 +12,7 @@ #ifndef _MAGICIAN_H_ #define _MAGICIAN_H_ +#include <linux/gpio.h> #include <mach/irqs.h> /* @@ -71,11 +72,13 @@ #define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2) #define IRQ_MAGICIAN_VBUS (IRQ_BOARD_START + 3) +#define MAGICIAN_NR_IRQS (IRQ_BOARD_START + 8) + /* * CPLD EGPIOs */ -#define MAGICIAN_EGPIO_BASE 0x80 /* GPIO_BOARD_START */ +#define MAGICIAN_EGPIO_BASE PXA_NR_BUILTIN_GPIO #define MAGICIAN_EGPIO(reg,bit) \ (MAGICIAN_EGPIO_BASE + 8*reg + bit) diff --git a/arch/arm/mach-pxa/include/mach/mainstone.h b/arch/arm/mach-pxa/include/mach/mainstone.h index 3461c4302ff..1bfc4e822a4 100644 --- a/arch/arm/mach-pxa/include/mach/mainstone.h +++ b/arch/arm/mach-pxa/include/mach/mainstone.h @@ -13,6 +13,8 @@ #ifndef ASM_ARCH_MAINSTONE_H #define ASM_ARCH_MAINSTONE_H +#include <mach/irqs.h> + #define MST_ETH_PHYS PXA_CS4_PHYS #define MST_FPGA_PHYS PXA_CS2_PHYS @@ -117,4 +119,23 @@ #define MST_PCMCIA_PWR_VCC_33 0x8 /* voltage VCC = 3.3V */ #define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */ +/* board specific IRQs */ +#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x)) +#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) +#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) +#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2) +#define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3) +#define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4) +#define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5) +#define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6) +#define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7) +#define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9) +#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10) +#define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11) +#define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13) +#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) +#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) + +#define MAINSTONE_NR_IRQS (IRQ_BOARD_START + 16) + #endif diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h deleted file mode 100644 index f626730ee42..00000000000 --- a/arch/arm/mach-pxa/include/mach/memory.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/memory.h - * - * Author: Nicolas Pitre - * Copyright: (C) 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* - * Physical DRAM offset. - */ -#define PHYS_OFFSET UL(0xa0000000) - -/* - * The nodes are matched with the physical SDRAM banks as follows: - * - * node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff - * node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff - * node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff - * node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff - * - * This needs a node mem size of 26 bits. - */ -#define NODE_MEM_SIZE_BITS 26 - -#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) -void cmx2xx_pci_adjust_zones(int node, unsigned long *size, - unsigned long *holes); - -#define arch_adjust_zones(node, size, holes) \ - cmx2xx_pci_adjust_zones(node, size, holes) - -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) -#endif - -#endif diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h index b13dc0269a6..cafadc33dfd 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h @@ -169,7 +169,6 @@ #define GPIO86_nSDCS2 MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH) #define GPIO87_nSDCS3 MFP_CFG_OUT(GPIO87, AF0, DRIVE_HIGH) #define GPIO88_RDnWR MFP_CFG_OUT(GPIO88, AF0, DRIVE_HIGH) -#define GPIO89_nACRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH) /* USB */ #define GPIO9_USB_RCV MFP_CFG_IN(GPIO9, AF1) @@ -186,6 +185,41 @@ #define GPIO30_ASSP_TXD MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW) #define GPIO31_ASSP_SFRM_IN MFP_CFG_IN(GPIO31, AF1) #define GPIO31_ASSP_SFRM_OUT MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW) -#endif + +/* AC97 */ +#define GPIO89_AC97_nRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH) +#endif /* CONFIG_CPU_PXA26x */ + +/* commonly used pin configurations */ +#define GPIOxx_LCD_16BPP \ + GPIO58_LCD_LDD_0, \ + GPIO59_LCD_LDD_1, \ + GPIO60_LCD_LDD_2, \ + GPIO61_LCD_LDD_3, \ + GPIO62_LCD_LDD_4, \ + GPIO63_LCD_LDD_5, \ + GPIO64_LCD_LDD_6, \ + GPIO65_LCD_LDD_7, \ + GPIO66_LCD_LDD_8, \ + GPIO67_LCD_LDD_9, \ + GPIO68_LCD_LDD_10, \ + GPIO69_LCD_LDD_11, \ + GPIO70_LCD_LDD_12, \ + GPIO71_LCD_LDD_13, \ + GPIO72_LCD_LDD_14, \ + GPIO73_LCD_LDD_15 + +#define GPIOxx_LCD_DSTN_16BPP \ + GPIOxx_LCD_16BPP, \ + GPIO74_LCD_FCLK, \ + GPIO75_LCD_LCLK, \ + GPIO76_LCD_PCLK + +#define GPIOxx_LCD_TFT_16BPP \ + GPIOxx_LCD_16BPP, \ + GPIO74_LCD_FCLK, \ + GPIO75_LCD_LCLK, \ + GPIO76_LCD_PCLK, \ + GPIO77_LCD_BIAS #endif /* __ASM_ARCH_MFP_PXA25X_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h index 6543c05f47e..b6132aa95dc 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h @@ -158,7 +158,9 @@ #define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1) #define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1) #define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH) +#define GPIO45_BTUART_RTS_LPM_LOW MFP_CFG_OUT(GPIO45, AF2, DRIVE_LOW) #define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH) +#define GPIO43_BTUART_TXD_LPM_LOW MFP_CFG_OUT(GPIO43, AF2, DRIVE_LOW) /* STUART */ #define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2) @@ -206,6 +208,7 @@ #define GPIO113_I2S_SYSCLK MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW) /* SSP 1 */ +#define GPIO23_SSP1_SCLK_IN MFP_CFG_IN(GPIO23, AF2) #define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW) #define GPIO29_SSP1_SCLK MFP_CFG_IN(GPIO29, AF3) #define GPIO27_SSP1_SYSCLK MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW) @@ -434,5 +437,35 @@ #define GPIO112_nMSINS MFP_CFG_IN(GPIO112, AF2) #define GPIO32_MSSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW) +/* commonly used pin configurations */ +#define GPIOxx_LCD_16BPP \ + GPIO58_LCD_LDD_0, \ + GPIO59_LCD_LDD_1, \ + GPIO60_LCD_LDD_2, \ + GPIO61_LCD_LDD_3, \ + GPIO62_LCD_LDD_4, \ + GPIO63_LCD_LDD_5, \ + GPIO64_LCD_LDD_6, \ + GPIO65_LCD_LDD_7, \ + GPIO66_LCD_LDD_8, \ + GPIO67_LCD_LDD_9, \ + GPIO68_LCD_LDD_10, \ + GPIO69_LCD_LDD_11, \ + GPIO70_LCD_LDD_12, \ + GPIO71_LCD_LDD_13, \ + GPIO72_LCD_LDD_14, \ + GPIO73_LCD_LDD_15 + +#define GPIOxx_LCD_TFT_16BPP \ + GPIOxx_LCD_16BPP, \ + GPIO74_LCD_FCLK, \ + GPIO75_LCD_LCLK, \ + GPIO76_LCD_PCLK, \ + GPIO77_LCD_BIAS + +/* these enable a work-around for a hw bug in pxa27x during ac97 warm reset */ +#define GPIO113_AC97_nRESET_GPIO_HIGH MFP_CFG_OUT(GPIO113, AF0, DEFAULT) +#define GPIO95_AC97_nRESET_GPIO_HIGH MFP_CFG_OUT(GPIO95, AF0, DEFAULT) + extern int keypad_set_wake(unsigned int on); #endif /* __ASM_ARCH_MFP_PXA27X_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h index 658b28ed129..cbf51ae8185 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h @@ -17,6 +17,7 @@ * * bit 23 - Input/Output (PXA2xx specific) * bit 24 - Wakeup Enable(PXA2xx specific) + * bit 25 - Keep Output (PXA2xx specific) */ #define MFP_DIR_IN (0x0 << 23) @@ -25,6 +26,14 @@ #define MFP_DIR(x) (((x) >> 23) & 0x1) #define MFP_LPM_CAN_WAKEUP (0x1 << 24) + +/* + * MFP_LPM_KEEP_OUTPUT must be specified for pins that need to + * retain their last output level (low or high). + * Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input. + */ +#define MFP_LPM_KEEP_OUTPUT (0x1 << 25) + #define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE) #define WAKEUP_ON_EDGE_FALL (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL) #define WAKEUP_ON_EDGE_BOTH (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH) diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h index ae8441192ef..4e1287070d2 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h @@ -71,10 +71,10 @@ #define GPIO46_CI_DD_7 MFP_CFG_DRV(GPIO46, AF0, DS04X) #define GPIO47_CI_DD_8 MFP_CFG_DRV(GPIO47, AF1, DS04X) #define GPIO48_CI_DD_9 MFP_CFG_DRV(GPIO48, AF1, DS04X) -#define GPIO52_CI_HSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X) -#define GPIO51_CI_VSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X) #define GPIO49_CI_MCLK MFP_CFG_DRV(GPIO49, AF0, DS04X) #define GPIO50_CI_PCLK MFP_CFG_DRV(GPIO50, AF0, DS04X) +#define GPIO51_CI_HSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X) +#define GPIO52_CI_VSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X) /* KEYPAD */ #define GPIO3_KP_DKIN_6 MFP_CFG_LPM(GPIO3, AF2, FLOAT) @@ -567,9 +567,9 @@ #define GPIO37_ULPI_DATA_OUT_7 MFP_CFG(GPIO37, AF3) #define GPIO33_ULPI_OTG_INTR MFP_CFG(GPIO33, AF1) -#define ULPI_DIR MFP_CFG_DRV(ULPI_DIR, MFP_AF0, MFP_DS01X) -#define ULPI_NXT MFP_CFG_DRV(ULPI_NXT, MFP_AF0, MFP_DS01X) -#define ULPI_STP MFP_CFG_DRV(ULPI_STP, MFP_AF0, MFP_DS01X) +#define ULPI_DIR MFP_CFG_DRV(ULPI_DIR, AF0, DS01X) +#define ULPI_NXT MFP_CFG_DRV(ULPI_NXT, AF0, DS01X) +#define ULPI_STP MFP_CFG_DRV(ULPI_STP, AF0, DS01X) #endif /* CONFIG_CPU_PXA310 */ #endif /* __ASM_ARCH_MFP_PXA300_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h index 07897e61d05..3ce4682eabb 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h @@ -283,6 +283,9 @@ #define GPIO41_UART1_TXD MFP_CFG_LPM(GPIO41, AF4, FLOAT) #define GPIO42_UART1_RXD MFP_CFG_LPM(GPIO42, AF4, FLOAT) #define GPIO42_UART1_TXD MFP_CFG_LPM(GPIO42, AF2, FLOAT) +#define GPIO75_UART1_RXD MFP_CFG_LPM(GPIO75, AF1, FLOAT) +#define GPIO76_UART1_RXD MFP_CFG_LPM(GPIO76, AF3, FLOAT) +#define GPIO76_UART1_TXD MFP_CFG_LPM(GPIO76, AF1, FLOAT) #define GPIO97_UART1_RXD MFP_CFG_LPM(GPIO97, AF1, FLOAT) #define GPIO97_UART1_TXD MFP_CFG_LPM(GPIO97, AF6, FLOAT) #define GPIO98_UART1_RXD MFP_CFG_LPM(GPIO98, AF6, FLOAT) @@ -291,6 +294,9 @@ #define GPIO43_UART1_RTS MFP_CFG_LPM(GPIO43, AF4, FLOAT) #define GPIO48_UART1_CTS MFP_CFG_LPM(GPIO48, AF4, FLOAT) #define GPIO48_UART1_RTS MFP_CFG_LPM(GPIO48, AF2, FLOAT) +#define GPIO77_UART1_CTS MFP_CFG_LPM(GPIO77, AF1, FLOAT) +#define GPIO82_UART1_RTS MFP_CFG_LPM(GPIO82, AF1, FLOAT) +#define GPIO82_UART1_CTS MFP_CFG_LPM(GPIO82, AF3, FLOAT) #define GPIO99_UART1_CTS MFP_CFG_LPM(GPIO99, AF1, FLOAT) #define GPIO99_UART1_RTS MFP_CFG_LPM(GPIO99, AF6, FLOAT) #define GPIO104_UART1_CTS MFP_CFG_LPM(GPIO104, AF6, FLOAT) @@ -299,13 +305,18 @@ #define GPIO45_UART1_DSR MFP_CFG_LPM(GPIO45, AF2, FLOAT) #define GPIO47_UART1_DTR MFP_CFG_LPM(GPIO47, AF2, FLOAT) #define GPIO47_UART1_DSR MFP_CFG_LPM(GPIO47, AF4, FLOAT) +#define GPIO79_UART1_DSR MFP_CFG_LPM(GPIO79, AF1, FLOAT) +#define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF1, FLOAT) +#define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF3, FLOAT) #define GPIO101_UART1_DTR MFP_CFG_LPM(GPIO101, AF6, FLOAT) #define GPIO101_UART1_DSR MFP_CFG_LPM(GPIO101, AF1, FLOAT) #define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF1, FLOAT) #define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF6, FLOAT) #define GPIO44_UART1_DCD MFP_CFG_LPM(GPIO44, AF2, FLOAT) +#define GPIO78_UART1_DCD MFP_CFG_LPM(GPIO78, AF1, FLOAT) #define GPIO100_UART1_DCD MFP_CFG_LPM(GPIO100, AF1, FLOAT) #define GPIO46_UART1_RI MFP_CFG_LPM(GPIO46, AF2, FLOAT) +#define GPIO80_UART1_RI MFP_CFG_LPM(GPIO80, AF1, FLOAT) #define GPIO102_UART1_RI MFP_CFG_LPM(GPIO102, AF1, FLOAT) /* UART2 */ @@ -438,6 +449,9 @@ #define GPIO2_RDY MFP_CFG(GPIO2, AF1) #define GPIO5_NPIOR MFP_CFG(GPIO5, AF3) +#define GPIO6_NPIOW MFP_CFG(GPIO6, AF3) +#define GPIO7_NPIOS16 MFP_CFG(GPIO7, AF3) +#define GPIO8_NPWAIT MFP_CFG(GPIO8, AF3) #define GPIO11_PWM0_OUT MFP_CFG(GPIO11, AF1) #define GPIO12_PWM1_OUT MFP_CFG(GPIO12, AF1) diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h index 0d119d3b922..04f7c97044f 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h @@ -69,6 +69,7 @@ #define nBE0_GPIO_60 MFP_CFG(nBE0, AF0) #define nBE1_GPIO_61 MFP_CFG(nBE1, AF0) #define RDY_GPIO_62 MFP_CFG(RDY, AF0) +#define PMIC_INT_GPIO83 MFP_CFG_LPM(PMIC_INT, AF0, PULL_HIGH) /* Chip Select */ #define DF_nCS0_nCS2 MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH) @@ -92,6 +93,9 @@ #define GPIO63_CI2C_SCL MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH) #define GPIO64_CI2C_SDA MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH) +#define GPIO73_CI2C_SCL MFP_CFG_LPM(GPIO73, AF1, PULL_HIGH) +#define GPIO74_CI2C_SDA MFP_CFG_LPM(GPIO74, AF1, PULL_HIGH) + #define GPIO77_CI2C_SCL MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH) #define GPIO78_CI2C_SDA MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH) @@ -345,6 +349,9 @@ #define GPIO69_UART1_CTS MFP_CFG(GPIO69, AF2) #define GPIO70_UART1_RTS MFP_CFG(GPIO70, AF2) +#define GPIO53_UART1_TXD MFP_CFG(GPIO53, AF2) +#define GPIO54_UART1_RXD MFP_CFG(GPIO54, AF2) + /* UART2 - BTUART */ #define GPIO91_UART2_RXD MFP_CFG(GPIO91, AF1) #define GPIO92_UART2_TXD MFP_CFG(GPIO92, AF1) diff --git a/arch/arm/mach-pxa/include/mach/mfp.h b/arch/arm/mach-pxa/include/mach/mfp.h index 482185053a9..271e249ae34 100644 --- a/arch/arm/mach-pxa/include/mach/mfp.h +++ b/arch/arm/mach-pxa/include/mach/mfp.h @@ -16,305 +16,6 @@ #ifndef __ASM_ARCH_MFP_H #define __ASM_ARCH_MFP_H -#define mfp_to_gpio(m) ((m) % 128) - -/* list of all the configurable MFP pins */ -enum { - MFP_PIN_INVALID = -1, - - MFP_PIN_GPIO0 = 0, - MFP_PIN_GPIO1, - MFP_PIN_GPIO2, - MFP_PIN_GPIO3, - MFP_PIN_GPIO4, - MFP_PIN_GPIO5, - MFP_PIN_GPIO6, - MFP_PIN_GPIO7, - MFP_PIN_GPIO8, - MFP_PIN_GPIO9, - MFP_PIN_GPIO10, - MFP_PIN_GPIO11, - MFP_PIN_GPIO12, - MFP_PIN_GPIO13, - MFP_PIN_GPIO14, - MFP_PIN_GPIO15, - MFP_PIN_GPIO16, - MFP_PIN_GPIO17, - MFP_PIN_GPIO18, - MFP_PIN_GPIO19, - MFP_PIN_GPIO20, - MFP_PIN_GPIO21, - MFP_PIN_GPIO22, - MFP_PIN_GPIO23, - MFP_PIN_GPIO24, - MFP_PIN_GPIO25, - MFP_PIN_GPIO26, - MFP_PIN_GPIO27, - MFP_PIN_GPIO28, - MFP_PIN_GPIO29, - MFP_PIN_GPIO30, - MFP_PIN_GPIO31, - MFP_PIN_GPIO32, - MFP_PIN_GPIO33, - MFP_PIN_GPIO34, - MFP_PIN_GPIO35, - MFP_PIN_GPIO36, - MFP_PIN_GPIO37, - MFP_PIN_GPIO38, - MFP_PIN_GPIO39, - MFP_PIN_GPIO40, - MFP_PIN_GPIO41, - MFP_PIN_GPIO42, - MFP_PIN_GPIO43, - MFP_PIN_GPIO44, - MFP_PIN_GPIO45, - MFP_PIN_GPIO46, - MFP_PIN_GPIO47, - MFP_PIN_GPIO48, - MFP_PIN_GPIO49, - MFP_PIN_GPIO50, - MFP_PIN_GPIO51, - MFP_PIN_GPIO52, - MFP_PIN_GPIO53, - MFP_PIN_GPIO54, - MFP_PIN_GPIO55, - MFP_PIN_GPIO56, - MFP_PIN_GPIO57, - MFP_PIN_GPIO58, - MFP_PIN_GPIO59, - MFP_PIN_GPIO60, - MFP_PIN_GPIO61, - MFP_PIN_GPIO62, - MFP_PIN_GPIO63, - MFP_PIN_GPIO64, - MFP_PIN_GPIO65, - MFP_PIN_GPIO66, - MFP_PIN_GPIO67, - MFP_PIN_GPIO68, - MFP_PIN_GPIO69, - MFP_PIN_GPIO70, - MFP_PIN_GPIO71, - MFP_PIN_GPIO72, - MFP_PIN_GPIO73, - MFP_PIN_GPIO74, - MFP_PIN_GPIO75, - MFP_PIN_GPIO76, - MFP_PIN_GPIO77, - MFP_PIN_GPIO78, - MFP_PIN_GPIO79, - MFP_PIN_GPIO80, - MFP_PIN_GPIO81, - MFP_PIN_GPIO82, - MFP_PIN_GPIO83, - MFP_PIN_GPIO84, - MFP_PIN_GPIO85, - MFP_PIN_GPIO86, - MFP_PIN_GPIO87, - MFP_PIN_GPIO88, - MFP_PIN_GPIO89, - MFP_PIN_GPIO90, - MFP_PIN_GPIO91, - MFP_PIN_GPIO92, - MFP_PIN_GPIO93, - MFP_PIN_GPIO94, - MFP_PIN_GPIO95, - MFP_PIN_GPIO96, - MFP_PIN_GPIO97, - MFP_PIN_GPIO98, - MFP_PIN_GPIO99, - MFP_PIN_GPIO100, - MFP_PIN_GPIO101, - MFP_PIN_GPIO102, - MFP_PIN_GPIO103, - MFP_PIN_GPIO104, - MFP_PIN_GPIO105, - MFP_PIN_GPIO106, - MFP_PIN_GPIO107, - MFP_PIN_GPIO108, - MFP_PIN_GPIO109, - MFP_PIN_GPIO110, - MFP_PIN_GPIO111, - MFP_PIN_GPIO112, - MFP_PIN_GPIO113, - MFP_PIN_GPIO114, - MFP_PIN_GPIO115, - MFP_PIN_GPIO116, - MFP_PIN_GPIO117, - MFP_PIN_GPIO118, - MFP_PIN_GPIO119, - MFP_PIN_GPIO120, - MFP_PIN_GPIO121, - MFP_PIN_GPIO122, - MFP_PIN_GPIO123, - MFP_PIN_GPIO124, - MFP_PIN_GPIO125, - MFP_PIN_GPIO126, - MFP_PIN_GPIO127, - MFP_PIN_GPIO0_2, - MFP_PIN_GPIO1_2, - MFP_PIN_GPIO2_2, - MFP_PIN_GPIO3_2, - MFP_PIN_GPIO4_2, - MFP_PIN_GPIO5_2, - MFP_PIN_GPIO6_2, - MFP_PIN_GPIO7_2, - MFP_PIN_GPIO8_2, - MFP_PIN_GPIO9_2, - MFP_PIN_GPIO10_2, - MFP_PIN_GPIO11_2, - MFP_PIN_GPIO12_2, - MFP_PIN_GPIO13_2, - MFP_PIN_GPIO14_2, - MFP_PIN_GPIO15_2, - MFP_PIN_GPIO16_2, - MFP_PIN_GPIO17_2, - - MFP_PIN_ULPI_STP, - MFP_PIN_ULPI_NXT, - MFP_PIN_ULPI_DIR, - - MFP_PIN_nXCVREN, - MFP_PIN_DF_CLE_nOE, - MFP_PIN_DF_nADV1_ALE, - MFP_PIN_DF_SCLK_E, - MFP_PIN_DF_SCLK_S, - MFP_PIN_nBE0, - MFP_PIN_nBE1, - MFP_PIN_DF_nADV2_ALE, - MFP_PIN_DF_INT_RnB, - MFP_PIN_DF_nCS0, - MFP_PIN_DF_nCS1, - MFP_PIN_nLUA, - MFP_PIN_nLLA, - MFP_PIN_DF_nWE, - MFP_PIN_DF_ALE_nWE, - MFP_PIN_DF_nRE_nOE, - MFP_PIN_DF_ADDR0, - MFP_PIN_DF_ADDR1, - MFP_PIN_DF_ADDR2, - MFP_PIN_DF_ADDR3, - MFP_PIN_DF_IO0, - MFP_PIN_DF_IO1, - MFP_PIN_DF_IO2, - MFP_PIN_DF_IO3, - MFP_PIN_DF_IO4, - MFP_PIN_DF_IO5, - MFP_PIN_DF_IO6, - MFP_PIN_DF_IO7, - MFP_PIN_DF_IO8, - MFP_PIN_DF_IO9, - MFP_PIN_DF_IO10, - MFP_PIN_DF_IO11, - MFP_PIN_DF_IO12, - MFP_PIN_DF_IO13, - MFP_PIN_DF_IO14, - MFP_PIN_DF_IO15, - - /* additional pins on PXA930 */ - MFP_PIN_GSIM_UIO, - MFP_PIN_GSIM_UCLK, - MFP_PIN_GSIM_UDET, - MFP_PIN_GSIM_nURST, - MFP_PIN_PMIC_INT, - MFP_PIN_RDY, - - MFP_PIN_MAX, -}; - -/* - * a possible MFP configuration is represented by a 32-bit integer - * - * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum) - * bit 10..12 - Alternate Function Selection - * bit 13..15 - Drive Strength - * bit 16..18 - Low Power Mode State - * bit 19..20 - Low Power Mode Edge Detection - * bit 21..22 - Run Mode Pull State - * - * to facilitate the definition, the following macros are provided - * - * MFP_CFG_DEFAULT - default MFP configuration value, with - * alternate function = 0, - * drive strength = fast 3mA (MFP_DS03X) - * low power mode = default - * edge detection = none - * - * MFP_CFG - default MFPR value with alternate function - * MFP_CFG_DRV - default MFPR value with alternate function and - * pin drive strength - * MFP_CFG_LPM - default MFPR value with alternate function and - * low power mode - * MFP_CFG_X - default MFPR value with alternate function, - * pin drive strength and low power mode - */ - -typedef unsigned long mfp_cfg_t; - -#define MFP_PIN(x) ((x) & 0x3ff) - -#define MFP_AF0 (0x0 << 10) -#define MFP_AF1 (0x1 << 10) -#define MFP_AF2 (0x2 << 10) -#define MFP_AF3 (0x3 << 10) -#define MFP_AF4 (0x4 << 10) -#define MFP_AF5 (0x5 << 10) -#define MFP_AF6 (0x6 << 10) -#define MFP_AF7 (0x7 << 10) -#define MFP_AF_MASK (0x7 << 10) -#define MFP_AF(x) (((x) >> 10) & 0x7) - -#define MFP_DS01X (0x0 << 13) -#define MFP_DS02X (0x1 << 13) -#define MFP_DS03X (0x2 << 13) -#define MFP_DS04X (0x3 << 13) -#define MFP_DS06X (0x4 << 13) -#define MFP_DS08X (0x5 << 13) -#define MFP_DS10X (0x6 << 13) -#define MFP_DS13X (0x7 << 13) -#define MFP_DS_MASK (0x7 << 13) -#define MFP_DS(x) (((x) >> 13) & 0x7) - -#define MFP_LPM_DEFAULT (0x0 << 16) -#define MFP_LPM_DRIVE_LOW (0x1 << 16) -#define MFP_LPM_DRIVE_HIGH (0x2 << 16) -#define MFP_LPM_PULL_LOW (0x3 << 16) -#define MFP_LPM_PULL_HIGH (0x4 << 16) -#define MFP_LPM_FLOAT (0x5 << 16) -#define MFP_LPM_INPUT (0x6 << 16) -#define MFP_LPM_STATE_MASK (0x7 << 16) -#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7) - -#define MFP_LPM_EDGE_NONE (0x0 << 19) -#define MFP_LPM_EDGE_RISE (0x1 << 19) -#define MFP_LPM_EDGE_FALL (0x2 << 19) -#define MFP_LPM_EDGE_BOTH (0x3 << 19) -#define MFP_LPM_EDGE_MASK (0x3 << 19) -#define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3) - -#define MFP_PULL_NONE (0x0 << 21) -#define MFP_PULL_LOW (0x1 << 21) -#define MFP_PULL_HIGH (0x2 << 21) -#define MFP_PULL_BOTH (0x3 << 21) -#define MFP_PULL_MASK (0x3 << 21) -#define MFP_PULL(x) (((x) >> 21) & 0x3) - -#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\ - MFP_LPM_EDGE_NONE | MFP_PULL_NONE) - -#define MFP_CFG(pin, af) \ - ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\ - (MFP_PIN(MFP_PIN_##pin) | MFP_##af)) - -#define MFP_CFG_DRV(pin, af, drv) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\ - (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv)) - -#define MFP_CFG_LPM(pin, af, lpm) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\ - (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm)) - -#define MFP_CFG_X(pin, af, drv, lpm) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\ - (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm)) +#include <plat/mfp.h> #endif /* __ASM_ARCH_MFP_H */ diff --git a/arch/arm/mach-pxa/include/mach/mioa701.h b/arch/arm/mach-pxa/include/mach/mioa701.h index 02868447b0b..e57f5c724e8 100644 --- a/arch/arm/mach-pxa/include/mach/mioa701.h +++ b/arch/arm/mach-pxa/include/mach/mioa701.h @@ -61,6 +61,9 @@ #define GPIO93_KEY_VOLUME_UP 93 #define GPIO94_KEY_VOLUME_DOWN 94 +/* Camera */ +#define GPIO56_MT9M111_nOE 56 + extern struct input_dev *mioa701_evdev; extern void mioa701_gpio_lpm_set(unsigned long mfp_pin); diff --git a/arch/arm/mach-pxa/include/mach/mmc.h b/arch/arm/mach-pxa/include/mach/mmc.h deleted file mode 100644 index 6d1304c9270..00000000000 --- a/arch/arm/mach-pxa/include/mach/mmc.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef ASMARM_ARCH_MMC_H -#define ASMARM_ARCH_MMC_H - -#include <linux/mmc/host.h> -#include <linux/interrupt.h> - -struct device; -struct mmc_host; - -struct pxamci_platform_data { - unsigned int ocr_mask; /* available voltages */ - unsigned long detect_delay; /* delay in jiffies before detecting cards after interrupt */ - int (*init)(struct device *, irq_handler_t , void *); - int (*get_ro)(struct device *); - void (*setpower)(struct device *, unsigned int); - void (*exit)(struct device *, void *); -}; - -extern void pxa_set_mci_info(struct pxamci_platform_data *info); -extern void pxa3xx_set_mci2_info(struct pxamci_platform_data *info); -extern void pxa3xx_set_mci3_info(struct pxamci_platform_data *info); - -#endif diff --git a/arch/arm/mach-pxa/include/mach/mtd-xip.h b/arch/arm/mach-pxa/include/mach/mtd-xip.h index 297387ec361..990d2bf2fb4 100644 --- a/arch/arm/mach-pxa/include/mach/mtd-xip.h +++ b/arch/arm/mach-pxa/include/mach/mtd-xip.h @@ -16,7 +16,6 @@ #define __ARCH_PXA_MTD_XIP_H__ #include <mach/regs-ost.h> -#include <mach/regs-intc.h> #define xip_irqpending() (ICIP & ICMR) diff --git a/arch/arm/mach-pxa/include/mach/mxm8x10.h b/arch/arm/mach-pxa/include/mach/mxm8x10.h new file mode 100644 index 00000000000..ffa15665a41 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/mxm8x10.h @@ -0,0 +1,21 @@ +#ifndef __MACH_MXM_8X10_H +#define __MACH_MXM_8X10_H + +#define MXM_8X10_ETH_PHYS 0x13000000 + +#if defined(CONFIG_MMC) + +#define MXM_8X10_SD_nCD (72) +#define MXM_8X10_SD_WP (84) + +extern void mxm_8x10_mmc_init(void); +#else +static inline void mxm_8x10_mmc_init(void) {} +#endif + +extern void mxm_8x10_usb_host_init(void); +extern void mxm_8x10_ac97_init(void); + +extern void mxm_8x10_barebones_init(void); + +#endif /* __MACH_MXM_8X10_H */ diff --git a/arch/arm/mach-pxa/include/mach/ohci.h b/arch/arm/mach-pxa/include/mach/ohci.h deleted file mode 100644 index 95b6e2a6e51..00000000000 --- a/arch/arm/mach-pxa/include/mach/ohci.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef ASMARM_ARCH_OHCI_H -#define ASMARM_ARCH_OHCI_H - -struct device; - -struct pxaohci_platform_data { - int (*init)(struct device *); - void (*exit)(struct device *); - - unsigned long flags; -#define ENABLE_PORT1 (1 << 0) -#define ENABLE_PORT2 (1 << 1) -#define ENABLE_PORT3 (1 << 2) -#define ENABLE_PORT_ALL (ENABLE_PORT1 | ENABLE_PORT2 | ENABLE_PORT3) - -#define POWER_SENSE_LOW (1 << 3) -#define POWER_CONTROL_LOW (1 << 4) -#define NO_OC_PROTECTION (1 << 5) -#define OC_MODE_GLOBAL (0 << 6) -#define OC_MODE_PERPORT (1 << 6) - - int power_on_delay; /* Power On to Power Good time - in ms - * HCD must wait for this duration before - * accessing a powered on port - */ - int port_mode; -#define PMM_NPS_MODE 1 -#define PMM_GLOBAL_MODE 2 -#define PMM_PERPORT_MODE 3 - - int power_budget; -}; - -extern void pxa_set_ohci_info(struct pxaohci_platform_data *info); - -#endif diff --git a/arch/arm/mach-pxa/include/mach/palm27x.h b/arch/arm/mach-pxa/include/mach/palm27x.h new file mode 100644 index 00000000000..d4eac3d6ffb --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/palm27x.h @@ -0,0 +1,81 @@ +/* + * Common functions for Palm LD, T5, TX, Z72 + * + * Copyright (C) 2010 + * Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef __INCLUDE_MACH_PALM27X__ +#define __INCLUDE_MACH_PALM27X__ + +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) +extern void __init palm27x_mmc_init(int detect, int ro, int power, + int power_inverted); +#else +static inline void palm27x_mmc_init(int detect, int ro, int power, + int power_inverted) +{} +#endif + +#if defined(CONFIG_SUSPEND) +extern void __init palm27x_pm_init(unsigned long str_base); +#else +static inline void palm27x_pm_init(unsigned long str_base) {} +#endif + +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) +extern struct pxafb_mode_info palm_320x480_lcd_mode; +extern struct pxafb_mode_info palm_320x320_lcd_mode; +extern struct pxafb_mode_info palm_320x320_new_lcd_mode; +extern void __init palm27x_lcd_init(int power, + struct pxafb_mode_info *mode); +#else +#define palm27x_lcd_init(power, mode) do {} while (0) +#endif + +#if defined(CONFIG_USB_PXA27X) || \ + defined(CONFIG_USB_PXA27X_MODULE) +extern void __init palm27x_udc_init(int vbus, int pullup, + int vbus_inverted); +#else +static inline void palm27x_udc_init(int vbus, int pullup, int vbus_inverted) {} +#endif + +#if defined(CONFIG_IRDA) || defined(CONFIG_IRDA_MODULE) +extern void __init palm27x_irda_init(int pwdn); +#else +static inline void palm27x_irda_init(int pwdn) {} +#endif + +#if defined(CONFIG_TOUCHSCREEN_WM97XX) || \ + defined(CONFIG_TOUCHSCREEN_WM97XX_MODULE) +extern void __init palm27x_ac97_init(int minv, int maxv, int jack, + int reset); +#else +static inline void palm27x_ac97_init(int minv, int maxv, int jack, int reset) {} +#endif + +#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE) +extern void __init palm27x_pwm_init(int bl, int lcd); +#else +static inline void palm27x_pwm_init(int bl, int lcd) {} +#endif + +#if defined(CONFIG_PDA_POWER) || defined(CONFIG_PDA_POWER_MODULE) +extern void __init palm27x_power_init(int ac, int usb); +#else +static inline void palm27x_power_init(int ac, int usb) {} +#endif + +#if defined(CONFIG_REGULATOR_MAX1586) || \ + defined(CONFIG_REGULATOR_MAX1586_MODULE) +extern void __init palm27x_pmic_init(void); +#else +static inline void palm27x_pmic_init(void) {} +#endif + +#endif /* __INCLUDE_MACH_PALM27X__ */ diff --git a/arch/arm/mach-pxa/include/mach/palmasoc.h b/arch/arm/mach-pxa/include/mach/palmasoc.h deleted file mode 100644 index 58afb30d529..00000000000 --- a/arch/arm/mach-pxa/include/mach/palmasoc.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _INCLUDE_PALMASOC_H_ -#define _INCLUDE_PALMASOC_H_ - -struct palm27x_asoc_info { - int jack_gpio; -}; - -#endif diff --git a/arch/arm/mach-pxa/include/mach/palmld.h b/arch/arm/mach-pxa/include/mach/palmld.h index fb13c82ad6d..b184f296023 100644 --- a/arch/arm/mach-pxa/include/mach/palmld.h +++ b/arch/arm/mach-pxa/include/mach/palmld.h @@ -13,6 +13,8 @@ #ifndef _INCLUDE_PALMLD_H_ #define _INCLUDE_PALMLD_H_ +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + /** HERE ARE GPIOs **/ /* GPIOs */ @@ -56,7 +58,6 @@ #define GPIO_NR_PALMLD_LED_AMBER 94 /* IDE */ -#define GPIO_NR_PALMLD_IDE_IRQ 95 #define GPIO_NR_PALMLD_IDE_RESET 98 #define GPIO_NR_PALMLD_IDE_PWEN 115 @@ -69,10 +70,10 @@ /* 20, 53 and 86 are usb related too */ /* INTERRUPTS */ -#define IRQ_GPIO_PALMLD_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMLD_GPIO_RESET) -#define IRQ_GPIO_PALMLD_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMLD_SD_DETECT_N) -#define IRQ_GPIO_PALMLD_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMLD_WM9712_IRQ) -#define IRQ_GPIO_PALMLD_IDE_IRQ IRQ_GPIO(GPIO_NR_PALMLD_IDE_IRQ) +#define IRQ_GPIO_PALMLD_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_GPIO_RESET) +#define IRQ_GPIO_PALMLD_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_SD_DETECT_N) +#define IRQ_GPIO_PALMLD_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_WM9712_IRQ) +#define IRQ_GPIO_PALMLD_IDE_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_IDE_IRQ) /** HERE ARE INIT VALUES **/ @@ -92,7 +93,7 @@ /* BATTERY */ #define PALMLD_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */ #define PALMLD_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */ -#define PALMLD_BAT_MAX_CURRENT 0 /* unknokn */ +#define PALMLD_BAT_MAX_CURRENT 0 /* unknown */ #define PALMLD_BAT_MIN_CURRENT 0 /* unknown */ #define PALMLD_BAT_MAX_CHARGE 1 /* unknown */ #define PALMLD_BAT_MIN_CHARGE 1 /* unknown */ diff --git a/arch/arm/mach-pxa/include/mach/palmt5.h b/arch/arm/mach-pxa/include/mach/palmt5.h index d15662aba00..e342c592140 100644 --- a/arch/arm/mach-pxa/include/mach/palmt5.h +++ b/arch/arm/mach-pxa/include/mach/palmt5.h @@ -15,6 +15,8 @@ #ifndef _INCLUDE_PALMT5_H_ #define _INCLUDE_PALMT5_H_ +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + /** HERE ARE GPIOs **/ /* GPIOs */ @@ -48,10 +50,10 @@ #define GPIO_NR_PALMT5_BT_RESET 83 /* INTERRUPTS */ -#define IRQ_GPIO_PALMT5_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMT5_SD_DETECT_N) -#define IRQ_GPIO_PALMT5_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMT5_WM9712_IRQ) -#define IRQ_GPIO_PALMT5_USB_DETECT IRQ_GPIO(GPIO_NR_PALMT5_USB_DETECT) -#define IRQ_GPIO_PALMT5_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMT5_GPIO_RESET) +#define IRQ_GPIO_PALMT5_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_SD_DETECT_N) +#define IRQ_GPIO_PALMT5_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_WM9712_IRQ) +#define IRQ_GPIO_PALMT5_USB_DETECT PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_USB_DETECT) +#define IRQ_GPIO_PALMT5_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_GPIO_RESET) /** HERE ARE INIT VALUES **/ @@ -66,7 +68,7 @@ /* BATTERY */ #define PALMT5_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ #define PALMT5_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ -#define PALMT5_BAT_MAX_CURRENT 0 /* unknokn */ +#define PALMT5_BAT_MAX_CURRENT 0 /* unknown */ #define PALMT5_BAT_MIN_CURRENT 0 /* unknown */ #define PALMT5_BAT_MAX_CHARGE 1 /* unknown */ #define PALMT5_BAT_MIN_CHARGE 1 /* unknown */ diff --git a/arch/arm/mach-pxa/include/mach/palmtc.h b/arch/arm/mach-pxa/include/mach/palmtc.h new file mode 100644 index 00000000000..81c727b3cfd --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/palmtc.h @@ -0,0 +1,88 @@ +/* + * linux/include/asm-arm/arch-pxa/palmtc-gpio.h + * + * GPIOs and interrupts for Palm Tungsten|C Handheld Computer + * + * Authors: Alex Osborne <bobofdoom@gmail.com> + * Marek Vasut <marek.vasut@gmail.com> + * Holger Bocklet <bitz.email@gmx.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_PALMTC_H_ +#define _INCLUDE_PALMTC_H_ + +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + +/** HERE ARE GPIOs **/ + +/* GPIOs */ +#define GPIO_NR_PALMTC_EARPHONE_DETECT 2 +#define GPIO_NR_PALMTC_CRADLE_DETECT 5 +#define GPIO_NR_PALMTC_HOTSYNC_BUTTON 7 + +/* SD/MMC */ +#define GPIO_NR_PALMTC_SD_DETECT_N 12 +#define GPIO_NR_PALMTC_SD_POWER 32 +#define GPIO_NR_PALMTC_SD_READONLY 54 + +/* WLAN */ +#define GPIO_NR_PALMTC_PCMCIA_READY 13 +#define GPIO_NR_PALMTC_PCMCIA_PWRREADY 14 +#define GPIO_NR_PALMTC_PCMCIA_POWER1 15 +#define GPIO_NR_PALMTC_PCMCIA_POWER2 33 +#define GPIO_NR_PALMTC_PCMCIA_POWER3 55 +#define GPIO_NR_PALMTC_PCMCIA_RESET 78 + +/* UDC */ +#define GPIO_NR_PALMTC_USB_DETECT_N 4 +#define GPIO_NR_PALMTC_USB_POWER 36 + +/* LCD/BACKLIGHT */ +#define GPIO_NR_PALMTC_BL_POWER 16 +#define GPIO_NR_PALMTC_LCD_POWER 44 +#define GPIO_NR_PALMTC_LCD_BLANK 38 + +/* UART */ +#define GPIO_NR_PALMTC_RS232_POWER 37 + +/* IRDA */ +#define GPIO_NR_PALMTC_IR_DISABLE 45 + +/* IRQs */ +#define IRQ_GPIO_PALMTC_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_SD_DETECT_N) +#define IRQ_GPIO_PALMTC_WLAN_READY PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_WLAN_READY) + +/* UCB1400 GPIOs */ +#define GPIO_NR_PALMTC_POWER_DETECT (0x80 | 0x00) +#define GPIO_NR_PALMTC_HEADPHONE_DETECT (0x80 | 0x01) +#define GPIO_NR_PALMTC_SPEAKER_ENABLE (0x80 | 0x03) +#define GPIO_NR_PALMTC_VIBRA_POWER (0x80 | 0x05) +#define GPIO_NR_PALMTC_LED_POWER (0x80 | 0x07) + +/** HERE ARE INIT VALUES **/ +#define PALMTC_UCB1400_GPIO_OFFSET 0x80 + +/* BATTERY */ +#define PALMTC_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */ +#define PALMTC_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */ +#define PALMTC_BAT_MAX_CURRENT 0 /* unknown */ +#define PALMTC_BAT_MIN_CURRENT 0 /* unknown */ +#define PALMTC_BAT_MAX_CHARGE 1 /* unknown */ +#define PALMTC_BAT_MIN_CHARGE 1 /* unknown */ +#define PALMTC_MAX_LIFE_MINS 240 /* on-life in minutes */ + +#define PALMTC_BAT_MEASURE_DELAY (HZ * 1) + +/* BACKLIGHT */ +#define PALMTC_MAX_INTENSITY 0xFE +#define PALMTC_DEFAULT_INTENSITY 0x7E +#define PALMTC_LIMIT_MASK 0x7F +#define PALMTC_PRESCALER 0x3F +#define PALMTC_PERIOD_NS 3500 + +#endif diff --git a/arch/arm/mach-pxa/include/mach/palmte2.h b/arch/arm/mach-pxa/include/mach/palmte2.h index 12361341f9d..f89e989a763 100644 --- a/arch/arm/mach-pxa/include/mach/palmte2.h +++ b/arch/arm/mach-pxa/include/mach/palmte2.h @@ -59,7 +59,7 @@ /* BATTERY */ #define PALMTE2_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ #define PALMTE2_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ -#define PALMTE2_BAT_MAX_CURRENT 0 /* unknokn */ +#define PALMTE2_BAT_MAX_CURRENT 0 /* unknown */ #define PALMTE2_BAT_MIN_CURRENT 0 /* unknown */ #define PALMTE2_BAT_MAX_CHARGE 1 /* unknown */ #define PALMTE2_BAT_MIN_CHARGE 1 /* unknown */ diff --git a/arch/arm/mach-pxa/include/mach/palmtreo.h b/arch/arm/mach-pxa/include/mach/palmtreo.h new file mode 100644 index 00000000000..714b6574393 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/palmtreo.h @@ -0,0 +1,68 @@ +/* + * GPIOs and interrupts for Palm Treo smartphones + * + * currently supported: + * Palm Treo 680 (GSM) + * Palm Centro 685 (GSM) + * + * Author: Tomas Cech <sleep_walker@suse.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * find more info at www.hackndev.com + * + */ + +#ifndef _INCLUDE_TREO_H_ +#define _INCLUDE_TREO_H_ + +/* GPIOs */ +#define GPIO_NR_TREO_POWER_DETECT 0 +#define GPIO_NR_TREO_AMP_EN 27 +#define GPIO_NR_TREO_GREEN_LED 20 +#define GPIO_NR_TREO_RED_LED 79 +#define GPIO_NR_TREO_SD_DETECT_N 113 +#define GPIO_NR_TREO_EP_DETECT_N 116 +#define GPIO_NR_TREO_USB_DETECT 1 +#define GPIO_NR_TREO_USB_PULLUP 114 +#define GPIO_NR_TREO_GSM_POWER 40 +#define GPIO_NR_TREO_GSM_RESET 87 +#define GPIO_NR_TREO_GSM_WAKE 57 +#define GPIO_NR_TREO_GSM_HOST_WAKE 14 +#define GPIO_NR_TREO_GSM_TRIGGER 10 +#define GPIO_NR_TREO_IR_EN 115 +#define GPIO_NR_TREO_IR_TXD 47 +#define GPIO_NR_TREO_BL_POWER 38 +#define GPIO_NR_TREO_LCD_POWER 25 + +/* Treo680 specific GPIOs */ +#define GPIO_NR_TREO680_SD_READONLY 33 +#define GPIO_NR_TREO680_SD_POWER 42 +#define GPIO_NR_TREO680_VIBRATE_EN 44 +#define GPIO_NR_TREO680_KEYB_BL 24 +#define GPIO_NR_TREO680_BT_EN 43 +#define GPIO_NR_TREO680_LCD_POWER 77 +#define GPIO_NR_TREO680_LCD_EN 86 +#define GPIO_NR_TREO680_LCD_EN_N 25 + +/* Centro685 specific GPIOs */ +#define GPIO_NR_CENTRO_SD_POWER 21 +#define GPIO_NR_CENTRO_VIBRATE_EN 22 +#define GPIO_NR_CENTRO_KEYB_BL 33 +#define GPIO_NR_CENTRO_BT_EN 80 + +/* Various addresses */ +#define TREO_PHYS_RAM_START 0xa0000000 +#define TREO_PHYS_IO_START 0x40000000 +#define TREO_STR_BASE 0xa2000000 + +/* BACKLIGHT */ +#define TREO_MAX_INTENSITY 254 +#define TREO_DEFAULT_INTENSITY 160 +#define TREO_LIMIT_MASK 0x7F +#define TREO_PRESCALER 63 +#define TREO_PERIOD_NS 3500 + +#endif diff --git a/arch/arm/mach-pxa/include/mach/palmtx.h b/arch/arm/mach-pxa/include/mach/palmtx.h index e74082c872e..92bc1f05300 100644 --- a/arch/arm/mach-pxa/include/mach/palmtx.h +++ b/arch/arm/mach-pxa/include/mach/palmtx.h @@ -16,6 +16,8 @@ #ifndef _INCLUDE_PALMTX_H_ #define _INCLUDE_PALMTX_H_ +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + /** HERE ARE GPIOs **/ /* GPIOs */ @@ -62,16 +64,16 @@ #define GPIO_NR_PALMTX_NAND_BUFFER_DIR 79 /* INTERRUPTS */ -#define IRQ_GPIO_PALMTX_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMTX_SD_DETECT_N) -#define IRQ_GPIO_PALMTX_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMTX_WM9712_IRQ) -#define IRQ_GPIO_PALMTX_USB_DETECT IRQ_GPIO(GPIO_NR_PALMTX_USB_DETECT) -#define IRQ_GPIO_PALMTX_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMTX_GPIO_RESET) +#define IRQ_GPIO_PALMTX_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_SD_DETECT_N) +#define IRQ_GPIO_PALMTX_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_WM9712_IRQ) +#define IRQ_GPIO_PALMTX_USB_DETECT PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_USB_DETECT) +#define IRQ_GPIO_PALMTX_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_GPIO_RESET) /** HERE ARE INIT VALUES **/ /* Various addresses */ #define PALMTX_PCMCIA_PHYS 0x28000000 -#define PALMTX_PCMCIA_VIRT 0xf0000000 +#define PALMTX_PCMCIA_VIRT IOMEM(0xf0000000) #define PALMTX_PCMCIA_SIZE 0x100000 #define PALMTX_PHYS_RAM_START 0xa0000000 @@ -82,6 +84,11 @@ #define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */ #define PALMTX_PHYS_NAND_START PXA_CS1_PHYS /* ChipSelect 1 */ +#define PALMTX_NAND_ALE_PHYS (PALMTX_PHYS_NAND_START | (1 << 24)) +#define PALMTX_NAND_CLE_PHYS (PALMTX_PHYS_NAND_START | (1 << 25)) +#define PALMTX_NAND_ALE_VIRT IOMEM(0xff100000) +#define PALMTX_NAND_CLE_VIRT IOMEM(0xff200000) + /* TOUCHSCREEN */ #define AC97_LINK_FRAME 21 @@ -89,7 +96,7 @@ /* BATTERY */ #define PALMTX_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ #define PALMTX_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ -#define PALMTX_BAT_MAX_CURRENT 0 /* unknokn */ +#define PALMTX_BAT_MAX_CURRENT 0 /* unknown */ #define PALMTX_BAT_MIN_CURRENT 0 /* unknown */ #define PALMTX_BAT_MAX_CHARGE 1 /* unknown */ #define PALMTX_BAT_MIN_CHARGE 1 /* unknown */ diff --git a/arch/arm/mach-pxa/include/mach/palmz72.h b/arch/arm/mach-pxa/include/mach/palmz72.h index 5032307ebf7..0d4700a7961 100644 --- a/arch/arm/mach-pxa/include/mach/palmz72.h +++ b/arch/arm/mach-pxa/include/mach/palmz72.h @@ -21,7 +21,7 @@ /* SD/MMC */ #define GPIO_NR_PALMZ72_SD_DETECT_N 14 #define GPIO_NR_PALMZ72_SD_POWER_N 98 -#define GPIO_NR_PALMZ72_SD_RO 115 +#define GPIO_NR_PALMZ72_SD_RO 115 /* Touchscreen */ #define GPIO_NR_PALMZ72_WM9712_IRQ 27 @@ -31,8 +31,7 @@ /* USB */ #define GPIO_NR_PALMZ72_USB_DETECT_N 15 -#define GPIO_NR_PALMZ72_USB_POWER 95 -#define GPIO_NR_PALMZ72_USB_PULLUP 12 +#define GPIO_NR_PALMZ72_USB_PULLUP 95 /* LCD/Backlight */ #define GPIO_NR_PALMZ72_BL_POWER 20 @@ -45,12 +44,17 @@ #define GPIO_NR_PALMZ72_BT_POWER 17 #define GPIO_NR_PALMZ72_BT_RESET 83 +/* Camera */ +#define GPIO_NR_PALMZ72_CAM_PWDN 56 +#define GPIO_NR_PALMZ72_CAM_RESET 57 +#define GPIO_NR_PALMZ72_CAM_POWER 91 + /** Initial values **/ /* Battery */ #define PALMZ72_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ #define PALMZ72_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ -#define PALMZ72_BAT_MAX_CURRENT 0 /* unknokn */ +#define PALMZ72_BAT_MAX_CURRENT 0 /* unknown */ #define PALMZ72_BAT_MIN_CURRENT 0 /* unknown */ #define PALMZ72_BAT_MAX_CHARGE 1 /* unknown */ #define PALMZ72_BAT_MIN_CHARGE 1 /* unknown */ diff --git a/arch/arm/mach-pxa/include/mach/pcm027.h b/arch/arm/mach-pxa/include/mach/pcm027.h index 4dcd2e8baa6..86ebd7b6c96 100644 --- a/arch/arm/mach-pxa/include/mach/pcm027.h +++ b/arch/arm/mach-pxa/include/mach/pcm027.h @@ -23,9 +23,20 @@ * Definitions of CPU card resources only */ +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + +/* phyCORE-PXA270 (PCM027) Interrupts */ +#define PCM027_IRQ(x) (IRQ_BOARD_START + (x)) +#define PCM027_BTDET_IRQ PCM027_IRQ(0) +#define PCM027_FF_RI_IRQ PCM027_IRQ(1) +#define PCM027_MMCDET_IRQ PCM027_IRQ(2) +#define PCM027_PM_5V_IRQ PCM027_IRQ(3) + +#define PCM027_NR_IRQS (IRQ_BOARD_START + 32) + /* I2C RTC */ #define PCM027_RTC_IRQ_GPIO 0 -#define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO) +#define PCM027_RTC_IRQ PXA_GPIO_TO_IRQ(PCM027_RTC_IRQ_GPIO) #define PCM027_RTC_IRQ_EDGE IRQ_TYPE_EDGE_FALLING #define ADR_PCM027_RTC 0x51 /* I2C address */ @@ -34,21 +45,21 @@ /* Ethernet chip (SMSC91C111) */ #define PCM027_ETH_IRQ_GPIO 52 -#define PCM027_ETH_IRQ IRQ_GPIO(PCM027_ETH_IRQ_GPIO) +#define PCM027_ETH_IRQ PXA_GPIO_TO_IRQ(PCM027_ETH_IRQ_GPIO) #define PCM027_ETH_IRQ_EDGE IRQ_TYPE_EDGE_RISING #define PCM027_ETH_PHYS PXA_CS5_PHYS #define PCM027_ETH_SIZE (1*1024*1024) /* CAN controller SJA1000 (unsupported yet) */ #define PCM027_CAN_IRQ_GPIO 114 -#define PCM027_CAN_IRQ IRQ_GPIO(PCM027_CAN_IRQ_GPIO) +#define PCM027_CAN_IRQ PXA_GPIO_TO_IRQ(PCM027_CAN_IRQ_GPIO) #define PCM027_CAN_IRQ_EDGE IRQ_TYPE_EDGE_FALLING #define PCM027_CAN_PHYS 0x22000000 #define PCM027_CAN_SIZE 0x100 /* SPI GPIO expander (unsupported yet) */ #define PCM027_EGPIO_IRQ_GPIO 27 -#define PCM027_EGPIO_IRQ IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO) +#define PCM027_EGPIO_IRQ PXA_GPIO_TO_IRQ(PCM027_EGPIO_IRQ_GPIO) #define PCM027_EGPIO_IRQ_EDGE IRQ_TYPE_EDGE_FALLING #define PCM027_EGPIO_CS 24 /* diff --git a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h index 8a4383b776d..7e544c14967 100644 --- a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h +++ b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h @@ -20,6 +20,7 @@ */ #include <mach/pcm027.h> +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ /* * definitions relevant only when the PCM-990 @@ -28,14 +29,13 @@ /* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */ #define PCM990_CTRL_INT_IRQ_GPIO 9 -#define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO) +#define PCM990_CTRL_INT_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_INT_IRQ_GPIO) #define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING #define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */ -#define PCM990_CTRL_BASE 0xea000000 #define PCM990_CTRL_SIZE (1*1024*1024) #define PCM990_CTRL_PWR_IRQ_GPIO 14 -#define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO) +#define PCM990_CTRL_PWR_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_PWR_IRQ_GPIO) #define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING /* visible CPLD (U7) registers */ @@ -69,13 +69,13 @@ #define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */ #define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */ -#define PCM990_CTRL_REG6 0x000C /* Interrupt Clear REGISTER */ +#define PCM990_CTRL_INTSETCLR 0x000C /* Interrupt Clear REGISTER */ #define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */ #define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */ #define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */ #define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */ -#define PCM990_CTRL_REG7 0x000E /* Interrupt Enable REGISTER */ +#define PCM990_CTRL_INTMSKENA 0x000E /* Interrupt Enable REGISTER */ #define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */ #define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */ #define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */ @@ -102,37 +102,11 @@ #define PCM990_CTRL_ACPRES 0x0004 /* DC Present */ #define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */ -#define PCM990_CTRL_P2V(x) ((x) - PCM990_CTRL_PHYS + PCM990_CTRL_BASE) -#define PCM990_CTRL_V2P(x) ((x) - PCM990_CTRL_BASE + PCM990_CTRL_PHYS) - -#ifndef __ASSEMBLY__ -# define __PCM990_CTRL_REG(x) \ - (*((volatile unsigned char *)PCM990_CTRL_P2V(x))) -#else -# define __PCM990_CTRL_REG(x) PCM990_CTRL_P2V(x) -#endif - -#define PCM990_INTMSKENA __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7) -#define PCM990_INTSETCLR __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6) -#define PCM990_CTRL0 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG0) -#define PCM990_CTRL1 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG1) -#define PCM990_CTRL2 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG2) -#define PCM990_CTRL3 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) -#define PCM990_CTRL4 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG4) -#define PCM990_CTRL5 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5) -#define PCM990_CTRL6 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6) -#define PCM990_CTRL7 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7) -#define PCM990_CTRL8 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG8) -#define PCM990_CTRL9 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG9) -#define PCM990_CTRL10 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG10) -#define PCM990_CTRL11 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG11) - - /* * IDE */ #define PCM990_IDE_IRQ_GPIO 13 -#define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO) +#define PCM990_IDE_IRQ PXA_GPIO_TO_IRQ(PCM990_IDE_IRQ_GPIO) #define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING #define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */ #define PCM990_IDE_PLD_BASE 0xee000000 @@ -166,40 +140,18 @@ #define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE) #define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS) -#ifndef __ASSEMBLY__ -# define __PCM990_IDE_PLD_REG(x) \ - (*((volatile unsigned char *)PCM990_IDE_PLD_P2V(x))) -#else -# define __PCM990_IDE_PLD_REG(x) PCM990_IDE_PLD_P2V(x) -#endif - -#define PCM990_IDE0 \ - __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG0) -#define PCM990_IDE1 \ - __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG1) -#define PCM990_IDE2 \ - __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG2) -#define PCM990_IDE3 \ - __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG3) -#define PCM990_IDE4 \ - __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG4) - /* * Compact Flash */ #define PCM990_CF_IRQ_GPIO 11 -#define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO) +#define PCM990_CF_IRQ PXA_GPIO_TO_IRQ(PCM990_CF_IRQ_GPIO) #define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING #define PCM990_CF_CD_GPIO 12 -#define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO) +#define PCM990_CF_CD PXA_GPIO_TO_IRQ(PCM990_CF_CD_GPIO) #define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING #define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */ -#define PCM990_CF_PLD_BASE 0xef000000 -#define PCM990_CF_PLD_SIZE (1*1024*1024) -#define PCM990_CF_PLD_P2V(x) ((x) - PCM990_CF_PLD_PHYS + PCM990_CF_PLD_BASE) -#define PCM990_CF_PLD_V2P(x) ((x) - PCM990_CF_PLD_BASE + PCM990_CF_PLD_PHYS) /* visible CPLD (U6) registers */ #define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */ @@ -239,33 +191,18 @@ #define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */ #define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */ -#ifndef __ASSEMBLY__ -# define __PCM990_CF_PLD_REG(x) \ - (*((volatile unsigned char *)PCM990_CF_PLD_P2V(x))) -#else -# define __PCM990_CF_PLD_REG(x) PCM990_CF_PLD_P2V(x) -#endif - -#define PCM990_CF0 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG0) -#define PCM990_CF1 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG1) -#define PCM990_CF2 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG2) -#define PCM990_CF3 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG3) -#define PCM990_CF4 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG4) -#define PCM990_CF5 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG5) -#define PCM990_CF6 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG6) - /* * Wolfson AC97 Touch */ #define PCM990_AC97_IRQ_GPIO 10 -#define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO) +#define PCM990_AC97_IRQ PXA_GPIO_TO_IRQ(PCM990_AC97_IRQ_GPIO) #define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING /* * MMC phyCORE */ #define PCM990_MMC0_IRQ_GPIO 9 -#define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO) +#define PCM990_MMC0_IRQ PXA_GPIO_TO_IRQ(PCM990_MMC0_IRQ_GPIO) #define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING /* diff --git a/arch/arm/mach-pxa/include/mach/pm.h b/arch/arm/mach-pxa/include/mach/pm.h index a6eeef8a075..51558bcee99 100644 --- a/arch/arm/mach-pxa/include/mach/pm.h +++ b/arch/arm/mach-pxa/include/mach/pm.h @@ -22,11 +22,12 @@ struct pxa_cpu_pm_fns { extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns; /* sleep.S */ -extern void pxa25x_cpu_suspend(unsigned int); -extern void pxa27x_cpu_suspend(unsigned int); -extern void pxa_cpu_resume(void); +extern int pxa25x_finish_suspend(unsigned long); +extern int pxa27x_finish_suspend(unsigned long); extern int pxa_pm_enter(suspend_state_t state); +extern int pxa_pm_prepare(void); +extern void pxa_pm_finish(void); /* NOTE: this is for PM debugging on Lubbock, it's really a big * ugly, but let's keep the crap minimum here, instead of direct diff --git a/arch/arm/mach-pxa/include/mach/poodle.h b/arch/arm/mach-pxa/include/mach/poodle.h index 0b3e6d051c6..b56b19351a0 100644 --- a/arch/arm/mach-pxa/include/mach/poodle.h +++ b/arch/arm/mach-pxa/include/mach/poodle.h @@ -15,6 +15,8 @@ #ifndef __ASM_ARCH_POODLE_H #define __ASM_ARCH_POODLE_H 1 +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + /* * GPIOs */ @@ -47,18 +49,18 @@ #define POODLE_GPIO_DISCHARGE_ON (42) /* Enable battery discharge */ /* PXA GPIOs */ -#define POODLE_IRQ_GPIO_ON_KEY IRQ_GPIO(0) -#define POODLE_IRQ_GPIO_AC_IN IRQ_GPIO(1) -#define POODLE_IRQ_GPIO_HP_IN IRQ_GPIO(4) -#define POODLE_IRQ_GPIO_CO IRQ_GPIO(16) -#define POODLE_IRQ_GPIO_TP_INT IRQ_GPIO(5) -#define POODLE_IRQ_GPIO_WAKEUP IRQ_GPIO(11) -#define POODLE_IRQ_GPIO_GA_INT IRQ_GPIO(10) -#define POODLE_IRQ_GPIO_CF_IRQ IRQ_GPIO(17) -#define POODLE_IRQ_GPIO_CF_CD IRQ_GPIO(14) -#define POODLE_IRQ_GPIO_nSD_INT IRQ_GPIO(8) -#define POODLE_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9) -#define POODLE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(13) +#define POODLE_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(0) +#define POODLE_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(1) +#define POODLE_IRQ_GPIO_HP_IN PXA_GPIO_TO_IRQ(4) +#define POODLE_IRQ_GPIO_CO PXA_GPIO_TO_IRQ(16) +#define POODLE_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(5) +#define POODLE_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(11) +#define POODLE_IRQ_GPIO_GA_INT PXA_GPIO_TO_IRQ(10) +#define POODLE_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(17) +#define POODLE_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(14) +#define POODLE_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(8) +#define POODLE_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(9) +#define POODLE_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(13) /* SCOOP GPIOs */ #define POODLE_SCOOP_CHARGE_ON SCOOP_GPCR_PA11 @@ -71,7 +73,7 @@ #define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT ) #define POODLE_SCOOP_IO_OUT ( 0 ) -#define POODLE_SCOOP_GPIO_BASE (NR_BUILTIN_GPIO) +#define POODLE_SCOOP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) #define POODLE_GPIO_CHARGE_ON (POODLE_SCOOP_GPIO_BASE + 0) #define POODLE_GPIO_CP401 (POODLE_SCOOP_GPIO_BASE + 2) #define POODLE_GPIO_VPEN (POODLE_SCOOP_GPIO_BASE + 7) @@ -85,6 +87,8 @@ #define POODLE_LOCOMO_GPIO_232VCC_ON LOCOMO_GPIO(12) #define POODLE_LOCOMO_GPIO_JK_B LOCOMO_GPIO(13) +#define POODLE_NR_IRQS (IRQ_BOARD_START + 4) /* 4 for LoCoMo */ + extern struct platform_device poodle_locomo_device; #endif /* __ASM_ARCH_POODLE_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa25x.h b/arch/arm/mach-pxa/include/mach/pxa25x.h index 508c3ba1f4d..3ac0baac735 100644 --- a/arch/arm/mach-pxa/include/mach/pxa25x.h +++ b/arch/arm/mach-pxa/include/mach/pxa25x.h @@ -4,5 +4,14 @@ #include <mach/hardware.h> #include <mach/pxa2xx-regs.h> #include <mach/mfp-pxa25x.h> +#include <mach/irqs.h> + +extern void __init pxa25x_map_io(void); +extern void __init pxa25x_init_irq(void); +#ifdef CONFIG_CPU_PXA26x +extern void __init pxa26x_init_irq(void); +#endif + +#define pxa25x_handle_irq icip_handle_irq #endif /* __MACH_PXA25x_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa27x-udc.h b/arch/arm/mach-pxa/include/mach/pxa27x-udc.h index ab1443f8bd8..4cf28f67070 100644 --- a/arch/arm/mach-pxa/include/mach/pxa27x-udc.h +++ b/arch/arm/mach-pxa/include/mach/pxa27x-udc.h @@ -56,9 +56,9 @@ #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ -#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt +#define UDCOTGICR_IEXR (1 << 17) /* Extra Transceiver Interrupt Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt +#define UDCOTGICR_IEXF (1 << 16) /* Extra Transceiver Interrupt Falling Edge Interrupt Enable */ #define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge Interrupt Enable */ diff --git a/arch/arm/mach-pxa/include/mach/pxa27x.h b/arch/arm/mach-pxa/include/mach/pxa27x.h index 6876e16c297..7cff640582b 100644 --- a/arch/arm/mach-pxa/include/mach/pxa27x.h +++ b/arch/arm/mach-pxa/include/mach/pxa27x.h @@ -1,9 +1,11 @@ #ifndef __MACH_PXA27x_H #define __MACH_PXA27x_H +#include <linux/suspend.h> #include <mach/hardware.h> #include <mach/pxa2xx-regs.h> #include <mach/mfp-pxa27x.h> +#include <mach/irqs.h> #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ @@ -16,4 +18,12 @@ #define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ + +extern void __init pxa27x_map_io(void); +extern void __init pxa27x_init_irq(void); +extern int __init pxa27x_set_pwrmode(unsigned int mode); +extern void pxa27x_cpu_pm_enter(suspend_state_t state); + +#define pxa27x_handle_irq ichp_handle_irq + #endif /* __MACH_PXA27x_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h b/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h deleted file mode 100644 index d5a48a96dea..00000000000 --- a/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h +++ /dev/null @@ -1,58 +0,0 @@ -#ifndef __ASM_ARCH_PXA27x_KEYPAD_H -#define __ASM_ARCH_PXA27x_KEYPAD_H - -#include <linux/input.h> - -#define MAX_MATRIX_KEY_ROWS (8) -#define MAX_MATRIX_KEY_COLS (8) - -/* pxa3xx keypad platform specific parameters - * - * NOTE: - * 1. direct_key_num indicates the number of keys in the direct keypad - * _plus_ the number of rotary-encoder sensor inputs, this can be - * left as 0 if only rotary encoders are enabled, the driver will - * automatically calculate this - * - * 2. direct_key_map is the key code map for the direct keys, if rotary - * encoder(s) are enabled, direct key 0/1(2/3) will be ignored - * - * 3. rotary can be either interpreted as a relative input event (e.g. - * REL_WHEEL/REL_HWHEEL) or specific keys (e.g. UP/DOWN/LEFT/RIGHT) - * - * 4. matrix key and direct key will use the same debounce_interval by - * default, which should be sufficient in most cases - */ -struct pxa27x_keypad_platform_data { - - /* code map for the matrix keys */ - unsigned int matrix_key_rows; - unsigned int matrix_key_cols; - unsigned int *matrix_key_map; - int matrix_key_map_size; - - /* direct keys */ - int direct_key_num; - unsigned int direct_key_map[8]; - - /* rotary encoders 0 */ - int enable_rotary0; - int rotary0_rel_code; - int rotary0_up_key; - int rotary0_down_key; - - /* rotary encoders 1 */ - int enable_rotary1; - int rotary1_rel_code; - int rotary1_up_key; - int rotary1_down_key; - - /* key debounce interval */ - unsigned int debounce_interval; -}; - -#define KEY(row, col, val) (((row) << 28) | ((col) << 24) | (val)) - -extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info); - -#endif /* __ASM_ARCH_PXA27x_KEYPAD_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h deleted file mode 100644 index 1209c44aa6f..00000000000 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h +++ /dev/null @@ -1,375 +0,0 @@ -#ifndef __ASM_ARCH_PXA2XX_GPIO_H -#define __ASM_ARCH_PXA2XX_GPIO_H - -#warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h - -#include <mach/gpio.h> - -/* GPIO alternate function assignments */ - -#define GPIO1_RST 1 /* reset */ -#define GPIO6_MMCCLK 6 /* MMC Clock */ -#define GPIO7_48MHz 7 /* 48 MHz clock output */ -#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ -#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ -#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ -#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ -#define GPIO12_32KHz 12 /* 32 kHz out */ -#define GPIO12_CIF_DD_7 12 /* Camera data pin 7 */ -#define GPIO13_MBGNT 13 /* memory controller grant */ -#define GPIO14_MBREQ 14 /* alternate bus master request */ -#define GPIO15_nCS_1 15 /* chip select 1 */ -#define GPIO16_PWM0 16 /* PWM0 output */ -#define GPIO17_PWM1 17 /* PWM1 output */ -#define GPIO17_CIF_DD_6 17 /* Camera data pin 6 */ -#define GPIO18_RDY 18 /* Ext. Bus Ready */ -#define GPIO19_DREQ1 19 /* External DMA Request */ -#define GPIO20_DREQ0 20 /* External DMA Request */ -#define GPIO23_SCLK 23 /* SSP clock */ -#define GPIO23_CIF_MCLK 23 /* Camera Master Clock */ -#define GPIO24_SFRM 24 /* SSP Frame */ -#define GPIO24_CIF_FV 24 /* Camera frame start signal */ -#define GPIO25_STXD 25 /* SSP transmit */ -#define GPIO25_CIF_LV 25 /* Camera line start signal */ -#define GPIO26_SRXD 26 /* SSP receive */ -#define GPIO26_CIF_PCLK 26 /* Camera Pixel Clock */ -#define GPIO27_SEXTCLK 27 /* SSP ext_clk */ -#define GPIO27_CIF_DD_0 27 /* Camera data pin 0 */ -#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ -#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ -#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ -#define GPIO31_SYNC 31 /* AC97/I2S sync */ -#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ -#define GPIO32_SYSCLK 32 /* I2S System Clock */ -#define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */ -#define GPIO33_nCS_5 33 /* chip select 5 */ -#define GPIO34_FFRXD 34 /* FFUART receive */ -#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ -#define GPIO35_FFCTS 35 /* FFUART Clear to send */ -#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ -#define GPIO37_FFDSR 37 /* FFUART data set ready */ -#define GPIO38_FFRI 38 /* FFUART Ring Indicator */ -#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ -#define GPIO39_FFTXD 39 /* FFUART transmit data */ -#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ -#define GPIO41_FFRTS 41 /* FFUART request to send */ -#define GPIO42_BTRXD 42 /* BTUART receive data */ -#define GPIO42_HWRXD 42 /* HWUART receive data */ -#define GPIO42_CIF_MCLK 42 /* Camera Master Clock */ -#define GPIO43_BTTXD 43 /* BTUART transmit data */ -#define GPIO43_HWTXD 43 /* HWUART transmit data */ -#define GPIO43_CIF_FV 43 /* Camera frame start signal */ -#define GPIO44_BTCTS 44 /* BTUART clear to send */ -#define GPIO44_HWCTS 44 /* HWUART clear to send */ -#define GPIO44_CIF_LV 44 /* Camera line start signal */ -#define GPIO45_BTRTS 45 /* BTUART request to send */ -#define GPIO45_HWRTS 45 /* HWUART request to send */ -#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */ -#define GPIO45_CIF_PCLK 45 /* Camera Pixel Clock */ -#define GPIO46_ICPRXD 46 /* ICP receive data */ -#define GPIO46_STRXD 46 /* STD_UART receive data */ -#define GPIO47_ICPTXD 47 /* ICP transmit data */ -#define GPIO47_STTXD 47 /* STD_UART transmit data */ -#define GPIO47_CIF_DD_0 47 /* Camera data pin 0 */ -#define GPIO48_nPOE 48 /* Output Enable for Card Space */ -#define GPIO48_CIF_DD_5 48 /* Camera data pin 5 */ -#define GPIO49_nPWE 49 /* Write Enable for Card Space */ -#define GPIO50_nPIOR 50 /* I/O Read for Card Space */ -#define GPIO50_CIF_DD_3 50 /* Camera data pin 3 */ -#define GPIO51_nPIOW 51 /* I/O Write for Card Space */ -#define GPIO51_CIF_DD_2 51 /* Camera data pin 2 */ -#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ -#define GPIO52_CIF_DD_4 52 /* Camera data pin 4 */ -#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ -#define GPIO53_MMCCLK 53 /* MMC Clock */ -#define GPIO53_CIF_MCLK 53 /* Camera Master Clock */ -#define GPIO54_MMCCLK 54 /* MMC Clock */ -#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ -#define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */ -#define GPIO54_CIF_PCLK 54 /* Camera Pixel Clock */ -#define GPIO55_nPREG 55 /* Card Address bit 26 */ -#define GPIO55_CIF_DD_1 55 /* Camera data pin 1 */ -#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ -#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ -#define GPIO58_LDD_0 58 /* LCD data pin 0 */ -#define GPIO59_LDD_1 59 /* LCD data pin 1 */ -#define GPIO60_LDD_2 60 /* LCD data pin 2 */ -#define GPIO61_LDD_3 61 /* LCD data pin 3 */ -#define GPIO62_LDD_4 62 /* LCD data pin 4 */ -#define GPIO63_LDD_5 63 /* LCD data pin 5 */ -#define GPIO64_LDD_6 64 /* LCD data pin 6 */ -#define GPIO65_LDD_7 65 /* LCD data pin 7 */ -#define GPIO66_LDD_8 66 /* LCD data pin 8 */ -#define GPIO66_MBREQ 66 /* alternate bus master req */ -#define GPIO67_LDD_9 67 /* LCD data pin 9 */ -#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ -#define GPIO68_LDD_10 68 /* LCD data pin 10 */ -#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ -#define GPIO69_LDD_11 69 /* LCD data pin 11 */ -#define GPIO69_MMCCLK 69 /* MMC_CLK */ -#define GPIO70_LDD_12 70 /* LCD data pin 12 */ -#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ -#define GPIO71_LDD_13 71 /* LCD data pin 13 */ -#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ -#define GPIO72_LDD_14 72 /* LCD data pin 14 */ -#define GPIO72_32kHz 72 /* 32 kHz clock */ -#define GPIO73_LDD_15 73 /* LCD data pin 15 */ -#define GPIO73_MBGNT 73 /* Memory controller grant */ -#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ -#define GPIO75_LCD_LCLK 75 /* LCD line clock */ -#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ -#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ -#define GPIO78_nCS_2 78 /* chip select 2 */ -#define GPIO79_nCS_3 79 /* chip select 3 */ -#define GPIO80_nCS_4 80 /* chip select 4 */ -#define GPIO81_NSCLK 81 /* NSSP clock */ -#define GPIO81_CIF_DD_0 81 /* Camera data pin 0 */ -#define GPIO82_NSFRM 82 /* NSSP Frame */ -#define GPIO82_CIF_DD_5 82 /* Camera data pin 5 */ -#define GPIO83_NSTXD 83 /* NSSP transmit */ -#define GPIO83_CIF_DD_4 83 /* Camera data pin 4 */ -#define GPIO84_NSRXD 84 /* NSSP receive */ -#define GPIO84_CIF_FV 84 /* Camera frame start signal */ -#define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */ -#define GPIO85_CIF_LV 85 /* Camera line start signal */ -#define GPIO90_CIF_DD_4 90 /* Camera data pin 4 */ -#define GPIO91_CIF_DD_5 91 /* Camera data pin 5 */ -#define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */ -#define GPIO93_CIF_DD_6 93 /* Camera data pin 6 */ -#define GPIO94_CIF_DD_5 94 /* Camera data pin 5 */ -#define GPIO95_CIF_DD_4 95 /* Camera data pin 4 */ -#define GPIO96_FFRXD 96 /* FFUART recieve */ -#define GPIO98_FFRTS 98 /* FFUART request to send */ -#define GPIO98_CIF_DD_0 98 /* Camera data pin 0 */ -#define GPIO99_FFTXD 99 /* FFUART transmit data */ -#define GPIO100_FFCTS 100 /* FFUART Clear to send */ -#define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */ -#define GPIO103_CIF_DD_3 103 /* Camera data pin 3 */ -#define GPIO104_CIF_DD_2 104 /* Camera data pin 2 */ -#define GPIO105_CIF_DD_1 105 /* Camera data pin 1 */ -#define GPIO106_CIF_DD_9 106 /* Camera data pin 9 */ -#define GPIO107_CIF_DD_8 107 /* Camera data pin 8 */ -#define GPIO108_CIF_DD_7 108 /* Camera data pin 7 */ -#define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */ -#define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */ -#define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */ -#define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */ -#define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */ -#define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */ -#define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */ -#define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */ -#define GPIO114_CIF_DD_1 114 /* Camera data pin 1 */ -#define GPIO115_CIF_DD_3 115 /* Camera data pin 3 */ -#define GPIO116_CIF_DD_2 116 /* Camera data pin 2 */ - -/* GPIO alternate function mode & direction */ - -#define GPIO_IN 0x000 -#define GPIO_OUT 0x080 -#define GPIO_ALT_FN_1_IN 0x100 -#define GPIO_ALT_FN_1_OUT 0x180 -#define GPIO_ALT_FN_2_IN 0x200 -#define GPIO_ALT_FN_2_OUT 0x280 -#define GPIO_ALT_FN_3_IN 0x300 -#define GPIO_ALT_FN_3_OUT 0x380 -#define GPIO_MD_MASK_NR 0x07f -#define GPIO_MD_MASK_DIR 0x080 -#define GPIO_MD_MASK_FN 0x300 -#define GPIO_DFLT_LOW 0x400 -#define GPIO_DFLT_HIGH 0x800 - -#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) -#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) -#define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT) -#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) -#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) -#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) -#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) -#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) -#define GPIO12_CIF_DD_7_MD (12 | GPIO_ALT_FN_2_IN) -#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) -#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) -#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) -#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) -#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) -#define GPIO17_CIF_DD_6_MD (17 | GPIO_ALT_FN_2_IN) -#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) -#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) -#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) -#define GPIO23_CIF_MCLK_MD (23 | GPIO_ALT_FN_1_OUT) -#define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT) -#define GPIO24_CIF_FV_MD (24 | GPIO_ALT_FN_1_OUT) -#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) -#define GPIO25_CIF_LV_MD (25 | GPIO_ALT_FN_1_OUT) -#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) -#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) -#define GPIO26_CIF_PCLK_MD (26 | GPIO_ALT_FN_2_IN) -#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) -#define GPIO27_CIF_DD_0_MD (27 | GPIO_ALT_FN_3_IN) -#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) -#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN) -#define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT) -#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) -#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) -#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) -#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) -#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) -#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) -#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) -#define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT) -#define GPIO32_MMCCLK_MD (32 | GPIO_ALT_FN_2_OUT) -#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) -#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) -#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) -#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) -#define GPIO35_KP_MKOUT6_MD (35 | GPIO_ALT_FN_2_OUT) -#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) -#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) -#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) -#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) -#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) -#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) -#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) -#define GPIO41_KP_MKOUT7_MD (41 | GPIO_ALT_FN_1_OUT) -#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) -#define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN) -#define GPIO42_CIF_MCLK_MD (42 | GPIO_ALT_FN_3_OUT) -#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) -#define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT) -#define GPIO43_CIF_FV_MD (43 | GPIO_ALT_FN_3_OUT) -#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) -#define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN) -#define GPIO44_CIF_LV_MD (44 | GPIO_ALT_FN_3_OUT) -#define GPIO45_CIF_PCLK_MD (45 | GPIO_ALT_FN_3_IN) -#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) -#define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT) -#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT) -#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) -#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) -#define GPIO47_CIF_DD_0_MD (47 | GPIO_ALT_FN_1_IN) -#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) -#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) -#define GPIO48_CIF_DD_5_MD (48 | GPIO_ALT_FN_1_IN) -#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) -#define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT) -#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) -#define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN) -#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) -#define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN) -#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) -#define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN) -#define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN) -#define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN) -#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) -#define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT) -#define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN) -#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) -#define GPIO52_CIF_DD_4_MD (52 | GPIO_ALT_FN_1_IN) -#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) -#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) -#define GPIO53_CIF_MCLK_MD (53 | GPIO_ALT_FN_2_OUT) -#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) -#define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT) -#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) -#define GPIO54_CIF_PCLK_MD (54 | GPIO_ALT_FN_3_IN) -#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) -#define GPIO55_CIF_DD_1_MD (55 | GPIO_ALT_FN_1_IN) -#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) -#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) -#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) -#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) -#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) -#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) -#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) -#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) -#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) -#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) -#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) -#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) -#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) -#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) -#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) -#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) -#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) -#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) -#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) -#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) -#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) -#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) -#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) -#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) -#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) -#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) -#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) -#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) -#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) -#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) -#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) -#define GPIO78_nPCE_2_MD (78 | GPIO_ALT_FN_1_OUT) -#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) -#define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT) -#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) -#define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT) -#define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN) -#define GPIO81_CIF_DD_0_MD (81 | GPIO_ALT_FN_2_IN) -#define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT) -#define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN) -#define GPIO82_CIF_DD_5_MD (82 | GPIO_ALT_FN_3_IN) -#define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT) -#define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN) -#define GPIO83_CIF_DD_4_MD (83 | GPIO_ALT_FN_3_IN) -#define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT) -#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN) -#define GPIO84_CIF_FV_MD (84 | GPIO_ALT_FN_3_IN) -#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) -#define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN) -#define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT) -#define GPIO88_USBH1_PWR_MD (88 | GPIO_ALT_FN_1_IN) -#define GPIO89_USBH1_PEN_MD (89 | GPIO_ALT_FN_2_OUT) -#define GPIO90_CIF_DD_4_MD (90 | GPIO_ALT_FN_3_IN) -#define GPIO91_CIF_DD_5_MD (91 | GPIO_ALT_FN_3_IN) -#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) -#define GPIO93_CIF_DD_6_MD (93 | GPIO_ALT_FN_2_IN) -#define GPIO94_CIF_DD_5_MD (94 | GPIO_ALT_FN_2_IN) -#define GPIO95_CIF_DD_4_MD (95 | GPIO_ALT_FN_2_IN) -#define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN) -#define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN) -#define GPIO96_FFRXD_MD (96 | GPIO_ALT_FN_3_IN) -#define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN) -#define GPIO98_CIF_DD_0_MD (98 | GPIO_ALT_FN_2_IN) -#define GPIO98_FFRTS_MD (98 | GPIO_ALT_FN_3_OUT) -#define GPIO99_FFTXD_MD (99 | GPIO_ALT_FN_3_OUT) -#define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN) -#define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN) -#define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT) -#define GPIO102_KP_MKIN2_MD (102 | GPIO_ALT_FN_1_IN) -#define GPIO103_CIF_DD_3_MD (103 | GPIO_ALT_FN_1_IN) -#define GPIO103_KP_MKOUT0_MD (103 | GPIO_ALT_FN_2_OUT) -#define GPIO104_CIF_DD_2_MD (104 | GPIO_ALT_FN_1_IN) -#define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT) -#define GPIO104_KP_MKOUT1_MD (104 | GPIO_ALT_FN_2_OUT) -#define GPIO105_CIF_DD_1_MD (105 | GPIO_ALT_FN_1_IN) -#define GPIO105_KP_MKOUT2_MD (105 | GPIO_ALT_FN_2_OUT) -#define GPIO106_CIF_DD_9_MD (106 | GPIO_ALT_FN_1_IN) -#define GPIO106_KP_MKOUT3_MD (106 | GPIO_ALT_FN_2_OUT) -#define GPIO107_CIF_DD_8_MD (107 | GPIO_ALT_FN_1_IN) -#define GPIO107_KP_MKOUT4_MD (107 | GPIO_ALT_FN_2_OUT) -#define GPIO108_CIF_DD_7_MD (108 | GPIO_ALT_FN_1_IN) -#define GPIO108_KP_MKOUT5_MD (108 | GPIO_ALT_FN_2_OUT) -#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT) -#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT) -#define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT) -#define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT) -#define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT) -#define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT) -#define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT) -#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT) -#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN) -#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) - -/* - * Handy routine to set GPIO alternate functions - */ -extern int pxa_gpio_mode( int gpio_mode ); - -#endif /* __ASM_ARCH_PXA2XX_GPIO_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h index 4fcddd9cab7..ee6ced1cea7 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h @@ -17,72 +17,6 @@ #include <mach/hardware.h> /* - * PXA Chip selects - */ - -#define PXA_CS0_PHYS 0x00000000 -#define PXA_CS1_PHYS 0x04000000 -#define PXA_CS2_PHYS 0x08000000 -#define PXA_CS3_PHYS 0x0C000000 -#define PXA_CS4_PHYS 0x10000000 -#define PXA_CS5_PHYS 0x14000000 - -/* - * Memory controller - */ - -#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ -#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ -#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ -#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ -#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ -#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ -#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ -#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ -#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ -#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ -#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ -#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ -#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ -#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ - -/* - * More handy macros for PCMCIA - * - * Arg is socket number - */ -#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */ -#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */ -#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */ - -/* MECR register defines */ -#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ -#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ - -#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */ -#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */ -#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */ -#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */ - -#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ -#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ -#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ -#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ -#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ -#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ -#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ -#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ -#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ -#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ -#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ -#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ -#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ -#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ - -/* * Power Manager */ diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h b/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h deleted file mode 100644 index b87cecd9bbd..00000000000 --- a/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef PXA2XX_SPI_H_ -#define PXA2XX_SPI_H_ - -#define PXA2XX_CS_ASSERT (0x01) -#define PXA2XX_CS_DEASSERT (0x02) - -/* device.platform_data for SSP controller devices */ -struct pxa2xx_spi_master { - u32 clock_enable; - u16 num_chipselect; - u8 enable_dma; -}; - -/* spi_board_info.controller_data for SPI slave devices, - * copied to spi_device.platform_data ... mostly for dma tuning - */ -struct pxa2xx_spi_chip { - u8 tx_threshold; - u8 rx_threshold; - u8 dma_burst_size; - u32 timeout; - u8 enable_loopback; - int gpio_cs; - void (*cs_control)(u32 command); -}; - -extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info); - -#endif /*PXA2XX_SPI_H_*/ diff --git a/arch/arm/mach-pxa/include/mach/pxa300.h b/arch/arm/mach-pxa/include/mach/pxa300.h index 2f33076c9e4..733b6412c3d 100644 --- a/arch/arm/mach-pxa/include/mach/pxa300.h +++ b/arch/arm/mach-pxa/include/mach/pxa300.h @@ -1,8 +1,7 @@ #ifndef __MACH_PXA300_H #define __MACH_PXA300_H -#include <mach/hardware.h> -#include <mach/pxa3xx-regs.h> +#include <mach/pxa3xx.h> #include <mach/mfp-pxa300.h> #endif /* __MACH_PXA300_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa320.h b/arch/arm/mach-pxa/include/mach/pxa320.h index cab78e90327..b6204e470d8 100644 --- a/arch/arm/mach-pxa/include/mach/pxa320.h +++ b/arch/arm/mach-pxa/include/mach/pxa320.h @@ -1,8 +1,7 @@ #ifndef __MACH_PXA320_H #define __MACH_PXA320_H -#include <mach/hardware.h> -#include <mach/pxa3xx-regs.h> +#include <mach/pxa3xx.h> #include <mach/mfp-pxa320.h> #endif /* __MACH_PXA320_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h index 7d1a059b3d4..f4d48d20754 100644 --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h @@ -16,15 +16,6 @@ #include <mach/hardware.h> /* - * Static Chip Selects - */ - -#define PXA300_CS0_PHYS (0x00000000) /* PXA300/PXA310 _only_ */ -#define PXA300_CS1_PHYS (0x30000000) /* PXA300/PXA310 _only_ */ -#define PXA3xx_CS2_PHYS (0x10000000) -#define PXA3xx_CS3_PHYS (0x14000000) - -/* * Oscillator Configuration Register (OSCC) */ #define OSCC __REG(0x41350000) /* Oscillator Configuration Register */ @@ -47,7 +38,7 @@ #define PCMD(x) __REG(0x40F50110 + ((x) << 2)) /* - * Slave Power Managment Unit + * Slave Power Management Unit */ #define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */ #define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */ @@ -140,6 +131,7 @@ #define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ #define CKENA __REG(0x4134000C) /* A Clock Enable Register */ #define CKENB __REG(0x41340010) /* B Clock Enable Register */ +#define CKENC __REG(0x41340024) /* C Clock Enable Register */ #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ #define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ @@ -208,7 +200,7 @@ #define CKEN_MVED 43 /* < MVED clock enable */ /* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ -#define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */ -#define PXA320_CKEN_GRAPHICS 7 /* Graphics controller clock enable */ +#define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */ +#define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */ #endif /* __ASM_ARCH_PXA3XX_REGS_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx.h b/arch/arm/mach-pxa/include/mach/pxa3xx.h new file mode 100644 index 00000000000..6dd7fa163e2 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa3xx.h @@ -0,0 +1,13 @@ +#ifndef __MACH_PXA3XX_H +#define __MACH_PXA3XX_H + +#include <mach/hardware.h> +#include <mach/pxa3xx-regs.h> +#include <mach/irqs.h> + +extern void __init pxa3xx_map_io(void); +extern void __init pxa3xx_init_irq(void); + +#define pxa3xx_handle_irq ichp_handle_irq + +#endif /* __MACH_PXA3XX_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx_nand.h b/arch/arm/mach-pxa/include/mach/pxa3xx_nand.h deleted file mode 100644 index 3478eae32d8..00000000000 --- a/arch/arm/mach-pxa/include/mach/pxa3xx_nand.h +++ /dev/null @@ -1,63 +0,0 @@ -#ifndef __ASM_ARCH_PXA3XX_NAND_H -#define __ASM_ARCH_PXA3XX_NAND_H - -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> - -struct pxa3xx_nand_timing { - unsigned int tCH; /* Enable signal hold time */ - unsigned int tCS; /* Enable signal setup time */ - unsigned int tWH; /* ND_nWE high duration */ - unsigned int tWP; /* ND_nWE pulse time */ - unsigned int tRH; /* ND_nRE high duration */ - unsigned int tRP; /* ND_nRE pulse width */ - unsigned int tR; /* ND_nWE high to ND_nRE low for read */ - unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */ - unsigned int tAR; /* ND_ALE low to ND_nRE low delay */ -}; - -struct pxa3xx_nand_cmdset { - uint16_t read1; - uint16_t read2; - uint16_t program; - uint16_t read_status; - uint16_t read_id; - uint16_t erase; - uint16_t reset; - uint16_t lock; - uint16_t unlock; - uint16_t lock_status; -}; - -struct pxa3xx_nand_flash { - const struct pxa3xx_nand_timing *timing; /* NAND Flash timing */ - const struct pxa3xx_nand_cmdset *cmdset; - - uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */ - uint32_t page_size; /* Page size in bytes (PAGE_SZ) */ - uint32_t flash_width; /* Width of Flash memory (DWIDTH_M) */ - uint32_t dfc_width; /* Width of flash controller(DWIDTH_C) */ - uint32_t num_blocks; /* Number of physical blocks in Flash */ - uint32_t chip_id; -}; - -struct pxa3xx_nand_platform_data { - - /* the data flash bus is shared between the Static Memory - * Controller and the Data Flash Controller, the arbiter - * controls the ownership of the bus - */ - int enable_arbiter; - - /* allow platform code to keep OBM/bootloader defined NFC config */ - int keep_config; - - const struct mtd_partition *parts; - unsigned int nr_parts; - - const struct pxa3xx_nand_flash * flash; - size_t num_flash; -}; - -extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info); -#endif /* __ASM_ARCH_PXA3XX_NAND_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa930.h b/arch/arm/mach-pxa/include/mach/pxa930.h index d45f76a9b54..190363b98d0 100644 --- a/arch/arm/mach-pxa/include/mach/pxa930.h +++ b/arch/arm/mach-pxa/include/mach/pxa930.h @@ -1,8 +1,7 @@ #ifndef __MACH_PXA930_H #define __MACH_PXA930_H -#include <mach/hardware.h> -#include <mach/pxa3xx-regs.h> +#include <mach/pxa3xx.h> #include <mach/mfp-pxa930.h> #endif /* __MACH_PXA930_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa930_rotary.h b/arch/arm/mach-pxa/include/mach/pxa930_rotary.h deleted file mode 100644 index 053587caffd..00000000000 --- a/arch/arm/mach-pxa/include/mach/pxa930_rotary.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __ASM_ARCH_PXA930_ROTARY_H -#define __ASM_ARCH_PXA930_ROTARY_H - -/* NOTE: - * - * rotary can be either interpreted as a ralative input event (e.g. - * REL_WHEEL or REL_HWHEEL) or a specific key event (e.g. UP/DOWN - * or LEFT/RIGHT), depending on if up_key & down_key are assigned - * or rel_code is assigned a non-zero value. When all are non-zero, - * up_key and down_key will be preferred. - */ -struct pxa930_rotary_platform_data { - int up_key; - int down_key; - int rel_code; -}; - -void __init pxa930_set_rotarykey_info(struct pxa930_rotary_platform_data *info); - -#endif /* __ASM_ARCH_PXA930_ROTARY_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa930_trkball.h b/arch/arm/mach-pxa/include/mach/pxa930_trkball.h deleted file mode 100644 index 5e0789bc472..00000000000 --- a/arch/arm/mach-pxa/include/mach/pxa930_trkball.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __ASM_ARCH_PXA930_TRKBALL_H -#define __ASM_ARCH_PXA930_TRKBALL_H - -struct pxa930_trkball_platform_data { - int x_filter; - int y_filter; -}; - -#endif /* __ASM_ARCH_PXA930_TRKBALL_H */ - diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h deleted file mode 100644 index 6932720ba04..00000000000 --- a/arch/arm/mach-pxa/include/mach/pxafb.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/pxafb.h - * - * Support for the xscale frame buffer. - * - * Author: Jean-Frederic Clere - * Created: Sep 22, 2003 - * Copyright: jfclere@sinix.net - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/fb.h> -#include <mach/regs-lcd.h> - -/* - * Supported LCD connections - * - * bits 0 - 3: for LCD panel type: - * - * STN - for passive matrix - * DSTN - for dual scan passive matrix - * TFT - for active matrix - * - * bits 4 - 9 : for bus width - * bits 10-17 : for AC Bias Pin Frequency - * bit 18 : for output enable polarity - * bit 19 : for pixel clock edge - * bit 20 : for output pixel format when base is RGBT16 - */ -#define LCD_CONN_TYPE(_x) ((_x) & 0x0f) -#define LCD_CONN_WIDTH(_x) (((_x) >> 4) & 0x1f) - -#define LCD_TYPE_MASK 0xf -#define LCD_TYPE_UNKNOWN 0 -#define LCD_TYPE_MONO_STN 1 -#define LCD_TYPE_MONO_DSTN 2 -#define LCD_TYPE_COLOR_STN 3 -#define LCD_TYPE_COLOR_DSTN 4 -#define LCD_TYPE_COLOR_TFT 5 -#define LCD_TYPE_SMART_PANEL 6 -#define LCD_TYPE_MAX 7 - -#define LCD_MONO_STN_4BPP ((4 << 4) | LCD_TYPE_MONO_STN) -#define LCD_MONO_STN_8BPP ((8 << 4) | LCD_TYPE_MONO_STN) -#define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN) -#define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN) -#define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN) -#define LCD_COLOR_TFT_8BPP ((8 << 4) | LCD_TYPE_COLOR_TFT) -#define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT) -#define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT) -#define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL) -#define LCD_SMART_PANEL_16BPP ((16 << 4) | LCD_TYPE_SMART_PANEL) -#define LCD_SMART_PANEL_18BPP ((18 << 4) | LCD_TYPE_SMART_PANEL) - -#define LCD_AC_BIAS_FREQ(x) (((x) & 0xff) << 10) -#define LCD_BIAS_ACTIVE_HIGH (0 << 18) -#define LCD_BIAS_ACTIVE_LOW (1 << 18) -#define LCD_PCLK_EDGE_RISE (0 << 19) -#define LCD_PCLK_EDGE_FALL (1 << 19) -#define LCD_ALTERNATE_MAPPING (1 << 20) - -/* - * This structure describes the machine which we are running on. - * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine - * of linux/drivers/video/pxafb.c - */ -struct pxafb_mode_info { - u_long pixclock; - - u_short xres; - u_short yres; - - u_char bpp; - u_int cmap_greyscale:1, - depth:8, - unused:23; - - /* Parallel Mode Timing */ - u_char hsync_len; - u_char left_margin; - u_char right_margin; - - u_char vsync_len; - u_char upper_margin; - u_char lower_margin; - u_char sync; - - /* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details - * Note: - * 1. all parameters in nanosecond (ns) - * 2. a0cs{rd,wr}_set_hld are controlled by the same register bits - * in pxa27x and pxa3xx, initialize them to the same value or - * the larger one will be used - * 3. same to {rd,wr}_pulse_width - * - * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity - * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0 - * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD - */ - unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */ - unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */ - unsigned wr_pulse_width; /* L_PCLK_WR pulse width */ - unsigned rd_pulse_width; /* L_FCLK_RD pulse width */ - unsigned cmd_inh_time; /* Command Inhibit time between two writes */ - unsigned op_hold_time; /* Output Hold time from L_FCLK_RD negation */ -}; - -struct pxafb_mach_info { - struct pxafb_mode_info *modes; - unsigned int num_modes; - - unsigned int lcd_conn; - unsigned long video_mem_size; - - u_int fixed_modes:1, - cmap_inverse:1, - cmap_static:1, - unused:29; - - /* The following should be defined in LCCR0 - * LCCR0_Act or LCCR0_Pas Active or Passive - * LCCR0_Sngl or LCCR0_Dual Single/Dual panel - * LCCR0_Mono or LCCR0_Color Mono/Color - * LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode) - * LCCR0_DMADel(Tcpu) (optional) DMA request delay - * - * The following should not be defined in LCCR0: - * LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM - * LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB - */ - u_int lccr0; - /* The following should be defined in LCCR3 - * LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity - * LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type - * LCCR3_Acb(X) AB Bias pin frequency - * LCCR3_DPC (optional) Double Pixel Clock mode (untested) - * - * The following should not be defined in LCCR3 - * LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp - */ - u_int lccr3; - /* The following should be defined in LCCR4 - * LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2 - * - * All other bits in LCCR4 should be left alone. - */ - u_int lccr4; - void (*pxafb_backlight_power)(int); - void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *); - void (*smart_update)(struct fb_info *); -}; -void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info); -void set_pxa_fb_parent(struct device *parent_dev); -unsigned long pxafb_get_hsync_time(struct device *dev); - -extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int); -extern int pxafb_smart_flush(struct fb_info *info); diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h deleted file mode 100644 index ad23e74b762..00000000000 --- a/arch/arm/mach-pxa/include/mach/regs-intc.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __ASM_MACH_REGS_INTC_H -#define __ASM_MACH_REGS_INTC_H - -#include <mach/hardware.h> - -/* - * Interrupt Controller - */ - -#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ -#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ -#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ -#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ -#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ -#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ - -#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ -#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ -#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ -#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ -#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ - -#endif /* __ASM_MACH_REGS_INTC_H */ diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h index a3e5f86ef67..628819995c5 100644 --- a/arch/arm/mach-pxa/include/mach/regs-ost.h +++ b/arch/arm/mach-pxa/include/mach/regs-ost.h @@ -7,17 +7,17 @@ * OS Timer & Match Registers */ -#define OSMR0 __REG(0x40A00000) /* */ -#define OSMR1 __REG(0x40A00004) /* */ -#define OSMR2 __REG(0x40A00008) /* */ -#define OSMR3 __REG(0x40A0000C) /* */ -#define OSMR4 __REG(0x40A00080) /* */ -#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ -#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ -#define OMCR4 __REG(0x40A000C0) /* */ -#define OSSR __REG(0x40A00014) /* OS Timer Status Register */ -#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ -#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ +#define OSMR0 io_p2v(0x40A00000) /* */ +#define OSMR1 io_p2v(0x40A00004) /* */ +#define OSMR2 io_p2v(0x40A00008) /* */ +#define OSMR3 io_p2v(0x40A0000C) /* */ +#define OSMR4 io_p2v(0x40A00080) /* */ +#define OSCR io_p2v(0x40A00010) /* OS Timer Counter Register */ +#define OSCR4 io_p2v(0x40A00040) /* OS Timer Counter Register */ +#define OMCR4 io_p2v(0x40A000C0) /* */ +#define OSSR io_p2v(0x40A00014) /* OS Timer Status Register */ +#define OWER io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */ +#define OIER io_p2v(0x40A0001C) /* OS Timer Interrupt Enable Register */ #define OSSR_M3 (1 << 3) /* Match status channel 3 */ #define OSSR_M2 (1 << 2) /* Match status channel 2 */ diff --git a/arch/arm/mach-pxa/include/mach/regs-ssp.h b/arch/arm/mach-pxa/include/mach/regs-ssp.h deleted file mode 100644 index 6a2ed35acd5..00000000000 --- a/arch/arm/mach-pxa/include/mach/regs-ssp.h +++ /dev/null @@ -1,134 +0,0 @@ -#ifndef __ASM_ARCH_REGS_SSP_H -#define __ASM_ARCH_REGS_SSP_H - -/* - * SSP Serial Port Registers - * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different. - * PXA255, PXA26x and PXA27x have extra ports, registers and bits. - */ - -#define SSCR0 (0x00) /* SSP Control Register 0 */ -#define SSCR1 (0x04) /* SSP Control Register 1 */ -#define SSSR (0x08) /* SSP Status Register */ -#define SSITR (0x0C) /* SSP Interrupt Test Register */ -#define SSDR (0x10) /* SSP Data Write/Data Read Register */ - -#define SSTO (0x28) /* SSP Time Out Register */ -#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */ -#define SSTSA (0x30) /* SSP Tx Timeslot Active */ -#define SSRSA (0x34) /* SSP Rx Timeslot Active */ -#define SSTSS (0x38) /* SSP Timeslot Status */ -#define SSACD (0x3C) /* SSP Audio Clock Divider */ - -#if defined(CONFIG_PXA3xx) -#define SSACDD (0x40) /* SSP Audio Clock Dither Divider */ -#endif - -/* Common PXA2xx bits first */ -#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ -#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ -#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ -#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ -#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ -#define SSCR0_National (0x2 << 4) /* National Microwire */ -#define SSCR0_ECS (1 << 6) /* External clock select */ -#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ - -#if defined(CONFIG_PXA25x) -#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ -#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ -#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) -#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ -#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ -#endif - -#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) -#define SSCR0_EDSS (1 << 20) /* Extended data size select */ -#define SSCR0_NCS (1 << 21) /* Network clock select */ -#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ -#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ -#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ -#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ -#define SSCR0_ACS (1 << 30) /* Audio clock select */ -#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ -#endif - -#if defined(CONFIG_PXA3xx) -#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */ -#endif - -#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ -#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ -#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ -#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ -#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ -#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ -#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ -#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ -#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ -#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ - -#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ -#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ -#define SSSR_BSY (1 << 4) /* SSP Busy */ -#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ -#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ -#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ - -#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */ -#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */ -#define SSCR0_NCS (1 << 21) /* Network Clock Select */ -#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */ - -/* extra bits in PXA255, PXA26x and PXA27x SSP ports */ -#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ -#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */ -#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */ -#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */ -#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */ -#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */ -#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */ -#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */ -#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */ -#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */ -#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */ -#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */ -#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */ -#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */ -#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */ -#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */ -#define SSCR1_IFS (1 << 16) /* Invert Frame Signal */ -#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */ -#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */ - -#define SSSR_BCE (1 << 23) /* Bit Count Error */ -#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */ -#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */ -#define SSSR_EOC (1 << 20) /* End Of Chain */ -#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ -#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ - -#if defined(CONFIG_PXA3xx) -#define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */ -#define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */ -#endif - -#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ -#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ -#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ -#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ -#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ -#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ -#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ -#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ -#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */ - -#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ -#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ -#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ -#if defined(CONFIG_PXA3xx) -#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */ -#endif - - -#endif /* __ASM_ARCH_REGS_SSP_H */ diff --git a/arch/arm/mach-pxa/include/mach/regs-u2d.h b/arch/arm/mach-pxa/include/mach/regs-u2d.h new file mode 100644 index 00000000000..c15c0c57de0 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-u2d.h @@ -0,0 +1,200 @@ +#ifndef __ASM_ARCH_PXA3xx_U2D_H +#define __ASM_ARCH_PXA3xx_U2D_H + +#include <mach/bitfield.h> + +/* + * USB2 device controller registers and bits definitions + */ +#define U2DCR (0x0000) /* U2D Control Register */ +#define U2DCR_NDC (1 << 31) /* NAK During Config */ +#define U2DCR_HSTC (0x7 << 28) /* High Speed Timeout Calibration */ +#define U2DCR_SPEOREN (1 << 27) /* Short Packet EOR INTR generation Enable */ +#define U2DCR_FSTC (0x7 << 24) /* Full Speed Timeout Calibration */ +#define U2DCR_UCLKOVR (1 << 22) /* UTM Clock Override */ +#define U2DCR_ABP (1 << 21) /* Application Bus Power */ +#define U2DCR_ADD (1 << 20) /* Application Device Disconnect */ +#define U2DCR_CC (1 << 19) /* Configuration Change */ +#define U2DCR_HS (1 << 18) /* High Speed USB Detection */ +#define U2DCR_SMAC (1 << 17) /* Switch Endpoint Memory to Active Configuration */ +#define U2DCR_DWRE (1 << 16) /* Device Remote Wake-up Feature */ +#define U2DCR_ACN (0xf << 12) /* Active U2D Configuration Number */ +#define U2DCR_AIN (0xf << 8) /* Active U2D Interface Number */ +#define U2DCR_AAISN (0xf << 4) /* Active U2D Alternate Interface Setting Number */ +#define U2DCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */ +#define U2DCR_UDR (1 << 2) /* U2D Resume */ +#define U2DCR_UDA (1 << 1) /* U2D Active */ +#define U2DCR_UDE (1 << 0) /* U2D Enable */ + +#define U2DICR (0x0004) /* U2D Interrupt Control Register */ +#define U2DISR (0x000C) /* U2D Interrupt Status Register */ +#define U2DINT_CC (1 << 31) /* Interrupt - Configuration Change */ +#define U2DINT_SOF (1 << 30) /* Interrupt - SOF */ +#define U2DINT_USOF (1 << 29) /* Interrupt - micro SOF */ +#define U2DINT_RU (1 << 28) /* Interrupt - Resume */ +#define U2DINT_SU (1 << 27) /* Interrupt - Suspend */ +#define U2DINT_RS (1 << 26) /* Interrupt - Reset */ +#define U2DINT_DPE (1 << 25) /* Interrupt - Data Packet Error */ +#define U2DINT_FIFOERR (0x4) /* Interrupt - endpoint FIFO error */ +#define U2DINT_PACKETCMP (0x2) /* Interrupt - endpoint packet complete */ +#define U2DINT_SPACKETCMP (0x1) /* Interrupt - endpoint short packet complete */ + +#define U2DFNR (0x0014) /* U2D Frame Number Register */ + +#define U2DINT(n, intr) (((intr) & 0x07) << (((n) & 0x07) * 3)) +#define U2DICR2 (0x0008) /* U2D Interrupt Control Register 2 */ +#define U2DISR2 (0x0010) /* U2D Interrupt Status Register 2 */ + +#define U2DOTGCR (0x0020) /* U2D OTG Control Register */ +#define U2DOTGCR_OTGEN (1 << 31) /* On-The-Go Enable */ +#define U2DOTGCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocal Port Support */ +#define U2DOTGCR_AHNP (1 << 29) /* A-device Host Negotiation Protocal Support */ +#define U2DOTGCR_BHNP (1 << 28) /* B-device Host Negotiation Protocal Enable */ + +#ifdef CONFIG_CPU_PXA930 +#define U2DOTGCR_LPA (1 << 15) /* ULPI low power mode active */ +#define U2DOTGCR_IESI (1 << 13) /* OTG interrupt Enable */ +#define U2DOTGCR_ISSI (1 << 12) /* OTG interrupt status */ +#endif + +#define U2DOTGCR_CKAF (1 << 5) /* Carkit Mode Alternate Function Select */ +#define U2DOTGCR_UTMID (1 << 4) /* UTMI Interface Disable */ +#define U2DOTGCR_ULAF (1 << 3) /* ULPI Mode Alternate Function Select */ +#define U2DOTGCR_SMAF (1 << 2) /* Serial Mode Alternate Function Select */ +#define U2DOTGCR_RTSM (1 << 1) /* Return to Synchronous Mode (ULPI Mode) */ +#define U2DOTGCR_ULE (1 << 0) /* ULPI Wrapper Enable */ + +#define U2DOTGICR (0x0024) /* U2D OTG Interrupt Control Register */ +#define U2DOTGISR (0x0028) /* U2D OTG Interrupt Status Register */ + +#define U2DOTGINT_SF (1 << 17) /* OTG Set Feature Command Received */ +#define U2DOTGINT_SI (1 << 16) /* OTG Interrupt */ +#define U2DOTGINT_RLS1 (1 << 14) /* RXCMD Linestate[1] Change Interrupt Rise */ +#define U2DOTGINT_RLS0 (1 << 13) /* RXCMD Linestate[0] Change Interrupt Rise */ +#define U2DOTGINT_RID (1 << 12) /* RXCMD OTG ID Change Interrupt Rise */ +#define U2DOTGINT_RSE (1 << 11) /* RXCMD OTG Session End Interrupt Rise */ +#define U2DOTGINT_RSV (1 << 10) /* RXCMD OTG Session Valid Interrupt Rise */ +#define U2DOTGINT_RVV (1 << 9) /* RXCMD OTG Vbus Valid Interrupt Rise */ +#define U2DOTGINT_RCK (1 << 8) /* RXCMD Carkit Interrupt Rise */ +#define U2DOTGINT_FLS1 (1 << 6) /* RXCMD Linestate[1] Change Interrupt Fall */ +#define U2DOTGINT_FLS0 (1 << 5) /* RXCMD Linestate[0] Change Interrupt Fall */ +#define U2DOTGINT_FID (1 << 4) /* RXCMD OTG ID Change Interrupt Fall */ +#define U2DOTGINT_FSE (1 << 3) /* RXCMD OTG Session End Interrupt Fall */ +#define U2DOTGINT_FSV (1 << 2) /* RXCMD OTG Session Valid Interrupt Fall */ +#define U2DOTGINT_FVV (1 << 1) /* RXCMD OTG Vbus Valid Interrupt Fall */ +#define U2DOTGINT_FCK (1 << 0) /* RXCMD Carkit Interrupt Fall */ + +#define U2DOTGUSR (0x002C) /* U2D OTG ULPI Status Register */ +#define U2DOTGUSR_LPA (1 << 31) /* ULPI Low Power Mode Active */ +#define U2DOTGUSR_S6A (1 << 30) /* ULPI Serial Mode (6-pin) Active */ +#define U2DOTGUSR_S3A (1 << 29) /* ULPI Serial Mode (3-pin) Active */ +#define U2DOTGUSR_CKA (1 << 28) /* ULPI Car Kit Mode Active */ +#define U2DOTGUSR_LS1 (1 << 6) /* RXCMD Linestate 1 Status */ +#define U2DOTGUSR_LS0 (1 << 5) /* RXCMD Linestate 0 Status */ +#define U2DOTGUSR_ID (1 << 4) /* OTG IDGnd Status */ +#define U2DOTGUSR_SE (1 << 3) /* OTG Session End Status */ +#define U2DOTGUSR_SV (1 << 2) /* OTG Session Valid Status */ +#define U2DOTGUSR_VV (1 << 1) /* OTG Vbus Valid Status */ +#define U2DOTGUSR_CK (1 << 0) /* Carkit Interrupt Status */ + +#define U2DOTGUCR (0x0030) /* U2D OTG ULPI Control Register */ +#define U2DOTGUCR_RUN (1 << 25) /* RUN */ +#define U2DOTGUCR_RNW (1 << 24) /* Read or Write operation */ +#define U2DOTGUCR_ADDR (0x3f << 16) /* Address of the ULPI PHY register */ +#define U2DOTGUCR_WDATA (0xff << 8) /* The data for a WRITE command */ +#define U2DOTGUCR_RDATA (0xff << 0) /* The data for a READ command */ + +#define U2DP3CR (0x0034) /* U2D Port 3 Control Register */ +#define U2DP3CR_P2SS (0x3 << 8) /* Host Port 2 Serial Mode Select */ +#define U2DP3CR_P3SS (0x7 << 4) /* Host Port 3 Serial Mode Select */ +#define U2DP3CR_VPVMBEN (0x1 << 2) /* Host Port 3 Vp/Vm Block Enable */ +#define U2DP3CR_CFG (0x3 << 0) /* Host Port 3 Configuration */ + +#define U2DCSR0 (0x0100) /* U2D Control/Status Register - Endpoint 0 */ +#define U2DCSR0_IPA (1 << 8) /* IN Packet Adjusted */ +#define U2DCSR0_SA (1 << 7) /* SETUP Active */ +#define U2DCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ +#define U2DCSR0_FST (1 << 5) /* Force Stall */ +#define U2DCSR0_SST (1 << 4) /* Send Stall */ +#define U2DCSR0_DME (1 << 3) /* DMA Enable */ +#define U2DCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ +#define U2DCSR0_IPR (1 << 1) /* IN Packet Ready */ +#define U2DCSR0_OPC (1 << 0) /* OUT Packet Complete */ + +#define U2DCSR(x) (0x0100 + ((x) << 2)) /* U2D Control/Status Register - Endpoint x */ +#define U2DCSR_BF (1 << 10) /* Buffer Full, for OUT eps */ +#define U2DCSR_BE (1 << 10) /* Buffer Empty, for IN eps */ +#define U2DCSR_DPE (1 << 9) /* Data Packet Error, for ISO eps only */ +#define U2DCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ +#define U2DCSR_SP (1 << 7) /* Short Packet Control/Status, for OUT eps only, readonly */ +#define U2DCSR_BNE (1 << 6) /* Buffer Not Empty, for OUT eps */ +#define U2DCSR_BNF (1 << 6) /* Buffer Not Full, for IN eps */ +#define U2DCSR_FST (1 << 5) /* Force STALL, write 1 set */ +#define U2DCSR_SST (1 << 4) /* Sent STALL, write 1 clear */ +#define U2DCSR_DME (1 << 3) /* DMA Enable */ +#define U2DCSR_TRN (1 << 2) /* Tx/Rx NAK, write 1 clear */ +#define U2DCSR_PC (1 << 1) /* Packet Complete, write 1 clear */ +#define U2DCSR_FS (1 << 0) /* FIFO needs Service */ + +#define U2DBCR0 (0x0200) /* U2D Byte Count Register - Endpoint 0 */ +#define U2DBCR(x) (0x0200 + ((x) << 2)) /* U2D Byte Count Register - Endpoint x */ + +#define U2DDR0 (0x0300) /* U2D Data Register - Endpoint 0 */ + +#define U2DEPCR(x) (0x0400 + ((x) << 2)) /* U2D Configuration Register - Endpoint x */ +#define U2DEPCR_EE (1 << 0) /* Endpoint Enable */ +#define U2DEPCR_BS_MASK (0x3FE) /* Buffer Size, BS*8=FIFO size, max 8184B = 8KB */ + +#define U2DSCA (0x0500) /* U2D Setup Command Address */ +#define U2DSCA_VALUE (0x0120) + +#define U2DEN0 (0x0504) /* U2D Endpoint Information Register - Endpoint 0 */ +#define U2DEN(x) (0x0504 + ((x) << 2)) /* U2D Endpoint Information Register - Endpoint x */ + +/* U2DMA registers */ +#define U2DMACSR0 (0x1000) /* U2DMA Control/Status Register - Channel 0 */ +#define U2DMACSR(x) (0x1000 + ((x) << 2)) /* U2DMA Control/Status Register - Channel x */ +#define U2DMACSR_RUN (1 << 31) /* Run Bit (read / write) */ +#define U2DMACSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ +#define U2DMACSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ +#define U2DMACSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ +#define U2DMACSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ +#define U2DMACSR_RASIRQEN (1 << 23) /* Request After Cnannel Stopped Interrupt Enable */ +#define U2DMACSR_MASKRUN (1 << 22) /* Mask Run */ +#define U2DMACSR_SCEMC (3 << 18) /* System Bus Split Completion Error Message Class */ +#define U2DMACSR_SCEMI (0x1f << 13) /* System Bus Split Completion Error Message Index */ +#define U2DMACSR_BUSERRTYPE (7 << 10) /* PX Bus Error Type */ +#define U2DMACSR_EORINTR (1 << 9) /* End Of Receive */ +#define U2DMACSR_REQPEND (1 << 8) /* Request Pending */ +#define U2DMACSR_RASINTR (1 << 4) /* Request After Channel Stopped (read / write 1 clear) */ +#define U2DMACSR_STOPINTR (1 << 3) /* Stop Interrupt (read only) */ +#define U2DMACSR_ENDINTR (1 << 2) /* End Interrupt (read / write 1 clear) */ +#define U2DMACSR_STARTINTR (1 << 1) /* Start Interrupt (read / write 1 clear) */ +#define U2DMACSR_BUSERRINTR (1 << 0) /* Bus Error Interrupt (read / write 1 clear) */ + +#define U2DMACR (0x1080) /* U2DMA Control Register */ +#define U2DMAINT (0x10F0) /* U2DMA Interrupt Register */ + +#define U2DMABR0 (0x1100) /* U2DMA Branch Register - Channel 0 */ +#define U2DMABR(x) (0x1100 + (x) << 2) /* U2DMA Branch Register - Channel x */ + +#define U2DMADADR0 (0x1200) /* U2DMA Descriptor Address Register - Channel 0 */ +#define U2DMADADR(x) (0x1200 + (x) * 0x10) /* U2DMA Descriptor Address Register - Channel x */ + +#define U2DMADADR_STOP (1U << 0) + +#define U2DMASADR0 (0x1204) /* U2DMA Source Address Register - Channel 0 */ +#define U2DMASADR(x) (0x1204 + (x) * 0x10) /* U2DMA Source Address Register - Channel x */ +#define U2DMATADR0 (0x1208) /* U2DMA Target Address Register - Channel 0 */ +#define U2DMATADR(x) (0x1208 + (x) * 0x10) /* U2DMA Target Address Register - Channel x */ + +#define U2DMACMDR0 (0x120C) /* U2DMA Command Address Register - Channel 0 */ +#define U2DMACMDR(x) (0x120C + (x) * 0x10) /* U2DMA Command Address Register - Channel x */ + +#define U2DMACMDR_XFRDIS (1 << 31) /* Transfer Direction */ +#define U2DMACMDR_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ +#define U2DMACMDR_ENDIRQEN (1 << 21) /* End Interrupt Enable */ +#define U2DMACMDR_PACKCOMP (1 << 13) /* Packet Complete */ +#define U2DMACMDR_LEN (0x07ff) /* length mask (max = 2K - 1) */ + +#endif /* __ASM_ARCH_PXA3xx_U2D_H */ diff --git a/arch/arm/mach-pxa/include/mach/sharpsl.h b/arch/arm/mach-pxa/include/mach/sharpsl.h deleted file mode 100644 index 8242e14a44f..00000000000 --- a/arch/arm/mach-pxa/include/mach/sharpsl.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * SharpSL SSP Driver - */ - -unsigned long corgi_ssp_ads7846_putget(unsigned long); -unsigned long corgi_ssp_ads7846_get(void); -void corgi_ssp_ads7846_put(unsigned long data); -void corgi_ssp_ads7846_lock(void); -void corgi_ssp_ads7846_unlock(void); -void corgi_ssp_lcdtg_send (unsigned char adrs, unsigned char data); -void corgi_ssp_blduty_set(int duty); -int corgi_ssp_max1111_get(unsigned long data); - -/* - * SharpSL Touchscreen Driver - */ - -struct corgits_machinfo { - unsigned long (*get_hsync_invperiod)(void); - void (*put_hsync)(void); - void (*wait_hsync)(void); -}; - - -/* - * SharpSL Backlight - */ -extern void corgibl_limit_intensity(int limit); -extern void corgi_lcd_limit_intensity(int limit); - - -/* - * SharpSL Battery/PM Driver - */ -extern void sharpsl_battery_kick(void); diff --git a/arch/arm/mach-pxa/include/mach/sharpsl_pm.h b/arch/arm/mach-pxa/include/mach/sharpsl_pm.h new file mode 100644 index 00000000000..905be6755f0 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/sharpsl_pm.h @@ -0,0 +1,113 @@ +/* + * SharpSL Battery/PM Driver + * + * Copyright (c) 2004-2005 Richard Purdie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef _MACH_SHARPSL_PM +#define _MACH_SHARPSL_PM + +struct sharpsl_charger_machinfo { + void (*init)(void); + void (*exit)(void); + int gpio_acin; + int gpio_batfull; + int batfull_irq; + int gpio_batlock; + int gpio_fatal; + void (*discharge)(int); + void (*discharge1)(int); + void (*charge)(int); + void (*measure_temp)(int); + void (*presuspend)(void); + void (*postsuspend)(void); + void (*earlyresume)(void); + unsigned long (*read_devdata)(int); +#define SHARPSL_BATT_VOLT 1 +#define SHARPSL_BATT_TEMP 2 +#define SHARPSL_ACIN_VOLT 3 +#define SHARPSL_STATUS_ACIN 4 +#define SHARPSL_STATUS_LOCK 5 +#define SHARPSL_STATUS_CHRGFULL 6 +#define SHARPSL_STATUS_FATAL 7 + unsigned long (*charger_wakeup)(void); + int (*should_wakeup)(unsigned int resume_on_alarm); + void (*backlight_limit)(int); + int (*backlight_get_status) (void); + int charge_on_volt; + int charge_on_temp; + int charge_acin_high; + int charge_acin_low; + int fatal_acin_volt; + int fatal_noacin_volt; + int bat_levels; + struct battery_thresh *bat_levels_noac; + struct battery_thresh *bat_levels_acin; + struct battery_thresh *bat_levels_noac_bl; + struct battery_thresh *bat_levels_acin_bl; + int status_high_acin; + int status_low_acin; + int status_high_noac; + int status_low_noac; +}; + +struct battery_thresh { + int voltage; + int percentage; +}; + +struct battery_stat { + int ac_status; /* APM AC Present/Not Present */ + int mainbat_status; /* APM Main Battery Status */ + int mainbat_percent; /* Main Battery Percentage Charge */ + int mainbat_voltage; /* Main Battery Voltage */ +}; + +struct sharpsl_pm_status { + struct device *dev; + struct timer_list ac_timer; + struct timer_list chrg_full_timer; + + int charge_mode; +#define CHRG_ERROR (-1) +#define CHRG_OFF (0) +#define CHRG_ON (1) +#define CHRG_DONE (2) + + unsigned int flags; +#define SHARPSL_SUSPENDED (1 << 0) /* Device is Suspended */ +#define SHARPSL_ALARM_ACTIVE (1 << 1) /* Alarm is for charging event (not user) */ +#define SHARPSL_BL_LIMIT (1 << 2) /* Backlight Intensity Limited */ +#define SHARPSL_APM_QUEUED (1 << 3) /* APM Event Queued */ +#define SHARPSL_DO_OFFLINE_CHRG (1 << 4) /* Trigger the offline charger */ + + int full_count; + unsigned long charge_start_time; + struct sharpsl_charger_machinfo *machinfo; + struct battery_stat battstat; +}; + +extern struct sharpsl_pm_status sharpsl_pm; + +extern struct battery_thresh sharpsl_battery_levels_acin[]; +extern struct battery_thresh sharpsl_battery_levels_noac[]; + +#define SHARPSL_LED_ERROR 2 +#define SHARPSL_LED_ON 1 +#define SHARPSL_LED_OFF 0 + +void sharpsl_battery_kick(void); +void sharpsl_pm_led(int val); + +/* MAX1111 Channel Definitions */ +#define MAX1111_BATT_VOLT 4u +#define MAX1111_BATT_TEMP 2u +#define MAX1111_ACIN_VOLT 6u +int sharpsl_pm_pxa_read_max1111(int channel); + +void corgi_lcd_limit_intensity(int limit); +#endif diff --git a/arch/arm/mach-pxa/include/mach/smemc.h b/arch/arm/mach-pxa/include/mach/smemc.h new file mode 100644 index 00000000000..b802f285fe0 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/smemc.h @@ -0,0 +1,75 @@ +/* + * Static memory controller register definitions for PXA CPUs + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __SMEMC_REGS_H +#define __SMEMC_REGS_H + +#define PXA2XX_SMEMC_BASE 0x48000000 +#define PXA3XX_SMEMC_BASE 0x4a000000 +#define SMEMC_VIRT IOMEM(0xf6000000) + +#define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */ +#define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */ +#define MSC0 (SMEMC_VIRT + 0x08) /* Static Memory Control Register 0 */ +#define MSC1 (SMEMC_VIRT + 0x0C) /* Static Memory Control Register 1 */ +#define MSC2 (SMEMC_VIRT + 0x10) /* Static Memory Control Register 2 */ +#define MECR (SMEMC_VIRT + 0x14) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ +#define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ +#define SXCNFG (SMEMC_VIRT + 0x1C) /* Synchronous Static Memory Control Register */ +#define SXMRS (SMEMC_VIRT + 0x24) /* MRS value to be written to Synchronous Flash or SMROM */ +#define MCMEM0 (SMEMC_VIRT + 0x28) /* Card interface Common Memory Space Socket 0 Timing */ +#define MCMEM1 (SMEMC_VIRT + 0x2C) /* Card interface Common Memory Space Socket 1 Timing */ +#define MCATT0 (SMEMC_VIRT + 0x30) /* Card interface Attribute Space Socket 0 Timing Configuration */ +#define MCATT1 (SMEMC_VIRT + 0x34) /* Card interface Attribute Space Socket 1 Timing Configuration */ +#define MCIO0 (SMEMC_VIRT + 0x38) /* Card interface I/O Space Socket 0 Timing Configuration */ +#define MCIO1 (SMEMC_VIRT + 0x3C) /* Card interface I/O Space Socket 1 Timing Configuration */ +#define MDMRS (SMEMC_VIRT + 0x40) /* MRS value to be written to SDRAM */ +#define BOOT_DEF (SMEMC_VIRT + 0x44) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ +#define MEMCLKCFG (SMEMC_VIRT + 0x68) /* Clock Configuration */ +#define CSADRCFG0 (SMEMC_VIRT + 0x80) /* Address Configuration Register for CS0 */ +#define CSADRCFG1 (SMEMC_VIRT + 0x84) /* Address Configuration Register for CS1 */ +#define CSADRCFG2 (SMEMC_VIRT + 0x88) /* Address Configuration Register for CS2 */ +#define CSADRCFG3 (SMEMC_VIRT + 0x8C) /* Address Configuration Register for CS3 */ +#define CSMSADRCFG (SMEMC_VIRT + 0xA0) /* Chip Select Configuration Register */ + +/* + * More handy macros for PCMCIA + * + * Arg is socket number + */ +#define MCMEM(s) (SMEMC_VIRT + 0x28 + ((s)<<2)) /* Card interface Common Memory Space Socket s Timing */ +#define MCATT(s) (SMEMC_VIRT + 0x30 + ((s)<<2)) /* Card interface Attribute Space Socket s Timing Configuration */ +#define MCIO(s) (SMEMC_VIRT + 0x38 + ((s)<<2)) /* Card interface I/O Space Socket s Timing Configuration */ + +/* MECR register defines */ +#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ +#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ + +#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */ +#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */ +#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */ +#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */ + +#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ +#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ +#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ +#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ +#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ +#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ +#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ +#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ +#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ +#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ +#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ +#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ +#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ +#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ + +#endif diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h index fa1998caa78..25c9f62e46a 100644 --- a/arch/arm/mach-pxa/include/mach/spitz.h +++ b/arch/arm/mach-pxa/include/mach/spitz.h @@ -15,8 +15,8 @@ #define __ASM_ARCH_SPITZ_H 1 #endif +#include "irqs.h" /* PXA_NR_BUILTIN_GPIO, PXA_GPIO_TO_IRQ */ #include <linux/fb.h> -#include <linux/gpio.h> /* Spitz/Akita GPIOs */ @@ -108,7 +108,7 @@ #define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) #define SPITZ_SCP_SUS_SET 0 -#define SPITZ_SCP_GPIO_BASE (NR_BUILTIN_GPIO) +#define SPITZ_SCP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) #define SPITZ_GPIO_LED_GREEN (SPITZ_SCP_GPIO_BASE + 0) #define SPITZ_GPIO_JK_B (SPITZ_SCP_GPIO_BASE + 1) #define SPITZ_GPIO_CHRG_ON (SPITZ_SCP_GPIO_BASE + 2) @@ -140,7 +140,7 @@ SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) #define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1) -#define SPITZ_SCP2_GPIO_BASE (NR_BUILTIN_GPIO + 12) +#define SPITZ_SCP2_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12) #define SPITZ_GPIO_IR_ON (SPITZ_SCP2_GPIO_BASE + 0) #define SPITZ_GPIO_AKIN_PULLUP (SPITZ_SCP2_GPIO_BASE + 1) #define SPITZ_GPIO_RESERVED_1 (SPITZ_SCP2_GPIO_BASE + 2) @@ -152,7 +152,7 @@ #define SPITZ_GPIO_MIC_BIAS (SPITZ_SCP2_GPIO_BASE + 8) /* Akita IO Expander GPIOs */ -#define AKITA_IOEXP_GPIO_BASE (NR_BUILTIN_GPIO + 12) +#define AKITA_IOEXP_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12) #define AKITA_GPIO_RESERVED_0 (AKITA_IOEXP_GPIO_BASE + 0) #define AKITA_GPIO_RESERVED_1 (AKITA_IOEXP_GPIO_BASE + 1) #define AKITA_GPIO_MIC_BIAS (AKITA_IOEXP_GPIO_BASE + 2) @@ -164,28 +164,26 @@ /* Spitz IRQ Definitions */ -#define SPITZ_IRQ_GPIO_KEY_INT IRQ_GPIO(SPITZ_GPIO_KEY_INT) -#define SPITZ_IRQ_GPIO_AC_IN IRQ_GPIO(SPITZ_GPIO_AC_IN) -#define SPITZ_IRQ_GPIO_AK_INT IRQ_GPIO(SPITZ_GPIO_AK_INT) -#define SPITZ_IRQ_GPIO_HP_IN IRQ_GPIO(SPITZ_GPIO_HP_IN) -#define SPITZ_IRQ_GPIO_TP_INT IRQ_GPIO(SPITZ_GPIO_TP_INT) -#define SPITZ_IRQ_GPIO_SYNC IRQ_GPIO(SPITZ_GPIO_SYNC) -#define SPITZ_IRQ_GPIO_ON_KEY IRQ_GPIO(SPITZ_GPIO_ON_KEY) -#define SPITZ_IRQ_GPIO_SWA IRQ_GPIO(SPITZ_GPIO_SWA) -#define SPITZ_IRQ_GPIO_SWB IRQ_GPIO(SPITZ_GPIO_SWB) -#define SPITZ_IRQ_GPIO_BAT_COVER IRQ_GPIO(SPITZ_GPIO_BAT_COVER) -#define SPITZ_IRQ_GPIO_FATAL_BAT IRQ_GPIO(SPITZ_GPIO_FATAL_BAT) -#define SPITZ_IRQ_GPIO_CO IRQ_GPIO(SPITZ_GPIO_CO) -#define SPITZ_IRQ_GPIO_CF_IRQ IRQ_GPIO(SPITZ_GPIO_CF_IRQ) -#define SPITZ_IRQ_GPIO_CF_CD IRQ_GPIO(SPITZ_GPIO_CF_CD) -#define SPITZ_IRQ_GPIO_CF2_IRQ IRQ_GPIO(SPITZ_GPIO_CF2_IRQ) -#define SPITZ_IRQ_GPIO_nSD_INT IRQ_GPIO(SPITZ_GPIO_nSD_INT) -#define SPITZ_IRQ_GPIO_nSD_DETECT IRQ_GPIO(SPITZ_GPIO_nSD_DETECT) +#define SPITZ_IRQ_GPIO_KEY_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_KEY_INT) +#define SPITZ_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(SPITZ_GPIO_AC_IN) +#define SPITZ_IRQ_GPIO_AK_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_AK_INT) +#define SPITZ_IRQ_GPIO_HP_IN PXA_GPIO_TO_IRQ(SPITZ_GPIO_HP_IN) +#define SPITZ_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_TP_INT) +#define SPITZ_IRQ_GPIO_SYNC PXA_GPIO_TO_IRQ(SPITZ_GPIO_SYNC) +#define SPITZ_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(SPITZ_GPIO_ON_KEY) +#define SPITZ_IRQ_GPIO_SWA PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWA) +#define SPITZ_IRQ_GPIO_SWB PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWB) +#define SPITZ_IRQ_GPIO_BAT_COVER PXA_GPIO_TO_IRQ(SPITZ_GPIO_BAT_COVER) +#define SPITZ_IRQ_GPIO_FATAL_BAT PXA_GPIO_TO_IRQ(SPITZ_GPIO_FATAL_BAT) +#define SPITZ_IRQ_GPIO_CO PXA_GPIO_TO_IRQ(SPITZ_GPIO_CO) +#define SPITZ_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_IRQ) +#define SPITZ_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_CD) +#define SPITZ_IRQ_GPIO_CF2_IRQ PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF2_IRQ) +#define SPITZ_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_INT) +#define SPITZ_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_DETECT) /* * Shared data structures */ -extern struct platform_device spitzscoop_device; -extern struct platform_device spitzscoop2_device; extern struct platform_device spitzssp_device; extern struct sharpsl_charger_machinfo spitz_pm_machinfo; diff --git a/arch/arm/mach-pxa/include/mach/ssp.h b/arch/arm/mach-pxa/include/mach/ssp.h deleted file mode 100644 index cb5cb766f0f..00000000000 --- a/arch/arm/mach-pxa/include/mach/ssp.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * ssp.h - * - * Copyright (C) 2003 Russell King, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This driver supports the following PXA CPU/SSP ports:- - * - * PXA250 SSP - * PXA255 SSP, NSSP - * PXA26x SSP, NSSP, ASSP - * PXA27x SSP1, SSP2, SSP3 - * PXA3xx SSP1, SSP2, SSP3, SSP4 - */ - -#ifndef __ASM_ARCH_SSP_H -#define __ASM_ARCH_SSP_H - -#include <linux/list.h> -#include <linux/io.h> - -enum pxa_ssp_type { - SSP_UNDEFINED = 0, - PXA25x_SSP, /* pxa 210, 250, 255, 26x */ - PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */ - PXA27x_SSP, -}; - -struct ssp_device { - struct platform_device *pdev; - struct list_head node; - - struct clk *clk; - void __iomem *mmio_base; - unsigned long phys_base; - - const char *label; - int port_id; - int type; - int use_count; - int irq; - int drcmr_rx; - int drcmr_tx; -}; - -/* - * SSP initialisation flags - */ -#define SSP_NO_IRQ 0x1 /* don't register an irq handler in SSP driver */ - -struct ssp_state { - u32 cr0; - u32 cr1; - u32 to; - u32 psp; -}; - -struct ssp_dev { - struct ssp_device *ssp; - u32 port; - u32 mode; - u32 flags; - u32 psp_flags; - u32 speed; - int irq; -}; - -int ssp_write_word(struct ssp_dev *dev, u32 data); -int ssp_read_word(struct ssp_dev *dev, u32 *data); -int ssp_flush(struct ssp_dev *dev); -void ssp_enable(struct ssp_dev *dev); -void ssp_disable(struct ssp_dev *dev); -void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp); -void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp); -int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags); -int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed); -void ssp_exit(struct ssp_dev *dev); - -/** - * ssp_write_reg - Write to a SSP register - * - * @dev: SSP device to access - * @reg: Register to write to - * @val: Value to be written. - */ -static inline void ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val) -{ - __raw_writel(val, dev->mmio_base + reg); -} - -/** - * ssp_read_reg - Read from a SSP register - * - * @dev: SSP device to access - * @reg: Register to read from - */ -static inline u32 ssp_read_reg(struct ssp_device *dev, u32 reg) -{ - return __raw_readl(dev->mmio_base + reg); -} - -struct ssp_device *ssp_request(int port, const char *label); -void ssp_free(struct ssp_device *); -#endif /* __ASM_ARCH_SSP_H */ diff --git a/arch/arm/mach-pxa/include/mach/system.h b/arch/arm/mach-pxa/include/mach/system.h deleted file mode 100644 index d1fce8b6d10..00000000000 --- a/arch/arm/mach-pxa/include/mach/system.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/system.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <asm/proc-fns.h> -#include "hardware.h" -#include "pxa2xx-regs.h" - -static inline void arch_idle(void) -{ - cpu_do_idle(); -} - - -void arch_reset(char mode, const char *cmd); diff --git a/arch/arm/mach-pxa/include/mach/timex.h b/arch/arm/mach-pxa/include/mach/timex.h deleted file mode 100644 index af6760a50e1..00000000000 --- a/arch/arm/mach-pxa/include/mach/timex.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/timex.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* Various drivers are still using the constant of CLOCK_TICK_RATE, for - * those drivers to at least work, the definition is provided here. - * - * NOTE: this is no longer accurate when multiple processors and boards - * are selected, newer drivers should not depend on this any more. Use - * either the clocksource/clockevent or get this at run-time by calling - * get_clock_tick_rate() (as defined in generic.c). - */ - -#if defined(CONFIG_PXA25x) -/* PXA250/210 timer base */ -#define CLOCK_TICK_RATE 3686400 -#elif defined(CONFIG_PXA27x) -/* PXA27x timer base */ -#ifdef CONFIG_MACH_MAINSTONE -#define CLOCK_TICK_RATE 3249600 -#else -#define CLOCK_TICK_RATE 3250000 -#endif -#else -#define CLOCK_TICK_RATE 3250000 -#endif diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h index 4df2d38507d..0497d95cef2 100644 --- a/arch/arm/mach-pxa/include/mach/tosa.h +++ b/arch/arm/mach-pxa/include/mach/tosa.h @@ -13,6 +13,8 @@ #ifndef _ASM_ARCH_TOSA_H_ #define _ASM_ARCH_TOSA_H_ 1 +#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ + /* TOSA Chip selects */ #define TOSA_LCDC_PHYS PXA_CS4_PHYS /* Internel Scoop */ @@ -20,10 +22,11 @@ /* Jacket Scoop */ #define TOSA_SCOOP_PHYS (PXA_CS5_PHYS + 0x00800000) +#define TOSA_NR_IRQS (IRQ_BOARD_START + TC6393XB_NR_IRQS) /* * SCOOP2 internal GPIOs */ -#define TOSA_SCOOP_GPIO_BASE NR_BUILTIN_GPIO +#define TOSA_SCOOP_GPIO_BASE PXA_NR_BUILTIN_GPIO #define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11 #define TOSA_GPIO_TC6393XB_REST_IN (TOSA_SCOOP_GPIO_BASE + 1) #define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2) @@ -41,7 +44,7 @@ /* * SCOOP2 jacket GPIOs */ -#define TOSA_SCOOP_JC_GPIO_BASE (NR_BUILTIN_GPIO + 12) +#define TOSA_SCOOP_JC_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12) #define TOSA_GPIO_BT_LED (TOSA_SCOOP_JC_GPIO_BASE + 0) #define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1) #define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2) @@ -58,7 +61,7 @@ /* * TC6393XB GPIOs */ -#define TOSA_TC6393XB_GPIO_BASE (NR_BUILTIN_GPIO + 2 * 12) +#define TOSA_TC6393XB_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 2 * 12) #define TOSA_GPIO_TG_ON (TOSA_TC6393XB_GPIO_BASE + 0) #define TOSA_GPIO_L_MUTE (TOSA_TC6393XB_GPIO_BASE + 1) @@ -140,34 +143,34 @@ /* * Interrupts */ -#define TOSA_IRQ_GPIO_WAKEUP IRQ_GPIO(TOSA_GPIO_WAKEUP) -#define TOSA_IRQ_GPIO_AC_IN IRQ_GPIO(TOSA_GPIO_AC_IN) -#define TOSA_IRQ_GPIO_RECORD_BTN IRQ_GPIO(TOSA_GPIO_RECORD_BTN) -#define TOSA_IRQ_GPIO_SYNC IRQ_GPIO(TOSA_GPIO_SYNC) -#define TOSA_IRQ_GPIO_USB_IN IRQ_GPIO(TOSA_GPIO_USB_IN) -#define TOSA_IRQ_GPIO_JACKET_DETECT IRQ_GPIO(TOSA_GPIO_JACKET_DETECT) -#define TOSA_IRQ_GPIO_nSD_INT IRQ_GPIO(TOSA_GPIO_nSD_INT) -#define TOSA_IRQ_GPIO_nSD_DETECT IRQ_GPIO(TOSA_GPIO_nSD_DETECT) -#define TOSA_IRQ_GPIO_BAT1_CRG IRQ_GPIO(TOSA_GPIO_BAT1_CRG) -#define TOSA_IRQ_GPIO_CF_CD IRQ_GPIO(TOSA_GPIO_CF_CD) -#define TOSA_IRQ_GPIO_BAT0_CRG IRQ_GPIO(TOSA_GPIO_BAT0_CRG) -#define TOSA_IRQ_GPIO_TC6393XB_INT IRQ_GPIO(TOSA_GPIO_TC6393XB_INT) -#define TOSA_IRQ_GPIO_BAT0_LOW IRQ_GPIO(TOSA_GPIO_BAT0_LOW) -#define TOSA_IRQ_GPIO_EAR_IN IRQ_GPIO(TOSA_GPIO_EAR_IN) -#define TOSA_IRQ_GPIO_CF_IRQ IRQ_GPIO(TOSA_GPIO_CF_IRQ) -#define TOSA_IRQ_GPIO_ON_KEY IRQ_GPIO(TOSA_GPIO_ON_KEY) -#define TOSA_IRQ_GPIO_VGA_LINE IRQ_GPIO(TOSA_GPIO_VGA_LINE) -#define TOSA_IRQ_GPIO_TP_INT IRQ_GPIO(TOSA_GPIO_TP_INT) -#define TOSA_IRQ_GPIO_JC_CF_IRQ IRQ_GPIO(TOSA_GPIO_JC_CF_IRQ) -#define TOSA_IRQ_GPIO_BAT_LOCKED IRQ_GPIO(TOSA_GPIO_BAT_LOCKED) -#define TOSA_IRQ_GPIO_BAT1_LOW IRQ_GPIO(TOSA_GPIO_BAT1_LOW) -#define TOSA_IRQ_GPIO_KEY_SENSE(a) IRQ_GPIO(69+(a)) - -#define TOSA_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW) +#define TOSA_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(TOSA_GPIO_WAKEUP) +#define TOSA_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_AC_IN) +#define TOSA_IRQ_GPIO_RECORD_BTN PXA_GPIO_TO_IRQ(TOSA_GPIO_RECORD_BTN) +#define TOSA_IRQ_GPIO_SYNC PXA_GPIO_TO_IRQ(TOSA_GPIO_SYNC) +#define TOSA_IRQ_GPIO_USB_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_USB_IN) +#define TOSA_IRQ_GPIO_JACKET_DETECT PXA_GPIO_TO_IRQ(TOSA_GPIO_JACKET_DETECT) +#define TOSA_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_nSD_INT) +#define TOSA_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(TOSA_GPIO_nSD_DETECT) +#define TOSA_IRQ_GPIO_BAT1_CRG PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT1_CRG) +#define TOSA_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(TOSA_GPIO_CF_CD) +#define TOSA_IRQ_GPIO_BAT0_CRG PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT0_CRG) +#define TOSA_IRQ_GPIO_TC6393XB_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_TC6393XB_INT) +#define TOSA_IRQ_GPIO_BAT0_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT0_LOW) +#define TOSA_IRQ_GPIO_EAR_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_EAR_IN) +#define TOSA_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(TOSA_GPIO_CF_IRQ) +#define TOSA_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(TOSA_GPIO_ON_KEY) +#define TOSA_IRQ_GPIO_VGA_LINE PXA_GPIO_TO_IRQ(TOSA_GPIO_VGA_LINE) +#define TOSA_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_TP_INT) +#define TOSA_IRQ_GPIO_JC_CF_IRQ PXA_GPIO_TO_IRQ(TOSA_GPIO_JC_CF_IRQ) +#define TOSA_IRQ_GPIO_BAT_LOCKED PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT_LOCKED) +#define TOSA_IRQ_GPIO_BAT1_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT1_LOW) +#define TOSA_IRQ_GPIO_KEY_SENSE(a) PXA_GPIO_TO_IRQ(69+(a)) + +#define TOSA_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_MAIN_BAT_LOW) #define TOSA_KEY_SYNC KEY_102ND /* ??? */ -#ifndef CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES +#ifndef CONFIG_TOSA_USE_EXT_KEYCODES #define TOSA_KEY_RECORD KEY_YEN #define TOSA_KEY_ADDRESSBOOK KEY_KATAKANA #define TOSA_KEY_CANCEL KEY_ESC diff --git a/arch/arm/mach-pxa/include/mach/trizeps4.h b/arch/arm/mach-pxa/include/mach/trizeps4.h index 903e1a2e664..ae3ca013afa 100644 --- a/arch/arm/mach-pxa/include/mach/trizeps4.h +++ b/arch/arm/mach-pxa/include/mach/trizeps4.h @@ -10,6 +10,8 @@ #ifndef _TRIPEPS4_H_ #define _TRIPEPS4_H_ +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + /* physical memory regions */ #define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ #define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */ @@ -43,30 +45,30 @@ /* Ethernet Controller Davicom DM9000 */ #define GPIO_DM9000 101 -#define TRIZEPS4_ETH_IRQ IRQ_GPIO(GPIO_DM9000) +#define TRIZEPS4_ETH_IRQ PXA_GPIO_TO_IRQ(GPIO_DM9000) /* UCB1400 audio / TS-controller */ #define GPIO_UCB1400 1 -#define TRIZEPS4_UCB1400_IRQ IRQ_GPIO(GPIO_UCB1400) +#define TRIZEPS4_UCB1400_IRQ PXA_GPIO_TO_IRQ(GPIO_UCB1400) /* PCMCIA socket Compact Flash */ #define GPIO_PCD 11 /* PCMCIA Card Detect */ -#define TRIZEPS4_CD_IRQ IRQ_GPIO(GPIO_PCD) +#define TRIZEPS4_CD_IRQ PXA_GPIO_TO_IRQ(GPIO_PCD) #define GPIO_PRDY 13 /* READY / nINT */ -#define TRIZEPS4_READY_NINT IRQ_GPIO(GPIO_PRDY) +#define TRIZEPS4_READY_NINT PXA_GPIO_TO_IRQ(GPIO_PRDY) /* MMC socket */ #define GPIO_MMC_DET 12 -#define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET) +#define TRIZEPS4_MMC_IRQ PXA_GPIO_TO_IRQ(GPIO_MMC_DET) /* DOC NAND chip */ #define GPIO_DOC_LOCK 94 #define GPIO_DOC_IRQ 93 -#define TRIZEPS4_DOC_IRQ IRQ_GPIO(GPIO_DOC_IRQ) +#define TRIZEPS4_DOC_IRQ PXA_GPIO_TO_IRQ(GPIO_DOC_IRQ) /* SPI interface */ #define GPIO_SPI 53 -#define TRIZEPS4_SPI_IRQ IRQ_GPIO(GPIO_SPI) +#define TRIZEPS4_SPI_IRQ PXA_GPIO_TO_IRQ(GPIO_SPI) /* LEDS using tx2 / rx2 */ #define GPIO_SYS_BUSY_LED 46 @@ -74,7 +76,7 @@ /* Off-module PIC on ConXS board */ #define GPIO_PIC 0 -#define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC) +#define TRIZEPS4_PIC_IRQ PXA_GPIO_TO_IRQ(GPIO_PIC) #ifdef CONFIG_MACH_TRIZEPS_CONXS /* for CONXS base board define these registers */ diff --git a/arch/arm/mach-pxa/include/mach/udc.h b/arch/arm/mach-pxa/include/mach/udc.h index 2f82332e81a..9a827e32db9 100644 --- a/arch/arm/mach-pxa/include/mach/udc.h +++ b/arch/arm/mach-pxa/include/mach/udc.h @@ -2,7 +2,7 @@ * arch/arm/mach-pxa/include/mach/udc.h * */ -#include <asm/mach/udc_pxa2xx.h> +#include <linux/platform_data/pxa2xx_udc.h> extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info); diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h index 5706cea95d1..8c27757e68f 100644 --- a/arch/arm/mach-pxa/include/mach/uncompress.h +++ b/arch/arm/mach-pxa/include/mach/uncompress.h @@ -10,20 +10,41 @@ */ #include <linux/serial_reg.h> -#include <mach/regs-uart.h> #include <asm/mach-types.h> -#define __REG(x) ((volatile unsigned long *)x) +#define FFUART_BASE (0x40100000) +#define BTUART_BASE (0x40200000) +#define STUART_BASE (0x40700000) -static volatile unsigned long *UART = FFUART; +unsigned long uart_base; +unsigned int uart_shift; +unsigned int uart_is_pxa; + +static inline unsigned char uart_read(int offset) +{ + return *(volatile unsigned char *)(uart_base + (offset << uart_shift)); +} + +static inline void uart_write(unsigned char val, int offset) +{ + *(volatile unsigned char *)(uart_base + (offset << uart_shift)) = val; +} + +static inline int uart_is_enabled(void) +{ + /* assume enabled by default for non-PXA uarts */ + return uart_is_pxa ? uart_read(UART_IER) & UART_IER_UUE : 1; +} static inline void putc(char c) { - if (!(UART[UART_IER] & IER_UUE)) + if (!uart_is_enabled()) return; - while (!(UART[UART_LSR] & LSR_TDRQ)) + + while (!(uart_read(UART_LSR) & UART_LSR_THRE)) barrier(); - UART[UART_TX] = c; + + uart_write(c, UART_TX); } /* @@ -35,12 +56,19 @@ static inline void flush(void) static inline void arch_decomp_setup(void) { + /* initialize to default */ + uart_base = FFUART_BASE; + uart_shift = 2; + uart_is_pxa = 1; + if (machine_is_littleton() || machine_is_intelmote2() - || machine_is_csb726()) - UART = STUART; -} + || machine_is_csb726() || machine_is_stargate2() + || machine_is_cm_x300() || machine_is_balloon3()) + uart_base = STUART_BASE; -/* - * nothing to do - */ -#define arch_decomp_wdog() + if (machine_is_arcom_zeus()) { + uart_base = 0x10000000; /* nCS4 */ + uart_shift = 1; + uart_is_pxa = 0; + } +} diff --git a/arch/arm/mach-pxa/include/mach/viper.h b/arch/arm/mach-pxa/include/mach/viper.h index 10988c270ca..5f5fbf1f648 100644 --- a/arch/arm/mach-pxa/include/mach/viper.h +++ b/arch/arm/mach-pxa/include/mach/viper.h @@ -85,8 +85,6 @@ /* Interrupt and Configuration Register (VIPER_ICR) */ /* This is a write only register. Only CF_RST is used under Linux */ -extern void viper_cf_rst(int state); - #define VIPER_ICR_RETRIG (1 << 0) #define VIPER_ICR_AUTO_CLR (1 << 1) #define VIPER_ICR_R_DIS (1 << 2) diff --git a/arch/arm/mach-pxa/include/mach/vmalloc.h b/arch/arm/mach-pxa/include/mach/vmalloc.h deleted file mode 100644 index e90c5eeb81d..00000000000 --- a/arch/arm/mach-pxa/include/mach/vmalloc.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/vmalloc.h - * - * Author: Nicolas Pitre - * Copyright: (C) 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#define VMALLOC_END (0xe8000000) diff --git a/arch/arm/mach-pxa/include/mach/vpac270.h b/arch/arm/mach-pxa/include/mach/vpac270.h new file mode 100644 index 00000000000..7bfa3dd0fd5 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/vpac270.h @@ -0,0 +1,42 @@ +/* + * GPIOs and interrupts for Voipac PXA270 + * + * Copyright (C) 2010 + * Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_VPAC270_H_ +#define _INCLUDE_VPAC270_H_ + +#define GPIO1_VPAC270_USER_BTN 1 + +#define GPIO15_VPAC270_LED_ORANGE 15 + +#define GPIO81_VPAC270_BKL_ON 81 +#define GPIO83_VPAC270_NL_ON 83 + +#define GPIO52_VPAC270_SD_READONLY 52 +#define GPIO53_VPAC270_SD_DETECT_N 53 + +#define GPIO84_VPAC270_PCMCIA_CD 84 +#define GPIO35_VPAC270_PCMCIA_RDY 35 +#define GPIO107_VPAC270_PCMCIA_PPEN 107 +#define GPIO11_VPAC270_PCMCIA_RESET 11 +#define GPIO17_VPAC270_CF_CD 17 +#define GPIO12_VPAC270_CF_RDY 12 +#define GPIO16_VPAC270_CF_RESET 16 + +#define GPIO41_VPAC270_UDC_DETECT 41 + +#define GPIO114_VPAC270_ETH_IRQ 114 + +#define GPIO36_VPAC270_IDE_IRQ 36 + +#define GPIO113_VPAC270_TS_IRQ 113 + +#endif diff --git a/arch/arm/mach-pxa/include/mach/z2.h b/arch/arm/mach-pxa/include/mach/z2.h new file mode 100644 index 00000000000..7b0f71ef316 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/z2.h @@ -0,0 +1,40 @@ +/* + * arch/arm/mach-pxa/include/mach/z2.h + * + * Author: Ken McGuire + * Created: Feb 6, 2009 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef ASM_ARCH_ZIPIT2_H +#define ASM_ARCH_ZIPIT2_H + +/* LEDs */ +#define GPIO10_ZIPITZ2_LED_WIFI 10 +#define GPIO85_ZIPITZ2_LED_CHARGED 85 +#define GPIO83_ZIPITZ2_LED_CHARGING 83 + +/* SD/MMC */ +#define GPIO96_ZIPITZ2_SD_DETECT 96 + +/* GPIO Buttons */ +#define GPIO1_ZIPITZ2_POWER_BUTTON 1 +#define GPIO98_ZIPITZ2_LID_BUTTON 98 + +/* Libertas GSPI8686 WiFi */ +#define GPIO14_ZIPITZ2_WIFI_POWER 14 +#define GPIO24_ZIPITZ2_WIFI_CS 24 +#define GPIO36_ZIPITZ2_WIFI_IRQ 36 + +/* LCD */ +#define GPIO19_ZIPITZ2_LCD_RESET 19 +#define GPIO88_ZIPITZ2_LCD_CS 88 + +/* MISC GPIOs */ +#define GPIO0_ZIPITZ2_AC_DETECT 0 +#define GPIO37_ZIPITZ2_HEADSET_DETECT 37 + +#endif diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h new file mode 100644 index 00000000000..56024f81d57 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/zeus.h @@ -0,0 +1,85 @@ +/* + * arch/arm/mach-pxa/include/mach/zeus.h + * + * Author: David Vrabel + * Created: Sept 28, 2005 + * Copyright: Arcom Control Systems Ltd. + * + * Maintained by: Marc Zyngier <maz@misterjones.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _MACH_ZEUS_H +#define _MACH_ZEUS_H + +#define ZEUS_NR_IRQS (IRQ_BOARD_START + 48) + +/* Physical addresses */ +#define ZEUS_FLASH_PHYS PXA_CS0_PHYS +#define ZEUS_ETH0_PHYS PXA_CS1_PHYS +#define ZEUS_ETH1_PHYS PXA_CS2_PHYS +#define ZEUS_CPLD_PHYS (PXA_CS4_PHYS+0x2000000) +#define ZEUS_SRAM_PHYS PXA_CS5_PHYS +#define ZEUS_PC104IO_PHYS (0x30000000) + +#define ZEUS_CPLD_VERSION_PHYS (ZEUS_CPLD_PHYS + 0x00000000) +#define ZEUS_CPLD_ISA_IRQ_PHYS (ZEUS_CPLD_PHYS + 0x00800000) +#define ZEUS_CPLD_CONTROL_PHYS (ZEUS_CPLD_PHYS + 0x01000000) +#define ZEUS_CPLD_EXTWDOG_PHYS (ZEUS_CPLD_PHYS + 0x01800000) + +/* GPIOs */ +#define ZEUS_AC97_GPIO 0 +#define ZEUS_WAKEUP_GPIO 1 +#define ZEUS_UARTA_GPIO 9 +#define ZEUS_UARTB_GPIO 10 +#define ZEUS_UARTC_GPIO 12 +#define ZEUS_UARTD_GPIO 11 +#define ZEUS_ETH0_GPIO 14 +#define ZEUS_ISA_GPIO 17 +#define ZEUS_BKLEN_GPIO 19 +#define ZEUS_USB2_PWREN_GPIO 22 +#define ZEUS_PTT_GPIO 27 +#define ZEUS_CF_CD_GPIO 35 +#define ZEUS_MMC_WP_GPIO 52 +#define ZEUS_MMC_CD_GPIO 53 +#define ZEUS_EXTGPIO_GPIO 91 +#define ZEUS_CF_PWEN_GPIO 97 +#define ZEUS_CF_RDY_GPIO 99 +#define ZEUS_LCD_EN_GPIO 101 +#define ZEUS_ETH1_GPIO 113 +#define ZEUS_CAN_GPIO 116 + +#define ZEUS_EXT0_GPIO_BASE 128 +#define ZEUS_EXT1_GPIO_BASE 160 +#define ZEUS_USER_GPIO_BASE 192 + +#define ZEUS_EXT0_GPIO(x) (ZEUS_EXT0_GPIO_BASE + (x)) +#define ZEUS_EXT1_GPIO(x) (ZEUS_EXT1_GPIO_BASE + (x)) +#define ZEUS_USER_GPIO(x) (ZEUS_USER_GPIO_BASE + (x)) + +#define ZEUS_CAN_SHDN_GPIO ZEUS_EXT1_GPIO(2) + +/* + * CPLD registers: + * Only 4 registers, but spread over a 32MB address space. + * Be gentle, and remap that over 32kB... + */ + +#define ZEUS_CPLD IOMEM(0xf0000000) +#define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000) +#define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000) +#define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000) + +/* CPLD register bits */ +#define ZEUS_CPLD_CONTROL_CF_RST 0x01 + +#define ZEUS_PC104IO IOMEM(0xf1000000) + +#define ZEUS_SRAM_SIZE (256 * 1024) + +#endif + + diff --git a/arch/arm/mach-pxa/include/mach/zylonite.h b/arch/arm/mach-pxa/include/mach/zylonite.h index bf6785adccf..ecca976f03d 100644 --- a/arch/arm/mach-pxa/include/mach/zylonite.h +++ b/arch/arm/mach-pxa/include/mach/zylonite.h @@ -5,16 +5,11 @@ #define EXT_GPIO(x) (128 + (x)) +#define ZYLONITE_NR_IRQS (IRQ_BOARD_START + 32) + /* the following variables are processor specific and initialized * by the corresponding zylonite_pxa3xx_init() */ -struct platform_mmc_slot { - int gpio_cd; - int gpio_wp; -}; - -extern struct platform_mmc_slot zylonite_mmc_slot[]; - extern int gpio_eth_irq; extern int gpio_debug_led1; extern int gpio_debug_led2; @@ -24,7 +19,7 @@ extern int wm9713_irq; extern int lcd_id; extern int lcd_orientation; -#ifdef CONFIG_CPU_PXA300 +#ifdef CONFIG_MACH_ZYLONITE300 extern void zylonite_pxa300_init(void); #else static inline void zylonite_pxa300_init(void) @@ -34,7 +29,7 @@ static inline void zylonite_pxa300_init(void) } #endif -#ifdef CONFIG_CPU_PXA320 +#ifdef CONFIG_MACH_ZYLONITE320 extern void zylonite_pxa320_init(void); #else static inline void zylonite_pxa320_init(void) |