diff options
Diffstat (limited to 'arch/arm/mach-orion5x')
46 files changed, 903 insertions, 1656 deletions
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 6604fc6ca58..2412efb6cdd 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -2,6 +2,18 @@ if ARCH_ORION5X menu "Orion Implementations" +config ARCH_ORION5X_DT + bool "Marvell Orion5x Flattened Device Tree" + select USE_OF + select ORION_CLK + select ORION_IRQCHIP + select ORION_TIMER + select PINCTRL + select PINCTRL_ORION + help + Say 'Y' here if you want your kernel to support the + Marvell Orion5x using flattened device tree. + config MACH_DB88F5281 bool "Marvell Orion-2 Development Board" select I2C_BOARDINFO @@ -16,6 +28,14 @@ config MACH_RD88F5182 Say 'Y' here if you want your kernel to support the Marvell Orion-NAS (88F5182) RD2 +config MACH_RD88F5182_DT + bool "Marvell Orion-NAS Reference Design (Flattened Device Tree)" + select ARCH_ORION5X_DT + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the Marvell + Orion-NAS (88F5182) RD2, Flattened Device Tree. + config MACH_KUROBOX_PRO bool "KuroBox Pro" select I2C_BOARDINFO @@ -26,7 +46,6 @@ config MACH_KUROBOX_PRO config MACH_DNS323 bool "D-Link DNS-323" select I2C_BOARDINFO - select PHYLIB help Say 'Y' here if you want your kernel to support the D-Link DNS-323 platform. @@ -86,7 +105,6 @@ config MACH_WRT350N_V2 config MACH_TS78XX bool "Technologic Systems TS-78xx" - select PM help Say 'Y' here if you want your kernel to support the Technologic Systems TS-78xx platform. @@ -97,27 +115,13 @@ config MACH_MV2120 Say 'Y' here if you want your kernel to support the HP Media Vault mv2120 or mv5100. -config MACH_EDMINI_V2 - bool "LaCie Ethernet Disk mini V2" - select I2C_BOARDINFO - help - Say 'Y' here if you want your kernel to support the - LaCie Ethernet Disk mini V2. - -config MACH_D2NET - bool "LaCie d2 Network" - select I2C_BOARDINFO +config MACH_D2NET_DT + bool "LaCie d2 Network / Big Disk Network (Flattened Device Tree)" + select ARCH_ORION5X_DT help Say 'Y' here if you want your kernel to support the LaCie d2 Network NAS. -config MACH_BIGDISK - bool "LaCie Big Disk Network" - select I2C_BOARDINFO - help - Say 'Y' here if you want your kernel to support the - LaCie Big Disk Network NAS. - config MACH_NET2BIG bool "LaCie 2Big Network" select I2C_BOARDINFO @@ -125,8 +129,9 @@ config MACH_NET2BIG Say 'Y' here if you want your kernel to support the LaCie 2Big Network NAS. -config MACH_MSS2 - bool "Maxtor Shared Storage II" +config MACH_MSS2_DT + bool "Maxtor Shared Storage II (Flattened Device Tree)" + select ARCH_ORION5X_DT help Say 'Y' here if you want your kernel to support the Maxtor Shared Storage II platform. diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 7f18cdacd48..a40b5c9a58c 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -1,4 +1,4 @@ -obj-y += common.o addr-map.o pci.o irq.o mpp.o +obj-y += common.o pci.o irq.o mpp.o obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o @@ -12,13 +12,14 @@ obj-$(CONFIG_MACH_TS409) += ts409-setup.o tsx09-common.o obj-$(CONFIG_MACH_WRT350N_V2) += wrt350n-v2-setup.o obj-$(CONFIG_MACH_TS78XX) += ts78xx-setup.o obj-$(CONFIG_MACH_MV2120) += mv2120-setup.o -obj-$(CONFIG_MACH_EDMINI_V2) += edmini_v2-setup.o -obj-$(CONFIG_MACH_D2NET) += d2net-setup.o -obj-$(CONFIG_MACH_BIGDISK) += d2net-setup.o obj-$(CONFIG_MACH_NET2BIG) += net2big-setup.o -obj-$(CONFIG_MACH_MSS2) += mss2-setup.o obj-$(CONFIG_MACH_WNR854T) += wnr854t-setup.o obj-$(CONFIG_MACH_RD88F5181L_GE) += rd88f5181l-ge-setup.o obj-$(CONFIG_MACH_RD88F5181L_FXO) += rd88f5181l-fxo-setup.o obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o obj-$(CONFIG_MACH_LINKSTATION_LSCHL) += ls-chl-setup.o + +obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o +obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o +obj-$(CONFIG_MACH_MSS2_DT) += board-mss2.o +obj-$(CONFIG_MACH_RD88F5182_DT) += board-rd88f5182.o diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c deleted file mode 100644 index 5ceafdccc45..00000000000 --- a/arch/arm/mach-orion5x/addr-map.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * arch/arm/mach-orion5x/addr-map.c - * - * Address map functions for Marvell Orion 5x SoCs - * - * Maintainer: Tzachi Perelstein <tzachi@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mbus.h> -#include <linux/io.h> -#include <linux/errno.h> -#include <mach/hardware.h> -#include "common.h" - -/* - * The Orion has fully programmable address map. There's a separate address - * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB, - * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own - * address decode windows that allow it to access any of the Orion resources. - * - * CPU address decoding -- - * Linux assumes that it is the boot loader that already setup the access to - * DDR and internal registers. - * Setup access to PCI and PCIe IO/MEM space is issued by this file. - * Setup access to various devices located on the device bus interface (e.g. - * flashes, RTC, etc) should be issued by machine-setup.c according to - * specific board population (by using orion5x_setup_*_win()). - * - * Non-CPU Masters address decoding -- - * Unlike the CPU, we setup the access from Orion's master interfaces to DDR - * banks only (the typical use case). - * Setup access for each master to DDR is issued by platform device setup. - */ - -/* - * Generic Address Decode Windows bit settings - */ -#define TARGET_DDR 0 -#define TARGET_DEV_BUS 1 -#define TARGET_PCI 3 -#define TARGET_PCIE 4 -#define TARGET_SRAM 9 -#define ATTR_PCIE_MEM 0x59 -#define ATTR_PCIE_IO 0x51 -#define ATTR_PCIE_WA 0x79 -#define ATTR_PCI_MEM 0x59 -#define ATTR_PCI_IO 0x51 -#define ATTR_DEV_CS0 0x1e -#define ATTR_DEV_CS1 0x1d -#define ATTR_DEV_CS2 0x1b -#define ATTR_DEV_BOOT 0xf -#define ATTR_SRAM 0x0 - -/* - * Helpers to get DDR bank info - */ -#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) -#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3)) -#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3)) - -/* - * CPU Address Decode Windows registers - */ -#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) -#define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4)) -#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4)) -#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) -#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4)) - - -struct mbus_dram_target_info orion5x_mbus_dram_info; -static int __initdata win_alloc_count; - -static int __init orion5x_cpu_win_can_remap(int win) -{ - u32 dev, rev; - - orion5x_pcie_id(&dev, &rev); - if ((dev == MV88F5281_DEV_ID && win < 4) - || (dev == MV88F5182_DEV_ID && win < 2) - || (dev == MV88F5181_DEV_ID && win < 2) - || (dev == MV88F6183_DEV_ID && win < 4)) - return 1; - - return 0; -} - -static int __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) -{ - if (win >= 8) { - printk(KERN_ERR "setup_cpu_win: trying to allocate " - "window %d\n", win); - return -ENOSPC; - } - - writel(base & 0xffff0000, CPU_WIN_BASE(win)); - writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1, - CPU_WIN_CTRL(win)); - - if (orion5x_cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - - writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win)); - writel(0, CPU_WIN_REMAP_HI(win)); - } - return 0; -} - -void __init orion5x_setup_cpu_mbus_bridge(void) -{ - int i; - int cs; - - /* - * First, disable and clear windows. - */ - for (i = 0; i < 8; i++) { - writel(0, CPU_WIN_BASE(i)); - writel(0, CPU_WIN_CTRL(i)); - if (orion5x_cpu_win_can_remap(i)) { - writel(0, CPU_WIN_REMAP_LO(i)); - writel(0, CPU_WIN_REMAP_HI(i)); - } - } - - /* - * Setup windows for PCI+PCIe IO+MEM space. - */ - setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, - TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE); - setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, - TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE); - setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE_MEM, -1); - setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, - TARGET_PCI, ATTR_PCI_MEM, -1); - win_alloc_count = 4; - - /* - * Setup MBUS dram target info. - */ - orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(DDR_BASE_CS(i)); - u32 size = readl(DDR_SIZE_CS(i)); - - /* - * Chip select enabled? - */ - if (size & 1) { - struct mbus_dram_window *w; - - w = &orion5x_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0xf & ~(1 << i); - w->base = base & 0xffff0000; - w->size = (size | 0x0000ffff) + 1; - } - } - orion5x_mbus_dram_info.num_cs = cs; -} - -void __init orion5x_setup_dev_boot_win(u32 base, u32 size) -{ - setup_cpu_win(win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); -} - -void __init orion5x_setup_dev0_win(u32 base, u32 size) -{ - setup_cpu_win(win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_CS0, -1); -} - -void __init orion5x_setup_dev1_win(u32 base, u32 size) -{ - setup_cpu_win(win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_CS1, -1); -} - -void __init orion5x_setup_dev2_win(u32 base, u32 size) -{ - setup_cpu_win(win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_CS2, -1); -} - -void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) -{ - setup_cpu_win(win_alloc_count++, base, size, - TARGET_PCIE, ATTR_PCIE_WA, -1); -} - -int __init orion5x_setup_sram_win(void) -{ - return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE, - ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); -} diff --git a/arch/arm/mach-orion5x/board-d2net.c b/arch/arm/mach-orion5x/board-d2net.c new file mode 100644 index 00000000000..8a728412415 --- /dev/null +++ b/arch/arm/mach-orion5x/board-d2net.c @@ -0,0 +1,109 @@ +/* + * arch/arm/mach-orion5x/board-d2net.c + * + * LaCie d2Network and Big Disk Network NAS setup + * + * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pci.h> +#include <linux/irq.h> +#include <linux/leds.h> +#include <linux/gpio.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/pci.h> +#include <mach/orion5x.h> +#include <plat/orion-gpio.h> +#include "common.h" + +/***************************************************************************** + * LaCie d2 Network Info + ****************************************************************************/ + +/***************************************************************************** + * GPIO LED's + ****************************************************************************/ + +/* + * The blue front LED is wired to the CPLD and can blink in relation with the + * SATA activity. + * + * The following array detail the different LED registers and the combination + * of their possible values: + * + * led_off | blink_ctrl | SATA active | LED state + * | | | + * 1 | x | x | off + * 0 | 0 | 0 | off + * 0 | 1 | 0 | blink (rate 300ms) + * 0 | x | 1 | on + * + * Notes: The blue and the red front LED's can't be on at the same time. + * Red LED have priority. + */ + +#define D2NET_GPIO_RED_LED 6 +#define D2NET_GPIO_BLUE_LED_BLINK_CTRL 16 +#define D2NET_GPIO_BLUE_LED_OFF 23 + +static struct gpio_led d2net_leds[] = { + { + .name = "d2net:blue:sata", + .default_trigger = "default-on", + .gpio = D2NET_GPIO_BLUE_LED_OFF, + .active_low = 1, + }, + { + .name = "d2net:red:fail", + .gpio = D2NET_GPIO_RED_LED, + }, +}; + +static struct gpio_led_platform_data d2net_led_data = { + .num_leds = ARRAY_SIZE(d2net_leds), + .leds = d2net_leds, +}; + +static struct platform_device d2net_gpio_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &d2net_led_data, + }, +}; + +static void __init d2net_gpio_leds_init(void) +{ + int err; + + /* Configure register blink_ctrl to allow SATA activity LED blinking. */ + err = gpio_request(D2NET_GPIO_BLUE_LED_BLINK_CTRL, "blue LED blink"); + if (err == 0) { + err = gpio_direction_output(D2NET_GPIO_BLUE_LED_BLINK_CTRL, 1); + if (err) + gpio_free(D2NET_GPIO_BLUE_LED_BLINK_CTRL); + } + if (err) + pr_err("d2net: failed to configure blue LED blink GPIO\n"); + + platform_device_register(&d2net_gpio_leds); +} + +/***************************************************************************** + * General Setup + ****************************************************************************/ + +void __init d2net_init(void) +{ + d2net_gpio_leds_init(); + + pr_notice("d2net: Flash write are not yet supported.\n"); +} diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c new file mode 100644 index 00000000000..79f033b1ddf --- /dev/null +++ b/arch/arm/mach-orion5x/board-dt.c @@ -0,0 +1,82 @@ +/* + * Copyright 2012 (C), Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * arch/arm/mach-orion5x/board-dt.c + * + * Flattened Device Tree board initialization + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/cpu.h> +#include <linux/mbus.h> +#include <linux/clk-provider.h> +#include <linux/clocksource.h> +#include <asm/system_misc.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <mach/orion5x.h> +#include <mach/bridge-regs.h> +#include <plat/irq.h> +#include <plat/time.h> +#include "common.h" + +static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL), + OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0", + NULL), + OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL), + OF_DEV_AUXDATA("marvell,orion-sata", 0xf1080000, "sata_mv.0", NULL), + OF_DEV_AUXDATA("marvell,orion-crypto", 0xf1090000, "mv_crypto", NULL), + {}, +}; + +static void __init orion5x_dt_init(void) +{ + char *dev_name; + u32 dev, rev; + + orion5x_id(&dev, &rev, &dev_name); + printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); + + BUG_ON(mvebu_mbus_dt_init(false)); + + /* + * Setup Orion address map + */ + orion5x_setup_wins(); + + /* + * Don't issue "Wait for Interrupt" instruction if we are + * running on D0 5281 silicon. + */ + if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { + printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); + cpu_idle_poll_ctrl(true); + } + + if (of_machine_is_compatible("maxtor,shared-storage-2")) + mss2_init(); + + of_platform_populate(NULL, of_default_bus_match_table, + orion5x_auxdata_lookup, NULL); +} + +static const char *orion5x_dt_compat[] = { + "marvell,orion5x", + NULL, +}; + +DT_MACHINE_START(ORION5X_DT, "Marvell Orion5x (Flattened Device Tree)") + /* Maintainer: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> */ + .map_io = orion5x_map_io, + .init_machine = orion5x_dt_init, + .restart = orion5x_restart, + .dt_compat = orion5x_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-orion5x/board-mss2.c b/arch/arm/mach-orion5x/board-mss2.c new file mode 100644 index 00000000000..66f9c3ba86c --- /dev/null +++ b/arch/arm/mach-orion5x/board-mss2.c @@ -0,0 +1,90 @@ +/* + * Maxtor Shared Storage II Board Setup + * + * Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pci.h> +#include <linux/irq.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/pci.h> +#include <mach/orion5x.h> +#include <mach/bridge-regs.h> +#include "common.h" + +/***************************************************************************** + * Maxtor Shared Storage II Info + ****************************************************************************/ + +/**************************************************************************** + * PCI setup + ****************************************************************************/ +static int __init mss2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + /* + * Check for devices with hard-wired IRQs. + */ + irq = orion5x_pci_map_irq(dev, slot, pin); + if (irq != -1) + return irq; + + return -1; +} + +static struct hw_pci mss2_pci __initdata = { + .nr_controllers = 2, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = mss2_pci_map_irq, +}; + +static int __init mss2_pci_init(void) +{ + if (machine_is_mss2()) + pci_common_init(&mss2_pci); + + return 0; +} +subsys_initcall(mss2_pci_init); + +/***************************************************************************** + * MSS2 power off method + ****************************************************************************/ +/* + * On the Maxtor Shared Storage II, the shutdown process is the following : + * - Userland modifies U-boot env to tell U-boot to go idle at next boot + * - The board reboots + * - U-boot starts and go into an idle mode until the user press "power" + */ +static void mss2_power_off(void) +{ + u32 reg; + + /* + * Enable and issue soft reset + */ + reg = readl(RSTOUTn_MASK); + reg |= 1 << 2; + writel(reg, RSTOUTn_MASK); + + reg = readl(CPU_SOFT_RESET); + reg |= 1; + writel(reg, CPU_SOFT_RESET); +} + +void __init mss2_init(void) +{ + /* register mss2 specific power-off method */ + pm_power_off = mss2_power_off; +} diff --git a/arch/arm/mach-orion5x/board-rd88f5182.c b/arch/arm/mach-orion5x/board-rd88f5182.c new file mode 100644 index 00000000000..270824b0e50 --- /dev/null +++ b/arch/arm/mach-orion5x/board-rd88f5182.c @@ -0,0 +1,116 @@ +/* + * arch/arm/mach-orion5x/rd88f5182-setup.c + * + * Marvell Orion-NAS Reference Design Setup + * + * Maintainer: Ronen Shitrit <rshitrit@marvell.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include <linux/gpio.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pci.h> +#include <linux/irq.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/pci.h> +#include <mach/orion5x.h> +#include "common.h" + +/***************************************************************************** + * RD-88F5182 Info + ****************************************************************************/ + +/* + * PCI + */ + +#define RD88F5182_PCI_SLOT0_OFFS 7 +#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7 +#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6 + +/***************************************************************************** + * PCI + ****************************************************************************/ + +static void __init rd88f5182_pci_preinit(void) +{ + int pin; + + /* + * Configure PCI GPIO IRQ pins + */ + pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; + if (gpio_request(pin, "PCI IntA") == 0) { + if (gpio_direction_input(pin) == 0) { + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + } else { + printk(KERN_ERR "rd88f5182_pci_preinit failed to " + "set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin); + } + + pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; + if (gpio_request(pin, "PCI IntB") == 0) { + if (gpio_direction_input(pin) == 0) { + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + } else { + printk(KERN_ERR "rd88f5182_pci_preinit failed to " + "set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin); + } +} + +static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot, + u8 pin) +{ + int irq; + + /* + * Check for devices with hard-wired IRQs. + */ + irq = orion5x_pci_map_irq(dev, slot, pin); + if (irq != -1) + return irq; + + /* + * PCI IRQs are connected via GPIOs + */ + switch (slot - RD88F5182_PCI_SLOT0_OFFS) { + case 0: + if (pin == 1) + return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN); + else + return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN); + default: + return -1; + } +} + +static struct hw_pci rd88f5182_pci __initdata = { + .nr_controllers = 2, + .preinit = rd88f5182_pci_preinit, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = rd88f5182_pci_map_irq, +}; + +static int __init rd88f5182_pci_init(void) +{ + if (of_machine_is_compatible("marvell,rd-88f5182-nas")) + pci_common_init(&rd88f5182_pci); + + return 0; +} + +subsys_initcall(rd88f5182_pci_init); diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 22ace0bf2f9..6bbb7b55c6d 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -15,20 +15,23 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/serial_8250.h> -#include <linux/mbus.h> #include <linux/mv643xx_i2c.h> #include <linux/ata_platform.h> +#include <linux/delay.h> +#include <linux/clk-provider.h> +#include <linux/cpu.h> #include <net/dsa.h> #include <asm/page.h> #include <asm/setup.h> -#include <asm/timex.h> +#include <asm/system_misc.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h> #include <mach/bridge-regs.h> #include <mach/hardware.h> #include <mach/orion5x.h> -#include <plat/orion_nand.h> +#include <linux/platform_data/mtd-orion_nand.h> +#include <linux/platform_data/usb-ehci-orion.h> #include <plat/time.h> #include <plat/common.h> #include "common.h" @@ -38,22 +41,12 @@ ****************************************************************************/ static struct map_desc orion5x_io_desc[] __initdata = { { - .virtual = ORION5X_REGS_VIRT_BASE, + .virtual = (unsigned long) ORION5X_REGS_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), .length = ORION5X_REGS_SIZE, .type = MT_DEVICE, }, { - .virtual = ORION5X_PCIE_IO_VIRT_BASE, - .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), - .length = ORION5X_PCIE_IO_SIZE, - .type = MT_DEVICE, - }, { - .virtual = ORION5X_PCI_IO_VIRT_BASE, - .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), - .length = ORION5X_PCI_IO_SIZE, - .type = MT_DEVICE, - }, { - .virtual = ORION5X_PCIE_WA_VIRT_BASE, + .virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), .length = ORION5X_PCIE_WA_SIZE, .type = MT_DEVICE, @@ -67,12 +60,25 @@ void __init orion5x_map_io(void) /***************************************************************************** + * CLK tree + ****************************************************************************/ +static struct clk *tclk; + +void __init clk_init(void) +{ + tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, + orion5x_tclk); + + orion_clkdev_init(tclk); +} + +/***************************************************************************** * EHCI0 ****************************************************************************/ void __init orion5x_ehci0_init(void) { - orion_ehci_init(&orion5x_mbus_dram_info, - ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); + orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL, + EHCI_PHY_ORION); } @@ -81,8 +87,7 @@ void __init orion5x_ehci0_init(void) ****************************************************************************/ void __init orion5x_ehci1_init(void) { - orion_ehci_1_init(&orion5x_mbus_dram_info, - ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); + orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); } @@ -91,9 +96,10 @@ void __init orion5x_ehci1_init(void) ****************************************************************************/ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) { - orion_ge00_init(eth_data, &orion5x_mbus_dram_info, + orion_ge00_init(eth_data, ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, - IRQ_ORION5X_ETH_ERR, orion5x_tclk); + IRQ_ORION5X_ETH_ERR, + MV643XX_TX_CSUM_DEFAULT_LIMIT); } @@ -121,17 +127,16 @@ void __init orion5x_i2c_init(void) ****************************************************************************/ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) { - orion_sata_init(sata_data, &orion5x_mbus_dram_info, - ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); + orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); } /***************************************************************************** * SPI ****************************************************************************/ -void __init orion5x_spi_init() +void __init orion5x_spi_init(void) { - orion_spi_init(SPI_PHYS_BASE, orion5x_tclk); + orion_spi_init(SPI_PHYS_BASE); } @@ -141,7 +146,7 @@ void __init orion5x_spi_init() void __init orion5x_uart0_init(void) { orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, - IRQ_ORION5X_UART0, orion5x_tclk); + IRQ_ORION5X_UART0, tclk); } /***************************************************************************** @@ -150,7 +155,7 @@ void __init orion5x_uart0_init(void) void __init orion5x_uart1_init(void) { orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, - IRQ_ORION5X_UART1, orion5x_tclk); + IRQ_ORION5X_UART1, tclk); } /***************************************************************************** @@ -158,8 +163,7 @@ void __init orion5x_uart1_init(void) ****************************************************************************/ void __init orion5x_xor_init(void) { - orion_xor0_init(&orion5x_mbus_dram_info, - ORION5X_XOR_PHYS_BASE, + orion_xor0_init(ORION5X_XOR_PHYS_BASE, ORION5X_XOR_PHYS_BASE + 0x200, IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); } @@ -169,12 +173,10 @@ void __init orion5x_xor_init(void) ****************************************************************************/ static void __init orion5x_crypto_init(void) { - int ret; - - ret = orion5x_setup_sram_win(); - if (ret) - return; - + mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET, + ORION_MBUS_SRAM_ATTR, + ORION5X_SRAM_PHYS_BASE, + ORION5X_SRAM_SIZE); orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, SZ_8K, IRQ_ORION5X_CESA); } @@ -182,9 +184,9 @@ static void __init orion5x_crypto_init(void) /***************************************************************************** * Watchdog ****************************************************************************/ -void __init orion5x_wdt_init(void) +static void __init orion5x_wdt_init(void) { - orion_wdt_init(orion5x_tclk); + orion_wdt_init(); } @@ -193,12 +195,57 @@ void __init orion5x_wdt_init(void) ****************************************************************************/ void __init orion5x_init_early(void) { + u32 rev, dev; + const char *mbus_soc_name; + orion_time_set_base(TIMER_VIRT_BASE); + + /* Initialize the MBUS driver */ + orion5x_pcie_id(&dev, &rev); + if (dev == MV88F5281_DEV_ID) + mbus_soc_name = "marvell,orion5x-88f5281-mbus"; + else if (dev == MV88F5182_DEV_ID) + mbus_soc_name = "marvell,orion5x-88f5182-mbus"; + else if (dev == MV88F5181_DEV_ID) + mbus_soc_name = "marvell,orion5x-88f5181-mbus"; + else if (dev == MV88F6183_DEV_ID) + mbus_soc_name = "marvell,orion5x-88f6183-mbus"; + else + mbus_soc_name = NULL; + mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE, + ORION5X_BRIDGE_WINS_SZ, + ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ); +} + +void orion5x_setup_wins(void) +{ + /* + * The PCIe windows will no longer be statically allocated + * here once Orion5x is migrated to the pci-mvebu driver. + */ + mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET, + ORION_MBUS_PCIE_IO_ATTR, + ORION5X_PCIE_IO_PHYS_BASE, + ORION5X_PCIE_IO_SIZE, + ORION5X_PCIE_IO_BUS_BASE); + mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET, + ORION_MBUS_PCIE_MEM_ATTR, + ORION5X_PCIE_MEM_PHYS_BASE, + ORION5X_PCIE_MEM_SIZE); + mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET, + ORION_MBUS_PCI_IO_ATTR, + ORION5X_PCI_IO_PHYS_BASE, + ORION5X_PCI_IO_SIZE, + ORION5X_PCI_IO_BUS_BASE); + mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET, + ORION_MBUS_PCI_MEM_ATTR, + ORION5X_PCI_MEM_PHYS_BASE, + ORION5X_PCI_MEM_SIZE); } int orion5x_tclk; -int __init orion5x_find_tclk(void) +static int __init orion5x_find_tclk(void) { u32 dev, rev; @@ -210,7 +257,7 @@ int __init orion5x_find_tclk(void) return 166666667; } -static void orion5x_timer_init(void) +void __init orion5x_timer_init(void) { orion5x_tclk = orion5x_find_tclk(); @@ -218,10 +265,6 @@ static void orion5x_timer_init(void) IRQ_ORION5X_BRIDGE, orion5x_tclk); } -struct sys_timer orion5x_timer = { - .init = orion5x_timer_init, -}; - /***************************************************************************** * General @@ -229,7 +272,7 @@ struct sys_timer orion5x_timer = { /* * Identify device ID and rev from PCIe configuration header space '0'. */ -static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) +void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) { orion5x_pcie_id(dev, rev); @@ -279,7 +322,10 @@ void __init orion5x_init(void) /* * Setup Orion address map */ - orion5x_setup_cpu_mbus_bridge(); + orion5x_setup_wins(); + + /* Setup root of clk tree */ + clk_init(); /* * Don't issue "Wait for Interrupt" instruction if we are @@ -287,7 +333,7 @@ void __init orion5x_init(void) */ if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); - disable_hlt(); + cpu_idle_poll_ctrl(true); } /* @@ -304,12 +350,22 @@ void __init orion5x_init(void) orion5x_wdt_init(); } +void orion5x_restart(enum reboot_mode mode, const char *cmd) +{ + /* + * Enable and issue soft reset + */ + orion5x_setbits(RSTOUTn_MASK, (1 << 2)); + orion5x_setbits(CPU_SOFT_RESET, 1); + mdelay(200); + orion5x_clrbits(CPU_SOFT_RESET, 1); +} + /* * Many orion-based systems have buggy bootloader implementations. * This is a common fixup for bogus memory tags. */ -void __init tag_fixup_mem32(struct tag *t, char **from, - struct meminfo *meminfo) +void __init tag_fixup_mem32(struct tag *t, char **from) { for (; t->hdr.size; t = tag_next(t)) if (t->hdr.tag == ATAG_MEM && diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index 909489f4d23..cd0389c6e82 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -1,10 +1,29 @@ #ifndef __ARCH_ORION5X_COMMON_H #define __ARCH_ORION5X_COMMON_H +#include <linux/reboot.h> + struct dsa_platform_data; struct mv643xx_eth_platform_data; struct mv_sata_platform_data; +#define ORION_MBUS_PCIE_MEM_TARGET 0x04 +#define ORION_MBUS_PCIE_MEM_ATTR 0x59 +#define ORION_MBUS_PCIE_IO_TARGET 0x04 +#define ORION_MBUS_PCIE_IO_ATTR 0x51 +#define ORION_MBUS_PCIE_WA_TARGET 0x04 +#define ORION_MBUS_PCIE_WA_ATTR 0x79 +#define ORION_MBUS_PCI_MEM_TARGET 0x03 +#define ORION_MBUS_PCI_MEM_ATTR 0x59 +#define ORION_MBUS_PCI_IO_TARGET 0x03 +#define ORION_MBUS_PCI_IO_ATTR 0x51 +#define ORION_MBUS_DEVBUS_BOOT_TARGET 0x01 +#define ORION_MBUS_DEVBUS_BOOT_ATTR 0x0f +#define ORION_MBUS_DEVBUS_TARGET(cs) 0x01 +#define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs)) +#define ORION_MBUS_SRAM_TARGET 0x09 +#define ORION_MBUS_SRAM_ATTR 0x00 + /* * Basic Orion init functions used early by machine-setup. */ @@ -12,22 +31,12 @@ void orion5x_map_io(void); void orion5x_init_early(void); void orion5x_init_irq(void); void orion5x_init(void); +void orion5x_id(u32 *dev, u32 *rev, char **dev_name); +void clk_init(void); extern int orion5x_tclk; -extern struct sys_timer orion5x_timer; +extern void orion5x_timer_init(void); -/* - * Enumerations and functions for Orion windows mapping. Used by Orion core - * functions to map its interfaces and by the machine-setup to map its on- - * board devices. Details in /mach-orion/addr-map.c - */ -extern struct mbus_dram_target_info orion5x_mbus_dram_info; -void orion5x_setup_cpu_mbus_bridge(void); -void orion5x_setup_dev_boot_win(u32 base, u32 size); -void orion5x_setup_dev0_win(u32 base, u32 size); -void orion5x_setup_dev1_win(u32 base, u32 size); -void orion5x_setup_dev2_win(u32 base, u32 size); -void orion5x_setup_pcie_wa_win(u32 base, u32 size); -int orion5x_setup_sram_win(void); +void orion5x_setup_wins(void); void orion5x_ehci0_init(void); void orion5x_ehci1_init(void); @@ -39,12 +48,14 @@ void orion5x_spi_init(void); void orion5x_uart0_init(void); void orion5x_uart1_init(void); void orion5x_xor_init(void); +void orion5x_restart(enum reboot_mode, const char *); /* * PCIe/PCI functions. */ struct pci_bus; struct pci_sys_data; +struct pci_dev; void orion5x_pcie_id(u32 *dev, u32 *rev); void orion5x_pci_disable(void); @@ -53,9 +64,23 @@ int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); int orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); -struct meminfo; struct tag; -extern void __init tag_fixup_mem32(struct tag *, char **, struct meminfo *); +extern void __init tag_fixup_mem32(struct tag *, char **); +#ifdef CONFIG_MACH_MSS2_DT +extern void mss2_init(void); +#else +static inline void mss2_init(void) {} +#endif + +/***************************************************************************** + * Helpers to access Orion registers + ****************************************************************************/ +/* + * These are not preempt-safe. Locks, if needed, must be taken + * care of by the caller. + */ +#define orion5x_setbits(r, mask) writel(readl(r) | (mask), (r)) +#define orion5x_clrbits(r, mask) writel(readl(r) & ~(mask), (r)) #endif diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c deleted file mode 100644 index 8c8300951f4..00000000000 --- a/arch/arm/mach-orion5x/d2net-setup.c +++ /dev/null @@ -1,360 +0,0 @@ -/* - * arch/arm/mach-orion5x/d2net-setup.c - * - * LaCie d2Network and Big Disk Network NAS setup - * - * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/pci.h> -#include <linux/irq.h> -#include <linux/mtd/physmap.h> -#include <linux/mv643xx_eth.h> -#include <linux/leds.h> -#include <linux/gpio_keys.h> -#include <linux/input.h> -#include <linux/i2c.h> -#include <linux/ata_platform.h> -#include <linux/gpio.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/pci.h> -#include <mach/orion5x.h> -#include "common.h" -#include "mpp.h" - -/***************************************************************************** - * LaCie d2 Network Info - ****************************************************************************/ - -/* - * 512KB NOR flash Device bus boot chip select - */ - -#define D2NET_NOR_BOOT_BASE 0xfff80000 -#define D2NET_NOR_BOOT_SIZE SZ_512K - -/***************************************************************************** - * 512KB NOR Flash on Boot Device - ****************************************************************************/ - -/* - * TODO: Check write support on flash MX29LV400CBTC-70G - */ - -static struct mtd_partition d2net_partitions[] = { - { - .name = "Full512kb", - .size = MTDPART_SIZ_FULL, - .offset = 0, - .mask_flags = MTD_WRITEABLE, - }, -}; - -static struct physmap_flash_data d2net_nor_flash_data = { - .width = 1, - .parts = d2net_partitions, - .nr_parts = ARRAY_SIZE(d2net_partitions), -}; - -static struct resource d2net_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = D2NET_NOR_BOOT_BASE, - .end = D2NET_NOR_BOOT_BASE - + D2NET_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device d2net_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &d2net_nor_flash_data, - }, - .num_resources = 1, - .resource = &d2net_nor_flash_resource, -}; - -/***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data d2net_eth_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -/***************************************************************************** - * I2C devices - ****************************************************************************/ - -/* - * i2c addr | chip | description - * 0x32 | Ricoh 5C372b | RTC - * 0x3e | GMT G762 | PWM fan controller - * 0x50 | HT24LC08 | eeprom (1kB) - * - * TODO: Add G762 support to the g760a driver. - */ -static struct i2c_board_info __initdata d2net_i2c_devices[] = { - { - I2C_BOARD_INFO("rs5c372b", 0x32), - }, { - I2C_BOARD_INFO("24c08", 0x50), - }, -}; - -/***************************************************************************** - * SATA - ****************************************************************************/ - -static struct mv_sata_platform_data d2net_sata_data = { - .n_ports = 2, -}; - -#define D2NET_GPIO_SATA0_POWER 3 -#define D2NET_GPIO_SATA1_POWER 12 - -static void __init d2net_sata_power_init(void) -{ - int err; - - err = gpio_request(D2NET_GPIO_SATA0_POWER, "SATA0 power"); - if (err == 0) { - err = gpio_direction_output(D2NET_GPIO_SATA0_POWER, 1); - if (err) - gpio_free(D2NET_GPIO_SATA0_POWER); - } - if (err) - pr_err("d2net: failed to configure SATA0 power GPIO\n"); - - err = gpio_request(D2NET_GPIO_SATA1_POWER, "SATA1 power"); - if (err == 0) { - err = gpio_direction_output(D2NET_GPIO_SATA1_POWER, 1); - if (err) - gpio_free(D2NET_GPIO_SATA1_POWER); - } - if (err) - pr_err("d2net: failed to configure SATA1 power GPIO\n"); -} - -/***************************************************************************** - * GPIO LED's - ****************************************************************************/ - -/* - * The blue front LED is wired to the CPLD and can blink in relation with the - * SATA activity. - * - * The following array detail the different LED registers and the combination - * of their possible values: - * - * led_off | blink_ctrl | SATA active | LED state - * | | | - * 1 | x | x | off - * 0 | 0 | 0 | off - * 0 | 1 | 0 | blink (rate 300ms) - * 0 | x | 1 | on - * - * Notes: The blue and the red front LED's can't be on at the same time. - * Red LED have priority. - */ - -#define D2NET_GPIO_RED_LED 6 -#define D2NET_GPIO_BLUE_LED_BLINK_CTRL 16 -#define D2NET_GPIO_BLUE_LED_OFF 23 - -static struct gpio_led d2net_leds[] = { - { - .name = "d2net:blue:sata", - .default_trigger = "default-on", - .gpio = D2NET_GPIO_BLUE_LED_OFF, - .active_low = 1, - }, - { - .name = "d2net:red:fail", - .gpio = D2NET_GPIO_RED_LED, - }, -}; - -static struct gpio_led_platform_data d2net_led_data = { - .num_leds = ARRAY_SIZE(d2net_leds), - .leds = d2net_leds, -}; - -static struct platform_device d2net_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &d2net_led_data, - }, -}; - -static void __init d2net_gpio_leds_init(void) -{ - int err; - - /* Configure GPIO over MPP max number. */ - orion_gpio_set_valid(D2NET_GPIO_BLUE_LED_OFF, 1); - - /* Configure register blink_ctrl to allow SATA activity LED blinking. */ - err = gpio_request(D2NET_GPIO_BLUE_LED_BLINK_CTRL, "blue LED blink"); - if (err == 0) { - err = gpio_direction_output(D2NET_GPIO_BLUE_LED_BLINK_CTRL, 1); - if (err) - gpio_free(D2NET_GPIO_BLUE_LED_BLINK_CTRL); - } - if (err) - pr_err("d2net: failed to configure blue LED blink GPIO\n"); - - platform_device_register(&d2net_gpio_leds); -} - -/**************************************************************************** - * GPIO keys - ****************************************************************************/ - -#define D2NET_GPIO_PUSH_BUTTON 18 -#define D2NET_GPIO_POWER_SWITCH_ON 8 -#define D2NET_GPIO_POWER_SWITCH_OFF 9 - -#define D2NET_SWITCH_POWER_ON 0x1 -#define D2NET_SWITCH_POWER_OFF 0x2 - -static struct gpio_keys_button d2net_buttons[] = { - { - .type = EV_SW, - .code = D2NET_SWITCH_POWER_OFF, - .gpio = D2NET_GPIO_POWER_SWITCH_OFF, - .desc = "Power rocker switch (auto|off)", - .active_low = 0, - }, - { - .type = EV_SW, - .code = D2NET_SWITCH_POWER_ON, - .gpio = D2NET_GPIO_POWER_SWITCH_ON, - .desc = "Power rocker switch (on|auto)", - .active_low = 0, - }, - { - .type = EV_KEY, - .code = KEY_POWER, - .gpio = D2NET_GPIO_PUSH_BUTTON, - .desc = "Front Push Button", - .active_low = 0, - }, -}; - -static struct gpio_keys_platform_data d2net_button_data = { - .buttons = d2net_buttons, - .nbuttons = ARRAY_SIZE(d2net_buttons), -}; - -static struct platform_device d2net_gpio_buttons = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &d2net_button_data, - }, -}; - -/***************************************************************************** - * General Setup - ****************************************************************************/ - -static unsigned int d2net_mpp_modes[] __initdata = { - MPP0_GPIO, /* Board ID (bit 0) */ - MPP1_GPIO, /* Board ID (bit 1) */ - MPP2_GPIO, /* Board ID (bit 2) */ - MPP3_GPIO, /* SATA 0 power */ - MPP4_UNUSED, - MPP5_GPIO, /* Fan fail detection */ - MPP6_GPIO, /* Red front LED */ - MPP7_UNUSED, - MPP8_GPIO, /* Rear power switch (on|auto) */ - MPP9_GPIO, /* Rear power switch (auto|off) */ - MPP10_UNUSED, - MPP11_UNUSED, - MPP12_GPIO, /* SATA 1 power */ - MPP13_UNUSED, - MPP14_SATA_LED, /* SATA 0 active */ - MPP15_SATA_LED, /* SATA 1 active */ - MPP16_GPIO, /* Blue front LED blink control */ - MPP17_UNUSED, - MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */ - MPP19_UNUSED, - 0, - /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */ - /* 23: Blue front LED off */ - /* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */ -}; - -#define D2NET_GPIO_INHIBIT_POWER_OFF 24 - -static void __init d2net_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(d2net_mpp_modes); - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_eth_init(&d2net_eth_data); - orion5x_i2c_init(); - orion5x_uart0_init(); - - d2net_sata_power_init(); - orion5x_sata_init(&d2net_sata_data); - - orion5x_setup_dev_boot_win(D2NET_NOR_BOOT_BASE, - D2NET_NOR_BOOT_SIZE); - platform_device_register(&d2net_nor_flash); - - platform_device_register(&d2net_gpio_buttons); - - d2net_gpio_leds_init(); - - pr_notice("d2net: Flash write are not yet supported.\n"); - - i2c_register_board_info(0, d2net_i2c_devices, - ARRAY_SIZE(d2net_i2c_devices)); - - orion_gpio_set_valid(D2NET_GPIO_INHIBIT_POWER_OFF, 1); -} - -/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */ - -#ifdef CONFIG_MACH_D2NET -MACHINE_START(D2NET, "LaCie d2 Network") - .atag_offset = 0x100, - .init_machine = d2net_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, - .fixup = tag_fixup_mem32, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_BIGDISK -MACHINE_START(BIGDISK, "LaCie Big Disk Network") - .atag_offset = 0x100, - .init_machine = d2net_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, - .fixup = tag_fixup_mem32, -MACHINE_END -#endif - diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index 4b79a80d5e1..dc01c4ffc9a 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -24,7 +24,7 @@ #include <asm/mach/arch.h> #include <asm/mach/pci.h> #include <mach/orion5x.h> -#include <plat/orion_nand.h> +#include <linux/platform_data/mtd-orion_nand.h> #include "common.h" #include "mpp.h" @@ -202,7 +202,7 @@ __initcall(db88f5281_7seg_init); * PCI ****************************************************************************/ -void __init db88f5281_pci_preinit(void) +static void __init db88f5281_pci_preinit(void) { int pin; @@ -214,7 +214,7 @@ void __init db88f5281_pci_preinit(void) if (gpio_direction_input(pin) == 0) { irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { - printk(KERN_ERR "db88f5281_pci_preinit faield to " + printk(KERN_ERR "db88f5281_pci_preinit failed to " "set_irq_type pin %d\n", pin); gpio_free(pin); } @@ -227,7 +227,7 @@ void __init db88f5281_pci_preinit(void) if (gpio_direction_input(pin) == 0) { irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { - printk(KERN_ERR "db88f5281_pci_preinit faield " + printk(KERN_ERR "db88f5281_pci_preinit failed " "to set_irq_type pin %d\n", pin); gpio_free(pin); } @@ -265,7 +265,6 @@ static int __init db88f5281_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci db88f5281_pci __initdata = { .nr_controllers = 2, .preinit = db88f5281_pci_preinit, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = db88f5281_pci_map_irq, @@ -341,16 +340,27 @@ static void __init db88f5281_init(void) orion5x_uart0_init(); orion5x_uart1_init(); - orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, - DB88F5281_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + DB88F5281_NOR_BOOT_BASE, + DB88F5281_NOR_BOOT_SIZE); platform_device_register(&db88f5281_boot_flash); - orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0), + ORION_MBUS_DEVBUS_ATTR(0), + DB88F5281_7SEG_BASE, + DB88F5281_7SEG_SIZE); - orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1), + ORION_MBUS_DEVBUS_ATTR(1), + DB88F5281_NOR_BASE, + DB88F5281_NOR_SIZE); platform_device_register(&db88f5281_nor_flash); - orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2), + ORION_MBUS_DEVBUS_ATTR(2), + DB88F5281_NAND_BASE, + DB88F5281_NAND_SIZE); platform_device_register(&db88f5281_nand_flash); i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); @@ -363,5 +373,6 @@ MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, + .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 343f60e9639..56edeab17b6 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -32,7 +32,9 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/pci.h> +#include <asm/system_info.h> #include <mach/orion5x.h> +#include <plat/orion-gpio.h> #include "common.h" #include "mpp.h" @@ -85,7 +87,6 @@ static int __init dns323_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci dns323_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = dns323_pci_map_irq, @@ -252,27 +253,6 @@ error_fail: * GPIO LEDs (simple - doesn't use hardware blinking support) */ -#define ORION_BLINK_HALF_PERIOD 100 /* ms */ - -static int dns323_gpio_blink_set(unsigned gpio, int state, - unsigned long *delay_on, unsigned long *delay_off) -{ - - if (delay_on && delay_off && !*delay_on && !*delay_off) - *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD; - - switch(state) { - case GPIO_LED_NO_BLINK_LOW: - case GPIO_LED_NO_BLINK_HIGH: - orion_gpio_set_blink(gpio, 0); - gpio_set_value(gpio, state); - break; - case GPIO_LED_BLINK: - orion_gpio_set_blink(gpio, 1); - } - return 0; -} - static struct gpio_led dns323ab_leds[] = { { .name = "power:blue", @@ -311,13 +291,13 @@ static struct gpio_led dns323c_leds[] = { static struct gpio_led_platform_data dns323ab_led_data = { .num_leds = ARRAY_SIZE(dns323ab_leds), .leds = dns323ab_leds, - .gpio_blink_set = dns323_gpio_blink_set, + .gpio_blink_set = orion_gpio_led_blink_set, }; static struct gpio_led_platform_data dns323c_led_data = { .num_leds = ARRAY_SIZE(dns323c_leds), .leds = dns323c_leds, - .gpio_blink_set = dns323_gpio_blink_set, + .gpio_blink_set = orion_gpio_led_blink_set, }; static struct platform_device dns323_gpio_leds = { @@ -631,7 +611,10 @@ static void __init dns323_init(void) /* setup flash mapping * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 */ - orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + DNS323_NOR_BOOT_BASE, + DNS323_NOR_BOOT_SIZE); platform_device_register(&dns323_nor_flash); /* Sort out LEDs, Buttons and i2c devices */ @@ -659,6 +642,8 @@ static void __init dns323_init(void) platform_device_register_simple("dns323c-fan", 0, NULL, 0); /* Register fixup for the PHY LEDs */ + if (!IS_BUILTIN(CONFIG_PHYLIB)) + break; phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK, dns323c_phy_fixup); @@ -721,7 +706,7 @@ static void __init dns323_init(void) * Note: AFAIK, rev B1 needs the same treatement but I'll let * somebody else test it. */ - writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c); + writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c); break; } } @@ -734,6 +719,7 @@ MACHINE_START(DNS323, "D-Link DNS-323") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, + .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c deleted file mode 100644 index 70a4e9265f0..00000000000 --- a/arch/arm/mach-orion5x/edmini_v2-setup.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * arch/arm/mach-orion5x/edmini_v2-setup.c - * - * LaCie Ethernet Disk mini V2 Setup - * - * Copyright (C) 2008 Christopher Moore <moore@free.fr> - * Copyright (C) 2008 Albert Aribaud <albert.aribaud@free.fr> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/* - * TODO: add Orion USB device port init when kernel.org support is added. - * TODO: add flash write support: see below. - * TODO: add power-off support. - * TODO: add I2C EEPROM support. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/pci.h> -#include <linux/irq.h> -#include <linux/mtd/physmap.h> -#include <linux/mv643xx_eth.h> -#include <linux/leds.h> -#include <linux/gpio_keys.h> -#include <linux/input.h> -#include <linux/i2c.h> -#include <linux/ata_platform.h> -#include <linux/gpio.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/pci.h> -#include <mach/orion5x.h> -#include "common.h" -#include "mpp.h" - -/***************************************************************************** - * EDMINI_V2 Info - ****************************************************************************/ - -/* - * 512KB NOR flash Device bus boot chip select - */ - -#define EDMINI_V2_NOR_BOOT_BASE 0xfff80000 -#define EDMINI_V2_NOR_BOOT_SIZE SZ_512K - -/***************************************************************************** - * 512KB NOR Flash on BOOT Device - ****************************************************************************/ - -/* - * Currently the MTD code does not recognize the MX29LV400CBCT as a bottom - * -type device. This could cause risks of accidentally erasing critical - * flash sectors. We thus define a single, write-protected partition covering - * the whole flash. - * TODO: once the flash part TOP/BOTTOM detection issue is sorted out in the MTD - * code, break this into at least three partitions: 'u-boot code', 'u-boot - * environment' and 'whatever is left'. - */ - -static struct mtd_partition edmini_v2_partitions[] = { - { - .name = "Full512kb", - .size = 0x00080000, - .offset = 0x00000000, - .mask_flags = MTD_WRITEABLE, - }, -}; - -static struct physmap_flash_data edmini_v2_nor_flash_data = { - .width = 1, - .parts = edmini_v2_partitions, - .nr_parts = ARRAY_SIZE(edmini_v2_partitions), -}; - -static struct resource edmini_v2_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = EDMINI_V2_NOR_BOOT_BASE, - .end = EDMINI_V2_NOR_BOOT_BASE - + EDMINI_V2_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device edmini_v2_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &edmini_v2_nor_flash_data, - }, - .num_resources = 1, - .resource = &edmini_v2_nor_flash_resource, -}; - -/***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data edmini_v2_eth_data = { - .phy_addr = 8, -}; - -/***************************************************************************** - * RTC 5C372a on I2C bus - ****************************************************************************/ - -#define EDMINIV2_RTC_GPIO 3 - -static struct i2c_board_info __initdata edmini_v2_i2c_rtc = { - I2C_BOARD_INFO("rs5c372a", 0x32), - .irq = 0, -}; - -/***************************************************************************** - * Sata - ****************************************************************************/ - -static struct mv_sata_platform_data edmini_v2_sata_data = { - .n_ports = 2, -}; - -/***************************************************************************** - * GPIO LED (simple - doesn't use hardware blinking support) - ****************************************************************************/ - -#define EDMINI_V2_GPIO_LED_POWER 16 - -static struct gpio_led edmini_v2_leds[] = { - { - .name = "power:blue", - .gpio = EDMINI_V2_GPIO_LED_POWER, - .active_low = 1, - }, -}; - -static struct gpio_led_platform_data edmini_v2_led_data = { - .num_leds = ARRAY_SIZE(edmini_v2_leds), - .leds = edmini_v2_leds, -}; - -static struct platform_device edmini_v2_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &edmini_v2_led_data, - }, -}; - -/**************************************************************************** - * GPIO key - ****************************************************************************/ - -#define EDMINI_V2_GPIO_KEY_POWER 18 - -static struct gpio_keys_button edmini_v2_buttons[] = { - { - .code = KEY_POWER, - .gpio = EDMINI_V2_GPIO_KEY_POWER, - .desc = "Power Button", - .active_low = 0, - }, -}; - -static struct gpio_keys_platform_data edmini_v2_button_data = { - .buttons = edmini_v2_buttons, - .nbuttons = ARRAY_SIZE(edmini_v2_buttons), -}; - -static struct platform_device edmini_v2_gpio_buttons = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &edmini_v2_button_data, - }, -}; - -/***************************************************************************** - * General Setup - ****************************************************************************/ -static unsigned int edminiv2_mpp_modes[] __initdata = { - MPP0_UNUSED, - MPP1_UNUSED, - MPP2_UNUSED, - MPP3_GPIO, /* RTC interrupt */ - MPP4_UNUSED, - MPP5_UNUSED, - MPP6_UNUSED, - MPP7_UNUSED, - MPP8_UNUSED, - MPP9_UNUSED, - MPP10_UNUSED, - MPP11_UNUSED, - MPP12_SATA_LED, /* SATA 0 presence */ - MPP13_SATA_LED, /* SATA 1 presence */ - MPP14_SATA_LED, /* SATA 0 active */ - MPP15_SATA_LED, /* SATA 1 active */ - /* 16: Power LED control (0 = On, 1 = Off) */ - MPP16_GPIO, - /* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */ - MPP17_GPIO, - /* 18: Power button status (0 = Released, 1 = Pressed) */ - MPP18_GPIO, - MPP19_UNUSED, - 0, -}; - -static void __init edmini_v2_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(edminiv2_mpp_modes); - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_eth_init(&edmini_v2_eth_data); - orion5x_i2c_init(); - orion5x_sata_init(&edmini_v2_sata_data); - orion5x_uart0_init(); - - orion5x_setup_dev_boot_win(EDMINI_V2_NOR_BOOT_BASE, - EDMINI_V2_NOR_BOOT_SIZE); - platform_device_register(&edmini_v2_nor_flash); - platform_device_register(&edmini_v2_gpio_leds); - platform_device_register(&edmini_v2_gpio_buttons); - - pr_notice("edmini_v2: USB device port, flash write and power-off " - "are not yet supported.\n"); - - /* Get RTC IRQ and register the chip */ - if (gpio_request(EDMINIV2_RTC_GPIO, "rtc") == 0) { - if (gpio_direction_input(EDMINIV2_RTC_GPIO) == 0) - edmini_v2_i2c_rtc.irq = gpio_to_irq(EDMINIV2_RTC_GPIO); - else - gpio_free(EDMINIV2_RTC_GPIO); - } - - if (edmini_v2_i2c_rtc.irq == 0) - pr_warning("edmini_v2: failed to get RTC IRQ\n"); - - i2c_register_board_info(0, &edmini_v2_i2c_rtc, 1); -} - -/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */ -MACHINE_START(EDMINI_V2, "LaCie Ethernet Disk mini V2") - /* Maintainer: Christopher Moore <moore@free.fr> */ - .atag_offset = 0x100, - .init_machine = edmini_v2_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, - .fixup = tag_fixup_mem32, -MACHINE_END diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h index 96484bcd34c..5766e3fbff6 100644 --- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h +++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h @@ -13,27 +13,25 @@ #include <mach/orion5x.h> -#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE | 0x100) +#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100) -#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104) +#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) -#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108) -#define WDT_RESET_OUT_EN 0x0002 +#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108) +#define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108) -#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c) +#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c) -#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110) +#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110) -#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C) - -#define WDT_INT_REQ 0x0008 +#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C) #define BRIDGE_INT_TIMER1_CLR (~0x0004) -#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200) - -#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x204) +#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200) -#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) +#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204) +#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300) +#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300) #endif diff --git a/arch/arm/mach-orion5x/include/mach/debug-macro.S b/arch/arm/mach-orion5x/include/mach/debug-macro.S deleted file mode 100644 index f340ed8f8dd..00000000000 --- a/arch/arm/mach-orion5x/include/mach/debug-macro.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/debug-macro.S - * - * Debugging macro include header - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <mach/orion5x.h> - - .macro addruart, rp, rv, tmp - ldr \rp, =ORION5X_REGS_PHYS_BASE - ldr \rv, =ORION5X_REGS_VIRT_BASE - orr \rp, \rp, #0x00012000 - orr \rv, \rv, #0x00012000 - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-orion5x/include/mach/entry-macro.S b/arch/arm/mach-orion5x/include/mach/entry-macro.S index d658992e540..79eb502a1e6 100644 --- a/arch/arm/mach-orion5x/include/mach/entry-macro.S +++ b/arch/arm/mach-orion5x/include/mach/entry-macro.S @@ -10,12 +10,6 @@ #include <mach/bridge-regs.h> - .macro disable_fiq - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - .macro get_irqnr_preamble, base, tmp ldr \base, =MAIN_IRQ_CAUSE .endm diff --git a/arch/arm/mach-orion5x/include/mach/gpio.h b/arch/arm/mach-orion5x/include/mach/gpio.h deleted file mode 100644 index a1d0b78decb..00000000000 --- a/arch/arm/mach-orion5x/include/mach/gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/gpio.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <plat/gpio.h> diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h deleted file mode 100644 index c5196101a23..00000000000 --- a/arch/arm/mach-orion5x/include/mach/io.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/io.h - * - * Tzachi Perelstein <tzachi@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include "orion5x.h" - -#define IO_SPACE_LIMIT 0xffffffff - -static inline void __iomem * -__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) -{ - void __iomem *retval; - unsigned long offs = paddr - ORION5X_REGS_PHYS_BASE; - if (mtype == MT_DEVICE && size && offs < ORION5X_REGS_SIZE && - size <= ORION5X_REGS_SIZE && offs + size <= ORION5X_REGS_SIZE) { - retval = (void __iomem *)ORION5X_REGS_VIRT_BASE + offs; - } else { - retval = __arm_ioremap(paddr, size, mtype); - } - - return retval; -} - -static inline void -__arch_iounmap(void __iomem *addr) -{ - if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE || - addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE)) - __iounmap(addr); -} - -#define __arch_ioremap __arch_ioremap -#define __arch_iounmap __arch_iounmap -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) - - -/***************************************************************************** - * Helpers to access Orion registers - ****************************************************************************/ -/* - * These are not preempt-safe. Locks, if needed, must be taken - * care of by the caller. - */ -#define orion5x_setbits(r, mask) writel(readl(r) | (mask), (r)) -#define orion5x_clrbits(r, mask) writel(readl(r) & ~(mask), (r)) - - -#endif diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 0a28bbc7689..b78ff324886 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -31,31 +31,29 @@ * fc000000 device bus mappings (cs0/cs1) * * virt phys size - * fdd00000 f1000000 1M on-chip peripheral registers - * fde00000 f2000000 1M PCIe I/O space - * fdf00000 f2100000 1M PCI I/O space - * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) + * fe000000 f1000000 1M on-chip peripheral registers + * fee00000 f2000000 64K PCIe I/O space + * fee10000 f2100000 64K PCI I/O space + * fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) ****************************************************************************/ #define ORION5X_REGS_PHYS_BASE 0xf1000000 -#define ORION5X_REGS_VIRT_BASE 0xfdd00000 +#define ORION5X_REGS_VIRT_BASE IOMEM(0xfe000000) #define ORION5X_REGS_SIZE SZ_1M #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 -#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000 -#define ORION5X_PCIE_IO_SIZE SZ_1M +#define ORION5X_PCIE_IO_SIZE SZ_64K #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 -#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 -#define ORION5X_PCI_IO_BUS_BASE 0x00100000 -#define ORION5X_PCI_IO_SIZE SZ_1M +#define ORION5X_PCI_IO_BUS_BASE 0x00010000 +#define ORION5X_PCI_IO_SIZE SZ_64K #define ORION5X_SRAM_PHYS_BASE (0xf2200000) #define ORION5X_SRAM_SIZE SZ_8K /* Relevant only for Orion-1/Orion-NAS */ #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 -#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 +#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000) #define ORION5X_PCIE_WA_SIZE SZ_16M #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 @@ -68,41 +66,46 @@ * Orion Registers Map ******************************************************************************/ -#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) - -#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) -#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) -#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) +#define ORION5X_DDR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x00000) +#define ORION5X_DDR_WINS_BASE (ORION5X_DDR_PHYS_BASE + 0x1500) +#define ORION5X_DDR_WINS_SZ (0x10) +#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000) +#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000) +#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000) +#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x)) #define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100) -#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600) -#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000) -#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) +#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x0600) +#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x1000) +#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2000) +#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2000) +#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2100) +#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2100) -#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) +#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000) +#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000) +#define ORION5X_BRIDGE_WINS_BASE (ORION5X_BRIDGE_PHYS_BASE) +#define ORION5X_BRIDGE_WINS_SZ (0x80) -#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) +#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000) -#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) +#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x40000) -#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) -#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) +#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x50000) +#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x50000) -#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900) -#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900) +#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x60900) +#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x60900) -#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) -#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) +#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x70000) +#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x70000) -#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) -#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) +#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x80000) +#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x80000) -#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x90000) +#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x90000) -#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) -#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) +#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0xa0000) +#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0xa0000) /******************************************************************************* * Device Bus Registers diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h deleted file mode 100644 index a1d6e46ab03..00000000000 --- a/arch/arm/mach-orion5x/include/mach/system.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/system.h - * - * Tzachi Perelstein <tzachi@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -#include <mach/bridge-regs.h> - -static inline void arch_idle(void) -{ - cpu_do_idle(); -} - -static inline void arch_reset(char mode, const char *cmd) -{ - /* - * Enable and issue soft reset - */ - orion5x_setbits(RSTOUTn_MASK, (1 << 2)); - orion5x_setbits(CPU_SOFT_RESET, 1); - mdelay(200); - orion5x_clrbits(CPU_SOFT_RESET, 1); -} - - -#endif diff --git a/arch/arm/mach-orion5x/include/mach/timex.h b/arch/arm/mach-orion5x/include/mach/timex.h deleted file mode 100644 index 4c69820e081..00000000000 --- a/arch/arm/mach-orion5x/include/mach/timex.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/timex.h - * - * Tzachi Perelstein <tzachi@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define CLOCK_TICK_RATE (100 * HZ) diff --git a/arch/arm/mach-orion5x/include/mach/uncompress.h b/arch/arm/mach-orion5x/include/mach/uncompress.h index 4322dba468a..abd26b542c3 100644 --- a/arch/arm/mach-orion5x/include/mach/uncompress.h +++ b/arch/arm/mach-orion5x/include/mach/uncompress.h @@ -46,4 +46,3 @@ static void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-orion5x/include/mach/vmalloc.h b/arch/arm/mach-orion5x/include/mach/vmalloc.h deleted file mode 100644 index 06b50aeff7b..00000000000 --- a/arch/arm/mach-orion5x/include/mach/vmalloc.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/vmalloc.h - */ - -#define VMALLOC_END 0xfd800000UL diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index b1b45fff776..cd4bac4d7e4 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -11,30 +11,55 @@ */ #include <linux/gpio.h> #include <linux/kernel.h> -#include <linux/init.h> #include <linux/irq.h> #include <linux/io.h> #include <mach/bridge-regs.h> +#include <plat/orion-gpio.h> #include <plat/irq.h> +#include <asm/exception.h> #include "common.h" -static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +static int __initdata gpio0_irqs[4] = { + IRQ_ORION5X_GPIO_0_7, + IRQ_ORION5X_GPIO_8_15, + IRQ_ORION5X_GPIO_16_23, + IRQ_ORION5X_GPIO_24_31, +}; + +#ifdef CONFIG_MULTI_IRQ_HANDLER +/* + * Compiling with both non-DT and DT support enabled, will + * break asm irq handler used by non-DT boards. Therefore, + * we provide a C-style irq handler even for non-DT boards, + * if MULTI_IRQ_HANDLER is set. + */ + +asmlinkage void +__exception_irq_entry orion5x_legacy_handle_irq(struct pt_regs *regs) { - BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); + u32 stat; - orion_gpio_irq_handler((irq - IRQ_ORION5X_GPIO_0_7) << 3); + stat = readl_relaxed(MAIN_IRQ_CAUSE); + stat &= readl_relaxed(MAIN_IRQ_MASK); + if (stat) { + unsigned int hwirq = __fls(stat); + handle_IRQ(hwirq, regs); + return; + } } +#endif void __init orion5x_init_irq(void) { - orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); + orion_irq_init(0, MAIN_IRQ_MASK); + +#ifdef CONFIG_MULTI_IRQ_HANDLER + set_handle_irq(orion5x_legacy_handle_irq); +#endif /* * Initialize gpiolib for GPIOs 0-31. */ - orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START); - irq_set_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); - irq_set_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); - irq_set_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); - irq_set_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler); + orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, 0, + IRQ_ORION5X_GPIO_START, gpio0_irqs); } diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index d3cd3f63258..fe6a48a325e 100644 --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c @@ -24,7 +24,7 @@ #include <asm/mach/arch.h> #include <asm/mach/pci.h> #include <mach/orion5x.h> -#include <plat/orion_nand.h> +#include <linux/platform_data/mtd-orion_nand.h> #include "common.h" #include "mpp.h" @@ -138,7 +138,6 @@ static int __init kurobox_pro_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci kurobox_pro_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = kurobox_pro_pci_map_irq, @@ -360,13 +359,17 @@ static void __init kurobox_pro_init(void) orion5x_uart1_init(); orion5x_xor_init(); - orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, - KUROBOX_PRO_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + KUROBOX_PRO_NOR_BOOT_BASE, + KUROBOX_PRO_NOR_BOOT_SIZE); platform_device_register(&kurobox_pro_nor_flash); if (machine_is_kurobox_pro()) { - orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, - KUROBOX_PRO_NAND_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0), + ORION_MBUS_DEVBUS_ATTR(0), + KUROBOX_PRO_NAND_BASE, + KUROBOX_PRO_NAND_SIZE); platform_device_register(&kurobox_pro_nand_flash); } @@ -384,8 +387,9 @@ MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, + .restart = orion5x_restart, MACHINE_END #endif @@ -397,7 +401,8 @@ MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, + .restart = orion5x_restart, MACHINE_END #endif diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c index 9503fff404e..028ea038d40 100644 --- a/arch/arm/mach-orion5x/ls-chl-setup.c +++ b/arch/arm/mach-orion5x/ls-chl-setup.c @@ -22,7 +22,6 @@ #include <linux/gpio.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/system.h> #include <mach/orion5x.h> #include "common.h" #include "mpp.h" @@ -140,7 +139,7 @@ static struct mv_sata_platform_data lschl_sata_data = { static void lschl_power_off(void) { - arm_machine_restart('h', NULL); + orion5x_restart(REBOOT_HARD, NULL); } /***************************************************************************** @@ -295,8 +294,10 @@ static void __init lschl_init(void) orion5x_uart0_init(); orion5x_xor_init(); - orion5x_setup_dev_boot_win(LSCHL_NOR_BOOT_BASE, - LSCHL_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + LSCHL_NOR_BOOT_BASE, + LSCHL_NOR_BOOT_SIZE); platform_device_register(&lschl_nor_flash); platform_device_register(&lschl_leds); @@ -323,6 +324,7 @@ MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, + .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c index ed6d772f4a2..32b7129b767 100644 --- a/arch/arm/mach-orion5x/ls_hgl-setup.c +++ b/arch/arm/mach-orion5x/ls_hgl-setup.c @@ -21,7 +21,6 @@ #include <linux/gpio.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/system.h> #include <mach/orion5x.h> #include "common.h" #include "mpp.h" @@ -186,7 +185,7 @@ static struct mv_sata_platform_data ls_hgl_sata_data = { static void ls_hgl_power_off(void) { - arm_machine_restart('h', NULL); + orion5x_restart(REBOOT_HARD, NULL); } @@ -244,8 +243,10 @@ static void __init ls_hgl_init(void) orion5x_uart0_init(); orion5x_xor_init(); - orion5x_setup_dev_boot_win(LS_HGL_NOR_BOOT_BASE, - LS_HGL_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + LS_HGL_NOR_BOOT_BASE, + LS_HGL_NOR_BOOT_SIZE); platform_device_register(&ls_hgl_nor_flash); platform_device_register(&ls_hgl_button_device); @@ -270,6 +271,7 @@ MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, + .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c index 743f7f1db18..a6493e76f96 100644 --- a/arch/arm/mach-orion5x/lsmini-setup.c +++ b/arch/arm/mach-orion5x/lsmini-setup.c @@ -21,7 +21,6 @@ #include <linux/gpio.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/system.h> #include <mach/orion5x.h> #include "common.h" #include "mpp.h" @@ -186,7 +185,7 @@ static struct mv_sata_platform_data lsmini_sata_data = { static void lsmini_power_off(void) { - arm_machine_restart('h', NULL); + orion5x_restart(REBOOT_HARD, NULL); } @@ -245,8 +244,10 @@ static void __init lsmini_init(void) orion5x_uart0_init(); orion5x_xor_init(); - orion5x_setup_dev_boot_win(LSMINI_NOR_BOOT_BASE, - LSMINI_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + LSMINI_NOR_BOOT_BASE, + LSMINI_NOR_BOOT_SIZE); platform_device_register(&lsmini_nor_flash); platform_device_register(&lsmini_button_device); @@ -272,7 +273,8 @@ MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, + .restart = orion5x_restart, MACHINE_END #endif diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c index b6ddd7a5db6..5b70026f478 100644 --- a/arch/arm/mach-orion5x/mpp.c +++ b/arch/arm/mach-orion5x/mpp.c @@ -10,7 +10,6 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mbus.h> #include <linux/io.h> #include <mach/hardware.h> #include <plat/mpp.h> diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h index eac68978a2c..db70e79a119 100644 --- a/arch/arm/mach-orion5x/mpp.h +++ b/arch/arm/mach-orion5x/mpp.h @@ -65,8 +65,8 @@ #define MPP8_GIGE MPP(8, 0x1, 0, 0, 1, 1, 1) #define MPP9_UNUSED MPP(9, 0x0, 0, 0, 1, 1, 1) -#define MPP9_GPIO MPP(9, 0x0, 0, 0, 1, 1, 1) -#define MPP9_GIGE MPP(9, 0x1, 1, 1, 1, 1, 1) +#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1, 1, 1) +#define MPP9_GIGE MPP(9, 0x1, 0, 0, 1, 1, 1) #define MPP10_UNUSED MPP(10, 0x0, 0, 0, 1, 1, 1) #define MPP10_GPIO MPP(10, 0x0, 1, 1, 1, 1, 1) diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c deleted file mode 100644 index 6020e26b1c7..00000000000 --- a/arch/arm/mach-orion5x/mss2-setup.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Maxtor Shared Storage II Board Setup - * - * Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/pci.h> -#include <linux/irq.h> -#include <linux/mtd/physmap.h> -#include <linux/mv643xx_eth.h> -#include <linux/leds.h> -#include <linux/gpio_keys.h> -#include <linux/input.h> -#include <linux/i2c.h> -#include <linux/ata_platform.h> -#include <linux/gpio.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/pci.h> -#include <mach/orion5x.h> -#include <mach/bridge-regs.h> -#include "common.h" -#include "mpp.h" - -#define MSS2_NOR_BOOT_BASE 0xff800000 -#define MSS2_NOR_BOOT_SIZE SZ_256K - -/***************************************************************************** - * Maxtor Shared Storage II Info - ****************************************************************************/ - -/* - * Maxtor Shared Storage II hardware : - * - Marvell 88F5182-A2 C500 - * - Marvell 88E1111 Gigabit Ethernet PHY - * - RTC M41T81 (@0x68) on I2C bus - * - 256KB NOR flash - * - 64MB of RAM - */ - -/***************************************************************************** - * 256KB NOR Flash on BOOT Device - ****************************************************************************/ - -static struct physmap_flash_data mss2_nor_flash_data = { - .width = 1, -}; - -static struct resource mss2_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = MSS2_NOR_BOOT_BASE, - .end = MSS2_NOR_BOOT_BASE + MSS2_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device mss2_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &mss2_nor_flash_data, - }, - .resource = &mss2_nor_flash_resource, - .num_resources = 1, -}; - -/**************************************************************************** - * PCI setup - ****************************************************************************/ -static int __init mss2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - /* - * Check for devices with hard-wired IRQs. - */ - irq = orion5x_pci_map_irq(dev, slot, pin); - if (irq != -1) - return irq; - - return -1; -} - -static struct hw_pci mss2_pci __initdata = { - .nr_controllers = 2, - .swizzle = pci_std_swizzle, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = mss2_pci_map_irq, -}; - -static int __init mss2_pci_init(void) -{ - if (machine_is_mss2()) - pci_common_init(&mss2_pci); - - return 0; -} -subsys_initcall(mss2_pci_init); - - -/***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data mss2_eth_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -/***************************************************************************** - * SATA - ****************************************************************************/ - -static struct mv_sata_platform_data mss2_sata_data = { - .n_ports = 2, -}; - -/***************************************************************************** - * GPIO buttons - ****************************************************************************/ - -#define MSS2_GPIO_KEY_RESET 12 -#define MSS2_GPIO_KEY_POWER 11 - -static struct gpio_keys_button mss2_buttons[] = { - { - .code = KEY_POWER, - .gpio = MSS2_GPIO_KEY_POWER, - .desc = "Power", - .active_low = 1, - }, { - .code = KEY_RESTART, - .gpio = MSS2_GPIO_KEY_RESET, - .desc = "Reset", - .active_low = 1, - }, -}; - -static struct gpio_keys_platform_data mss2_button_data = { - .buttons = mss2_buttons, - .nbuttons = ARRAY_SIZE(mss2_buttons), -}; - -static struct platform_device mss2_button_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &mss2_button_data, - }, -}; - -/***************************************************************************** - * RTC m41t81 on I2C bus - ****************************************************************************/ - -#define MSS2_GPIO_RTC_IRQ 3 - -static struct i2c_board_info __initdata mss2_i2c_rtc = { - I2C_BOARD_INFO("m41t81", 0x68), -}; - -/***************************************************************************** - * MSS2 power off method - ****************************************************************************/ -/* - * On the Maxtor Shared Storage II, the shutdown process is the following : - * - Userland modifies U-boot env to tell U-boot to go idle at next boot - * - The board reboots - * - U-boot starts and go into an idle mode until the user press "power" - */ -static void mss2_power_off(void) -{ - u32 reg; - - /* - * Enable and issue soft reset - */ - reg = readl(RSTOUTn_MASK); - reg |= 1 << 2; - writel(reg, RSTOUTn_MASK); - - reg = readl(CPU_SOFT_RESET); - reg |= 1; - writel(reg, CPU_SOFT_RESET); -} - -/**************************************************************************** - * General Setup - ****************************************************************************/ -static unsigned int mss2_mpp_modes[] __initdata = { - MPP0_GPIO, /* Power LED */ - MPP1_GPIO, /* Error LED */ - MPP2_UNUSED, - MPP3_GPIO, /* RTC interrupt */ - MPP4_GPIO, /* HDD ind. (Single/Dual)*/ - MPP5_GPIO, /* HD0 5V control */ - MPP6_GPIO, /* HD0 12V control */ - MPP7_GPIO, /* HD1 5V control */ - MPP8_GPIO, /* HD1 12V control */ - MPP9_UNUSED, - MPP10_GPIO, /* Fan control */ - MPP11_GPIO, /* Power button */ - MPP12_GPIO, /* Reset button */ - MPP13_UNUSED, - MPP14_SATA_LED, /* SATA 0 active */ - MPP15_SATA_LED, /* SATA 1 active */ - MPP16_UNUSED, - MPP17_UNUSED, - MPP18_UNUSED, - MPP19_UNUSED, - 0, -}; - -static void __init mss2_init(void) -{ - /* Setup basic Orion functions. Need to be called early. */ - orion5x_init(); - - orion5x_mpp_conf(mss2_mpp_modes); - - /* - * MPP[20] Unused - * MPP[21] PCI clock - * MPP[22] USB 0 over current - * MPP[23] USB 1 over current - */ - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_ehci1_init(); - orion5x_eth_init(&mss2_eth_data); - orion5x_i2c_init(); - orion5x_sata_init(&mss2_sata_data); - orion5x_uart0_init(); - orion5x_xor_init(); - - orion5x_setup_dev_boot_win(MSS2_NOR_BOOT_BASE, MSS2_NOR_BOOT_SIZE); - platform_device_register(&mss2_nor_flash); - - platform_device_register(&mss2_button_device); - - if (gpio_request(MSS2_GPIO_RTC_IRQ, "rtc") == 0) { - if (gpio_direction_input(MSS2_GPIO_RTC_IRQ) == 0) - mss2_i2c_rtc.irq = gpio_to_irq(MSS2_GPIO_RTC_IRQ); - else - gpio_free(MSS2_GPIO_RTC_IRQ); - } - i2c_register_board_info(0, &mss2_i2c_rtc, 1); - - /* register mss2 specific power-off method */ - pm_power_off = mss2_power_off; -} - -MACHINE_START(MSS2, "Maxtor Shared Storage II") - /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */ - .atag_offset = 0x100, - .init_machine = mss2_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, - .fixup = tag_fixup_mem32 -MACHINE_END diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c index 201ae367628..e032f01da49 100644 --- a/arch/arm/mach-orion5x/mv2120-setup.c +++ b/arch/arm/mach-orion5x/mv2120-setup.c @@ -204,7 +204,10 @@ static void __init mv2120_init(void) orion5x_uart0_init(); orion5x_xor_init(); - orion5x_setup_dev_boot_win(MV2120_NOR_BOOT_BASE, MV2120_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + MV2120_NOR_BOOT_BASE, + MV2120_NOR_BOOT_SIZE); platform_device_register(&mv2120_nor_flash); platform_device_register(&mv2120_button_device); @@ -233,6 +236,7 @@ MACHINE_START(MV2120, "HP Media Vault mv2120") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, - .fixup = tag_fixup_mem32 + .init_time = orion5x_timer_init, + .fixup = tag_fixup_mem32, + .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c index 6197c79a2ec..ba73dc7ffb9 100644 --- a/arch/arm/mach-orion5x/net2big-setup.c +++ b/arch/arm/mach-orion5x/net2big-setup.c @@ -25,6 +25,7 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <mach/orion5x.h> +#include <plat/orion-gpio.h> #include "common.h" #include "mpp.h" @@ -396,8 +397,10 @@ static void __init net2big_init(void) net2big_sata_power_init(); orion5x_sata_init(&net2big_sata_data); - orion5x_setup_dev_boot_win(NET2BIG_NOR_BOOT_BASE, - NET2BIG_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + NET2BIG_NOR_BOOT_BASE, + NET2BIG_NOR_BOOT_SIZE); platform_device_register(&net2big_nor_flash); platform_device_register(&net2big_gpio_buttons); @@ -424,7 +427,8 @@ MACHINE_START(NET2BIG, "LaCie 2Big Network") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, + .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index bc4a920e26e..87a12d6930f 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -18,6 +18,8 @@ #include <asm/irq.h> #include <asm/mach/pci.h> #include <plat/pcie.h> +#include <plat/addr-map.h> +#include <mach/orion5x.h> #include "common.h" /***************************************************************************** @@ -36,7 +38,7 @@ /***************************************************************************** * PCIe controller ****************************************************************************/ -#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) +#define PCIE_BASE (ORION5X_PCIE_VIRT_BASE) void __init orion5x_pcie_id(u32 *dev, u32 *rev) { @@ -109,7 +111,7 @@ static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, return PCIBIOS_DEVICE_NOT_FOUND; } - ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, + ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE, bus, devfn, where, size, val); return ret; @@ -145,7 +147,7 @@ static int __init pcie_setup(struct pci_sys_data *sys) /* * Generic PCIe unit setup. */ - orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); + orion_pcie_setup(PCIE_BASE); /* * Check whether to apply Orion-1/Orion-NAS PCIe config @@ -155,42 +157,32 @@ static int __init pcie_setup(struct pci_sys_data *sys) if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " "read transaction workaround\n"); - orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, - ORION5X_PCIE_WA_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET, + ORION_MBUS_PCIE_WA_ATTR, + ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE); pcie_ops.read = pcie_rd_conf_wa; } + pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE); + /* * Request resources. */ - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + res = kzalloc(sizeof(struct resource), GFP_KERNEL); if (!res) panic("pcie_setup unable to alloc resources"); /* - * IORESOURCE_IO - */ - res[0].name = "PCIe I/O Space"; - res[0].flags = IORESOURCE_IO; - res[0].start = ORION5X_PCIE_IO_BUS_BASE; - res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; - if (request_resource(&ioport_resource, &res[0])) - panic("Request PCIe IO resource failed\n"); - sys->resource[0] = &res[0]; - - /* * IORESOURCE_MEM */ - res[1].name = "PCIe Memory Space"; - res[1].flags = IORESOURCE_MEM; - res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; - res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; - if (request_resource(&iomem_resource, &res[1])) + res->name = "PCIe Memory Space"; + res->flags = IORESOURCE_MEM; + res->start = ORION5X_PCIE_MEM_PHYS_BASE; + res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1; + if (request_resource(&iomem_resource, res)) panic("Request PCIe Memory resource failed\n"); - sys->resource[1] = &res[1]; - - sys->resource[2] = NULL; - sys->io_offset = 0; + pci_add_resource_offset(&sys->resources, res, sys->mem_offset); return 1; } @@ -198,7 +190,7 @@ static int __init pcie_setup(struct pci_sys_data *sys) /***************************************************************************** * PCI controller ****************************************************************************/ -#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) +#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x)) #define PCI_MODE ORION5X_PCI_REG(0xd00) #define PCI_CMD ORION5X_PCI_REG(0xc00) #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) @@ -248,11 +240,11 @@ static int __init pcie_setup(struct pci_sys_data *sys) #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ - ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) + ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : NULL) #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ - ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) + ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : NULL) #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) @@ -412,8 +404,9 @@ static void __init orion5x_pci_master_slave_enable(void) orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); } -static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) +static void __init orion5x_setup_pci_wins(void) { + const struct mbus_dram_target_info *dram = mv_mbus_dram_info(); u32 win_enable; int bus; int i; @@ -430,7 +423,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) bus = orion5x_pci_local_bus_nr(); for (i = 0; i < dram->num_cs; i++) { - struct mbus_dram_window *cs = dram->cs + i; + const struct mbus_dram_window *cs = dram->cs + i; u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); u32 reg; u32 val; @@ -477,7 +470,7 @@ static int __init pci_setup(struct pci_sys_data *sys) /* * Point PCI unit MBUS decode windows to DRAM space. */ - orion5x_setup_pci_wins(&orion5x_mbus_dram_info); + orion5x_setup_pci_wins(); /* * Master + Slave enable @@ -489,37 +482,25 @@ static int __init pci_setup(struct pci_sys_data *sys) */ orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); + pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE); + /* * Request resources */ - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + res = kzalloc(sizeof(struct resource), GFP_KERNEL); if (!res) panic("pci_setup unable to alloc resources"); /* - * IORESOURCE_IO - */ - res[0].name = "PCI I/O Space"; - res[0].flags = IORESOURCE_IO; - res[0].start = ORION5X_PCI_IO_BUS_BASE; - res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; - if (request_resource(&ioport_resource, &res[0])) - panic("Request PCI IO resource failed\n"); - sys->resource[0] = &res[0]; - - /* * IORESOURCE_MEM */ - res[1].name = "PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; - res[1].start = ORION5X_PCI_MEM_PHYS_BASE; - res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; - if (request_resource(&iomem_resource, &res[1])) + res->name = "PCI Memory Space"; + res->flags = IORESOURCE_MEM; + res->start = ORION5X_PCI_MEM_PHYS_BASE; + res->end = res->start + ORION5X_PCI_MEM_SIZE - 1; + if (request_resource(&iomem_resource, res)) panic("Request PCI Memory resource failed\n"); - sys->resource[1] = &res[1]; - - sys->resource[2] = NULL; - sys->io_offset = 0; + pci_add_resource_offset(&sys->resources, res, sys->mem_offset); return 1; } @@ -528,7 +509,7 @@ static int __init pci_setup(struct pci_sys_data *sys) /***************************************************************************** * General PCIe + PCI ****************************************************************************/ -static void __devinit rc_pci_fixup(struct pci_dev *dev) +static void rc_pci_fixup(struct pci_dev *dev) { /* * Prevent enumeration of root complex. @@ -579,9 +560,11 @@ struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys struct pci_bus *bus; if (nr == 0) { - bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); + bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, + &sys->resources); } else if (nr == 1 && !orion5x_pci_disabled) { - bus = pci_scan_bus(sys->busnr, &pci_ops, sys); + bus = pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys, + &sys->resources); } else { bus = NULL; BUG(); diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c index ebd6767d8e8..213b3e143c5 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c @@ -18,7 +18,6 @@ #include <linux/ethtool.h> #include <net/dsa.h> #include <asm/mach-types.h> -#include <asm/leds.h> #include <asm/mach/arch.h> #include <asm/mach/pci.h> #include <mach/orion5x.h> @@ -124,8 +123,10 @@ static void __init rd88f5181l_fxo_init(void) orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ); orion5x_uart0_init(); - orion5x_setup_dev_boot_win(RD88F5181L_FXO_NOR_BOOT_BASE, - RD88F5181L_FXO_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + RD88F5181L_FXO_NOR_BOOT_BASE, + RD88F5181L_FXO_NOR_BOOT_SIZE); platform_device_register(&rd88f5181l_fxo_nor_boot_flash); } @@ -149,7 +150,6 @@ rd88f5181l_fxo_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci rd88f5181l_fxo_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = rd88f5181l_fxo_pci_map_irq, @@ -173,6 +173,7 @@ MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, + .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c index 05db2d336b0..594800e1d69 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c @@ -19,7 +19,6 @@ #include <linux/i2c.h> #include <net/dsa.h> #include <asm/mach-types.h> -#include <asm/leds.h> #include <asm/mach/arch.h> #include <asm/mach/pci.h> #include <mach/orion5x.h> @@ -131,8 +130,10 @@ static void __init rd88f5181l_ge_init(void) orion5x_i2c_init(); orion5x_uart0_init(); - orion5x_setup_dev_boot_win(RD88F5181L_GE_NOR_BOOT_BASE, - RD88F5181L_GE_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + RD88F5181L_GE_NOR_BOOT_BASE, + RD88F5181L_GE_NOR_BOOT_SIZE); platform_device_register(&rd88f5181l_ge_nor_boot_flash); i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1); @@ -161,7 +162,6 @@ rd88f5181l_ge_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci rd88f5181l_ge_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = rd88f5181l_ge_pci_map_irq, @@ -185,6 +185,7 @@ MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, + .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index e47fa0578ae..b576ef5f18a 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -19,8 +19,8 @@ #include <linux/mv643xx_eth.h> #include <linux/ata_platform.h> #include <linux/i2c.h> +#include <linux/leds.h> #include <asm/mach-types.h> -#include <asm/leds.h> #include <asm/mach/arch.h> #include <asm/mach/pci.h> #include <mach/orion5x.h> @@ -53,12 +53,6 @@ #define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7 #define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6 -/* - * GPIO Debug LED - */ - -#define RD88F5182_GPIO_DBG_LED 0 - /***************************************************************************** * 16M NOR Flash on Device bus CS1 ****************************************************************************/ @@ -83,61 +77,38 @@ static struct platform_device rd88f5182_nor_flash = { .resource = &rd88f5182_nor_flash_resource, }; -#ifdef CONFIG_LEDS - /***************************************************************************** - * Use GPIO debug led as CPU active indication + * Use GPIO LED as CPU active indication ****************************************************************************/ -static void rd88f5182_dbgled_event(led_event_t evt) -{ - int val; - - if (evt == led_idle_end) - val = 1; - else if (evt == led_idle_start) - val = 0; - else - return; - - gpio_set_value(RD88F5182_GPIO_DBG_LED, val); -} - -static int __init rd88f5182_dbgled_init(void) -{ - int pin; - - if (machine_is_rd88f5182()) { - pin = RD88F5182_GPIO_DBG_LED; +#define RD88F5182_GPIO_LED 0 - if (gpio_request(pin, "DBGLED") == 0) { - if (gpio_direction_output(pin, 0) != 0) { - printk(KERN_ERR "rd88f5182_dbgled_init failed " - "to set output pin %d\n", pin); - gpio_free(pin); - return 0; - } - } else { - printk(KERN_ERR "rd88f5182_dbgled_init failed " - "to request gpio %d\n", pin); - return 0; - } - - leds_event = rd88f5182_dbgled_event; - } - - return 0; -} +static struct gpio_led rd88f5182_gpio_led_pins[] = { + { + .name = "rd88f5182:cpu", + .default_trigger = "cpu0", + .gpio = RD88F5182_GPIO_LED, + }, +}; -__initcall(rd88f5182_dbgled_init); +static struct gpio_led_platform_data rd88f5182_gpio_led_data = { + .leds = rd88f5182_gpio_led_pins, + .num_leds = ARRAY_SIZE(rd88f5182_gpio_led_pins), +}; -#endif +static struct platform_device rd88f5182_gpio_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &rd88f5182_gpio_led_data, + }, +}; /***************************************************************************** * PCI ****************************************************************************/ -void __init rd88f5182_pci_preinit(void) +static void __init rd88f5182_pci_preinit(void) { int pin; @@ -149,7 +120,7 @@ void __init rd88f5182_pci_preinit(void) if (gpio_direction_input(pin) == 0) { irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { - printk(KERN_ERR "rd88f5182_pci_preinit faield to " + printk(KERN_ERR "rd88f5182_pci_preinit failed to " "set_irq_type pin %d\n", pin); gpio_free(pin); } @@ -162,7 +133,7 @@ void __init rd88f5182_pci_preinit(void) if (gpio_direction_input(pin) == 0) { irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { - printk(KERN_ERR "rd88f5182_pci_preinit faield to " + printk(KERN_ERR "rd88f5182_pci_preinit failed to " "set_irq_type pin %d\n", pin); gpio_free(pin); } @@ -200,7 +171,6 @@ static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci rd88f5182_pci __initdata = { .nr_controllers = 2, .preinit = rd88f5182_pci_preinit, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = rd88f5182_pci_map_irq, @@ -294,11 +264,16 @@ static void __init rd88f5182_init(void) orion5x_uart0_init(); orion5x_xor_init(); - orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, - RD88F5182_NOR_BOOT_SIZE); - - orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + RD88F5182_NOR_BOOT_BASE, + RD88F5182_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1), + ORION_MBUS_DEVBUS_ATTR(1), + RD88F5182_NOR_BASE, + RD88F5182_NOR_SIZE); platform_device_register(&rd88f5182_nor_flash); + platform_device_register(&rd88f5182_gpio_leds); i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); } @@ -310,5 +285,6 @@ MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, + .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c index 64317251ec0..78a1e6ab1b9 100644 --- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c @@ -16,12 +16,10 @@ #include <linux/mtd/physmap.h> #include <linux/mv643xx_eth.h> #include <linux/spi/spi.h> -#include <linux/spi/orion_spi.h> #include <linux/spi/flash.h> #include <linux/ethtool.h> #include <net/dsa.h> #include <asm/mach-types.h> -#include <asm/leds.h> #include <asm/mach/arch.h> #include <asm/mach/pci.h> #include <mach/orion5x.h> @@ -102,7 +100,6 @@ static void __init rd88f6183ap_ge_init(void) static struct hw_pci rd88f6183ap_ge_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = orion5x_pci_map_irq, @@ -126,6 +123,7 @@ MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, + .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index 29f1526f7b7..6208d125c1b 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c @@ -77,7 +77,7 @@ static struct platform_device tsp2_nor_flash = { #define TSP2_PCI_SLOT0_OFFS 7 #define TSP2_PCI_SLOT0_IRQ_PIN 11 -void __init tsp2_pci_preinit(void) +static void __init tsp2_pci_preinit(void) { int pin; @@ -122,7 +122,6 @@ static int __init tsp2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci tsp2_pci __initdata = { .nr_controllers = 2, .preinit = tsp2_pci_preinit, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = tsp2_pci_map_irq, @@ -330,8 +329,10 @@ static void __init tsp2_init(void) /* * Configure peripherals. */ - orion5x_setup_dev_boot_win(TSP2_NOR_BOOT_BASE, - TSP2_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + TSP2_NOR_BOOT_BASE, + TSP2_NOR_BOOT_SIZE); platform_device_register(&tsp2_nor_flash); orion5x_ehci0_init(); @@ -362,6 +363,7 @@ MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, + .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 31e51f9b4b6..9136797addb 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -106,7 +106,7 @@ static struct platform_device qnap_ts209_nor_flash = { #define QNAP_TS209_PCI_SLOT0_IRQ_PIN 6 #define QNAP_TS209_PCI_SLOT1_IRQ_PIN 7 -void __init qnap_ts209_pci_preinit(void) +static void __init qnap_ts209_pci_preinit(void) { int pin; @@ -170,7 +170,6 @@ static int __init qnap_ts209_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci qnap_ts209_pci __initdata = { .nr_controllers = 2, .preinit = qnap_ts209_pci_preinit, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = qnap_ts209_pci_map_irq, @@ -178,7 +177,7 @@ static struct hw_pci qnap_ts209_pci __initdata = { static int __init qnap_ts209_pci_init(void) { - if (machine_is_ts_x09()) + if (machine_is_ts209()) pci_common_init(&qnap_ts209_pci); return 0; @@ -287,8 +286,10 @@ static void __init qnap_ts209_init(void) /* * Configure peripherals. */ - orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, - QNAP_TS209_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + QNAP_TS209_NOR_BOOT_BASE, + QNAP_TS209_NOR_BOOT_SIZE); platform_device_register(&qnap_ts209_nor_flash); orion5x_ehci0_init(); @@ -327,6 +328,7 @@ MACHINE_START(TS209, "QNAP TS-109/TS-209") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, + .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c index 0fbcc14e09d..5c079d31201 100644 --- a/arch/arm/mach-orion5x/ts409-setup.c +++ b/arch/arm/mach-orion5x/ts409-setup.c @@ -140,7 +140,6 @@ static int __init qnap_ts409_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci qnap_ts409_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = qnap_ts409_pci_map_irq, @@ -278,8 +277,10 @@ static void __init qnap_ts409_init(void) /* * Configure peripherals. */ - orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE, - QNAP_TS409_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + QNAP_TS409_NOR_BOOT_BASE, + QNAP_TS409_NOR_BOOT_SIZE); platform_device_register(&qnap_ts409_nor_flash); orion5x_ehci0_init(); @@ -316,6 +317,7 @@ MACHINE_START(TS409, "QNAP TS-409") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, + .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/ts78xx-fpga.h b/arch/arm/mach-orion5x/ts78xx-fpga.h index 151e89e1e67..97c393d39ae 100644 --- a/arch/arm/mach-orion5x/ts78xx-fpga.h +++ b/arch/arm/mach-orion5x/ts78xx-fpga.h @@ -28,9 +28,9 @@ struct fpga_device { struct fpga_devices { /* Technologic Systems */ - struct fpga_device ts_rtc; - struct fpga_device ts_nand; - struct fpga_device ts_rng; + struct fpga_device ts_rtc; + struct fpga_device ts_nand; + struct fpga_device ts_rng; }; struct ts78xx_fpga_data { diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index 6c75cd35c4c..db16dae441e 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c @@ -8,6 +8,8 @@ * warranty of any kind, whether express or implied. */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + #include <linux/kernel.h> #include <linux/init.h> #include <linux/sysfs.h> @@ -34,7 +36,7 @@ * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE */ #define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000 -#define TS78XX_FPGA_REGS_VIRT_BASE 0xff900000 +#define TS78XX_FPGA_REGS_VIRT_BASE IOMEM(0xff900000) #define TS78XX_FPGA_REGS_SIZE SZ_1M static struct ts78xx_fpga_data ts78xx_fpga = { @@ -48,14 +50,14 @@ static struct ts78xx_fpga_data ts78xx_fpga = { ****************************************************************************/ static struct map_desc ts78xx_io_desc[] __initdata = { { - .virtual = TS78XX_FPGA_REGS_VIRT_BASE, + .virtual = (unsigned long)TS78XX_FPGA_REGS_VIRT_BASE, .pfn = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE), .length = TS78XX_FPGA_REGS_SIZE, .type = MT_DEVICE, }, }; -void __init ts78xx_map_io(void) +static void __init ts78xx_map_io(void) { orion5x_map_io(); iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc)); @@ -78,8 +80,8 @@ static struct mv_sata_platform_data ts78xx_sata_data = { /***************************************************************************** * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c ****************************************************************************/ -#define TS_RTC_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x808) -#define TS_RTC_DATA (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c) +#define TS_RTC_CTRL (TS78XX_FPGA_REGS_VIRT_BASE + 0x808) +#define TS_RTC_DATA (TS78XX_FPGA_REGS_VIRT_BASE + 0x80c) static unsigned char ts78xx_ts_rtc_readbyte(unsigned long addr) { @@ -115,7 +117,7 @@ static struct platform_device ts78xx_ts_rtc_device = { * I've used the method TS use in their rtc7800.c example for the detection * * TODO: track down a guinea pig without an RTC to see if we can work out a - * better RTC detection routine + * better RTC detection routine */ static int ts78xx_ts_rtc_load(void) { @@ -141,10 +143,14 @@ static int ts78xx_ts_rtc_load(void) } else rc = platform_device_add(&ts78xx_ts_rtc_device); + if (rc) + pr_info("RTC could not be registered: %d\n", + rc); return rc; } } + pr_info("RTC not found\n"); return -ENODEV; }; @@ -156,8 +162,8 @@ static void ts78xx_ts_rtc_unload(void) /***************************************************************************** * NAND Flash ****************************************************************************/ -#define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x800) /* VIRT */ -#define TS_NAND_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x804) /* PHYS */ +#define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE + 0x800) /* VIRT */ +#define TS_NAND_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x804) /* PHYS */ /* * hardware specific access to control-lines @@ -245,8 +251,6 @@ static void ts78xx_ts_nand_read_buf(struct mtd_info *mtd, readsb(io_base, buf, len); } -const char *ts_nand_part_probes[] = { "cmdlinepart", NULL }; - static struct mtd_partition ts78xx_ts_nand_parts[] = { { .name = "mbr", @@ -271,11 +275,10 @@ static struct mtd_partition ts78xx_ts_nand_parts[] = { static struct platform_nand_data ts78xx_ts_nand_data = { .chip = { .nr_chips = 1, - .part_probe_types = ts_nand_part_probes, .partitions = ts78xx_ts_nand_parts, .nr_partitions = ARRAY_SIZE(ts78xx_ts_nand_parts), .chip_delay = 15, - .options = NAND_USE_FLASH_BBT, + .bbt_options = NAND_BBT_USE_FLASH, }, .ctrl = { /* @@ -292,11 +295,8 @@ static struct platform_nand_data ts78xx_ts_nand_data = { }, }; -static struct resource ts78xx_ts_nand_resources = { - .start = TS_NAND_DATA, - .end = TS_NAND_DATA + 4, - .flags = IORESOURCE_MEM, -}; +static struct resource ts78xx_ts_nand_resources + = DEFINE_RES_MEM(TS_NAND_DATA, 4); static struct platform_device ts78xx_ts_nand_device = { .name = "gen_nand", @@ -319,6 +319,8 @@ static int ts78xx_ts_nand_load(void) } else rc = platform_device_add(&ts78xx_ts_nand_device); + if (rc) + pr_info("NAND could not be registered: %d\n", rc); return rc; }; @@ -332,11 +334,8 @@ static void ts78xx_ts_nand_unload(void) ****************************************************************************/ #define TS_RNG_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x044) -static struct resource ts78xx_ts_rng_resource = { - .flags = IORESOURCE_MEM, - .start = TS_RNG_DATA, - .end = TS_RNG_DATA + 4 - 1, -}; +static struct resource ts78xx_ts_rng_resource + = DEFINE_RES_MEM(TS_RNG_DATA, 4); static struct timeriomem_rng_data ts78xx_ts_rng_data = { .period = 1000000, /* one second */ @@ -363,6 +362,8 @@ static int ts78xx_ts_rng_load(void) } else rc = platform_device_add(&ts78xx_ts_rng_device); + if (rc) + pr_info("RNG could not be registered: %d\n", rc); return rc; }; @@ -402,7 +403,7 @@ static void ts78xx_fpga_supports(void) /* enable devices if magic matches */ switch ((ts78xx_fpga.id >> 8) & 0xffffff) { case TS7800_FPGA_MAGIC: - pr_warning("TS-7800 FPGA: unrecognized revision 0x%.2x\n", + pr_warning("unrecognised FPGA revision 0x%.2x\n", ts78xx_fpga.id & 0xff); ts78xx_fpga.supports.ts_rtc.present = 1; ts78xx_fpga.supports.ts_nand.present = 1; @@ -422,26 +423,20 @@ static int ts78xx_fpga_load_devices(void) if (ts78xx_fpga.supports.ts_rtc.present == 1) { tmp = ts78xx_ts_rtc_load(); - if (tmp) { - pr_info("TS-78xx: RTC not registered\n"); + if (tmp) ts78xx_fpga.supports.ts_rtc.present = 0; - } ret |= tmp; } if (ts78xx_fpga.supports.ts_nand.present == 1) { tmp = ts78xx_ts_nand_load(); - if (tmp) { - pr_info("TS-78xx: NAND not registered\n"); + if (tmp) ts78xx_fpga.supports.ts_nand.present = 0; - } ret |= tmp; } if (ts78xx_fpga.supports.ts_rng.present == 1) { tmp = ts78xx_ts_rng_load(); - if (tmp) { - pr_info("TS-78xx: RNG not registered\n"); + if (tmp) ts78xx_fpga.supports.ts_rng.present = 0; - } ret |= tmp; } @@ -466,7 +461,7 @@ static int ts78xx_fpga_load(void) { ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE); - pr_info("TS-78xx FPGA: magic=0x%.6x, rev=0x%.2x\n", + pr_info("FPGA magic=0x%.6x, rev=0x%.2x\n", (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff); @@ -494,7 +489,7 @@ static int ts78xx_fpga_unload(void) * UrJTAG SVN since r1381 can be used to reprogram the FPGA */ if (ts78xx_fpga.id != fpga_id) { - pr_err("TS-78xx FPGA: magic/rev mismatch\n" + pr_err("FPGA magic/rev mismatch\n" "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n", (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff, (fpga_id >> 8) & 0xffffff, fpga_id & 0xff); @@ -525,7 +520,7 @@ static ssize_t ts78xx_fpga_store(struct kobject *kobj, int value, ret; if (ts78xx_fpga.state < 0) { - pr_err("TS-78xx FPGA: borked, you must powercycle asap\n"); + pr_err("FPGA borked, you must powercycle ASAP\n"); return -EBUSY; } @@ -533,10 +528,8 @@ static ssize_t ts78xx_fpga_store(struct kobject *kobj, value = 1; else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0) value = 0; - else { - pr_err("ts78xx_fpga_store: Invalid value\n"); + else return -EINVAL; - } if (ts78xx_fpga.state == value) return n; @@ -614,7 +607,7 @@ static void __init ts78xx_init(void) /* FPGA init */ ts78xx_fpga_devices_zero_init(); ret = ts78xx_fpga_load(); - ret = sysfs_create_file(power_kobj, &ts78xx_fpga_attr.attr); + ret = sysfs_create_file(firmware_kobj, &ts78xx_fpga_attr.attr); if (ret) pr_err("sysfs_create_file failed: %d\n", ret); } @@ -626,5 +619,6 @@ MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC") .map_io = ts78xx_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, + .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/tsx09-common.c b/arch/arm/mach-orion5x/tsx09-common.c index c9abb8fbfa7..7189827d641 100644 --- a/arch/arm/mach-orion5x/tsx09-common.c +++ b/arch/arm/mach-orion5x/tsx09-common.c @@ -15,6 +15,7 @@ #include <linux/mv643xx_eth.h> #include <linux/timex.h> #include <linux/serial_reg.h> +#include <mach/orion5x.h> #include "tsx09-common.h" #include "common.h" diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c index b8be7d8d0cf..80a56ee245b 100644 --- a/arch/arm/mach-orion5x/wnr854t-setup.c +++ b/arch/arm/mach-orion5x/wnr854t-setup.c @@ -127,8 +127,10 @@ static void __init wnr854t_init(void) orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ); orion5x_uart0_init(); - orion5x_setup_dev_boot_win(WNR854T_NOR_BOOT_BASE, - WNR854T_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + WNR854T_NOR_BOOT_BASE, + WNR854T_NOR_BOOT_SIZE); platform_device_register(&wnr854t_nor_flash); } @@ -155,7 +157,6 @@ static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci wnr854t_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = wnr854t_pci_map_irq, @@ -177,6 +178,7 @@ MACHINE_START(WNR854T, "Netgear WNR854T") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, + .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c index faf81a03936..670e30dc0d1 100644 --- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c +++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c @@ -213,8 +213,10 @@ static void __init wrt350n_v2_init(void) orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ); orion5x_uart0_init(); - orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE, - WRT350N_V2_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + WRT350N_V2_NOR_BOOT_BASE, + WRT350N_V2_NOR_BOOT_SIZE); platform_device_register(&wrt350n_v2_nor_flash); platform_device_register(&wrt350n_v2_leds); platform_device_register(&wrt350n_v2_button_device); @@ -243,7 +245,6 @@ static int __init wrt350n_v2_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci wrt350n_v2_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = wrt350n_v2_pci_map_irq, @@ -265,6 +266,7 @@ MACHINE_START(WRT350N_V2, "Linksys WRT350N v2") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, + .restart = orion5x_restart, MACHINE_END |