diff options
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_2430_data.c')
| -rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_2430_data.c | 895 |
1 files changed, 590 insertions, 305 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 12d939e456c..6d1b6090217 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -1,7 +1,8 @@ /* * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips * - * Copyright (C) 2009-2010 Nokia Corporation + * Copyright (C) 2009-2011 Nokia Corporation + * Copyright (C) 2012 Texas Instruments, Inc. * Paul Walmsley * * This program is free software; you can redistribute it and/or modify @@ -11,429 +12,713 @@ * XXX handle crossbar/shared link difference for L3? * XXX these should be marked initdata for multi-OMAP kernels */ -#include <plat/omap_hwmod.h> -#include <mach/irqs.h> -#include <plat/cpu.h> -#include <plat/dma.h> -#include <plat/serial.h> -#include "omap_hwmod_common_data.h" +#include <linux/i2c-omap.h> +#include <linux/platform_data/asoc-ti-mcbsp.h> +#include <linux/platform_data/spi-omap2-mcspi.h> +#include <linux/omap-dma.h> +#include <linux/platform_data/mailbox-omap.h> +#include <plat/dmtimer.h> + +#include "omap_hwmod.h" +#include "mmc.h" +#include "l3_2xxx.h" +#include "soc.h" +#include "omap_hwmod_common_data.h" #include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" +#include "i2c.h" +#include "wd_timer.h" /* * OMAP2430 hardware module integration data * - * ALl of the data in this section should be autogeneratable from the + * All of the data in this section should be autogeneratable from the * TI hardware database or other technical documentation. Data that * is driver-specific or driver-kernel integration-specific belongs * elsewhere. */ -static struct omap_hwmod omap2430_mpu_hwmod; -static struct omap_hwmod omap2430_iva_hwmod; -static struct omap_hwmod omap2430_l3_main_hwmod; -static struct omap_hwmod omap2430_l4_core_hwmod; -static struct omap_hwmod omap2430_wd_timer2_hwmod; - -/* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { - .master = &omap2430_l3_main_hwmod, - .slave = &omap2430_l4_core_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; +/* + * IP blocks + */ -/* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { - .master = &omap2430_mpu_hwmod, - .slave = &omap2430_l3_main_hwmod, - .user = OCP_USER_MPU, +/* IVA2 (IVA2) */ +static struct omap_hwmod_rst_info omap2430_iva_resets[] = { + { .name = "logic", .rst_shift = 0 }, + { .name = "mmu", .rst_shift = 1 }, }; -/* Slave interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { - &omap2430_mpu__l3_main, +static struct omap_hwmod omap2430_iva_hwmod = { + .name = "iva", + .class = &iva_hwmod_class, + .clkdm_name = "dsp_clkdm", + .rst_lines = omap2430_iva_resets, + .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets), + .main_clk = "dsp_fck", }; -/* Master interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { - &omap2430_l3_main__l4_core, +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, }; -/* L3 */ -static struct omap_hwmod omap2430_l3_main_hwmod = { - .name = "l3_main", - .class = &l3_hwmod_class, - .masters = omap2430_l3_main_masters, - .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), - .slaves = omap2430_l3_main_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), - .flags = HWMOD_NO_IDLEST, +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, + .rev = OMAP_I2C_IP_VERSION_1, + .reset = &omap_i2c_reset, }; -static struct omap_hwmod omap2430_l4_wkup_hwmod; -static struct omap_hwmod omap2430_uart1_hwmod; -static struct omap_hwmod omap2430_uart2_hwmod; -static struct omap_hwmod omap2430_uart3_hwmod; - -/* L4_CORE -> L4_WKUP interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_l4_wkup_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_i2c_dev_attr i2c_dev_attr = { + .fifo_depth = 8, /* bytes */ + .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 | + OMAP_I2C_FLAG_FORCE_19200_INT_CLK, }; -/* L4 CORE -> UART1 interface */ -static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = { - { - .pa_start = OMAP2_UART1_BASE, - .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, +/* I2C1 */ +static struct omap_hwmod omap2430_i2c1_hwmod = { + .name = "i2c1", + .flags = HWMOD_16BIT_REG, + .main_clk = "i2chs1_fck", + .prcm = { + .omap2 = { + /* + * NOTE: The CM_FCLKEN* and CM_ICLKEN* for + * I2CHS IP's do not follow the usual pattern. + * prcm_reg_id alone cannot be used to program + * the iclk and fclk. Needs to be handled using + * additional flags when clk handling is moved + * to hwmod framework. + */ + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_I2CHS1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, + }, }, + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, }; -static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_uart1_hwmod, - .clk = "uart1_ick", - .addr = omap2430_uart1_addr_space, - .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART2 interface */ -static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = { - { - .pa_start = OMAP2_UART2_BASE, - .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, +/* I2C2 */ +static struct omap_hwmod omap2430_i2c2_hwmod = { + .name = "i2c2", + .flags = HWMOD_16BIT_REG, + .main_clk = "i2chs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_I2CHS2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, + }, }, + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, }; -static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_uart2_hwmod, - .clk = "uart2_ick", - .addr = omap2430_uart2_addr_space, - .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space), - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* gpio5 */ +static struct omap_hwmod omap2430_gpio5_hwmod = { + .name = "gpio5", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "gpio5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 2, + .module_bit = OMAP2430_EN_GPIO5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, + }, + }, + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &omap2xxx_gpio_dev_attr, }; -/* L4 PER -> UART3 interface */ -static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = { - { - .pa_start = OMAP2_UART3_BASE, - .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, +/* dma attributes */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, + .lch_count = 32, }; -static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_uart3_hwmod, - .clk = "uart3_ick", - .addr = omap2430_uart3_addr_space, - .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space), - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod omap2430_dma_system_hwmod = { + .name = "dma", + .class = &omap2xxx_dma_hwmod_class, + .mpu_irqs = omap2_dma_system_irqs, + .main_clk = "core_l3_ck", + .dev_attr = &dma_dev_attr, + .flags = HWMOD_NO_IDLEST, }; -/* Slave interfaces on the L4_CORE interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { - &omap2430_l3_main__l4_core, +/* mailbox */ +static struct omap_mbox_dev_info omap2430_mailbox_info[] = { + { .name = "dsp", .tx_id = 0, .rx_id = 1 }, }; -/* Master interfaces on the L4_CORE interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { - &omap2430_l4_core__l4_wkup, +static struct omap_mbox_pdata omap2430_mailbox_attrs = { + .num_users = 4, + .num_fifos = 6, + .info_cnt = ARRAY_SIZE(omap2430_mailbox_info), + .info = omap2430_mailbox_info, }; -/* L4 CORE */ -static struct omap_hwmod omap2430_l4_core_hwmod = { - .name = "l4_core", - .class = &l4_hwmod_class, - .masters = omap2430_l4_core_masters, - .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), - .slaves = omap2430_l4_core_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), - .flags = HWMOD_NO_IDLEST, +static struct omap_hwmod omap2430_mailbox_hwmod = { + .name = "mailbox", + .class = &omap2xxx_mailbox_hwmod_class, + .main_clk = "mailboxes_ick", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, + }, + }, + .dev_attr = &omap2430_mailbox_attrs, }; -/* Slave interfaces on the L4_WKUP interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { - &omap2430_l4_core__l4_wkup, - &omap2_l4_core__uart1, - &omap2_l4_core__uart2, - &omap2_l4_core__uart3, +/* mcspi3 */ +static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { + .num_chipselect = 2, }; -/* Master interfaces on the L4_WKUP interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { +static struct omap_hwmod omap2430_mcspi3_hwmod = { + .name = "mcspi3", + .main_clk = "mcspi3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP2430_EN_MCSPI3_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, + }, + }, + .class = &omap2xxx_mcspi_class, + .dev_attr = &omap_mcspi3_dev_attr, }; -/* L4 WKUP */ -static struct omap_hwmod omap2430_l4_wkup_hwmod = { - .name = "l4_wkup", - .class = &l4_hwmod_class, - .masters = omap2430_l4_wkup_masters, - .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), - .slaves = omap2430_l4_wkup_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), - .flags = HWMOD_NO_IDLEST, +/* usbhsotg */ +static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { + .rev_offs = 0x0400, + .sysc_offs = 0x0404, + .syss_offs = 0x0408, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, }; -/* Master interfaces on the MPU device */ -static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { - &omap2430_mpu__l3_main, +static struct omap_hwmod_class usbotg_class = { + .name = "usbotg", + .sysc = &omap2430_usbhsotg_sysc, }; -/* MPU */ -static struct omap_hwmod omap2430_mpu_hwmod = { - .name = "mpu", - .class = &mpu_hwmod_class, - .main_clk = "mpu_ck", - .masters = omap2430_mpu_masters, - .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +/* usb_otg_hs */ +static struct omap_hwmod omap2430_usbhsotg_hwmod = { + .name = "usb_otg_hs", + .main_clk = "usbhs_ick", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_USBHS_MASK, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, + }, + }, + .class = &usbotg_class, + /* + * Erratum ID: i479 idle_req / idle_ack mechanism potentially + * broken when autoidle is enabled + * workaround is to disable the autoidle bit at module level. + */ + .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE + | HWMOD_SWSUP_MSTANDBY, }; /* - * IVA2_1 interface data + * 'mcbsp' class + * multi channel buffered serial port controller */ -/* IVA2 <- L3 interface */ -static struct omap_hwmod_ocp_if omap2430_l3__iva = { - .master = &omap2430_l3_main_hwmod, - .slave = &omap2430_iva_hwmod, - .clk = "dsp_fck", - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { + .rev_offs = 0x007C, + .sysc_offs = 0x008C, + .sysc_flags = (SYSC_HAS_SOFTRESET), + .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = { - &omap2430_l3__iva, +static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { + .name = "mcbsp", + .sysc = &omap2430_mcbsp_sysc, + .rev = MCBSP_CONFIG_TYPE2, }; -/* - * IVA2 (IVA2) - */ - -static struct omap_hwmod omap2430_iva_hwmod = { - .name = "iva", - .class = &iva_hwmod_class, - .masters = omap2430_iva_masters, - .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { + { .role = "pad_fck", .clk = "mcbsp_clks" }, + { .role = "prcm_fck", .clk = "func_96m_ck" }, }; -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { - { - .pa_start = 0x49016000, - .pa_end = 0x4901607f, - .flags = ADDR_TYPE_RT +/* mcbsp1 */ +static struct omap_hwmod omap2430_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap2430_mcbsp_hwmod_class, + .main_clk = "mcbsp1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, + }, }, + .opt_clks = mcbsp_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), }; -static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_wd_timer2_hwmod, - .clk = "mpu_wdt_ick", - .addr = omap2430_wd_timer2_addrs, - .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* - * 'wd_timer' class - * 32-bit watchdog upward counter that generates a pulse on the reset pin on - * overflow condition - */ - -static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .sysc_fields = &omap_hwmod_sysc_type1, +/* mcbsp2 */ +static struct omap_hwmod omap2430_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap2430_mcbsp_hwmod_class, + .main_clk = "mcbsp2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, + }, + }, + .opt_clks = mcbsp_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), }; -static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { - .name = "wd_timer", - .sysc = &omap2430_wd_timer_sysc, +/* mcbsp3 */ +static struct omap_hwmod omap2430_mcbsp3_hwmod = { + .name = "mcbsp3", + .class = &omap2430_mcbsp_hwmod_class, + .main_clk = "mcbsp3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_MCBSP3_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, + }, + }, + .opt_clks = mcbsp_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), }; -/* wd_timer2 */ -static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { - &omap2430_l4_wkup__wd_timer2, +/* mcbsp4 */ +static struct omap_hwmod omap2430_mcbsp4_hwmod = { + .name = "mcbsp4", + .class = &omap2430_mcbsp_hwmod_class, + .main_clk = "mcbsp4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_MCBSP4_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, + }, + }, + .opt_clks = mcbsp_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), }; -static struct omap_hwmod omap2430_wd_timer2_hwmod = { - .name = "wd_timer2", - .class = &omap2430_wd_timer_hwmod_class, - .main_clk = "mpu_wdt_fck", +/* mcbsp5 */ +static struct omap_hwmod omap2430_mcbsp5_hwmod = { + .name = "mcbsp5", + .class = &omap2430_mcbsp_hwmod_class, + .main_clk = "mcbsp5_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, + .module_bit = OMAP2430_EN_MCBSP5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, }, }, - .slaves = omap2430_wd_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .opt_clks = mcbsp_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), }; -/* UART */ - -static struct omap_hwmod_class_sysconfig uart_sysc = { - .rev_offs = 0x50, - .sysc_offs = 0x54, - .syss_offs = 0x58, - .sysc_flags = (SYSC_HAS_SIDLEMODE | +/* MMC/SD/SDIO common */ +static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { + .rev_offs = 0x1fc, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_class uart_class = { - .name = "uart", - .sysc = &uart_sysc, +static struct omap_hwmod_class omap2430_mmc_class = { + .name = "mmc", + .sysc = &omap2430_mmc_sysc, }; -/* UART1 */ +/* MMC/SD/SDIO1 */ +static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { + { .role = "dbck", .clk = "mmchsdb1_fck" }, +}; -static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { - { .irq = INT_24XX_UART1_IRQ, }, +static struct omap_mmc_dev_attr mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, }; -static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, - { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, +static struct omap_hwmod omap2430_mmc1_hwmod = { + .name = "mmc1", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .opt_clks = omap2430_mmc1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), + .main_clk = "mmchs1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP2430_EN_MMCHS1_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, + }, + }, + .dev_attr = &mmc1_dev_attr, + .class = &omap2430_mmc_class, }; -static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { - &omap2_l4_core__uart1, +/* MMC/SD/SDIO2 */ +static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { + { .role = "dbck", .clk = "mmchsdb2_fck" }, }; -static struct omap_hwmod omap2430_uart1_hwmod = { - .name = "uart1", - .mpu_irqs = uart1_mpu_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), - .sdma_reqs = uart1_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), - .main_clk = "uart1_fck", +static struct omap_hwmod omap2430_mmc2_hwmod = { + .name = "mmc2", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .opt_clks = omap2430_mmc2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), + .main_clk = "mmchs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP2430_EN_MMCHS2_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, + }, + }, + .class = &omap2430_mmc_class, +}; + +/* HDQ1W/1-wire */ +static struct omap_hwmod omap2430_hdq1w_hwmod = { + .name = "hdq1w", + .main_clk = "hdq_fck", .prcm = { .omap2 = { .module_offs = CORE_MOD, .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART1_SHIFT, + .module_bit = OMAP24XX_EN_HDQ_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, + .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT, }, }, - .slaves = omap2430_uart1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), - .class = &uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .class = &omap2_hdq1w_class, }; -/* UART2 */ +/* + * interfaces + */ -static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { - { .irq = INT_24XX_UART2_IRQ, }, +/* L3 -> L4_CORE interface */ +/* l3_core -> usbhsotg interface */ +static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { + .master = &omap2430_usbhsotg_hwmod, + .slave = &omap2xxx_l3_main_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU, +}; + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_i2c1_hwmod, + .clk = "i2c1_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, - { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_i2c2_hwmod, + .clk = "i2c2_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { - &omap2_l4_core__uart2, +/* l4_core ->usbhsotg interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_usbhsotg_hwmod, + .clk = "usb_l4_ick", + .user = OCP_USER_MPU, }; -static struct omap_hwmod omap2430_uart2_hwmod = { - .name = "uart2", - .mpu_irqs = uart2_mpu_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), - .sdma_reqs = uart2_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), - .main_clk = "uart2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, - }, - }, - .slaves = omap2430_uart2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), - .class = &uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +/* L4 CORE -> MMC1 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mmc1_hwmod, + .clk = "mmchs1_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* UART3 */ +/* L4 CORE -> MMC2 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mmc2_hwmod, + .clk = "mmchs2_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; -static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { - { .irq = INT_24XX_UART3_IRQ, }, +/* l4 core -> mcspi3 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcspi3_hwmod, + .clk = "mcspi3_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, - { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, +/* IVA2 <- L3 interface */ +static struct omap_hwmod_ocp_if omap2430_l3__iva = { + .master = &omap2xxx_l3_main_hwmod, + .slave = &omap2430_iva_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { - &omap2_l4_core__uart3, +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_timer1_hwmod, + .clk = "gpt1_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod omap2430_uart3_hwmod = { - .name = "uart3", - .mpu_irqs = uart3_mpu_irqs, - .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), - .sdma_reqs = uart3_sdma_reqs, - .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), - .main_clk = "uart3_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 2, - .module_bit = OMAP24XX_EN_UART3_SHIFT, - .idlest_reg_id = 2, - .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, - }, - }, - .slaves = omap2430_uart3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), - .class = &uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -}; - -static __initdata struct omap_hwmod *omap2430_hwmods[] = { - &omap2430_l3_main_hwmod, - &omap2430_l4_core_hwmod, - &omap2430_l4_wkup_hwmod, - &omap2430_mpu_hwmod, - &omap2430_iva_hwmod, - &omap2430_wd_timer2_hwmod, - &omap2430_uart1_hwmod, - &omap2430_uart2_hwmod, - &omap2430_uart3_hwmod, +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_wd_timer2_hwmod, + .clk = "mpu_wdt_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio1_hwmod, + .clk = "gpios_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio2 */ +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio2_hwmod, + .clk = "gpios_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio3 */ +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio3_hwmod, + .clk = "gpios_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio4 */ +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio4_hwmod, + .clk = "gpios_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> gpio5 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_gpio5_hwmod, + .clk = "gpio5_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { + .master = &omap2430_dma_system_hwmod, + .slave = &omap2xxx_l3_main_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dma_system */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_dma_system_hwmod, + .clk = "sdma_ick", + .addr = omap2_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mailbox */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mailbox_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcbsp2_hwmod, + .clk = "mcbsp2_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcbsp3_hwmod, + .clk = "mcbsp3_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcbsp4_hwmod, + .clk = "mcbsp4_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mcbsp5 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcbsp5_hwmod, + .clk = "mcbsp5_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> hdq1w */ +static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_hdq1w_hwmod, + .clk = "hdq_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, +}; + +/* l4_wkup -> 32ksync_counter */ +static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_counter_32k_hwmod, + .clk = "sync_32k_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if omap2430_l3__gpmc = { + .master = &omap2xxx_l3_main_hwmod, + .slave = &omap2xxx_gpmc_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { + &omap2xxx_l3_main__l4_core, + &omap2xxx_mpu__l3_main, + &omap2xxx_dss__l3, + &omap2430_usbhsotg__l3, + &omap2430_l4_core__i2c1, + &omap2430_l4_core__i2c2, + &omap2xxx_l4_core__l4_wkup, + &omap2_l4_core__uart1, + &omap2_l4_core__uart2, + &omap2_l4_core__uart3, + &omap2430_l4_core__usbhsotg, + &omap2430_l4_core__mmc1, + &omap2430_l4_core__mmc2, + &omap2xxx_l4_core__mcspi1, + &omap2xxx_l4_core__mcspi2, + &omap2430_l4_core__mcspi3, + &omap2430_l3__iva, + &omap2430_l4_wkup__timer1, + &omap2xxx_l4_core__timer2, + &omap2xxx_l4_core__timer3, + &omap2xxx_l4_core__timer4, + &omap2xxx_l4_core__timer5, + &omap2xxx_l4_core__timer6, + &omap2xxx_l4_core__timer7, + &omap2xxx_l4_core__timer8, + &omap2xxx_l4_core__timer9, + &omap2xxx_l4_core__timer10, + &omap2xxx_l4_core__timer11, + &omap2xxx_l4_core__timer12, + &omap2430_l4_wkup__wd_timer2, + &omap2xxx_l4_core__dss, + &omap2xxx_l4_core__dss_dispc, + &omap2xxx_l4_core__dss_rfbi, + &omap2xxx_l4_core__dss_venc, + &omap2430_l4_wkup__gpio1, + &omap2430_l4_wkup__gpio2, + &omap2430_l4_wkup__gpio3, + &omap2430_l4_wkup__gpio4, + &omap2430_l4_core__gpio5, + &omap2430_dma_system__l3, + &omap2430_l4_core__dma_system, + &omap2430_l4_core__mailbox, + &omap2430_l4_core__mcbsp1, + &omap2430_l4_core__mcbsp2, + &omap2430_l4_core__mcbsp3, + &omap2430_l4_core__mcbsp4, + &omap2430_l4_core__mcbsp5, + &omap2430_l4_core__hdq1w, + &omap2xxx_l4_core__rng, + &omap2xxx_l4_core__sham, + &omap2xxx_l4_core__aes, + &omap2430_l4_wkup__counter_32k, + &omap2430_l3__gpmc, NULL, }; int __init omap2430_hwmod_init(void) { - return omap_hwmod_init(omap2430_hwmods); + omap_hwmod_init(); + return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); } - - |