diff options
Diffstat (limited to 'arch/arm/mach-omap2/io.c')
| -rw-r--r-- | arch/arm/mach-omap2/io.c | 604 |
1 files changed, 444 insertions, 160 deletions
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index c2032041d26..8f559450c87 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -16,41 +16,56 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ - #include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> #include <linux/clk.h> -#include <linux/omapfb.h> #include <asm/tlb.h> - #include <asm/mach/map.h> -#include <plat/sram.h> -#include <plat/sdrc.h> -#include <plat/gpmc.h> -#include <plat/serial.h> +#include <linux/omap-dma.h> +#include "omap_hwmod.h" +#include "soc.h" +#include "iomap.h" +#include "voltage.h" +#include "powerdomain.h" +#include "clockdomain.h" +#include "common.h" +#include "clock.h" #include "clock2xxx.h" #include "clock3xxx.h" #include "clock44xx.h" -#include "io.h" - -#include <plat/omap-pm.h> -#include "powerdomain.h" +#include "omap-pm.h" +#include "sdrc.h" +#include "control.h" +#include "serial.h" +#include "sram.h" +#include "cm2xxx.h" +#include "cm3xxx.h" +#include "prm.h" +#include "cm.h" +#include "prcm_mpu44xx.h" +#include "prminst44xx.h" +#include "cminst44xx.h" +#include "prm2xxx.h" +#include "prm3xxx.h" +#include "prm44xx.h" -#include "clockdomain.h" -#include <plat/omap_hwmod.h> -#include <plat/multi.h> +/* + * omap_clk_soc_init: points to a function that does the SoC-specific + * clock initializations + */ +static int (*omap_clk_soc_init)(void); /* * The machine specific code may provide the extra mapping besides the * default mapping provided here. */ -#ifdef CONFIG_ARCH_OMAP2 +#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) static struct map_desc omap24xx_io_desc[] __initdata = { { .virtual = L3_24XX_VIRT, @@ -66,7 +81,7 @@ static struct map_desc omap24xx_io_desc[] __initdata = { }, }; -#ifdef CONFIG_ARCH_OMAP2420 +#ifdef CONFIG_SOC_OMAP2420 static struct map_desc omap242x_io_desc[] __initdata = { { .virtual = DSP_MEM_2420_VIRT, @@ -90,7 +105,7 @@ static struct map_desc omap242x_io_desc[] __initdata = { #endif -#ifdef CONFIG_ARCH_OMAP2430 +#ifdef CONFIG_SOC_OMAP2430 static struct map_desc omap243x_io_desc[] __initdata = { { .virtual = L4_WK_243X_VIRT, @@ -164,17 +179,37 @@ static struct map_desc omap34xx_io_desc[] __initdata = { .length = L4_EMU_34XX_SIZE, .type = MT_DEVICE }, -#if defined(CONFIG_DEBUG_LL) && \ - (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3)) +}; +#endif + +#ifdef CONFIG_SOC_TI81XX +static struct map_desc omapti81xx_io_desc[] __initdata = { { - .virtual = ZOOM_UART_VIRT, - .pfn = __phys_to_pfn(ZOOM_UART_BASE), - .length = SZ_1M, + .virtual = L4_34XX_VIRT, + .pfn = __phys_to_pfn(L4_34XX_PHYS), + .length = L4_34XX_SIZE, .type = MT_DEVICE - }, + } +}; #endif + +#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) +static struct map_desc omapam33xx_io_desc[] __initdata = { + { + .virtual = L4_34XX_VIRT, + .pfn = __phys_to_pfn(L4_34XX_PHYS), + .length = L4_34XX_SIZE, + .type = MT_DEVICE + }, + { + .virtual = L4_WK_AM33XX_VIRT, + .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), + .length = L4_WK_AM33XX_SIZE, + .type = MT_DEVICE + } }; #endif + #ifdef CONFIG_ARCH_OMAP4 static struct map_desc omap44xx_io_desc[] __initdata = { { @@ -190,91 +225,112 @@ static struct map_desc omap44xx_io_desc[] __initdata = { .type = MT_DEVICE, }, { - .virtual = OMAP44XX_GPMC_VIRT, - .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS), - .length = OMAP44XX_GPMC_SIZE, + .virtual = L4_PER_44XX_VIRT, + .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), + .length = L4_PER_44XX_SIZE, .type = MT_DEVICE, }, +#ifdef CONFIG_OMAP4_ERRATA_I688 { - .virtual = OMAP44XX_EMIF1_VIRT, - .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS), - .length = OMAP44XX_EMIF1_SIZE, - .type = MT_DEVICE, + .virtual = OMAP4_SRAM_VA, + .pfn = __phys_to_pfn(OMAP4_SRAM_PA), + .length = PAGE_SIZE, + .type = MT_MEMORY_RW_SO, }, +#endif + +}; +#endif + +#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) +static struct map_desc omap54xx_io_desc[] __initdata = { { - .virtual = OMAP44XX_EMIF2_VIRT, - .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS), - .length = OMAP44XX_EMIF2_SIZE, + .virtual = L3_54XX_VIRT, + .pfn = __phys_to_pfn(L3_54XX_PHYS), + .length = L3_54XX_SIZE, .type = MT_DEVICE, }, { - .virtual = OMAP44XX_DMM_VIRT, - .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS), - .length = OMAP44XX_DMM_SIZE, + .virtual = L4_54XX_VIRT, + .pfn = __phys_to_pfn(L4_54XX_PHYS), + .length = L4_54XX_SIZE, .type = MT_DEVICE, }, { - .virtual = L4_PER_44XX_VIRT, - .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), - .length = L4_PER_44XX_SIZE, + .virtual = L4_WK_54XX_VIRT, + .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), + .length = L4_WK_54XX_SIZE, .type = MT_DEVICE, }, { - .virtual = L4_EMU_44XX_VIRT, - .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS), - .length = L4_EMU_44XX_SIZE, + .virtual = L4_PER_54XX_VIRT, + .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), + .length = L4_PER_54XX_SIZE, .type = MT_DEVICE, }, +#ifdef CONFIG_OMAP4_ERRATA_I688 + { + .virtual = OMAP4_SRAM_VA, + .pfn = __phys_to_pfn(OMAP4_SRAM_PA), + .length = PAGE_SIZE, + .type = MT_MEMORY_RW_SO, + }, +#endif }; #endif -static void __init _omap2_map_common_io(void) -{ - /* Normally devicemaps_init() would flush caches and tlb after - * mdesc->map_io(), but we must also do it here because of the CPU - * revision check below. - */ - local_flush_tlb_all(); - flush_cache_all(); - - omap2_check_revision(); - omap_sram_init(); -} - -#ifdef CONFIG_ARCH_OMAP2420 -void __init omap242x_map_common_io(void) +#ifdef CONFIG_SOC_OMAP2420 +void __init omap242x_map_io(void) { iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); - _omap2_map_common_io(); } #endif -#ifdef CONFIG_ARCH_OMAP2430 -void __init omap243x_map_common_io(void) +#ifdef CONFIG_SOC_OMAP2430 +void __init omap243x_map_io(void) { iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); - _omap2_map_common_io(); } #endif #ifdef CONFIG_ARCH_OMAP3 -void __init omap34xx_map_common_io(void) +void __init omap3_map_io(void) { iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); - _omap2_map_common_io(); +} +#endif + +#ifdef CONFIG_SOC_TI81XX +void __init ti81xx_map_io(void) +{ + iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); +} +#endif + +#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) +void __init am33xx_map_io(void) +{ + iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); } #endif #ifdef CONFIG_ARCH_OMAP4 -void __init omap44xx_map_common_io(void) +void __init omap4_map_io(void) { iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); - _omap2_map_common_io(); + omap_barriers_init(); } #endif +#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) +void __init omap5_map_io(void) +{ + iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); + omap_barriers_init(); +} +#endif /* * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters * @@ -314,47 +370,10 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); } -void __iomem *omap_irq_base; - -/* - * Initialize asm_irq_base for entry-macro.S - */ -static inline void omap_irq_base_init(void) -{ - if (cpu_is_omap24xx()) - omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE); - else if (cpu_is_omap34xx()) - omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE); - else if (cpu_is_omap44xx()) - omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE); - else - pr_err("Could not initialize omap_irq_base\n"); -} - -void __init omap2_init_common_infrastructure(void) +static void __init omap_hwmod_init_postsetup(void) { u8 postsetup_state; - if (cpu_is_omap242x()) { - omap2xxx_powerdomains_init(); - omap2_clockdomains_init(); - omap2420_hwmod_init(); - } else if (cpu_is_omap243x()) { - omap2xxx_powerdomains_init(); - omap2_clockdomains_init(); - omap2430_hwmod_init(); - } else if (cpu_is_omap34xx()) { - omap3xxx_powerdomains_init(); - omap2_clockdomains_init(); - omap3xxx_hwmod_init(); - } else if (cpu_is_omap44xx()) { - omap44xx_powerdomains_init(); - omap44xx_clockdomains_init(); - omap44xx_hwmod_init(); - } else { - pr_err("Could not init hwmod data - unknown SoC\n"); - } - /* Set the default postsetup state for all hwmods */ #ifdef CONFIG_PM_RUNTIME postsetup_state = _HWMOD_STATE_IDLE; @@ -363,90 +382,355 @@ void __init omap2_init_common_infrastructure(void) #endif omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); - /* - * Set the default postsetup state for unusual modules (like - * MPU WDT). - * - * The postsetup_state is not actually used until - * omap_hwmod_late_init(), so boards that desire full watchdog - * coverage of kernel initialization can reprogram the - * postsetup_state between the calls to - * omap2_init_common_infra() and omap2_init_common_devices(). - * - * XXX ideally we could detect whether the MPU WDT was currently - * enabled here and make this conditional - */ - postsetup_state = _HWMOD_STATE_DISABLED; - omap_hwmod_for_each_by_class("wd_timer", - _set_hwmod_postsetup_state, - &postsetup_state); - omap_pm_if_early_init(); +} - if (cpu_is_omap2420()) - omap2420_clk_init(); - else if (cpu_is_omap2430()) - omap2430_clk_init(); - else if (cpu_is_omap34xx()) - omap3xxx_clk_init(); - else if (cpu_is_omap44xx()) - omap4xxx_clk_init(); - else - pr_err("Could not init clock framework - unknown SoC\n"); +static void __init __maybe_unused omap_common_late_init(void) +{ + omap_mux_late_init(); + omap2_common_pm_late_init(); + omap_soc_device_init(); } -void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, - struct omap_sdrc_params *sdrc_cs1) +#ifdef CONFIG_SOC_OMAP2420 +void __init omap2420_init_early(void) { - omap_serial_early_init(); + omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); + omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), + OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE), + NULL); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL); + omap2xxx_check_revision(); + omap2xxx_prm_init(); + omap2xxx_cm_init(); + omap2xxx_voltagedomains_init(); + omap242x_powerdomains_init(); + omap242x_clockdomains_init(); + omap2420_hwmod_init(); + omap_hwmod_init_postsetup(); + omap_clk_soc_init = omap2420_clk_init; +} - omap_hwmod_late_init(); +void __init omap2420_init_late(void) +{ + omap_common_late_init(); + omap2_pm_init(); + omap2_clk_enable_autoidle_all(); +} +#endif - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { - omap2_sdrc_init(sdrc_cs0, sdrc_cs1); - _omap2_init_reprogram_sdrc(); - } - gpmc_init(); +#ifdef CONFIG_SOC_OMAP2430 +void __init omap2430_init_early(void) +{ + omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); + omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), + OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), + NULL); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL); + omap2xxx_check_revision(); + omap2xxx_prm_init(); + omap2xxx_cm_init(); + omap2xxx_voltagedomains_init(); + omap243x_powerdomains_init(); + omap243x_clockdomains_init(); + omap2430_hwmod_init(); + omap_hwmod_init_postsetup(); + omap_clk_soc_init = omap2430_clk_init; +} - omap_irq_base_init(); +void __init omap2430_init_late(void) +{ + omap_common_late_init(); + omap2_pm_init(); + omap2_clk_enable_autoidle_all(); } +#endif /* - * NOTE: Please use ioremap + __raw_read/write where possible instead of these + * Currently only board-omap3beagle.c should call this because of the + * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. */ +#ifdef CONFIG_ARCH_OMAP3 +void __init omap3_init_early(void) +{ + omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); + omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), + OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), + NULL); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); + omap3xxx_check_revision(); + omap3xxx_check_features(); + omap3xxx_prm_init(); + omap3xxx_cm_init(); + omap3xxx_voltagedomains_init(); + omap3xxx_powerdomains_init(); + omap3xxx_clockdomains_init(); + omap3xxx_hwmod_init(); + omap_hwmod_init_postsetup(); + omap_clk_soc_init = omap3xxx_clk_init; +} + +void __init omap3430_init_early(void) +{ + omap3_init_early(); + if (of_have_populated_dt()) + omap_clk_soc_init = omap3430_dt_clk_init; +} + +void __init omap35xx_init_early(void) +{ + omap3_init_early(); + if (of_have_populated_dt()) + omap_clk_soc_init = omap3430_dt_clk_init; +} + +void __init omap3630_init_early(void) +{ + omap3_init_early(); + if (of_have_populated_dt()) + omap_clk_soc_init = omap3630_dt_clk_init; +} + +void __init am35xx_init_early(void) +{ + omap3_init_early(); + if (of_have_populated_dt()) + omap_clk_soc_init = am35xx_dt_clk_init; +} + +void __init ti81xx_init_early(void) +{ + omap2_set_globals_tap(OMAP343X_CLASS, + OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), + NULL); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); + omap3xxx_check_revision(); + ti81xx_check_features(); + omap3xxx_voltagedomains_init(); + omap3xxx_powerdomains_init(); + omap3xxx_clockdomains_init(); + omap3xxx_hwmod_init(); + omap_hwmod_init_postsetup(); + if (of_have_populated_dt()) + omap_clk_soc_init = ti81xx_dt_clk_init; + else + omap_clk_soc_init = omap3xxx_clk_init; +} + +void __init omap3_init_late(void) +{ + omap_common_late_init(); + omap3_pm_init(); + omap2_clk_enable_autoidle_all(); +} + +void __init omap3430_init_late(void) +{ + omap_common_late_init(); + omap3_pm_init(); + omap2_clk_enable_autoidle_all(); +} + +void __init omap35xx_init_late(void) +{ + omap_common_late_init(); + omap3_pm_init(); + omap2_clk_enable_autoidle_all(); +} + +void __init omap3630_init_late(void) +{ + omap_common_late_init(); + omap3_pm_init(); + omap2_clk_enable_autoidle_all(); +} + +void __init am35xx_init_late(void) +{ + omap_common_late_init(); + omap3_pm_init(); + omap2_clk_enable_autoidle_all(); +} -u8 omap_readb(u32 pa) +void __init ti81xx_init_late(void) { - return __raw_readb(OMAP2_L4_IO_ADDRESS(pa)); + omap_common_late_init(); + omap3_pm_init(); + omap2_clk_enable_autoidle_all(); } -EXPORT_SYMBOL(omap_readb); +#endif + +#ifdef CONFIG_SOC_AM33XX +void __init am33xx_init_early(void) +{ + omap2_set_globals_tap(AM335X_CLASS, + AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); + omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), + NULL); + omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE)); + omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL); + omap3xxx_check_revision(); + am33xx_check_features(); + am33xx_powerdomains_init(); + am33xx_clockdomains_init(); + am33xx_hwmod_init(); + omap_hwmod_init_postsetup(); + omap_clk_soc_init = am33xx_dt_clk_init; +} + +void __init am33xx_init_late(void) +{ + omap_common_late_init(); +} +#endif + +#ifdef CONFIG_SOC_AM43XX +void __init am43xx_init_early(void) +{ + omap2_set_globals_tap(AM335X_CLASS, + AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); + omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), + NULL); + omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE)); + omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL); + omap_prm_base_init(); + omap_cm_base_init(); + omap3xxx_check_revision(); + am33xx_check_features(); + am43xx_powerdomains_init(); + am43xx_clockdomains_init(); + am43xx_hwmod_init(); + omap_hwmod_init_postsetup(); + omap_l2_cache_init(); + omap_clk_soc_init = am43xx_dt_clk_init; +} + +void __init am43xx_init_late(void) +{ + omap_common_late_init(); +} +#endif -u16 omap_readw(u32 pa) +#ifdef CONFIG_ARCH_OMAP4 +void __init omap4430_init_early(void) { - return __raw_readw(OMAP2_L4_IO_ADDRESS(pa)); + omap2_set_globals_tap(OMAP443X_CLASS, + OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), + OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE)); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), + OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE)); + omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); + omap_prm_base_init(); + omap_cm_base_init(); + omap4xxx_check_revision(); + omap4xxx_check_features(); + omap4_pm_init_early(); + omap44xx_prm_init(); + omap44xx_voltagedomains_init(); + omap44xx_powerdomains_init(); + omap44xx_clockdomains_init(); + omap44xx_hwmod_init(); + omap_hwmod_init_postsetup(); + omap_l2_cache_init(); + omap_clk_soc_init = omap4xxx_dt_clk_init; } -EXPORT_SYMBOL(omap_readw); -u32 omap_readl(u32 pa) +void __init omap4430_init_late(void) { - return __raw_readl(OMAP2_L4_IO_ADDRESS(pa)); + omap_common_late_init(); + omap4_pm_init(); + omap2_clk_enable_autoidle_all(); } -EXPORT_SYMBOL(omap_readl); +#endif -void omap_writeb(u8 v, u32 pa) +#ifdef CONFIG_SOC_OMAP5 +void __init omap5_init_early(void) { - __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa)); + omap2_set_globals_tap(OMAP54XX_CLASS, + OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), + OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE)); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE), + OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); + omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); + omap_prm_base_init(); + omap_cm_base_init(); + omap44xx_prm_init(); + omap5xxx_check_revision(); + omap54xx_voltagedomains_init(); + omap54xx_powerdomains_init(); + omap54xx_clockdomains_init(); + omap54xx_hwmod_init(); + omap_hwmod_init_postsetup(); + omap_clk_soc_init = omap5xxx_dt_clk_init; } -EXPORT_SYMBOL(omap_writeb); -void omap_writew(u16 v, u32 pa) +void __init omap5_init_late(void) { - __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa)); + omap_common_late_init(); } -EXPORT_SYMBOL(omap_writew); +#endif -void omap_writel(u32 v, u32 pa) +#ifdef CONFIG_SOC_DRA7XX +void __init dra7xx_init_early(void) { - __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa)); + omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), + OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE)); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE), + OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); + omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); + omap_prm_base_init(); + omap_cm_base_init(); + omap44xx_prm_init(); + dra7xxx_check_revision(); + dra7xx_powerdomains_init(); + dra7xx_clockdomains_init(); + dra7xx_hwmod_init(); + omap_hwmod_init_postsetup(); + omap_clk_soc_init = dra7xx_dt_clk_init; +} + +void __init dra7xx_init_late(void) +{ + omap_common_late_init(); +} +#endif + + +void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, + struct omap_sdrc_params *sdrc_cs1) +{ + omap_sram_init(); + + if (cpu_is_omap24xx() || omap3_has_sdrc()) { + omap2_sdrc_init(sdrc_cs0, sdrc_cs1); + _omap2_init_reprogram_sdrc(); + } +} + +int __init omap_clk_init(void) +{ + int ret = 0; + + if (!omap_clk_soc_init) + return 0; + + ret = of_prcm_init(); + if (!ret) + ret = omap_clk_soc_init(); + + return ret; } -EXPORT_SYMBOL(omap_writel); |