diff options
Diffstat (limited to 'arch/arm/mach-omap2/clock.c')
| -rw-r--r-- | arch/arm/mach-omap2/clock.c | 1241 |
1 files changed, 440 insertions, 801 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 759c72a48f7..591581a6653 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -2,7 +2,7 @@ * linux/arch/arm/mach-omap2/clock.c * * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2008 Nokia Corporation + * Copyright (C) 2004-2010 Nokia Corporation * * Contacts: * Richard Woodruff <r-woodruff2@ti.com> @@ -14,165 +14,172 @@ */ #undef DEBUG -#include <linux/module.h> #include <linux/kernel.h> -#include <linux/device.h> +#include <linux/export.h> #include <linux/list.h> #include <linux/errno.h> +#include <linux/err.h> #include <linux/delay.h> -#include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/io.h> #include <linux/bitops.h> +#include <linux/clk-private.h> +#include <asm/cpu.h> -#include <plat/clock.h> -#include <plat/clockdomain.h> -#include <plat/cpu.h> -#include <plat/prcm.h> -#include <asm/div64.h> +#include <trace/events/power.h> -#include <plat/sdrc.h> -#include "sdrc.h" +#include "soc.h" +#include "clockdomain.h" #include "clock.h" -#include "prm.h" -#include "prm-regbits-24xx.h" #include "cm.h" +#include "cm2xxx.h" +#include "cm3xxx.h" #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" - -/* DPLL rate rounding: minimum DPLL multiplier, divider values */ -#define DPLL_MIN_MULTIPLIER 1 -#define DPLL_MIN_DIVIDER 1 - -/* Possible error results from _dpll_test_mult */ -#define DPLL_MULT_UNDERFLOW -1 +#include "common.h" /* - * Scale factor to mitigate roundoff errors in DPLL rate rounding. - * The higher the scale factor, the greater the risk of arithmetic overflow, - * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR - * must be a power of DPLL_SCALE_BASE. + * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait + * for a module to indicate that it is no longer in idle */ -#define DPLL_SCALE_FACTOR 64 -#define DPLL_SCALE_BASE 2 -#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ - (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) - -/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ -#define DPLL_FINT_BAND1_MIN 750000 -#define DPLL_FINT_BAND1_MAX 2100000 -#define DPLL_FINT_BAND2_MIN 7500000 -#define DPLL_FINT_BAND2_MAX 21000000 +#define MAX_MODULE_ENABLE_WAIT 100000 -/* _dpll_test_fint() return codes */ -#define DPLL_FINT_UNDERFLOW -1 -#define DPLL_FINT_INVALID -2 +u16 cpu_mask; -u8 cpu_mask; +/* + * clkdm_control: if true, then when a clock is enabled in the + * hardware, its clockdomain will first be enabled; and when a clock + * is disabled in the hardware, its clockdomain will be disabled + * afterwards. + */ +static bool clkdm_control = true; -/*------------------------------------------------------------------------- - * OMAP2/3/4 specific clock functions - *-------------------------------------------------------------------------*/ +static LIST_HEAD(clk_hw_omap_clocks); +void __iomem *clk_memmaps[CLK_MAX_MEMMAPS]; -void omap2_init_dpll_parent(struct clk *clk) +void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) { - u32 v; - struct dpll_data *dd; + if (clk->flags & MEMMAP_ADDRESSING) { + struct clk_omap_reg *r = (struct clk_omap_reg *)® + writel_relaxed(val, clk_memmaps[r->index] + r->offset); + } else { + writel_relaxed(val, reg); + } +} - dd = clk->dpll_data; - if (!dd) - return; +u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) +{ + u32 val; - /* Return bypass rate if DPLL is bypassed */ - v = __raw_readl(dd->control_reg); - v &= dd->enable_mask; - v >>= __ffs(dd->enable_mask); - - /* Reparent in case the dpll is in bypass */ - if (cpu_is_omap24xx()) { - if (v == OMAP2XXX_EN_DPLL_LPBYPASS || - v == OMAP2XXX_EN_DPLL_FRBYPASS) - clk_reparent(clk, dd->clk_bypass); - } else if (cpu_is_omap34xx()) { - if (v == OMAP3XXX_EN_DPLL_LPBYPASS || - v == OMAP3XXX_EN_DPLL_FRBYPASS) - clk_reparent(clk, dd->clk_bypass); - } else if (cpu_is_omap44xx()) { - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || - v == OMAP4XXX_EN_DPLL_FRBYPASS || - v == OMAP4XXX_EN_DPLL_MNBYPASS) - clk_reparent(clk, dd->clk_bypass); + if (clk->flags & MEMMAP_ADDRESSING) { + struct clk_omap_reg *r = (struct clk_omap_reg *)® + val = readl_relaxed(clk_memmaps[r->index] + r->offset); + } else { + val = readl_relaxed(reg); } - return; + + return val; } -/** - * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware - * @clk: struct clk * - * - * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes - * don't take effect until the VALID_CONFIG bit is written, write the - * VALID_CONFIG bit and wait for the write to complete. No return value. +/* + * Used for clocks that have the same value as the parent clock, + * divided by some factor */ -static void _omap2xxx_clk_commit(struct clk *clk) +unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, + unsigned long parent_rate) { - if (!cpu_is_omap24xx()) - return; + struct clk_hw_omap *oclk; - if (!(clk->flags & DELAYED_APP)) - return; + if (!hw) { + pr_warn("%s: hw is NULL\n", __func__); + return -EINVAL; + } + + oclk = to_clk_hw_omap(hw); - prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, - OMAP2_PRCM_CLKCFG_CTRL_OFFSET); - /* OCP barrier */ - prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET); + WARN_ON(!oclk->fixed_div); + + return parent_rate / oclk->fixed_div; } /* - * _dpll_test_fint - test whether an Fint value is valid for the DPLL - * @clk: DPLL struct clk to test - * @n: divider value (N) to test - * - * Tests whether a particular divider @n will result in a valid DPLL - * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter - * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate - * (assuming that it is counting N upwards), or -2 if the enclosing loop - * should skip to the next iteration (again assuming N is increasing). + * OMAP2+ specific clock functions */ -static int _dpll_test_fint(struct clk *clk, u8 n) -{ - struct dpll_data *dd; - long fint; - int ret = 0; - dd = clk->dpll_data; +/* Private functions */ - /* DPLL divider must result in a valid jitter correction val */ - fint = clk->parent->rate / (n + 1); - if (fint < DPLL_FINT_BAND1_MIN) { - pr_debug("rejecting n=%d due to Fint failure, " - "lowering max_divider\n", n); - dd->max_divider = n; - ret = DPLL_FINT_UNDERFLOW; +/** + * _wait_idlest_generic - wait for a module to leave the idle state + * @clk: module clock to wait for (needed for register offsets) + * @reg: virtual address of module IDLEST register + * @mask: value to mask against to determine if the module is active + * @idlest: idle state indicator (0 or 1) for the clock + * @name: name of the clock (for printk) + * + * Wait for a module to leave idle, where its idle-status register is + * not inside the CM module. Returns 1 if the module left idle + * promptly, or 0 if the module did not leave idle before the timeout + * elapsed. XXX Deprecated - should be moved into drivers for the + * individual IP block that the IDLEST register exists in. + */ +static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, + u32 mask, u8 idlest, const char *name) +{ + int i = 0, ena = 0; - } else if (fint > DPLL_FINT_BAND1_MAX && - fint < DPLL_FINT_BAND2_MIN) { + ena = (idlest) ? 0 : mask; - pr_debug("rejecting n=%d due to Fint failure\n", n); - ret = DPLL_FINT_INVALID; + omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena), + MAX_MODULE_ENABLE_WAIT, i); - } else if (fint > DPLL_FINT_BAND2_MAX) { + if (i < MAX_MODULE_ENABLE_WAIT) + pr_debug("omap clock: module associated with clock %s ready after %d loops\n", + name, i); + else + pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n", + name, MAX_MODULE_ENABLE_WAIT); - pr_debug("rejecting n=%d due to Fint failure, " - "boosting min_divider\n", n); - dd->min_divider = n; - ret = DPLL_FINT_INVALID; + return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; +}; + +/** + * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE + * @clk: struct clk * belonging to the module + * + * If the necessary clocks for the OMAP hardware IP block that + * corresponds to clock @clk are enabled, then wait for the module to + * indicate readiness (i.e., to leave IDLE). This code does not + * belong in the clock code and will be moved in the medium term to + * module-dependent code. No return value. + */ +static void _omap2_module_wait_ready(struct clk_hw_omap *clk) +{ + void __iomem *companion_reg, *idlest_reg; + u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; + s16 prcm_mod; + int r; + /* Not all modules have multiple clocks that their IDLEST depends on */ + if (clk->ops->find_companion) { + clk->ops->find_companion(clk, &companion_reg, &other_bit); + if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit))) + return; } - return ret; + clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); + r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); + if (r) { + /* IDLEST register not in the CM module */ + _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), + idlest_val, __clk_get_name(clk->hw.clk)); + } else { + cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); + }; } +/* Public functions */ + /** * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk * @clk: OMAP clock struct ptr to use @@ -181,134 +188,39 @@ static int _dpll_test_fint(struct clk *clk, u8 n) * clockdomain pointer, and save it into the struct clk. Intended to be * called during clk_register(). No return value. */ -#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ -void omap2_init_clk_clkdm(struct clk *clk) +void omap2_init_clk_clkdm(struct clk_hw *hw) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); struct clockdomain *clkdm; + const char *clk_name; if (!clk->clkdm_name) return; + clk_name = __clk_get_name(hw->clk); + clkdm = clkdm_lookup(clk->clkdm_name); if (clkdm) { pr_debug("clock: associated clk %s to clkdm %s\n", - clk->name, clk->clkdm_name); + clk_name, clk->clkdm_name); clk->clkdm = clkdm; } else { - pr_debug("clock: could not associate clk %s to " - "clkdm %s\n", clk->name, clk->clkdm_name); - } -} -#endif - -/** - * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware - * @clk: OMAP clock struct ptr to use - * - * Given a pointer to a source-selectable struct clk, read the hardware - * register and determine what its parent is currently set to. Update the - * clk->parent field with the appropriate clk ptr. - */ -void omap2_init_clksel_parent(struct clk *clk) -{ - const struct clksel *clks; - const struct clksel_rate *clkr; - u32 r, found = 0; - - if (!clk->clksel) - return; - - r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; - r >>= __ffs(clk->clksel_mask); - - for (clks = clk->clksel; clks->parent && !found; clks++) { - for (clkr = clks->rates; clkr->div && !found; clkr++) { - if ((clkr->flags & cpu_mask) && (clkr->val == r)) { - if (clk->parent != clks->parent) { - pr_debug("clock: inited %s parent " - "to %s (was %s)\n", - clk->name, clks->parent->name, - ((clk->parent) ? - clk->parent->name : "NULL")); - clk_reparent(clk, clks->parent); - }; - found = 1; - } - } + pr_debug("clock: could not associate clk %s to clkdm %s\n", + clk_name, clk->clkdm_name); } - - if (!found) - printk(KERN_ERR "clock: init parent: could not find " - "regval %0x for clock %s\n", r, clk->name); - - return; } /** - * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate - * @clk: struct clk * of a DPLL + * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable * - * DPLLs can be locked or bypassed - basically, enabled or disabled. - * When locked, the DPLL output depends on the M and N values. When - * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock - * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and - * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively - * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. - * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is - * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 - * if the clock @clk is not a DPLL. - */ -u32 omap2_get_dpll_rate(struct clk *clk) -{ - long long dpll_clk; - u32 dpll_mult, dpll_div, v; - struct dpll_data *dd; - - dd = clk->dpll_data; - if (!dd) - return 0; - - /* Return bypass rate if DPLL is bypassed */ - v = __raw_readl(dd->control_reg); - v &= dd->enable_mask; - v >>= __ffs(dd->enable_mask); - - if (cpu_is_omap24xx()) { - if (v == OMAP2XXX_EN_DPLL_LPBYPASS || - v == OMAP2XXX_EN_DPLL_FRBYPASS) - return dd->clk_bypass->rate; - } else if (cpu_is_omap34xx()) { - if (v == OMAP3XXX_EN_DPLL_LPBYPASS || - v == OMAP3XXX_EN_DPLL_FRBYPASS) - return dd->clk_bypass->rate; - } else if (cpu_is_omap44xx()) { - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || - v == OMAP4XXX_EN_DPLL_FRBYPASS || - v == OMAP4XXX_EN_DPLL_MNBYPASS) - return dd->clk_bypass->rate; - } - - v = __raw_readl(dd->mult_div1_reg); - dpll_mult = v & dd->mult_mask; - dpll_mult >>= __ffs(dd->mult_mask); - dpll_div = v & dd->div1_mask; - dpll_div >>= __ffs(dd->div1_mask); - - dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; - do_div(dpll_clk, dpll_div + 1); - - return dpll_clk; -} - -/* - * Used for clocks that have the same value as the parent clock, - * divided by some factor + * Prevent the OMAP clock code from calling into the clockdomain code + * when a hardware clock in that clockdomain is enabled or disabled. + * Intended to be called at init time from omap*_clk_init(). No + * return value. */ -unsigned long omap2_fixed_divisor_recalc(struct clk *clk) +void __init omap2_clk_disable_clkdm_control(void) { - WARN_ON(!clk->fixed_div); - - return clk->parent->rate / clk->fixed_div; + clkdm_control = false; } /** @@ -332,8 +244,8 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk) * associate this type of code with per-module data structures to * avoid this issue, and remove the casts. No return value. */ -void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, - u8 *other_bit) +void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, + void __iomem **other_reg, u8 *other_bit) { u32 r; @@ -351,7 +263,8 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk * @clk: struct clk * to find IDLEST info for * @idlest_reg: void __iomem ** to return the CM_IDLEST va in - * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in + * @idlest_bit: u8 * to return the CM_IDLEST bit shift in + * @idlest_val: u8 * to return the idle status indicator * * Return the CM_IDLEST register address and bit shift corresponding * to the module that "owns" this clock. This default code assumes @@ -360,735 +273,461 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, * register address ID (e.g., that CM_FCLKEN2 corresponds to * CM_IDLEST2). This is not true for all modules. No return value. */ -void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, - u8 *idlest_bit) +void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, + void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) { u32 r; r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); *idlest_reg = (__force void __iomem *)r; *idlest_bit = clk->enable_bit; + + /* + * 24xx uses 0 to indicate not ready, and 1 to indicate ready. + * 34xx reverses this, just to keep us on our toes + * AM35xx uses both, depending on the module. + */ + if (cpu_is_omap24xx()) + *idlest_val = OMAP24XX_CM_IDLEST_VAL; + else if (cpu_is_omap34xx()) + *idlest_val = OMAP34XX_CM_IDLEST_VAL; + else + BUG(); + } /** - * omap2_module_wait_ready - wait for an OMAP module to leave IDLE - * @clk: struct clk * belonging to the module + * omap2_dflt_clk_enable - enable a clock in the hardware + * @hw: struct clk_hw * of the clock to enable * - * If the necessary clocks for the OMAP hardware IP block that - * corresponds to clock @clk are enabled, then wait for the module to - * indicate readiness (i.e., to leave IDLE). This code does not - * belong in the clock code and will be moved in the medium term to - * module-dependent code. No return value. + * Enable the clock @hw in the hardware. We first call into the OMAP + * clockdomain code to "enable" the corresponding clockdomain if this + * is the first enabled user of the clockdomain. Then program the + * hardware to enable the clock. Then wait for the IP block that uses + * this clock to leave idle (if applicable). Returns the error value + * from clkdm_clk_enable() if it terminated with an error, or -EINVAL + * if @hw has a null clock enable_reg, or zero upon success. */ -static void omap2_module_wait_ready(struct clk *clk) +int omap2_dflt_clk_enable(struct clk_hw *hw) { - void __iomem *companion_reg, *idlest_reg; - u8 other_bit, idlest_bit; - - /* Not all modules have multiple clocks that their IDLEST depends on */ - if (clk->ops->find_companion) { - clk->ops->find_companion(clk, &companion_reg, &other_bit); - if (!(__raw_readl(companion_reg) & (1 << other_bit))) - return; - } - - clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit); + struct clk_hw_omap *clk; + u32 v; + int ret = 0; - omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name); -} + clk = to_clk_hw_omap(hw); -int omap2_dflt_clk_enable(struct clk *clk) -{ - u32 v; + if (clkdm_control && clk->clkdm) { + ret = clkdm_clk_enable(clk->clkdm, hw->clk); + if (ret) { + WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), + clk->clkdm->name, ret); + return ret; + } + } if (unlikely(clk->enable_reg == NULL)) { - pr_err("clock.c: Enable for %s without enable code\n", - clk->name); - return 0; /* REVISIT: -EINVAL */ + pr_err("%s: %s missing enable_reg\n", __func__, + __clk_get_name(hw->clk)); + ret = -EINVAL; + goto err; } - v = __raw_readl(clk->enable_reg); + /* FIXME should not have INVERT_ENABLE bit here */ + v = omap2_clk_readl(clk, clk->enable_reg); if (clk->flags & INVERT_ENABLE) v &= ~(1 << clk->enable_bit); else v |= (1 << clk->enable_bit); - __raw_writel(v, clk->enable_reg); - v = __raw_readl(clk->enable_reg); /* OCP barrier */ + omap2_clk_writel(v, clk, clk->enable_reg); + v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ - if (clk->ops->find_idlest) - omap2_module_wait_ready(clk); + if (clk->ops && clk->ops->find_idlest) + _omap2_module_wait_ready(clk); return 0; + +err: + if (clkdm_control && clk->clkdm) + clkdm_clk_disable(clk->clkdm, hw->clk); + return ret; } -void omap2_dflt_clk_disable(struct clk *clk) +/** + * omap2_dflt_clk_disable - disable a clock in the hardware + * @hw: struct clk_hw * of the clock to disable + * + * Disable the clock @hw in the hardware, and call into the OMAP + * clockdomain code to "disable" the corresponding clockdomain if all + * clocks/hwmods in that clockdomain are now disabled. No return + * value. + */ +void omap2_dflt_clk_disable(struct clk_hw *hw) { + struct clk_hw_omap *clk; u32 v; + clk = to_clk_hw_omap(hw); if (!clk->enable_reg) { /* - * 'Independent' here refers to a clock which is not + * 'independent' here refers to a clock which is not * controlled by its parent. */ - printk(KERN_ERR "clock: clk_disable called on independent " - "clock %s which has no enable_reg\n", clk->name); + pr_err("%s: independent clock %s has no enable_reg\n", + __func__, __clk_get_name(hw->clk)); return; } - v = __raw_readl(clk->enable_reg); + v = omap2_clk_readl(clk, clk->enable_reg); if (clk->flags & INVERT_ENABLE) v |= (1 << clk->enable_bit); else v &= ~(1 << clk->enable_bit); - __raw_writel(v, clk->enable_reg); + omap2_clk_writel(v, clk, clk->enable_reg); /* No OCP barrier needed here since it is a disable operation */ -} - -const struct clkops clkops_omap2_dflt_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_companion = omap2_clk_dflt_find_companion, - .find_idlest = omap2_clk_dflt_find_idlest, -}; - -const struct clkops clkops_omap2_dflt = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, -}; - -/* Enables clock without considering parent dependencies or use count - * REVISIT: Maybe change this to use clk->enable like on omap1? - */ -static int _omap2_clk_enable(struct clk *clk) -{ - return clk->ops->enable(clk); -} -/* Disables clock without considering parent dependencies or use count */ -static void _omap2_clk_disable(struct clk *clk) -{ - clk->ops->disable(clk); + if (clkdm_control && clk->clkdm) + clkdm_clk_disable(clk->clkdm, hw->clk); } -void omap2_clk_disable(struct clk *clk) -{ - if (clk->usecount > 0 && !(--clk->usecount)) { - _omap2_clk_disable(clk); - if (clk->parent) - omap2_clk_disable(clk->parent); -#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ - if (clk->clkdm) - omap2_clkdm_clk_disable(clk->clkdm, clk); -#endif - - } -} - -int omap2_clk_enable(struct clk *clk) +/** + * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw + * @hw: struct clk_hw * of the clock being enabled + * + * Increment the usecount of the clockdomain of the clock pointed to + * by @hw; if the usecount is 1, the clockdomain will be "enabled." + * Only needed for clocks that don't use omap2_dflt_clk_enable() as + * their enable function pointer. Passes along the return value of + * clkdm_clk_enable(), -EINVAL if @hw is not associated with a + * clockdomain, or 0 if clock framework-based clockdomain control is + * not implemented. + */ +int omap2_clkops_enable_clkdm(struct clk_hw *hw) { + struct clk_hw_omap *clk; int ret = 0; - if (clk->usecount++ == 0) { -#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ - if (clk->clkdm) - omap2_clkdm_clk_enable(clk->clkdm, clk); -#endif + clk = to_clk_hw_omap(hw); - if (clk->parent) { - ret = omap2_clk_enable(clk->parent); - if (ret) - goto err; - } - - ret = _omap2_clk_enable(clk); - if (ret) { - if (clk->parent) - omap2_clk_disable(clk->parent); - - goto err; - } + if (unlikely(!clk->clkdm)) { + pr_err("%s: %s: no clkdm set ?!\n", __func__, + __clk_get_name(hw->clk)); + return -EINVAL; } - return ret; - -err: -#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ - if (clk->clkdm) - omap2_clkdm_clk_disable(clk->clkdm, clk); -#endif - clk->usecount--; - return ret; -} -/* - * Used for clocks that are part of CLKSEL_xyz governed clocks. - * REVISIT: Maybe change to use clk->enable() functions like on omap1? - */ -unsigned long omap2_clksel_recalc(struct clk *clk) -{ - unsigned long rate; - u32 div = 0; + if (unlikely(clk->enable_reg)) + pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, + __clk_get_name(hw->clk)); - pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); - - div = omap2_clksel_get_divisor(clk); - if (div == 0) - return clk->rate; - - rate = clk->parent->rate / div; + if (!clkdm_control) { + pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", + __func__, __clk_get_name(hw->clk)); + return 0; + } - pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div); + ret = clkdm_clk_enable(clk->clkdm, hw->clk); + WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); - return rate; + return ret; } /** - * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent - * @clk: OMAP struct clk ptr to inspect - * @src_clk: OMAP struct clk ptr of the parent clk to search for + * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw + * @hw: struct clk_hw * of the clock being disabled * - * Scan the struct clksel array associated with the clock to find - * the element associated with the supplied parent clock address. - * Returns a pointer to the struct clksel on success or NULL on error. + * Decrement the usecount of the clockdomain of the clock pointed to + * by @hw; if the usecount is 0, the clockdomain will be "disabled." + * Only needed for clocks that don't use omap2_dflt_clk_disable() as their + * disable function pointer. No return value. */ -static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, - struct clk *src_clk) +void omap2_clkops_disable_clkdm(struct clk_hw *hw) { - const struct clksel *clks; + struct clk_hw_omap *clk; - if (!clk->clksel) - return NULL; + clk = to_clk_hw_omap(hw); - for (clks = clk->clksel; clks->parent; clks++) { - if (clks->parent == src_clk) - break; /* Found the requested parent */ + if (unlikely(!clk->clkdm)) { + pr_err("%s: %s: no clkdm set ?!\n", __func__, + __clk_get_name(hw->clk)); + return; } - if (!clks->parent) { - printk(KERN_ERR "clock: Could not find parent clock %s in " - "clksel array of clock %s\n", src_clk->name, - clk->name); - return NULL; + if (unlikely(clk->enable_reg)) + pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, + __clk_get_name(hw->clk)); + + if (!clkdm_control) { + pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", + __func__, __clk_get_name(hw->clk)); + return; } - return clks; + clkdm_clk_disable(clk->clkdm, hw->clk); } /** - * omap2_clksel_round_rate_div - find divisor for the given clock and rate - * @clk: OMAP struct clk to use - * @target_rate: desired clock rate - * @new_div: ptr to where we should store the divisor - * - * Finds 'best' divider value in an array based on the source and target - * rates. The divider array must be sorted with smallest divider first. - * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, - * they are only settable as part of virtual_prcm set. + * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? + * @hw: struct clk_hw * to check * - * Returns the rounded clock rate or returns 0xffffffff on error. + * Return 1 if the clock represented by @hw is enabled in the + * hardware, or 0 otherwise. Intended for use in the struct + * clk_ops.is_enabled function pointer. */ -u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, - u32 *new_div) +int omap2_dflt_clk_is_enabled(struct clk_hw *hw) { - unsigned long test_rate; - const struct clksel *clks; - const struct clksel_rate *clkr; - u32 last_div = 0; - - pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", - clk->name, target_rate); - - *new_div = 1; - - clks = omap2_get_clksel_by_parent(clk, clk->parent); - if (!clks) - return ~0; + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + u32 v; - for (clkr = clks->rates; clkr->div; clkr++) { - if (!(clkr->flags & cpu_mask)) - continue; + v = omap2_clk_readl(clk, clk->enable_reg); - /* Sanity check */ - if (clkr->div <= last_div) - pr_err("clock: clksel_rate table not sorted " - "for clock %s", clk->name); + if (clk->flags & INVERT_ENABLE) + v ^= BIT(clk->enable_bit); - last_div = clkr->div; + v &= BIT(clk->enable_bit); - test_rate = clk->parent->rate / clkr->div; + return v ? 1 : 0; +} - if (test_rate <= target_rate) - break; /* found it */ - } +static int __initdata mpurate; - if (!clkr->div) { - pr_err("clock: Could not find divisor for target " - "rate %ld for clock %s parent %s\n", target_rate, - clk->name, clk->parent->name); - return ~0; - } +/* + * By default we use the rate set by the bootloader. + * You can override this with mpurate= cmdline option. + */ +static int __init omap_clk_setup(char *str) +{ + get_option(&str, &mpurate); - *new_div = clkr->div; + if (!mpurate) + return 1; - pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, - (clk->parent->rate / clkr->div)); + if (mpurate < 1000) + mpurate *= 1000000; - return (clk->parent->rate / clkr->div); + return 1; } +__setup("mpurate=", omap_clk_setup); /** - * omap2_clksel_round_rate - find rounded rate for the given clock and rate - * @clk: OMAP struct clk to use - * @target_rate: desired clock rate + * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock + * @clk: struct clk * to initialize * - * Compatibility wrapper for OMAP clock framework - * Finds best target rate based on the source clock and possible dividers. - * rates. The divider array must be sorted with smallest divider first. - * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, - * they are only settable as part of virtual_prcm set. - * - * Returns the rounded clock rate or returns 0xffffffff on error. + * Add an OMAP clock @clk to the internal list of OMAP clocks. Used + * temporarily for autoidle handling, until this support can be + * integrated into the common clock framework code in some way. No + * return value. */ -long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) -{ - u32 new_div; - - return omap2_clksel_round_rate_div(clk, target_rate, &new_div); -} - - -/* Given a clock and a rate apply a clock specific rounding function */ -long omap2_clk_round_rate(struct clk *clk, unsigned long rate) +void omap2_init_clk_hw_omap_clocks(struct clk *clk) { - if (clk->round_rate) - return clk->round_rate(clk, rate); + struct clk_hw_omap *c; - if (clk->flags & RATE_FIXED) - printk(KERN_ERR "clock: generic omap2_clk_round_rate called " - "on fixed-rate clock %s\n", clk->name); + if (__clk_get_flags(clk) & CLK_IS_BASIC) + return; - return clk->rate; + c = to_clk_hw_omap(__clk_get_hw(clk)); + list_add(&c->node, &clk_hw_omap_clocks); } /** - * omap2_clksel_to_divisor() - turn clksel field value into integer divider - * @clk: OMAP struct clk to use - * @field_val: register field value to find + * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that + * support it * - * Given a struct clk of a rate-selectable clksel clock, and a register field - * value to search for, find the corresponding clock divisor. The register - * field value should be pre-masked and shifted down so the LSB is at bit 0 - * before calling. Returns 0 on error + * Enable clock autoidle on all OMAP clocks that have allow_idle + * function pointers associated with them. This function is intended + * to be temporary until support for this is added to the common clock + * code. Returns 0. */ -u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) +int omap2_clk_enable_autoidle_all(void) { - const struct clksel *clks; - const struct clksel_rate *clkr; + struct clk_hw_omap *c; - clks = omap2_get_clksel_by_parent(clk, clk->parent); - if (!clks) - return 0; - - for (clkr = clks->rates; clkr->div; clkr++) { - if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) - break; - } + list_for_each_entry(c, &clk_hw_omap_clocks, node) + if (c->ops && c->ops->allow_idle) + c->ops->allow_idle(c); - if (!clkr->div) { - printk(KERN_ERR "clock: Could not find fieldval %d for " - "clock %s parent %s\n", field_val, clk->name, - clk->parent->name); - return 0; - } + of_ti_clk_allow_autoidle_all(); - return clkr->div; + return 0; } /** - * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value - * @clk: OMAP struct clk to use - * @div: integer divisor to search for + * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that + * support it * - * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, - * find the corresponding register field value. The return register value is - * the value before left-shifting. Returns ~0 on error + * Disable clock autoidle on all OMAP clocks that have allow_idle + * function pointers associated with them. This function is intended + * to be temporary until support for this is added to the common clock + * code. Returns 0. */ -u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) +int omap2_clk_disable_autoidle_all(void) { - const struct clksel *clks; - const struct clksel_rate *clkr; + struct clk_hw_omap *c; - /* should never happen */ - WARN_ON(div == 0); + list_for_each_entry(c, &clk_hw_omap_clocks, node) + if (c->ops && c->ops->deny_idle) + c->ops->deny_idle(c); - clks = omap2_get_clksel_by_parent(clk, clk->parent); - if (!clks) - return ~0; + of_ti_clk_deny_autoidle_all(); - for (clkr = clks->rates; clkr->div; clkr++) { - if ((clkr->flags & cpu_mask) && (clkr->div == div)) - break; - } - - if (!clkr->div) { - printk(KERN_ERR "clock: Could not find divisor %d for " - "clock %s parent %s\n", div, clk->name, - clk->parent->name); - return ~0; - } - - return clkr->val; + return 0; } /** - * omap2_clksel_get_divisor - get current divider applied to parent clock. - * @clk: OMAP struct clk to use. + * omap2_clk_deny_idle - disable autoidle on an OMAP clock + * @clk: struct clk * to disable autoidle for * - * Returns the integer divisor upon success or 0 on error. + * Disable autoidle on an OMAP clock. */ -u32 omap2_clksel_get_divisor(struct clk *clk) -{ - u32 v; - - if (!clk->clksel_mask) - return 0; - - v = __raw_readl(clk->clksel_reg) & clk->clksel_mask; - v >>= __ffs(clk->clksel_mask); - - return omap2_clksel_to_divisor(clk, v); -} - -int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) +int omap2_clk_deny_idle(struct clk *clk) { - u32 v, field_val, validrate, new_div = 0; - - if (!clk->clksel_mask) - return -EINVAL; - - validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); - if (validrate != rate) - return -EINVAL; + struct clk_hw_omap *c; - field_val = omap2_divisor_to_clksel(clk, new_div); - if (field_val == ~0) + if (__clk_get_flags(clk) & CLK_IS_BASIC) return -EINVAL; - v = __raw_readl(clk->clksel_reg); - v &= ~clk->clksel_mask; - v |= field_val << __ffs(clk->clksel_mask); - __raw_writel(v, clk->clksel_reg); - v = __raw_readl(clk->clksel_reg); /* OCP barrier */ - - clk->rate = clk->parent->rate / new_div; - - _omap2xxx_clk_commit(clk); - + c = to_clk_hw_omap(__clk_get_hw(clk)); + if (c->ops && c->ops->deny_idle) + c->ops->deny_idle(c); return 0; } - -/* Set the clock rate for a clock source */ -int omap2_clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret = -EINVAL; - - pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); - - /* CONFIG_PARTICIPANT clocks are changed only in sets via the - rate table mechanism, driven by mpu_speed */ - if (clk->flags & CONFIG_PARTICIPANT) - return -EINVAL; - - /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ - if (clk->set_rate) - ret = clk->set_rate(clk, rate); - - return ret; -} - -/* - * Converts encoded control register address into a full address - * On error, the return value (parent_div) will be 0. +/** + * omap2_clk_allow_idle - enable autoidle on an OMAP clock + * @clk: struct clk * to enable autoidle for + * + * Enable autoidle on an OMAP clock. */ -static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, - u32 *field_val) -{ - const struct clksel *clks; - const struct clksel_rate *clkr; - - clks = omap2_get_clksel_by_parent(clk, src_clk); - if (!clks) - return 0; - - for (clkr = clks->rates; clkr->div; clkr++) { - if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE) - break; /* Found the default rate for this platform */ - } - - if (!clkr->div) { - printk(KERN_ERR "clock: Could not find default rate for " - "clock %s parent %s\n", clk->name, - src_clk->parent->name); - return 0; - } - - /* Should never happen. Add a clksel mask to the struct clk. */ - WARN_ON(clk->clksel_mask == 0); - - *field_val = clkr->val; - - return clkr->div; -} - -int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) +int omap2_clk_allow_idle(struct clk *clk) { - u32 field_val, v, parent_div; - - if (clk->flags & CONFIG_PARTICIPANT) - return -EINVAL; + struct clk_hw_omap *c; - if (!clk->clksel) + if (__clk_get_flags(clk) & CLK_IS_BASIC) return -EINVAL; - parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val); - if (!parent_div) - return -EINVAL; - - /* Set new source value (previous dividers if any in effect) */ - v = __raw_readl(clk->clksel_reg); - v &= ~clk->clksel_mask; - v |= field_val << __ffs(clk->clksel_mask); - __raw_writel(v, clk->clksel_reg); - v = __raw_readl(clk->clksel_reg); /* OCP barrier */ - - _omap2xxx_clk_commit(clk); - - clk_reparent(clk, new_parent); - - /* CLKSEL clocks follow their parents' rates, divided by a divisor */ - clk->rate = new_parent->rate; - - if (parent_div > 0) - clk->rate /= parent_div; - - pr_debug("clock: set parent of %s to %s (new rate %ld)\n", - clk->name, clk->parent->name, clk->rate); - + c = to_clk_hw_omap(__clk_get_hw(clk)); + if (c->ops && c->ops->allow_idle) + c->ops->allow_idle(c); return 0; } -/* DPLL rate rounding code */ - /** - * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding - * @clk: struct clk * of the DPLL - * @tolerance: maximum rate error tolerance + * omap2_clk_enable_init_clocks - prepare & enable a list of clocks + * @clk_names: ptr to an array of strings of clock names to enable + * @num_clocks: number of clock names in @clk_names * - * Set the maximum DPLL rate error tolerance for the rate rounding - * algorithm. The rate tolerance is an attempt to balance DPLL power - * saving (the least divider value "n") vs. rate fidelity (the least - * difference between the desired DPLL target rate and the rounded - * rate out of the algorithm). So, increasing the tolerance is likely - * to decrease DPLL power consumption and increase DPLL rate error. - * Returns -EINVAL if provided a null clock ptr or a clk that is not a - * DPLL; or 0 upon success. + * Prepare and enable a list of clocks, named by @clk_names. No + * return value. XXX Deprecated; only needed until these clocks are + * properly claimed and enabled by the drivers or core code that uses + * them. XXX What code disables & calls clk_put on these clocks? */ -int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) +void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) { - if (!clk || !clk->dpll_data) - return -EINVAL; - - clk->dpll_data->rate_tolerance = tolerance; + struct clk *init_clk; + int i; - return 0; + for (i = 0; i < num_clocks; i++) { + init_clk = clk_get(NULL, clk_names[i]); + clk_prepare_enable(init_clk); + } } -static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, - unsigned int m, unsigned int n) -{ - unsigned long long num; - - num = (unsigned long long)parent_rate * m; - do_div(num, n); - return num; -} +const struct clk_hw_omap_ops clkhwops_wait = { + .find_idlest = omap2_clk_dflt_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; -/* - * _dpll_test_mult - test a DPLL multiplier value - * @m: pointer to the DPLL m (multiplier) value under test - * @n: current DPLL n (divider) value under test - * @new_rate: pointer to storage for the resulting rounded rate - * @target_rate: the desired DPLL rate - * @parent_rate: the DPLL's parent clock rate - * - * This code tests a DPLL multiplier value, ensuring that the - * resulting rate will not be higher than the target_rate, and that - * the multiplier value itself is valid for the DPLL. Initially, the - * integer pointed to by the m argument should be prescaled by - * multiplying by DPLL_SCALE_FACTOR. The code will replace this with - * a non-scaled m upon return. This non-scaled m will result in a - * new_rate as close as possible to target_rate (but not greater than - * target_rate) given the current (parent_rate, n, prescaled m) - * triple. Returns DPLL_MULT_UNDERFLOW in the event that the - * non-scaled m attempted to underflow, which can allow the calling - * function to bail out early; or 0 upon success. +/** + * omap_clocks_register - register an array of omap_clk + * @ocs: pointer to an array of omap_clk to register */ -static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, - unsigned long target_rate, - unsigned long parent_rate) +void __init omap_clocks_register(struct omap_clk oclks[], int cnt) { - int r = 0, carry = 0; + struct omap_clk *c; - /* Unscale m and round if necessary */ - if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) - carry = 1; - *m = (*m / DPLL_SCALE_FACTOR) + carry; - - /* - * The new rate must be <= the target rate to avoid programming - * a rate that is impossible for the hardware to handle - */ - *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); - if (*new_rate > target_rate) { - (*m)--; - *new_rate = 0; - } - - /* Guard against m underflow */ - if (*m < DPLL_MIN_MULTIPLIER) { - *m = DPLL_MIN_MULTIPLIER; - *new_rate = 0; - r = DPLL_MULT_UNDERFLOW; + for (c = oclks; c < oclks + cnt; c++) { + clkdev_add(&c->lk); + if (!__clk_init(NULL, c->lk.clk)) + omap2_init_clk_hw_omap_clocks(c->lk.clk); } - - if (*new_rate == 0) - *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); - - return r; } /** - * omap2_dpll_round_rate - round a target rate for an OMAP DPLL - * @clk: struct clk * for a DPLL - * @target_rate: desired DPLL clock rate + * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument + * @mpurate_ck_name: clk name of the clock to change rate * - * Given a DPLL, a desired target rate, and a rate tolerance, round - * the target rate to a possible, programmable rate for this DPLL. - * Rate tolerance is assumed to be set by the caller before this - * function is called. Attempts to select the minimum possible n - * within the tolerance to reduce power consumption. Stores the - * computed (m, n) in the DPLL's dpll_data structure so set_rate() - * will not need to call this (expensive) function again. Returns ~0 - * if the target rate cannot be rounded, either because the rate is - * too low or because the rate tolerance is set too tightly; or the - * rounded rate upon success. + * Change the ARM MPU clock rate to the rate specified on the command + * line, if one was specified. @mpurate_ck_name should be + * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. + * XXX Does not handle voltage scaling - on OMAP2xxx this is currently + * handled by the virt_prcm_set clock, but this should be handled by + * the OPP layer. XXX This is intended to be handled by the OPP layer + * code in the near future and should be removed from the clock code. + * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects + * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name + * cannot be found, or 0 upon success. */ -long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) +int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) { - int m, n, r, e, scaled_max_m; - unsigned long scaled_rt_rp, new_rate; - int min_e = -1, min_e_m = -1, min_e_n = -1; - struct dpll_data *dd; - - if (!clk || !clk->dpll_data) - return ~0; - - dd = clk->dpll_data; - - pr_debug("clock: starting DPLL round_rate for clock %s, target rate " - "%ld\n", clk->name, target_rate); - - scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); - scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; - - dd->last_rounded_rate = 0; - - for (n = dd->min_divider; n <= dd->max_divider; n++) { - - /* Is the (input clk, divider) pair valid for the DPLL? */ - r = _dpll_test_fint(clk, n); - if (r == DPLL_FINT_UNDERFLOW) - break; - else if (r == DPLL_FINT_INVALID) - continue; - - /* Compute the scaled DPLL multiplier, based on the divider */ - m = scaled_rt_rp * n; - - /* - * Since we're counting n up, a m overflow means we - * can bail out completely (since as n increases in - * the next iteration, there's no way that m can - * increase beyond the current m) - */ - if (m > scaled_max_m) - break; + struct clk *mpurate_ck; + int r; - r = _dpll_test_mult(&m, n, &new_rate, target_rate, - dd->clk_ref->rate); - - /* m can't be set low enough for this n - try with a larger n */ - if (r == DPLL_MULT_UNDERFLOW) - continue; - - e = target_rate - new_rate; - pr_debug("clock: n = %d: m = %d: rate error is %d " - "(new_rate = %ld)\n", n, m, e, new_rate); - - if (min_e == -1 || - min_e >= (int)(abs(e) - dd->rate_tolerance)) { - min_e = e; - min_e_m = m; - min_e_n = n; + if (!mpurate) + return -EINVAL; - pr_debug("clock: found new least error %d\n", min_e); + mpurate_ck = clk_get(NULL, mpurate_ck_name); + if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) + return -ENOENT; - /* We found good settings -- bail out now */ - if (min_e <= dd->rate_tolerance) - break; - } - } - - if (min_e < 0) { - pr_debug("clock: error: target rate or tolerance too low\n"); - return ~0; + r = clk_set_rate(mpurate_ck, mpurate); + if (r < 0) { + WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", + mpurate_ck_name, mpurate, r); + clk_put(mpurate_ck); + return -EINVAL; } - dd->last_rounded_m = min_e_m; - dd->last_rounded_n = min_e_n; - dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate, - min_e_m, min_e_n); - - pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", - min_e, min_e_m, min_e_n); - pr_debug("clock: final rate: %ld (target rate: %ld)\n", - dd->last_rounded_rate, target_rate); + calibrate_delay(); + clk_put(mpurate_ck); - return dd->last_rounded_rate; + return 0; } -/*------------------------------------------------------------------------- - * Omap2 clock reset and init functions - *-------------------------------------------------------------------------*/ - -#ifdef CONFIG_OMAP_RESET_CLOCKS -void omap2_clk_disable_unused(struct clk *clk) +/** + * omap2_clk_print_new_rates - print summary of current clock tree rates + * @hfclkin_ck_name: clk name for the off-chip HF oscillator + * @core_ck_name: clk name for the on-chip CORE_CLK + * @mpu_ck_name: clk name for the ARM MPU clock + * + * Prints a short message to the console with the HFCLKIN oscillator + * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. + * Called by the boot-time MPU rate switching code. XXX This is intended + * to be handled by the OPP layer code in the near future and should be + * removed from the clock code. No return value. + */ +void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, + const char *core_ck_name, + const char *mpu_ck_name) { - u32 regval32, v; + struct clk *hfclkin_ck, *core_ck, *mpu_ck; + unsigned long hfclkin_rate; - v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; + mpu_ck = clk_get(NULL, mpu_ck_name); + if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) + return; + + core_ck = clk_get(NULL, core_ck_name); + if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) + return; - regval32 = __raw_readl(clk->enable_reg); - if ((regval32 & (1 << clk->enable_bit)) == v) + hfclkin_ck = clk_get(NULL, hfclkin_ck_name); + if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) return; - printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); - if (cpu_is_omap34xx()) { - omap2_clk_enable(clk); - omap2_clk_disable(clk); - } else - _omap2_clk_disable(clk); - if (clk->clkdm != NULL) - pwrdm_clkdm_state_switch(clk->clkdm); + hfclkin_rate = clk_get_rate(hfclkin_ck); + + pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", + (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), + (clk_get_rate(core_ck) / 1000000), + (clk_get_rate(mpu_ck) / 1000000)); } -#endif |