diff options
Diffstat (limited to 'arch/arm/mach-mv78xx0')
25 files changed, 997 insertions, 1012 deletions
diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig index d83cb86837d..f2d309d0619 100644 --- a/arch/arm/mach-mv78xx0/Kconfig +++ b/arch/arm/mach-mv78xx0/Kconfig @@ -8,6 +8,18 @@ config MACH_DB78X00_BP Say 'Y' here if you want your kernel to support the Marvell DB-78x00-BP Development Board. +config MACH_RD78X00_MASA + bool "Marvell RD-78x00-mASA Reference Design" + help + Say 'Y' here if you want your kernel to support the + Marvell RD-78x00-mASA Reference Design. + +config MACH_TERASTATION_WXL + bool "Buffalo WLX (Terastation Duo) NAS" + help + Say 'Y' here if you want your kernel to support the + Buffalo WXL Nas. + endmenu endif diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile index ec16c05c3b1..7cd04634d30 100644 --- a/arch/arm/mach-mv78xx0/Makefile +++ b/arch/arm/mach-mv78xx0/Makefile @@ -1,2 +1,4 @@ -obj-y += common.o addr-map.o irq.o pcie.o +obj-y += common.o mpp.o irq.o pcie.o obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o +obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o +obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o diff --git a/arch/arm/mach-mv78xx0/Makefile.boot b/arch/arm/mach-mv78xx0/Makefile.boot index 67039c3e0c4..760a0efe758 100644 --- a/arch/arm/mach-mv78xx0/Makefile.boot +++ b/arch/arm/mach-mv78xx0/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c deleted file mode 100644 index 311d5b0e9bc..00000000000 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/addr-map.c - * - * Address map functions for Marvell MV78xx0 SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mbus.h> -#include <linux/io.h> -#include "common.h" - -/* - * Generic Address Decode Windows bit settings - */ -#define TARGET_DDR 0 -#define TARGET_DEV_BUS 1 -#define TARGET_PCIE0 4 -#define TARGET_PCIE1 8 -#define TARGET_PCIE(i) ((i) ? TARGET_PCIE1 : TARGET_PCIE0) -#define ATTR_DEV_SPI_ROM 0x1f -#define ATTR_DEV_BOOT 0x2f -#define ATTR_DEV_CS3 0x37 -#define ATTR_DEV_CS2 0x3b -#define ATTR_DEV_CS1 0x3d -#define ATTR_DEV_CS0 0x3e -#define ATTR_PCIE_IO(l) (0xf0 & ~(0x10 << (l))) -#define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l))) - -/* - * Helpers to get DDR bank info - */ -#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) -#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) - -/* - * CPU Address Decode Windows registers - */ -#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) -#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) -#define WIN_CTRL_OFF 0x0000 -#define WIN_BASE_OFF 0x0004 -#define WIN_REMAP_LO_OFF 0x0008 -#define WIN_REMAP_HI_OFF 0x000c - - -struct mbus_dram_target_info mv78xx0_mbus_dram_info; - -static void __init __iomem *win_cfg_base(int win) -{ - /* - * Find the control register base address for this window. - * - * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's) - * MBUS bridge depending on which CPU core we're running on, - * so we don't need to take that into account here. - */ - - return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win)); -} - -static int __init cpu_win_can_remap(int win) -{ - if (win < 8) - return 1; - - return 0; -} - -static void __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) -{ - void __iomem *addr = win_cfg_base(win); - u32 ctrl; - - base &= 0xffff0000; - ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; - - writel(base, addr + WIN_BASE_OFF); - writel(ctrl, addr + WIN_CTRL_OFF); - if (cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - - writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF); - writel(0, addr + WIN_REMAP_HI_OFF); - } -} - -void __init mv78xx0_setup_cpu_mbus(void) -{ - void __iomem *addr; - int i; - int cs; - - /* - * First, disable and clear windows. - */ - for (i = 0; i < 14; i++) { - addr = win_cfg_base(i); - - writel(0, addr + WIN_BASE_OFF); - writel(0, addr + WIN_CTRL_OFF); - if (cpu_win_can_remap(i)) { - writel(0, addr + WIN_REMAP_LO_OFF); - writel(0, addr + WIN_REMAP_HI_OFF); - } - } - - /* - * Setup MBUS dram target info. - */ - mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - - if (mv78xx0_core_index() == 0) - addr = (void __iomem *)DDR_WINDOW_CPU0_BASE; - else - addr = (void __iomem *)DDR_WINDOW_CPU1_BASE; - - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(addr + DDR_BASE_CS_OFF(i)); - u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); - - /* - * Chip select enabled? - */ - if (size & 1) { - struct mbus_dram_window *w; - - w = &mv78xx0_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0xf & ~(1 << i); - w->base = base & 0xffff0000; - w->size = (size | 0x0000ffff) + 1; - } - } - mv78xx0_mbus_dram_info.num_cs = cs; -} - -void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, - int maj, int min) -{ - setup_cpu_win(window, base, size, TARGET_PCIE(maj), - ATTR_PCIE_IO(min), -1); -} - -void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, - int maj, int min) -{ - setup_cpu_win(window, base, size, TARGET_PCIE(maj), - ATTR_PCIE_MEM(min), -1); -} diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c new file mode 100644 index 00000000000..1f2ef98b37c --- /dev/null +++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c @@ -0,0 +1,155 @@ +/* + * arch/arm/mach-mv78xx0/buffalo-wxl-setup.c + * + * Buffalo WXL (Terastation Duo) Setup routines + * + * sebastien requiem <sebastien@requiem.fr> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/ata_platform.h> +#include <linux/mv643xx_eth.h> +#include <linux/ethtool.h> +#include <linux/i2c.h> +#include <mach/mv78xx0.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include "common.h" +#include "mpp.h" + + +/* This arch has 2 Giga Ethernet */ + +static struct mv643xx_eth_platform_data db78x00_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(0), +}; + +static struct mv643xx_eth_platform_data db78x00_ge01_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(8), +}; + + +/* 2 SATA controller supporting HotPlug */ + +static struct mv_sata_platform_data db78x00_sata_data = { + .n_ports = 2, +}; + +static struct i2c_board_info __initdata db78x00_i2c_rtc = { + I2C_BOARD_INFO("ds1338", 0x68), +}; + + +static unsigned int wxl_mpp_config[] __initdata = { + MPP0_GE1_TXCLK, + MPP1_GE1_TXCTL, + MPP2_GE1_RXCTL, + MPP3_GE1_RXCLK, + MPP4_GE1_TXD0, + MPP5_GE1_TXD1, + MPP6_GE1_TXD2, + MPP7_GE1_TXD3, + MPP8_GE1_RXD0, + MPP9_GE1_RXD1, + MPP10_GE1_RXD2, + MPP11_GE1_RXD3, + MPP12_GPIO, + MPP13_SYSRST_OUTn, + MPP14_SATA1_ACTn, + MPP15_SATA0_ACTn, + MPP16_GPIO, + MPP17_GPIO, + MPP18_GPIO, + MPP19_GPIO, + MPP20_GPIO, + MPP21_GPIO, + MPP22_GPIO, + MPP23_GPIO, + MPP24_UA2_TXD, + MPP25_UA2_RXD, + MPP26_UA2_CTSn, + MPP27_UA2_RTSn, + MPP28_GPIO, + MPP29_SYSRST_OUTn, + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_UNUSED, + MPP41_UNUSED, + MPP42_UNUSED, + MPP43_UNUSED, + MPP44_UNUSED, + MPP45_UNUSED, + MPP46_UNUSED, + MPP47_UNUSED, + MPP48_SATA1_ACTn, + MPP49_SATA0_ACTn, + 0 +}; + + +static void __init wxl_init(void) +{ + /* + * Basic MV78xx0 setup. Needs to be called early. + */ + mv78xx0_init(); + mv78xx0_mpp_conf(wxl_mpp_config); + + /* + * Partition on-chip peripherals between the two CPU cores. + */ + mv78xx0_ehci0_init(); + mv78xx0_ehci1_init(); + mv78xx0_ehci2_init(); + mv78xx0_ge00_init(&db78x00_ge00_data); + mv78xx0_ge01_init(&db78x00_ge01_data); + mv78xx0_sata_init(&db78x00_sata_data); + mv78xx0_uart0_init(); + mv78xx0_uart1_init(); + mv78xx0_uart2_init(); + mv78xx0_uart3_init(); + mv78xx0_i2c_init(); + i2c_register_board_info(0, &db78x00_i2c_rtc, 1); +} + +static int __init wxl_pci_init(void) +{ + if (machine_is_terastation_wxl()) { + /* + * Assign the x16 PCIe slot on the board to CPU core + * #0, and let CPU core #1 have the four x1 slots. + */ + if (mv78xx0_core_index() == 0) + mv78xx0_pcie_init(0, 1); + else + mv78xx0_pcie_init(1, 0); + } + + return 0; +} +subsys_initcall(wxl_pci_init); + +MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL") + /* Maintainer: Sebastien Requiem <sebastien@requiem.fr> */ + .atag_offset = 0x100, + .init_machine = wxl_init, + .map_io = mv78xx0_map_io, + .init_early = mv78xx0_init_early, + .init_irq = mv78xx0_init_irq, + .init_time = mv78xx0_timer_init, + .restart = mv78xx0_restart, +MACHINE_END diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index b0e4e0d8f50..e6ac679bece 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -12,18 +12,22 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/serial_8250.h> -#include <linux/mbus.h> -#include <linux/mv643xx_eth.h> #include <linux/ata_platform.h> +#include <linux/clk-provider.h> +#include <linux/ethtool.h> +#include <asm/hardware/cache-feroceon-l2.h> #include <asm/mach/map.h> #include <asm/mach/time.h> #include <mach/mv78xx0.h> -#include <plat/cache-feroceon-l2.h> -#include <plat/ehci-orion.h> -#include <plat/orion_nand.h> +#include <mach/bridge-regs.h> +#include <linux/platform_data/usb-ehci-orion.h> +#include <linux/platform_data/mtd-orion_nand.h> #include <plat/time.h> +#include <plat/common.h> +#include <plat/addr-map.h> #include "common.h" +static int get_tclk(void); /***************************************************************************** * Common bits @@ -100,24 +104,24 @@ static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk) static int get_tclk(void) { - int tclk; + int tclk_freq; /* * TCLK tick rate is configured by DEV_A[2:0] strap pins. */ switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) { case 1: - tclk = 166666667; + tclk_freq = 166666667; break; case 3: - tclk = 200000000; + tclk_freq = 200000000; break; default: panic("unknown TCLK PLL setting: %.8x\n", readl(SAMPLE_AT_RESET_HIGH)); } - return tclk; + return tclk_freq; } @@ -126,17 +130,12 @@ static int get_tclk(void) ****************************************************************************/ static struct map_desc mv78xx0_io_desc[] __initdata = { { - .virtual = MV78XX0_CORE_REGS_VIRT_BASE, + .virtual = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE, .pfn = 0, .length = MV78XX0_CORE_REGS_SIZE, .type = MT_DEVICE, }, { - .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), - .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), - .length = MV78XX0_PCIE_IO_SIZE * 8, - .type = MT_DEVICE, - }, { - .virtual = MV78XX0_REGS_VIRT_BASE, + .virtual = (unsigned long) MV78XX0_REGS_VIRT_BASE, .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), .length = MV78XX0_REGS_SIZE, .type = MT_DEVICE, @@ -163,562 +162,226 @@ void __init mv78xx0_map_io(void) /***************************************************************************** - * EHCI + * CLK tree ****************************************************************************/ -static struct orion_ehci_data mv78xx0_ehci_data = { - .dram = &mv78xx0_mbus_dram_info, - .phy_version = EHCI_PHY_NA, -}; +static struct clk *tclk; -static u64 ehci_dmamask = 0xffffffffUL; +static void __init clk_init(void) +{ + tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, + get_tclk()); + orion_clkdev_init(tclk); +} /***************************************************************************** - * EHCI0 + * EHCI ****************************************************************************/ -static struct resource mv78xx0_ehci0_resources[] = { - { - .start = USB0_PHYS_BASE, - .end = USB0_PHYS_BASE + 0x0fff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_USB_0, - .end = IRQ_MV78XX0_USB_0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ehci0 = { - .name = "orion-ehci", - .id = 0, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &mv78xx0_ehci_data, - }, - .resource = mv78xx0_ehci0_resources, - .num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources), -}; - void __init mv78xx0_ehci0_init(void) { - platform_device_register(&mv78xx0_ehci0); + orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA); } /***************************************************************************** * EHCI1 ****************************************************************************/ -static struct resource mv78xx0_ehci1_resources[] = { - { - .start = USB1_PHYS_BASE, - .end = USB1_PHYS_BASE + 0x0fff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_USB_1, - .end = IRQ_MV78XX0_USB_1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ehci1 = { - .name = "orion-ehci", - .id = 1, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &mv78xx0_ehci_data, - }, - .resource = mv78xx0_ehci1_resources, - .num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources), -}; - void __init mv78xx0_ehci1_init(void) { - platform_device_register(&mv78xx0_ehci1); + orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1); } /***************************************************************************** * EHCI2 ****************************************************************************/ -static struct resource mv78xx0_ehci2_resources[] = { - { - .start = USB2_PHYS_BASE, - .end = USB2_PHYS_BASE + 0x0fff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_USB_2, - .end = IRQ_MV78XX0_USB_2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ehci2 = { - .name = "orion-ehci", - .id = 2, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &mv78xx0_ehci_data, - }, - .resource = mv78xx0_ehci2_resources, - .num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources), -}; - void __init mv78xx0_ehci2_init(void) { - platform_device_register(&mv78xx0_ehci2); + orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2); } /***************************************************************************** * GE00 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = { - .t_clk = 0, - .dram = &mv78xx0_mbus_dram_info, -}; - -static struct resource mv78xx0_ge00_shared_resources[] = { - { - .name = "ge00 base", - .start = GE00_PHYS_BASE + 0x2000, - .end = GE00_PHYS_BASE + 0x3fff, - .flags = IORESOURCE_MEM, - }, { - .name = "ge err irq", - .start = IRQ_MV78XX0_GE_ERR, - .end = IRQ_MV78XX0_GE_ERR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ge00_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &mv78xx0_ge00_shared_data, - }, - .num_resources = ARRAY_SIZE(mv78xx0_ge00_shared_resources), - .resource = mv78xx0_ge00_shared_resources, -}; - -static struct resource mv78xx0_ge00_resources[] = { - { - .name = "ge00 irq", - .start = IRQ_MV78XX0_GE00_SUM, - .end = IRQ_MV78XX0_GE00_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ge00 = { - .name = MV643XX_ETH_NAME, - .id = 0, - .num_resources = 1, - .resource = mv78xx0_ge00_resources, -}; - void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &mv78xx0_ge00_shared; - mv78xx0_ge00.dev.platform_data = eth_data; - - platform_device_register(&mv78xx0_ge00_shared); - platform_device_register(&mv78xx0_ge00); + orion_ge00_init(eth_data, + GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, + IRQ_MV78XX0_GE_ERR, + MV643XX_TX_CSUM_DEFAULT_LIMIT); } /***************************************************************************** * GE01 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = { - .t_clk = 0, - .dram = &mv78xx0_mbus_dram_info, - .shared_smi = &mv78xx0_ge00_shared, -}; - -static struct resource mv78xx0_ge01_shared_resources[] = { - { - .name = "ge01 base", - .start = GE01_PHYS_BASE + 0x2000, - .end = GE01_PHYS_BASE + 0x3fff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device mv78xx0_ge01_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 1, - .dev = { - .platform_data = &mv78xx0_ge01_shared_data, - }, - .num_resources = 1, - .resource = mv78xx0_ge01_shared_resources, -}; - -static struct resource mv78xx0_ge01_resources[] = { - { - .name = "ge01 irq", - .start = IRQ_MV78XX0_GE01_SUM, - .end = IRQ_MV78XX0_GE01_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ge01 = { - .name = MV643XX_ETH_NAME, - .id = 1, - .num_resources = 1, - .resource = mv78xx0_ge01_resources, -}; - void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &mv78xx0_ge01_shared; - mv78xx0_ge01.dev.platform_data = eth_data; - - platform_device_register(&mv78xx0_ge01_shared); - platform_device_register(&mv78xx0_ge01); + orion_ge01_init(eth_data, + GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, + NO_IRQ, + MV643XX_TX_CSUM_DEFAULT_LIMIT); } /***************************************************************************** * GE10 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = { - .t_clk = 0, - .dram = &mv78xx0_mbus_dram_info, - .shared_smi = &mv78xx0_ge00_shared, -}; - -static struct resource mv78xx0_ge10_shared_resources[] = { - { - .name = "ge10 base", - .start = GE10_PHYS_BASE + 0x2000, - .end = GE10_PHYS_BASE + 0x3fff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device mv78xx0_ge10_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 2, - .dev = { - .platform_data = &mv78xx0_ge10_shared_data, - }, - .num_resources = 1, - .resource = mv78xx0_ge10_shared_resources, -}; - -static struct resource mv78xx0_ge10_resources[] = { - { - .name = "ge10 irq", - .start = IRQ_MV78XX0_GE10_SUM, - .end = IRQ_MV78XX0_GE10_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ge10 = { - .name = MV643XX_ETH_NAME, - .id = 2, - .num_resources = 1, - .resource = mv78xx0_ge10_resources, -}; - void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &mv78xx0_ge10_shared; - mv78xx0_ge10.dev.platform_data = eth_data; + u32 dev, rev; - platform_device_register(&mv78xx0_ge10_shared); - platform_device_register(&mv78xx0_ge10); + /* + * On the Z0, ge10 and ge11 are internally connected back + * to back, and not brought out. + */ + mv78xx0_pcie_id(&dev, &rev); + if (dev == MV78X00_Z0_DEV_ID) { + eth_data->phy_addr = MV643XX_ETH_PHY_NONE; + eth_data->speed = SPEED_1000; + eth_data->duplex = DUPLEX_FULL; + } + + orion_ge10_init(eth_data, + GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, + NO_IRQ); } /***************************************************************************** * GE11 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = { - .t_clk = 0, - .dram = &mv78xx0_mbus_dram_info, - .shared_smi = &mv78xx0_ge00_shared, -}; - -static struct resource mv78xx0_ge11_shared_resources[] = { - { - .name = "ge11 base", - .start = GE11_PHYS_BASE + 0x2000, - .end = GE11_PHYS_BASE + 0x3fff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device mv78xx0_ge11_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 3, - .dev = { - .platform_data = &mv78xx0_ge11_shared_data, - }, - .num_resources = 1, - .resource = mv78xx0_ge11_shared_resources, -}; - -static struct resource mv78xx0_ge11_resources[] = { - { - .name = "ge11 irq", - .start = IRQ_MV78XX0_GE11_SUM, - .end = IRQ_MV78XX0_GE11_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ge11 = { - .name = MV643XX_ETH_NAME, - .id = 3, - .num_resources = 1, - .resource = mv78xx0_ge11_resources, -}; - void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &mv78xx0_ge11_shared; - mv78xx0_ge11.dev.platform_data = eth_data; + u32 dev, rev; + + /* + * On the Z0, ge10 and ge11 are internally connected back + * to back, and not brought out. + */ + mv78xx0_pcie_id(&dev, &rev); + if (dev == MV78X00_Z0_DEV_ID) { + eth_data->phy_addr = MV643XX_ETH_PHY_NONE; + eth_data->speed = SPEED_1000; + eth_data->duplex = DUPLEX_FULL; + } - platform_device_register(&mv78xx0_ge11_shared); - platform_device_register(&mv78xx0_ge11); + orion_ge11_init(eth_data, + GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, + NO_IRQ); } +/***************************************************************************** + * I2C + ****************************************************************************/ +void __init mv78xx0_i2c_init(void) +{ + orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8); + orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8); +} /***************************************************************************** * SATA ****************************************************************************/ -static struct resource mv78xx0_sata_resources[] = { - { - .name = "sata base", - .start = SATA_PHYS_BASE, - .end = SATA_PHYS_BASE + 0x5000 - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "sata irq", - .start = IRQ_MV78XX0_SATA, - .end = IRQ_MV78XX0_SATA, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_sata = { - .name = "sata_mv", - .id = 0, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(mv78xx0_sata_resources), - .resource = mv78xx0_sata_resources, -}; - void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) { - sata_data->dram = &mv78xx0_mbus_dram_info; - mv78xx0_sata.dev.platform_data = sata_data; - platform_device_register(&mv78xx0_sata); + orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA); } /***************************************************************************** * UART0 ****************************************************************************/ -static struct plat_serial8250_port mv78xx0_uart0_data[] = { - { - .mapbase = UART0_PHYS_BASE, - .membase = (char *)UART0_VIRT_BASE, - .irq = IRQ_MV78XX0_UART_0, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource mv78xx0_uart0_resources[] = { - { - .start = UART0_PHYS_BASE, - .end = UART0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_UART_0, - .end = IRQ_MV78XX0_UART_0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_uart0 = { - .name = "serial8250", - .id = 0, - .dev = { - .platform_data = mv78xx0_uart0_data, - }, - .resource = mv78xx0_uart0_resources, - .num_resources = ARRAY_SIZE(mv78xx0_uart0_resources), -}; - void __init mv78xx0_uart0_init(void) { - platform_device_register(&mv78xx0_uart0); + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, + IRQ_MV78XX0_UART_0, tclk); } /***************************************************************************** * UART1 ****************************************************************************/ -static struct plat_serial8250_port mv78xx0_uart1_data[] = { - { - .mapbase = UART1_PHYS_BASE, - .membase = (char *)UART1_VIRT_BASE, - .irq = IRQ_MV78XX0_UART_1, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource mv78xx0_uart1_resources[] = { - { - .start = UART1_PHYS_BASE, - .end = UART1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_UART_1, - .end = IRQ_MV78XX0_UART_1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_uart1 = { - .name = "serial8250", - .id = 1, - .dev = { - .platform_data = mv78xx0_uart1_data, - }, - .resource = mv78xx0_uart1_resources, - .num_resources = ARRAY_SIZE(mv78xx0_uart1_resources), -}; - void __init mv78xx0_uart1_init(void) { - platform_device_register(&mv78xx0_uart1); + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, + IRQ_MV78XX0_UART_1, tclk); } /***************************************************************************** * UART2 ****************************************************************************/ -static struct plat_serial8250_port mv78xx0_uart2_data[] = { - { - .mapbase = UART2_PHYS_BASE, - .membase = (char *)UART2_VIRT_BASE, - .irq = IRQ_MV78XX0_UART_2, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource mv78xx0_uart2_resources[] = { - { - .start = UART2_PHYS_BASE, - .end = UART2_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_UART_2, - .end = IRQ_MV78XX0_UART_2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_uart2 = { - .name = "serial8250", - .id = 2, - .dev = { - .platform_data = mv78xx0_uart2_data, - }, - .resource = mv78xx0_uart2_resources, - .num_resources = ARRAY_SIZE(mv78xx0_uart2_resources), -}; - void __init mv78xx0_uart2_init(void) { - platform_device_register(&mv78xx0_uart2); + orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE, + IRQ_MV78XX0_UART_2, tclk); } - /***************************************************************************** * UART3 ****************************************************************************/ -static struct plat_serial8250_port mv78xx0_uart3_data[] = { - { - .mapbase = UART3_PHYS_BASE, - .membase = (char *)UART3_VIRT_BASE, - .irq = IRQ_MV78XX0_UART_3, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource mv78xx0_uart3_resources[] = { - { - .start = UART3_PHYS_BASE, - .end = UART3_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_UART_3, - .end = IRQ_MV78XX0_UART_3, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_uart3 = { - .name = "serial8250", - .id = 3, - .dev = { - .platform_data = mv78xx0_uart3_data, - }, - .resource = mv78xx0_uart3_resources, - .num_resources = ARRAY_SIZE(mv78xx0_uart3_resources), -}; - void __init mv78xx0_uart3_init(void) { - platform_device_register(&mv78xx0_uart3); + orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE, + IRQ_MV78XX0_UART_3, tclk); } - /***************************************************************************** * Time handling ****************************************************************************/ -static void mv78xx0_timer_init(void) +void __init mv78xx0_init_early(void) { - orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk()); + orion_time_set_base(TIMER_VIRT_BASE); + if (mv78xx0_core_index() == 0) + mvebu_mbus_init("marvell,mv78xx0-mbus", + BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ, + DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ); + else + mvebu_mbus_init("marvell,mv78xx0-mbus", + BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ, + DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ); } -struct sys_timer mv78xx0_timer = { - .init = mv78xx0_timer_init, -}; +void __init_refok mv78xx0_timer_init(void) +{ + orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, + IRQ_MV78XX0_TIMER_1, get_tclk()); +} /***************************************************************************** * General ****************************************************************************/ +static char * __init mv78xx0_id(void) +{ + u32 dev, rev; + + mv78xx0_pcie_id(&dev, &rev); + + if (dev == MV78X00_Z0_DEV_ID) { + if (rev == MV78X00_REV_Z0) + return "MV78X00-Z0"; + else + return "MV78X00-Rev-Unsupported"; + } else if (dev == MV78100_DEV_ID) { + if (rev == MV78100_REV_A0) + return "MV78100-A0"; + else if (rev == MV78100_REV_A1) + return "MV78100-A1"; + else + return "MV78100-Rev-Unsupported"; + } else if (dev == MV78200_DEV_ID) { + if (rev == MV78100_REV_A0) + return "MV78200-A0"; + else + return "MV78200-Rev-Unsupported"; + } else { + return "Device-Unknown"; + } +} + static int __init is_l2_writethrough(void) { return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); @@ -730,31 +393,38 @@ void __init mv78xx0_init(void) int hclk; int pclk; int l2clk; - int tclk; core_index = mv78xx0_core_index(); hclk = get_hclk(); get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); - tclk = get_tclk(); - printk(KERN_INFO "MV78xx0 core #%d, ", core_index); + printk(KERN_INFO "%s ", mv78xx0_id()); + printk("core #%d, ", core_index); printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000); printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); - printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000); - - mv78xx0_setup_cpu_mbus(); + printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); #ifdef CONFIG_CACHE_FEROCEON_L2 feroceon_l2_init(is_l2_writethrough()); #endif - mv78xx0_ge00_shared_data.t_clk = tclk; - mv78xx0_ge01_shared_data.t_clk = tclk; - mv78xx0_ge10_shared_data.t_clk = tclk; - mv78xx0_ge11_shared_data.t_clk = tclk; - mv78xx0_uart0_data[0].uartclk = tclk; - mv78xx0_uart1_data[0].uartclk = tclk; - mv78xx0_uart2_data[0].uartclk = tclk; - mv78xx0_uart3_data[0].uartclk = tclk; + /* Setup root of clk tree */ + clk_init(); +} + +void mv78xx0_restart(enum reboot_mode mode, const char *cmd) +{ + /* + * Enable soft reset to assert RSTOUTn. + */ + writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); + + /* + * Assert soft reset. + */ + writel(SOFT_RESET, SYSTEM_SOFT_RESET); + + while (1) + ; } diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h index 78af5de319d..6889af26077 100644 --- a/arch/arm/mach-mv78xx0/common.h +++ b/arch/arm/mach-mv78xx0/common.h @@ -11,6 +11,8 @@ #ifndef __ARCH_MV78XX0_COMMON_H #define __ARCH_MV78XX0_COMMON_H +#include <linux/reboot.h> + struct mv643xx_eth_platform_data; struct mv_sata_platform_data; @@ -20,15 +22,17 @@ struct mv_sata_platform_data; int mv78xx0_core_index(void); void mv78xx0_map_io(void); void mv78xx0_init(void); +void mv78xx0_init_early(void); void mv78xx0_init_irq(void); -extern struct mbus_dram_target_info mv78xx0_mbus_dram_info; void mv78xx0_setup_cpu_mbus(void); void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, int maj, int min); void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, int maj, int min); +void mv78xx0_pcie_id(u32 *dev, u32 *rev); + void mv78xx0_ehci0_init(void); void mv78xx0_ehci1_init(void); void mv78xx0_ehci2_init(void); @@ -42,8 +46,10 @@ void mv78xx0_uart0_init(void); void mv78xx0_uart1_init(void); void mv78xx0_uart2_init(void); void mv78xx0_uart3_init(void); +void mv78xx0_i2c_init(void); +void mv78xx0_restart(enum reboot_mode, const char *); -extern struct sys_timer mv78xx0_timer; +extern void mv78xx0_timer_init(void); #endif diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c index 2e285bbb7bb..4e0f22b30bc 100644 --- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c +++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c @@ -14,6 +14,7 @@ #include <linux/ata_platform.h> #include <linux/mv643xx_eth.h> #include <linux/ethtool.h> +#include <linux/i2c.h> #include <mach/mv78xx0.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -28,21 +29,22 @@ static struct mv643xx_eth_platform_data db78x00_ge01_data = { }; static struct mv643xx_eth_platform_data db78x00_ge10_data = { - .phy_addr = MV643XX_ETH_PHY_NONE, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, + .phy_addr = MV643XX_ETH_PHY_ADDR(10), }; static struct mv643xx_eth_platform_data db78x00_ge11_data = { - .phy_addr = MV643XX_ETH_PHY_NONE, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, + .phy_addr = MV643XX_ETH_PHY_ADDR(11), }; static struct mv_sata_platform_data db78x00_sata_data = { .n_ports = 2, }; +static struct i2c_board_info __initdata db78x00_i2c_rtc = { + I2C_BOARD_INFO("ds1338", 0x68), +}; + + static void __init db78x00_init(void) { /* @@ -64,6 +66,8 @@ static void __init db78x00_init(void) mv78xx0_sata_init(&db78x00_sata_data); mv78xx0_uart0_init(); mv78xx0_uart2_init(); + mv78xx0_i2c_init(); + i2c_register_board_info(0, &db78x00_i2c_rtc, 1); } else { mv78xx0_uart1_init(); mv78xx0_uart3_init(); @@ -89,11 +93,11 @@ subsys_initcall(db78x00_pci_init); MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board") /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ - .phys_io = MV78XX0_REGS_PHYS_BASE, - .io_pg_offst = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, + .atag_offset = 0x100, .init_machine = db78x00_init, .map_io = mv78xx0_map_io, + .init_early = mv78xx0_init_early, .init_irq = mv78xx0_init_irq, - .timer = &mv78xx0_timer, + .init_time = mv78xx0_timer_init, + .restart = mv78xx0_restart, MACHINE_END diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h new file mode 100644 index 00000000000..e20d6da234a --- /dev/null +++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h @@ -0,0 +1,37 @@ +/* + * arch/arm/mach-mv78xx0/include/mach/bridge-regs.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_BRIDGE_REGS_H +#define __ASM_ARCH_BRIDGE_REGS_H + +#include <mach/mv78xx0.h> + +#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) +#define L2_WRITETHROUGH 0x00020000 + +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) +#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) +#define SOFT_RESET_OUT_EN 0x00000004 + +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) +#define SOFT_RESET 0x00000001 + +#define BRIDGE_INT_TIMER1_CLR (~0x0004) + +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) +#define IRQ_CAUSE_ERR_OFF 0x0000 +#define IRQ_CAUSE_LOW_OFF 0x0004 +#define IRQ_CAUSE_HIGH_OFF 0x0008 +#define IRQ_MASK_ERR_OFF 0x000c +#define IRQ_MASK_LOW_OFF 0x0010 +#define IRQ_MASK_HIGH_OFF 0x0014 + +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) +#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) + +#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S b/arch/arm/mach-mv78xx0/include/mach/debug-macro.S deleted file mode 100644 index a06442fbd34..00000000000 --- a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S +++ /dev/null @@ -1,20 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/debug-macro.S - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <mach/mv78xx0.h> - - .macro addruart,rx - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 @ MMU enabled? - ldreq \rx, =MV78XX0_REGS_PHYS_BASE - ldrne \rx, =MV78XX0_REGS_VIRT_BASE - orr \rx, \rx, #0x00012000 - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S b/arch/arm/mach-mv78xx0/include/mach/entry-macro.S index fbfb2693ce6..6b1f088e059 100644 --- a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S +++ b/arch/arm/mach-mv78xx0/include/mach/entry-macro.S @@ -8,13 +8,7 @@ * warranty of any kind, whether express or implied. */ -#include <mach/mv78xx0.h> - - .macro disable_fiq - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm +#include <mach/bridge-regs.h> .macro get_irqnr_preamble, base, tmp ldr \base, =IRQ_VIRT_BASE diff --git a/arch/arm/mach-mv78xx0/include/mach/gpio.h b/arch/arm/mach-mv78xx0/include/mach/gpio.h deleted file mode 100644 index d9d1535ea10..00000000000 --- a/arch/arm/mach-mv78xx0/include/mach/gpio.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * arch/asm-arm/mach-mv78xx0/include/mach/gpio.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - -#include <mach/irqs.h> -#include <plat/gpio.h> -#include <asm-generic/gpio.h> /* cansleep wrappers */ - -extern int mv78xx0_core_index(void); - -#define GPIO_MAX 32 -#define GPIO_OUT(pin) (DEV_BUS_VIRT_BASE + 0x0100) -#define GPIO_IO_CONF(pin) (DEV_BUS_VIRT_BASE + 0x0104) -#define GPIO_BLINK_EN(pin) (DEV_BUS_VIRT_BASE + 0x0108) -#define GPIO_IN_POL(pin) (DEV_BUS_VIRT_BASE + 0x010c) -#define GPIO_DATA_IN(pin) (DEV_BUS_VIRT_BASE + 0x0110) -#define GPIO_EDGE_CAUSE(pin) (DEV_BUS_VIRT_BASE + 0x0114) -#define GPIO_MASK_OFF (mv78xx0_core_index() ? 0x18 : 0) -#define GPIO_EDGE_MASK(pin) (DEV_BUS_VIRT_BASE + 0x0118 + GPIO_MASK_OFF) -#define GPIO_LEVEL_MASK(pin) (DEV_BUS_VIRT_BASE + 0x011c + GPIO_MASK_OFF) - -static inline int gpio_to_irq(int pin) -{ - return pin + IRQ_MV78XX0_GPIO_START; -} - -static inline int irq_to_gpio(int irq) -{ - return irq - IRQ_MV78XX0_GPIO_START; -} - - -#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/hardware.h b/arch/arm/mach-mv78xx0/include/mach/hardware.h index 5d887557e12..67cab0a08e0 100644 --- a/arch/arm/mach-mv78xx0/include/mach/hardware.h +++ b/arch/arm/mach-mv78xx0/include/mach/hardware.h @@ -11,11 +11,4 @@ #include "mv78xx0.h" -#define pcibios_assign_all_busses() 1 - -#define PCIBIOS_MIN_IO 0x00001000 -#define PCIBIOS_MIN_MEM 0x01000000 -#define PCIMEM_BASE MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */ - - #endif diff --git a/arch/arm/mach-mv78xx0/include/mach/io.h b/arch/arm/mach-mv78xx0/include/mach/io.h deleted file mode 100644 index 450e0e1ad09..00000000000 --- a/arch/arm/mach-mv78xx0/include/mach/io.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/io.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include "mv78xx0.h" - -#define IO_SPACE_LIMIT 0xffffffff - -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0)) - + MV78XX0_PCIE_IO_VIRT_BASE(0)); -} - -#define __io(a) __io(a) -#define __mem_pci(a) (a) - - -#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/memory.h b/arch/arm/mach-mv78xx0/include/mach/memory.h deleted file mode 100644 index e663042d307..00000000000 --- a/arch/arm/mach-mv78xx0/include/mach/memory.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/memory.h - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -#define PHYS_OFFSET UL(0x00000000) - -#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index e930ea5330a..723748d8ba7 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -29,27 +29,27 @@ * * virt phys size * fe400000 f102x000 16K core-specific peripheral registers - * fe700000 f0800000 1M PCIe #0 I/O space - * fe800000 f0900000 1M PCIe #1 I/O space - * fe900000 f0a00000 1M PCIe #2 I/O space - * fea00000 f0b00000 1M PCIe #3 I/O space - * feb00000 f0c00000 1M PCIe #4 I/O space - * fec00000 f0d00000 1M PCIe #5 I/O space - * fed00000 f0e00000 1M PCIe #6 I/O space - * fee00000 f0f00000 1M PCIe #7 I/O space - * fef00000 f1000000 1M on-chip peripheral registers + * fee00000 f0800000 64K PCIe #0 I/O space + * fee10000 f0900000 64K PCIe #1 I/O space + * fee20000 f0a00000 64K PCIe #2 I/O space + * fee30000 f0b00000 64K PCIe #3 I/O space + * fee40000 f0c00000 64K PCIe #4 I/O space + * fee50000 f0d00000 64K PCIe #5 I/O space + * fee60000 f0e00000 64K PCIe #6 I/O space + * fee70000 f0f00000 64K PCIe #7 I/O space + * fd000000 f1000000 1M on-chip peripheral registers */ #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 -#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 +#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) +#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 #define MV78XX0_CORE_REGS_SIZE SZ_16K #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) -#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) #define MV78XX0_PCIE_IO_SIZE SZ_1M #define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE 0xfef00000 +#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000) #define MV78XX0_REGS_SIZE SZ_1M #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 @@ -59,67 +59,69 @@ * Core-specific peripheral registers. */ #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) -#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) -#define L2_WRITETHROUGH 0x00020000 -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) -#define SOFT_RESET_OUT_EN 0x00000004 -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) -#define SOFT_RESET 0x00000001 -#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) -#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) -#define BRIDGE_INT_TIMER0 0x0002 -#define BRIDGE_INT_TIMER1 0x0004 -#define BRIDGE_INT_TIMER1_CLR (~0x0004) -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) -#define IRQ_CAUSE_ERR_OFF 0x0000 -#define IRQ_CAUSE_LOW_OFF 0x0004 -#define IRQ_CAUSE_HIGH_OFF 0x0008 -#define IRQ_MASK_ERR_OFF 0x000c -#define IRQ_MASK_LOW_OFF 0x0010 -#define IRQ_MASK_HIGH_OFF 0x0014 -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) +#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE) +#define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE) +#define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE) +#define BRIDGE_WINS_SZ (0xA000) /* * Register Map */ -#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) -#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) -#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1700) - -#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) -#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) -#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) -#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) -#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) -#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200) -#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200) -#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300) -#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300) - -#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000) -#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000) - -#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000) -#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000) -#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000) -#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000) - -#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000) -#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000) -#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000) - -#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000) -#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000) - -#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000) -#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000) -#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000) -#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000) - -#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) +#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) +#define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000) +#define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500) +#define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570) +#define DDR_WINDOW_CPU_SZ (0x20) + +#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) +#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) +#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030) +#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034) +#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) +#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) +#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100) +#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) +#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) +#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) +#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) +#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200) +#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200) +#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300) +#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300) + +#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000) +#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000) + +#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000) +#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000) +#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000) +#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000) + +#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000) +#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000) +#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000) + +#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000) +#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000) + +#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000) +#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000) +#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000) +#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000) + +#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000) +/* + * Supported devices and revisions. + */ +#define MV78X00_Z0_DEV_ID 0x6381 +#define MV78X00_REV_Z0 1 + +#define MV78100_DEV_ID 0x7810 +#define MV78100_REV_A0 1 +#define MV78100_REV_A1 2 + +#define MV78200_DEV_ID 0x7820 +#define MV78200_REV_A0 1 #endif diff --git a/arch/arm/mach-mv78xx0/include/mach/system.h b/arch/arm/mach-mv78xx0/include/mach/system.h deleted file mode 100644 index 7d517940883..00000000000 --- a/arch/arm/mach-mv78xx0/include/mach/system.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/system.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -#include <mach/hardware.h> -#include <mach/mv78xx0.h> - -static inline void arch_idle(void) -{ - cpu_do_idle(); -} - -static inline void arch_reset(char mode) -{ - /* - * Enable soft reset to assert RSTOUTn. - */ - writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); - - /* - * Assert soft reset. - */ - writel(SOFT_RESET, SYSTEM_SOFT_RESET); - - while (1) - ; -} - - -#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/timex.h b/arch/arm/mach-mv78xx0/include/mach/timex.h deleted file mode 100644 index 0e8c443c723..00000000000 --- a/arch/arm/mach-mv78xx0/include/mach/timex.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/timex.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define CLOCK_TICK_RATE (100 * HZ) diff --git a/arch/arm/mach-mv78xx0/include/mach/uncompress.h b/arch/arm/mach-mv78xx0/include/mach/uncompress.h index 365264298e7..6a761c44a29 100644 --- a/arch/arm/mach-mv78xx0/include/mach/uncompress.h +++ b/arch/arm/mach-mv78xx0/include/mach/uncompress.h @@ -44,4 +44,3 @@ static void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-mv78xx0/include/mach/vmalloc.h b/arch/arm/mach-mv78xx0/include/mach/vmalloc.h deleted file mode 100644 index 1c4954386a8..00000000000 --- a/arch/arm/mach-mv78xx0/include/mach/vmalloc.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/vmalloc.h - */ - -#define VMALLOC_END 0xfe000000 diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 30b7e4bcdbc..32073444024 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c @@ -7,46 +7,34 @@ * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ - +#include <linux/gpio.h> #include <linux/kernel.h> -#include <linux/init.h> -#include <linux/pci.h> #include <linux/irq.h> -#include <asm/gpio.h> -#include <mach/mv78xx0.h> +#include <linux/io.h> +#include <mach/bridge-regs.h> +#include <plat/orion-gpio.h> #include <plat/irq.h> #include "common.h" -static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - BUG_ON(irq < IRQ_MV78XX0_GPIO_0_7 || irq > IRQ_MV78XX0_GPIO_24_31); - - orion_gpio_irq_handler((irq - IRQ_MV78XX0_GPIO_0_7) << 3); -} +static int __initdata gpio0_irqs[4] = { + IRQ_MV78XX0_GPIO_0_7, + IRQ_MV78XX0_GPIO_8_15, + IRQ_MV78XX0_GPIO_16_23, + IRQ_MV78XX0_GPIO_24_31, +}; void __init mv78xx0_init_irq(void) { - int i; - - orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); - orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); - orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); + orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); + orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); + orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF); /* - * Mask and clear GPIO IRQ interrupts. + * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask + * registers for core #1 are at an offset of 0x18 from those of + * core #0.) */ - writel(0, GPIO_LEVEL_MASK(0)); - writel(0, GPIO_EDGE_MASK(0)); - writel(0, GPIO_EDGE_CAUSE(0)); - - for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) { - set_irq_chip(i, &orion_gpio_irq_chip); - set_irq_handler(i, handle_level_irq); - irq_desc[i].status |= IRQ_LEVEL; - set_irq_flags(i, IRQF_VALID); - } - set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); - set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); - set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); - set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); + orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, + mv78xx0_core_index() ? 0x18 : 0, + IRQ_MV78XX0_GPIO_START, gpio0_irqs); } diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c new file mode 100644 index 00000000000..df50342179e --- /dev/null +++ b/arch/arm/mach-mv78xx0/mpp.c @@ -0,0 +1,37 @@ +/* + * arch/arm/mach-mv78x00/mpp.c + * + * MPP functions for Marvell MV78x00 SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include <linux/gpio.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <plat/mpp.h> +#include <mach/hardware.h> +#include "common.h" +#include "mpp.h" + +static unsigned int __init mv78xx0_variant(void) +{ + u32 dev, rev; + + mv78xx0_pcie_id(&dev, &rev); + + if (dev == MV78100_DEV_ID && rev >= MV78100_REV_A0) + return MPP_78100_A0_MASK; + + printk(KERN_ERR "MPP setup: unknown mv78x00 variant " + "(dev %#x rev %#x)\n", dev, rev); + return 0; +} + +void __init mv78xx0_mpp_conf(unsigned int *mpp_list) +{ + orion_mpp_conf(mpp_list, mv78xx0_variant(), + MPP_MAX, DEV_BUS_VIRT_BASE); +} diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h new file mode 100644 index 00000000000..3752302ae2e --- /dev/null +++ b/arch/arm/mach-mv78xx0/mpp.h @@ -0,0 +1,341 @@ +/* + * linux/arch/arm/mach-mv78xx0/mpp.h -- Multi Purpose Pins + * + * + * sebastien requiem <sebastien@requiem.fr> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MV78X00_MPP_H +#define __MV78X00_MPP_H + +#define MPP(_num, _sel, _in, _out, _78100_A0) (\ + /* MPP number */ ((_num) & 0xff) | \ + /* MPP select value */ (((_sel) & 0xf) << 8) | \ + /* may be input signal */ ((!!(_in)) << 12) | \ + /* may be output signal */ ((!!(_out)) << 13) | \ + /* available on A0 */ ((!!(_78100_A0)) << 14)) + + /* num sel i o 78100_A0 */ + +#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) + +#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) +#define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1) +#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1) +#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1) + +#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1) +#define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1) +#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1) +#define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1) + +#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1) +#define MPP2_GE0_CRS MPP(2, 0x1, 0, 0, 1) +#define MPP2_GE1_RXCTL MPP(2, 0x2, 0, 0, 1) +#define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1) + +#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1) +#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 0, 1) +#define MPP3_GE1_RXCLK MPP(3, 0x2, 0, 0, 1) +#define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1) + +#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1) +#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 0, 1) +#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 0, 1) +#define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1) + +#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1) +#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 0, 1) +#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 0, 1) +#define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1) + +#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1) +#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 0, 1) +#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 0, 1) +#define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1) + +#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1) +#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 0, 1) +#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 0, 1) +#define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1) + +#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1) +#define MPP8_GE0_RXD4 MPP(8, 0x1, 0, 0, 1) +#define MPP8_GE1_RXD0 MPP(8, 0x2, 0, 0, 1) +#define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1) + +#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1) +#define MPP9_GE0_RXD5 MPP(9, 0x1, 0, 0, 1) +#define MPP9_GE1_RXD1 MPP(9, 0x2, 0, 0, 1) +#define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1) + +#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1) +#define MPP10_GE0_RXD6 MPP(10, 0x1, 0, 0, 1) +#define MPP10_GE1_RXD2 MPP(10, 0x2, 0, 0, 1) +#define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1) + +#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1) +#define MPP11_GE0_RXD7 MPP(11, 0x1, 0, 0, 1) +#define MPP11_GE1_RXD3 MPP(11, 0x2, 0, 0, 1) +#define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1) + +#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1) +#define MPP12_M_BB MPP(12, 0x3, 0, 0, 1) +#define MPP12_UA0_CTSn MPP(12, 0x4, 0, 0, 1) +#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 0, 1) +#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 0, 1) +#define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1) + +#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1) +#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 0, 1) +#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 0, 1) +#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 0, 1) +#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 0, 1) +#define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1) + +#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1) +#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 0, 1) +#define MPP14_UA1_CTSn MPP(14, 0x4, 0, 0, 1) +#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 0, 1) +#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 0, 1) +#define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1) + +#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1) +#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 0, 1) +#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 0, 1) +#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 0, 1) +#define MPP15_TDM_SMISO MPP(15, 0x6, 0, 0, 1) +#define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1) + +#define MPP16_GPIO MPP(16, 0x0, 1, 1, 1) +#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 0, 1) +#define MPP16_UA2_TXD MPP(16, 0x4, 0, 0, 1) +#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 0, 1) +#define MPP16_TDM_INTn MPP(16, 0x6, 0, 0, 1) +#define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1) + + +#define MPP17_GPIO MPP(17, 0x0, 1, 1, 1) +#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 0, 1) +#define MPP17_UA2_RXD MPP(17, 0x4, 0, 0, 1) +#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 0, 1) +#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 0, 1) +#define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1) + + +#define MPP18_GPIO MPP(18, 0x0, 1, 1, 1) +#define MPP18_UA0_CTSn MPP(18, 0x4, 0, 0, 1) +#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 0, 1) +#define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1) + + + +#define MPP19_GPIO MPP(19, 0x0, 1, 1, 1) +#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 0, 1) +#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 0, 1) +#define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1) + + +#define MPP20_GPIO MPP(20, 0x0, 1, 1, 1) +#define MPP20_UA1_CTSs MPP(20, 0x4, 0, 0, 1) +#define MPP20_TDM_PCLK MPP(20, 0x6, 0, 0, 0) +#define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1) + + + +#define MPP21_GPIO MPP(21, 0x0, 1, 1, 1) +#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 0, 1) +#define MPP21_TDM_FSYNC MPP(21, 0x6, 0, 0, 0) +#define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1) + + + +#define MPP22_GPIO MPP(22, 0x0, 1, 1, 1) +#define MPP22_UA3_TDX MPP(22, 0x4, 0, 0, 1) +#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 0, 1) +#define MPP22_TDM_DRX MPP(22, 0x6, 0, 0, 1) +#define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1) + + + +#define MPP23_GPIO MPP(23, 0x0, 1, 1, 1) +#define MPP23_UA3_RDX MPP(23, 0x4, 0, 0, 1) +#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 0, 1) +#define MPP23_TDM_DTX MPP(23, 0x6, 0, 0, 1) +#define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1) + + +#define MPP24_GPIO MPP(24, 0x0, 1, 1, 1) +#define MPP24_UA2_TXD MPP(24, 0x4, 0, 0, 1) +#define MPP24_TDM_INTn MPP(24, 0x6, 0, 0, 1) +#define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1) + + +#define MPP25_GPIO MPP(25, 0x0, 1, 1, 1) +#define MPP25_UA2_RXD MPP(25, 0x4, 0, 0, 1) +#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 0, 1) +#define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1) + + +#define MPP26_GPIO MPP(26, 0x0, 1, 1, 1) +#define MPP26_UA2_CTSn MPP(26, 0x4, 0, 0, 1) +#define MPP26_TDM_PCLK MPP(26, 0x6, 0, 0, 1) +#define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1) + + +#define MPP27_GPIO MPP(27, 0x0, 1, 1, 1) +#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 0, 1) +#define MPP27_TDM_FSYNC MPP(27, 0x6, 0, 0, 1) +#define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1) + + +#define MPP28_GPIO MPP(28, 0x0, 1, 1, 1) +#define MPP28_UA3_TXD MPP(28, 0x4, 0, 0, 1) +#define MPP28_TDM_DRX MPP(28, 0x6, 0, 0, 1) +#define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1) + +#define MPP29_GPIO MPP(29, 0x0, 1, 1, 1) +#define MPP29_UA3_RXD MPP(29, 0x4, 0, 0, 1) +#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 0, 1) +#define MPP29_TDM_DTX MPP(29, 0x6, 0, 0, 1) +#define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1) + +#define MPP30_GPIO MPP(30, 0x0, 1, 1, 1) +#define MPP30_UA3_CTSn MPP(30, 0x4, 0, 0, 1) +#define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1) + +#define MPP31_GPIO MPP(31, 0x0, 1, 1, 1) +#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 0, 1) +#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 0, 1) +#define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1) + + +#define MPP32_GPIO MPP(32, 0x1, 1, 1, 1) +#define MPP32_UA3_TDX MPP(32, 0x4, 0, 0, 1) +#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 0, 1) +#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 0, 1) +#define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1) + + +#define MPP33_GPIO MPP(33, 0x1, 1, 1, 1) +#define MPP33_UA3_RDX MPP(33, 0x4, 0, 0, 1) +#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 0, 1) +#define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1) + + + +#define MPP34_GPIO MPP(34, 0x1, 1, 1, 1) +#define MPP34_UA2_TDX MPP(34, 0x4, 0, 0, 1) +#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 0, 1) +#define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1) + + + +#define MPP35_GPIO MPP(35, 0x1, 1, 1, 1) +#define MPP35_UA2_RDX MPP(35, 0x4, 0, 0, 1) +#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 0, 1) +#define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1) + +#define MPP36_GPIO MPP(36, 0x1, 1, 1, 1) +#define MPP36_UA0_CTSn MPP(36, 0x2, 0, 0, 1) +#define MPP36_UA2_TDX MPP(36, 0x4, 0, 0, 1) +#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 0, 1) +#define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1) + + +#define MPP37_GPIO MPP(37, 0x1, 1, 1, 1) +#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 0, 1) +#define MPP37_UA2_RXD MPP(37, 0x4, 0, 0, 1) +#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 0, 1) +#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 0, 1) +#define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1) + + + + +#define MPP38_GPIO MPP(38, 0x1, 1, 1, 1) +#define MPP38_UA1_CTSn MPP(38, 0x2, 0, 0, 1) +#define MPP38_UA3_TXD MPP(38, 0x4, 0, 0, 1) +#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 0, 1) +#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 0, 1) +#define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1) + + + + +#define MPP39_GPIO MPP(39, 0x1, 1, 1, 1) +#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 0, 1) +#define MPP39_UA3_RXD MPP(39, 0x4, 0, 0, 1) +#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 0, 1) +#define MPP39_TDM_SMISO MPP(39, 0x6, 0, 0, 1) +#define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1) + + + +#define MPP40_GPIO MPP(40, 0x1, 1, 1, 1) +#define MPP40_TDM_INTn MPP(40, 0x6, 0, 0, 1) +#define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1) + + + +#define MPP41_GPIO MPP(41, 0x1, 1, 1, 1) +#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 0, 1) +#define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1) + + + +#define MPP42_GPIO MPP(42, 0x1, 1, 1, 1) +#define MPP42_TDM_PCLK MPP(42, 0x6, 0, 0, 1) +#define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1) + + + +#define MPP43_GPIO MPP(43, 0x1, 1, 1, 1) +#define MPP43_TDM_FSYNC MPP(43, 0x6, 0, 0, 1) +#define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1) + + + +#define MPP44_GPIO MPP(44, 0x1, 1, 1, 1) +#define MPP44_TDM_DRX MPP(44, 0x6, 0, 0, 1) +#define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1) + + + +#define MPP45_GPIO MPP(45, 0x1, 1, 1, 1) +#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 0, 1) +#define MPP45_TDM_DRX MPP(45, 0x6, 0, 0, 1) +#define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1) + + +#define MPP46_GPIO MPP(46, 0x1, 1, 1, 1) +#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 0, 1) +#define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1) + + +#define MPP47_GPIO MPP(47, 0x1, 1, 1, 1) +#define MPP47_UNUSED MPP(47, 0x0, 0, 0, 1) + + + +#define MPP48_GPIO MPP(48, 0x1, 1, 1, 1) +#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 0, 1) +#define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1) + + + +#define MPP49_GPIO MPP(49, 0x1, 1, 1, 1) +#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 0, 1) +#define MPP49_M_BB MPP(49, 0x4, 0, 0, 1) +#define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1) + + +#define MPP_MAX 49 + +void mv78xx0_mpp_conf(unsigned int *mpp_list); + +#endif diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index aad3a7a2f83..445e553f4a2 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -11,124 +11,90 @@ #include <linux/kernel.h> #include <linux/pci.h> #include <linux/mbus.h> +#include <video/vga.h> #include <asm/irq.h> #include <asm/mach/pci.h> #include <plat/pcie.h> +#include <mach/mv78xx0.h> #include "common.h" +#define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4) +#define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane))) +#define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4) +#define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane))) + struct pcie_port { u8 maj; u8 min; u8 root_bus_nr; void __iomem *base; spinlock_t conf_lock; - char io_space_name[16]; char mem_space_name[16]; - struct resource res[2]; + struct resource res; }; static struct pcie_port pcie_port[8]; static int num_pcie_ports; static struct resource pcie_io_space; -static struct resource pcie_mem_space; +void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) +{ + *dev = orion_pcie_dev_id(PCIE00_VIRT_BASE); + *rev = orion_pcie_rev(PCIE00_VIRT_BASE); +} + +u32 pcie_port_size[8] = { + 0, + 0x30000000, + 0x10000000, + 0x10000000, + 0x08000000, + 0x08000000, + 0x08000000, + 0x04000000, +}; static void __init mv78xx0_pcie_preinit(void) { int i; u32 size_each; u32 start; - int win; pcie_io_space.name = "PCIe I/O Space"; pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0); pcie_io_space.end = MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1; - pcie_io_space.flags = IORESOURCE_IO; + pcie_io_space.flags = IORESOURCE_MEM; if (request_resource(&iomem_resource, &pcie_io_space)) panic("can't allocate PCIe I/O space"); - pcie_mem_space.name = "PCIe MEM Space"; - pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE; - pcie_mem_space.end = - MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1; - pcie_mem_space.flags = IORESOURCE_MEM; - if (request_resource(&iomem_resource, &pcie_mem_space)) - panic("can't allocate PCIe MEM space"); + if (num_pcie_ports > 7) + panic("invalid number of PCIe ports"); + size_each = pcie_port_size[num_pcie_ports]; + + start = MV78XX0_PCIE_MEM_PHYS_BASE; for (i = 0; i < num_pcie_ports; i++) { struct pcie_port *pp = pcie_port + i; - snprintf(pp->io_space_name, sizeof(pp->io_space_name), - "PCIe %d.%d I/O", pp->maj, pp->min); - pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; - pp->res[0].name = pp->io_space_name; - pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i); - pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1; - pp->res[0].flags = IORESOURCE_IO; - snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d.%d MEM", pp->maj, pp->min); pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res[1].name = pp->mem_space_name; - pp->res[1].flags = IORESOURCE_MEM; - } - - switch (num_pcie_ports) { - case 0: - size_each = 0; - break; - - case 1: - size_each = 0x30000000; - break; - - case 2 ... 3: - size_each = 0x10000000; - break; - - case 4 ... 6: - size_each = 0x08000000; - break; - - case 7: - size_each = 0x04000000; - break; - - default: - panic("invalid number of PCIe ports"); - } - - start = MV78XX0_PCIE_MEM_PHYS_BASE; - for (i = 0; i < num_pcie_ports; i++) { - struct pcie_port *pp = pcie_port + i; - - pp->res[1].start = start; - pp->res[1].end = start + size_each - 1; + pp->res.name = pp->mem_space_name; + pp->res.flags = IORESOURCE_MEM; + pp->res.start = start; + pp->res.end = start + size_each - 1; start += size_each; - } - - for (i = 0; i < num_pcie_ports; i++) { - struct pcie_port *pp = pcie_port + i; - if (request_resource(&pcie_io_space, &pp->res[0])) - panic("can't allocate PCIe I/O sub-space"); - - if (request_resource(&pcie_mem_space, &pp->res[1])) + if (request_resource(&iomem_resource, &pp->res)) panic("can't allocate PCIe MEM sub-space"); - } - - win = 0; - for (i = 0; i < num_pcie_ports; i++) { - struct pcie_port *pp = pcie_port + i; - mv78xx0_setup_pcie_io_win(win++, pp->res[0].start, - pp->res[0].end - pp->res[0].start + 1, - pp->maj, pp->min); - - mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start, - pp->res[1].end - pp->res[1].start + 1, - pp->maj, pp->min); + mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min), + MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min), + pp->res.start, resource_size(&pp->res)); + mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min), + MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min), + i * SZ_64K, SZ_64K, 0); } } @@ -140,32 +106,20 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) return 0; pp = &pcie_port[nr]; + sys->private_data = pp; pp->root_bus_nr = sys->busnr; /* * Generic PCIe unit setup. */ orion_pcie_set_local_bus_nr(pp->base, sys->busnr); - orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info); - - sys->resource[0] = &pp->res[0]; - sys->resource[1] = &pp->res[1]; - sys->resource[2] = NULL; - - return 1; -} + orion_pcie_setup(pp->base); -static struct pcie_port *bus_to_port(int bus) -{ - int i; + pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr)); - for (i = num_pcie_ports - 1; i >= 0; i--) { - int rbus = pcie_port[i].root_bus_nr; - if (rbus != -1 && rbus <= bus) - break; - } + pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); - return i >= 0 ? pcie_port + i : NULL; + return 1; } static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) @@ -183,7 +137,8 @@ static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - struct pcie_port *pp = bus_to_port(bus->number); + struct pci_sys_data *sys = bus->sysdata; + struct pcie_port *pp = sys->private_data; unsigned long flags; int ret; @@ -202,7 +157,8 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - struct pcie_port *pp = bus_to_port(bus->number); + struct pci_sys_data *sys = bus->sysdata; + struct pcie_port *pp = sys->private_data; unsigned long flags; int ret; @@ -221,7 +177,7 @@ static struct pci_ops pcie_ops = { .write = pcie_wr_conf, }; -static void __devinit rc_pci_fixup(struct pci_dev *dev) +static void rc_pci_fixup(struct pci_dev *dev) { /* * Prevent enumeration of root complex. @@ -244,7 +200,8 @@ mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys) struct pci_bus *bus; if (nr < num_pcie_ports) { - bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); + bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, + &sys->resources); } else { bus = NULL; BUG(); @@ -253,9 +210,11 @@ mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys) return bus; } -static int __init mv78xx0_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot, + u8 pin) { - struct pcie_port *pp = bus_to_port(dev->bus->number); + struct pci_sys_data *sys = dev->bus->sysdata; + struct pcie_port *pp = sys->private_data; return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min; } @@ -263,17 +222,16 @@ static int __init mv78xx0_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci mv78xx0_pci __initdata = { .nr_controllers = 8, .preinit = mv78xx0_pcie_preinit, - .swizzle = pci_std_swizzle, .setup = mv78xx0_pcie_setup, .scan = mv78xx0_pcie_scan_bus, .map_irq = mv78xx0_pcie_map_irq, }; -static void __init add_pcie_port(int maj, int min, unsigned long base) +static void __init add_pcie_port(int maj, int min, void __iomem *base) { printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min); - if (orion_pcie_link_up((void __iomem *)base)) { + if (orion_pcie_link_up(base)) { struct pcie_port *pp = &pcie_port[num_pcie_ports++]; printk("link up\n"); @@ -281,9 +239,9 @@ static void __init add_pcie_port(int maj, int min, unsigned long base) pp->maj = maj; pp->min = min; pp->root_bus_nr = -1; - pp->base = (void __iomem *)base; + pp->base = base; spin_lock_init(&pp->conf_lock); - memset(pp->res, 0, sizeof(pp->res)); + memset(&pp->res, 0, sizeof(pp->res)); } else { printk("link down, ignoring\n"); } @@ -291,9 +249,11 @@ static void __init add_pcie_port(int maj, int min, unsigned long base) void __init mv78xx0_pcie_init(int init_port0, int init_port1) { + vga_base = MV78XX0_PCIE_MEM_PHYS_BASE; + if (init_port0) { add_pcie_port(0, 0, PCIE00_VIRT_BASE); - if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) { + if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) { add_pcie_port(0, 1, PCIE01_VIRT_BASE); add_pcie_port(0, 2, PCIE02_VIRT_BASE); add_pcie_port(0, 3, PCIE03_VIRT_BASE); diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c new file mode 100644 index 00000000000..d2d06f3957f --- /dev/null +++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c @@ -0,0 +1,88 @@ +/* + * arch/arm/mach-mv78x00/rd78x00-masa-setup.c + * + * Marvell RD-78x00-mASA Development Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/ata_platform.h> +#include <linux/mv643xx_eth.h> +#include <linux/ethtool.h> +#include <mach/mv78xx0.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include "common.h" + +static struct mv643xx_eth_platform_data rd78x00_masa_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(8), +}; + +static struct mv643xx_eth_platform_data rd78x00_masa_ge01_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(9), +}; + +static struct mv643xx_eth_platform_data rd78x00_masa_ge10_data = { +}; + +static struct mv643xx_eth_platform_data rd78x00_masa_ge11_data = { +}; + +static struct mv_sata_platform_data rd78x00_masa_sata_data = { + .n_ports = 2, +}; + +static void __init rd78x00_masa_init(void) +{ + /* + * Basic MV78x00 setup. Needs to be called early. + */ + mv78xx0_init(); + + /* + * Partition on-chip peripherals between the two CPU cores. + */ + if (mv78xx0_core_index() == 0) { + mv78xx0_ehci0_init(); + mv78xx0_ehci1_init(); + mv78xx0_ge00_init(&rd78x00_masa_ge00_data); + mv78xx0_ge10_init(&rd78x00_masa_ge10_data); + mv78xx0_sata_init(&rd78x00_masa_sata_data); + mv78xx0_uart0_init(); + mv78xx0_uart2_init(); + } else { + mv78xx0_ehci2_init(); + mv78xx0_ge01_init(&rd78x00_masa_ge01_data); + mv78xx0_ge11_init(&rd78x00_masa_ge11_data); + mv78xx0_uart1_init(); + mv78xx0_uart3_init(); + } +} + +static int __init rd78x00_pci_init(void) +{ + /* + * Assign all PCIe devices to CPU core #0. + */ + if (machine_is_rd78x00_masa() && mv78xx0_core_index() == 0) + mv78xx0_pcie_init(1, 1); + + return 0; +} +subsys_initcall(rd78x00_pci_init); + +MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board") + /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ + .atag_offset = 0x100, + .init_machine = rd78x00_masa_init, + .map_io = mv78xx0_map_io, + .init_early = mv78xx0_init_early, + .init_irq = mv78xx0_init_irq, + .init_time = mv78xx0_timer_init, + .restart = mv78xx0_restart, +MACHINE_END |