aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/mach-kirkwood/pcie.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-kirkwood/pcie.c')
-rw-r--r--arch/arm/mach-kirkwood/pcie.c131
1 files changed, 64 insertions, 67 deletions
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 6e8b2efa3c3..12d86f39f38 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -12,21 +12,31 @@
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/clk.h>
+#include <linux/mbus.h>
#include <video/vga.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include <mach/bridge-regs.h>
-#include <plat/addr-map.h>
#include "common.h"
+/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
+#define KIRKWOOD_MBUS_PCIE0_MEM_TARGET 0x4
+#define KIRKWOOD_MBUS_PCIE0_MEM_ATTR 0xe8
+#define KIRKWOOD_MBUS_PCIE0_IO_TARGET 0x4
+#define KIRKWOOD_MBUS_PCIE0_IO_ATTR 0xe0
+#define KIRKWOOD_MBUS_PCIE1_MEM_TARGET 0x4
+#define KIRKWOOD_MBUS_PCIE1_MEM_ATTR 0xd8
+#define KIRKWOOD_MBUS_PCIE1_IO_TARGET 0x4
+#define KIRKWOOD_MBUS_PCIE1_IO_ATTR 0xd0
+
static void kirkwood_enable_pcie_clk(const char *port)
{
struct clk *clk;
clk = clk_get_sys("pcie", port);
if (IS_ERR(clk)) {
- printk(KERN_ERR "PCIE clock %s missing\n", port);
+ pr_err("PCIE clock %s missing\n", port);
return;
}
clk_prepare_enable(clk);
@@ -47,8 +57,8 @@ void kirkwood_enable_pcie(void)
void kirkwood_pcie_id(u32 *dev, u32 *rev)
{
kirkwood_enable_pcie();
- *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
- *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
+ *dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
+ *rev = orion_pcie_rev(PCIE_VIRT_BASE);
}
struct pcie_port {
@@ -56,7 +66,7 @@ struct pcie_port {
void __iomem *base;
spinlock_t conf_lock;
int irq;
- struct resource res[2];
+ struct resource res;
};
static int pcie_port_map[2];
@@ -133,46 +143,30 @@ static struct pci_ops pcie_ops = {
static void __init pcie0_ioresources_init(struct pcie_port *pp)
{
- pp->base = (void __iomem *)PCIE_VIRT_BASE;
+ pp->base = PCIE_VIRT_BASE;
pp->irq = IRQ_KIRKWOOD_PCIE;
/*
- * IORESOURCE_IO
- */
- pp->res[0].name = "PCIe 0 I/O Space";
- pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
- pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
- pp->res[0].flags = IORESOURCE_IO;
-
- /*
* IORESOURCE_MEM
*/
- pp->res[1].name = "PCIe 0 MEM";
- pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
- pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
- pp->res[1].flags = IORESOURCE_MEM;
+ pp->res.name = "PCIe 0 MEM";
+ pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+ pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+ pp->res.flags = IORESOURCE_MEM;
}
static void __init pcie1_ioresources_init(struct pcie_port *pp)
{
- pp->base = (void __iomem *)PCIE1_VIRT_BASE;
+ pp->base = PCIE1_VIRT_BASE;
pp->irq = IRQ_KIRKWOOD_PCIE1;
/*
- * IORESOURCE_IO
- */
- pp->res[0].name = "PCIe 1 I/O Space";
- pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
- pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
- pp->res[0].flags = IORESOURCE_IO;
-
- /*
* IORESOURCE_MEM
*/
- pp->res[1].name = "PCIe 1 MEM";
- pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
- pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
- pp->res[1].flags = IORESOURCE_MEM;
+ pp->res.name = "PCIe 1 MEM";
+ pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
+ pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
+ pp->res.flags = IORESOURCE_MEM;
}
static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
@@ -184,7 +178,7 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
return 0;
index = pcie_port_map[nr];
- printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
+ pr_info("PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
pp = kzalloc(sizeof(*pp), GFP_KERNEL);
if (!pp)
@@ -197,23 +191,22 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
case 0:
kirkwood_enable_pcie_clk("0");
pcie0_ioresources_init(pp);
+ pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
break;
case 1:
kirkwood_enable_pcie_clk("1");
pcie1_ioresources_init(pp);
+ pci_ioremap_io(SZ_64K * sys->busnr,
+ KIRKWOOD_PCIE1_IO_PHYS_BASE);
break;
default:
panic("PCIe setup: invalid controller %d", index);
}
- if (request_resource(&ioport_resource, &pp->res[0]))
- panic("Request PCIe%d IO resource failed\n", index);
- if (request_resource(&iomem_resource, &pp->res[1]))
+ if (request_resource(&iomem_resource, &pp->res))
panic("Request PCIe%d Memory resource failed\n", index);
- sys->io_offset = 0;
- pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
- pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+ pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
/*
* Generic PCIe unit setup.
@@ -225,14 +218,19 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
return 1;
}
-static void __devinit rc_pci_fixup(struct pci_dev *dev)
+/*
+ * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
+ * is operating as a root complex this needs to be switched to
+ * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
+ * the device. Decoding setup is handled by the orion code.
+ */
+static void rc_pci_fixup(struct pci_dev *dev)
{
- /*
- * Prevent enumeration of root complex.
- */
if (dev->bus->parent == NULL && dev->devfn == 0) {
int i;
+ dev->class &= 0xff;
+ dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
dev->resource[i].start = 0;
dev->resource[i].end = 0;
@@ -242,22 +240,6 @@ static void __devinit rc_pci_fixup(struct pci_dev *dev)
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
-static struct pci_bus __init *
-kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
-{
- struct pci_bus *bus;
-
- if (nr < num_pcie_ports) {
- bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
- &sys->resources);
- } else {
- bus = NULL;
- BUG();
- }
-
- return bus;
-}
-
static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
@@ -269,23 +251,38 @@ static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
static struct hw_pci kirkwood_pci __initdata = {
.setup = kirkwood_pcie_setup,
- .scan = kirkwood_pcie_scan_bus,
.map_irq = kirkwood_pcie_map_irq,
+ .ops = &pcie_ops,
};
-static void __init add_pcie_port(int index, unsigned long base)
+static void __init add_pcie_port(int index, void __iomem *base)
{
- printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
-
- if (orion_pcie_link_up((void __iomem *)base)) {
- printk(KERN_INFO "link up\n");
- pcie_port_map[num_pcie_ports++] = index;
- } else
- printk(KERN_INFO "link down, ignoring\n");
+ pcie_port_map[num_pcie_ports++] = index;
+ pr_info("Kirkwood PCIe port %d: link %s\n", index,
+ orion_pcie_link_up(base) ? "up" : "down");
}
void __init kirkwood_pcie_init(unsigned int portmask)
{
+ mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE0_IO_TARGET,
+ KIRKWOOD_MBUS_PCIE0_IO_ATTR,
+ KIRKWOOD_PCIE_IO_PHYS_BASE,
+ KIRKWOOD_PCIE_IO_SIZE,
+ KIRKWOOD_PCIE_IO_BUS_BASE);
+ mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE0_MEM_TARGET,
+ KIRKWOOD_MBUS_PCIE0_MEM_ATTR,
+ KIRKWOOD_PCIE_MEM_PHYS_BASE,
+ KIRKWOOD_PCIE_MEM_SIZE);
+ mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE1_IO_TARGET,
+ KIRKWOOD_MBUS_PCIE1_IO_ATTR,
+ KIRKWOOD_PCIE1_IO_PHYS_BASE,
+ KIRKWOOD_PCIE1_IO_SIZE,
+ KIRKWOOD_PCIE1_IO_BUS_BASE);
+ mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE1_MEM_TARGET,
+ KIRKWOOD_MBUS_PCIE1_MEM_ATTR,
+ KIRKWOOD_PCIE1_MEM_PHYS_BASE,
+ KIRKWOOD_PCIE1_MEM_SIZE);
+
vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
if (portmask & KW_PCIE0)
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-11-10 16:30:18 +0000