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Diffstat (limited to 'arch/arm/mach-ixp4xx/ixdp425-setup.c')
-rw-r--r--arch/arm/mach-ixp4xx/ixdp425-setup.c118
1 files changed, 78 insertions, 40 deletions
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index d5008d8fc9a..e7b8befa872 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -1,7 +1,7 @@
/*
* arch/arm/mach-ixp4xx/ixdp425-setup.c
*
- * IXDP425/IXCDP1100 board-setup
+ * IXDP425/IXCDP1100 board-setup
*
* Copyright (C) 2003-2005 MontaVista Software, Inc.
*
@@ -14,21 +14,30 @@
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
-#include <linux/slab.h>
+#include <linux/i2c-gpio.h>
#include <linux/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
-
+#include <linux/delay.h>
+#include <linux/gpio.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
-#include <asm/hardware.h>
+#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
-#include <asm/delay.h>
+
+#define IXDP425_SDA_PIN 7
+#define IXDP425_SCL_PIN 6
+
+/* NAND Flash pins */
+#define IXDP425_NAND_NCE_PIN 12
+
+#define IXDP425_NAND_CMD_BYTE 0x01
+#define IXDP425_NAND_ADDR_BYTE 0x02
static struct flash_platform_data ixdp425_flash_data = {
.map_name = "cfi_probe",
@@ -52,9 +61,6 @@ static struct platform_device ixdp425_flash = {
#if defined(CONFIG_MTD_NAND_PLATFORM) || \
defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
-#ifdef CONFIG_MTD_PARTITIONS
-const char *part_probes[] = { "cmdlinepart", NULL };
-
static struct mtd_partition ixdp425_partitions[] = {
{
.name = "ixp400 NAND FS 0",
@@ -66,7 +72,6 @@ static struct mtd_partition ixdp425_partitions[] = {
.size = MTDPART_SIZ_FULL
},
};
-#endif
static void
ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
@@ -76,10 +81,10 @@ ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
if (ctrl & NAND_CTRL_CHANGE) {
if (ctrl & NAND_NCE) {
- gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_LOW);
+ gpio_set_value(IXDP425_NAND_NCE_PIN, 0);
udelay(5);
} else
- gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_HIGH);
+ gpio_set_value(IXDP425_NAND_NCE_PIN, 1);
offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0;
offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0;
@@ -92,13 +97,10 @@ ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
static struct platform_nand_data ixdp425_flash_nand_data = {
.chip = {
+ .nr_chips = 1,
.chip_delay = 30,
- .options = NAND_NO_AUTOINCR,
-#ifdef CONFIG_MTD_PARTITIONS
- .part_probe_types = part_probes,
.partitions = ixdp425_partitions,
.nr_partitions = ARRAY_SIZE(ixdp425_partitions),
-#endif
},
.ctrl = {
.cmd_ctrl = ixdp425_flash_nand_cmd_ctrl
@@ -120,18 +122,17 @@ static struct platform_device ixdp425_flash_nand = {
};
#endif /* CONFIG_MTD_NAND_PLATFORM */
-static struct ixp4xx_i2c_pins ixdp425_i2c_gpio_pins = {
+static struct i2c_gpio_platform_data ixdp425_i2c_gpio_data = {
.sda_pin = IXDP425_SDA_PIN,
.scl_pin = IXDP425_SCL_PIN,
};
-static struct platform_device ixdp425_i2c_controller = {
- .name = "IXP4XX-I2C",
+static struct platform_device ixdp425_i2c_gpio = {
+ .name = "i2c-gpio",
.id = 0,
- .dev = {
- .platform_data = &ixdp425_i2c_gpio_pins,
+ .dev = {
+ .platform_data = &ixdp425_i2c_gpio_data,
},
- .num_resources = 0
};
static struct resource ixdp425_uart_resources[] = {
@@ -177,14 +178,41 @@ static struct platform_device ixdp425_uart = {
.resource = ixdp425_uart_resources
};
+/* Built-in 10/100 Ethernet MAC interfaces */
+static struct eth_plat_info ixdp425_plat_eth[] = {
+ {
+ .phy = 0,
+ .rxq = 3,
+ .txreadyq = 20,
+ }, {
+ .phy = 1,
+ .rxq = 4,
+ .txreadyq = 21,
+ }
+};
+
+static struct platform_device ixdp425_eth[] = {
+ {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEB,
+ .dev.platform_data = ixdp425_plat_eth,
+ }, {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEC,
+ .dev.platform_data = ixdp425_plat_eth + 1,
+ }
+};
+
static struct platform_device *ixdp425_devices[] __initdata = {
- &ixdp425_i2c_controller,
+ &ixdp425_i2c_gpio,
&ixdp425_flash,
#if defined(CONFIG_MTD_NAND_PLATFORM) || \
defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
&ixdp425_flash_nand,
#endif
- &ixdp425_uart
+ &ixdp425_uart,
+ &ixdp425_eth[0],
+ &ixdp425_eth[1],
};
static void __init ixdp425_init(void)
@@ -200,7 +228,8 @@ static void __init ixdp425_init(void)
ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3),
ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1;
- gpio_line_config(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_OUT);
+ gpio_request(IXDP425_NAND_NCE_PIN, "NAND NCE pin");
+ gpio_direction_output(IXDP425_NAND_NCE_PIN, 0);
/* Configure expansion bus for NAND Flash */
*IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN |
@@ -222,51 +251,60 @@ static void __init ixdp425_init(void)
#ifdef CONFIG_ARCH_IXDP425
MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
/* Maintainer: MontaVista Software, Inc. */
- .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
- .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
.map_io = ixp4xx_map_io,
+ .init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
- .timer = &ixp4xx_timer,
- .boot_params = 0x0100,
+ .init_time = ixp4xx_timer_init,
+ .atag_offset = 0x100,
.init_machine = ixdp425_init,
+#if defined(CONFIG_PCI)
+ .dma_zone_size = SZ_64M,
+#endif
+ .restart = ixp4xx_restart,
MACHINE_END
#endif
#ifdef CONFIG_MACH_IXDP465
MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
/* Maintainer: MontaVista Software, Inc. */
- .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
- .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
.map_io = ixp4xx_map_io,
+ .init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
- .timer = &ixp4xx_timer,
- .boot_params = 0x0100,
+ .init_time = ixp4xx_timer_init,
+ .atag_offset = 0x100,
.init_machine = ixdp425_init,
+#if defined(CONFIG_PCI)
+ .dma_zone_size = SZ_64M,
+#endif
MACHINE_END
#endif
#ifdef CONFIG_ARCH_PRPMC1100
MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
/* Maintainer: MontaVista Software, Inc. */
- .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
- .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
.map_io = ixp4xx_map_io,
+ .init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
- .timer = &ixp4xx_timer,
- .boot_params = 0x0100,
+ .init_time = ixp4xx_timer_init,
+ .atag_offset = 0x100,
.init_machine = ixdp425_init,
+#if defined(CONFIG_PCI)
+ .dma_zone_size = SZ_64M,
+#endif
MACHINE_END
#endif
#ifdef CONFIG_MACH_KIXRP435
MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
/* Maintainer: MontaVista Software, Inc. */
- .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
- .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
.map_io = ixp4xx_map_io,
+ .init_early = ixp4xx_init_early,
.init_irq = ixp4xx_init_irq,
- .timer = &ixp4xx_timer,
- .boot_params = 0x0100,
+ .init_time = ixp4xx_timer_init,
+ .atag_offset = 0x100,
.init_machine = ixdp425_init,
+#if defined(CONFIG_PCI)
+ .dma_zone_size = SZ_64M,
+#endif
MACHINE_END
#endif
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-12-20 13:11:29 +0000