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Diffstat (limited to 'arch/arm/mach-ixp4xx/common.c')
-rw-r--r--arch/arm/mach-ixp4xx/common.c347
1 files changed, 258 insertions, 89 deletions
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 0bce09799d1..fc4b7b24265 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -17,29 +17,43 @@
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/serial.h>
-#include <linux/sched.h>
#include <linux/tty.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>
#include <linux/time.h>
-#include <linux/timex.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/io.h>
-
+#include <linux/export.h>
+#include <linux/gpio.h>
+#include <linux/cpu.h>
+#include <linux/pci.h>
+#include <linux/sched_clock.h>
#include <mach/udc.h>
#include <mach/hardware.h>
+#include <mach/io.h>
#include <asm/uaccess.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/irq.h>
-
+#include <asm/system_misc.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
+#define IXP4XX_TIMER_FREQ 66666000
+
+/*
+ * The timer register doesn't allow to specify the two least significant bits of
+ * the timeout value and assumes them being zero. So make sure IXP4XX_LATCH is
+ * the best value with the two least significant bits unset.
+ */
+#define IXP4XX_LATCH DIV_ROUND_CLOSEST(IXP4XX_TIMER_FREQ, \
+ (IXP4XX_OST_RELOAD_MASK + 1) * HZ) * \
+ (IXP4XX_OST_RELOAD_MASK + 1)
+
static void __init ixp4xx_clocksource_init(void);
static void __init ixp4xx_clockevent_init(void);
static struct clock_event_device clockevent_ixp4xx;
@@ -49,29 +63,26 @@ static struct clock_event_device clockevent_ixp4xx;
*************************************************************************/
static struct map_desc ixp4xx_io_desc[] __initdata = {
{ /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
- .virtual = IXP4XX_PERIPHERAL_BASE_VIRT,
+ .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
.pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
.length = IXP4XX_PERIPHERAL_REGION_SIZE,
.type = MT_DEVICE
}, { /* Expansion Bus Config Registers */
- .virtual = IXP4XX_EXP_CFG_BASE_VIRT,
+ .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
.pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
.length = IXP4XX_EXP_CFG_REGION_SIZE,
.type = MT_DEVICE
}, { /* PCI Registers */
- .virtual = IXP4XX_PCI_CFG_BASE_VIRT,
+ .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
.pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
.length = IXP4XX_PCI_CFG_REGION_SIZE,
.type = MT_DEVICE
- },
-#ifdef CONFIG_DEBUG_LL
- { /* Debug UART mapping */
- .virtual = IXP4XX_DEBUG_UART_BASE_VIRT,
- .pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
- .length = IXP4XX_DEBUG_UART_REGION_SIZE,
+ }, { /* Queue Manager */
+ .virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
+ .pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
+ .length = IXP4XX_QMGR_REGION_SIZE,
.type = MT_DEVICE
- }
-#endif
+ },
};
void __init ixp4xx_map_io(void)
@@ -79,6 +90,44 @@ void __init ixp4xx_map_io(void)
iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
}
+/*
+ * GPIO-functions
+ */
+/*
+ * The following converted to the real HW bits the gpio_line_config
+ */
+/* GPIO pin types */
+#define IXP4XX_GPIO_OUT 0x1
+#define IXP4XX_GPIO_IN 0x2
+
+/* GPIO signal types */
+#define IXP4XX_GPIO_LOW 0
+#define IXP4XX_GPIO_HIGH 1
+
+/* GPIO Clocks */
+#define IXP4XX_GPIO_CLK_0 14
+#define IXP4XX_GPIO_CLK_1 15
+
+static void gpio_line_config(u8 line, u32 direction)
+{
+ if (direction == IXP4XX_GPIO_IN)
+ *IXP4XX_GPIO_GPOER |= (1 << line);
+ else
+ *IXP4XX_GPIO_GPOER &= ~(1 << line);
+}
+
+static void gpio_line_get(u8 line, int *value)
+{
+ *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1;
+}
+
+static void gpio_line_set(u8 line, int value)
+{
+ if (value == IXP4XX_GPIO_HIGH)
+ *IXP4XX_GPIO_GPOUTR |= (1 << line);
+ else if (value == IXP4XX_GPIO_LOW)
+ *IXP4XX_GPIO_GPOUTR &= ~(1 << line);
+}
/*************************************************************************
* IXP4xx chipset IRQ handling
@@ -104,7 +153,7 @@ static signed char irq2gpio[32] = {
7, 8, 9, 10, 11, 12, -1, -1,
};
-int gpio_to_irq(int gpio)
+static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
{
int irq;
@@ -114,22 +163,10 @@ int gpio_to_irq(int gpio)
}
return -EINVAL;
}
-EXPORT_SYMBOL(gpio_to_irq);
-
-int irq_to_gpio(unsigned int irq)
-{
- int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
-
- if (gpio == -1)
- return -EINVAL;
-
- return gpio;
-}
-EXPORT_SYMBOL(irq_to_gpio);
-static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
+static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
{
- int line = irq2gpio[irq];
+ int line = irq2gpio[d->irq];
u32 int_style;
enum ixp4xx_irq_type irq_type;
volatile u32 *int_reg;
@@ -166,9 +203,9 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
}
if (irq_type == IXP4XX_IRQ_EDGE)
- ixp4xx_irq_edge |= (1 << irq);
+ ixp4xx_irq_edge |= (1 << d->irq);
else
- ixp4xx_irq_edge &= ~(1 << irq);
+ ixp4xx_irq_edge &= ~(1 << d->irq);
if (line >= 8) { /* pins 8-15 */
line -= 8;
@@ -187,22 +224,22 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
*int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
/* Configure the line as an input */
- gpio_line_config(irq2gpio[irq], IXP4XX_GPIO_IN);
+ gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
return 0;
}
-static void ixp4xx_irq_mask(unsigned int irq)
+static void ixp4xx_irq_mask(struct irq_data *d)
{
- if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
- *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
+ if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
+ *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
else
- *IXP4XX_ICMR &= ~(1 << irq);
+ *IXP4XX_ICMR &= ~(1 << d->irq);
}
-static void ixp4xx_irq_ack(unsigned int irq)
+static void ixp4xx_irq_ack(struct irq_data *d)
{
- int line = (irq < 32) ? irq2gpio[irq] : -1;
+ int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
if (line >= 0)
*IXP4XX_GPIO_GPISR = (1 << line);
@@ -212,29 +249,35 @@ static void ixp4xx_irq_ack(unsigned int irq)
* Level triggered interrupts on GPIO lines can only be cleared when the
* interrupt condition disappears.
*/
-static void ixp4xx_irq_unmask(unsigned int irq)
+static void ixp4xx_irq_unmask(struct irq_data *d)
{
- if (!(ixp4xx_irq_edge & (1 << irq)))
- ixp4xx_irq_ack(irq);
+ if (!(ixp4xx_irq_edge & (1 << d->irq)))
+ ixp4xx_irq_ack(d);
- if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
- *IXP4XX_ICMR2 |= (1 << (irq - 32));
+ if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
+ *IXP4XX_ICMR2 |= (1 << (d->irq - 32));
else
- *IXP4XX_ICMR |= (1 << irq);
+ *IXP4XX_ICMR |= (1 << d->irq);
}
static struct irq_chip ixp4xx_irq_chip = {
.name = "IXP4xx",
- .ack = ixp4xx_irq_ack,
- .mask = ixp4xx_irq_mask,
- .unmask = ixp4xx_irq_unmask,
- .set_type = ixp4xx_set_irq_type,
+ .irq_ack = ixp4xx_irq_ack,
+ .irq_mask = ixp4xx_irq_mask,
+ .irq_unmask = ixp4xx_irq_unmask,
+ .irq_set_type = ixp4xx_set_irq_type,
};
void __init ixp4xx_init_irq(void)
{
int i = 0;
+ /*
+ * ixp4xx does not implement the XScale PWRMODE register
+ * so it must not call cpu_do_idle().
+ */
+ cpu_idle_poll_ctrl(true);
+
/* Route all sources to IRQ instead of FIQ */
*IXP4XX_ICLR = 0x0;
@@ -251,8 +294,8 @@ void __init ixp4xx_init_irq(void)
/* Default to all level triggered */
for(i = 0; i < NR_IRQS; i++) {
- set_irq_chip(i, &ixp4xx_irq_chip);
- set_irq_handler(i, handle_level_irq);
+ irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
+ handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}
@@ -278,7 +321,7 @@ static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
static struct irqaction ixp4xx_timer_irq = {
.name = "timer1",
- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = ixp4xx_timer_interrupt,
.dev_id = &clockevent_ixp4xx,
};
@@ -301,10 +344,6 @@ void __init ixp4xx_timer_init(void)
ixp4xx_clockevent_init();
}
-struct sys_timer ixp4xx_timer = {
- .init = ixp4xx_timer_init,
-};
-
static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
@@ -374,12 +413,56 @@ static struct platform_device *ixp46x_devices[] __initdata = {
unsigned long ixp4xx_exp_bus_size;
EXPORT_SYMBOL(ixp4xx_exp_bus_size);
+static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+ gpio_line_config(gpio, IXP4XX_GPIO_IN);
+
+ return 0;
+}
+
+static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
+ int level)
+{
+ gpio_line_set(gpio, level);
+ gpio_line_config(gpio, IXP4XX_GPIO_OUT);
+
+ return 0;
+}
+
+static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
+{
+ int value;
+
+ gpio_line_get(gpio, &value);
+
+ return value;
+}
+
+static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
+ int value)
+{
+ gpio_line_set(gpio, value);
+}
+
+static struct gpio_chip ixp4xx_gpio_chip = {
+ .label = "IXP4XX_GPIO_CHIP",
+ .direction_input = ixp4xx_gpio_direction_input,
+ .direction_output = ixp4xx_gpio_direction_output,
+ .get = ixp4xx_gpio_get_value,
+ .set = ixp4xx_gpio_set_value,
+ .to_irq = ixp4xx_gpio_to_irq,
+ .base = 0,
+ .ngpio = 16,
+};
+
void __init ixp4xx_sys_init(void)
{
ixp4xx_exp_bus_size = SZ_16M;
platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
+ gpiochip_add(&ixp4xx_gpio_chip);
+
if (cpu_is_ixp46x()) {
int region;
@@ -399,41 +482,30 @@ void __init ixp4xx_sys_init(void)
}
/*
- * clocksource
+ * sched_clock()
*/
-static cycle_t ixp4xx_get_cycles(struct clocksource *cs)
+static u64 notrace ixp4xx_read_sched_clock(void)
{
return *IXP4XX_OSTS;
}
-static struct clocksource clocksource_ixp4xx = {
- .name = "OSTS",
- .rating = 200,
- .read = ixp4xx_get_cycles,
- .mask = CLOCKSOURCE_MASK(32),
- .shift = 20,
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
+/*
+ * clocksource
+ */
-unsigned long ixp4xx_timer_freq = FREQ;
-EXPORT_SYMBOL(ixp4xx_timer_freq);
-static void __init ixp4xx_clocksource_init(void)
+static cycle_t ixp4xx_clocksource_read(struct clocksource *c)
{
- clocksource_ixp4xx.mult =
- clocksource_hz2mult(ixp4xx_timer_freq,
- clocksource_ixp4xx.shift);
- clocksource_register(&clocksource_ixp4xx);
+ return *IXP4XX_OSTS;
}
-/*
- * sched_clock()
- */
-unsigned long long sched_clock(void)
+unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
+EXPORT_SYMBOL(ixp4xx_timer_freq);
+static void __init ixp4xx_clocksource_init(void)
{
- cycle_t cyc = ixp4xx_get_cycles(NULL);
- struct clocksource *cs = &clocksource_ixp4xx;
+ sched_clock_register(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
- return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
+ clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
+ ixp4xx_clocksource_read);
}
/*
@@ -457,7 +529,7 @@ static void ixp4xx_set_mode(enum clock_event_mode mode,
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
- osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
+ osrt = IXP4XX_LATCH & ~IXP4XX_OST_RELOAD_MASK;
opts = IXP4XX_OST_ENABLE;
break;
case CLOCK_EVT_MODE_ONESHOT:
@@ -484,20 +556,117 @@ static struct clock_event_device clockevent_ixp4xx = {
.name = "ixp4xx timer1",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.rating = 200,
- .shift = 24,
.set_mode = ixp4xx_set_mode,
.set_next_event = ixp4xx_set_next_event,
};
static void __init ixp4xx_clockevent_init(void)
{
- clockevent_ixp4xx.mult = div_sc(FREQ, NSEC_PER_SEC,
- clockevent_ixp4xx.shift);
- clockevent_ixp4xx.max_delta_ns =
- clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
- clockevent_ixp4xx.min_delta_ns =
- clockevent_delta2ns(0xf, &clockevent_ixp4xx);
clockevent_ixp4xx.cpumask = cpumask_of(0);
+ clockevents_config_and_register(&clockevent_ixp4xx, IXP4XX_TIMER_FREQ,
+ 0xf, 0xfffffffe);
+}
+
+void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
+{
+ if (mode == REBOOT_SOFT) {
+ /* Jump into ROM at address 0 */
+ soft_restart(0);
+ } else {
+ /* Use on-chip reset capability */
- clockevents_register_device(&clockevent_ixp4xx);
+ /* set the "key" register to enable access to
+ * "timer" and "enable" registers
+ */
+ *IXP4XX_OSWK = IXP4XX_WDT_KEY;
+
+ /* write 0 to the timer register for an immediate reset */
+ *IXP4XX_OSWT = 0;
+
+ *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
+ }
+}
+
+#ifdef CONFIG_PCI
+static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
+{
+ return (dma_addr + size) > SZ_64M;
+}
+
+static int ixp4xx_platform_notify_remove(struct device *dev)
+{
+ if (dev_is_pci(dev))
+ dmabounce_unregister_dev(dev);
+
+ return 0;
+}
+#endif
+
+/*
+ * Setup DMA mask to 64MB on PCI devices and 4 GB on all other things.
+ */
+static int ixp4xx_platform_notify(struct device *dev)
+{
+ dev->dma_mask = &dev->coherent_dma_mask;
+
+#ifdef CONFIG_PCI
+ if (dev_is_pci(dev)) {
+ dev->coherent_dma_mask = DMA_BIT_MASK(28); /* 64 MB */
+ dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
+ return 0;
+ }
+#endif
+
+ dev->coherent_dma_mask = DMA_BIT_MASK(32);
+ return 0;
+}
+
+int dma_set_coherent_mask(struct device *dev, u64 mask)
+{
+ if (dev_is_pci(dev))
+ mask &= DMA_BIT_MASK(28); /* 64 MB */
+
+ if ((mask & DMA_BIT_MASK(28)) == DMA_BIT_MASK(28)) {
+ dev->coherent_dma_mask = mask;
+ return 0;
+ }
+
+ return -EIO; /* device wanted sub-64MB mask */
+}
+EXPORT_SYMBOL(dma_set_coherent_mask);
+
+#ifdef CONFIG_IXP4XX_INDIRECT_PCI
+/*
+ * In the case of using indirect PCI, we simply return the actual PCI
+ * address and our read/write implementation use that to drive the
+ * access registers. If something outside of PCI is ioremap'd, we
+ * fallback to the default.
+ */
+
+static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
+ unsigned int mtype, void *caller)
+{
+ if (!is_pci_memory(addr))
+ return __arm_ioremap_caller(addr, size, mtype, caller);
+
+ return (void __iomem *)addr;
+}
+
+static void ixp4xx_iounmap(void __iomem *addr)
+{
+ if (!is_pci_memory((__force u32)addr))
+ __iounmap(addr);
+}
+#endif
+
+void __init ixp4xx_init_early(void)
+{
+ platform_notify = ixp4xx_platform_notify;
+#ifdef CONFIG_PCI
+ platform_notify_remove = ixp4xx_platform_notify_remove;
+#endif
+#ifdef CONFIG_IXP4XX_INDIRECT_PCI
+ arch_ioremap_caller = ixp4xx_ioremap_caller;
+ arch_iounmap = ixp4xx_iounmap;
+#endif
}
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-11-05 05:51:35 +0000