diff options
Diffstat (limited to 'arch/arm/mach-ixp2000/include/mach')
| -rw-r--r-- | arch/arm/mach-ixp2000/include/mach/debug-macro.S | 25 | ||||
| -rw-r--r-- | arch/arm/mach-ixp2000/include/mach/enp2611.h | 46 | ||||
| -rw-r--r-- | arch/arm/mach-ixp2000/include/mach/entry-macro.S | 60 | ||||
| -rw-r--r-- | arch/arm/mach-ixp2000/include/mach/gpio.h | 48 | ||||
| -rw-r--r-- | arch/arm/mach-ixp2000/include/mach/hardware.h | 44 | ||||
| -rw-r--r-- | arch/arm/mach-ixp2000/include/mach/io.h | 134 | ||||
| -rw-r--r-- | arch/arm/mach-ixp2000/include/mach/irqs.h | 207 | ||||
| -rw-r--r-- | arch/arm/mach-ixp2000/include/mach/ixdp2x00.h | 92 | ||||
| -rw-r--r-- | arch/arm/mach-ixp2000/include/mach/ixdp2x01.h | 57 | ||||
| -rw-r--r-- | arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h | 451 | ||||
| -rw-r--r-- | arch/arm/mach-ixp2000/include/mach/memory.h | 31 | ||||
| -rw-r--r-- | arch/arm/mach-ixp2000/include/mach/platform.h | 152 | ||||
| -rw-r--r-- | arch/arm/mach-ixp2000/include/mach/system.h | 49 | ||||
| -rw-r--r-- | arch/arm/mach-ixp2000/include/mach/timex.h | 13 | ||||
| -rw-r--r-- | arch/arm/mach-ixp2000/include/mach/uncompress.h | 47 | ||||
| -rw-r--r-- | arch/arm/mach-ixp2000/include/mach/vmalloc.h | 20 |
16 files changed, 0 insertions, 1476 deletions
diff --git a/arch/arm/mach-ixp2000/include/mach/debug-macro.S b/arch/arm/mach-ixp2000/include/mach/debug-macro.S deleted file mode 100644 index 0ef533b2097..00000000000 --- a/arch/arm/mach-ixp2000/include/mach/debug-macro.S +++ /dev/null @@ -1,25 +0,0 @@ -/* arch/arm/mach-ixp2000/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - - .macro addruart, rp, rv - mov \rp, #0x00030000 -#ifdef __ARMEB__ - orr \rp, \rp, #0x00000003 -#endif - orr \rv, \rp, #0xfe000000 @ virtual base - orr \rv, \rv, #0x00f00000 - orr \rp, \rp, #0xc0000000 @ Physical base - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-ixp2000/include/mach/enp2611.h b/arch/arm/mach-ixp2000/include/mach/enp2611.h deleted file mode 100644 index 9ce3690061d..00000000000 --- a/arch/arm/mach-ixp2000/include/mach/enp2611.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/enp2611.h - * - * Register and other defines for Radisys ENP-2611 - * - * Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The - * original version carries the following notices: - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __ENP2611_H -#define __ENP2611_H - -#define ENP2611_CALEB_PHYS_BASE 0xc5000000 -#define ENP2611_CALEB_VIRT_BASE 0xfe000000 -#define ENP2611_CALEB_SIZE 0x00100000 - -#define ENP2611_PM3386_0_PHYS_BASE 0xc6000000 -#define ENP2611_PM3386_0_VIRT_BASE 0xfe100000 -#define ENP2611_PM3386_0_SIZE 0x00100000 - -#define ENP2611_PM3386_1_PHYS_BASE 0xc6400000 -#define ENP2611_PM3386_1_VIRT_BASE 0xfe200000 -#define ENP2611_PM3386_1_SIZE 0x00100000 - -#define ENP2611_GPIO_SCL 7 -#define ENP2611_GPIO_SDA 6 - -#define IRQ_ENP2611_THERMAL IRQ_IXP2000_GPIO4 -#define IRQ_ENP2611_OPTION_BOARD IRQ_IXP2000_GPIO3 -#define IRQ_ENP2611_CALEB IRQ_IXP2000_GPIO2 -#define IRQ_ENP2611_PM3386_1 IRQ_IXP2000_GPIO1 -#define IRQ_ENP2611_PM3386_0 IRQ_IXP2000_GPIO0 - - -#endif diff --git a/arch/arm/mach-ixp2000/include/mach/entry-macro.S b/arch/arm/mach-ixp2000/include/mach/entry-macro.S deleted file mode 100644 index 5850ffc8c75..00000000000 --- a/arch/arm/mach-ixp2000/include/mach/entry-macro.S +++ /dev/null @@ -1,60 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for IXP2000-based platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <mach/irqs.h> - - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - mov \irqnr, #0x0 @clear out irqnr as default - mov \base, #0xfe000000 - orr \base, \base, #0x00e00000 - orr \base, \base, #0x08 - ldr \irqstat, [\base] @ get interrupts - - cmp \irqstat, #0 - beq 1001f - - clz \irqnr, \irqstat - mov \base, #31 - subs \irqnr, \base, \irqnr - - /* - * We handle PCIA and PCIB here so we don't have an - * extra layer of code just to check these two bits. - */ - cmp \irqnr, #IRQ_IXP2000_PCI - bne 1001f - - mov \base, #0xfe000000 - orr \base, \base, #0x00c00000 - orr \base, \base, #0x00000100 - orr \base, \base, #0x00000058 - ldr \irqstat, [\base] - - mov \tmp, #(1<<26) - tst \irqstat, \tmp - movne \irqnr, #IRQ_IXP2000_PCIA - bne 1001f - - mov \tmp, #(1<<27) - tst \irqstat, \tmp - movne \irqnr, #IRQ_IXP2000_PCIB - -1001: - .endm - diff --git a/arch/arm/mach-ixp2000/include/mach/gpio.h b/arch/arm/mach-ixp2000/include/mach/gpio.h deleted file mode 100644 index 4a88d2c33da..00000000000 --- a/arch/arm/mach-ixp2000/include/mach/gpio.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/gpio.h - * - * Copyright (C) 2002 Intel Corporation. - * - * This program is free software, you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * IXP2000 GPIO in/out, edge/level detection for IRQs: - * IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High - * or both Falling-edge and Rising-edge. - * This must be called *before* the corresponding IRQ is registerd. - * Use this instead of directly setting the GPIO registers. - * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb) - */ -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - -#ifndef __ASSEMBLY__ - -#define GPIO_IN 0 -#define GPIO_OUT 1 - -#define IXP2000_GPIO_LOW 0 -#define IXP2000_GPIO_HIGH 1 - -extern void gpio_line_config(int line, int direction); - -static inline int gpio_line_get(int line) -{ - return (((*IXP2000_GPIO_PLR) >> line) & 1); -} - -static inline void gpio_line_set(int line, int value) -{ - if (value == IXP2000_GPIO_HIGH) { - ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line); - } else if (value == IXP2000_GPIO_LOW) { - ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line); - } -} - -#endif /* !__ASSEMBLY__ */ - -#endif /* ASM_ARCH_IXP2000_GPIO_H_ */ diff --git a/arch/arm/mach-ixp2000/include/mach/hardware.h b/arch/arm/mach-ixp2000/include/mach/hardware.h deleted file mode 100644 index f033de4e749..00000000000 --- a/arch/arm/mach-ixp2000/include/mach/hardware.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/hardware.h - * - * Hardware definitions for IXP2400/2800 based systems - * - * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com> - * - * Maintainer: Deepak Saxena <dsaxena@mvista.com> - * - * Copyright (C) 2001-2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __ASM_ARCH_HARDWARE_H__ -#define __ASM_ARCH_HARDWARE_H__ - -/* - * This needs to be platform-specific? - */ -#define PCIBIOS_MIN_IO 0x00000000 -#define PCIBIOS_MIN_MEM 0x00000000 - -#include "ixp2000-regs.h" /* Chipset Registers */ - -#define pcibios_assign_all_busses() 0 - -/* - * Platform helper functions - */ -#include "platform.h" - -/* - * Platform-specific bits - */ -#include "enp2611.h" /* ENP-2611 */ -#include "ixdp2x00.h" /* IXDP2400/2800 */ -#include "ixdp2x01.h" /* IXDP2401/2801 */ - -#endif /* _ASM_ARCH_HARDWARE_H__ */ diff --git a/arch/arm/mach-ixp2000/include/mach/io.h b/arch/arm/mach-ixp2000/include/mach/io.h deleted file mode 100644 index 859e584914d..00000000000 --- a/arch/arm/mach-ixp2000/include/mach/io.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/io.h - * - * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyrgiht (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#include <mach/hardware.h> - -#define IO_SPACE_LIMIT 0xffffffff -#define __mem_pci(a) (a) - -/* - * The A? revisions of the IXP2000s assert byte lanes for PCI I/O - * transactions the other way round (MEM transactions don't have this - * issue), so if we want to support those models, we need to override - * the standard I/O functions. - * - * B0 and later have a bit that can be set to 1 to get the proper - * behavior for I/O transactions, which then allows us to use the - * standard I/O functions. This is what we do if the user does not - * explicitly ask for support for pre-B0. - */ -#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO -#define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE)) - -#define alignb(addr) (void __iomem *)((unsigned long)(addr) ^ 3) -#define alignw(addr) (void __iomem *)((unsigned long)(addr) ^ 2) - -#define outb(v,p) __raw_writeb((v),alignb(___io(p))) -#define outw(v,p) __raw_writew((v),alignw(___io(p))) -#define outl(v,p) __raw_writel((v),___io(p)) - -#define inb(p) ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; }) -#define inw(p) \ - ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; }) -#define inl(p) \ - ({ unsigned int __v = (__raw_readl(___io(p))); __v; }) - -#define outsb(p,d,l) __raw_writesb(alignb(___io(p)),d,l) -#define outsw(p,d,l) __raw_writesw(alignw(___io(p)),d,l) -#define outsl(p,d,l) __raw_writesl(___io(p),d,l) - -#define insb(p,d,l) __raw_readsb(alignb(___io(p)),d,l) -#define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l) -#define insl(p,d,l) __raw_readsl(___io(p),d,l) - -#define __is_io_address(p) ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE) - -#define ioread8(p) \ - ({ \ - unsigned int __v; \ - \ - if (__is_io_address(p)) { \ - __v = __raw_readb(alignb(p)); \ - } else { \ - __v = __raw_readb(p); \ - } \ - \ - __v; \ - }) \ - -#define ioread16(p) \ - ({ \ - unsigned int __v; \ - \ - if (__is_io_address(p)) { \ - __v = __raw_readw(alignw(p)); \ - } else { \ - __v = le16_to_cpu(__raw_readw(p)); \ - } \ - \ - __v; \ - }) - -#define ioread32(p) \ - ({ \ - unsigned int __v; \ - \ - if (__is_io_address(p)) { \ - __v = __raw_readl(p); \ - } else { \ - __v = le32_to_cpu(__raw_readl(p)); \ - } \ - \ - __v; \ - }) - -#define iowrite8(v,p) \ - ({ \ - if (__is_io_address(p)) { \ - __raw_writeb((v), alignb(p)); \ - } else { \ - __raw_writeb((v), p); \ - } \ - }) - -#define iowrite16(v,p) \ - ({ \ - if (__is_io_address(p)) { \ - __raw_writew((v), alignw(p)); \ - } else { \ - __raw_writew(cpu_to_le16(v), p); \ - } \ - }) - -#define iowrite32(v,p) \ - ({ \ - if (__is_io_address(p)) { \ - __raw_writel((v), p); \ - } else { \ - __raw_writel(cpu_to_le32(v), p); \ - } \ - }) - -#define ioport_map(port, nr) ___io(port) - -#define ioport_unmap(addr) -#else -#define __io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE)) -#endif - - -#endif diff --git a/arch/arm/mach-ixp2000/include/mach/irqs.h b/arch/arm/mach-ixp2000/include/mach/irqs.h deleted file mode 100644 index bee96bcafdc..00000000000 --- a/arch/arm/mach-ixp2000/include/mach/irqs.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/irqs.h - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _IRQS_H -#define _IRQS_H - -/* - * Do NOT add #ifdef MACHINE_FOO in here. - * Simpy add your machine IRQs here and increase NR_IRQS if needed to - * hold your machine's IRQ table. - */ - -/* - * Some interrupt numbers go unused b/c the IRQ mask/ummask/status - * register has those bit reserved. We just mark those interrupts - * as invalid and this allows us to do mask/unmask with a single - * shift operation instead of having to map the IRQ number to - * a HW IRQ number. - */ -#define IRQ_IXP2000_SOFT_INT 0 /* soft interrupt */ -#define IRQ_IXP2000_ERRSUM 1 /* OR of all bits in ErrorStatus reg*/ -#define IRQ_IXP2000_UART 2 -#define IRQ_IXP2000_GPIO 3 -#define IRQ_IXP2000_TIMER1 4 -#define IRQ_IXP2000_TIMER2 5 -#define IRQ_IXP2000_TIMER3 6 -#define IRQ_IXP2000_TIMER4 7 -#define IRQ_IXP2000_PMU 8 -#define IRQ_IXP2000_SPF 9 /* Slow port framer IRQ */ -#define IRQ_IXP2000_DMA1 10 -#define IRQ_IXP2000_DMA2 11 -#define IRQ_IXP2000_DMA3 12 -#define IRQ_IXP2000_PCI_DOORBELL 13 -#define IRQ_IXP2000_ME_ATTN 14 -#define IRQ_IXP2000_PCI 15 /* PCI INTA or INTB */ -#define IRQ_IXP2000_THDA0 16 /* thread 0-31A */ -#define IRQ_IXP2000_THDA1 17 /* thread 32-63A, IXP2800 only */ -#define IRQ_IXP2000_THDA2 18 /* thread 64-95A */ -#define IRQ_IXP2000_THDA3 19 /* thread 96-127A, IXP2800 only */ -#define IRQ_IXP2000_THDB0 24 /* thread 0-31B */ -#define IRQ_IXP2000_THDB1 25 /* thread 32-63B, IXP2800 only */ -#define IRQ_IXP2000_THDB2 26 /* thread 64-95B */ -#define IRQ_IXP2000_THDB3 27 /* thread 96-127B, IXP2800 only */ - -/* define generic GPIOs */ -#define IRQ_IXP2000_GPIO0 32 -#define IRQ_IXP2000_GPIO1 33 -#define IRQ_IXP2000_GPIO2 34 -#define IRQ_IXP2000_GPIO3 35 -#define IRQ_IXP2000_GPIO4 36 -#define IRQ_IXP2000_GPIO5 37 -#define IRQ_IXP2000_GPIO6 38 -#define IRQ_IXP2000_GPIO7 39 - -/* split off the 2 PCI sources */ -#define IRQ_IXP2000_PCIA 40 -#define IRQ_IXP2000_PCIB 41 - -/* Int sources from IRQ_ERROR_STATUS */ -#define IRQ_IXP2000_DRAM0_MIN_ERR 42 -#define IRQ_IXP2000_DRAM0_MAJ_ERR 43 -#define IRQ_IXP2000_DRAM1_MIN_ERR 44 -#define IRQ_IXP2000_DRAM1_MAJ_ERR 45 -#define IRQ_IXP2000_DRAM2_MIN_ERR 46 -#define IRQ_IXP2000_DRAM2_MAJ_ERR 47 -/* 48-57 reserved */ -#define IRQ_IXP2000_SRAM0_ERR 58 -#define IRQ_IXP2000_SRAM1_ERR 59 -#define IRQ_IXP2000_SRAM2_ERR 60 -#define IRQ_IXP2000_SRAM3_ERR 61 -/* 62-65 reserved */ -#define IRQ_IXP2000_MEDIA_ERR 66 -#define IRQ_IXP2000_PCI_ERR 67 -#define IRQ_IXP2000_SP_INT 68 - -#define NR_IXP2000_IRQS 69 - -#define IXP2000_BOARD_IRQ(x) (NR_IXP2000_IRQS + (x)) - -#define IXP2000_BOARD_IRQ_MASK(irq) (1 << (irq - NR_IXP2000_IRQS)) - -#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) -#define IXP2000_VALID_ERR_IRQ_MASK (\ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT) ) - -/* - * This allows for all the on-chip sources plus up to 32 CPLD based - * IRQs. Should be more than enough. - */ -#define IXP2000_BOARD_IRQS 32 -#define NR_IRQS (NR_IXP2000_IRQS + IXP2000_BOARD_IRQS) - - -/* - * IXDP2400 specific IRQs - */ -#define IRQ_IXDP2400_INGRESS_NPU IXP2000_BOARD_IRQ(0) -#define IRQ_IXDP2400_ENET IXP2000_BOARD_IRQ(1) -#define IRQ_IXDP2400_MEDIA_PCI IXP2000_BOARD_IRQ(2) -#define IRQ_IXDP2400_MEDIA_SP IXP2000_BOARD_IRQ(3) -#define IRQ_IXDP2400_SF_PCI IXP2000_BOARD_IRQ(4) -#define IRQ_IXDP2400_SF_SP IXP2000_BOARD_IRQ(5) -#define IRQ_IXDP2400_PMC IXP2000_BOARD_IRQ(6) -#define IRQ_IXDP2400_TVM IXP2000_BOARD_IRQ(7) - -#define NR_IXDP2400_IRQS ((IRQ_IXDP2400_TVM)+1) -#define IXDP2400_NR_IRQS NR_IXDP2400_IRQS - NR_IXP2000_IRQS - -/* IXDP2800 specific IRQs */ -#define IRQ_IXDP2800_EGRESS_ENET IXP2000_BOARD_IRQ(0) -#define IRQ_IXDP2800_INGRESS_NPU IXP2000_BOARD_IRQ(1) -#define IRQ_IXDP2800_PMC IXP2000_BOARD_IRQ(2) -#define IRQ_IXDP2800_FABRIC_PCI IXP2000_BOARD_IRQ(3) -#define IRQ_IXDP2800_FABRIC IXP2000_BOARD_IRQ(4) -#define IRQ_IXDP2800_MEDIA IXP2000_BOARD_IRQ(5) - -#define NR_IXDP2800_IRQS ((IRQ_IXDP2800_MEDIA)+1) -#define IXDP2800_NR_IRQS NR_IXDP2800_IRQS - NR_IXP2000_IRQS - -/* - * IRQs on both IXDP2x01 boards - */ -#define IRQ_IXDP2X01_SPCI_DB_0 IXP2000_BOARD_IRQ(2) -#define IRQ_IXDP2X01_SPCI_DB_1 IXP2000_BOARD_IRQ(3) -#define IRQ_IXDP2X01_SPCI_PMC_INTA IXP2000_BOARD_IRQ(4) -#define IRQ_IXDP2X01_SPCI_PMC_INTB IXP2000_BOARD_IRQ(5) -#define IRQ_IXDP2X01_SPCI_PMC_INTC IXP2000_BOARD_IRQ(6) -#define IRQ_IXDP2X01_SPCI_PMC_INTD IXP2000_BOARD_IRQ(7) -#define IRQ_IXDP2X01_SPCI_FIC_INT IXP2000_BOARD_IRQ(8) -#define IRQ_IXDP2X01_IPMI_FROM IXP2000_BOARD_IRQ(16) -#define IRQ_IXDP2X01_125US IXP2000_BOARD_IRQ(17) -#define IRQ_IXDP2X01_DB_0_ADD IXP2000_BOARD_IRQ(18) -#define IRQ_IXDP2X01_DB_1_ADD IXP2000_BOARD_IRQ(19) -#define IRQ_IXDP2X01_UART1 IXP2000_BOARD_IRQ(21) -#define IRQ_IXDP2X01_UART2 IXP2000_BOARD_IRQ(22) -#define IRQ_IXDP2X01_FIC_ADD_INT IXP2000_BOARD_IRQ(24) -#define IRQ_IXDP2X01_CS8900 IXP2000_BOARD_IRQ(25) -#define IRQ_IXDP2X01_BBSRAM IXP2000_BOARD_IRQ(26) - -#define IXDP2X01_VALID_IRQ_MASK ( \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) ) - -/* - * IXDP2401 specific IRQs - */ -#define IRQ_IXDP2401_INTA_82546 IXP2000_BOARD_IRQ(0) -#define IRQ_IXDP2401_INTB_82546 IXP2000_BOARD_IRQ(1) - -#define IXDP2401_VALID_IRQ_MASK ( \ - IXDP2X01_VALID_IRQ_MASK | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546)) - -/* - * IXDP2801-specific IRQs - */ -#define IRQ_IXDP2801_RIV IXP2000_BOARD_IRQ(0) -#define IRQ_IXDP2801_CNFG_MEDIA IXP2000_BOARD_IRQ(27) -#define IRQ_IXDP2801_CLOCK_REF IXP2000_BOARD_IRQ(28) - -#define IXDP2801_VALID_IRQ_MASK ( \ - IXDP2X01_VALID_IRQ_MASK | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF)) - -#define NR_IXDP2X01_IRQS ((IRQ_IXDP2801_CLOCK_REF) + 1) - -#endif /*_IRQS_H*/ diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h deleted file mode 100644 index 5df8479d948..00000000000 --- a/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/ixdp2x00.h - * - * Register and other defines for IXDP2[48]00 platforms - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef _IXDP2X00_H_ -#define _IXDP2X00_H_ - -/* - * On board CPLD memory map - */ -#define IXDP2X00_PHYS_CPLD_BASE 0xc7000000 -#define IXDP2X00_VIRT_CPLD_BASE 0xfe000000 -#define IXDP2X00_CPLD_SIZE 0x00100000 - - -#define IXDP2X00_CPLD_REG(x) \ - (volatile unsigned long *)(IXDP2X00_VIRT_CPLD_BASE | x) - -/* - * IXDP2400 CPLD registers - */ -#define IXDP2400_CPLD_SYSLED IXDP2X00_CPLD_REG(0x0) -#define IXDP2400_CPLD_DISP_DATA IXDP2X00_CPLD_REG(0x4) -#define IXDP2400_CPLD_CLOCK_SPEED IXDP2X00_CPLD_REG(0x8) -#define IXDP2400_CPLD_INT_STAT IXDP2X00_CPLD_REG(0xc) -#define IXDP2400_CPLD_REV IXDP2X00_CPLD_REG(0x10) -#define IXDP2400_CPLD_SYS_CLK_M IXDP2X00_CPLD_REG(0x14) -#define IXDP2400_CPLD_SYS_CLK_N IXDP2X00_CPLD_REG(0x18) -#define IXDP2400_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x48) - -/* - * IXDP2800 CPLD registers - */ -#define IXDP2800_CPLD_INT_STAT IXDP2X00_CPLD_REG(0x0) -#define IXDP2800_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x140) - - -#define IXDP2X00_GPIO_I2C_ENABLE 0x02 -#define IXDP2X00_GPIO_SCL 0x07 -#define IXDP2X00_GPIO_SDA 0x06 - -/* - * PCI devfns for on-board devices. We need these to be able to - * properly translate IRQs and for device removal. - */ -#define IXDP2400_SLAVE_ENET_DEVFN 0x18 /* Bus 1 */ -#define IXDP2400_MASTER_ENET_DEVFN 0x20 /* Bus 1 */ -#define IXDP2400_MEDIA_DEVFN 0x28 /* Bus 1 */ -#define IXDP2400_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */ - -#define IXDP2800_SLAVE_ENET_DEVFN 0x20 /* Bus 1 */ -#define IXDP2800_MASTER_ENET_DEVFN 0x18 /* Bus 1 */ -#define IXDP2800_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */ - -#define IXDP2X00_P2P_DEVFN 0x20 /* Bus 0 */ -#define IXDP2X00_21555_DEVFN 0x30 /* Bus 0 */ -#define IXDP2X00_SLAVE_NPU_DEVFN 0x28 /* Bus 1 */ -#define IXDP2X00_PMC_DEVFN 0x38 /* Bus 1 */ -#define IXDP2X00_MASTER_NPU_DEVFN 0x38 /* Bus 1 */ - -#ifndef __ASSEMBLY__ -/* - * The master NPU is always PCI master. - */ -static inline unsigned int ixdp2x00_master_npu(void) -{ - return !!ixp2000_is_pcimaster(); -} - -/* - * Helper functions used by ixdp2400 and ixdp2800 specific code - */ -void ixdp2x00_init_irq(volatile unsigned long*, volatile unsigned long *, unsigned long); -void ixdp2x00_slave_pci_postinit(void); -void ixdp2x00_init_machine(void); -void ixdp2x00_map_io(void); - -#endif - -#endif /*_IXDP2X00_H_ */ diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h deleted file mode 100644 index 4c1f04083e5..00000000000 --- a/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/ixdp2x01.h - * - * Platform definitions for IXDP2X01 && IXDP2801 systems - * - * Author: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2004 (c) MontaVista Software, Inc. - * - * Based on original code Copyright (c) 2002-2003 Intel Corporation - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __IXDP2X01_H__ -#define __IXDP2X01_H__ - -#define IXDP2X01_PHYS_CPLD_BASE 0xc6024000 -#define IXDP2X01_VIRT_CPLD_BASE 0xfe000000 -#define IXDP2X01_CPLD_REGION_SIZE 0x00100000 - -#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg) -#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg) - -#define IXDP2X01_UART1_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x40) -#define IXDP2X01_UART1_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x40) - -#define IXDP2X01_UART2_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x60) -#define IXDP2X01_UART2_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x60) - -#define IXDP2X01_CS8900_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x80) -#define IXDP2X01_CS8900_VIRT_END (IXDP2X01_CS8900_VIRT_BASE + 16) - -#define IXDP2X01_CPLD_RESET_REG IXDP2X01_CPLD_VIRT_REG(0x00) -#define IXDP2X01_INT_MASK_SET_REG IXDP2X01_CPLD_VIRT_REG(0x08) -#define IXDP2X01_INT_STAT_REG IXDP2X01_CPLD_VIRT_REG(0x0C) -#define IXDP2X01_INT_RAW_REG IXDP2X01_CPLD_VIRT_REG(0x10) -#define IXDP2X01_INT_MASK_CLR_REG IXDP2X01_INT_RAW_REG -#define IXDP2X01_INT_SIM_REG IXDP2X01_CPLD_VIRT_REG(0x14) - -#define IXDP2X01_CPLD_FLASH_REG IXDP2X01_CPLD_VIRT_REG(0x20) - -#define IXDP2X01_CPLD_FLASH_INTERN 0x8000 -#define IXDP2X01_CPLD_FLASH_BANK_MASK 0xF -#define IXDP2X01_FLASH_WINDOW_BITS 25 -#define IXDP2X01_FLASH_WINDOW_SIZE (1 << IXDP2X01_FLASH_WINDOW_BITS) -#define IXDP2X01_FLASH_WINDOW_MASK (IXDP2X01_FLASH_WINDOW_SIZE - 1) - -#define IXDP2X01_UART_CLK 1843200 - -#define IXDP2X01_GPIO_I2C_ENABLE 0x02 -#define IXDP2X01_GPIO_SCL 0x07 -#define IXDP2X01_GPIO_SDA 0x06 - -#endif /* __IXDP2x01_H__ */ diff --git a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h deleted file mode 100644 index 822f63f2f4a..00000000000 --- a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h +++ /dev/null @@ -1,451 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h - * - * Chipset register definitions for IXP2400/2800 based systems. - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef _IXP2000_REGS_H_ -#define _IXP2000_REGS_H_ - -/* - * IXP2000 linux memory map: - * - * virt phys size - * fb000000 db000000 16M PCI CFG1 - * fc000000 da000000 16M PCI CFG0 - * fd000000 d8000000 16M PCI I/O - * fe[0-7]00000 8M per-platform mappings - * fe900000 80000000 1M SRAM #0 (first MB) - * fea00000 cb400000 1M SCRATCH ring get/put - * feb00000 c8000000 1M MSF - * fec00000 df000000 1M PCI CSRs - * fed00000 de000000 1M PCI CREG - * fee00000 d6000000 1M INTCTL - * fef00000 c0000000 1M CAP - */ - -/* - * Static I/O regions. - * - * Most of the registers are clumped in 4K regions spread throughout - * the 0xc0000000 -> 0xc0100000 address range, but we just map in - * the whole range using a single 1 MB section instead of small - * 4K pages. - * - * CAP stands for CSR Access Proxy. - * - * If you change the virtual address of this mapping, please propagate - * the change to arch/arm/kernel/debug.S, which hardcodes the virtual - * address of the UART located in this region. - */ - -#define IXP2000_CAP_PHYS_BASE 0xc0000000 -#define IXP2000_CAP_VIRT_BASE 0xfef00000 -#define IXP2000_CAP_SIZE 0x00100000 - -/* - * Addresses for specific on-chip peripherals. - */ -#define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000 -#define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000 -#define IXP2000_UART_PHYS_BASE 0xc0030000 -#define IXP2000_UART_VIRT_BASE 0xfef30000 -#define IXP2000_TIMER_VIRT_BASE 0xfef20000 -#define IXP2000_UENGINE_CSR_VIRT_BASE 0xfef18000 -#define IXP2000_GPIO_VIRT_BASE 0xfef10000 - -/* - * Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual - * addresses of the INTCTL and PCI_CSR mappings are hardcoded in - * entry-macro.S, so if you ever change these please propagate - * the change. - */ -#define IXP2000_INTCTL_PHYS_BASE 0xd6000000 -#define IXP2000_INTCTL_VIRT_BASE 0xfee00000 -#define IXP2000_INTCTL_SIZE 0x00100000 - -#define IXP2000_PCI_CREG_PHYS_BASE 0xde000000 -#define IXP2000_PCI_CREG_VIRT_BASE 0xfed00000 -#define IXP2000_PCI_CREG_SIZE 0x00100000 - -#define IXP2000_PCI_CSR_PHYS_BASE 0xdf000000 -#define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000 -#define IXP2000_PCI_CSR_SIZE 0x00100000 - -#define IXP2000_MSF_PHYS_BASE 0xc8000000 -#define IXP2000_MSF_VIRT_BASE 0xfeb00000 -#define IXP2000_MSF_SIZE 0x00100000 - -#define IXP2000_SCRATCH_RING_PHYS_BASE 0xcb400000 -#define IXP2000_SCRATCH_RING_VIRT_BASE 0xfea00000 -#define IXP2000_SCRATCH_RING_SIZE 0x00100000 - -#define IXP2000_SRAM0_PHYS_BASE 0x80000000 -#define IXP2000_SRAM0_VIRT_BASE 0xfe900000 -#define IXP2000_SRAM0_SIZE 0x00100000 - -#define IXP2000_PCI_IO_PHYS_BASE 0xd8000000 -#define IXP2000_PCI_IO_VIRT_BASE 0xfd000000 -#define IXP2000_PCI_IO_SIZE 0x01000000 - -#define IXP2000_PCI_CFG0_PHYS_BASE 0xda000000 -#define IXP2000_PCI_CFG0_VIRT_BASE 0xfc000000 -#define IXP2000_PCI_CFG0_SIZE 0x01000000 - -#define IXP2000_PCI_CFG1_PHYS_BASE 0xdb000000 -#define IXP2000_PCI_CFG1_VIRT_BASE 0xfb000000 -#define IXP2000_PCI_CFG1_SIZE 0x01000000 - -/* - * Timers - */ -#define IXP2000_TIMER_REG(x) ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x))) -/* Timer control */ -#define IXP2000_T1_CTL IXP2000_TIMER_REG(0x00) -#define IXP2000_T2_CTL IXP2000_TIMER_REG(0x04) -#define IXP2000_T3_CTL IXP2000_TIMER_REG(0x08) -#define IXP2000_T4_CTL IXP2000_TIMER_REG(0x0c) -/* Store initial value */ -#define IXP2000_T1_CLD IXP2000_TIMER_REG(0x10) -#define IXP2000_T2_CLD IXP2000_TIMER_REG(0x14) -#define IXP2000_T3_CLD IXP2000_TIMER_REG(0x18) -#define IXP2000_T4_CLD IXP2000_TIMER_REG(0x1c) -/* Read current value */ -#define IXP2000_T1_CSR IXP2000_TIMER_REG(0x20) -#define IXP2000_T2_CSR IXP2000_TIMER_REG(0x24) -#define IXP2000_T3_CSR IXP2000_TIMER_REG(0x28) -#define IXP2000_T4_CSR IXP2000_TIMER_REG(0x2c) -/* Clear associated timer interrupt */ -#define IXP2000_T1_CLR IXP2000_TIMER_REG(0x30) -#define IXP2000_T2_CLR IXP2000_TIMER_REG(0x34) -#define IXP2000_T3_CLR IXP2000_TIMER_REG(0x38) -#define IXP2000_T4_CLR IXP2000_TIMER_REG(0x3c) -/* Timer watchdog enable for T4 */ -#define IXP2000_TWDE IXP2000_TIMER_REG(0x40) - -#define WDT_ENABLE 0x00000001 -#define TIMER_DIVIDER_256 0x00000008 -#define TIMER_ENABLE 0x00000080 -#define IRQ_MASK_TIMER1 (1 << 4) - -/* - * Interrupt controller registers - */ -#define IXP2000_INTCTL_REG(x) (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x)) -#define IXP2000_IRQ_STATUS IXP2000_INTCTL_REG(0x08) -#define IXP2000_IRQ_ENABLE IXP2000_INTCTL_REG(0x10) -#define IXP2000_IRQ_ENABLE_SET IXP2000_INTCTL_REG(0x10) -#define IXP2000_IRQ_ENABLE_CLR IXP2000_INTCTL_REG(0x18) -#define IXP2000_FIQ_ENABLE_CLR IXP2000_INTCTL_REG(0x14) -#define IXP2000_IRQ_ERR_STATUS IXP2000_INTCTL_REG(0x24) -#define IXP2000_IRQ_ERR_ENABLE_SET IXP2000_INTCTL_REG(0x2c) -#define IXP2000_FIQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x30) -#define IXP2000_IRQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x34) -#define IXP2000_IRQ_THD_RAW_STATUS_A_0 IXP2000_INTCTL_REG(0x60) -#define IXP2000_IRQ_THD_RAW_STATUS_A_1 IXP2000_INTCTL_REG(0x64) -#define IXP2000_IRQ_THD_RAW_STATUS_A_2 IXP2000_INTCTL_REG(0x68) -#define IXP2000_IRQ_THD_RAW_STATUS_A_3 IXP2000_INTCTL_REG(0x6c) -#define IXP2000_IRQ_THD_RAW_STATUS_B_0 IXP2000_INTCTL_REG(0x80) -#define IXP2000_IRQ_THD_RAW_STATUS_B_1 IXP2000_INTCTL_REG(0x84) -#define IXP2000_IRQ_THD_RAW_STATUS_B_2 IXP2000_INTCTL_REG(0x88) -#define IXP2000_IRQ_THD_RAW_STATUS_B_3 IXP2000_INTCTL_REG(0x8c) -#define IXP2000_IRQ_THD_STATUS_A_0 IXP2000_INTCTL_REG(0xe0) -#define IXP2000_IRQ_THD_STATUS_A_1 IXP2000_INTCTL_REG(0xe4) -#define IXP2000_IRQ_THD_STATUS_A_2 IXP2000_INTCTL_REG(0xe8) -#define IXP2000_IRQ_THD_STATUS_A_3 IXP2000_INTCTL_REG(0xec) -#define IXP2000_IRQ_THD_STATUS_B_0 IXP2000_INTCTL_REG(0x100) -#define IXP2000_IRQ_THD_STATUS_B_1 IXP2000_INTCTL_REG(0x104) -#define IXP2000_IRQ_THD_STATUS_B_2 IXP2000_INTCTL_REG(0x108) -#define IXP2000_IRQ_THD_STATUS_B_3 IXP2000_INTCTL_REG(0x10c) -#define IXP2000_IRQ_THD_ENABLE_SET_A_0 IXP2000_INTCTL_REG(0x160) -#define IXP2000_IRQ_THD_ENABLE_SET_A_1 IXP2000_INTCTL_REG(0x164) -#define IXP2000_IRQ_THD_ENABLE_SET_A_2 IXP2000_INTCTL_REG(0x168) -#define IXP2000_IRQ_THD_ENABLE_SET_A_3 IXP2000_INTCTL_REG(0x16c) -#define IXP2000_IRQ_THD_ENABLE_SET_B_0 IXP2000_INTCTL_REG(0x180) -#define IXP2000_IRQ_THD_ENABLE_SET_B_1 IXP2000_INTCTL_REG(0x184) -#define IXP2000_IRQ_THD_ENABLE_SET_B_2 IXP2000_INTCTL_REG(0x188) -#define IXP2000_IRQ_THD_ENABLE_SET_B_3 IXP2000_INTCTL_REG(0x18c) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0 IXP2000_INTCTL_REG(0x1e0) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1 IXP2000_INTCTL_REG(0x1e4) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2 IXP2000_INTCTL_REG(0x1e8) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3 IXP2000_INTCTL_REG(0x1ec) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0 IXP2000_INTCTL_REG(0x200) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1 IXP2000_INTCTL_REG(0x204) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2 IXP2000_INTCTL_REG(0x208) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3 IXP2000_INTCTL_REG(0x20c) - -/* - * Mask of valid IRQs in the 32-bit IRQ register. We use - * this to mark certain IRQs as being invalid. - */ -#define IXP2000_VALID_IRQ_MASK 0x0f0fffff - -/* - * PCI config register access from core - */ -#define IXP2000_PCI_CREG(x) (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x)) -#define IXP2000_PCI_CMDSTAT IXP2000_PCI_CREG(0x04) -#define IXP2000_PCI_CSR_BAR IXP2000_PCI_CREG(0x10) -#define IXP2000_PCI_SRAM_BAR IXP2000_PCI_CREG(0x14) -#define IXP2000_PCI_SDRAM_BAR IXP2000_PCI_CREG(0x18) - -/* - * PCI CSRs - */ -#define IXP2000_PCI_CSR(x) (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x)) - -/* - * PCI outbound interrupts - */ -#define IXP2000_PCI_OUT_INT_STATUS IXP2000_PCI_CSR(0x30) -#define IXP2000_PCI_OUT_INT_MASK IXP2000_PCI_CSR(0x34) -/* - * PCI communications - */ -#define IXP2000_PCI_MAILBOX0 IXP2000_PCI_CSR(0x50) -#define IXP2000_PCI_MAILBOX1 IXP2000_PCI_CSR(0x54) -#define IXP2000_PCI_MAILBOX2 IXP2000_PCI_CSR(0x58) -#define IXP2000_PCI_MAILBOX3 IXP2000_PCI_CSR(0x5C) -#define IXP2000_XSCALE_DOORBELL IXP2000_PCI_CSR(0x60) -#define IXP2000_XSCALE_DOORBELL_SETUP IXP2000_PCI_CSR(0x64) -#define IXP2000_PCI_DOORBELL IXP2000_PCI_CSR(0x70) -#define IXP2000_PCI_DOORBELL_SETUP IXP2000_PCI_CSR(0x74) - -/* - * DMA engines - */ -#define IXP2000_PCI_CH1_BYTE_CNT IXP2000_PCI_CSR(0x80) -#define IXP2000_PCI_CH1_ADDR IXP2000_PCI_CSR(0x84) -#define IXP2000_PCI_CH1_DRAM_ADDR IXP2000_PCI_CSR(0x88) -#define IXP2000_PCI_CH1_DESC_PTR IXP2000_PCI_CSR(0x8C) -#define IXP2000_PCI_CH1_CNTRL IXP2000_PCI_CSR(0x90) -#define IXP2000_PCI_CH1_ME_PARAM IXP2000_PCI_CSR(0x94) -#define IXP2000_PCI_CH2_BYTE_CNT IXP2000_PCI_CSR(0xA0) -#define IXP2000_PCI_CH2_ADDR IXP2000_PCI_CSR(0xA4) -#define IXP2000_PCI_CH2_DRAM_ADDR IXP2000_PCI_CSR(0xA8) -#define IXP2000_PCI_CH2_DESC_PTR IXP2000_PCI_CSR(0xAC) -#define IXP2000_PCI_CH2_CNTRL IXP2000_PCI_CSR(0xB0) -#define IXP2000_PCI_CH2_ME_PARAM IXP2000_PCI_CSR(0xB4) -#define IXP2000_PCI_CH3_BYTE_CNT IXP2000_PCI_CSR(0xC0) -#define IXP2000_PCI_CH3_ADDR IXP2000_PCI_CSR(0xC4) -#define IXP2000_PCI_CH3_DRAM_ADDR IXP2000_PCI_CSR(0xC8) -#define IXP2000_PCI_CH3_DESC_PTR IXP2000_PCI_CSR(0xCC) -#define IXP2000_PCI_CH3_CNTRL IXP2000_PCI_CSR(0xD0) -#define IXP2000_PCI_CH3_ME_PARAM IXP2000_PCI_CSR(0xD4) -#define IXP2000_DMA_INF_MODE IXP2000_PCI_CSR(0xE0) -/* - * Size masks for BARs - */ -#define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC) -#define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100) -/* - * Control and uEngine related - */ -#define IXP2000_PCI_CONTROL IXP2000_PCI_CSR(0x13C) -#define IXP2000_PCI_ADDR_EXT IXP2000_PCI_CSR(0x140) -#define IXP2000_PCI_ME_PUSH_STATUS IXP2000_PCI_CSR(0x148) -#define IXP2000_PCI_ME_PUSH_EN IXP2000_PCI_CSR(0x14C) -#define IXP2000_PCI_ERR_STATUS IXP2000_PCI_CSR(0x150) -#define IXP2000_PCI_ERR_ENABLE IXP2000_PCI_CSR(0x154) -/* - * Inbound PCI interrupt control - */ -#define IXP2000_PCI_XSCALE_INT_STATUS IXP2000_PCI_CSR(0x158) -#define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C) - -#define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */ -#define IXP2000_PCICNTL_PCF (1<<28) /* PCI Central function bit */ -#define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */ - -/* These are from the IRQ register in the PCI ISR register */ -#define PCI_CONTROL_BE_DEO (1 << 22) /* Big Endian Data Enable Out */ -#define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */ -#define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */ -#define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */ -#define PCI_CONTROL_IEE (1 << 17) /* I/O cycle Endian swap Enable */ - -#define IXP2000_PCI_RST_REL (1 << 2) -#define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF) -#define CFG_PCI_BOOT_HOST (1 << 2) -#define CFG_BOOT_PROM (1 << 1) - -/* - * SlowPort CSRs - * - * The slowport is used to access things like flash, SONET framer control - * ports, slave microprocessors, CPLDs, and others of chip memory mapped - * peripherals. - */ -#define SLOWPORT_CSR(x) (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x)) - -#define IXP2000_SLOWPORT_CCR SLOWPORT_CSR(0x00) -#define IXP2000_SLOWPORT_WTC1 SLOWPORT_CSR(0x04) -#define IXP2000_SLOWPORT_WTC2 SLOWPORT_CSR(0x08) -#define IXP2000_SLOWPORT_RTC1 SLOWPORT_CSR(0x0c) -#define IXP2000_SLOWPORT_RTC2 SLOWPORT_CSR(0x10) -#define IXP2000_SLOWPORT_FSR SLOWPORT_CSR(0x14) -#define IXP2000_SLOWPORT_PCR SLOWPORT_CSR(0x18) -#define IXP2000_SLOWPORT_ADC SLOWPORT_CSR(0x1C) -#define IXP2000_SLOWPORT_FAC SLOWPORT_CSR(0x20) -#define IXP2000_SLOWPORT_FRM SLOWPORT_CSR(0x24) -#define IXP2000_SLOWPORT_FIN SLOWPORT_CSR(0x28) - -/* - * CCR values. - * The CCR configures the clock division for the slowport interface. - */ -#define SLOWPORT_CCR_DIV_1 0x00 -#define SLOWPORT_CCR_DIV_2 0x01 -#define SLOWPORT_CCR_DIV_4 0x02 -#define SLOWPORT_CCR_DIV_6 0x03 -#define SLOWPORT_CCR_DIV_8 0x04 -#define SLOWPORT_CCR_DIV_10 0x05 -#define SLOWPORT_CCR_DIV_12 0x06 -#define SLOWPORT_CCR_DIV_14 0x07 -#define SLOWPORT_CCR_DIV_16 0x08 -#define SLOWPORT_CCR_DIV_18 0x09 -#define SLOWPORT_CCR_DIV_20 0x0a -#define SLOWPORT_CCR_DIV_22 0x0b -#define SLOWPORT_CCR_DIV_24 0x0c -#define SLOWPORT_CCR_DIV_26 0x0d -#define SLOWPORT_CCR_DIV_28 0x0e -#define SLOWPORT_CCR_DIV_30 0x0f - -/* - * PCR values. PCR configure the mode of the interface. - */ -#define SLOWPORT_MODE_FLASH 0x00 -#define SLOWPORT_MODE_LUCENT 0x01 -#define SLOWPORT_MODE_PMC_SIERRA 0x02 -#define SLOWPORT_MODE_INTEL_UP 0x03 -#define SLOWPORT_MODE_MOTOROLA_UP 0x04 - -/* - * ADC values. Defines data and address bus widths. - */ -#define SLOWPORT_ADDR_WIDTH_8 0x00 -#define SLOWPORT_ADDR_WIDTH_16 0x01 -#define SLOWPORT_ADDR_WIDTH_24 0x02 -#define SLOWPORT_ADDR_WIDTH_32 0x03 -#define SLOWPORT_DATA_WIDTH_8 0x00 -#define SLOWPORT_DATA_WIDTH_16 0x10 -#define SLOWPORT_DATA_WIDTH_24 0x20 -#define SLOWPORT_DATA_WIDTH_32 0x30 - -/* - * Masks and shifts for various fields in the WTC and RTC registers. - */ -#define SLOWPORT_WRTC_MASK_HD 0x0003 -#define SLOWPORT_WRTC_MASK_PW 0x003c -#define SLOWPORT_WRTC_MASK_SU 0x03c0 - -#define SLOWPORT_WRTC_SHIFT_HD 0x00 -#define SLOWPORT_WRTC_SHIFT_SU 0x02 -#define SLOWPORT_WRTC_SHFIT_PW 0x06 - - -/* - * GPIO registers & GPIO interface. - */ -#define IXP2000_GPIO_REG(x) ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x))) -#define IXP2000_GPIO_PLR IXP2000_GPIO_REG(0x00) -#define IXP2000_GPIO_PDPR IXP2000_GPIO_REG(0x04) -#define IXP2000_GPIO_PDSR IXP2000_GPIO_REG(0x08) -#define IXP2000_GPIO_PDCR IXP2000_GPIO_REG(0x0c) -#define IXP2000_GPIO_POPR IXP2000_GPIO_REG(0x10) -#define IXP2000_GPIO_POSR IXP2000_GPIO_REG(0x14) -#define IXP2000_GPIO_POCR IXP2000_GPIO_REG(0x18) -#define IXP2000_GPIO_REDR IXP2000_GPIO_REG(0x1c) -#define IXP2000_GPIO_FEDR IXP2000_GPIO_REG(0x20) -#define IXP2000_GPIO_EDSR IXP2000_GPIO_REG(0x24) -#define IXP2000_GPIO_LSHR IXP2000_GPIO_REG(0x28) -#define IXP2000_GPIO_LSLR IXP2000_GPIO_REG(0x2c) -#define IXP2000_GPIO_LDSR IXP2000_GPIO_REG(0x30) -#define IXP2000_GPIO_INER IXP2000_GPIO_REG(0x34) -#define IXP2000_GPIO_INSR IXP2000_GPIO_REG(0x38) -#define IXP2000_GPIO_INCR IXP2000_GPIO_REG(0x3c) -#define IXP2000_GPIO_INST IXP2000_GPIO_REG(0x40) - -/* - * "Global" registers...whatever that's supposed to mean. - */ -#define GLOBAL_REG_BASE (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00) -#define GLOBAL_REG(x) (volatile unsigned long*)(GLOBAL_REG_BASE | (x)) - -#define IXP2000_MAJ_PROD_TYPE_MASK 0x001F0000 -#define IXP2000_MAJ_PROD_TYPE_IXP2000 0x00000000 -#define IXP2000_MIN_PROD_TYPE_MASK 0x0000FF00 -#define IXP2000_MIN_PROD_TYPE_IXP2400 0x00000200 -#define IXP2000_MIN_PROD_TYPE_IXP2850 0x00000100 -#define IXP2000_MIN_PROD_TYPE_IXP2800 0x00000000 -#define IXP2000_MAJ_REV_MASK 0x000000F0 -#define IXP2000_MIN_REV_MASK 0x0000000F -#define IXP2000_PROD_ID_MASK 0xFFFFFFFF - -#define IXP2000_PRODUCT_ID GLOBAL_REG(0x00) -#define IXP2000_MISC_CONTROL GLOBAL_REG(0x04) -#define IXP2000_MSF_CLK_CNTRL GLOBAL_REG(0x08) -#define IXP2000_RESET0 GLOBAL_REG(0x0c) -#define IXP2000_RESET1 GLOBAL_REG(0x10) -#define IXP2000_CCR GLOBAL_REG(0x14) -#define IXP2000_STRAP_OPTIONS GLOBAL_REG(0x18) - -#define RSTALL (1 << 16) -#define WDT_RESET_ENABLE 0x01000000 - - -/* - * MSF registers. The IXP2400 and IXP2800 have somewhat different MSF - * units, but the registers that differ between the two don't overlap, - * so we can have one register list for both. - */ -#define IXP2000_MSF_REG(x) ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x))) -#define IXP2000_MSF_RX_CONTROL IXP2000_MSF_REG(0x0000) -#define IXP2000_MSF_TX_CONTROL IXP2000_MSF_REG(0x0004) -#define IXP2000_MSF_INTERRUPT_STATUS IXP2000_MSF_REG(0x0008) -#define IXP2000_MSF_INTERRUPT_ENABLE IXP2000_MSF_REG(0x000c) -#define IXP2000_MSF_CSIX_TYPE_MAP IXP2000_MSF_REG(0x0010) -#define IXP2000_MSF_FC_EGRESS_STATUS IXP2000_MSF_REG(0x0014) -#define IXP2000_MSF_FC_INGRESS_STATUS IXP2000_MSF_REG(0x0018) -#define IXP2000_MSF_HWM_CONTROL IXP2000_MSF_REG(0x0024) -#define IXP2000_MSF_FC_STATUS_OVERRIDE IXP2000_MSF_REG(0x0028) -#define IXP2000_MSF_CLOCK_CONTROL IXP2000_MSF_REG(0x002c) -#define IXP2000_MSF_RX_PORT_MAP IXP2000_MSF_REG(0x0040) -#define IXP2000_MSF_RBUF_ELEMENT_DONE IXP2000_MSF_REG(0x0044) -#define IXP2000_MSF_RX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0048) -#define IXP2000_MSF_RX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0048) -#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0 IXP2000_MSF_REG(0x0050) -#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1 IXP2000_MSF_REG(0x0054) -#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2 IXP2000_MSF_REG(0x0058) -#define IXP2000_MSF_TX_SEQUENCE_0 IXP2000_MSF_REG(0x0060) -#define IXP2000_MSF_TX_SEQUENCE_1 IXP2000_MSF_REG(0x0064) -#define IXP2000_MSF_TX_SEQUENCE_2 IXP2000_MSF_REG(0x0068) -#define IXP2000_MSF_TX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0070) -#define IXP2000_MSF_TX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0070) -#define IXP2000_MSF_RX_UP_CONTROL_0 IXP2000_MSF_REG(0x0080) -#define IXP2000_MSF_RX_UP_CONTROL_1 IXP2000_MSF_REG(0x0084) -#define IXP2000_MSF_RX_UP_CONTROL_2 IXP2000_MSF_REG(0x0088) -#define IXP2000_MSF_RX_UP_CONTROL_3 IXP2000_MSF_REG(0x008c) -#define IXP2000_MSF_TX_UP_CONTROL_0 IXP2000_MSF_REG(0x0090) -#define IXP2000_MSF_TX_UP_CONTROL_1 IXP2000_MSF_REG(0x0094) -#define IXP2000_MSF_TX_UP_CONTROL_2 IXP2000_MSF_REG(0x0098) -#define IXP2000_MSF_TX_UP_CONTROL_3 IXP2000_MSF_REG(0x009c) -#define IXP2000_MSF_TRAIN_DATA IXP2000_MSF_REG(0x00a0) -#define IXP2000_MSF_TRAIN_CALENDAR IXP2000_MSF_REG(0x00a4) -#define IXP2000_MSF_TRAIN_FLOW_CONTROL IXP2000_MSF_REG(0x00a8) -#define IXP2000_MSF_TX_CALENDAR_0 IXP2000_MSF_REG(0x1000) -#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS IXP2000_MSF_REG(0x1400) - - -#endif /* _IXP2000_H_ */ diff --git a/arch/arm/mach-ixp2000/include/mach/memory.h b/arch/arm/mach-ixp2000/include/mach/memory.h deleted file mode 100644 index 98e3471be15..00000000000 --- a/arch/arm/mach-ixp2000/include/mach/memory.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/memory.h - * - * Copyright (c) 2002 Intel Corp. - * Copyright (c) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -#define PHYS_OFFSET UL(0x00000000) - -#include <mach/ixp2000-regs.h> - -#define IXP2000_PCI_SDRAM_OFFSET (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0) - -#define __phys_to_bus(x) ((x) + (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET)) -#define __bus_to_phys(x) ((x) - (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET)) - -#define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v)) -#define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b)) -#define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p)) -#define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b)) - -#endif - diff --git a/arch/arm/mach-ixp2000/include/mach/platform.h b/arch/arm/mach-ixp2000/include/mach/platform.h deleted file mode 100644 index 42182c79ed9..00000000000 --- a/arch/arm/mach-ixp2000/include/mach/platform.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/platform.h - * - * Various bits of code used by platform-level code. - * - * Author: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2004 (c) MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - - -#ifndef __ASSEMBLY__ - -static inline unsigned long ixp2000_reg_read(volatile void *reg) -{ - return *((volatile unsigned long *)reg); -} - -static inline void ixp2000_reg_write(volatile void *reg, unsigned long val) -{ - *((volatile unsigned long *)reg) = val; -} - -/* - * On the IXP2400, we can't use XCB=000 due to chip bugs. We use - * XCB=101 instead, but that makes all I/O accesses bufferable. This - * is not a problem in general, but we do have to be slightly more - * careful because I/O writes are no longer automatically flushed out - * of the write buffer. - * - * In cases where we want to make sure that a write has been flushed - * out of the write buffer before we proceed, for example when masking - * a device interrupt before re-enabling IRQs in CPSR, we can use this - * function, ixp2000_reg_wrb, which performs a write, a readback, and - * issues a dummy instruction dependent on the value of the readback - * (mov rX, rX) to make sure that the readback has completed before we - * continue. - */ -static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val) -{ - unsigned long dummy; - - *((volatile unsigned long *)reg) = val; - - dummy = *((volatile unsigned long *)reg); - __asm__ __volatile__("mov %0, %0" : "+r" (dummy)); -} - -/* - * Boards may multiplex different devices on the 2nd channel of - * the slowport interface that each need different configuration - * settings. For example, the IXDP2400 uses channel 2 on the interface - * to access the CPLD, the switch fabric card, and the media card. Each - * one needs a different mode so drivers must save/restore the mode - * before and after each operation. - * - * acquire_slowport(&your_config); - * ... - * do slowport operations - * ... - * release_slowport(); - * - * Note that while you have the slowport, you are holding a spinlock, - * so your code should be written as if you explicitly acquired a lock. - * - * The configuration only affects device 2 on the slowport, so the - * MTD map driver does not acquire/release the slowport. - */ -struct slowport_cfg { - unsigned long CCR; /* Clock divide */ - unsigned long WTC; /* Write Timing Control */ - unsigned long RTC; /* Read Timing Control */ - unsigned long PCR; /* Protocol Control Register */ - unsigned long ADC; /* Address/Data Width Control */ -}; - - -void ixp2000_acquire_slowport(struct slowport_cfg *, struct slowport_cfg *); -void ixp2000_release_slowport(struct slowport_cfg *); - -/* - * IXP2400 A0/A1 and IXP2800 A0/A1/A2 have broken slowport that requires - * tweaking of addresses in the MTD driver. - */ -static inline unsigned ixp2000_has_broken_slowport(void) -{ - unsigned long id = *IXP2000_PRODUCT_ID; - unsigned long id_prod = id & (IXP2000_MAJ_PROD_TYPE_MASK | - IXP2000_MIN_PROD_TYPE_MASK); - return (((id_prod == - /* fixed in IXP2400-B0 */ - (IXP2000_MAJ_PROD_TYPE_IXP2000 | - IXP2000_MIN_PROD_TYPE_IXP2400)) && - ((id & IXP2000_MAJ_REV_MASK) == 0)) || - ((id_prod == - /* fixed in IXP2800-B0 */ - (IXP2000_MAJ_PROD_TYPE_IXP2000 | - IXP2000_MIN_PROD_TYPE_IXP2800)) && - ((id & IXP2000_MAJ_REV_MASK) == 0)) || - ((id_prod == - /* fixed in IXP2850-B0 */ - (IXP2000_MAJ_PROD_TYPE_IXP2000 | - IXP2000_MIN_PROD_TYPE_IXP2850)) && - ((id & IXP2000_MAJ_REV_MASK) == 0))); -} - -static inline unsigned int ixp2000_has_flash(void) -{ - return ((*IXP2000_STRAP_OPTIONS) & (CFG_BOOT_PROM)); -} - -static inline unsigned int ixp2000_is_pcimaster(void) -{ - return ((*IXP2000_STRAP_OPTIONS) & (CFG_PCI_BOOT_HOST)); -} - -void ixp2000_map_io(void); -void ixp2000_uart_init(void); -void ixp2000_init_irq(void); -void ixp2000_init_time(unsigned long); -unsigned long ixp2000_gettimeoffset(void); - -struct pci_sys_data; - -u32 *ixp2000_pci_config_addr(unsigned int bus, unsigned int devfn, int where); -void ixp2000_pci_preinit(void); -int ixp2000_pci_setup(int, struct pci_sys_data*); -struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*); -int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *); -int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32); - -/* - * Several of the IXP2000 systems have banked flash so we need to extend the - * flash_platform_data structure with some private pointers - */ -struct ixp2000_flash_data { - struct flash_platform_data *platform_data; - int nr_banks; - unsigned long (*bank_setup)(unsigned long); -}; - -struct ixp2000_i2c_pins { - unsigned long sda_pin; - unsigned long scl_pin; -}; - - -#endif /* !__ASSEMBLY__ */ diff --git a/arch/arm/mach-ixp2000/include/mach/system.h b/arch/arm/mach-ixp2000/include/mach/system.h deleted file mode 100644 index de370992c84..00000000000 --- a/arch/arm/mach-ixp2000/include/mach/system.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/system.h - * - * Copyright (C) 2002 Intel Corp. - * Copyricht (C) 2003-2005 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <mach/hardware.h> -#include <asm/mach-types.h> - -static inline void arch_idle(void) -{ - cpu_do_idle(); -} - -static inline void arch_reset(char mode, const char *cmd) -{ - local_irq_disable(); - - /* - * Reset flash banking register so that we are pointing at - * RedBoot bank. - */ - if (machine_is_ixdp2401()) { - ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG, - ((0 >> IXDP2X01_FLASH_WINDOW_BITS) - | IXDP2X01_CPLD_FLASH_INTERN)); - ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff); - } - - /* - * On IXDP2801 we need to write this magic sequence to the CPLD - * to cause a complete reset of the CPU and all external devices - * and move the flash bank register back to 0. - */ - if (machine_is_ixdp2801() || machine_is_ixdp28x5()) { - unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG; - - reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF); - ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg); - ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000); - } - - ixp2000_reg_wrb(IXP2000_RESET0, RSTALL); -} diff --git a/arch/arm/mach-ixp2000/include/mach/timex.h b/arch/arm/mach-ixp2000/include/mach/timex.h deleted file mode 100644 index 835e659f93d..00000000000 --- a/arch/arm/mach-ixp2000/include/mach/timex.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/timex.h - * - * IXP2000 architecture timex specifications - */ - - -/* - * Default clock is 50MHz APB, but platform code can override this - */ -#define CLOCK_TICK_RATE 50000000 - - diff --git a/arch/arm/mach-ixp2000/include/mach/uncompress.h b/arch/arm/mach-ixp2000/include/mach/uncompress.h deleted file mode 100644 index ce363087df7..00000000000 --- a/arch/arm/mach-ixp2000/include/mach/uncompress.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/uncompress.h - * - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2002 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include <linux/serial_reg.h> - -#define UART_BASE 0xc0030000 - -#define PHYS(x) ((volatile unsigned long *)(UART_BASE + x)) - -#define UARTDR PHYS(0x00) /* Transmit reg dlab=0 */ -#define UARTDLL PHYS(0x00) /* Divisor Latch reg dlab=1*/ -#define UARTDLM PHYS(0x04) /* Divisor Latch reg dlab=1*/ -#define UARTIER PHYS(0x04) /* Interrupt enable reg */ -#define UARTFCR PHYS(0x08) /* FIFO control reg dlab =0*/ -#define UARTLCR PHYS(0x0c) /* Control reg */ -#define UARTSR PHYS(0x14) /* Status reg */ - - -static inline void putc(int c) -{ - int j = 0x1000; - - while (--j && !(*UARTSR & UART_LSR_THRE)) - barrier(); - - *UARTDR = c; -} - -static inline void flush(void) -{ -} - -#define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-ixp2000/include/mach/vmalloc.h b/arch/arm/mach-ixp2000/include/mach/vmalloc.h deleted file mode 100644 index 61c8dae24f9..00000000000 --- a/arch/arm/mach-ixp2000/include/mach/vmalloc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/vmalloc.h - * - * Author: Naeem Afzal <naeem.m.afzal@intel.com> - * - * Copyright 2002 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_END 0xfb000000UL |