diff options
Diffstat (limited to 'arch/arm/mach-iop13xx')
21 files changed, 1883 insertions, 254 deletions
diff --git a/arch/arm/mach-iop13xx/Makefile.boot b/arch/arm/mach-iop13xx/Makefile.boot index 0b0e19fdfe6..3a8c38c3189 100644 --- a/arch/arm/mach-iop13xx/Makefile.boot +++ b/arch/arm/mach-iop13xx/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-iop13xx/include/mach/adma.h b/arch/arm/mach-iop13xx/include/mach/adma.h new file mode 100644 index 00000000000..a86fd0ed775 --- /dev/null +++ b/arch/arm/mach-iop13xx/include/mach/adma.h @@ -0,0 +1,621 @@ +/* + * Copyright(c) 2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#ifndef _ADMA_H +#define _ADMA_H +#include <linux/types.h> +#include <linux/io.h> +#include <mach/hardware.h> +#include <asm/hardware/iop_adma.h> + +#define ADMA_ACCR(chan) (chan->mmr_base + 0x0) +#define ADMA_ACSR(chan) (chan->mmr_base + 0x4) +#define ADMA_ADAR(chan) (chan->mmr_base + 0x8) +#define ADMA_IIPCR(chan) (chan->mmr_base + 0x18) +#define ADMA_IIPAR(chan) (chan->mmr_base + 0x1c) +#define ADMA_IIPUAR(chan) (chan->mmr_base + 0x20) +#define ADMA_ANDAR(chan) (chan->mmr_base + 0x24) +#define ADMA_ADCR(chan) (chan->mmr_base + 0x28) +#define ADMA_CARMD(chan) (chan->mmr_base + 0x2c) +#define ADMA_ABCR(chan) (chan->mmr_base + 0x30) +#define ADMA_DLADR(chan) (chan->mmr_base + 0x34) +#define ADMA_DUADR(chan) (chan->mmr_base + 0x38) +#define ADMA_SLAR(src, chan) (chan->mmr_base + (0x3c + (src << 3))) +#define ADMA_SUAR(src, chan) (chan->mmr_base + (0x40 + (src << 3))) + +struct iop13xx_adma_src { + u32 src_addr; + union { + u32 upper_src_addr; + struct { + unsigned int pq_upper_src_addr:24; + unsigned int pq_dmlt:8; + }; + }; +}; + +struct iop13xx_adma_desc_ctrl { + unsigned int int_en:1; + unsigned int xfer_dir:2; + unsigned int src_select:4; + unsigned int zero_result:1; + unsigned int block_fill_en:1; + unsigned int crc_gen_en:1; + unsigned int crc_xfer_dis:1; + unsigned int crc_seed_fetch_dis:1; + unsigned int status_write_back_en:1; + unsigned int endian_swap_en:1; + unsigned int reserved0:2; + unsigned int pq_update_xfer_en:1; + unsigned int dual_xor_en:1; + unsigned int pq_xfer_en:1; + unsigned int p_xfer_dis:1; + unsigned int reserved1:10; + unsigned int relax_order_en:1; + unsigned int no_snoop_en:1; +}; + +struct iop13xx_adma_byte_count { + unsigned int byte_count:24; + unsigned int host_if:3; + unsigned int reserved:2; + unsigned int zero_result_err_q:1; + unsigned int zero_result_err:1; + unsigned int tx_complete:1; +}; + +struct iop13xx_adma_desc_hw { + u32 next_desc; + union { + u32 desc_ctrl; + struct iop13xx_adma_desc_ctrl desc_ctrl_field; + }; + union { + u32 crc_addr; + u32 block_fill_data; + u32 q_dest_addr; + }; + union { + u32 byte_count; + struct iop13xx_adma_byte_count byte_count_field; + }; + union { + u32 dest_addr; + u32 p_dest_addr; + }; + union { + u32 upper_dest_addr; + u32 pq_upper_dest_addr; + }; + struct iop13xx_adma_src src[1]; +}; + +struct iop13xx_adma_desc_dual_xor { + u32 next_desc; + u32 desc_ctrl; + u32 reserved; + u32 byte_count; + u32 h_dest_addr; + u32 h_upper_dest_addr; + u32 src0_addr; + u32 upper_src0_addr; + u32 src1_addr; + u32 upper_src1_addr; + u32 h_src_addr; + u32 h_upper_src_addr; + u32 d_src_addr; + u32 d_upper_src_addr; + u32 d_dest_addr; + u32 d_upper_dest_addr; +}; + +struct iop13xx_adma_desc_pq_update { + u32 next_desc; + u32 desc_ctrl; + u32 reserved; + u32 byte_count; + u32 p_dest_addr; + u32 p_upper_dest_addr; + u32 src0_addr; + u32 upper_src0_addr; + u32 src1_addr; + u32 upper_src1_addr; + u32 p_src_addr; + u32 p_upper_src_addr; + u32 q_src_addr; + struct { + unsigned int q_upper_src_addr:24; + unsigned int q_dmlt:8; + }; + u32 q_dest_addr; + u32 q_upper_dest_addr; +}; + +static inline int iop_adma_get_max_xor(void) +{ + return 16; +} + +#define iop_adma_get_max_pq iop_adma_get_max_xor + +static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan) +{ + return __raw_readl(ADMA_ADAR(chan)); +} + +static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan, + u32 next_desc_addr) +{ + __raw_writel(next_desc_addr, ADMA_ANDAR(chan)); +} + +#define ADMA_STATUS_BUSY (1 << 13) + +static inline char iop_chan_is_busy(struct iop_adma_chan *chan) +{ + if (__raw_readl(ADMA_ACSR(chan)) & + ADMA_STATUS_BUSY) + return 1; + else + return 0; +} + +static inline int +iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots) +{ + return 1; +} +#define iop_desc_is_aligned(x, y) 1 + +static inline int +iop_chan_memcpy_slot_count(size_t len, int *slots_per_op) +{ + *slots_per_op = 1; + return 1; +} + +#define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s) + +static inline int +iop_chan_memset_slot_count(size_t len, int *slots_per_op) +{ + *slots_per_op = 1; + return 1; +} + +static inline int +iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op) +{ + static const char slot_count_table[] = { 1, 2, 2, 2, + 2, 3, 3, 3, + 3, 4, 4, 4, + 4, 5, 5, 5, + }; + *slots_per_op = slot_count_table[src_cnt - 1]; + return *slots_per_op; +} + +#define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024) +#define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT +#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT +#define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT +#define IOP_ADMA_PQ_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT +#define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o) +#define iop_chan_pq_slot_count iop_chan_xor_slot_count +#define iop_chan_pq_zero_sum_slot_count iop_chan_xor_slot_count + +static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->byte_count_field.byte_count; +} + +static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + int src_idx) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->src[src_idx].src_addr; +} + +static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->desc_ctrl_field.src_select + 1; +} + +static inline void +iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; + hw_desc->desc_ctrl = u_desc_ctrl.value; + hw_desc->crc_addr = 0; +} + +static inline void +iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ + u_desc_ctrl.field.block_fill_en = 1; + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; + hw_desc->desc_ctrl = u_desc_ctrl.value; + hw_desc->crc_addr = 0; +} + +/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ +static inline void +iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.src_select = src_cnt - 1; + u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; + hw_desc->desc_ctrl = u_desc_ctrl.value; + hw_desc->crc_addr = 0; + +} +#define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i) + +/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ +static inline int +iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.src_select = src_cnt - 1; + u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ + u_desc_ctrl.field.zero_result = 1; + u_desc_ctrl.field.status_write_back_en = 1; + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; + hw_desc->desc_ctrl = u_desc_ctrl.value; + hw_desc->crc_addr = 0; + + return 1; +} + +static inline void +iop_desc_init_pq(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.src_select = src_cnt - 1; + u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ + u_desc_ctrl.field.pq_xfer_en = 1; + u_desc_ctrl.field.p_xfer_dis = !!(flags & DMA_PREP_PQ_DISABLE_P); + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; + hw_desc->desc_ctrl = u_desc_ctrl.value; +} + +static inline void +iop_desc_init_pq_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.src_select = src_cnt - 1; + u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ + u_desc_ctrl.field.zero_result = 1; + u_desc_ctrl.field.status_write_back_en = 1; + u_desc_ctrl.field.pq_xfer_en = 1; + u_desc_ctrl.field.p_xfer_dis = !!(flags & DMA_PREP_PQ_DISABLE_P); + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; + hw_desc->desc_ctrl = u_desc_ctrl.value; +} + +static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + u32 byte_count) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + hw_desc->byte_count = byte_count; +} + +static inline void +iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) +{ + int slots_per_op = desc->slots_per_op; + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter; + int i = 0; + + if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { + hw_desc->byte_count = len; + } else { + do { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + i += slots_per_op; + } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT); + + if (len) { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iter->byte_count = len; + } + } +} + +#define iop_desc_set_pq_zero_sum_byte_count iop_desc_set_zero_sum_byte_count + +static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + dma_addr_t addr) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + hw_desc->dest_addr = addr; + hw_desc->upper_dest_addr = 0; +} + +static inline void +iop_desc_set_pq_addr(struct iop_adma_desc_slot *desc, dma_addr_t *addr) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + + hw_desc->dest_addr = addr[0]; + hw_desc->q_dest_addr = addr[1]; + hw_desc->upper_dest_addr = 0; +} + +static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc, + dma_addr_t addr) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + hw_desc->src[0].src_addr = addr; + hw_desc->src[0].upper_src_addr = 0; +} + +static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc, + int src_idx, dma_addr_t addr) +{ + int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter; + int i = 0; + + do { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iter->src[src_idx].src_addr = addr; + iter->src[src_idx].upper_src_addr = 0; + slot_cnt -= slots_per_op; + if (slot_cnt) { + i += slots_per_op; + addr += IOP_ADMA_XOR_MAX_BYTE_COUNT; + } + } while (slot_cnt); +} + +static inline void +iop_desc_set_pq_src_addr(struct iop_adma_desc_slot *desc, int src_idx, + dma_addr_t addr, unsigned char coef) +{ + int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter; + struct iop13xx_adma_src *src; + int i = 0; + + do { + iter = iop_hw_desc_slot_idx(hw_desc, i); + src = &iter->src[src_idx]; + src->src_addr = addr; + src->pq_upper_src_addr = 0; + src->pq_dmlt = coef; + slot_cnt -= slots_per_op; + if (slot_cnt) { + i += slots_per_op; + addr += IOP_ADMA_PQ_MAX_BYTE_COUNT; + } + } while (slot_cnt); +} + +static inline void +iop_desc_init_interrupt(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + iop_desc_init_memcpy(desc, 1); + iop_desc_set_byte_count(desc, chan, 0); + iop_desc_set_dest_addr(desc, chan, 0); + iop_desc_set_memcpy_src_addr(desc, 0); +} + +#define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr +#define iop_desc_set_pq_zero_sum_src_addr iop_desc_set_pq_src_addr + +static inline void +iop_desc_set_pq_zero_sum_addr(struct iop_adma_desc_slot *desc, int pq_idx, + dma_addr_t *src) +{ + iop_desc_set_xor_src_addr(desc, pq_idx, src[pq_idx]); + iop_desc_set_xor_src_addr(desc, pq_idx+1, src[pq_idx+1]); +} + +static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, + u32 next_desc_addr) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + + iop_paranoia(hw_desc->next_desc); + hw_desc->next_desc = next_desc_addr; +} + +static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->next_desc; +} + +static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + hw_desc->next_desc = 0; +} + +static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc, + u32 val) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + hw_desc->block_fill_data = val; +} + +static inline enum sum_check_flags +iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; + struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field; + enum sum_check_flags flags; + + BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result)); + + flags = byte_count.zero_result_err_q << SUM_CHECK_Q; + flags |= byte_count.zero_result_err << SUM_CHECK_P; + + return flags; +} + +static inline void iop_chan_append(struct iop_adma_chan *chan) +{ + u32 adma_accr; + + adma_accr = __raw_readl(ADMA_ACCR(chan)); + adma_accr |= 0x2; + __raw_writel(adma_accr, ADMA_ACCR(chan)); +} + +static inline u32 iop_chan_get_status(struct iop_adma_chan *chan) +{ + return __raw_readl(ADMA_ACSR(chan)); +} + +static inline void iop_chan_disable(struct iop_adma_chan *chan) +{ + u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan)); + adma_chan_ctrl &= ~0x1; + __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan)); +} + +static inline void iop_chan_enable(struct iop_adma_chan *chan) +{ + u32 adma_chan_ctrl; + + adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan)); + adma_chan_ctrl |= 0x1; + __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan)); +} + +static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(ADMA_ACSR(chan)); + status &= (1 << 12); + __raw_writel(status, ADMA_ACSR(chan)); +} + +static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(ADMA_ACSR(chan)); + status &= (1 << 11); + __raw_writel(status, ADMA_ACSR(chan)); +} + +static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(ADMA_ACSR(chan)); + status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3); + __raw_writel(status, ADMA_ACSR(chan)); +} + +static inline int +iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan) +{ + return test_bit(9, &status); +} + +static inline int +iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan) +{ + return test_bit(5, &status); +} + +static inline int +iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan) +{ + return test_bit(4, &status); +} + +static inline int +iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan) +{ + return test_bit(3, &status); +} + +static inline int +iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +static inline int +iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +static inline int +iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +#endif /* _ADMA_H */ diff --git a/arch/arm/mach-iop13xx/include/mach/entry-macro.S b/arch/arm/mach-iop13xx/include/mach/entry-macro.S new file mode 100644 index 00000000000..1a2d603488d --- /dev/null +++ b/arch/arm/mach-iop13xx/include/mach/entry-macro.S @@ -0,0 +1,42 @@ +/* + * iop13xx low level irq macros + * Copyright (c) 2005-2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple + * Place - Suite 330, Boston, MA 02111-1307 USA. + * + */ + .macro get_irqnr_preamble, base, tmp + mrc p15, 0, \tmp, c15, c1, 0 + orr \tmp, \tmp, #(1 << 6) + mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access + .endm + + /* + * Note: a 1-cycle window exists where iintvec will return the value + * of iintbase, so we explicitly check for "bad zeros" + */ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC + cmp \irqnr, #0 + mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero + adds \irqstat, \irqnr, #1 @ Check for 0xffffffff + movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + mrc p15, 0, \tmp1, c15, c1, 0 + ands \tmp2, \tmp1, #(1 << 6) + bicne \tmp1, \tmp1, #(1 << 6) + mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access + .endm diff --git a/arch/arm/mach-iop13xx/include/mach/hardware.h b/arch/arm/mach-iop13xx/include/mach/hardware.h new file mode 100644 index 00000000000..786fa266fab --- /dev/null +++ b/arch/arm/mach-iop13xx/include/mach/hardware.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H +#include <asm/types.h> + +#ifndef __ASSEMBLY__ +extern u16 iop13xx_dev_id(void); +extern void iop13xx_set_atu_mmr_bases(void); +#endif + +/* + * Generic chipset bits + * + */ +#include "iop13xx.h" + +/* + * Board specific bits + */ +#include "iq81340.h" + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h new file mode 100644 index 00000000000..17b40279e0a --- /dev/null +++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h @@ -0,0 +1,507 @@ +#ifndef _IOP13XX_HW_H_ +#define _IOP13XX_HW_H_ + +#ifndef __ASSEMBLY__ + +#include <linux/reboot.h> + +/* The ATU offsets can change based on the strapping */ +extern u32 iop13xx_atux_pmmr_offset; +extern u32 iop13xx_atue_pmmr_offset; +void iop13xx_init_early(void); +void iop13xx_init_irq(void); +void iop13xx_map_io(void); +void iop13xx_platform_init(void); +void iop13xx_add_tpmi_devices(void); +void iop13xx_init_irq(void); +void iop13xx_restart(enum reboot_mode, const char *); + +/* CPUID CP6 R0 Page 0 */ +static inline int iop13xx_cpu_id(void) +{ + int id; + asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id)); + return id; +} + +/* WDTCR CP6 R7 Page 9 */ +static inline u32 read_wdtcr(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val)); + return val; +} +static inline void write_wdtcr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val)); +} + +/* WDTSR CP6 R8 Page 9 */ +static inline u32 read_wdtsr(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val)); + return val; +} +static inline void write_wdtsr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val)); +} + +/* RCSR - Reset Cause Status Register */ +static inline u32 read_rcsr(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val)); + return val; +} + +extern unsigned long get_iop_tick_rate(void); +#endif + +/* + * IOP13XX I/O and Mem space regions for PCI autoconfiguration + */ +#define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */ +#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE + +/* PCI MAP + * bus range cpu phys cpu virt note + * 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM + * 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window + * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window + * + * IO MAP + * 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window + * 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window + */ +#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL +#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */ + +#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL +#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL +#define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET) +#define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\ + IOP13XX_PCIX_LOWER_MEM_BA) +#define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\ + IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) +#define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\ + IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) + +#define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL +#define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE +#define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\ + IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) +#define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\ + IOP13XX_PCIX_LOWER_MEM_BA) + +/* PCI-E ranges */ +#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL +#define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */ + +#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL +#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL +#define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET) +#define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\ + IOP13XX_PCIE_LOWER_MEM_BA) +#define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\ + IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) +#define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\ + IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) + +/* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */ +#define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL +#define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE +#define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\ + IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) +#define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\ + IOP13XX_PCIE_LOWER_MEM_BA) + +/* PBI Ranges */ +#define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL +#define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL +#define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL +#define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE +#define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\ + IOP13XX_PBI_MEM_WINDOW_SIZE - 1) + +/* + * IOP13XX chipset registers + */ +#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */ +#define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL) /* PMMR phys. address */ +#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000 +#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\ + IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) +#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\ + IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) +#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\ + + IOP13XX_PMMR_PHYS_MEM_BASE) +#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\ + + IOP13XX_PMMR_VIRT_MEM_BASE) +#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) +#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) +#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) +#define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) +#define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) +#define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) +#define IOP13XX_PMMR_SIZE 0x00080000 + +/*=================== Defines for Platform Devices =====================*/ +#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300) +#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340) +#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300) +#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340) + +#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500) +#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520) +#define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540) +#define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500) +#define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520) +#define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540) + +/* ATU selection flags */ +/* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */ +#define IOP13XX_INIT_ATU_DEFAULT (0) +#define IOP13XX_INIT_ATU_ATUX (1 << 0) +#define IOP13XX_INIT_ATU_ATUE (1 << 1) +#define IOP13XX_INIT_ATU_NONE (1 << 2) + +/* UART selection flags */ +/* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */ +#define IOP13XX_INIT_UART_DEFAULT (0) +#define IOP13XX_INIT_UART_0 (1 << 0) +#define IOP13XX_INIT_UART_1 (1 << 1) + +/* I2C selection flags */ +/* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */ +#define IOP13XX_INIT_I2C_DEFAULT (0) +#define IOP13XX_INIT_I2C_0 (1 << 0) +#define IOP13XX_INIT_I2C_1 (1 << 1) +#define IOP13XX_INIT_I2C_2 (1 << 2) + +/* ADMA selection flags */ +/* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */ +#define IOP13XX_INIT_ADMA_DEFAULT (0) +#define IOP13XX_INIT_ADMA_0 (1 << 0) +#define IOP13XX_INIT_ADMA_1 (1 << 1) +#define IOP13XX_INIT_ADMA_2 (1 << 2) + +/* Platform devices */ +#define IQ81340_NUM_UART 2 +#define IQ81340_NUM_I2C 3 +#define IQ81340_NUM_PHYS_MAP_FLASH 1 +#define IQ81340_NUM_ADMA 3 +#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \ + IQ81340_NUM_I2C + \ + IQ81340_NUM_PHYS_MAP_FLASH + \ + IQ81340_NUM_ADMA) + +/*========================== PMMR offsets for key registers ============*/ +#define IOP13XX_ATU0_PMMR_OFFSET 0x00048000 +#define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000 +#define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000 +#define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000 +#define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200 +#define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400 +#define IOP13XX_PBI_PMMR_OFFSET 0x00001580 +#define IOP13XX_MU_PMMR_OFFSET 0x00004000 +#define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188 +#define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188) + +#define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */ +#define IOP13XX_CONTROLLER_ONLY (1 << 14) +#define IOP13XX_INTERFACE_SEL_PCIX (1 << 15) + +#define IOP13XX_PMON_PMMR_OFFSET 0x0001A000 +#define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\ + IOP13XX_PMON_PMMR_OFFSET) +#define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\ + IOP13XX_PMON_PMMR_OFFSET) + +#define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0) +#define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4) +#define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8) +#define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC) + +#define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30) +#define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34) +#define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38) +#define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C) + +#define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70) +#define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74) +#define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78) +#define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C) + +#define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040) +#define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044) + +/*================================ATU===================================*/ +#define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\ + iop13xx_atux_pmmr_offset + (ofs)) + +#define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\ + iop13xx_atux_pmmr_offset + 0x2) + +#define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\ + iop13xx_atux_pmmr_offset + 0x4) +#define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\ + iop13xx_atux_pmmr_offset + 0x6) + +#define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10) +#define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14) +#define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18) +#define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c) +#define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20) +#define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24) +#define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40) +#define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44) +#define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48) +#define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c) +#define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50) +#define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54) +#define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58) +#define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c) +#define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60) +#define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70) +#define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74) +#define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78) +#define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4) +#define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200) +#define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204) +#define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208) +#define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c) +#define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210) + +#define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300) +#define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304) +#define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308) +#define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c) +#define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310) +#define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314) +#define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318) +#define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c) +#define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320) +#define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324) +#define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328) +#define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c) +#define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330) +#define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334) + +#define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1) +#define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25) +#define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21) +#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15) +#define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14) +#define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16) + +#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18) +#define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17) +#define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16) +#define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15) +#define IOP13XX_ATUX_STAT_ERR_COR (1 << 14) +#define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13) +#define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12) +#define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11) +#define IOP13XX_ATUX_STAT_TX_SERR (1 << 10) +#define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 ) +#define IOP13XX_ATUX_STAT_BIST (1 << 8 ) +#define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 ) +#define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 ) +#define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 ) +#define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 ) +#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 ) +#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 ) + +#define IOP13XX_ATUX_PCIXSR_BUS_NUM (8) +#define IOP13XX_ATUX_PCIXSR_DEV_NUM (3) +#define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0) + +#define IOP13XX_ATUX_IALR_DISABLE 0x00000001 +#define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000 + +#define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\ + iop13xx_atue_pmmr_offset + (ofs)) + +#define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\ + iop13xx_atue_pmmr_offset + 0x2) +#define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\ + iop13xx_atue_pmmr_offset + 0x4) +#define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\ + iop13xx_atue_pmmr_offset + 0x6) + +#define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10) +#define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14) +#define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18) +#define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c) +#define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20) +#define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24) +#define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40) +#define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44) +#define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48) +#define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c) +#define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50) +#define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54) +#define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58) +#define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c) +#define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60) +#define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\ + iop13xx_atue_pmmr_offset + 0xe2) +#define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304) +#define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308) +#define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c) +#define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310) +#define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314) +#define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318) +#define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c) +#define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320) +#define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324) + +#define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70) +#define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74) +#define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78) +#define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300) +#define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c) +#define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330) + +#define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384) +#define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388) + +#define IOP13XX_ATUE_ATUCR_IVM (1 << 6) +#define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1) +#define IOP13XX_ATUE_OCCAR_BUS_NUM (24) +#define IOP13XX_ATUE_OCCAR_DEV_NUM (19) +#define IOP13XX_ATUE_OCCAR_FUNC_NUM (16) +#define IOP13XX_ATUE_OCCAR_EXT_REG (8) +#define IOP13XX_ATUE_OCCAR_REG (2) + +#define IOP13XX_ATUE_PCSR_BUS_NUM (24) +#define IOP13XX_ATUE_PCSR_DEV_NUM (19) +#define IOP13XX_ATUE_PCSR_FUNC_NUM (16) +#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15) +#define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14) +#define IOP13XX_ATUE_PCSR_END_POINT (1 << 13) +#define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12) + +#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff) +#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f) +#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7) + +#define IOP13XX_ATUE_PCSR_CORE_RESET (8) +#define IOP13XX_ATUE_PCSR_FUNC_NUM (16) + +#define IOP13XX_ATUE_LSTS_TRAINING (1 << 11) +#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28) +#define IOP13XX_ATUE_STAT_PME (1 << 27) +#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26) +#define IOP13XX_ATUE_STAT_IVM (1 << 25) +#define IOP13XX_ATUE_STAT_BIST (1 << 24) +#define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18) +#define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17) +#define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16) +#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13) +#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12) +#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11) +#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10) +#define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 ) +#define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 ) +#define IOP13XX_ATUE_STAT_CRS (1 << 7 ) +#define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 ) +#define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 ) +#define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 ) +#define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 ) +#define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 ) +#define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 ) +#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 ) + +#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31) +#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30) +#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29) +#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28) +#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20) +#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19) +#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18) +#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17) +#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16) +#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15) +#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14) +#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13) +#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12) +#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 ) +#define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 ) + +#define IOP13XX_ATUE_IALR_DISABLE (0x00000001) +#define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000) +#define IOP13XX_ATU_OUMBAR_FUNC_NUM (28) +#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7) +/*=======================================================================*/ + +/*============================MESSAGING UNIT=============================*/ +#define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\ + (ofs)) + +#define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10) +#define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14) +#define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18) +#define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C) +#define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20) +#define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24) +#define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28) +#define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C) +#define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30) +#define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34) +#define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38) +#define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C) +#define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48) +#define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50) +#define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54) +#define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84) + +#define IOP13XX_MU_WINDOW_SIZE (8 * 1024) +#define IOP13XX_MU_BASE_PHYS (0xff000000) +#define IOP13XX_MU_BASE_PCI (0xff000000) +#define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48) +#define IOP13XX_MU_MIMR_CORE_SELECT (15) +/*=======================================================================*/ + +/*==============================ADMA UNITS===============================*/ +#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9)) +#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0) + +/*==============================XSI BRIDGE===============================*/ +#define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c) +#define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790) +#define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794) +#define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \ + IOP13XX_PMMR_VIRT_TO_PHYS(\ + IOP13XX_ATUE_OCCDR))\ + && (__raw_readl(IOP13XX_XBG_BECSR) & 1)) +#define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \ + IOP13XX_PMMR_VIRT_TO_PHYS(\ + IOP13XX_ATUX_OCCDR))\ + && (__raw_readl(IOP13XX_XBG_BECSR) & 1)) +/*=======================================================================*/ + +#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\ + (ofs)) + +#define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0) +#define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4) +#define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8) +#define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc) +#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10) +#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) + +#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180) + +/* Watchdog timer definitions */ +#define IOP_WDTCR_EN_ARM 0x1e1e1e1e +#define IOP_WDTCR_EN 0xe1e1e1e1 +#define IOP_WDTCR_DIS_ARM 0x1f1f1f1f +#define IOP_WDTCR_DIS 0xf1f1f1f1 +#define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */ +#define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */ +#define IOP13XX_WDTCR_IB_RESET (1 << 0) + +#endif /* _IOP13XX_HW_H_ */ diff --git a/arch/arm/mach-iop13xx/include/mach/iq81340.h b/arch/arm/mach-iop13xx/include/mach/iq81340.h new file mode 100644 index 00000000000..ba2cf931e9c --- /dev/null +++ b/arch/arm/mach-iop13xx/include/mach/iq81340.h @@ -0,0 +1,28 @@ +#ifndef _IQ81340_H_ +#define _IQ81340_H_ + +#define IQ81340_PCE_BAR0 IOP13XX_PBI_LOWER_MEM_RA +#define IQ81340_PCE_BAR1 (IQ81340_PCE_BAR0 + 0x02000000) + +#define IQ81340_FLASHBASE IQ81340_PCE_BAR0 /* Flash */ + +#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a)) + +#define IQ81340_PRD_CODE IQ81340_PCE_BAR1_OFFSET(0) +#define IQ81340_BRD_STEP IQ81340_PCE_BAR1_OFFSET(0x10000) +#define IQ81340_CPLD_REV IQ81340_PCE_BAR1_OFFSET(0x20000) +#define IQ81340_LED IQ81340_PCE_BAR1_OFFSET(0x30000) +#define IQ81340_LHEX IQ81340_PCE_BAR1_OFFSET(0x40000) +#define IQ81340_RHEX IQ81340_PCE_BAR1_OFFSET(0x50000) +#define IQ81340_BUZZER IQ81340_PCE_BAR1_OFFSET(0x60000) +#define IQ81340_32K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x70000) +#define IQ81340_256K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x80000) +#define IQ81340_ROTARY_SW IQ81340_PCE_BAR1_OFFSET(0xd0000) +#define IQ81340_BATT_STAT IQ81340_PCE_BAR1_OFFSET(0xf0000) +#define IQ81340_CMP_FLSH IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */ + +#define PBI_CF_IDE_BASE (IQ81340_CMP_FLSH) +#define PBI_CF_BAR_ADDR (IOP13XX_PBI_BAR1) + + +#endif /* _IQ81340_H_ */ diff --git a/arch/arm/mach-iop13xx/include/mach/irqs.h b/arch/arm/mach-iop13xx/include/mach/irqs.h new file mode 100644 index 00000000000..e8d24d32121 --- /dev/null +++ b/arch/arm/mach-iop13xx/include/mach/irqs.h @@ -0,0 +1,194 @@ +#ifndef _IOP13XX_IRQS_H_ +#define _IOP13XX_IRQS_H_ + +#ifndef __ASSEMBLER__ +#include <linux/types.h> + +/* INTPND0 CP6 R0 Page 3 + */ +static inline u32 read_intpnd_0(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val)); + return val; +} + +/* INTPND1 CP6 R1 Page 3 + */ +static inline u32 read_intpnd_1(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val)); + return val; +} + +/* INTPND2 CP6 R2 Page 3 + */ +static inline u32 read_intpnd_2(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val)); + return val; +} + +/* INTPND3 CP6 R3 Page 3 + */ +static inline u32 read_intpnd_3(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val)); + return val; +} +#endif + +#define INTBASE 0 +#define INTSIZE_4 1 + +/* + * iop34x chipset interrupts + */ +#define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x)) + +/* + * On IRQ or FIQ register + */ +#define IRQ_IOP13XX_ADMA0_EOT (0) +#define IRQ_IOP13XX_ADMA0_EOC (1) +#define IRQ_IOP13XX_ADMA1_EOT (2) +#define IRQ_IOP13XX_ADMA1_EOC (3) +#define IRQ_IOP13XX_ADMA2_EOT (4) +#define IRQ_IOP13XX_ADMA2_EOC (5) +#define IRQ_IOP134_WATCHDOG (6) +#define IRQ_IOP13XX_RSVD_7 (7) +#define IRQ_IOP13XX_TIMER0 (8) +#define IRQ_IOP13XX_TIMER1 (9) +#define IRQ_IOP13XX_I2C_0 (10) +#define IRQ_IOP13XX_I2C_1 (11) +#define IRQ_IOP13XX_MSG (12) +#define IRQ_IOP13XX_MSGIBQ (13) +#define IRQ_IOP13XX_ATU_IM (14) +#define IRQ_IOP13XX_ATU_BIST (15) +#define IRQ_IOP13XX_PPMU (16) +#define IRQ_IOP13XX_COREPMU (17) +#define IRQ_IOP13XX_CORECACHE (18) +#define IRQ_IOP13XX_RSVD_19 (19) +#define IRQ_IOP13XX_RSVD_20 (20) +#define IRQ_IOP13XX_RSVD_21 (21) +#define IRQ_IOP13XX_RSVD_22 (22) +#define IRQ_IOP13XX_RSVD_23 (23) +#define IRQ_IOP13XX_XINT0 (24) +#define IRQ_IOP13XX_XINT1 (25) +#define IRQ_IOP13XX_XINT2 (26) +#define IRQ_IOP13XX_XINT3 (27) +#define IRQ_IOP13XX_XINT4 (28) +#define IRQ_IOP13XX_XINT5 (29) +#define IRQ_IOP13XX_XINT6 (30) +#define IRQ_IOP13XX_XINT7 (31) + /* IINTSRC1 bit */ +#define IRQ_IOP13XX_XINT8 (32) /* 0 */ +#define IRQ_IOP13XX_XINT9 (33) /* 1 */ +#define IRQ_IOP13XX_XINT10 (34) /* 2 */ +#define IRQ_IOP13XX_XINT11 (35) /* 3 */ +#define IRQ_IOP13XX_XINT12 (36) /* 4 */ +#define IRQ_IOP13XX_XINT13 (37) /* 5 */ +#define IRQ_IOP13XX_XINT14 (38) /* 6 */ +#define IRQ_IOP13XX_XINT15 (39) /* 7 */ +#define IRQ_IOP13XX_RSVD_40 (40) /* 8 */ +#define IRQ_IOP13XX_RSVD_41 (41) /* 9 */ +#define IRQ_IOP13XX_RSVD_42 (42) /* 10 */ +#define IRQ_IOP13XX_RSVD_43 (43) /* 11 */ +#define IRQ_IOP13XX_RSVD_44 (44) /* 12 */ +#define IRQ_IOP13XX_RSVD_45 (45) /* 13 */ +#define IRQ_IOP13XX_RSVD_46 (46) /* 14 */ +#define IRQ_IOP13XX_RSVD_47 (47) /* 15 */ +#define IRQ_IOP13XX_RSVD_48 (48) /* 16 */ +#define IRQ_IOP13XX_RSVD_49 (49) /* 17 */ +#define IRQ_IOP13XX_RSVD_50 (50) /* 18 */ +#define IRQ_IOP13XX_UART0 (51) /* 19 */ +#define IRQ_IOP13XX_UART1 (52) /* 20 */ +#define IRQ_IOP13XX_PBIE (53) /* 21 */ +#define IRQ_IOP13XX_ATU_CRW (54) /* 22 */ +#define IRQ_IOP13XX_ATU_ERR (55) /* 23 */ +#define IRQ_IOP13XX_MCU_ERR (56) /* 24 */ +#define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */ +#define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */ +#define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */ +#define IRQ_IOP13XX_RSVD_60 (60) /* 28 */ +#define IRQ_IOP13XX_RSVD_61 (61) /* 29 */ +#define IRQ_IOP13XX_MSG_ERR (62) /* 30 */ +#define IRQ_IOP13XX_RSVD_63 (63) /* 31 */ + /* IINTSRC2 bit */ +#define IRQ_IOP13XX_INTERPROC (64) /* 0 */ +#define IRQ_IOP13XX_RSVD_65 (65) /* 1 */ +#define IRQ_IOP13XX_RSVD_66 (66) /* 2 */ +#define IRQ_IOP13XX_RSVD_67 (67) /* 3 */ +#define IRQ_IOP13XX_RSVD_68 (68) /* 4 */ +#define IRQ_IOP13XX_RSVD_69 (69) /* 5 */ +#define IRQ_IOP13XX_RSVD_70 (70) /* 6 */ +#define IRQ_IOP13XX_RSVD_71 (71) /* 7 */ +#define IRQ_IOP13XX_RSVD_72 (72) /* 8 */ +#define IRQ_IOP13XX_RSVD_73 (73) /* 9 */ +#define IRQ_IOP13XX_RSVD_74 (74) /* 10 */ +#define IRQ_IOP13XX_RSVD_75 (75) /* 11 */ +#define IRQ_IOP13XX_RSVD_76 (76) /* 12 */ +#define IRQ_IOP13XX_RSVD_77 (77) /* 13 */ +#define IRQ_IOP13XX_RSVD_78 (78) /* 14 */ +#define IRQ_IOP13XX_RSVD_79 (79) /* 15 */ +#define IRQ_IOP13XX_RSVD_80 (80) /* 16 */ +#define IRQ_IOP13XX_RSVD_81 (81) /* 17 */ +#define IRQ_IOP13XX_RSVD_82 (82) /* 18 */ +#define IRQ_IOP13XX_RSVD_83 (83) /* 19 */ +#define IRQ_IOP13XX_RSVD_84 (84) /* 20 */ +#define IRQ_IOP13XX_RSVD_85 (85) /* 21 */ +#define IRQ_IOP13XX_RSVD_86 (86) /* 22 */ +#define IRQ_IOP13XX_RSVD_87 (87) /* 23 */ +#define IRQ_IOP13XX_RSVD_88 (88) /* 24 */ +#define IRQ_IOP13XX_RSVD_89 (89) /* 25 */ +#define IRQ_IOP13XX_RSVD_90 (90) /* 26 */ +#define IRQ_IOP13XX_RSVD_91 (91) /* 27 */ +#define IRQ_IOP13XX_RSVD_92 (92) /* 28 */ +#define IRQ_IOP13XX_RSVD_93 (93) /* 29 */ +#define IRQ_IOP13XX_SIB_ERR (94) /* 30 */ +#define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */ + /* IINTSRC3 bit */ +#define IRQ_IOP13XX_I2C_2 (96) /* 0 */ +#define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */ +#define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */ +#define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */ +#define IRQ_IOP13XX_IMU (100) /* 4 */ +#define IRQ_IOP13XX_RSVD_101 (101) /* 5 */ +#define IRQ_IOP13XX_RSVD_102 (102) /* 6 */ +#define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */ +#define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */ +#define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */ +#define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */ +#define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */ +#define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */ +#define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */ +#define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */ +#define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */ +#define IRQ_IOP13XX_RSVD_112 (112) /* 16 */ +#define IRQ_IOP13XX_INBD_MSI (113) /* 17 */ +#define IRQ_IOP13XX_RSVD_114 (114) /* 18 */ +#define IRQ_IOP13XX_RSVD_115 (115) /* 19 */ +#define IRQ_IOP13XX_RSVD_116 (116) /* 20 */ +#define IRQ_IOP13XX_RSVD_117 (117) /* 21 */ +#define IRQ_IOP13XX_RSVD_118 (118) /* 22 */ +#define IRQ_IOP13XX_RSVD_119 (119) /* 23 */ +#define IRQ_IOP13XX_RSVD_120 (120) /* 24 */ +#define IRQ_IOP13XX_RSVD_121 (121) /* 25 */ +#define IRQ_IOP13XX_RSVD_122 (122) /* 26 */ +#define IRQ_IOP13XX_RSVD_123 (123) /* 27 */ +#define IRQ_IOP13XX_RSVD_124 (124) /* 28 */ +#define IRQ_IOP13XX_RSVD_125 (125) /* 29 */ +#define IRQ_IOP13XX_RSVD_126 (126) /* 30 */ +#define IRQ_IOP13XX_HPI (127) /* 31 */ + +#ifdef CONFIG_PCI_MSI +#define IRQ_IOP13XX_MSI_0 (IRQ_IOP13XX_HPI + 1) +#define NR_IOP13XX_IRQS (IRQ_IOP13XX_MSI_0 + 128) +#else +#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1) +#endif + +#endif /* _IOP13XX_IRQ_H_ */ diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h new file mode 100644 index 00000000000..7c032d0ab24 --- /dev/null +++ b/arch/arm/mach-iop13xx/include/mach/memory.h @@ -0,0 +1,72 @@ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#include <mach/hardware.h> + +/* + * Physical DRAM offset. + */ +#define PLAT_PHYS_OFFSET UL(0x00000000) + +#ifndef __ASSEMBLY__ + +#if defined(CONFIG_ARCH_IOP13XX) +#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE) +#define IOP13XX_PMMR_V_END (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE) +#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE) +#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE) + +static inline dma_addr_t __virt_to_lbus(void __iomem *x) +{ + return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE; +} + +static inline void __iomem *__lbus_to_virt(dma_addr_t x) +{ + return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE; +} + +#define __is_lbus_dma(a) \ + ((a) >= IOP13XX_PMMR_P_START && (a) < IOP13XX_PMMR_P_END) + +#define __is_lbus_virt(a) \ + ((a) >= IOP13XX_PMMR_V_START && (a) < IOP13XX_PMMR_V_END) + +/* Device is an lbus device if it is on the platform bus of the IOP13XX */ +#define is_lbus_device(dev) \ + (dev && strncmp(dev->bus->name, "platform", 8) == 0) + +#define __arch_dma_to_virt(dev, addr) \ + ({ \ + void * __virt; \ + dma_addr_t __dma = addr; \ + if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \ + __virt = __lbus_to_virt(__dma); \ + else \ + __virt = (void *)__phys_to_virt(__dma); \ + __virt; \ + }) + +#define __arch_virt_to_dma(dev, addr) \ + ({ \ + void * __virt = addr; \ + dma_addr_t __dma; \ + if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \ + __dma = __virt_to_lbus(__virt); \ + else \ + __dma = __virt_to_phys((unsigned long)__virt); \ + __dma; \ + }) + +#define __arch_pfn_to_dma(dev, pfn) \ + ({ \ + /* __is_lbus_virt() can never be true for RAM pages */ \ + (dma_addr_t)__pfn_to_phys(pfn); \ + }) + +#define __arch_dma_to_pfn(dev, addr) __phys_to_pfn(addr) + +#endif /* CONFIG_ARCH_IOP13XX */ +#endif /* !ASSEMBLY */ + +#endif diff --git a/arch/arm/mach-iop13xx/include/mach/msi.h b/arch/arm/mach-iop13xx/include/mach/msi.h new file mode 100644 index 00000000000..b80c5ae17e9 --- /dev/null +++ b/arch/arm/mach-iop13xx/include/mach/msi.h @@ -0,0 +1,11 @@ +#ifndef _IOP13XX_MSI_H_ +#define _IOP13XX_MSI_H_ +#ifdef CONFIG_PCI_MSI +void iop13xx_msi_init(void); +#else +static inline void iop13xx_msi_init(void) +{ + return; +} +#endif +#endif diff --git a/arch/arm/mach-iop13xx/include/mach/pci.h b/arch/arm/mach-iop13xx/include/mach/pci.h new file mode 100644 index 00000000000..59f42b53557 --- /dev/null +++ b/arch/arm/mach-iop13xx/include/mach/pci.h @@ -0,0 +1,57 @@ +#ifndef _IOP13XX_PCI_H_ +#define _IOP13XX_PCI_H_ +#include <linux/io.h> +#include <mach/irqs.h> + +struct pci_sys_data; +struct hw_pci; +int iop13xx_pci_setup(int nr, struct pci_sys_data *sys); +struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *); +void iop13xx_atu_select(struct hw_pci *plat_pci); +void iop13xx_pci_init(void); +void iop13xx_map_pci_memory(void); + +#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY | \ + PCI_STATUS_SIG_TARGET_ABORT | \ + PCI_STATUS_REC_TARGET_ABORT | \ + PCI_STATUS_REC_TARGET_ABORT | \ + PCI_STATUS_REC_MASTER_ABORT | \ + PCI_STATUS_SIG_SYSTEM_ERROR | \ + PCI_STATUS_DETECTED_PARITY) + +#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR | \ + IOP13XX_ATUE_STAT_ROOT_SYS_ERR | \ + IOP13XX_ATUE_STAT_PCI_IFACE_ERR | \ + IOP13XX_ATUE_STAT_ERR_COR | \ + IOP13XX_ATUE_STAT_ERR_UNCOR | \ + IOP13XX_ATUE_STAT_CRS | \ + IOP13XX_ATUE_STAT_DET_PAR_ERR | \ + IOP13XX_ATUE_STAT_EXT_REC_MABORT | \ + IOP13XX_ATUE_STAT_SIG_TABORT | \ + IOP13XX_ATUE_STAT_EXT_REC_TABORT | \ + IOP13XX_ATUE_STAT_MASTER_DATA_PAR) + +#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM | \ + IOP13XX_ATUX_STAT_REC_SCEM | \ + IOP13XX_ATUX_STAT_TX_SERR | \ + IOP13XX_ATUX_STAT_DET_PAR_ERR | \ + IOP13XX_ATUX_STAT_INT_REC_MABORT | \ + IOP13XX_ATUX_STAT_REC_SERR | \ + IOP13XX_ATUX_STAT_EXT_REC_MABORT | \ + IOP13XX_ATUX_STAT_EXT_REC_TABORT | \ + IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \ + IOP13XX_ATUX_STAT_MASTER_DATA_PAR) + +/* PCI interrupts + */ +#define ATUX_INTA IRQ_IOP13XX_XINT0 +#define ATUX_INTB IRQ_IOP13XX_XINT1 +#define ATUX_INTC IRQ_IOP13XX_XINT2 +#define ATUX_INTD IRQ_IOP13XX_XINT3 + +#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA +#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB +#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC +#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD + +#endif /* _IOP13XX_PCI_H_ */ diff --git a/arch/arm/mach-iop13xx/include/mach/time.h b/arch/arm/mach-iop13xx/include/mach/time.h new file mode 100644 index 00000000000..15bc9bb78a6 --- /dev/null +++ b/arch/arm/mach-iop13xx/include/mach/time.h @@ -0,0 +1,126 @@ +#ifndef _IOP13XX_TIME_H_ +#define _IOP13XX_TIME_H_ + +#include <mach/irqs.h> + +#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0 + +#define IOP_TMR_EN 0x02 +#define IOP_TMR_RELOAD 0x04 +#define IOP_TMR_PRIVILEGED 0x08 +#define IOP_TMR_RATIO_1_1 0x00 + +#define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19) +#define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19) +#define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19) +#define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19) +#define IOP13XX_CORE_FREQ_MASK (7 << 16) +#define IOP13XX_CORE_FREQ_600 (0 << 16) +#define IOP13XX_CORE_FREQ_667 (1 << 16) +#define IOP13XX_CORE_FREQ_800 (2 << 16) +#define IOP13XX_CORE_FREQ_933 (3 << 16) +#define IOP13XX_CORE_FREQ_1000 (4 << 16) +#define IOP13XX_CORE_FREQ_1200 (5 << 16) + +void iop_init_time(unsigned long tickrate); + +static inline unsigned long iop13xx_core_freq(void) +{ + unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ); + freq &= IOP13XX_CORE_FREQ_MASK; + switch (freq) { + case IOP13XX_CORE_FREQ_600: + return 600000000; + case IOP13XX_CORE_FREQ_667: + return 667000000; + case IOP13XX_CORE_FREQ_800: + return 800000000; + case IOP13XX_CORE_FREQ_933: + return 933000000; + case IOP13XX_CORE_FREQ_1000: + return 1000000000; + case IOP13XX_CORE_FREQ_1200: + return 1200000000; + default: + printk("%s: warning unknown frequency, defaulting to 800Mhz\n", + __func__); + } + + return 800000000; +} + +static inline unsigned long iop13xx_xsi_bus_ratio(void) +{ + unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ); + ratio &= IOP13XX_XSI_FREQ_RATIO_MASK; + switch (ratio) { + case IOP13XX_XSI_FREQ_RATIO_2: + return 2; + case IOP13XX_XSI_FREQ_RATIO_3: + return 3; + case IOP13XX_XSI_FREQ_RATIO_4: + return 4; + default: + printk("%s: warning unknown ratio, defaulting to 2\n", + __func__); + } + + return 2; +} + +static inline u32 read_tmr0(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val)); + return val; +} + +static inline void write_tmr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); +} + +static inline void write_tmr1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val)); +} + +static inline u32 read_tcr0(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val)); + return val; +} + +static inline void write_tcr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c2, c9, 0" : : "r" (val)); +} + +static inline u32 read_tcr1(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val)); + return val; +} + +static inline void write_tcr1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c3, c9, 0" : : "r" (val)); +} + +static inline void write_trr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val)); +} + +static inline void write_trr1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val)); +} + +static inline void write_tisr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val)); +} +#endif diff --git a/arch/arm/mach-iop13xx/include/mach/uncompress.h b/arch/arm/mach-iop13xx/include/mach/uncompress.h new file mode 100644 index 00000000000..d3791ece277 --- /dev/null +++ b/arch/arm/mach-iop13xx/include/mach/uncompress.h @@ -0,0 +1,22 @@ +#include <asm/types.h> +#include <linux/serial_reg.h> +#include <mach/hardware.h> + +#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS) +#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) + +static inline void putc(char c) +{ + while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE) + barrier(); + UART_BASE[UART_TX] = c; +} + +static inline void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c index 5b22fdeca52..faaf7d4482c 100644 --- a/arch/arm/mach-iop13xx/io.c +++ b/arch/arm/mach-iop13xx/io.c @@ -18,30 +18,13 @@ */ #include <linux/kernel.h> #include <linux/module.h> -#include <asm/hardware.h> -#include <asm/io.h> +#include <linux/io.h> +#include <mach/hardware.h> -void * __iomem __iop13xx_io(unsigned long io_addr) -{ - void __iomem * io_virt; - - switch (io_addr) { - case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA: - io_virt = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(io_addr); - break; - case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA: - io_virt = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(io_addr); - break; - default: - BUG(); - } - - return io_virt; -} -EXPORT_SYMBOL(__iop13xx_io); +#include "pci.h" -void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size, - unsigned int mtype) +static void __iomem *__iop13xx_ioremap_caller(phys_addr_t cookie, + size_t size, unsigned int mtype, void *caller) { void __iomem * retval; @@ -50,42 +33,34 @@ void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size, if (unlikely(!iop13xx_atux_mem_base)) retval = NULL; else - retval = (void *)(iop13xx_atux_mem_base + + retval = (iop13xx_atux_mem_base + (cookie - IOP13XX_PCIX_LOWER_MEM_RA)); break; case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA: if (unlikely(!iop13xx_atue_mem_base)) retval = NULL; else - retval = (void *)(iop13xx_atue_mem_base + + retval = (iop13xx_atue_mem_base + (cookie - IOP13XX_PCIE_LOWER_MEM_RA)); break; case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA: - retval = __arm_ioremap(IOP13XX_PBI_LOWER_MEM_PA + + retval = __arm_ioremap_caller(IOP13XX_PBI_LOWER_MEM_PA + (cookie - IOP13XX_PBI_LOWER_MEM_RA), - size, mtype); - break; - case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA: - retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie); - break; - case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA: - retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie); + size, mtype, __builtin_return_address(0)); break; case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA: - retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie); + retval = IOP13XX_PMMR_PHYS_TO_VIRT(cookie); break; default: - retval = __arm_ioremap(cookie, size, mtype); + retval = __arm_ioremap_caller(cookie, size, mtype, + caller); } return retval; } -EXPORT_SYMBOL(__iop13xx_ioremap); -void __iop13xx_iounmap(void __iomem *addr) +static void __iop13xx_iounmap(volatile void __iomem *addr) { - extern void __iounmap(volatile void __iomem *addr); - if (iop13xx_atue_mem_base) if (addr >= (void __iomem *) iop13xx_atue_mem_base && addr < (void __iomem *) (iop13xx_atue_mem_base + @@ -99,9 +74,7 @@ void __iop13xx_iounmap(void __iomem *addr) goto skip; switch ((u32) addr) { - case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA: - case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA: - case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA: + case (u32)IOP13XX_PMMR_VIRT_MEM_BASE ... (u32)IOP13XX_PMMR_UPPER_MEM_VA: goto skip; } __iounmap(addr); @@ -109,4 +82,9 @@ void __iop13xx_iounmap(void __iomem *addr) skip: return; } -EXPORT_SYMBOL(__iop13xx_iounmap); + +void __init iop13xx_init_early(void) +{ + arch_ioremap_caller = __iop13xx_ioremap_caller; + arch_iounmap = __iop13xx_iounmap; +} diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c index 77b24cd1d88..9cd07d39609 100644 --- a/arch/arm/mach-iop13xx/iq81340mc.c +++ b/arch/arm/mach-iop13xx/iq81340mc.c @@ -18,19 +18,19 @@ */ #include <linux/pci.h> -#include <asm/hardware.h> +#include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach/pci.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/arch/pci.h> +#include <mach/pci.h> #include <asm/mach/time.h> -#include <asm/arch/time.h> +#include <mach/time.h> extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */ static int __init -iq81340mc_pcix_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) +iq81340mc_pcix_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin) { switch (idsel) { case 1: @@ -54,7 +54,6 @@ iq81340mc_pcix_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) } static struct hw_pci iq81340mc_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 0, .setup = iop13xx_pci_setup, .map_irq = iq81340mc_pcix_map_irq, @@ -85,18 +84,14 @@ static void __init iq81340mc_timer_init(void) iop_init_time(bus_freq); } -static struct sys_timer iq81340mc_timer = { - .init = iq81340mc_timer_init, - .offset = iop_gettimeoffset, -}; - MACHINE_START(IQ81340MC, "Intel IQ81340MC") /* Maintainer: Dan Williams <dan.j.williams@intel.com> */ - .phys_io = IOP13XX_PMMR_PHYS_MEM_BASE, - .io_pg_offst = (IOP13XX_PMMR_VIRT_MEM_BASE >> 18) & 0xfffc, - .boot_params = 0x00000100, + .atag_offset = 0x100, + .init_early = iop13xx_init_early, .map_io = iop13xx_map_io, .init_irq = iop13xx_init_irq, - .timer = &iq81340mc_timer, + .init_time = iq81340mc_timer_init, .init_machine = iq81340mc_init, + .restart = iop13xx_restart, + .nr_irqs = NR_IOP13XX_IRQS, MACHINE_END diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c index e8522b3b816..b3ec11cb707 100644 --- a/arch/arm/mach-iop13xx/iq81340sc.c +++ b/arch/arm/mach-iop13xx/iq81340sc.c @@ -18,19 +18,19 @@ */ #include <linux/pci.h> -#include <asm/hardware.h> +#include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach/pci.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/arch/pci.h> +#include <mach/pci.h> #include <asm/mach/time.h> -#include <asm/arch/time.h> +#include <mach/time.h> extern int init_atu; static int __init -iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) +iq81340sc_atux_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin) { WARN_ON(idsel < 1 || idsel > 2); @@ -56,7 +56,6 @@ iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) } static struct hw_pci iq81340sc_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 0, .setup = iop13xx_pci_setup, .scan = iop13xx_scan_bus, @@ -87,18 +86,14 @@ static void __init iq81340sc_timer_init(void) iop_init_time(bus_freq); } -static struct sys_timer iq81340sc_timer = { - .init = iq81340sc_timer_init, - .offset = iop_gettimeoffset, -}; - MACHINE_START(IQ81340SC, "Intel IQ81340SC") /* Maintainer: Dan Williams <dan.j.williams@intel.com> */ - .phys_io = IOP13XX_PMMR_PHYS_MEM_BASE, - .io_pg_offst = (IOP13XX_PMMR_VIRT_MEM_BASE >> 18) & 0xfffc, - .boot_params = 0x00000100, + .atag_offset = 0x100, + .init_early = iop13xx_init_early, .map_io = iop13xx_map_io, .init_irq = iop13xx_init_irq, - .timer = &iq81340sc_timer, + .init_time = iq81340sc_timer_init, .init_machine = iq81340sc_init, + .restart = iop13xx_restart, + .nr_irqs = NR_IOP13XX_IRQS, MACHINE_END diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c index 69f07b25b3c..bc739701c30 100644 --- a/arch/arm/mach-iop13xx/irq.c +++ b/arch/arm/mach-iop13xx/irq.c @@ -23,10 +23,9 @@ #include <asm/uaccess.h> #include <asm/mach/irq.h> #include <asm/irq.h> -#include <asm/hardware.h> -#include <asm/mach-types.h> -#include <asm/arch/irqs.h> -#include <asm/arch/msi.h> +#include <mach/hardware.h> +#include <mach/irqs.h> +#include <mach/msi.h> /* INTCTL0 CP6 R0 Page 4 */ @@ -124,79 +123,79 @@ static void write_intsize(u32 val) /* 0 = Interrupt Masked and 1 = Interrupt not masked */ static void -iop13xx_irq_mask0 (unsigned int irq) +iop13xx_irq_mask0 (struct irq_data *d) { - write_intctl_0(read_intctl_0() & ~(1 << (irq - 0))); + write_intctl_0(read_intctl_0() & ~(1 << (d->irq - 0))); } static void -iop13xx_irq_mask1 (unsigned int irq) +iop13xx_irq_mask1 (struct irq_data *d) { - write_intctl_1(read_intctl_1() & ~(1 << (irq - 32))); + write_intctl_1(read_intctl_1() & ~(1 << (d->irq - 32))); } static void -iop13xx_irq_mask2 (unsigned int irq) +iop13xx_irq_mask2 (struct irq_data *d) { - write_intctl_2(read_intctl_2() & ~(1 << (irq - 64))); + write_intctl_2(read_intctl_2() & ~(1 << (d->irq - 64))); } static void -iop13xx_irq_mask3 (unsigned int irq) +iop13xx_irq_mask3 (struct irq_data *d) { - write_intctl_3(read_intctl_3() & ~(1 << (irq - 96))); + write_intctl_3(read_intctl_3() & ~(1 << (d->irq - 96))); } static void -iop13xx_irq_unmask0(unsigned int irq) +iop13xx_irq_unmask0(struct irq_data *d) { - write_intctl_0(read_intctl_0() | (1 << (irq - 0))); + write_intctl_0(read_intctl_0() | (1 << (d->irq - 0))); } static void -iop13xx_irq_unmask1(unsigned int irq) +iop13xx_irq_unmask1(struct irq_data *d) { - write_intctl_1(read_intctl_1() | (1 << (irq - 32))); + write_intctl_1(read_intctl_1() | (1 << (d->irq - 32))); } static void -iop13xx_irq_unmask2(unsigned int irq) +iop13xx_irq_unmask2(struct irq_data *d) { - write_intctl_2(read_intctl_2() | (1 << (irq - 64))); + write_intctl_2(read_intctl_2() | (1 << (d->irq - 64))); } static void -iop13xx_irq_unmask3(unsigned int irq) +iop13xx_irq_unmask3(struct irq_data *d) { - write_intctl_3(read_intctl_3() | (1 << (irq - 96))); + write_intctl_3(read_intctl_3() | (1 << (d->irq - 96))); } static struct irq_chip iop13xx_irqchip1 = { - .name = "IOP13xx-1", - .ack = iop13xx_irq_mask0, - .mask = iop13xx_irq_mask0, - .unmask = iop13xx_irq_unmask0, + .name = "IOP13xx-1", + .irq_ack = iop13xx_irq_mask0, + .irq_mask = iop13xx_irq_mask0, + .irq_unmask = iop13xx_irq_unmask0, }; static struct irq_chip iop13xx_irqchip2 = { - .name = "IOP13xx-2", - .ack = iop13xx_irq_mask1, - .mask = iop13xx_irq_mask1, - .unmask = iop13xx_irq_unmask1, + .name = "IOP13xx-2", + .irq_ack = iop13xx_irq_mask1, + .irq_mask = iop13xx_irq_mask1, + .irq_unmask = iop13xx_irq_unmask1, }; static struct irq_chip iop13xx_irqchip3 = { - .name = "IOP13xx-3", - .ack = iop13xx_irq_mask2, - .mask = iop13xx_irq_mask2, - .unmask = iop13xx_irq_unmask2, + .name = "IOP13xx-3", + .irq_ack = iop13xx_irq_mask2, + .irq_mask = iop13xx_irq_mask2, + .irq_unmask = iop13xx_irq_unmask2, }; static struct irq_chip iop13xx_irqchip4 = { - .name = "IOP13xx-4", - .ack = iop13xx_irq_mask3, - .mask = iop13xx_irq_mask3, - .unmask = iop13xx_irq_unmask3, + .name = "IOP13xx-4", + .irq_ack = iop13xx_irq_mask3, + .irq_mask = iop13xx_irq_mask3, + .irq_unmask = iop13xx_irq_unmask3, }; extern void iop_init_cp6_handler(void); @@ -225,15 +224,15 @@ void __init iop13xx_init_irq(void) for(i = 0; i <= IRQ_IOP13XX_HPI; i++) { if (i < 32) - set_irq_chip(i, &iop13xx_irqchip1); + irq_set_chip(i, &iop13xx_irqchip1); else if (i < 64) - set_irq_chip(i, &iop13xx_irqchip2); + irq_set_chip(i, &iop13xx_irqchip2); else if (i < 96) - set_irq_chip(i, &iop13xx_irqchip3); + irq_set_chip(i, &iop13xx_irqchip3); else - set_irq_chip(i, &iop13xx_irqchip4); + irq_set_chip(i, &iop13xx_irqchip4); - set_irq_handler(i, handle_level_irq); + irq_set_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c index 63ef1124ca5..e7730cf9c15 100644 --- a/arch/arm/mach-iop13xx/msi.c +++ b/arch/arm/mach-iop13xx/msi.c @@ -23,10 +23,7 @@ #include <linux/msi.h> #include <asm/mach/irq.h> #include <asm/irq.h> - - -#define IOP13XX_NUM_MSI_IRQS 128 -static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS); +#include <mach/irqs.h> /* IMIPR0 CP6 R8 Page 1 */ @@ -110,8 +107,7 @@ static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc) do { j = find_first_bit(&status, 32); (write_imipr[i])(1 << j); /* write back to clear bit */ - desc = irq_desc + IRQ_IOP13XX_MSI_0 + j + (32*i); - desc_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i), desc); + generic_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i)); status = (read_imipr[i])(); } while (status); } @@ -119,67 +115,37 @@ static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc) void __init iop13xx_msi_init(void) { - set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); -} - -/* - * Dynamic irq allocate and deallocation - */ -int create_irq(void) -{ - int irq, pos; - -again: - pos = find_first_zero_bit(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS); - irq = IRQ_IOP13XX_MSI_0 + pos; - if (irq > NR_IRQS) - return -ENOSPC; - /* test_and_set_bit operates on 32-bits at a time */ - if (test_and_set_bit(pos, msi_irq_in_use)) - goto again; - - dynamic_irq_init(irq); - - return irq; + irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); } -void destroy_irq(unsigned int irq) -{ - int pos = irq - IRQ_IOP13XX_MSI_0; - - dynamic_irq_cleanup(irq); - - clear_bit(pos, msi_irq_in_use); -} - -void arch_teardown_msi_irq(unsigned int irq) -{ - destroy_irq(irq); -} - -static void iop13xx_msi_nop(unsigned int irq) +static void iop13xx_msi_nop(struct irq_data *d) { return; } static struct irq_chip iop13xx_msi_chip = { .name = "PCI-MSI", - .ack = iop13xx_msi_nop, - .enable = unmask_msi_irq, - .disable = mask_msi_irq, - .mask = mask_msi_irq, - .unmask = unmask_msi_irq, + .irq_ack = iop13xx_msi_nop, + .irq_enable = unmask_msi_irq, + .irq_disable = mask_msi_irq, + .irq_mask = mask_msi_irq, + .irq_unmask = unmask_msi_irq, }; int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) { - int id, irq = create_irq(); + int id, irq = irq_alloc_desc_from(IRQ_IOP13XX_MSI_0, -1); struct msi_msg msg; if (irq < 0) return irq; - set_irq_msi(irq, desc); + if (irq >= NR_IOP13XX_IRQS) { + irq_free_desc(irq); + return -ENOSPC; + } + + irq_set_msi_desc(irq, desc); msg.address_hi = 0x0; msg.address_lo = IOP13XX_MU_MIMR_PCI; @@ -188,7 +154,12 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); write_msi_msg(irq, &msg); - set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); + irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); return 0; } + +void arch_teardown_msi_irq(unsigned int irq) +{ + irq_free_desc(irq); +} diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 7825c1aaa27..9082b84aeeb 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -18,14 +18,16 @@ */ #include <linux/pci.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/jiffies.h> +#include <linux/export.h> #include <asm/irq.h> -#include <asm/hardware.h> +#include <mach/hardware.h> #include <asm/sizes.h> #include <asm/signal.h> #include <asm/mach/pci.h> -#include <asm/arch/pci.h> +#include <mach/pci.h> #define IOP13XX_PCI_DEBUG 0 #define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x))) @@ -34,12 +36,10 @@ u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */ u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */ static struct pci_bus *pci_bus_atux = 0; static struct pci_bus *pci_bus_atue = 0; -u32 iop13xx_atue_mem_base; -u32 iop13xx_atux_mem_base; +void __iomem *iop13xx_atue_mem_base; +void __iomem *iop13xx_atux_mem_base; size_t iop13xx_atue_mem_size; size_t iop13xx_atux_mem_size; -unsigned long iop13xx_pcibios_min_io = 0; -unsigned long iop13xx_pcibios_min_mem = 0; EXPORT_SYMBOL(iop13xx_atue_mem_base); EXPORT_SYMBOL(iop13xx_atux_mem_base); @@ -88,8 +88,7 @@ void iop13xx_map_pci_memory(void) } if (end) { - iop13xx_atux_mem_base = - (u32) __arm_ioremap_pfn( + iop13xx_atux_mem_base = __arm_ioremap_pfn( __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA) , 0, iop13xx_atux_mem_size, MT_DEVICE); if (!iop13xx_atux_mem_base) { @@ -99,7 +98,7 @@ void iop13xx_map_pci_memory(void) } } else iop13xx_atux_mem_size = 0; - PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", + PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n", __func__, atu, iop13xx_atux_mem_size, iop13xx_atux_mem_base); break; @@ -114,8 +113,7 @@ void iop13xx_map_pci_memory(void) } if (end) { - iop13xx_atue_mem_base = - (u32) __arm_ioremap_pfn( + iop13xx_atue_mem_base = __arm_ioremap_pfn( __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA) , 0, iop13xx_atue_mem_size, MT_DEVICE); if (!iop13xx_atue_mem_base) { @@ -125,13 +123,13 @@ void iop13xx_map_pci_memory(void) } } else iop13xx_atue_mem_size = 0; - PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", + PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n", __func__, atu, iop13xx_atue_mem_size, iop13xx_atue_mem_base); break; } - printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n", + printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n", atu ? "ATUE" : "ATUX", (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) / SZ_1M, @@ -224,7 +222,7 @@ static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where) /* This routine checks the status of the last configuration cycle. If an error * was detected it returns >0, else it returns a 0. The errors being checked * are parity, master abort, target abort (master and target). These types of - * errors occure during a config cycle where there is no device, like during + * errors occur during a config cycle where there is no device, like during * the discovery stage. */ static int iop13xx_atux_pci_status(int clear) @@ -331,7 +329,7 @@ static struct pci_ops iop13xx_atux_ops = { /* This routine checks the status of the last configuration cycle. If an error * was detected it returns >0, else it returns a 0. The errors being checked * are parity, master abort, target abort (master and target). These types of - * errors occure during a config cycle where there is no device, like during + * errors occur during a config cycle where there is no device, like during * the discovery stage. */ static int iop13xx_atue_pci_status(int clear) @@ -389,7 +387,7 @@ static int iop13xx_atue_pci_status(int clear) } static int -iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) +iop13xx_pcie_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin) { WARN_ON(idsel != 0); @@ -537,14 +535,14 @@ struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys) while(time_before(jiffies, atux_trhfa_timeout)) udelay(100); - bus = pci_bus_atux = pci_scan_bus(sys->busnr, - &iop13xx_atux_ops, - sys); + bus = pci_bus_atux = pci_scan_root_bus(NULL, sys->busnr, + &iop13xx_atux_ops, + sys, &sys->resources); break; case IOP13XX_INIT_ATU_ATUE: - bus = pci_bus_atue = pci_scan_bus(sys->busnr, - &iop13xx_atue_ops, - sys); + bus = pci_bus_atue = pci_scan_root_bus(NULL, sys->busnr, + &iop13xx_atue_ops, + sys, &sys->resources); break; } @@ -970,7 +968,7 @@ void __init iop13xx_pci_init(void) __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR); /* Setup the Min Address for PCI memory... */ - iop13xx_pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA; + pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA; /* if Linux is given control of an ATU * clear out its prior configuration, @@ -986,7 +984,7 @@ void __init iop13xx_pci_init(void) iop13xx_atux_setup(); } - hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, + hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 0, "imprecise external abort"); } @@ -1002,7 +1000,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) if (nr > 1) return 0; - res = kcalloc(2, sizeof(struct resource), GFP_KERNEL); + res = kzalloc(sizeof(struct resource), GFP_KERNEL); if (!res) panic("PCI: unable to alloc resources"); @@ -1026,8 +1024,10 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) which_atu = 0; } - if (!which_atu) + if (!which_atu) { + kfree(res); return 0; + } switch(which_atu) { case IOP13XX_INIT_ATU_ATUX: @@ -1039,17 +1039,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) << IOP13XX_ATUX_PCIXSR_FUNC_NUM; __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); - res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET; - res[0].end = IOP13XX_PCIX_UPPER_IO_PA; - res[0].name = "IQ81340 ATUX PCI I/O Space"; - res[0].flags = IORESOURCE_IO; + pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA); - res[1].start = IOP13XX_PCIX_LOWER_MEM_RA; - res[1].end = IOP13XX_PCIX_UPPER_MEM_RA; - res[1].name = "IQ81340 ATUX PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; + res->start = IOP13XX_PCIX_LOWER_MEM_RA; + res->end = IOP13XX_PCIX_UPPER_MEM_RA; + res->name = "IQ81340 ATUX PCI Memory Space"; + res->flags = IORESOURCE_MEM; sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET; - sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA; break; case IOP13XX_INIT_ATU_ATUE: /* Note: the function number field in the PCSR is ro */ @@ -1060,29 +1056,23 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) __raw_writel(pcsr, IOP13XX_ATUE_PCSR); - res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET; - res[0].end = IOP13XX_PCIE_UPPER_IO_PA; - res[0].name = "IQ81340 ATUE PCI I/O Space"; - res[0].flags = IORESOURCE_IO; + pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA); - res[1].start = IOP13XX_PCIE_LOWER_MEM_RA; - res[1].end = IOP13XX_PCIE_UPPER_MEM_RA; - res[1].name = "IQ81340 ATUE PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; + res->start = IOP13XX_PCIE_LOWER_MEM_RA; + res->end = IOP13XX_PCIE_UPPER_MEM_RA; + res->name = "IQ81340 ATUE PCI Memory Space"; + res->flags = IORESOURCE_MEM; sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET; - sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA; sys->map_irq = iop13xx_pcie_map_irq; break; default: + kfree(res); return 0; } - request_resource(&ioport_resource, &res[0]); - request_resource(&iomem_resource, &res[1]); + request_resource(&iomem_resource, res); - sys->resource[0] = &res[0]; - sys->resource[1] = &res[1]; - sys->resource[2] = NULL; + pci_add_resource_offset(&sys->resources, res, sys->mem_offset); return 1; } diff --git a/arch/arm/mach-iop13xx/pci.h b/arch/arm/mach-iop13xx/pci.h new file mode 100644 index 00000000000..d45a80b3080 --- /dev/null +++ b/arch/arm/mach-iop13xx/pci.h @@ -0,0 +1,6 @@ +#include <linux/types.h> + +extern void __iomem *iop13xx_atue_mem_base; +extern void __iomem *iop13xx_atux_mem_base; +extern size_t iop13xx_atue_mem_size; +extern size_t iop13xx_atux_mem_size; diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c index 246f6d47872..bca96f43349 100644 --- a/arch/arm/mach-iop13xx/setup.c +++ b/arch/arm/mach-iop13xx/setup.c @@ -17,15 +17,17 @@ * */ +#include <linux/dma-mapping.h> #include <linux/serial_8250.h> +#include <linux/io.h> #ifdef CONFIG_MTD_PHYSMAP #include <linux/mtd/physmap.h> #endif #include <asm/mach/map.h> -#include <asm/hardware.h> +#include <mach/hardware.h> #include <asm/irq.h> -#include <asm/io.h> #include <asm/hardware/iop_adma.h> +#include <mach/irqs.h> #define IOP13XX_UART_XTAL 33334000 #define IOP13XX_SETUP_DEBUG 0 @@ -35,20 +37,10 @@ */ static struct map_desc iop13xx_std_desc[] __initdata = { { /* mem mapped registers */ - .virtual = IOP13XX_PMMR_VIRT_MEM_BASE, + .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE, .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE), .length = IOP13XX_PMMR_SIZE, .type = MT_DEVICE, - }, { /* PCIE IO space */ - .virtual = IOP13XX_PCIE_LOWER_IO_VA, - .pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA), - .length = IOP13XX_PCIX_IO_WINDOW_SIZE, - .type = MT_DEVICE, - }, { /* PCIX IO space */ - .virtual = IOP13XX_PCIX_LOWER_IO_VA, - .pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA), - .length = IOP13XX_PCIX_IO_WINDOW_SIZE, - .type = MT_DEVICE, }, }; @@ -80,8 +72,8 @@ static struct resource iop13xx_uart1_resources[] = { static struct plat_serial8250_port iop13xx_uart0_data[] = { { - .membase = (char*)(IOP13XX_UART0_VIRT), - .mapbase = (IOP13XX_UART0_PHYS), + .membase = IOP13XX_UART0_VIRT, + .mapbase = IOP13XX_UART0_PHYS, .irq = IRQ_IOP13XX_UART0, .uartclk = IOP13XX_UART_XTAL, .regshift = 2, @@ -93,8 +85,8 @@ static struct plat_serial8250_port iop13xx_uart0_data[] = { static struct plat_serial8250_port iop13xx_uart1_data[] = { { - .membase = (char*)(IOP13XX_UART1_VIRT), - .mapbase = (IOP13XX_UART1_PHYS), + .membase = IOP13XX_UART1_VIRT, + .mapbase = IOP13XX_UART1_PHYS, .irq = IRQ_IOP13XX_UART1, .uartclk = IOP13XX_UART_XTAL, .regshift = 2, @@ -307,7 +299,7 @@ static struct resource iop13xx_adma_2_resources[] = { } }; -static u64 iop13xx_adma_dmamask = DMA_64BIT_MASK; +static u64 iop13xx_adma_dmamask = DMA_BIT_MASK(64); static struct iop_adma_platform_data iop13xx_adma_0_data = { .hw_id = 0, .pool_size = PAGE_SIZE, @@ -331,7 +323,7 @@ static struct platform_device iop13xx_adma_0_channel = { .resource = iop13xx_adma_0_resources, .dev = { .dma_mask = &iop13xx_adma_dmamask, - .coherent_dma_mask = DMA_64BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(64), .platform_data = (void *) &iop13xx_adma_0_data, }, }; @@ -343,7 +335,7 @@ static struct platform_device iop13xx_adma_1_channel = { .resource = iop13xx_adma_1_resources, .dev = { .dma_mask = &iop13xx_adma_dmamask, - .coherent_dma_mask = DMA_64BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(64), .platform_data = (void *) &iop13xx_adma_1_data, }, }; @@ -355,7 +347,7 @@ static struct platform_device iop13xx_adma_2_channel = { .resource = iop13xx_adma_2_resources, .dev = { .dma_mask = &iop13xx_adma_dmamask, - .coherent_dma_mask = DMA_64BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(64), .platform_data = (void *) &iop13xx_adma_2_data, }, }; @@ -477,10 +469,7 @@ void __init iop13xx_platform_init(void) plat_data = &iop13xx_adma_0_data; dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); dma_cap_set(DMA_XOR, plat_data->cap_mask); - dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); - dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask); - dma_cap_set(DMA_MEMSET, plat_data->cap_mask); - dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); + dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); break; case IOP13XX_INIT_ADMA_1: @@ -489,10 +478,7 @@ void __init iop13xx_platform_init(void) plat_data = &iop13xx_adma_1_data; dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); dma_cap_set(DMA_XOR, plat_data->cap_mask); - dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); - dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask); - dma_cap_set(DMA_MEMSET, plat_data->cap_mask); - dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); + dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); break; case IOP13XX_INIT_ADMA_2: @@ -501,14 +487,10 @@ void __init iop13xx_platform_init(void) plat_data = &iop13xx_adma_2_data; dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); dma_cap_set(DMA_XOR, plat_data->cap_mask); - dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); - dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask); - dma_cap_set(DMA_MEMSET, plat_data->cap_mask); - dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); + dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); - dma_cap_set(DMA_PQ_XOR, plat_data->cap_mask); - dma_cap_set(DMA_PQ_UPDATE, plat_data->cap_mask); - dma_cap_set(DMA_PQ_ZERO_SUM, plat_data->cap_mask); + dma_cap_set(DMA_PQ, plat_data->cap_mask); + dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask); break; } } @@ -612,3 +594,14 @@ static int __init iop13xx_init_adma_setup(char *str) __setup("iop13xx_init_adma", iop13xx_init_adma_setup); __setup("iop13xx_init_uart", iop13xx_init_uart_setup); __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup); + +void iop13xx_restart(enum reboot_mode mode, const char *cmd) +{ + /* + * Reset the internal bus (warning both cores are reset) + */ + write_wdtcr(IOP_WDTCR_EN_ARM); + write_wdtcr(IOP_WDTCR_EN); + write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); + write_wdtcr(0x1000); +} diff --git a/arch/arm/mach-iop13xx/tpmi.c b/arch/arm/mach-iop13xx/tpmi.c index 2476347ea62..db511ec2b1d 100644 --- a/arch/arm/mach-iop13xx/tpmi.c +++ b/arch/arm/mach-iop13xx/tpmi.c @@ -21,9 +21,10 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/dma-mapping.h> -#include <asm/io.h> +#include <linux/io.h> #include <asm/irq.h> #include <asm/sizes.h> +#include <mach/irqs.h> /* assumes CONTROLLER_ONLY# is never asserted in the ESSR register */ #define IOP13XX_TPMI_MMR(dev) IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12)) @@ -151,7 +152,7 @@ static struct resource iop13xx_tpmi_3_resources[] = { } }; -u64 iop13xx_tpmi_mask = DMA_64BIT_MASK; +u64 iop13xx_tpmi_mask = DMA_BIT_MASK(64); static struct platform_device iop13xx_tpmi_0_device = { .name = "iop-tpmi", .id = 0, @@ -159,7 +160,7 @@ static struct platform_device iop13xx_tpmi_0_device = { .resource = iop13xx_tpmi_0_resources, .dev = { .dma_mask = &iop13xx_tpmi_mask, - .coherent_dma_mask = DMA_64BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(64), }, }; @@ -170,7 +171,7 @@ static struct platform_device iop13xx_tpmi_1_device = { .resource = iop13xx_tpmi_1_resources, .dev = { .dma_mask = &iop13xx_tpmi_mask, - .coherent_dma_mask = DMA_64BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(64), }, }; @@ -181,7 +182,7 @@ static struct platform_device iop13xx_tpmi_2_device = { .resource = iop13xx_tpmi_2_resources, .dev = { .dma_mask = &iop13xx_tpmi_mask, - .coherent_dma_mask = DMA_64BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(64), }, }; @@ -192,7 +193,7 @@ static struct platform_device iop13xx_tpmi_3_device = { .resource = iop13xx_tpmi_3_resources, .dev = { .dma_mask = &iop13xx_tpmi_mask, - .coherent_dma_mask = DMA_64BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(64), }, }; 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