diff options
Diffstat (limited to 'arch/arm/mach-integrator/integrator_ap.c')
| -rw-r--r-- | arch/arm/mach-integrator/integrator_ap.c | 566 |
1 files changed, 388 insertions, 178 deletions
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index df37e93c6fc..660ca6feff4 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -24,49 +24,61 @@ #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/string.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/amba/bus.h> #include <linux/amba/kmi.h> - -#include <asm/hardware.h> -#include <asm/io.h> -#include <asm/irq.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/irqchip/versatile-fpga.h> +#include <linux/mtd/physmap.h> +#include <linux/clk.h> +#include <linux/platform_data/clk-integrator.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/stat.h> +#include <linux/sys_soc.h> +#include <linux/termios.h> +#include <linux/sched_clock.h> +#include <linux/clk-provider.h> + +#include <asm/hardware/arm_timer.h> #include <asm/setup.h> #include <asm/param.h> /* HZ */ #include <asm/mach-types.h> -#include <asm/arch/lm.h> - #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> #include <asm/mach/time.h> +#include "hardware.h" +#include "cm.h" #include "common.h" +#include "pci_v3.h" +#include "lm.h" + +/* Base address to the AP system controller */ +void __iomem *ap_syscon_base; +/* Base address to the external bus interface */ +static void __iomem *ebi_base; + -/* +/* * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx * is the (PA >> 12). * * Setup a VA for the Integrator interrupt controller (for header #0, * just for now). */ -#define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE) -#define VA_SC_BASE IO_ADDRESS(INTEGRATOR_SC_BASE) -#define VA_EBI_BASE IO_ADDRESS(INTEGRATOR_EBI_BASE) -#define VA_CMIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_IC_OFFSET +#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE) /* * Logical Physical - * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) - * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) - * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k) - * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) * ef000000 Cache flush - * f1000000 10000000 Core module registers * f1100000 11000000 System controller registers - * f1200000 12000000 EBI registers * f1300000 13000000 Counter/Timer * f1400000 14000000 Interrupt controller * f1600000 16000000 UART 0 @@ -75,23 +87,8 @@ * f1b00000 1b000000 GPIO */ -static struct map_desc ap_io_desc[] __initdata = { +static struct map_desc ap_io_desc[] __initdata __maybe_unused = { { - .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { - .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { - .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), .length = SZ_4K, @@ -107,213 +104,430 @@ static struct map_desc ap_io_desc[] __initdata = { .length = SZ_4K, .type = MT_DEVICE }, { - .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE), .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE), .length = SZ_4K, .type = MT_DEVICE }, { - .virtual = IO_ADDRESS(INTEGRATOR_GPIO_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_GPIO_BASE), + .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE), + .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE), .length = SZ_4K, .type = MT_DEVICE - }, { - .virtual = PCI_MEMORY_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, { - .virtual = PCI_CONFIG_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, { - .virtual = PCI_V3_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE), - .length = SZ_64K, - .type = MT_DEVICE - }, { - .virtual = PCI_IO_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_IO_BASE), - .length = SZ_64K, - .type = MT_DEVICE } }; static void __init ap_map_io(void) { iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); -} - -#define INTEGRATOR_SC_VALID_INT 0x003fffff - -static void sc_mask_irq(unsigned int irq) -{ - writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_CLEAR); -} - -static void sc_unmask_irq(unsigned int irq) -{ - writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_SET); -} - -static struct irq_chip sc_chip = { - .name = "SC", - .ack = sc_mask_irq, - .mask = sc_mask_irq, - .unmask = sc_unmask_irq, -}; - -static void __init ap_init_irq(void) -{ - unsigned int i; - - /* Disable all interrupts initially. */ - /* Do the core module ones */ - writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); - - /* do the header card stuff next */ - writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); - writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); - - for (i = 0; i < NR_IRQS; i++) { - if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) { - set_irq_chip(i, &sc_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } - } + pci_v3_early_init(); } #ifdef CONFIG_PM static unsigned long ic_irq_enable; -static int irq_suspend(struct sys_device *dev, pm_message_t state) +static int irq_suspend(void) { ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE); return 0; } -static int irq_resume(struct sys_device *dev) +static void irq_resume(void) { /* disable all irq sources */ - writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); + cm_clear_irqs(); writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET); - return 0; } #else #define irq_suspend NULL #define irq_resume NULL #endif -static struct sysdev_class irq_class = { - .name = "irq", +static struct syscore_ops irq_syscore_ops = { .suspend = irq_suspend, .resume = irq_resume, }; -static struct sys_device irq_device = { - .id = 0, - .cls = &irq_class, -}; - -static int __init irq_init_sysfs(void) +static int __init irq_syscore_init(void) { - int ret = sysdev_class_register(&irq_class); - if (ret == 0) - ret = sysdev_register(&irq_device); - return ret; + register_syscore_ops(&irq_syscore_ops); + + return 0; } -device_initcall(irq_init_sysfs); +device_initcall(irq_syscore_init); /* * Flash handling. */ -#define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET) -#define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET) -#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) -#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) - -static int ap_flash_init(void) +static int ap_flash_init(struct platform_device *dev) { u32 tmp; - writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC); + writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, + ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); - tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE; - writel(tmp, EBI_CSR1); + tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) | + INTEGRATOR_EBI_WRITE_ENABLE; + writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); - if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) { - writel(0xa05f, EBI_LOCK); - writel(tmp, EBI_CSR1); - writel(0, EBI_LOCK); + if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) + & INTEGRATOR_EBI_WRITE_ENABLE)) { + writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); + writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); + writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); } return 0; } -static void ap_flash_exit(void) +static void ap_flash_exit(struct platform_device *dev) { u32 tmp; - writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC); + writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, + ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); - tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE; - writel(tmp, EBI_CSR1); + tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) & + ~INTEGRATOR_EBI_WRITE_ENABLE; + writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); - if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) { - writel(0xa05f, EBI_LOCK); - writel(tmp, EBI_CSR1); - writel(0, EBI_LOCK); + if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) & + INTEGRATOR_EBI_WRITE_ENABLE) { + writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); + writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); + writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); } } -static void ap_flash_set_vpp(int on) +static void ap_flash_set_vpp(struct platform_device *pdev, int on) { - unsigned long reg = on ? SC_CTRLS : SC_CTRLC; - - writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg); + if (on) + writel(INTEGRATOR_SC_CTRL_nFLVPPEN, + ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET); + else + writel(INTEGRATOR_SC_CTRL_nFLVPPEN, + ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); } -static struct flash_platform_data ap_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data ap_flash_data = { .width = 4, .init = ap_flash_init, .exit = ap_flash_exit, .set_vpp = ap_flash_set_vpp, }; -static struct resource cfi_flash_resource = { - .start = INTEGRATOR_FLASH_BASE, - .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1, - .flags = IORESOURCE_MEM, +/* + * For the PL010 found in the Integrator/AP some of the UART control is + * implemented in the system controller and accessed using a callback + * from the driver. + */ +static void integrator_uart_set_mctrl(struct amba_device *dev, + void __iomem *base, unsigned int mctrl) +{ + unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask; + u32 phybase = dev->res.start; + + if (phybase == INTEGRATOR_UART0_BASE) { + /* UART0 */ + rts_mask = 1 << 4; + dtr_mask = 1 << 5; + } else { + /* UART1 */ + rts_mask = 1 << 6; + dtr_mask = 1 << 7; + } + + if (mctrl & TIOCM_RTS) + ctrlc |= rts_mask; + else + ctrls |= rts_mask; + + if (mctrl & TIOCM_DTR) + ctrlc |= dtr_mask; + else + ctrls |= dtr_mask; + + __raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET); + __raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); +} + +struct amba_pl010_data ap_uart_data = { + .set_mctrl = integrator_uart_set_mctrl, }; -static struct platform_device cfi_flash_device = { - .name = "armflash", - .id = 0, - .dev = { - .platform_data = &ap_flash_data, - }, - .num_resources = 1, - .resource = &cfi_flash_resource, +/* + * Where is the timer (VA)? + */ +#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE) +#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE) +#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE) + +static unsigned long timer_reload; + +static u64 notrace integrator_read_sched_clock(void) +{ + return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE); +} + +static void integrator_clocksource_init(unsigned long inrate, + void __iomem *base) +{ + u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC; + unsigned long rate = inrate; + + if (rate >= 1500000) { + rate /= 16; + ctrl |= TIMER_CTRL_DIV16; + } + + writel(0xffff, base + TIMER_LOAD); + writel(ctrl, base + TIMER_CTRL); + + clocksource_mmio_init(base + TIMER_VALUE, "timer2", + rate, 200, 16, clocksource_mmio_readl_down); + sched_clock_register(integrator_read_sched_clock, 16, rate); +} + +static void __iomem * clkevt_base; + +/* + * IRQ handler for the timer + */ +static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + + /* clear the interrupt */ + writel(1, clkevt_base + TIMER_INTCLR); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) +{ + u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE; + + /* Disable timer */ + writel(ctrl, clkevt_base + TIMER_CTRL); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + /* Enable the timer and start the periodic tick */ + writel(timer_reload, clkevt_base + TIMER_LOAD); + ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; + writel(ctrl, clkevt_base + TIMER_CTRL); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* Leave the timer disabled, .set_next_event will enable it */ + ctrl &= ~TIMER_CTRL_PERIODIC; + writel(ctrl, clkevt_base + TIMER_CTRL); + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_RESUME: + default: + /* Just leave in disabled state */ + break; + } + +} + +static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt) +{ + unsigned long ctrl = readl(clkevt_base + TIMER_CTRL); + + writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); + writel(next, clkevt_base + TIMER_LOAD); + writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); + + return 0; +} + +static struct clock_event_device integrator_clockevent = { + .name = "timer1", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = clkevt_set_mode, + .set_next_event = clkevt_set_next_event, + .rating = 300, +}; + +static struct irqaction integrator_timer_irq = { + .name = "timer", + .flags = IRQF_TIMER | IRQF_IRQPOLL, + .handler = integrator_timer_interrupt, + .dev_id = &integrator_clockevent, +}; + +static void integrator_clockevent_init(unsigned long inrate, + void __iomem *base, int irq) +{ + unsigned long rate = inrate; + unsigned int ctrl = 0; + + clkevt_base = base; + /* Calculate and program a divisor */ + if (rate > 0x100000 * HZ) { + rate /= 256; + ctrl |= TIMER_CTRL_DIV256; + } else if (rate > 0x10000 * HZ) { + rate /= 16; + ctrl |= TIMER_CTRL_DIV16; + } + timer_reload = rate / HZ; + writel(ctrl, clkevt_base + TIMER_CTRL); + + setup_irq(irq, &integrator_timer_irq); + clockevents_config_and_register(&integrator_clockevent, + rate, + 1, + 0xffffU); +} + +void __init ap_init_early(void) +{ +} + +static void __init ap_of_timer_init(void) +{ + struct device_node *node; + const char *path; + void __iomem *base; + int err; + int irq; + struct clk *clk; + unsigned long rate; + + of_clk_init(NULL); + + err = of_property_read_string(of_aliases, + "arm,timer-primary", &path); + if (WARN_ON(err)) + return; + node = of_find_node_by_path(path); + base = of_iomap(node, 0); + if (WARN_ON(!base)) + return; + + clk = of_clk_get(node, 0); + BUG_ON(IS_ERR(clk)); + clk_prepare_enable(clk); + rate = clk_get_rate(clk); + + writel(0, base + TIMER_CTRL); + integrator_clocksource_init(rate, base); + + err = of_property_read_string(of_aliases, + "arm,timer-secondary", &path); + if (WARN_ON(err)) + return; + node = of_find_node_by_path(path); + base = of_iomap(node, 0); + if (WARN_ON(!base)) + return; + irq = irq_of_parse_and_map(node, 0); + + clk = of_clk_get(node, 0); + BUG_ON(IS_ERR(clk)); + clk_prepare_enable(clk); + rate = clk_get_rate(clk); + + writel(0, base + TIMER_CTRL); + integrator_clockevent_init(rate, base, irq); +} + +static const struct of_device_id fpga_irq_of_match[] __initconst = { + { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, }, + { /* Sentinel */ } }; -static void __init ap_init(void) +static void __init ap_init_irq_of(void) +{ + cm_init(); + of_irq_init(fpga_irq_of_match); +} + +/* For the Device Tree, add in the UART callbacks as AUXDATA */ +static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE, + "rtc", NULL), + OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE, + "uart0", &ap_uart_data), + OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE, + "uart1", &ap_uart_data), + OF_DEV_AUXDATA("arm,primecell", KMI0_BASE, + "kmi0", NULL), + OF_DEV_AUXDATA("arm,primecell", KMI1_BASE, + "kmi1", NULL), + OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE, + "physmap-flash", &ap_flash_data), + { /* sentinel */ }, +}; + +static const struct of_device_id ap_syscon_match[] = { + { .compatible = "arm,integrator-ap-syscon"}, + { }, +}; + +static const struct of_device_id ebi_match[] = { + { .compatible = "arm,external-bus-interface"}, + { }, +}; + +static void __init ap_init_of(void) { unsigned long sc_dec; + struct device_node *syscon; + struct device_node *ebi; + struct device *parent; + struct soc_device *soc_dev; + struct soc_device_attribute *soc_dev_attr; + u32 ap_sc_id; int i; - platform_device_register(&cfi_flash_device); + syscon = of_find_matching_node(NULL, ap_syscon_match); + if (!syscon) + return; + ebi = of_find_matching_node(NULL, ebi_match); + if (!ebi) + return; + + ap_syscon_base = of_iomap(syscon, 0); + if (!ap_syscon_base) + return; + ebi_base = of_iomap(ebi, 0); + if (!ebi_base) + return; + + of_platform_populate(NULL, of_default_bus_match_table, + ap_auxdata_lookup, NULL); + + ap_sc_id = readl(ap_syscon_base); + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return; + + soc_dev_attr->soc_id = "XVC"; + soc_dev_attr->machine = "Integrator/AP"; + soc_dev_attr->family = "Integrator"; + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c", + 'A' + (ap_sc_id & 0x0f)); + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr->revision); + kfree(soc_dev_attr); + return; + } + + parent = soc_device_to_device(soc_dev); + integrator_init_sysfs(parent, ap_sc_id); - sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET); + sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET); for (i = 0; i < 4; i++) { struct lm_device *lmdev; @@ -327,30 +541,26 @@ static void __init ap_init(void) lmdev->resource.start = 0xc0000000 + 0x10000000 * i; lmdev->resource.end = lmdev->resource.start + 0x0fffffff; lmdev->resource.flags = IORESOURCE_MEM; - lmdev->irq = IRQ_AP_EXPINT0 + i; + lmdev->irq = irq_of_parse_and_map(syscon, i); lmdev->id = i; lm_device_register(lmdev); } } -static void __init ap_init_timer(void) -{ - integrator_time_init(1000000 * TICKS_PER_uSEC / HZ, 0); -} - -static struct sys_timer ap_timer = { - .init = ap_init_timer, - .offset = integrator_gettimeoffset, +static const char * ap_dt_board_compat[] = { + "arm,integrator-ap", + NULL, }; -MACHINE_START(INTEGRATOR, "ARM-Integrator") - /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .phys_io = 0x16000000, - .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc, - .boot_params = 0x00000100, +DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)") + .reserve = integrator_reserve, .map_io = ap_map_io, - .init_irq = ap_init_irq, - .timer = &ap_timer, - .init_machine = ap_init, + .init_early = ap_init_early, + .init_irq = ap_init_irq_of, + .handle_irq = fpga_handle_irq, + .init_time = ap_of_timer_init, + .init_machine = ap_init_of, + .restart = integrator_restart, + .dt_compat = ap_dt_board_compat, MACHINE_END |