diff options
Diffstat (limited to 'arch/arm/mach-imx/mm-imx27.c')
| -rw-r--r-- | arch/arm/mach-imx/mm-imx27.c | 44 |
1 files changed, 37 insertions, 7 deletions
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c index 374e48b7a41..7d82a5a5b16 100644 --- a/arch/arm/mach-imx/mm-imx27.c +++ b/arch/arm/mach-imx/mm-imx27.c @@ -20,11 +20,15 @@ #include <linux/mm.h> #include <linux/init.h> -#include <mach/hardware.h> -#include <mach/common.h> +#include <linux/pinctrl/machine.h> #include <asm/pgtable.h> #include <asm/mach/map.h> +#include "common.h" +#include "devices/devices-common.h" +#include "hardware.h" +#include "iomux-v1.h" + /* MX27 memory map definition */ static struct map_desc imx27_io_desc[] __initdata = { /* @@ -56,16 +60,42 @@ static struct map_desc imx27_io_desc[] __initdata = { */ void __init mx27_map_io(void) { - mxc_set_cpu_type(MXC_CPU_MX27); - mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); - iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc)); } -int imx27_register_gpios(void); +void __init imx27_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MX27); + imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR), + MX27_NUM_GPIO_PORT); +} void __init mx27_init_irq(void) { mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); - imx27_register_gpios(); +} + +static const struct resource imx27_audmux_res[] __initconst = { + DEFINE_RES_MEM(MX27_AUDMUX_BASE_ADDR, SZ_4K), +}; + +void __init imx27_soc_init(void) +{ + mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); + mxc_device_init(); + + /* i.mx27 has the i.mx21 type gpio */ + mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio", 2, MX27_GPIO3_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); + + pinctrl_provide_dummies(); + imx_add_imx_dma("imx27-dma", MX27_DMA_BASE_ADDR, + MX27_INT_DMACH0, 0); /* No ERR irq */ + /* imx27 has the imx21 type audmux */ + platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res, + ARRAY_SIZE(imx27_audmux_res)); } |